#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <time.h>

  struct  timespec start, end;
  long long int time_taken;

__device__ int is_a_match(char *password_crack)
{
  char password_number_1[] = "AA9996";
  char password_number_2[] = "AS1234";
  char password_number_3[] = "LK9091";
  char password_number_4[] = "FD1223";
  char *number_1 = password_crack;
  char *number_2 = password_crack;
  char *number_3 = password_crack;
  char *number_4 = password_crack;
  char *password_1 = password_number_1;
  char *password_2 = password_number_2;
  char *password_3 = password_number_3;
  char *password_4 = password_number_4;

  while(*number_1 == *password_1) 
  {
   if(*number_1 == '\0')
    {
    printf("***match found*** %s\n",password_number_1);
      break;
    }
    number_1++;
    password_1++;
  }
    
  while(*number_2 == *password_2)
  {
   if(*number_2 == '\0')
    {
    printf("***match found*** %s\n",password_number_2);
      break;
    }
    number_2++;
    password_2++;
  }

  while(*number_3 == *password_3) 
  {
   if(*number_3 == '\0')
    {
    printf("***match found*** %s\n",password_number_3);
      break;
    }
    number_3++;
    password_3++;
  }

  while(*number_4 == *password_4)
  {
   if(*number_4 == '\0')
    {
    printf("***match found*** %s\n",password_number_4);
      return 1;
    }
    number_4++;
    password_4++;
  }
  return 0;
}
__global__ void  kernel() 
{
  char a,b,c,d;
  char password[7];
  password[6] = '\0';
  int i = blockIdx.x+65;
  int j = threadIdx.x+65;
  char firstValue = i;
  char secondValue = j;
  password[0] = firstValue;
 password[1] = secondValue;
    for(a='0'; a<='9'; a++){
      for(b='0'; b<='9'; b++){
        for(c='0';c<='9';c++){
          for(d='0';d<='9';d++){
            password[2] = a;
            password[3] = b;
            password[4]= c;
            password[5]=d;
          if(is_a_match(password)) {
        //printf("***match found***");
          }
             else {
         //printf(" %s\n", password);          
            }
          }
        } 
      }
   }
}

int t_difference(struct timespec *start, struct timespec *end, long long int *difference) 
{
  long long int ds =  end->tv_sec - start->tv_sec;
  long long int dn =  end->tv_nsec - start->tv_nsec;

  if(dn < 0 ) 
  {
    ds--;
    dn += 1000000000;
  }
  *difference = ds * 1000000000 + dn;
  return !(*difference > 0);
}

int main() {
  clock_gettime(CLOCK_MONOTONIC, &start);
  kernel <<<26,26>>>();
  cudaDeviceSynchronize();
  clock_gettime(CLOCK_MONOTONIC, &end);
  t_difference(&start, &end, &time_taken);
  printf("Total time taken was %lldns or %0.9lfs\n", time_taken, (time_taken/1.0e9));
  return 0;
}




	.file	"tmpxft_00305a48_00000000-6_CUDA-password_crack.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10is_a_matchPc
	.type	_Z10is_a_matchPc, @function
_Z10is_a_matchPc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10is_a_matchPc, .-_Z10is_a_matchPc
	.globl	_Z12t_differenceP8timespecS0_Px
	.type	_Z12t_differenceP8timespecS0_Px, @function
_Z12t_differenceP8timespecS0_Px:
.LFB2028:
	.cfi_startproc
	endbr64
	movq	(%rsi), %rax
	movq	8(%rsi), %rcx
	subq	(%rdi), %rax
	subq	8(%rdi), %rcx
	jns	.L5
	decq	%rax
	addq	$1000000000, %rcx
.L5:
	imulq	$1000000000, %rax, %rax
	addq	%rcx, %rax
	testq	%rax, %rax
	movq	%rax, (%rdx)
	setle	%al
	movzbl	%al, %eax
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z12t_differenceP8timespecS0_Px, .-_Z12t_differenceP8timespecS0_Px
	.globl	_Z24__device_stub__Z6kernelvv
	.type	_Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z6kernelv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L7:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
	.globl	_Z6kernelv
	.type	_Z6kernelv, @function
_Z6kernelv:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z24__device_stub__Z6kernelvv
	.cfi_endproc
.LFE2055:
	.size	_Z6kernelv, .-_Z6kernelv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Total time taken was %lldns or %0.9lfs\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$1, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	leaq	start(%rip), %rbx
	movq	%rbx, %rsi
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	call	clock_gettime@PLT
	movl	$2147483661, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	addq	%rdi, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	call	_Z24__device_stub__Z6kernelvv
.L13:
	call	cudaDeviceSynchronize@PLT
	leaq	end(%rip), %rbp
	movl	$1, %edi
	movq	%rbp, %rsi
	call	clock_gettime@PLT
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	leaq	time_taken(%rip), %rdx
	call	_Z12t_differenceP8timespecS0_Px
	movq	time_taken(%rip), %rdx
	leaq	.LC1(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtsi2sdq	%rdx, %xmm0
	divsd	.LC0(%rip), %xmm0
	call	__printf_chk@PLT
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z6kernelv"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kernelv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	time_taken
	.bss
	.align 8
	.type	time_taken, @object
	.size	time_taken, 8
time_taken:
	.zero	8
	.globl	end
	.align 16
	.type	end, @object
	.size	end, 16
end:
	.zero	16
	.globl	start
	.align 16
	.type	start, @object
	.size	start, 16
start:
	.zero	16
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1104006501
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <time.h>

  struct  timespec start, end;
  long long int time_taken;

__device__ int is_a_match(char *password_crack)
{
  char password_number_1[] = "AA9996";
  char password_number_2[] = "AS1234";
  char password_number_3[] = "LK9091";
  char password_number_4[] = "FD1223";
  char *number_1 = password_crack;
  char *number_2 = password_crack;
  char *number_3 = password_crack;
  char *number_4 = password_crack;
  char *password_1 = password_number_1;
  char *password_2 = password_number_2;
  char *password_3 = password_number_3;
  char *password_4 = password_number_4;

  while(*number_1 == *password_1) 
  {
   if(*number_1 == '\0')
    {
    printf("***match found*** %s\n",password_number_1);
      break;
    }
    number_1++;
    password_1++;
  }
    
  while(*number_2 == *password_2)
  {
   if(*number_2 == '\0')
    {
    printf("***match found*** %s\n",password_number_2);
      break;
    }
    number_2++;
    password_2++;
  }

  while(*number_3 == *password_3) 
  {
   if(*number_3 == '\0')
    {
    printf("***match found*** %s\n",password_number_3);
      break;
    }
    number_3++;
    password_3++;
  }

  while(*number_4 == *password_4)
  {
   if(*number_4 == '\0')
    {
    printf("***match found*** %s\n",password_number_4);
      return 1;
    }
    number_4++;
    password_4++;
  }
  return 0;
}
__global__ void  kernel() 
{
  char a,b,c,d;
  char password[7];
  password[6] = '\0';
  int i = blockIdx.x+65;
  int j = threadIdx.x+65;
  char firstValue = i;
  char secondValue = j;
  password[0] = firstValue;
 password[1] = secondValue;
    for(a='0'; a<='9'; a++){
      for(b='0'; b<='9'; b++){
        for(c='0';c<='9';c++){
          for(d='0';d<='9';d++){
            password[2] = a;
            password[3] = b;
            password[4]= c;
            password[5]=d;
          if(is_a_match(password)) {
        //printf("***match found***");
          }
             else {
         //printf(" %s\n", password);          
            }
          }
        } 
      }
   }
}

int t_difference(struct timespec *start, struct timespec *end, long long int *difference) 
{
  long long int ds =  end->tv_sec - start->tv_sec;
  long long int dn =  end->tv_nsec - start->tv_nsec;

  if(dn < 0 ) 
  {
    ds--;
    dn += 1000000000;
  }
  *difference = ds * 1000000000 + dn;
  return !(*difference > 0);
}

int main() {
  clock_gettime(CLOCK_MONOTONIC, &start);
  kernel <<<26,26>>>();
  hipDeviceSynchronize();
  clock_gettime(CLOCK_MONOTONIC, &end);
  t_difference(&start, &end, &time_taken);
  printf("Total time taken was %lldns or %0.9lfs\n", time_taken, (time_taken/1.0e9));
  return 0;
}




	.text
	.file	"CUDA-password_crack.hip"
	.globl	_Z21__device_stub__kernelv      # -- Begin function _Z21__device_stub__kernelv
	.type	_Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv:             # @_Z21__device_stub__kernelv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z6kernelv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
	.cfi_endproc
                                        # -- End function
	.globl	_Z12t_differenceP8timespecS0_Px # -- Begin function _Z12t_differenceP8timespecS0_Px
	.type	_Z12t_differenceP8timespecS0_Px,@function
_Z12t_differenceP8timespecS0_Px:        # @_Z12t_differenceP8timespecS0_Px
	.cfi_startproc
# %bb.0:
	movq	(%rsi), %rax
	subq	(%rdi), %rax
	movq	8(%rsi), %rcx
	subq	8(%rdi), %rcx
	leaq	1000000000(%rcx), %rsi
	movq	%rcx, %rdi
	sarq	$63, %rdi
	addq	%rax, %rdi
	testq	%rcx, %rcx
	cmovnsq	%rcx, %rsi
	imulq	$1000000000, %rdi, %rcx         # imm = 0x3B9ACA00
	xorl	%eax, %eax
	addq	%rsi, %rcx
	movq	%rcx, (%rdx)
	setle	%al
	retq
.Lfunc_end1:
	.size	_Z12t_differenceP8timespecS0_Px, .Lfunc_end1-_Z12t_differenceP8timespecS0_Px
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x41cdcd6500000000              # double 1.0E+9
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$start, %esi
	movl	$1, %edi
	callq	clock_gettime
	movabsq	$4294967322, %rdi               # imm = 0x10000001A
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	callq	_Z21__device_stub__kernelv
.LBB2_2:
	callq	hipDeviceSynchronize
	movl	$end, %esi
	movl	$1, %edi
	callq	clock_gettime
	movq	end(%rip), %rax
	subq	start(%rip), %rax
	movq	end+8(%rip), %rcx
	subq	start+8(%rip), %rcx
	leaq	1000000000(%rcx), %rdx
	movq	%rcx, %rsi
	sarq	$63, %rsi
	addq	%rax, %rsi
	testq	%rcx, %rcx
	cmovnsq	%rcx, %rdx
	imulq	$1000000000, %rsi, %rsi         # imm = 0x3B9ACA00
	addq	%rdx, %rsi
	movq	%rsi, time_taken(%rip)
	cvtsi2sd	%rsi, %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelv, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	start,@object                   # @start
	.bss
	.globl	start
	.p2align	3, 0x0
start:
	.zero	16
	.size	start, 16

	.type	end,@object                     # @end
	.globl	end
	.p2align	3, 0x0
end:
	.zero	16
	.size	end, 16

	.type	time_taken,@object              # @time_taken
	.globl	time_taken
	.p2align	3, 0x0
time_taken:
	.quad	0                               # 0x0
	.size	time_taken, 8

	.type	_Z6kernelv,@object              # @_Z6kernelv
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelv
	.p2align	3, 0x0
_Z6kernelv:
	.quad	_Z21__device_stub__kernelv
	.size	_Z6kernelv, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Total time taken was %lldns or %0.9lfs\n"
	.size	.L.str, 40

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kernelv"
	.size	.L__unnamed_1, 11

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelv
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym start
	.addrsig_sym end
	.addrsig_sym _Z6kernelv
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
	v_or_b32_e32 v2, 2, v0
	v_cmp_eq_u32_e64 s0, 0, v6
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v2, v0, s0
	s_mov_b32 s0, exec_lo
	v_cmpx_ne_u64_e32 0, v[7:8]
	s_xor_b32 s10, exec_lo, s0
	s_cbranch_execz .LBB0_87
; %bb.1:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v11, 2 :: v_dual_and_b32 v6, 2, v10
	v_mov_b32_e32 v30, 0
	v_and_b32_e32 v0, -3, v10
	v_mbcnt_lo_u32_b32 v33, -1, 0
	v_mov_b32_e32 v12, 1
	s_mov_b32 s12, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_21 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
                                        ;     Child Loop BB0_37 Depth 2
                                        ;     Child Loop BB0_45 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_75 Depth 2
                                        ;     Child Loop BB0_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[4:5]
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v32, 0, v5 :: v_dual_cndmask_b32 v31, 56, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v31
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v31
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[9:10], 3, v[31:32]
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v14, v8
	v_mov_b32_e32 v13, v7
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB0_5:                                ; %.preheader31
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v10, v[13:14]
	v_mov_b32_e32 v16, s11
	v_add_co_u32 v13, vcc_lo, v13, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v15, 0xffff, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], s4, v[15:16]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v9
	v_or_b32_e32 v3, v16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v2, v15, v2
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow232
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_7:                                ; %Flow234
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB0_8:                                ; %Flow236
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v9, v7
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	s_clause 0x5
	flat_load_u8 v2, v[7:8]
	flat_load_u8 v3, v[7:8] offset:1
	flat_load_u8 v9, v[7:8] offset:2
	flat_load_u8 v10, v[7:8] offset:3
	flat_load_u8 v13, v[7:8] offset:5
	flat_load_u8 v14, v[7:8] offset:4
	v_mov_b32_e32 v16, v30
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v3, 8, v3
	s_clause 0x1
	flat_load_u8 v15, v[7:8] offset:7
	flat_load_d16_hi_u8 v16, v[7:8] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_or_b32_e32 v2, v3, v2
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v3, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v2, v2, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v3, 0, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v2, v2, 0, 0
	v_or3_b32 v2, v2, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v15
	v_add_nc_u32_e32 v15, -8, v31
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_or3_b32 v3, v3, v16, v9
	v_add_co_u32 v9, vcc_lo, v7, 8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
.LBB0_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v15
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_16
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v15
	s_cbranch_execz .LBB0_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_13:                               ; %.preheader29
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v16, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v15
	flat_load_u8 v16, v[16:17]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v17, s11 :: v_dual_and_b32 v16, 0xffff, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], s0, v[16:17]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v14, v17, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v16, v13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %Flow227
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_15:                               ; %Flow229
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr15
.LBB0_16:                               ; %Flow231
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v17, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v13, v[9:10]
	flat_load_u8 v14, v[9:10] offset:1
	flat_load_u8 v16, v[9:10] offset:2
	flat_load_u8 v17, v[9:10] offset:3
	flat_load_u8 v18, v[9:10] offset:5
	flat_load_u8 v19, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v20, v30 :: v_dual_and_b32 v13, 0xffff, v13
	s_clause 0x1
	flat_load_u8 v21, v[9:10] offset:7
	flat_load_d16_hi_u8 v20, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v14, 8, v14
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v16, 16, v16
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v17, 24, v17
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v13, v14, v13
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v14, 8, v18
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v13, v13, v16, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v14, 0, v19, v14
	v_add_nc_u32_e32 v17, -8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v13, v13, 0, 0
	v_or3_b32 v13, v13, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v16, 24, v21
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v14, v14, v20, v16
.LBB0_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v17
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_24
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v17
	s_cbranch_execz .LBB0_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_21:                               ; %.preheader27
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v18, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v17
	flat_load_u8 v18, v[18:19]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v19, s11 :: v_dual_and_b32 v18, 0xffff, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], s0, v[18:19]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v16, v19, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v18, v15
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_21
; %bb.22:                               ; %Flow222
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_23:                               ; %Flow224
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr17
.LBB0_24:                               ; %Flow226
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v15, v[9:10]
	flat_load_u8 v16, v[9:10] offset:1
	flat_load_u8 v18, v[9:10] offset:2
	flat_load_u8 v19, v[9:10] offset:3
	flat_load_u8 v20, v[9:10] offset:5
	flat_load_u8 v21, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v22, v30 :: v_dual_and_b32 v15, 0xffff, v15
	s_clause 0x1
	flat_load_u8 v23, v[9:10] offset:7
	flat_load_d16_hi_u8 v22, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v16, 8, v16
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v18
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v15, v16, v15
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v16, 8, v20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v15, v15, v18, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v16, 0, v21, v16
	v_add_nc_u32_e32 v19, -8, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v15, v15, 0, 0
	v_or3_b32 v15, v15, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v23
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v16, v16, v22, v18
.LBB0_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_32
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB0_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_29:                               ; %.preheader25
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v20, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v19
	flat_load_u8 v20, v[20:21]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v21, s11 :: v_dual_and_b32 v20, 0xffff, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v18, v21, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v20, v17
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_29
; %bb.30:                               ; %Flow217
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_31:                               ; %Flow219
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr19
.LBB0_32:                               ; %Flow221
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v21, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v17, v[9:10]
	flat_load_u8 v18, v[9:10] offset:1
	flat_load_u8 v20, v[9:10] offset:2
	flat_load_u8 v21, v[9:10] offset:3
	flat_load_u8 v22, v[9:10] offset:5
	flat_load_u8 v23, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v24, v30 :: v_dual_and_b32 v17, 0xffff, v17
	s_clause 0x1
	flat_load_u8 v25, v[9:10] offset:7
	flat_load_d16_hi_u8 v24, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v18, 8, v18
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v20, 16, v20
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v21, 24, v21
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v17, v18, v17
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v18, 8, v22
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v17, v17, v20, v21
	s_waitcnt vmcnt(2)
	v_or3_b32 v18, 0, v23, v18
	v_add_nc_u32_e32 v21, -8, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v17, v17, 0, 0
	v_or3_b32 v17, v17, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v20, 24, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v18, v18, v24, v20
.LBB0_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v21
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_40
; %bb.35:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v21
	s_cbranch_execz .LBB0_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_37:                               ; %.preheader23
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v22, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v21
	flat_load_u8 v22, v[22:23]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v23, s11 :: v_dual_and_b32 v22, 0xffff, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], s0, v[22:23]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v22, v19
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_37
; %bb.38:                               ; %Flow212
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_39:                               ; %Flow214
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr21
.LBB0_40:                               ; %Flow216
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v23, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v19, v[9:10]
	flat_load_u8 v20, v[9:10] offset:1
	flat_load_u8 v22, v[9:10] offset:2
	flat_load_u8 v23, v[9:10] offset:3
	flat_load_u8 v24, v[9:10] offset:5
	flat_load_u8 v25, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v26, v30 :: v_dual_and_b32 v19, 0xffff, v19
	s_clause 0x1
	flat_load_u8 v27, v[9:10] offset:7
	flat_load_d16_hi_u8 v26, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v20, 8, v20
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v22, 16, v22
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v23, 24, v23
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v19, v20, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v20, 8, v24
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v19, v19, v22, v23
	s_waitcnt vmcnt(2)
	v_or3_b32 v20, 0, v25, v20
	v_add_nc_u32_e32 v23, -8, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v19, v19, 0, 0
	v_or3_b32 v19, v19, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v22, 24, v27
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v20, v20, v26, v22
.LBB0_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v23
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_48
; %bb.43:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v23
	s_cbranch_execz .LBB0_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s13, 0
	s_mov_b64 s[4:5], 0
.LBB0_45:                               ; %.preheader21
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v24, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v25, vcc_lo, s5, v10, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v23
	flat_load_u8 v24, v[24:25]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v25, s11 :: v_dual_and_b32 v24, 0xffff, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[24:25], s0, v[24:25]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s13, vcc_lo, s13
	v_or_b32_e32 v22, v25, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v24, v21
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_45
; %bb.46:                               ; %Flow207
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_47:                               ; %Flow209
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr23
.LBB0_48:                               ; %Flow211
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v25, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v21, v[9:10]
	flat_load_u8 v22, v[9:10] offset:1
	flat_load_u8 v24, v[9:10] offset:2
	flat_load_u8 v25, v[9:10] offset:3
	flat_load_u8 v26, v[9:10] offset:5
	flat_load_u8 v27, v[9:10] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v28, v30 :: v_dual_and_b32 v21, 0xffff, v21
	s_clause 0x1
	flat_load_u8 v29, v[9:10] offset:7
	flat_load_d16_hi_u8 v28, v[9:10] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v22, 8, v22
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v24, 16, v24
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v25, 24, v25
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_or_b32_e32 v21, v22, v21
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v22, 8, v26
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v21, v21, v24, v25
	s_waitcnt vmcnt(2)
	v_or3_b32 v22, 0, v27, v22
	v_add_nc_u32_e32 v25, -8, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v21, v21, 0, 0
	v_or3_b32 v21, v21, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v24, 24, v29
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v22, v22, v28, v24
.LBB0_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v25
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_56
; %bb.51:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v25
	s_cbranch_execz .LBB0_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB0_53:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v26, v[9:10]
	v_mov_b32_e32 v27, s11
	v_add_nc_u32_e32 v25, -1, v25
	v_add_co_u32 v9, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v26, 0xffff, v26
	v_lshlrev_b64 v[26:27], s0, v[26:27]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v24, v27, v24
	v_or_b32_e32 v23, v26, v23
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_53
; %bb.54:                               ; %Flow202
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_55:                               ; %Flow204
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_56:                               ; %Flow206
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x5
	flat_load_u8 v23, v[9:10]
	flat_load_u8 v24, v[9:10] offset:1
	flat_load_u8 v25, v[9:10] offset:2
	flat_load_u8 v26, v[9:10] offset:3
	flat_load_u8 v27, v[9:10] offset:5
	flat_load_u8 v28, v[9:10] offset:4
	v_mov_b32_e32 v29, v30
	s_clause 0x1
	flat_load_u8 v34, v[9:10] offset:7
	flat_load_d16_hi_u8 v29, v[9:10] offset:6
	s_waitcnt vmcnt(7) lgkmcnt(0)
	v_and_b32_e32 v9, 0xffff, v23
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v10, 8, v24
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v23, 16, v25
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v24, 8, v27
	v_or_b32_e32 v9, v10, v9
	v_lshlrev_b32_e32 v10, 24, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v23, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v10, 0, v28, v24
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v23, 24, v34
	v_or3_b32 v9, v9, 0, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v24, v10, v29, v23
	v_or3_b32 v23, v9, 0, 0
.LBB0_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v29, v33
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v29
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_64
; %bb.59:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[27:28], v30, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[9:10], v30, s[2:3] offset:40
	global_load_b64 v[25:26], v30, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v10, v10, v28
	v_and_b32_e32 v9, v9, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v10, 24
	v_mul_hi_u32 v34, v9, 24
	v_mul_lo_u32 v9, v9, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v34, v10
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v25, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v26, v10, vcc_lo
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[27:28]
	s_cbranch_execz .LBB0_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s5, 0
.LBB0_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v30, s[2:3] offset:40
	global_load_b64 v[34:35], v30, s[2:3]
	v_dual_mov_b32 v28, v10 :: v_dual_mov_b32 v27, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[9:10], null, v25, 24, v[34:35]
	v_and_b32_e32 v34, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v34, 24, v[10:11]
	v_mov_b32_e32 v10, v25
	global_load_b64 v[25:26], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v30, v[25:28], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[27:28]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_61
; %bb.62:                               ; %Flow199
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_63:                               ; %Flow201
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[34:35], v30, s[2:3] offset:40
	global_load_b128 v[25:28], v30, s[2:3]
	v_readfirstlane_b32 s4, v9
	v_readfirstlane_b32 s5, v10
	s_mov_b32 s15, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v34
	v_readfirstlane_b32 s7, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s13, s6, 24
	s_mul_i32 s14, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s17, s13, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v34, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v35, vcc_lo, s17, v26, vcc_lo
	v_dual_mov_b32 v9, s15 :: v_dual_mov_b32 v10, v30
	global_store_b128 v[34:35], v[9:12], off offset:8
.LBB0_66:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_lt_u64_e32 vcc_lo, 56, v[4:5]
	v_or_b32_e32 v9, 0, v1
	v_or_b32_e32 v10, v0, v6
	v_lshl_add_u32 v34, v31, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v10, v0
	v_lshlrev_b64 v[9:10], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v27, vcc_lo, v27, s6
	v_and_b32_e32 v34, 0x1e0, v34
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v27, v9
	v_and_or_b32 v0, 0xffffff1f, v0, v34
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, v28, v10, vcc_lo
	s_clause 0x3
	global_store_b128 v[9:10], v[0:3], off
	global_store_b128 v[9:10], v[13:16], off offset:16
	global_store_b128 v[9:10], v[17:20], off offset:32
	global_store_b128 v[9:10], v[21:24], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_74
; %bb.67:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v30, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v30, s[2:3] offset:40
	v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v0
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[4:5]
	s_mul_i32 s7, s17, 24
	s_mul_hi_u32 s15, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s15, s15, s7
	v_add_co_u32 v13, vcc_lo, v25, s16
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v26, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v30, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[17:18]
	s_cbranch_execz .LBB0_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s15, 0
.LBB0_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[13:14], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v30, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_69
.LBB0_70:                               ; %Flow197
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[0:1], v30, s[2:3] offset:16
	s_mov_b32 s15, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s15, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s15, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s15
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[29:30], off offset:8
.LBB0_72:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v29, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[29:30], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_74:                               ; %Flow198
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s13, s13, s1
	v_add_co_u32 v0, vcc_lo, v25, s14
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_75:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_75 Depth=2
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_77:                               ;   in Loop: Header=BB0_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_75 Depth=2
	s_mov_b32 s1, -1
.LBB0_80:                               ; %Flow192
                                        ;   in Loop: Header=BB0_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_75
; %bb.81:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[0:3], v[9:10], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_85
; %bb.82:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[2:3], v30, s[2:3] offset:40
	global_load_b64 v[9:10], v30, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v30, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v17, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v17, s4
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v18 :: v_dual_cndmask_b32 v13, v13, v17
	v_and_b32_e32 v3, v14, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v13, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v17, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v17, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v15, v2
	v_mov_b32_e32 v15, v9
	v_add_co_ci_u32_e32 v3, vcc_lo, v16, v3, vcc_lo
	v_mov_b32_e32 v16, v10
	global_store_b64 v[2:3], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[2:3], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v30, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[15:16]
	v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v15, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_84
.LBB0_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v4, vcc_lo, v4, v31
	v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v32, vcc_lo
	v_add_co_u32 v7, s0, v7, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s0, v8, v32, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_2
; %bb.86:                               ; %Flow237
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr10
.LBB0_87:                               ; %Flow253
	s_and_not1_saveexec_b32 s1, s10
	s_cbranch_execz .LBB0_116
; %bb.88:
	s_load_b64 s[2:3], s[8:9], 0x50
	s_waitcnt vmcnt(0)
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_94
; %bb.89:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[5:6], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[7:8], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v3, 24
	v_mul_lo_u32 v4, v4, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v9, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[5:6]
	s_cbranch_execz .LBB0_93
; %bb.90:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s6, 0
.LBB0_91:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[3:4], v0, s[2:3] offset:40
	global_load_b64 v[11:12], v0, s[2:3]
	v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v6, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v4, v4, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v3, 24, v[11:12]
	v_mov_b32_e32 v3, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[3:4]
	global_load_b64 v[3:4], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[5:6]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_91
; %bb.92:                               ; %Flow249
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_93:                               ; %Flow251
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_94:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s11, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s8, s7, 24
	s_mul_hi_u32 s9, s6, 24
	s_mul_i32 s10, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_96
; %bb.95:
	s_add_i32 s13, s9, s8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v12, v3
	v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
	global_store_b128 v[8:9], v[11:14], off offset:8
.LBB0_96:
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_104
; %bb.97:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_100
; %bb.98:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s11, 0
.LBB0_99:                               ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_99
.LBB0_100:                              ; %Flow247
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s11, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_102
; %bb.101:
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_102:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_104
; %bb.103:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_104:                              ; %Flow248
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s9, s9, s8
	v_add_co_u32 v0, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_105:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_105 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_107:                              ;   in Loop: Header=BB0_105 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB0_110
.LBB0_109:                              ;   in Loop: Header=BB0_105 Depth=1
	s_mov_b32 s6, -1
.LBB0_110:                              ; %Flow242
                                        ;   in Loop: Header=BB0_105 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB0_105
; %bb.111:
	global_load_b128 v[0:3], v[6:7], off
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_115
; %bb.112:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_115
; %bb.113:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_114:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_114
.LBB0_115:                              ; %__ockl_hostcall_preview.exit
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_116:                              ; %Flow254
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	__ockl_printf_append_string_n, .Lfunc_end0-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 5708
; NumSgprs: 34
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z6kernelv              ; -- Begin function _Z6kernelv
	.globl	_Z6kernelv
	.p2align	8
	.type	_Z6kernelv,@function
_Z6kernelv:                             ; @_Z6kernelv
; %bb.0:
	v_add_nc_u16 v1, s15, 0x41
	v_mov_b32_e32 v38, 0
	v_lshlrev_b16 v0, 8, v0
	s_mov_b64 s[18:19], s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	v_and_b32_e32 v1, 0xff, v1
	v_cmp_ne_u32_e64 s28, 4, -1
	v_cmp_ne_u32_e64 s29, 12, -1
	v_cmp_ne_u32_e64 s33, 20, -1
	v_cmp_ne_u32_e64 s34, 28, -1
	v_or_b32_e32 v0, v0, v1
	v_add_nc_u32_e64 v43, 4, -1
	v_add_nc_u32_e64 v44, 12, -1
	v_add_nc_u32_e64 v45, 20, -1
	v_add_nc_u32_e64 v46, 28, -1
	v_dual_mov_b32 v50, 48 :: v_dual_mov_b32 v47, 0x3639
	v_dual_mov_b32 v48, 0x39394141 :: v_dual_mov_b32 v41, 2
	v_dual_mov_b32 v49, 0x3433 :: v_dual_mov_b32 v42, 1
	v_dual_mov_b32 v51, 0x32315341 :: v_dual_mov_b32 v36, 33
	v_mov_b32_e32 v52, 0x3139
	v_mov_b32_e32 v53, 0x30394b4c
	v_mov_b32_e32 v54, 0x3332
	v_mov_b32_e32 v55, 0x32314446
	v_mbcnt_lo_u32_b32 v56, -1, 0
	s_cmp_lg_u64 s[0:1], 0
	v_add_nc_u16 v0, v0, 0x4100
	s_mov_b64 s[24:25], src_private_base
	s_mov_b32 s20, 0
	s_cselect_b32 s24, 22, 0
	s_mov_b32 s32, 48
	s_clause 0x1
	scratch_store_b8 off, v38, off offset:42
	scratch_store_b16 off, v0, off offset:36
.LBB1_1:                                ; %.preheader31
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_2 Depth 2
                                        ;       Child Loop BB1_3 Depth 3
                                        ;         Child Loop BB1_4 Depth 4
                                        ;           Child Loop BB1_6 Depth 5
                                        ;           Child Loop BB1_13 Depth 5
                                        ;           Child Loop BB1_21 Depth 5
                                        ;           Child Loop BB1_27 Depth 5
                                        ;           Child Loop BB1_36 Depth 5
                                        ;           Child Loop BB1_38 Depth 5
                                        ;           Child Loop BB1_41 Depth 5
                                        ;             Child Loop BB1_44 Depth 6
                                        ;             Child Loop BB1_52 Depth 6
                                        ;             Child Loop BB1_60 Depth 6
                                        ;             Child Loop BB1_68 Depth 6
                                        ;             Child Loop BB1_76 Depth 6
                                        ;             Child Loop BB1_84 Depth 6
                                        ;             Child Loop BB1_92 Depth 6
                                        ;             Child Loop BB1_100 Depth 6
                                        ;             Child Loop BB1_108 Depth 6
                                        ;             Child Loop BB1_114 Depth 6
                                        ;             Child Loop BB1_123 Depth 6
                                        ;           Child Loop BB1_131 Depth 5
                                        ;           Child Loop BB1_139 Depth 5
                                        ;           Child Loop BB1_145 Depth 5
                                        ;           Child Loop BB1_154 Depth 5
                                        ;           Child Loop BB1_158 Depth 5
                                        ;           Child Loop BB1_165 Depth 5
                                        ;           Child Loop BB1_173 Depth 5
                                        ;           Child Loop BB1_179 Depth 5
                                        ;           Child Loop BB1_188 Depth 5
                                        ;           Child Loop BB1_190 Depth 5
                                        ;           Child Loop BB1_193 Depth 5
                                        ;             Child Loop BB1_196 Depth 6
                                        ;             Child Loop BB1_204 Depth 6
                                        ;             Child Loop BB1_212 Depth 6
                                        ;             Child Loop BB1_220 Depth 6
                                        ;             Child Loop BB1_228 Depth 6
                                        ;             Child Loop BB1_236 Depth 6
                                        ;             Child Loop BB1_244 Depth 6
                                        ;             Child Loop BB1_252 Depth 6
                                        ;             Child Loop BB1_260 Depth 6
                                        ;             Child Loop BB1_266 Depth 6
                                        ;             Child Loop BB1_275 Depth 6
                                        ;           Child Loop BB1_283 Depth 5
                                        ;           Child Loop BB1_291 Depth 5
                                        ;           Child Loop BB1_297 Depth 5
                                        ;           Child Loop BB1_306 Depth 5
                                        ;           Child Loop BB1_310 Depth 5
                                        ;           Child Loop BB1_317 Depth 5
                                        ;           Child Loop BB1_325 Depth 5
                                        ;           Child Loop BB1_331 Depth 5
                                        ;           Child Loop BB1_340 Depth 5
                                        ;           Child Loop BB1_342 Depth 5
                                        ;           Child Loop BB1_345 Depth 5
                                        ;             Child Loop BB1_348 Depth 6
                                        ;             Child Loop BB1_356 Depth 6
                                        ;             Child Loop BB1_364 Depth 6
                                        ;             Child Loop BB1_372 Depth 6
                                        ;             Child Loop BB1_380 Depth 6
                                        ;             Child Loop BB1_388 Depth 6
                                        ;             Child Loop BB1_396 Depth 6
                                        ;             Child Loop BB1_404 Depth 6
                                        ;             Child Loop BB1_412 Depth 6
                                        ;             Child Loop BB1_418 Depth 6
                                        ;             Child Loop BB1_427 Depth 6
                                        ;           Child Loop BB1_435 Depth 5
                                        ;           Child Loop BB1_443 Depth 5
                                        ;           Child Loop BB1_449 Depth 5
                                        ;           Child Loop BB1_458 Depth 5
                                        ;           Child Loop BB1_462 Depth 5
                                        ;           Child Loop BB1_469 Depth 5
                                        ;           Child Loop BB1_477 Depth 5
                                        ;           Child Loop BB1_483 Depth 5
                                        ;           Child Loop BB1_492 Depth 5
                                        ;           Child Loop BB1_494 Depth 5
                                        ;           Child Loop BB1_497 Depth 5
                                        ;             Child Loop BB1_500 Depth 6
                                        ;             Child Loop BB1_508 Depth 6
                                        ;             Child Loop BB1_516 Depth 6
                                        ;             Child Loop BB1_524 Depth 6
                                        ;             Child Loop BB1_532 Depth 6
                                        ;             Child Loop BB1_540 Depth 6
                                        ;             Child Loop BB1_548 Depth 6
                                        ;             Child Loop BB1_556 Depth 6
                                        ;             Child Loop BB1_564 Depth 6
                                        ;             Child Loop BB1_570 Depth 6
                                        ;             Child Loop BB1_579 Depth 6
                                        ;           Child Loop BB1_587 Depth 5
                                        ;           Child Loop BB1_595 Depth 5
                                        ;           Child Loop BB1_601 Depth 5
                                        ;           Child Loop BB1_610 Depth 5
	v_mov_b32_e32 v57, 48
.LBB1_2:                                ; %.preheader30
                                        ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_3 Depth 3
                                        ;         Child Loop BB1_4 Depth 4
                                        ;           Child Loop BB1_6 Depth 5
                                        ;           Child Loop BB1_13 Depth 5
                                        ;           Child Loop BB1_21 Depth 5
                                        ;           Child Loop BB1_27 Depth 5
                                        ;           Child Loop BB1_36 Depth 5
                                        ;           Child Loop BB1_38 Depth 5
                                        ;           Child Loop BB1_41 Depth 5
                                        ;             Child Loop BB1_44 Depth 6
                                        ;             Child Loop BB1_52 Depth 6
                                        ;             Child Loop BB1_60 Depth 6
                                        ;             Child Loop BB1_68 Depth 6
                                        ;             Child Loop BB1_76 Depth 6
                                        ;             Child Loop BB1_84 Depth 6
                                        ;             Child Loop BB1_92 Depth 6
                                        ;             Child Loop BB1_100 Depth 6
                                        ;             Child Loop BB1_108 Depth 6
                                        ;             Child Loop BB1_114 Depth 6
                                        ;             Child Loop BB1_123 Depth 6
                                        ;           Child Loop BB1_131 Depth 5
                                        ;           Child Loop BB1_139 Depth 5
                                        ;           Child Loop BB1_145 Depth 5
                                        ;           Child Loop BB1_154 Depth 5
                                        ;           Child Loop BB1_158 Depth 5
                                        ;           Child Loop BB1_165 Depth 5
                                        ;           Child Loop BB1_173 Depth 5
                                        ;           Child Loop BB1_179 Depth 5
                                        ;           Child Loop BB1_188 Depth 5
                                        ;           Child Loop BB1_190 Depth 5
                                        ;           Child Loop BB1_193 Depth 5
                                        ;             Child Loop BB1_196 Depth 6
                                        ;             Child Loop BB1_204 Depth 6
                                        ;             Child Loop BB1_212 Depth 6
                                        ;             Child Loop BB1_220 Depth 6
                                        ;             Child Loop BB1_228 Depth 6
                                        ;             Child Loop BB1_236 Depth 6
                                        ;             Child Loop BB1_244 Depth 6
                                        ;             Child Loop BB1_252 Depth 6
                                        ;             Child Loop BB1_260 Depth 6
                                        ;             Child Loop BB1_266 Depth 6
                                        ;             Child Loop BB1_275 Depth 6
                                        ;           Child Loop BB1_283 Depth 5
                                        ;           Child Loop BB1_291 Depth 5
                                        ;           Child Loop BB1_297 Depth 5
                                        ;           Child Loop BB1_306 Depth 5
                                        ;           Child Loop BB1_310 Depth 5
                                        ;           Child Loop BB1_317 Depth 5
                                        ;           Child Loop BB1_325 Depth 5
                                        ;           Child Loop BB1_331 Depth 5
                                        ;           Child Loop BB1_340 Depth 5
                                        ;           Child Loop BB1_342 Depth 5
                                        ;           Child Loop BB1_345 Depth 5
                                        ;             Child Loop BB1_348 Depth 6
                                        ;             Child Loop BB1_356 Depth 6
                                        ;             Child Loop BB1_364 Depth 6
                                        ;             Child Loop BB1_372 Depth 6
                                        ;             Child Loop BB1_380 Depth 6
                                        ;             Child Loop BB1_388 Depth 6
                                        ;             Child Loop BB1_396 Depth 6
                                        ;             Child Loop BB1_404 Depth 6
                                        ;             Child Loop BB1_412 Depth 6
                                        ;             Child Loop BB1_418 Depth 6
                                        ;             Child Loop BB1_427 Depth 6
                                        ;           Child Loop BB1_435 Depth 5
                                        ;           Child Loop BB1_443 Depth 5
                                        ;           Child Loop BB1_449 Depth 5
                                        ;           Child Loop BB1_458 Depth 5
                                        ;           Child Loop BB1_462 Depth 5
                                        ;           Child Loop BB1_469 Depth 5
                                        ;           Child Loop BB1_477 Depth 5
                                        ;           Child Loop BB1_483 Depth 5
                                        ;           Child Loop BB1_492 Depth 5
                                        ;           Child Loop BB1_494 Depth 5
                                        ;           Child Loop BB1_497 Depth 5
                                        ;             Child Loop BB1_500 Depth 6
                                        ;             Child Loop BB1_508 Depth 6
                                        ;             Child Loop BB1_516 Depth 6
                                        ;             Child Loop BB1_524 Depth 6
                                        ;             Child Loop BB1_532 Depth 6
                                        ;             Child Loop BB1_540 Depth 6
                                        ;             Child Loop BB1_548 Depth 6
                                        ;             Child Loop BB1_556 Depth 6
                                        ;             Child Loop BB1_564 Depth 6
                                        ;             Child Loop BB1_570 Depth 6
                                        ;             Child Loop BB1_579 Depth 6
                                        ;           Child Loop BB1_587 Depth 5
                                        ;           Child Loop BB1_595 Depth 5
                                        ;           Child Loop BB1_601 Depth 5
                                        ;           Child Loop BB1_610 Depth 5
	v_mov_b32_e32 v58, 48
.LBB1_3:                                ; %.preheader
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_4 Depth 4
                                        ;           Child Loop BB1_6 Depth 5
                                        ;           Child Loop BB1_13 Depth 5
                                        ;           Child Loop BB1_21 Depth 5
                                        ;           Child Loop BB1_27 Depth 5
                                        ;           Child Loop BB1_36 Depth 5
                                        ;           Child Loop BB1_38 Depth 5
                                        ;           Child Loop BB1_41 Depth 5
                                        ;             Child Loop BB1_44 Depth 6
                                        ;             Child Loop BB1_52 Depth 6
                                        ;             Child Loop BB1_60 Depth 6
                                        ;             Child Loop BB1_68 Depth 6
                                        ;             Child Loop BB1_76 Depth 6
                                        ;             Child Loop BB1_84 Depth 6
                                        ;             Child Loop BB1_92 Depth 6
                                        ;             Child Loop BB1_100 Depth 6
                                        ;             Child Loop BB1_108 Depth 6
                                        ;             Child Loop BB1_114 Depth 6
                                        ;             Child Loop BB1_123 Depth 6
                                        ;           Child Loop BB1_131 Depth 5
                                        ;           Child Loop BB1_139 Depth 5
                                        ;           Child Loop BB1_145 Depth 5
                                        ;           Child Loop BB1_154 Depth 5
                                        ;           Child Loop BB1_158 Depth 5
                                        ;           Child Loop BB1_165 Depth 5
                                        ;           Child Loop BB1_173 Depth 5
                                        ;           Child Loop BB1_179 Depth 5
                                        ;           Child Loop BB1_188 Depth 5
                                        ;           Child Loop BB1_190 Depth 5
                                        ;           Child Loop BB1_193 Depth 5
                                        ;             Child Loop BB1_196 Depth 6
                                        ;             Child Loop BB1_204 Depth 6
                                        ;             Child Loop BB1_212 Depth 6
                                        ;             Child Loop BB1_220 Depth 6
                                        ;             Child Loop BB1_228 Depth 6
                                        ;             Child Loop BB1_236 Depth 6
                                        ;             Child Loop BB1_244 Depth 6
                                        ;             Child Loop BB1_252 Depth 6
                                        ;             Child Loop BB1_260 Depth 6
                                        ;             Child Loop BB1_266 Depth 6
                                        ;             Child Loop BB1_275 Depth 6
                                        ;           Child Loop BB1_283 Depth 5
                                        ;           Child Loop BB1_291 Depth 5
                                        ;           Child Loop BB1_297 Depth 5
                                        ;           Child Loop BB1_306 Depth 5
                                        ;           Child Loop BB1_310 Depth 5
                                        ;           Child Loop BB1_317 Depth 5
                                        ;           Child Loop BB1_325 Depth 5
                                        ;           Child Loop BB1_331 Depth 5
                                        ;           Child Loop BB1_340 Depth 5
                                        ;           Child Loop BB1_342 Depth 5
                                        ;           Child Loop BB1_345 Depth 5
                                        ;             Child Loop BB1_348 Depth 6
                                        ;             Child Loop BB1_356 Depth 6
                                        ;             Child Loop BB1_364 Depth 6
                                        ;             Child Loop BB1_372 Depth 6
                                        ;             Child Loop BB1_380 Depth 6
                                        ;             Child Loop BB1_388 Depth 6
                                        ;             Child Loop BB1_396 Depth 6
                                        ;             Child Loop BB1_404 Depth 6
                                        ;             Child Loop BB1_412 Depth 6
                                        ;             Child Loop BB1_418 Depth 6
                                        ;             Child Loop BB1_427 Depth 6
                                        ;           Child Loop BB1_435 Depth 5
                                        ;           Child Loop BB1_443 Depth 5
                                        ;           Child Loop BB1_449 Depth 5
                                        ;           Child Loop BB1_458 Depth 5
                                        ;           Child Loop BB1_462 Depth 5
                                        ;           Child Loop BB1_469 Depth 5
                                        ;           Child Loop BB1_477 Depth 5
                                        ;           Child Loop BB1_483 Depth 5
                                        ;           Child Loop BB1_492 Depth 5
                                        ;           Child Loop BB1_494 Depth 5
                                        ;           Child Loop BB1_497 Depth 5
                                        ;             Child Loop BB1_500 Depth 6
                                        ;             Child Loop BB1_508 Depth 6
                                        ;             Child Loop BB1_516 Depth 6
                                        ;             Child Loop BB1_524 Depth 6
                                        ;             Child Loop BB1_532 Depth 6
                                        ;             Child Loop BB1_540 Depth 6
                                        ;             Child Loop BB1_548 Depth 6
                                        ;             Child Loop BB1_556 Depth 6
                                        ;             Child Loop BB1_564 Depth 6
                                        ;             Child Loop BB1_570 Depth 6
                                        ;             Child Loop BB1_579 Depth 6
                                        ;           Child Loop BB1_587 Depth 5
                                        ;           Child Loop BB1_595 Depth 5
                                        ;           Child Loop BB1_601 Depth 5
                                        ;           Child Loop BB1_610 Depth 5
	v_mov_b32_e32 v59, 48
.LBB1_4:                                ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB1_6 Depth 5
                                        ;           Child Loop BB1_13 Depth 5
                                        ;           Child Loop BB1_21 Depth 5
                                        ;           Child Loop BB1_27 Depth 5
                                        ;           Child Loop BB1_36 Depth 5
                                        ;           Child Loop BB1_38 Depth 5
                                        ;           Child Loop BB1_41 Depth 5
                                        ;             Child Loop BB1_44 Depth 6
                                        ;             Child Loop BB1_52 Depth 6
                                        ;             Child Loop BB1_60 Depth 6
                                        ;             Child Loop BB1_68 Depth 6
                                        ;             Child Loop BB1_76 Depth 6
                                        ;             Child Loop BB1_84 Depth 6
                                        ;             Child Loop BB1_92 Depth 6
                                        ;             Child Loop BB1_100 Depth 6
                                        ;             Child Loop BB1_108 Depth 6
                                        ;             Child Loop BB1_114 Depth 6
                                        ;             Child Loop BB1_123 Depth 6
                                        ;           Child Loop BB1_131 Depth 5
                                        ;           Child Loop BB1_139 Depth 5
                                        ;           Child Loop BB1_145 Depth 5
                                        ;           Child Loop BB1_154 Depth 5
                                        ;           Child Loop BB1_158 Depth 5
                                        ;           Child Loop BB1_165 Depth 5
                                        ;           Child Loop BB1_173 Depth 5
                                        ;           Child Loop BB1_179 Depth 5
                                        ;           Child Loop BB1_188 Depth 5
                                        ;           Child Loop BB1_190 Depth 5
                                        ;           Child Loop BB1_193 Depth 5
                                        ;             Child Loop BB1_196 Depth 6
                                        ;             Child Loop BB1_204 Depth 6
                                        ;             Child Loop BB1_212 Depth 6
                                        ;             Child Loop BB1_220 Depth 6
                                        ;             Child Loop BB1_228 Depth 6
                                        ;             Child Loop BB1_236 Depth 6
                                        ;             Child Loop BB1_244 Depth 6
                                        ;             Child Loop BB1_252 Depth 6
                                        ;             Child Loop BB1_260 Depth 6
                                        ;             Child Loop BB1_266 Depth 6
                                        ;             Child Loop BB1_275 Depth 6
                                        ;           Child Loop BB1_283 Depth 5
                                        ;           Child Loop BB1_291 Depth 5
                                        ;           Child Loop BB1_297 Depth 5
                                        ;           Child Loop BB1_306 Depth 5
                                        ;           Child Loop BB1_310 Depth 5
                                        ;           Child Loop BB1_317 Depth 5
                                        ;           Child Loop BB1_325 Depth 5
                                        ;           Child Loop BB1_331 Depth 5
                                        ;           Child Loop BB1_340 Depth 5
                                        ;           Child Loop BB1_342 Depth 5
                                        ;           Child Loop BB1_345 Depth 5
                                        ;             Child Loop BB1_348 Depth 6
                                        ;             Child Loop BB1_356 Depth 6
                                        ;             Child Loop BB1_364 Depth 6
                                        ;             Child Loop BB1_372 Depth 6
                                        ;             Child Loop BB1_380 Depth 6
                                        ;             Child Loop BB1_388 Depth 6
                                        ;             Child Loop BB1_396 Depth 6
                                        ;             Child Loop BB1_404 Depth 6
                                        ;             Child Loop BB1_412 Depth 6
                                        ;             Child Loop BB1_418 Depth 6
                                        ;             Child Loop BB1_427 Depth 6
                                        ;           Child Loop BB1_435 Depth 5
                                        ;           Child Loop BB1_443 Depth 5
                                        ;           Child Loop BB1_449 Depth 5
                                        ;           Child Loop BB1_458 Depth 5
                                        ;           Child Loop BB1_462 Depth 5
                                        ;           Child Loop BB1_469 Depth 5
                                        ;           Child Loop BB1_477 Depth 5
                                        ;           Child Loop BB1_483 Depth 5
                                        ;           Child Loop BB1_492 Depth 5
                                        ;           Child Loop BB1_494 Depth 5
                                        ;           Child Loop BB1_497 Depth 5
                                        ;             Child Loop BB1_500 Depth 6
                                        ;             Child Loop BB1_508 Depth 6
                                        ;             Child Loop BB1_516 Depth 6
                                        ;             Child Loop BB1_524 Depth 6
                                        ;             Child Loop BB1_532 Depth 6
                                        ;             Child Loop BB1_540 Depth 6
                                        ;             Child Loop BB1_548 Depth 6
                                        ;             Child Loop BB1_556 Depth 6
                                        ;             Child Loop BB1_564 Depth 6
                                        ;             Child Loop BB1_570 Depth 6
                                        ;             Child Loop BB1_579 Depth 6
                                        ;           Child Loop BB1_587 Depth 5
                                        ;           Child Loop BB1_595 Depth 5
                                        ;           Child Loop BB1_601 Depth 5
                                        ;           Child Loop BB1_610 Depth 5
	scratch_load_u8 v0, off, off offset:36
	s_mov_b32 s35, exec_lo
	s_clause 0xf
	scratch_store_b8 off, v50, off offset:38
	scratch_store_b8 off, v57, off offset:39
	scratch_store_b8 off, v58, off offset:40
	scratch_store_b8 off, v59, off offset:41
	scratch_store_b8 off, v38, off offset:10
	scratch_store_b16 off, v47, off offset:8
	scratch_store_b32 off, v48, off offset:4
	scratch_store_b8 off, v38, off offset:18
	scratch_store_b16 off, v49, off offset:16
	scratch_store_b32 off, v51, off offset:12
	scratch_store_b8 off, v38, off offset:26
	scratch_store_b16 off, v52, off offset:24
	scratch_store_b32 off, v53, off offset:20
	scratch_store_b8 off, v38, off offset:34
	scratch_store_b16 off, v54, off offset:32
	scratch_store_b32 off, v55, off offset:28
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0x41, v0
	s_cbranch_execz .LBB1_156
; %bb.5:                                ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	v_mov_b32_e32 v0, 0x41
	s_mov_b32 s1, 1
	s_mov_b32 s0, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
.LBB1_6:                                ; %.lr.ph.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 0xff, v0
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	v_cmp_ne_u16_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=5
	s_add_i32 s6, s1, 36
	s_add_i32 s7, s1, 4
	scratch_load_u8 v0, off, s6
	scratch_load_u8 v1, off, s7
	s_and_not1_b32 s4, s4, exec_lo
	s_add_i32 s1, s1, 1
	s_and_not1_b32 s3, s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, v0, v1
	s_and_b32 s6, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s6
.LBB1_8:                                ; %Flow1139
                                        ;   in Loop: Header=BB1_6 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s4
	s_or_b32 s0, s5, s0
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_6
; %bb.9:                                ; %loop.exit.guard
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_156
; %bb.10:                               ;   in Loop: Header=BB1_4 Depth=4
	s_load_b64 s[26:27], s[18:19], 0x50
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_16
; %bb.11:                               ;   in Loop: Header=BB1_4 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[4:5], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_15
; %bb.12:                               ; %.preheader3.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s3, 0
.LBB1_13:                               ; %.preheader3.i.i.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_13
; %bb.14:                               ; %Flow1133
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_15:                               ; %Flow1135
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_16:                               ; %.loopexit4.i.i.i.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b128 v[0:3], v38, s[26:27]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_4 Depth=4
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[4:5], v[39:42], off offset:8
.LBB1_18:                               ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_26
; %bb.19:                               ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_22
; %bb.20:                               ; %.preheader1.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s8, 0
.LBB1_21:                               ; %.preheader1.i.i.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_21
.LBB1_22:                               ; %Flow1131
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_24
; %bb.23:                               ;   in Loop: Header=BB1_4 Depth=4
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_24:                               ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_26
; %bb.25:                               ;   in Loop: Header=BB1_4 Depth=4
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_26:                               ; %Flow1132
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_27:                               ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_29
; %bb.28:                               ;   in Loop: Header=BB1_27 Depth=5
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_29:                               ;   in Loop: Header=BB1_27 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_31
; %bb.30:                               ;   in Loop: Header=BB1_27 Depth=5
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_32
.LBB1_31:                               ;   in Loop: Header=BB1_27 Depth=5
	s_mov_b32 s1, -1
.LBB1_32:                               ; %Flow1126
                                        ;   in Loop: Header=BB1_27 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_27
; %bb.33:                               ;   in Loop: Header=BB1_4 Depth=4
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_37
; %bb.34:                               ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27] offset:24 glc
	global_load_b64 v[6:7], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_37
; %bb.35:                               ; %.preheader.i.i.i.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, 0
.LBB1_36:                               ; %.preheader.i.i.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_36
.LBB1_37:                               ; %__ockl_printf_begin.exit.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s24 :: v_dual_mov_b32 v5, v38
	v_mov_b32_e32 v6, v38
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v2, v43
	s_mov_b32 s0, 0
.LBB1_38:                               ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, 1, v2
	scratch_load_u8 v3, v2, off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v3
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_38
; %bb.39:                               ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s28
	s_cbranch_vccz .LBB1_126
; %bb.40:                               ;   in Loop: Header=BB1_4 Depth=4
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_mov_b32_e32 v28, 4
	s_mov_b32 s6, 0
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s25, vcc_lo
	v_and_b32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v4, vcc_lo, v4, 4
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s25, v3, vcc_lo
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v5, vcc_lo
.LBB1_41:                               ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB1_44 Depth 6
                                        ;             Child Loop BB1_52 Depth 6
                                        ;             Child Loop BB1_60 Depth 6
                                        ;             Child Loop BB1_68 Depth 6
                                        ;             Child Loop BB1_76 Depth 6
                                        ;             Child Loop BB1_84 Depth 6
                                        ;             Child Loop BB1_92 Depth 6
                                        ;             Child Loop BB1_100 Depth 6
                                        ;             Child Loop BB1_108 Depth 6
                                        ;             Child Loop BB1_114 Depth 6
                                        ;             Child Loop BB1_123 Depth 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 56, v[22:23]
                                        ; implicit-def: $sgpr1
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v25, 0, v23 :: v_dual_cndmask_b32 v24, 56, v22
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_47
; %bb.42:                               ;   in Loop: Header=BB1_41 Depth=5
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB1_46
; %bb.43:                               ; %.preheader31.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	v_lshlrev_b64 v[6:7], 3, v[24:25]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, v28
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_44:                               ; %.preheader31.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_u8 v8, v7, off
	v_mov_b32_e32 v9, s20
	v_add_nc_u32_e32 v7, 1, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0xffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], s0, v[8:9]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, s0, v6
	v_or_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v4, v8, v4
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_44
; %bb.45:                               ; %Flow1098
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_46:                               ; %Flow1100
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
.LBB1_47:                               ; %Flow1102
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v8, s1
	v_mov_b32_e32 v18, v28
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_49
; %bb.48:                               ;   in Loop: Header=BB1_41 Depth=5
	s_clause 0x5
	scratch_load_u8 v4, v28, off
	scratch_load_u8 v5, v28, off offset:1
	scratch_load_u8 v6, v28, off offset:2
	scratch_load_u8 v7, v28, off offset:3
	scratch_load_u8 v8, v28, off offset:5
	scratch_load_u8 v9, v28, off offset:4
	v_mov_b32_e32 v10, v38
	v_add_nc_u32_e32 v18, 8, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v4, 0xffff, v4
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v5, 8, v5
	s_clause 0x1
	scratch_load_u8 v11, v28, off offset:7
	scratch_load_d16_hi_u8 v10, v28, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v6, 16, v6
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v7, 24, v7
	v_or_b32_e32 v4, v5, v4
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v5, 8, v8
	v_add_nc_u32_e32 v8, -8, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v4, v4, v6, v7
	s_waitcnt vmcnt(2)
	v_or3_b32 v5, 0, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v4, v4, 0, 0
	v_or3_b32 v4, v4, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v6, 24, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v5, v5, v10, v6
.LBB1_49:                               ; %.loopexit32.i.i
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v8
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_55
; %bb.50:                               ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB1_54
; %bb.51:                               ; %.preheader29.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_52:                               ; %.preheader29.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v10, s20 :: v_dual_add_nc_u32 v9, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v8
	scratch_load_u8 v9, v9, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], s0, v[9:10]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v6, v9, v6
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_52
; %bb.53:                               ; %Flow1093
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_54:                               ; %Flow1095
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr8
.LBB1_55:                               ; %Flow1097
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v10, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_57
; %bb.56:                               ;   in Loop: Header=BB1_41 Depth=5
	s_clause 0x5
	scratch_load_u8 v6, v18, off
	scratch_load_u8 v7, v18, off offset:1
	scratch_load_u8 v9, v18, off offset:2
	scratch_load_u8 v10, v18, off offset:3
	scratch_load_u8 v11, v18, off offset:5
	scratch_load_u8 v12, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v13, v38 :: v_dual_and_b32 v6, 0xffff, v6
	s_clause 0x1
	scratch_load_u8 v14, v18, off offset:7
	scratch_load_d16_hi_u8 v13, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v7, 8, v7
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v6, v7, v6
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v7, 8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v6, v6, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v7, 0, v12, v7
	v_add_nc_u32_e32 v10, -8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v6, v6, 0, 0
	v_or3_b32 v6, v6, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v7, v7, v13, v9
.LBB1_57:                               ; %.loopexit30.i.i
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v10
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_63
; %bb.58:                               ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB1_62
; %bb.59:                               ; %.preheader27.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_60:                               ; %.preheader27.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s20 :: v_dual_add_nc_u32 v11, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v10
	scratch_load_u8 v11, v11, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], s0, v[11:12]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v9, v12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v8, v11, v8
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_60
; %bb.61:                               ; %Flow1088
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_62:                               ; %Flow1090
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr10
.LBB1_63:                               ; %Flow1092
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v12, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_65
; %bb.64:                               ;   in Loop: Header=BB1_41 Depth=5
	s_clause 0x5
	scratch_load_u8 v8, v18, off
	scratch_load_u8 v9, v18, off offset:1
	scratch_load_u8 v11, v18, off offset:2
	scratch_load_u8 v12, v18, off offset:3
	scratch_load_u8 v13, v18, off offset:5
	scratch_load_u8 v14, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v15, v38 :: v_dual_and_b32 v8, 0xffff, v8
	s_clause 0x1
	scratch_load_u8 v16, v18, off offset:7
	scratch_load_d16_hi_u8 v15, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v9, 8, v9
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v11, 16, v11
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v12, 24, v12
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v8, v9, v8
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v9, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v8, v8, v11, v12
	s_waitcnt vmcnt(2)
	v_or3_b32 v9, 0, v14, v9
	v_add_nc_u32_e32 v12, -8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v8, v8, 0, 0
	v_or3_b32 v8, v8, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v11, 24, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v15, v11
.LBB1_65:                               ; %.loopexit28.i.i
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v12
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_71
; %bb.66:                               ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v12
	s_cbranch_execz .LBB1_70
; %bb.67:                               ; %.preheader25.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_68:                               ; %.preheader25.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v14, s20 :: v_dual_add_nc_u32 v13, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v12
	scratch_load_u8 v13, v13, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xffff, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], s0, v[13:14]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v10, v13, v10
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_68
; %bb.69:                               ; %Flow1083
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_70:                               ; %Flow1085
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr12
.LBB1_71:                               ; %Flow1087
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v14, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_73
; %bb.72:                               ;   in Loop: Header=BB1_41 Depth=5
	s_clause 0x5
	scratch_load_u8 v10, v18, off
	scratch_load_u8 v11, v18, off offset:1
	scratch_load_u8 v13, v18, off offset:2
	scratch_load_u8 v14, v18, off offset:3
	scratch_load_u8 v15, v18, off offset:5
	scratch_load_u8 v16, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v17, v38 :: v_dual_and_b32 v10, 0xffff, v10
	s_clause 0x1
	scratch_load_u8 v19, v18, off offset:7
	scratch_load_d16_hi_u8 v17, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v11
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v13, 16, v13
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v10, v11, v10
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v11, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v10, v10, v13, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v16, v11
	v_add_nc_u32_e32 v14, -8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v10, v10, 0, 0
	v_or3_b32 v10, v10, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v13, 24, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v11, v11, v17, v13
.LBB1_73:                               ; %.loopexit26.i.i
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v14
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_79
; %bb.74:                               ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v14
	s_cbranch_execz .LBB1_78
; %bb.75:                               ; %.preheader23.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_76:                               ; %.preheader23.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v16, s20 :: v_dual_add_nc_u32 v15, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v14
	scratch_load_u8 v15, v15, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v15, v12
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_76
; %bb.77:                               ; %Flow1078
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_78:                               ; %Flow1080
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr14
.LBB1_79:                               ; %Flow1082
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v16, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_81
; %bb.80:                               ;   in Loop: Header=BB1_41 Depth=5
	s_clause 0x5
	scratch_load_u8 v12, v18, off
	scratch_load_u8 v13, v18, off offset:1
	scratch_load_u8 v15, v18, off offset:2
	scratch_load_u8 v16, v18, off offset:3
	scratch_load_u8 v17, v18, off offset:5
	scratch_load_u8 v19, v18, off offset:4
	v_mov_b32_e32 v20, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v12, 0xffff, v12
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v13, 8, v13
	s_clause 0x1
	scratch_load_u8 v21, v18, off offset:7
	scratch_load_d16_hi_u8 v20, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v12, v13, v12
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v13, 8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v12, v12, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v13, 0, v19, v13
	v_add_nc_u32_e32 v16, -8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, 0, 0
	v_or3_b32 v12, v12, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v13, v13, v20, v15
.LBB1_81:                               ; %.loopexit24.i.i
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v16
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_87
; %bb.82:                               ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v16
	s_cbranch_execz .LBB1_86
; %bb.83:                               ; %.preheader21.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_84:                               ; %.preheader21.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v20, s20 :: v_dual_add_nc_u32 v17, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v16
	scratch_load_u8 v17, v17, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v19, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v19, v14
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_84
; %bb.85:                               ; %Flow1073
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_86:                               ; %Flow1075
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr16
.LBB1_87:                               ; %Flow1077
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_89
; %bb.88:                               ;   in Loop: Header=BB1_41 Depth=5
	s_clause 0x5
	scratch_load_u8 v14, v18, off
	scratch_load_u8 v15, v18, off offset:1
	scratch_load_u8 v17, v18, off offset:2
	scratch_load_u8 v19, v18, off offset:3
	scratch_load_u8 v20, v18, off offset:5
	scratch_load_u8 v21, v18, off offset:4
	v_mov_b32_e32 v26, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xffff, v14
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v15, 8, v15
	s_clause 0x1
	scratch_load_u8 v27, v18, off offset:7
	scratch_load_d16_hi_u8 v26, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v14, v15, v14
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v14, v14, v17, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v21, v15
	v_add_nc_u32_e32 v19, -8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v14, 0, 0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v27
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v15, v26, v17
.LBB1_89:                               ; %.loopexit22.i.i
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_95
; %bb.90:                               ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB1_94
; %bb.91:                               ; %.preheader.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_92:                               ; %.preheader.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_u8 v20, v18, off
	v_mov_b32_e32 v21, s20
	v_add_nc_u32_e32 v19, -1, v19
	v_add_nc_u32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v20, 0xffff, v20
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, v21, v17
	v_or_b32_e32 v16, v20, v16
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_92
; %bb.93:                               ; %Flow1068
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_94:                               ; %Flow1070
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr18
.LBB1_95:                               ; %Flow1072
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_97
; %bb.96:                               ;   in Loop: Header=BB1_41 Depth=5
	s_clause 0x5
	scratch_load_u8 v16, v18, off
	scratch_load_u8 v17, v18, off offset:1
	scratch_load_u8 v19, v18, off offset:2
	scratch_load_u8 v20, v18, off offset:3
	scratch_load_u8 v21, v18, off offset:5
	scratch_load_u8 v26, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v27, v38 :: v_dual_and_b32 v16, 0xffff, v16
	s_clause 0x1
	scratch_load_u8 v29, v18, off offset:7
	scratch_load_d16_hi_u8 v27, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v17, 8, v17
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v19, 8, v21
	v_or_b32_e32 v16, v17, v16
	v_lshlrev_b32_e32 v17, 24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_or3_b32 v16, v16, v18, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v26, v19
	v_or3_b32 v16, v16, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v29
	s_waitcnt vmcnt(0)
	v_or3_b32 v17, v17, v27, v18
.LBB1_97:                               ; %.loopexit.i.i
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v26, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v27, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_103
; %bb.98:                               ;   in Loop: Header=BB1_41 Depth=5
	global_load_b64 v[20:21], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[26:27], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v19, v19, v21
	v_and_b32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v19, 24
	v_mul_hi_u32 v29, v18, 24
	v_mul_lo_u32 v18, v18, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v29, v19
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, v27, v19, vcc_lo
	global_load_b64 v[18:19], v[18:19], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[26:27], v[20:21]
	s_cbranch_execz .LBB1_102
; %bb.99:                               ; %.preheader3.i.i19.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_mov_b32 s3, 0
.LBB1_100:                              ; %.preheader3.i.i19.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[29:30], v38, s[26:27]
	v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, v18, v20
	v_and_b32_e32 v19, v19, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v18, 24, v[29:30]
	v_mov_b32_e32 v18, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, v19, 24, v[18:19]
	v_mov_b32_e32 v27, v29
	global_load_b64 v[18:19], v[26:27], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[20:21]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_100
; %bb.101:                              ; %Flow1065
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_102:                              ; %Flow1067
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_103:                              ; %.loopexit4.i.i14.i.i
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v38, s[26:27] offset:40
	global_load_b128 v[18:21], v38, s[26:27]
	v_readfirstlane_b32 s2, v26
	v_readfirstlane_b32 s3, v27
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v29
	v_readfirstlane_b32 s5, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s7, s4, 24
	s_mul_i32 s8, s4, 24
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_105
; %bb.104:                              ;   in Loop: Header=BB1_41 Depth=5
	s_add_i32 s11, s7, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v19, vcc_lo
	v_dual_mov_b32 v39, s9 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[26:27], v[39:42], off offset:8
.LBB1_105:                              ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s10
	v_cmp_lt_u64_e32 vcc_lo, 56, v[22:23]
	v_or_b32_e32 v26, 2, v2
	v_lshl_add_u32 v27, v24, 2, 28
	s_lshl_b64 s[4:5], s[4:5], 12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v26, v2 :: v_dual_and_b32 v29, 0x1e0, v27
	v_lshlrev_b64 v[26:27], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v20, vcc_lo, v20, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_and_or_b32 v2, 0xffffff1f, v2, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v20, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, v21, v27, vcc_lo
	s_clause 0x3
	global_store_b128 v[20:21], v[2:5], off
	global_store_b128 v[20:21], v[6:9], off offset:16
	global_store_b128 v[20:21], v[10:13], off offset:32
	global_store_b128 v[20:21], v[14:17], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_113
; %bb.106:                              ;   in Loop: Header=BB1_41 Depth=5
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	v_readfirstlane_b32 s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[2:3]
	s_mul_i32 s5, s11, 24
	s_mul_hi_u32 s9, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v19, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[10:11]
	s_cbranch_execz .LBB1_109
; %bb.107:                              ; %.preheader1.i.i17.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_mov_b32 s9, 0
.LBB1_108:                              ; %.preheader1.i.i17.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_108
.LBB1_109:                              ; %Flow1063
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s9, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_111
; %bb.110:                              ;   in Loop: Header=BB1_41 Depth=5
	s_bcnt1_i32_b32 s9, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s9
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_111:                              ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_113
; %bb.112:                              ;   in Loop: Header=BB1_41 Depth=5
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_113:                              ; %Flow1064
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s7, s7, s1
	v_add_co_u32 v2, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_114:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_116
; %bb.115:                              ;   in Loop: Header=BB1_114 Depth=6
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_116:                              ;   in Loop: Header=BB1_114 Depth=6
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_118
; %bb.117:                              ;   in Loop: Header=BB1_114 Depth=6
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_119
.LBB1_118:                              ;   in Loop: Header=BB1_114 Depth=6
	s_mov_b32 s1, -1
.LBB1_119:                              ; %Flow1058
                                        ;   in Loop: Header=BB1_114 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_114
; %bb.120:                              ;   in Loop: Header=BB1_41 Depth=5
	global_load_b128 v[2:5], v[20:21], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_124
; %bb.121:                              ;   in Loop: Header=BB1_41 Depth=5
	s_clause 0x2
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[10:11], v38, s[26:27] offset:24 glc
	global_load_b64 v[8:9], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v4, v6
	v_mul_hi_u32 v12, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v10
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v11
	global_store_b64 v[8:9], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_124
; %bb.122:                              ; %.preheader.i.i16.i.i.preheader
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_mov_b32 s0, 0
.LBB1_123:                              ; %.preheader.i.i16.i.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_41 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
	v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_123
.LBB1_124:                              ; %__ockl_hostcall_preview.exit20.i.i
                                        ;   in Loop: Header=BB1_41 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v22, vcc_lo, v22, v24
	v_sub_co_ci_u32_e32 v23, vcc_lo, v23, v25, vcc_lo
	v_add_nc_u32_e32 v28, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[22:23]
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_41
; %bb.125:                              ; %Flow1103
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, 0
	s_branch .LBB1_127
.LBB1_126:                              ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, -1
.LBB1_127:                              ; %Flow1120
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_156
; %bb.128:                              ;   in Loop: Header=BB1_4 Depth=4
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v3, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_134
; %bb.129:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b64 v[4:5], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_133
; %bb.130:                              ; %.preheader3.i.i.i41.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s3, 0
.LBB1_131:                              ; %.preheader3.i.i.i41.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_131
; %bb.132:                              ; %Flow1116
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_133:                              ; %Flow1118
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_134:                              ; %.loopexit4.i.i.i36.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v38, s[26:27] offset:40
	global_load_b128 v[4:7], v38, s[26:27]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_136
; %bb.135:                              ;   in Loop: Header=BB1_4 Depth=4
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[2:3], v[39:42], off offset:8
.LBB1_136:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[2:3], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v2
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v38
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v6, s20
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s22
	v_mov_b32_e32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_144
; %bb.137:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_140
; %bb.138:                              ; %.preheader1.i.i.i39.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s8, 0
.LBB1_139:                              ; %.preheader1.i.i.i39.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v38, v[0:3], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_139
.LBB1_140:                              ; %Flow1114
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_142
; %bb.141:                              ;   in Loop: Header=BB1_4 Depth=4
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[37:38], off offset:8
.LBB1_142:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_144
; %bb.143:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b32 v37, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_144:                              ; %Flow1115
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_145:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_147
; %bb.146:                              ;   in Loop: Header=BB1_145 Depth=5
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_147:                              ;   in Loop: Header=BB1_145 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_149
; %bb.148:                              ;   in Loop: Header=BB1_145 Depth=5
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_150
.LBB1_149:                              ;   in Loop: Header=BB1_145 Depth=5
	s_mov_b32 s1, -1
.LBB1_150:                              ; %Flow1109
                                        ;   in Loop: Header=BB1_145 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_145
; %bb.151:                              ;   in Loop: Header=BB1_4 Depth=4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_155
; %bb.152:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x2
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27] offset:24 glc
	global_load_b64 v[4:5], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_155
; %bb.153:                              ; %.preheader.i.i.i38.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, 0
.LBB1_154:                              ; %.preheader.i.i.i38.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_154
.LBB1_155:                              ; %Flow1107
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_156:                              ; %Flow1140
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s35
	s_clause 0x1
	scratch_load_u8 v0, off, off offset:36
	scratch_load_u8 v1, off, off offset:12
	s_mov_b32 s35, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e64 v0, v1
	s_cbranch_execz .LBB1_308
; %bb.157:                              ; %.lr.ph218.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s1, 1
	s_mov_b32 s0, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
.LBB1_158:                              ; %.lr.ph218.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_and_b32_e32 v0, 0xff, v0
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u16_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_160
; %bb.159:                              ;   in Loop: Header=BB1_158 Depth=5
	s_add_i32 s6, s1, 36
	s_add_i32 s7, s1, 12
	scratch_load_u8 v0, off, s6
	scratch_load_u8 v1, off, s7
	s_and_not1_b32 s4, s4, exec_lo
	s_add_i32 s1, s1, 1
	s_and_not1_b32 s3, s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, v0, v1
	s_and_b32 s6, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s6
.LBB1_160:                              ; %Flow1052
                                        ;   in Loop: Header=BB1_158 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s4
	s_or_b32 s0, s5, s0
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_158
; %bb.161:                              ; %loop.exit.guard789
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_308
; %bb.162:                              ;   in Loop: Header=BB1_4 Depth=4
	s_load_b64 s[26:27], s[18:19], 0x50
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_168
; %bb.163:                              ;   in Loop: Header=BB1_4 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[4:5], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_167
; %bb.164:                              ; %.preheader3.i.i.i48.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s3, 0
.LBB1_165:                              ; %.preheader3.i.i.i48.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_165
; %bb.166:                              ; %Flow1046
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_167:                              ; %Flow1048
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_168:                              ; %.loopexit4.i.i.i42.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b128 v[0:3], v38, s[26:27]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_170
; %bb.169:                              ;   in Loop: Header=BB1_4 Depth=4
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[4:5], v[39:42], off offset:8
.LBB1_170:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_178
; %bb.171:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_174
; %bb.172:                              ; %.preheader1.i.i.i46.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s8, 0
.LBB1_173:                              ; %.preheader1.i.i.i46.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_173
.LBB1_174:                              ; %Flow1044
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_176
; %bb.175:                              ;   in Loop: Header=BB1_4 Depth=4
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_176:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_178
; %bb.177:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_178:                              ; %Flow1045
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_179:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_181
; %bb.180:                              ;   in Loop: Header=BB1_179 Depth=5
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_181:                              ;   in Loop: Header=BB1_179 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_183
; %bb.182:                              ;   in Loop: Header=BB1_179 Depth=5
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_184
.LBB1_183:                              ;   in Loop: Header=BB1_179 Depth=5
	s_mov_b32 s1, -1
.LBB1_184:                              ; %Flow1039
                                        ;   in Loop: Header=BB1_179 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_179
; %bb.185:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_189
; %bb.186:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27] offset:24 glc
	global_load_b64 v[6:7], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_189
; %bb.187:                              ; %.preheader.i.i.i45.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, 0
.LBB1_188:                              ; %.preheader.i.i.i45.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_188
.LBB1_189:                              ; %__ockl_printf_begin.exit49.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s24 :: v_dual_mov_b32 v5, v38
	v_mov_b32_e32 v6, v38
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v2, v44
	s_mov_b32 s0, 0
.LBB1_190:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, 1, v2
	scratch_load_u8 v3, v2, off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v3
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_190
; %bb.191:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s29
	s_cbranch_vccz .LBB1_278
; %bb.192:                              ;   in Loop: Header=BB1_4 Depth=4
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_mov_b32_e32 v28, 12
	s_mov_b32 s6, 0
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s25, vcc_lo
	v_and_b32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v4, vcc_lo, v4, 12
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s25, v3, vcc_lo
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v5, vcc_lo
.LBB1_193:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB1_196 Depth 6
                                        ;             Child Loop BB1_204 Depth 6
                                        ;             Child Loop BB1_212 Depth 6
                                        ;             Child Loop BB1_220 Depth 6
                                        ;             Child Loop BB1_228 Depth 6
                                        ;             Child Loop BB1_236 Depth 6
                                        ;             Child Loop BB1_244 Depth 6
                                        ;             Child Loop BB1_252 Depth 6
                                        ;             Child Loop BB1_260 Depth 6
                                        ;             Child Loop BB1_266 Depth 6
                                        ;             Child Loop BB1_275 Depth 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 56, v[22:23]
                                        ; implicit-def: $sgpr1
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v25, 0, v23 :: v_dual_cndmask_b32 v24, 56, v22
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_199
; %bb.194:                              ;   in Loop: Header=BB1_193 Depth=5
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB1_198
; %bb.195:                              ; %.preheader31.i50.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	v_lshlrev_b64 v[6:7], 3, v[24:25]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, v28
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_196:                              ; %.preheader31.i50.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_u8 v8, v7, off
	v_mov_b32_e32 v9, s20
	v_add_nc_u32_e32 v7, 1, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0xffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], s0, v[8:9]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, s0, v6
	v_or_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v4, v8, v4
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_196
; %bb.197:                              ; %Flow1011
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_198:                              ; %Flow1013
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
.LBB1_199:                              ; %Flow1015
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v8, s1
	v_mov_b32_e32 v18, v28
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_201
; %bb.200:                              ;   in Loop: Header=BB1_193 Depth=5
	s_clause 0x5
	scratch_load_u8 v4, v28, off
	scratch_load_u8 v5, v28, off offset:1
	scratch_load_u8 v6, v28, off offset:2
	scratch_load_u8 v7, v28, off offset:3
	scratch_load_u8 v8, v28, off offset:5
	scratch_load_u8 v9, v28, off offset:4
	v_mov_b32_e32 v10, v38
	v_add_nc_u32_e32 v18, 8, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v4, 0xffff, v4
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v5, 8, v5
	s_clause 0x1
	scratch_load_u8 v11, v28, off offset:7
	scratch_load_d16_hi_u8 v10, v28, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v6, 16, v6
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v7, 24, v7
	v_or_b32_e32 v4, v5, v4
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v5, 8, v8
	v_add_nc_u32_e32 v8, -8, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v4, v4, v6, v7
	s_waitcnt vmcnt(2)
	v_or3_b32 v5, 0, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v4, v4, 0, 0
	v_or3_b32 v4, v4, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v6, 24, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v5, v5, v10, v6
.LBB1_201:                              ; %.loopexit32.i51.i
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v8
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_207
; %bb.202:                              ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB1_206
; %bb.203:                              ; %.preheader29.i52.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_204:                              ; %.preheader29.i52.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v10, s20 :: v_dual_add_nc_u32 v9, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v8
	scratch_load_u8 v9, v9, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], s0, v[9:10]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v6, v9, v6
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_204
; %bb.205:                              ; %Flow1006
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_206:                              ; %Flow1008
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr8
.LBB1_207:                              ; %Flow1010
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v10, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_209
; %bb.208:                              ;   in Loop: Header=BB1_193 Depth=5
	s_clause 0x5
	scratch_load_u8 v6, v18, off
	scratch_load_u8 v7, v18, off offset:1
	scratch_load_u8 v9, v18, off offset:2
	scratch_load_u8 v10, v18, off offset:3
	scratch_load_u8 v11, v18, off offset:5
	scratch_load_u8 v12, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v13, v38 :: v_dual_and_b32 v6, 0xffff, v6
	s_clause 0x1
	scratch_load_u8 v14, v18, off offset:7
	scratch_load_d16_hi_u8 v13, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v7, 8, v7
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v6, v7, v6
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v7, 8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v6, v6, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v7, 0, v12, v7
	v_add_nc_u32_e32 v10, -8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v6, v6, 0, 0
	v_or3_b32 v6, v6, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v7, v7, v13, v9
.LBB1_209:                              ; %.loopexit30.i53.i
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v10
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_215
; %bb.210:                              ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB1_214
; %bb.211:                              ; %.preheader27.i54.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_212:                              ; %.preheader27.i54.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s20 :: v_dual_add_nc_u32 v11, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v10
	scratch_load_u8 v11, v11, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], s0, v[11:12]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v9, v12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v8, v11, v8
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_212
; %bb.213:                              ; %Flow1001
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_214:                              ; %Flow1003
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr10
.LBB1_215:                              ; %Flow1005
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v12, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_217
; %bb.216:                              ;   in Loop: Header=BB1_193 Depth=5
	s_clause 0x5
	scratch_load_u8 v8, v18, off
	scratch_load_u8 v9, v18, off offset:1
	scratch_load_u8 v11, v18, off offset:2
	scratch_load_u8 v12, v18, off offset:3
	scratch_load_u8 v13, v18, off offset:5
	scratch_load_u8 v14, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v15, v38 :: v_dual_and_b32 v8, 0xffff, v8
	s_clause 0x1
	scratch_load_u8 v16, v18, off offset:7
	scratch_load_d16_hi_u8 v15, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v9, 8, v9
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v11, 16, v11
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v12, 24, v12
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v8, v9, v8
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v9, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v8, v8, v11, v12
	s_waitcnt vmcnt(2)
	v_or3_b32 v9, 0, v14, v9
	v_add_nc_u32_e32 v12, -8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v8, v8, 0, 0
	v_or3_b32 v8, v8, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v11, 24, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v15, v11
.LBB1_217:                              ; %.loopexit28.i55.i
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v12
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_223
; %bb.218:                              ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v12
	s_cbranch_execz .LBB1_222
; %bb.219:                              ; %.preheader25.i56.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_220:                              ; %.preheader25.i56.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v14, s20 :: v_dual_add_nc_u32 v13, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v12
	scratch_load_u8 v13, v13, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xffff, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], s0, v[13:14]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v10, v13, v10
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_220
; %bb.221:                              ; %Flow996
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_222:                              ; %Flow998
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr12
.LBB1_223:                              ; %Flow1000
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v14, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_225
; %bb.224:                              ;   in Loop: Header=BB1_193 Depth=5
	s_clause 0x5
	scratch_load_u8 v10, v18, off
	scratch_load_u8 v11, v18, off offset:1
	scratch_load_u8 v13, v18, off offset:2
	scratch_load_u8 v14, v18, off offset:3
	scratch_load_u8 v15, v18, off offset:5
	scratch_load_u8 v16, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v17, v38 :: v_dual_and_b32 v10, 0xffff, v10
	s_clause 0x1
	scratch_load_u8 v19, v18, off offset:7
	scratch_load_d16_hi_u8 v17, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v11
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v13, 16, v13
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v10, v11, v10
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v11, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v10, v10, v13, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v16, v11
	v_add_nc_u32_e32 v14, -8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v10, v10, 0, 0
	v_or3_b32 v10, v10, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v13, 24, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v11, v11, v17, v13
.LBB1_225:                              ; %.loopexit26.i57.i
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v14
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_231
; %bb.226:                              ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v14
	s_cbranch_execz .LBB1_230
; %bb.227:                              ; %.preheader23.i58.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_228:                              ; %.preheader23.i58.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v16, s20 :: v_dual_add_nc_u32 v15, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v14
	scratch_load_u8 v15, v15, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v15, v12
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_228
; %bb.229:                              ; %Flow991
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_230:                              ; %Flow993
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr14
.LBB1_231:                              ; %Flow995
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v16, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_233
; %bb.232:                              ;   in Loop: Header=BB1_193 Depth=5
	s_clause 0x5
	scratch_load_u8 v12, v18, off
	scratch_load_u8 v13, v18, off offset:1
	scratch_load_u8 v15, v18, off offset:2
	scratch_load_u8 v16, v18, off offset:3
	scratch_load_u8 v17, v18, off offset:5
	scratch_load_u8 v19, v18, off offset:4
	v_mov_b32_e32 v20, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v12, 0xffff, v12
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v13, 8, v13
	s_clause 0x1
	scratch_load_u8 v21, v18, off offset:7
	scratch_load_d16_hi_u8 v20, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v12, v13, v12
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v13, 8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v12, v12, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v13, 0, v19, v13
	v_add_nc_u32_e32 v16, -8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, 0, 0
	v_or3_b32 v12, v12, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v13, v13, v20, v15
.LBB1_233:                              ; %.loopexit24.i59.i
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v16
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_239
; %bb.234:                              ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v16
	s_cbranch_execz .LBB1_238
; %bb.235:                              ; %.preheader21.i60.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_236:                              ; %.preheader21.i60.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v20, s20 :: v_dual_add_nc_u32 v17, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v16
	scratch_load_u8 v17, v17, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v19, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v19, v14
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_236
; %bb.237:                              ; %Flow986
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_238:                              ; %Flow988
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr16
.LBB1_239:                              ; %Flow990
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_241
; %bb.240:                              ;   in Loop: Header=BB1_193 Depth=5
	s_clause 0x5
	scratch_load_u8 v14, v18, off
	scratch_load_u8 v15, v18, off offset:1
	scratch_load_u8 v17, v18, off offset:2
	scratch_load_u8 v19, v18, off offset:3
	scratch_load_u8 v20, v18, off offset:5
	scratch_load_u8 v21, v18, off offset:4
	v_mov_b32_e32 v26, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xffff, v14
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v15, 8, v15
	s_clause 0x1
	scratch_load_u8 v27, v18, off offset:7
	scratch_load_d16_hi_u8 v26, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v14, v15, v14
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v14, v14, v17, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v21, v15
	v_add_nc_u32_e32 v19, -8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v14, 0, 0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v27
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v15, v26, v17
.LBB1_241:                              ; %.loopexit22.i61.i
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_247
; %bb.242:                              ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB1_246
; %bb.243:                              ; %.preheader.i62.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_244:                              ; %.preheader.i62.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_u8 v20, v18, off
	v_mov_b32_e32 v21, s20
	v_add_nc_u32_e32 v19, -1, v19
	v_add_nc_u32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v20, 0xffff, v20
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, v21, v17
	v_or_b32_e32 v16, v20, v16
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_244
; %bb.245:                              ; %Flow981
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_246:                              ; %Flow983
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr18
.LBB1_247:                              ; %Flow985
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_249
; %bb.248:                              ;   in Loop: Header=BB1_193 Depth=5
	s_clause 0x5
	scratch_load_u8 v16, v18, off
	scratch_load_u8 v17, v18, off offset:1
	scratch_load_u8 v19, v18, off offset:2
	scratch_load_u8 v20, v18, off offset:3
	scratch_load_u8 v21, v18, off offset:5
	scratch_load_u8 v26, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v27, v38 :: v_dual_and_b32 v16, 0xffff, v16
	s_clause 0x1
	scratch_load_u8 v29, v18, off offset:7
	scratch_load_d16_hi_u8 v27, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v17, 8, v17
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v19, 8, v21
	v_or_b32_e32 v16, v17, v16
	v_lshlrev_b32_e32 v17, 24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_or3_b32 v16, v16, v18, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v26, v19
	v_or3_b32 v16, v16, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v29
	s_waitcnt vmcnt(0)
	v_or3_b32 v17, v17, v27, v18
.LBB1_249:                              ; %.loopexit.i63.i
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v26, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v27, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_255
; %bb.250:                              ;   in Loop: Header=BB1_193 Depth=5
	global_load_b64 v[20:21], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[26:27], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v19, v19, v21
	v_and_b32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v19, 24
	v_mul_hi_u32 v29, v18, 24
	v_mul_lo_u32 v18, v18, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v29, v19
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, v27, v19, vcc_lo
	global_load_b64 v[18:19], v[18:19], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[26:27], v[20:21]
	s_cbranch_execz .LBB1_254
; %bb.251:                              ; %.preheader3.i.i19.i70.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_mov_b32 s3, 0
.LBB1_252:                              ; %.preheader3.i.i19.i70.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[29:30], v38, s[26:27]
	v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, v18, v20
	v_and_b32_e32 v19, v19, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v18, 24, v[29:30]
	v_mov_b32_e32 v18, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, v19, 24, v[18:19]
	v_mov_b32_e32 v27, v29
	global_load_b64 v[18:19], v[26:27], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[20:21]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_252
; %bb.253:                              ; %Flow978
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_254:                              ; %Flow980
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_255:                              ; %.loopexit4.i.i14.i64.i
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v38, s[26:27] offset:40
	global_load_b128 v[18:21], v38, s[26:27]
	v_readfirstlane_b32 s2, v26
	v_readfirstlane_b32 s3, v27
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v29
	v_readfirstlane_b32 s5, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s7, s4, 24
	s_mul_i32 s8, s4, 24
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_257
; %bb.256:                              ;   in Loop: Header=BB1_193 Depth=5
	s_add_i32 s11, s7, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v19, vcc_lo
	v_dual_mov_b32 v39, s9 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[26:27], v[39:42], off offset:8
.LBB1_257:                              ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s10
	v_cmp_lt_u64_e32 vcc_lo, 56, v[22:23]
	v_or_b32_e32 v26, 2, v2
	v_lshl_add_u32 v27, v24, 2, 28
	s_lshl_b64 s[4:5], s[4:5], 12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v26, v2 :: v_dual_and_b32 v29, 0x1e0, v27
	v_lshlrev_b64 v[26:27], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v20, vcc_lo, v20, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_and_or_b32 v2, 0xffffff1f, v2, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v20, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, v21, v27, vcc_lo
	s_clause 0x3
	global_store_b128 v[20:21], v[2:5], off
	global_store_b128 v[20:21], v[6:9], off offset:16
	global_store_b128 v[20:21], v[10:13], off offset:32
	global_store_b128 v[20:21], v[14:17], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_265
; %bb.258:                              ;   in Loop: Header=BB1_193 Depth=5
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	v_readfirstlane_b32 s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[2:3]
	s_mul_i32 s5, s11, 24
	s_mul_hi_u32 s9, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v19, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[10:11]
	s_cbranch_execz .LBB1_261
; %bb.259:                              ; %.preheader1.i.i17.i68.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_mov_b32 s9, 0
.LBB1_260:                              ; %.preheader1.i.i17.i68.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_260
.LBB1_261:                              ; %Flow976
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s9, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_263
; %bb.262:                              ;   in Loop: Header=BB1_193 Depth=5
	s_bcnt1_i32_b32 s9, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s9
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_263:                              ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_265
; %bb.264:                              ;   in Loop: Header=BB1_193 Depth=5
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_265:                              ; %Flow977
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s7, s7, s1
	v_add_co_u32 v2, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_266:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_268
; %bb.267:                              ;   in Loop: Header=BB1_266 Depth=6
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_268:                              ;   in Loop: Header=BB1_266 Depth=6
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_270
; %bb.269:                              ;   in Loop: Header=BB1_266 Depth=6
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_271
.LBB1_270:                              ;   in Loop: Header=BB1_266 Depth=6
	s_mov_b32 s1, -1
.LBB1_271:                              ; %Flow971
                                        ;   in Loop: Header=BB1_266 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_266
; %bb.272:                              ;   in Loop: Header=BB1_193 Depth=5
	global_load_b128 v[2:5], v[20:21], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_276
; %bb.273:                              ;   in Loop: Header=BB1_193 Depth=5
	s_clause 0x2
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[10:11], v38, s[26:27] offset:24 glc
	global_load_b64 v[8:9], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v4, v6
	v_mul_hi_u32 v12, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v10
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v11
	global_store_b64 v[8:9], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_276
; %bb.274:                              ; %.preheader.i.i16.i67.i.preheader
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_mov_b32 s0, 0
.LBB1_275:                              ; %.preheader.i.i16.i67.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_193 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
	v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_275
.LBB1_276:                              ; %__ockl_hostcall_preview.exit20.i66.i
                                        ;   in Loop: Header=BB1_193 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v22, vcc_lo, v22, v24
	v_sub_co_ci_u32_e32 v23, vcc_lo, v23, v25, vcc_lo
	v_add_nc_u32_e32 v28, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[22:23]
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_193
; %bb.277:                              ; %Flow1016
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, 0
	s_branch .LBB1_279
.LBB1_278:                              ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, -1
.LBB1_279:                              ; %Flow1033
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_308
; %bb.280:                              ;   in Loop: Header=BB1_4 Depth=4
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v3, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_286
; %bb.281:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b64 v[4:5], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_285
; %bb.282:                              ; %.preheader3.i.i.i77.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s3, 0
.LBB1_283:                              ; %.preheader3.i.i.i77.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_283
; %bb.284:                              ; %Flow1029
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_285:                              ; %Flow1031
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_286:                              ; %.loopexit4.i.i.i71.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v38, s[26:27] offset:40
	global_load_b128 v[4:7], v38, s[26:27]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_288
; %bb.287:                              ;   in Loop: Header=BB1_4 Depth=4
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[2:3], v[39:42], off offset:8
.LBB1_288:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[2:3], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v2
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v38
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v6, s20
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s22
	v_mov_b32_e32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_296
; %bb.289:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_292
; %bb.290:                              ; %.preheader1.i.i.i75.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s8, 0
.LBB1_291:                              ; %.preheader1.i.i.i75.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v38, v[0:3], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_291
.LBB1_292:                              ; %Flow1027
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_294
; %bb.293:                              ;   in Loop: Header=BB1_4 Depth=4
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[37:38], off offset:8
.LBB1_294:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_296
; %bb.295:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b32 v37, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_296:                              ; %Flow1028
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_297:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_299
; %bb.298:                              ;   in Loop: Header=BB1_297 Depth=5
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_299:                              ;   in Loop: Header=BB1_297 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_301
; %bb.300:                              ;   in Loop: Header=BB1_297 Depth=5
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_302
.LBB1_301:                              ;   in Loop: Header=BB1_297 Depth=5
	s_mov_b32 s1, -1
.LBB1_302:                              ; %Flow1022
                                        ;   in Loop: Header=BB1_297 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_297
; %bb.303:                              ;   in Loop: Header=BB1_4 Depth=4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_307
; %bb.304:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x2
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27] offset:24 glc
	global_load_b64 v[4:5], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_307
; %bb.305:                              ; %.preheader.i.i.i74.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, 0
.LBB1_306:                              ; %.preheader.i.i.i74.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_306
.LBB1_307:                              ; %Flow1020
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_308:                              ; %Flow1053
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s35
	s_clause 0x1
	scratch_load_u8 v0, off, off offset:36
	scratch_load_u8 v1, off, off offset:20
	s_mov_b32 s35, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e64 v0, v1
	s_cbranch_execz .LBB1_460
; %bb.309:                              ; %.lr.ph221.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s1, 1
	s_mov_b32 s0, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
.LBB1_310:                              ; %.lr.ph221.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_and_b32_e32 v0, 0xff, v0
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u16_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_312
; %bb.311:                              ;   in Loop: Header=BB1_310 Depth=5
	s_add_i32 s6, s1, 36
	s_add_i32 s7, s1, 20
	scratch_load_u8 v0, off, s6
	scratch_load_u8 v1, off, s7
	s_and_not1_b32 s4, s4, exec_lo
	s_add_i32 s1, s1, 1
	s_and_not1_b32 s3, s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, v0, v1
	s_and_b32 s6, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s6
.LBB1_312:                              ; %Flow965
                                        ;   in Loop: Header=BB1_310 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s4
	s_or_b32 s0, s5, s0
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_310
; %bb.313:                              ; %loop.exit.guard791
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_460
; %bb.314:                              ;   in Loop: Header=BB1_4 Depth=4
	s_load_b64 s[26:27], s[18:19], 0x50
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_320
; %bb.315:                              ;   in Loop: Header=BB1_4 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[4:5], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_319
; %bb.316:                              ; %.preheader3.i.i.i85.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s3, 0
.LBB1_317:                              ; %.preheader3.i.i.i85.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_317
; %bb.318:                              ; %Flow959
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_319:                              ; %Flow961
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_320:                              ; %.loopexit4.i.i.i79.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b128 v[0:3], v38, s[26:27]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_322
; %bb.321:                              ;   in Loop: Header=BB1_4 Depth=4
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[4:5], v[39:42], off offset:8
.LBB1_322:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_330
; %bb.323:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_326
; %bb.324:                              ; %.preheader1.i.i.i83.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s8, 0
.LBB1_325:                              ; %.preheader1.i.i.i83.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_325
.LBB1_326:                              ; %Flow957
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_328
; %bb.327:                              ;   in Loop: Header=BB1_4 Depth=4
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_328:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_330
; %bb.329:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_330:                              ; %Flow958
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_331:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_333
; %bb.332:                              ;   in Loop: Header=BB1_331 Depth=5
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_333:                              ;   in Loop: Header=BB1_331 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_335
; %bb.334:                              ;   in Loop: Header=BB1_331 Depth=5
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_336
.LBB1_335:                              ;   in Loop: Header=BB1_331 Depth=5
	s_mov_b32 s1, -1
.LBB1_336:                              ; %Flow952
                                        ;   in Loop: Header=BB1_331 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_331
; %bb.337:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_341
; %bb.338:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27] offset:24 glc
	global_load_b64 v[6:7], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_341
; %bb.339:                              ; %.preheader.i.i.i82.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, 0
.LBB1_340:                              ; %.preheader.i.i.i82.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_340
.LBB1_341:                              ; %__ockl_printf_begin.exit86.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s24 :: v_dual_mov_b32 v5, v38
	v_mov_b32_e32 v6, v38
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v2, v45
	s_mov_b32 s0, 0
.LBB1_342:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, 1, v2
	scratch_load_u8 v3, v2, off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v3
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_342
; %bb.343:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccz .LBB1_430
; %bb.344:                              ;   in Loop: Header=BB1_4 Depth=4
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_mov_b32_e32 v28, 20
	s_mov_b32 s6, 0
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s25, vcc_lo
	v_and_b32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v4, vcc_lo, v4, 20
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s25, v3, vcc_lo
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v5, vcc_lo
.LBB1_345:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB1_348 Depth 6
                                        ;             Child Loop BB1_356 Depth 6
                                        ;             Child Loop BB1_364 Depth 6
                                        ;             Child Loop BB1_372 Depth 6
                                        ;             Child Loop BB1_380 Depth 6
                                        ;             Child Loop BB1_388 Depth 6
                                        ;             Child Loop BB1_396 Depth 6
                                        ;             Child Loop BB1_404 Depth 6
                                        ;             Child Loop BB1_412 Depth 6
                                        ;             Child Loop BB1_418 Depth 6
                                        ;             Child Loop BB1_427 Depth 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 56, v[22:23]
                                        ; implicit-def: $sgpr1
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v25, 0, v23 :: v_dual_cndmask_b32 v24, 56, v22
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_351
; %bb.346:                              ;   in Loop: Header=BB1_345 Depth=5
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB1_350
; %bb.347:                              ; %.preheader31.i87.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	v_lshlrev_b64 v[6:7], 3, v[24:25]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, v28
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_348:                              ; %.preheader31.i87.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_u8 v8, v7, off
	v_mov_b32_e32 v9, s20
	v_add_nc_u32_e32 v7, 1, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0xffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], s0, v[8:9]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, s0, v6
	v_or_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v4, v8, v4
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_348
; %bb.349:                              ; %Flow924
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_350:                              ; %Flow926
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
.LBB1_351:                              ; %Flow928
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v8, s1
	v_mov_b32_e32 v18, v28
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_353
; %bb.352:                              ;   in Loop: Header=BB1_345 Depth=5
	s_clause 0x5
	scratch_load_u8 v4, v28, off
	scratch_load_u8 v5, v28, off offset:1
	scratch_load_u8 v6, v28, off offset:2
	scratch_load_u8 v7, v28, off offset:3
	scratch_load_u8 v8, v28, off offset:5
	scratch_load_u8 v9, v28, off offset:4
	v_mov_b32_e32 v10, v38
	v_add_nc_u32_e32 v18, 8, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v4, 0xffff, v4
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v5, 8, v5
	s_clause 0x1
	scratch_load_u8 v11, v28, off offset:7
	scratch_load_d16_hi_u8 v10, v28, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v6, 16, v6
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v7, 24, v7
	v_or_b32_e32 v4, v5, v4
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v5, 8, v8
	v_add_nc_u32_e32 v8, -8, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v4, v4, v6, v7
	s_waitcnt vmcnt(2)
	v_or3_b32 v5, 0, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v4, v4, 0, 0
	v_or3_b32 v4, v4, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v6, 24, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v5, v5, v10, v6
.LBB1_353:                              ; %.loopexit32.i88.i
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v8
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_359
; %bb.354:                              ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB1_358
; %bb.355:                              ; %.preheader29.i89.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_356:                              ; %.preheader29.i89.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v10, s20 :: v_dual_add_nc_u32 v9, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v8
	scratch_load_u8 v9, v9, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], s0, v[9:10]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v6, v9, v6
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_356
; %bb.357:                              ; %Flow919
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_358:                              ; %Flow921
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr8
.LBB1_359:                              ; %Flow923
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v10, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_361
; %bb.360:                              ;   in Loop: Header=BB1_345 Depth=5
	s_clause 0x5
	scratch_load_u8 v6, v18, off
	scratch_load_u8 v7, v18, off offset:1
	scratch_load_u8 v9, v18, off offset:2
	scratch_load_u8 v10, v18, off offset:3
	scratch_load_u8 v11, v18, off offset:5
	scratch_load_u8 v12, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v13, v38 :: v_dual_and_b32 v6, 0xffff, v6
	s_clause 0x1
	scratch_load_u8 v14, v18, off offset:7
	scratch_load_d16_hi_u8 v13, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v7, 8, v7
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v6, v7, v6
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v7, 8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v6, v6, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v7, 0, v12, v7
	v_add_nc_u32_e32 v10, -8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v6, v6, 0, 0
	v_or3_b32 v6, v6, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v7, v7, v13, v9
.LBB1_361:                              ; %.loopexit30.i90.i
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v10
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_367
; %bb.362:                              ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB1_366
; %bb.363:                              ; %.preheader27.i91.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_364:                              ; %.preheader27.i91.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s20 :: v_dual_add_nc_u32 v11, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v10
	scratch_load_u8 v11, v11, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], s0, v[11:12]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v9, v12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v8, v11, v8
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_364
; %bb.365:                              ; %Flow914
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_366:                              ; %Flow916
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr10
.LBB1_367:                              ; %Flow918
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v12, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_369
; %bb.368:                              ;   in Loop: Header=BB1_345 Depth=5
	s_clause 0x5
	scratch_load_u8 v8, v18, off
	scratch_load_u8 v9, v18, off offset:1
	scratch_load_u8 v11, v18, off offset:2
	scratch_load_u8 v12, v18, off offset:3
	scratch_load_u8 v13, v18, off offset:5
	scratch_load_u8 v14, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v15, v38 :: v_dual_and_b32 v8, 0xffff, v8
	s_clause 0x1
	scratch_load_u8 v16, v18, off offset:7
	scratch_load_d16_hi_u8 v15, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v9, 8, v9
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v11, 16, v11
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v12, 24, v12
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v8, v9, v8
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v9, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v8, v8, v11, v12
	s_waitcnt vmcnt(2)
	v_or3_b32 v9, 0, v14, v9
	v_add_nc_u32_e32 v12, -8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v8, v8, 0, 0
	v_or3_b32 v8, v8, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v11, 24, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v15, v11
.LBB1_369:                              ; %.loopexit28.i92.i
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v12
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_375
; %bb.370:                              ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v12
	s_cbranch_execz .LBB1_374
; %bb.371:                              ; %.preheader25.i93.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_372:                              ; %.preheader25.i93.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v14, s20 :: v_dual_add_nc_u32 v13, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v12
	scratch_load_u8 v13, v13, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xffff, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], s0, v[13:14]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v10, v13, v10
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_372
; %bb.373:                              ; %Flow909
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_374:                              ; %Flow911
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr12
.LBB1_375:                              ; %Flow913
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v14, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_377
; %bb.376:                              ;   in Loop: Header=BB1_345 Depth=5
	s_clause 0x5
	scratch_load_u8 v10, v18, off
	scratch_load_u8 v11, v18, off offset:1
	scratch_load_u8 v13, v18, off offset:2
	scratch_load_u8 v14, v18, off offset:3
	scratch_load_u8 v15, v18, off offset:5
	scratch_load_u8 v16, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v17, v38 :: v_dual_and_b32 v10, 0xffff, v10
	s_clause 0x1
	scratch_load_u8 v19, v18, off offset:7
	scratch_load_d16_hi_u8 v17, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v11
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v13, 16, v13
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v10, v11, v10
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v11, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v10, v10, v13, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v16, v11
	v_add_nc_u32_e32 v14, -8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v10, v10, 0, 0
	v_or3_b32 v10, v10, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v13, 24, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v11, v11, v17, v13
.LBB1_377:                              ; %.loopexit26.i94.i
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v14
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_383
; %bb.378:                              ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v14
	s_cbranch_execz .LBB1_382
; %bb.379:                              ; %.preheader23.i95.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_380:                              ; %.preheader23.i95.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v16, s20 :: v_dual_add_nc_u32 v15, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v14
	scratch_load_u8 v15, v15, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v15, v12
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_380
; %bb.381:                              ; %Flow904
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_382:                              ; %Flow906
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr14
.LBB1_383:                              ; %Flow908
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v16, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_385
; %bb.384:                              ;   in Loop: Header=BB1_345 Depth=5
	s_clause 0x5
	scratch_load_u8 v12, v18, off
	scratch_load_u8 v13, v18, off offset:1
	scratch_load_u8 v15, v18, off offset:2
	scratch_load_u8 v16, v18, off offset:3
	scratch_load_u8 v17, v18, off offset:5
	scratch_load_u8 v19, v18, off offset:4
	v_mov_b32_e32 v20, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v12, 0xffff, v12
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v13, 8, v13
	s_clause 0x1
	scratch_load_u8 v21, v18, off offset:7
	scratch_load_d16_hi_u8 v20, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v12, v13, v12
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v13, 8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v12, v12, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v13, 0, v19, v13
	v_add_nc_u32_e32 v16, -8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, 0, 0
	v_or3_b32 v12, v12, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v13, v13, v20, v15
.LBB1_385:                              ; %.loopexit24.i96.i
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v16
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_391
; %bb.386:                              ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v16
	s_cbranch_execz .LBB1_390
; %bb.387:                              ; %.preheader21.i97.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_388:                              ; %.preheader21.i97.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v20, s20 :: v_dual_add_nc_u32 v17, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v16
	scratch_load_u8 v17, v17, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v19, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v19, v14
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_388
; %bb.389:                              ; %Flow899
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_390:                              ; %Flow901
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr16
.LBB1_391:                              ; %Flow903
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_393
; %bb.392:                              ;   in Loop: Header=BB1_345 Depth=5
	s_clause 0x5
	scratch_load_u8 v14, v18, off
	scratch_load_u8 v15, v18, off offset:1
	scratch_load_u8 v17, v18, off offset:2
	scratch_load_u8 v19, v18, off offset:3
	scratch_load_u8 v20, v18, off offset:5
	scratch_load_u8 v21, v18, off offset:4
	v_mov_b32_e32 v26, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xffff, v14
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v15, 8, v15
	s_clause 0x1
	scratch_load_u8 v27, v18, off offset:7
	scratch_load_d16_hi_u8 v26, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v14, v15, v14
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v14, v14, v17, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v21, v15
	v_add_nc_u32_e32 v19, -8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v14, 0, 0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v27
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v15, v26, v17
.LBB1_393:                              ; %.loopexit22.i98.i
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_399
; %bb.394:                              ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB1_398
; %bb.395:                              ; %.preheader.i99.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_396:                              ; %.preheader.i99.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_u8 v20, v18, off
	v_mov_b32_e32 v21, s20
	v_add_nc_u32_e32 v19, -1, v19
	v_add_nc_u32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v20, 0xffff, v20
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, v21, v17
	v_or_b32_e32 v16, v20, v16
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_396
; %bb.397:                              ; %Flow894
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_398:                              ; %Flow896
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr18
.LBB1_399:                              ; %Flow898
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_401
; %bb.400:                              ;   in Loop: Header=BB1_345 Depth=5
	s_clause 0x5
	scratch_load_u8 v16, v18, off
	scratch_load_u8 v17, v18, off offset:1
	scratch_load_u8 v19, v18, off offset:2
	scratch_load_u8 v20, v18, off offset:3
	scratch_load_u8 v21, v18, off offset:5
	scratch_load_u8 v26, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v27, v38 :: v_dual_and_b32 v16, 0xffff, v16
	s_clause 0x1
	scratch_load_u8 v29, v18, off offset:7
	scratch_load_d16_hi_u8 v27, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v17, 8, v17
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v19, 8, v21
	v_or_b32_e32 v16, v17, v16
	v_lshlrev_b32_e32 v17, 24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_or3_b32 v16, v16, v18, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v26, v19
	v_or3_b32 v16, v16, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v29
	s_waitcnt vmcnt(0)
	v_or3_b32 v17, v17, v27, v18
.LBB1_401:                              ; %.loopexit.i100.i
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v26, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v27, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_407
; %bb.402:                              ;   in Loop: Header=BB1_345 Depth=5
	global_load_b64 v[20:21], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[26:27], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v19, v19, v21
	v_and_b32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v19, 24
	v_mul_hi_u32 v29, v18, 24
	v_mul_lo_u32 v18, v18, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v29, v19
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, v27, v19, vcc_lo
	global_load_b64 v[18:19], v[18:19], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[26:27], v[20:21]
	s_cbranch_execz .LBB1_406
; %bb.403:                              ; %.preheader3.i.i19.i107.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_mov_b32 s3, 0
.LBB1_404:                              ; %.preheader3.i.i19.i107.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[29:30], v38, s[26:27]
	v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, v18, v20
	v_and_b32_e32 v19, v19, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v18, 24, v[29:30]
	v_mov_b32_e32 v18, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, v19, 24, v[18:19]
	v_mov_b32_e32 v27, v29
	global_load_b64 v[18:19], v[26:27], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[20:21]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_404
; %bb.405:                              ; %Flow891
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_406:                              ; %Flow893
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_407:                              ; %.loopexit4.i.i14.i101.i
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v38, s[26:27] offset:40
	global_load_b128 v[18:21], v38, s[26:27]
	v_readfirstlane_b32 s2, v26
	v_readfirstlane_b32 s3, v27
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v29
	v_readfirstlane_b32 s5, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s7, s4, 24
	s_mul_i32 s8, s4, 24
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_409
; %bb.408:                              ;   in Loop: Header=BB1_345 Depth=5
	s_add_i32 s11, s7, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v19, vcc_lo
	v_dual_mov_b32 v39, s9 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[26:27], v[39:42], off offset:8
.LBB1_409:                              ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s10
	v_cmp_lt_u64_e32 vcc_lo, 56, v[22:23]
	v_or_b32_e32 v26, 2, v2
	v_lshl_add_u32 v27, v24, 2, 28
	s_lshl_b64 s[4:5], s[4:5], 12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v26, v2 :: v_dual_and_b32 v29, 0x1e0, v27
	v_lshlrev_b64 v[26:27], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v20, vcc_lo, v20, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_and_or_b32 v2, 0xffffff1f, v2, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v20, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, v21, v27, vcc_lo
	s_clause 0x3
	global_store_b128 v[20:21], v[2:5], off
	global_store_b128 v[20:21], v[6:9], off offset:16
	global_store_b128 v[20:21], v[10:13], off offset:32
	global_store_b128 v[20:21], v[14:17], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_417
; %bb.410:                              ;   in Loop: Header=BB1_345 Depth=5
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	v_readfirstlane_b32 s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[2:3]
	s_mul_i32 s5, s11, 24
	s_mul_hi_u32 s9, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v19, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[10:11]
	s_cbranch_execz .LBB1_413
; %bb.411:                              ; %.preheader1.i.i17.i105.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_mov_b32 s9, 0
.LBB1_412:                              ; %.preheader1.i.i17.i105.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_412
.LBB1_413:                              ; %Flow889
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s9, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_415
; %bb.414:                              ;   in Loop: Header=BB1_345 Depth=5
	s_bcnt1_i32_b32 s9, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s9
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_415:                              ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_417
; %bb.416:                              ;   in Loop: Header=BB1_345 Depth=5
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_417:                              ; %Flow890
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s7, s7, s1
	v_add_co_u32 v2, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_418:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_420
; %bb.419:                              ;   in Loop: Header=BB1_418 Depth=6
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_420:                              ;   in Loop: Header=BB1_418 Depth=6
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_422
; %bb.421:                              ;   in Loop: Header=BB1_418 Depth=6
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_423
.LBB1_422:                              ;   in Loop: Header=BB1_418 Depth=6
	s_mov_b32 s1, -1
.LBB1_423:                              ; %Flow884
                                        ;   in Loop: Header=BB1_418 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_418
; %bb.424:                              ;   in Loop: Header=BB1_345 Depth=5
	global_load_b128 v[2:5], v[20:21], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_428
; %bb.425:                              ;   in Loop: Header=BB1_345 Depth=5
	s_clause 0x2
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[10:11], v38, s[26:27] offset:24 glc
	global_load_b64 v[8:9], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v4, v6
	v_mul_hi_u32 v12, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v10
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v11
	global_store_b64 v[8:9], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_428
; %bb.426:                              ; %.preheader.i.i16.i104.i.preheader
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_mov_b32 s0, 0
.LBB1_427:                              ; %.preheader.i.i16.i104.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_345 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
	v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_427
.LBB1_428:                              ; %__ockl_hostcall_preview.exit20.i103.i
                                        ;   in Loop: Header=BB1_345 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v22, vcc_lo, v22, v24
	v_sub_co_ci_u32_e32 v23, vcc_lo, v23, v25, vcc_lo
	v_add_nc_u32_e32 v28, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[22:23]
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_345
; %bb.429:                              ; %Flow929
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, 0
	s_branch .LBB1_431
.LBB1_430:                              ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, -1
.LBB1_431:                              ; %Flow946
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_460
; %bb.432:                              ;   in Loop: Header=BB1_4 Depth=4
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v3, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_438
; %bb.433:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b64 v[4:5], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_437
; %bb.434:                              ; %.preheader3.i.i.i114.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s3, 0
.LBB1_435:                              ; %.preheader3.i.i.i114.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_435
; %bb.436:                              ; %Flow942
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_437:                              ; %Flow944
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_438:                              ; %.loopexit4.i.i.i108.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v38, s[26:27] offset:40
	global_load_b128 v[4:7], v38, s[26:27]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_440
; %bb.439:                              ;   in Loop: Header=BB1_4 Depth=4
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[2:3], v[39:42], off offset:8
.LBB1_440:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[2:3], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v2
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v38
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v6, s20
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s22
	v_mov_b32_e32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_448
; %bb.441:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_444
; %bb.442:                              ; %.preheader1.i.i.i112.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s8, 0
.LBB1_443:                              ; %.preheader1.i.i.i112.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v38, v[0:3], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_443
.LBB1_444:                              ; %Flow940
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_446
; %bb.445:                              ;   in Loop: Header=BB1_4 Depth=4
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[37:38], off offset:8
.LBB1_446:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_448
; %bb.447:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b32 v37, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_448:                              ; %Flow941
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_449:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_451
; %bb.450:                              ;   in Loop: Header=BB1_449 Depth=5
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_451:                              ;   in Loop: Header=BB1_449 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_453
; %bb.452:                              ;   in Loop: Header=BB1_449 Depth=5
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_454
.LBB1_453:                              ;   in Loop: Header=BB1_449 Depth=5
	s_mov_b32 s1, -1
.LBB1_454:                              ; %Flow935
                                        ;   in Loop: Header=BB1_449 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_449
; %bb.455:                              ;   in Loop: Header=BB1_4 Depth=4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_459
; %bb.456:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x2
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27] offset:24 glc
	global_load_b64 v[4:5], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_459
; %bb.457:                              ; %.preheader.i.i.i111.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, 0
.LBB1_458:                              ; %.preheader.i.i.i111.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_458
.LBB1_459:                              ; %Flow933
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_460:                              ; %Flow966
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s35
	s_clause 0x1
	scratch_load_u8 v0, off, off offset:36
	scratch_load_u8 v1, off, off offset:28
	s_mov_b32 s35, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e64 v0, v1
	s_cbranch_execz .LBB1_612
; %bb.461:                              ; %.lr.ph224.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s1, 1
	s_mov_b32 s0, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
.LBB1_462:                              ; %.lr.ph224.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_and_b32_e32 v0, 0xff, v0
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u16_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB1_464
; %bb.463:                              ;   in Loop: Header=BB1_462 Depth=5
	s_add_i32 s6, s1, 36
	s_add_i32 s7, s1, 28
	scratch_load_u8 v0, off, s6
	scratch_load_u8 v1, off, s7
	s_and_not1_b32 s4, s4, exec_lo
	s_add_i32 s1, s1, 1
	s_and_not1_b32 s3, s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, v0, v1
	s_and_b32 s6, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s6
.LBB1_464:                              ; %Flow878
                                        ;   in Loop: Header=BB1_462 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s4
	s_or_b32 s0, s5, s0
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_462
; %bb.465:                              ; %loop.exit.guard793
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_612
; %bb.466:                              ;   in Loop: Header=BB1_4 Depth=4
	s_load_b64 s[26:27], s[18:19], 0x50
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_472
; %bb.467:                              ;   in Loop: Header=BB1_4 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[2:3], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[4:5], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v3
	v_and_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[2:3]
	s_cbranch_execz .LBB1_471
; %bb.468:                              ; %.preheader3.i.i.i122.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s3, 0
.LBB1_469:                              ; %.preheader3.i.i.i122.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v0, v2
	v_and_b32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 24, v[6:7]
	v_mov_b32_e32 v0, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[0:1]
	global_load_b64 v[0:1], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_469
; %bb.470:                              ; %Flow872
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_471:                              ; %Flow874
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_472:                              ; %.loopexit4.i.i.i116.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b128 v[0:3], v38, s[26:27]
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_474
; %bb.473:                              ;   in Loop: Header=BB1_4 Depth=4
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v5, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[4:5], v[39:42], off offset:8
.LBB1_474:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[4:5], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
	v_dual_mov_b32 v37, v38 :: v_dual_mov_b32 v2, s20
	v_dual_mov_b32 v39, v38 :: v_dual_mov_b32 v4, s22
	v_mov_b32_e32 v3, s21
	v_mov_b32_e32 v5, s23
	s_clause 0x3
	global_store_b128 v[6:7], v[36:39], off
	global_store_b128 v[6:7], v[2:5], off offset:16
	global_store_b128 v[6:7], v[2:5], off offset:32
	global_store_b128 v[6:7], v[2:5], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_482
; %bb.475:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	s_mov_b32 s5, exec_lo
	v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s3, v3
	v_and_b32_e32 v2, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v8, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[10:13], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_478
; %bb.476:                              ; %.preheader1.i.i.i120.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s8, 0
.LBB1_477:                              ; %.preheader1.i.i.i120.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_477
.LBB1_478:                              ; %Flow870
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_480
; %bb.479:                              ;   in Loop: Header=BB1_4 Depth=4
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_480:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_482
; %bb.481:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_482:                              ; %Flow871
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v0, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_483:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_485
; %bb.484:                              ;   in Loop: Header=BB1_483 Depth=5
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_485:                              ;   in Loop: Header=BB1_483 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_487
; %bb.486:                              ;   in Loop: Header=BB1_483 Depth=5
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_488
.LBB1_487:                              ;   in Loop: Header=BB1_483 Depth=5
	s_mov_b32 s1, -1
.LBB1_488:                              ; %Flow865
                                        ;   in Loop: Header=BB1_483 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_483
; %bb.489:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_493
; %bb.490:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x2
	global_load_b64 v[4:5], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27] offset:24 glc
	global_load_b64 v[6:7], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v10, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v2, v4
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v8
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v10, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v9
	global_store_b64 v[6:7], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_493
; %bb.491:                              ; %.preheader.i.i.i119.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, 0
.LBB1_492:                              ; %.preheader.i.i.i119.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
	v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_492
.LBB1_493:                              ; %__ockl_printf_begin.exit123.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	v_dual_mov_b32 v4, s24 :: v_dual_mov_b32 v5, v38
	v_mov_b32_e32 v6, v38
	s_mov_b64 s[8:9], s[18:19]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
	v_mov_b32_e32 v2, v46
	s_mov_b32 s0, 0
.LBB1_494:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, 1, v2
	scratch_load_u8 v3, v2, off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v3
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_494
; %bb.495:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s34
	s_cbranch_vccz .LBB1_582
; %bb.496:                              ;   in Loop: Header=BB1_4 Depth=4
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_mov_b32_e32 v28, 28
	s_mov_b32 s6, 0
	v_cndmask_b32_e32 v4, 0, v2, vcc_lo
	v_cndmask_b32_e64 v3, 0, s25, vcc_lo
	v_and_b32_e32 v2, -3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v4, vcc_lo, v4, 28
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s25, v3, vcc_lo
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v5, vcc_lo
.LBB1_497:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB1_500 Depth 6
                                        ;             Child Loop BB1_508 Depth 6
                                        ;             Child Loop BB1_516 Depth 6
                                        ;             Child Loop BB1_524 Depth 6
                                        ;             Child Loop BB1_532 Depth 6
                                        ;             Child Loop BB1_540 Depth 6
                                        ;             Child Loop BB1_548 Depth 6
                                        ;             Child Loop BB1_556 Depth 6
                                        ;             Child Loop BB1_564 Depth 6
                                        ;             Child Loop BB1_570 Depth 6
                                        ;             Child Loop BB1_579 Depth 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 56, v[22:23]
                                        ; implicit-def: $sgpr1
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v25, 0, v23 :: v_dual_cndmask_b32 v24, 56, v22
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_503
; %bb.498:                              ;   in Loop: Header=BB1_497 Depth=5
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB1_502
; %bb.499:                              ; %.preheader31.i124.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	v_lshlrev_b64 v[6:7], 3, v[24:25]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, v28
	v_mov_b32_e32 v5, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_500:                              ; %.preheader31.i124.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_u8 v8, v7, off
	v_mov_b32_e32 v9, s20
	v_add_nc_u32_e32 v7, 1, v7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0xffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], s0, v[8:9]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, s0, v6
	v_or_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_or_b32_e32 v4, v8, v4
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_500
; %bb.501:                              ; %Flow837
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_502:                              ; %Flow839
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
.LBB1_503:                              ; %Flow841
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v8, s1
	v_mov_b32_e32 v18, v28
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_505
; %bb.504:                              ;   in Loop: Header=BB1_497 Depth=5
	s_clause 0x5
	scratch_load_u8 v4, v28, off
	scratch_load_u8 v5, v28, off offset:1
	scratch_load_u8 v6, v28, off offset:2
	scratch_load_u8 v7, v28, off offset:3
	scratch_load_u8 v8, v28, off offset:5
	scratch_load_u8 v9, v28, off offset:4
	v_mov_b32_e32 v10, v38
	v_add_nc_u32_e32 v18, 8, v28
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v4, 0xffff, v4
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v5, 8, v5
	s_clause 0x1
	scratch_load_u8 v11, v28, off offset:7
	scratch_load_d16_hi_u8 v10, v28, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v6, 16, v6
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v7, 24, v7
	v_or_b32_e32 v4, v5, v4
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v5, 8, v8
	v_add_nc_u32_e32 v8, -8, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v4, v4, v6, v7
	s_waitcnt vmcnt(2)
	v_or3_b32 v5, 0, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v4, v4, 0, 0
	v_or3_b32 v4, v4, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v6, 24, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v5, v5, v10, v6
.LBB1_505:                              ; %.loopexit32.i125.i
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v8
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_511
; %bb.506:                              ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB1_510
; %bb.507:                              ; %.preheader29.i126.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_508:                              ; %.preheader29.i126.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v10, s20 :: v_dual_add_nc_u32 v9, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v8
	scratch_load_u8 v9, v9, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], s0, v[9:10]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v6, v9, v6
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_508
; %bb.509:                              ; %Flow832
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_510:                              ; %Flow834
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr8
.LBB1_511:                              ; %Flow836
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v10, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_513
; %bb.512:                              ;   in Loop: Header=BB1_497 Depth=5
	s_clause 0x5
	scratch_load_u8 v6, v18, off
	scratch_load_u8 v7, v18, off offset:1
	scratch_load_u8 v9, v18, off offset:2
	scratch_load_u8 v10, v18, off offset:3
	scratch_load_u8 v11, v18, off offset:5
	scratch_load_u8 v12, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v13, v38 :: v_dual_and_b32 v6, 0xffff, v6
	s_clause 0x1
	scratch_load_u8 v14, v18, off offset:7
	scratch_load_d16_hi_u8 v13, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v7, 8, v7
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v10, 24, v10
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v6, v7, v6
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v7, 8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v6, v6, v9, v10
	s_waitcnt vmcnt(2)
	v_or3_b32 v7, 0, v12, v7
	v_add_nc_u32_e32 v10, -8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v6, v6, 0, 0
	v_or3_b32 v6, v6, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v7, v7, v13, v9
.LBB1_513:                              ; %.loopexit30.i127.i
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v10
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_519
; %bb.514:                              ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB1_518
; %bb.515:                              ; %.preheader27.i128.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_516:                              ; %.preheader27.i128.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v12, s20 :: v_dual_add_nc_u32 v11, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v10
	scratch_load_u8 v11, v11, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, 0xffff, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], s0, v[11:12]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v9, v12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v8, v11, v8
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_516
; %bb.517:                              ; %Flow827
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_518:                              ; %Flow829
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr10
.LBB1_519:                              ; %Flow831
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v12, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_521
; %bb.520:                              ;   in Loop: Header=BB1_497 Depth=5
	s_clause 0x5
	scratch_load_u8 v8, v18, off
	scratch_load_u8 v9, v18, off offset:1
	scratch_load_u8 v11, v18, off offset:2
	scratch_load_u8 v12, v18, off offset:3
	scratch_load_u8 v13, v18, off offset:5
	scratch_load_u8 v14, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v15, v38 :: v_dual_and_b32 v8, 0xffff, v8
	s_clause 0x1
	scratch_load_u8 v16, v18, off offset:7
	scratch_load_d16_hi_u8 v15, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v9, 8, v9
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v11, 16, v11
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v12, 24, v12
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v8, v9, v8
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v9, 8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v8, v8, v11, v12
	s_waitcnt vmcnt(2)
	v_or3_b32 v9, 0, v14, v9
	v_add_nc_u32_e32 v12, -8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v8, v8, 0, 0
	v_or3_b32 v8, v8, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v11, 24, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v9, v9, v15, v11
.LBB1_521:                              ; %.loopexit28.i129.i
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v12
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_527
; %bb.522:                              ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v12
	s_cbranch_execz .LBB1_526
; %bb.523:                              ; %.preheader25.i130.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_524:                              ; %.preheader25.i130.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v14, s20 :: v_dual_add_nc_u32 v13, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v12
	scratch_load_u8 v13, v13, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0xffff, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], s0, v[13:14]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v10, v13, v10
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_524
; %bb.525:                              ; %Flow822
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_526:                              ; %Flow824
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr12
.LBB1_527:                              ; %Flow826
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v14, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_529
; %bb.528:                              ;   in Loop: Header=BB1_497 Depth=5
	s_clause 0x5
	scratch_load_u8 v10, v18, off
	scratch_load_u8 v11, v18, off offset:1
	scratch_load_u8 v13, v18, off offset:2
	scratch_load_u8 v14, v18, off offset:3
	scratch_load_u8 v15, v18, off offset:5
	scratch_load_u8 v16, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v17, v38 :: v_dual_and_b32 v10, 0xffff, v10
	s_clause 0x1
	scratch_load_u8 v19, v18, off offset:7
	scratch_load_d16_hi_u8 v17, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v11, 8, v11
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v13, 16, v13
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v10, v11, v10
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v11, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v10, v10, v13, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v11, 0, v16, v11
	v_add_nc_u32_e32 v14, -8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v10, v10, 0, 0
	v_or3_b32 v10, v10, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v13, 24, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v11, v11, v17, v13
.LBB1_529:                              ; %.loopexit26.i131.i
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v14
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_535
; %bb.530:                              ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v14
	s_cbranch_execz .LBB1_534
; %bb.531:                              ; %.preheader23.i132.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_532:                              ; %.preheader23.i132.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v16, s20 :: v_dual_add_nc_u32 v15, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v14
	scratch_load_u8 v15, v15, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], s0, v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v15, v12
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_532
; %bb.533:                              ; %Flow817
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_534:                              ; %Flow819
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr14
.LBB1_535:                              ; %Flow821
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v16, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_537
; %bb.536:                              ;   in Loop: Header=BB1_497 Depth=5
	s_clause 0x5
	scratch_load_u8 v12, v18, off
	scratch_load_u8 v13, v18, off offset:1
	scratch_load_u8 v15, v18, off offset:2
	scratch_load_u8 v16, v18, off offset:3
	scratch_load_u8 v17, v18, off offset:5
	scratch_load_u8 v19, v18, off offset:4
	v_mov_b32_e32 v20, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v12, 0xffff, v12
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v13, 8, v13
	s_clause 0x1
	scratch_load_u8 v21, v18, off offset:7
	scratch_load_d16_hi_u8 v20, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v15, 16, v15
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v16, 24, v16
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v12, v13, v12
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v13, 8, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v12, v12, v15, v16
	s_waitcnt vmcnt(2)
	v_or3_b32 v13, 0, v19, v13
	v_add_nc_u32_e32 v16, -8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v12, v12, 0, 0
	v_or3_b32 v12, v12, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v15, 24, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v13, v13, v20, v15
.LBB1_537:                              ; %.loopexit24.i133.i
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v16
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_543
; %bb.538:                              ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v16
	s_cbranch_execz .LBB1_542
; %bb.539:                              ; %.preheader21.i134.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB1_540:                              ; %.preheader21.i134.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v20, s20 :: v_dual_add_nc_u32 v17, s5, v18
	s_add_i32 s5, s5, 1
	v_cmp_eq_u32_e32 vcc_lo, s5, v16
	scratch_load_u8 v17, v17, off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v19, 0xffff, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], s0, v[19:20]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	v_or_b32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v19, v14
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_540
; %bb.541:                              ; %Flow812
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_542:                              ; %Flow814
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr16
.LBB1_543:                              ; %Flow816
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_saveexec_b32 s0, s2
	v_mov_b32_e32 v19, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_545
; %bb.544:                              ;   in Loop: Header=BB1_497 Depth=5
	s_clause 0x5
	scratch_load_u8 v14, v18, off
	scratch_load_u8 v15, v18, off offset:1
	scratch_load_u8 v17, v18, off offset:2
	scratch_load_u8 v19, v18, off offset:3
	scratch_load_u8 v20, v18, off offset:5
	scratch_load_u8 v21, v18, off offset:4
	v_mov_b32_e32 v26, v38
	s_waitcnt vmcnt(5)
	v_and_b32_e32 v14, 0xffff, v14
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v15, 8, v15
	s_clause 0x1
	scratch_load_u8 v27, v18, off offset:7
	scratch_load_d16_hi_u8 v26, v18, off offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v17, 16, v17
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_nc_u32_e32 v18, 8, v18
	v_or_b32_e32 v14, v15, v14
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v14, v14, v17, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v15, 0, v21, v15
	v_add_nc_u32_e32 v19, -8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v14, v14, 0, 0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v17, 24, v27
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v15, v26, v17
.LBB1_545:                              ; %.loopexit22.i135.i
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v19
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_551
; %bb.546:                              ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0, v19
	s_cbranch_execz .LBB1_550
; %bb.547:                              ; %.preheader.i136.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s4, 0
.LBB1_548:                              ; %.preheader.i136.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	scratch_load_u8 v20, v18, off
	v_mov_b32_e32 v21, s20
	v_add_nc_u32_e32 v19, -1, v19
	v_add_nc_u32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v20, 0xffff, v20
	v_lshlrev_b64 v[20:21], s0, v[20:21]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v17, v21, v17
	v_or_b32_e32 v16, v20, v16
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_548
; %bb.549:                              ; %Flow807
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_550:                              ; %Flow809
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr18
.LBB1_551:                              ; %Flow811
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_553
; %bb.552:                              ;   in Loop: Header=BB1_497 Depth=5
	s_clause 0x5
	scratch_load_u8 v16, v18, off
	scratch_load_u8 v17, v18, off offset:1
	scratch_load_u8 v19, v18, off offset:2
	scratch_load_u8 v20, v18, off offset:3
	scratch_load_u8 v21, v18, off offset:5
	scratch_load_u8 v26, v18, off offset:4
	s_waitcnt vmcnt(5)
	v_dual_mov_b32 v27, v38 :: v_dual_and_b32 v16, 0xffff, v16
	s_clause 0x1
	scratch_load_u8 v29, v18, off offset:7
	scratch_load_d16_hi_u8 v27, v18, off offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v17, 8, v17
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v19
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v19, 8, v21
	v_or_b32_e32 v16, v17, v16
	v_lshlrev_b32_e32 v17, 24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_or3_b32 v16, v16, v18, v17
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v26, v19
	v_or3_b32 v16, v16, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v29
	s_waitcnt vmcnt(0)
	v_or3_b32 v17, v17, v27, v18
.LBB1_553:                              ; %.loopexit.i137.i
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v26, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v27, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_559
; %bb.554:                              ;   in Loop: Header=BB1_497 Depth=5
	global_load_b64 v[20:21], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[26:27], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v19, v19, v21
	v_and_b32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v19, 24
	v_mul_hi_u32 v29, v18, 24
	v_mul_lo_u32 v18, v18, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v29, v19
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, v27, v19, vcc_lo
	global_load_b64 v[18:19], v[18:19], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[26:27], v[20:21]
	s_cbranch_execz .LBB1_558
; %bb.555:                              ; %.preheader3.i.i19.i144.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_mov_b32 s3, 0
.LBB1_556:                              ; %.preheader3.i.i19.i144.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v38, s[26:27] offset:40
	global_load_b64 v[29:30], v38, s[26:27]
	v_dual_mov_b32 v20, v26 :: v_dual_mov_b32 v21, v27
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, v18, v20
	v_and_b32_e32 v19, v19, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v18, 24, v[29:30]
	v_mov_b32_e32 v18, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, v19, 24, v[18:19]
	v_mov_b32_e32 v27, v29
	global_load_b64 v[18:19], v[26:27], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[26:27], v38, v[18:21], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[20:21]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_556
; %bb.557:                              ; %Flow804
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_558:                              ; %Flow806
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_559:                              ; %.loopexit4.i.i14.i138.i
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v38, s[26:27] offset:40
	global_load_b128 v[18:21], v38, s[26:27]
	v_readfirstlane_b32 s2, v26
	v_readfirstlane_b32 s3, v27
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v29
	v_readfirstlane_b32 s5, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s7, s4, 24
	s_mul_i32 s8, s4, 24
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_561
; %bb.560:                              ;   in Loop: Header=BB1_497 Depth=5
	s_add_i32 s11, s7, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v19, vcc_lo
	v_dual_mov_b32 v39, s9 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[26:27], v[39:42], off offset:8
.LBB1_561:                              ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s10
	v_cmp_lt_u64_e32 vcc_lo, 56, v[22:23]
	v_or_b32_e32 v26, 2, v2
	v_lshl_add_u32 v27, v24, 2, 28
	s_lshl_b64 s[4:5], s[4:5], 12
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v26, v2 :: v_dual_and_b32 v29, 0x1e0, v27
	v_lshlrev_b64 v[26:27], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v20, vcc_lo, v20, s4
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_and_or_b32 v2, 0xffffff1f, v2, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, v20, v26
	v_add_co_ci_u32_e32 v21, vcc_lo, v21, v27, vcc_lo
	s_clause 0x3
	global_store_b128 v[20:21], v[2:5], off
	global_store_b128 v[20:21], v[6:9], off offset:16
	global_store_b128 v[20:21], v[10:13], off offset:32
	global_store_b128 v[20:21], v[14:17], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_569
; %bb.562:                              ;   in Loop: Header=BB1_497 Depth=5
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v2
	v_readfirstlane_b32 s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[2:3]
	s_mul_i32 s5, s11, 24
	s_mul_hi_u32 s9, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v19, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[10:11]
	s_cbranch_execz .LBB1_565
; %bb.563:                              ; %.preheader1.i.i17.i142.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_mov_b32 s9, 0
.LBB1_564:                              ; %.preheader1.i.i17.i142.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_564
.LBB1_565:                              ; %Flow802
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[2:3], v38, s[26:27] offset:16
	s_mov_b32 s9, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v4, s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_567
; %bb.566:                              ;   in Loop: Header=BB1_497 Depth=5
	s_bcnt1_i32_b32 s9, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s9
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[37:38], off offset:8
.LBB1_567:                              ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_569
; %bb.568:                              ;   in Loop: Header=BB1_497 Depth=5
	global_load_b32 v37, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_569:                              ; %Flow803
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s7, s7, s1
	v_add_co_u32 v2, vcc_lo, v18, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_570:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_572
; %bb.571:                              ;   in Loop: Header=BB1_570 Depth=6
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_572:                              ;   in Loop: Header=BB1_570 Depth=6
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_574
; %bb.573:                              ;   in Loop: Header=BB1_570 Depth=6
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_575
.LBB1_574:                              ;   in Loop: Header=BB1_570 Depth=6
	s_mov_b32 s1, -1
.LBB1_575:                              ; %Flow797
                                        ;   in Loop: Header=BB1_570 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_570
; %bb.576:                              ;   in Loop: Header=BB1_497 Depth=5
	global_load_b128 v[2:5], v[20:21], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_580
; %bb.577:                              ;   in Loop: Header=BB1_497 Depth=5
	s_clause 0x2
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[10:11], v38, s[26:27] offset:24 glc
	global_load_b64 v[8:9], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v12, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v4, v6
	v_mul_hi_u32 v12, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v10
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v11
	global_store_b64 v[8:9], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_580
; %bb.578:                              ; %.preheader.i.i16.i141.i.preheader
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_mov_b32 s0, 0
.LBB1_579:                              ; %.preheader.i.i16.i141.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ;           Parent Loop BB1_497 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v38, v[4:7], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]
	v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_579
.LBB1_580:                              ; %__ockl_hostcall_preview.exit20.i140.i
                                        ;   in Loop: Header=BB1_497 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v22, vcc_lo, v22, v24
	v_sub_co_ci_u32_e32 v23, vcc_lo, v23, v25, vcc_lo
	v_add_nc_u32_e32 v28, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[22:23]
	s_or_b32 s6, vcc_lo, s6
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_497
; %bb.581:                              ; %Flow842
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, 0
	s_branch .LBB1_583
.LBB1_582:                              ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, -1
.LBB1_583:                              ; %Flow859
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_612
; %bb.584:                              ;   in Loop: Header=BB1_4 Depth=4
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v37, v56 :: v_dual_mov_b32 v2, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v3, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_590
; %bb.585:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b64 v[4:5], v38, s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27]
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v5
	v_and_b32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB1_589
; %bb.586:                              ; %.preheader3.i.i.i151.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s3, 0
.LBB1_587:                              ; %.preheader3.i.i.i151.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v38, s[26:27] offset:40
	global_load_b64 v[8:9], v38, s[26:27]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]
	v_and_b32_e32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]
	v_mov_b32_e32 v3, v6
	global_load_b64 v[2:3], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v38, v[2:5], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_587
; %bb.588:                              ; %Flow855
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_589:                              ; %Flow857
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_590:                              ; %.loopexit4.i.i.i145.i
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v38, s[26:27] offset:40
	global_load_b128 v[4:7], v38, s[26:27]
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[4:5], s[2:3], s[4:5]
	s_mul_i32 s1, s5, 24
	s_mul_hi_u32 s6, s4, 24
	s_mul_i32 s7, s4, 24
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_592
; %bb.591:                              ;   in Loop: Header=BB1_4 Depth=4
	s_add_i32 s10, s6, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v3, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v39, s8 :: v_dual_mov_b32 v40, v38
	global_store_b128 v[2:3], v[39:42], off offset:8
.LBB1_592:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s9
	s_lshl_b64 s[4:5], s[4:5], 12
	v_lshlrev_b64 v[2:3], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s21, s20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v2
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo
	v_mov_b32_e32 v2, v38
	v_dual_mov_b32 v3, v38 :: v_dual_mov_b32 v6, s20
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s22
	v_mov_b32_e32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB1_600
; %bb.593:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x1
	global_load_b64 v[10:11], v38, s[26:27] offset:32 glc
	global_load_b64 v[0:1], v38, s[26:27] offset:40
	v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v9, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[8:9], s[2:3]
	s_mul_i32 s5, s9, 24
	s_mul_hi_u32 s9, s8, 24
	s_mul_i32 s8, s8, 24
	s_add_i32 s9, s9, s5
	v_add_co_u32 v6, vcc_lo, v4, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v5, vcc_lo
	s_mov_b32 s5, exec_lo
	global_store_b64 v[6:7], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[8:11], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[10:11]
	s_cbranch_execz .LBB1_596
; %bb.594:                              ; %.preheader1.i.i.i149.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s8, 0
.LBB1_595:                              ; %.preheader1.i.i.i149.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v38, v[0:3], s[26:27] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB1_595
.LBB1_596:                              ; %Flow853
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b64 v[0:1], v38, s[26:27] offset:16
	s_mov_b32 s8, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v2, s8, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_598
; %bb.597:                              ;   in Loop: Header=BB1_4 Depth=4
	s_bcnt1_i32_b32 s8, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s8
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[37:38], off offset:8
.LBB1_598:                              ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_600
; %bb.599:                              ;   in Loop: Header=BB1_4 Depth=4
	global_load_b32 v37, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s5, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[37:38], off
	s_and_b32 m0, s5, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_600:                              ; %Flow854
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s6, s6, s1
	v_add_co_u32 v0, vcc_lo, v4, s7
	v_add_co_ci_u32_e32 v1, vcc_lo, s6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_601:                              ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_603
; %bb.602:                              ;   in Loop: Header=BB1_601 Depth=5
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_603:                              ;   in Loop: Header=BB1_601 Depth=5
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_605
; %bb.604:                              ;   in Loop: Header=BB1_601 Depth=5
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_606
.LBB1_605:                              ;   in Loop: Header=BB1_601 Depth=5
	s_mov_b32 s1, -1
.LBB1_606:                              ; %Flow848
                                        ;   in Loop: Header=BB1_601 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_601
; %bb.607:                              ;   in Loop: Header=BB1_4 Depth=4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_611
; %bb.608:                              ;   in Loop: Header=BB1_4 Depth=4
	s_clause 0x2
	global_load_b64 v[2:3], v38, s[26:27] offset:40
	global_load_b64 v[6:7], v38, s[26:27] offset:24 glc
	global_load_b64 v[4:5], v38, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v8, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v0, v0, v8
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v0, v2
	v_mul_hi_u32 v8, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v6
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v7
	global_store_b64 v[4:5], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[6:7]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_611
; %bb.609:                              ; %.preheader.i.i.i148.i.preheader
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_mov_b32 s0, 0
.LBB1_610:                              ; %.preheader.i.i.i148.i
                                        ;   Parent Loop BB1_1 Depth=1
                                        ;     Parent Loop BB1_2 Depth=2
                                        ;       Parent Loop BB1_3 Depth=3
                                        ;         Parent Loop BB1_4 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v38, v[0:3], s[26:27] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_610
.LBB1_611:                              ; %Flow846
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_612:                              ; %Flow879
                                        ;   in Loop: Header=BB1_4 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s35
	v_and_b32_e32 v0, 0xff, v59
	v_cmp_gt_u16_e32 vcc_lo, 57, v0
	v_add_nc_u16 v59, v0, 1
	s_cbranch_vccnz .LBB1_4
; %bb.613:                              ;   in Loop: Header=BB1_3 Depth=3
	v_and_b32_e32 v0, 0xff, v58
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u16_e32 vcc_lo, 57, v0
	v_add_nc_u16 v58, v0, 1
	s_cbranch_vccnz .LBB1_3
; %bb.614:                              ;   in Loop: Header=BB1_2 Depth=2
	v_and_b32_e32 v0, 0xff, v57
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u16_e32 vcc_lo, 57, v0
	v_add_nc_u16 v57, v0, 1
	s_cbranch_vccnz .LBB1_2
; %bb.615:                              ;   in Loop: Header=BB1_1 Depth=1
	v_and_b32_e32 v0, 0xff, v50
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u16_e32 vcc_lo, 57, v0
	v_add_nc_u16 v50, v0, 1
	s_cbranch_vccnz .LBB1_1
; %bb.616:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 48
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 60
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6kernelv, .Lfunc_end1-_Z6kernelv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 28996
; NumSgprs: 38
; NumVgprs: 60
; ScratchSize: 48
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 60
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"***match found*** %s\n"
	.size	.str, 22

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         80
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelv
    .private_segment_fixed_size: 48
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     60
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
