/* 
    @Author:    3sne ( Mukur Panchani )
    @FileName:  q2MatrixSummer.cu
    @Task:      CUDA program compute sums of two matrices, using different parallelism techniques.
 */

#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>

__global__ void addMatRowThreads(int *a, int *b, int *c, int m, int n) {
    
    int id = threadIdx.x;
    for ( int i = 0; i < n; i++ ) {
        int ind = id * n + i;
        c[ind] = a[ind] + b[ind];
    }

}

__global__ void addMatColThreads(int *a, int *b, int *c, int m, int n) {
    
    int id = threadIdx.x;
    for ( int i = 0; i < m; i++ ) {
        int ind = i * n + id;
        c[ind] = a[ind] + b[ind];
    }

}

__global__ void addMatElementThread(int *a, int *b, int *c, int m, int n) {

    int ci = threadIdx.x;
    int ri = threadIdx.y;
    int id = ri * m + ci;
    c[id] = a[id] + b[id]; 

}

int main() {
    int *matA, *matB, *matC;
    int *da, *db, *dc;
    int m, n;
    printf("== Enter Dimension of Matrix A and B (m x n) ==\n");
    printf("m >> "); scanf("%d", &m);
    printf("n >> "); scanf("%d", &n);

    matA = (int*)malloc(sizeof(int) * m * n);
    matB = (int*)malloc(sizeof(int) * m * n);
    matC = (int*)malloc(sizeof(int) * m * n);

    printf("== Matrix A Elements ==\n");
    for(int i = 0; i < m * n; i++) {
        scanf("%d", &matA[i]);
    }
    printf("== Matrix B Elements ==\n");
    for(int i = 0; i < m * n; i++) {
        scanf("%d", &matB[i]);
    }

    cudaMalloc((void **) &da, sizeof(int) * m * n);
    cudaMalloc((void **) &db, sizeof(int) * m * n);
    cudaMalloc((void **) &dc, sizeof(int) * m * n);

    cudaMemcpy(da, matA, sizeof(int) * m * n, cudaMemcpyHostToDevice);
    cudaMemcpy(db, matB, sizeof(int) * m * n, cudaMemcpyHostToDevice);

    printf("\nChoose a degree of parallelism >> \n");
    printf("1. Thread handles row\n");
    printf("2. Thread handles column\n");
    printf("3. Thread handles element\nChoice >> ");
    int choice = 0;
    scanf("%d", &choice);
    dim3 block_conf (n, m);
    switch(choice) {
        case 1://Part A: 1 Thread handles 1 row >>
            printf("Chose: Thread handles row\n");
            addMatRowThreads<<<1,m>>>(da, db, dc, m, n);
            break;

        case 2://Part B: 1 Thread handles 1 column >>
            printf("Chose: Thread handles column\n");
            addMatColThreads<<<1,n>>>(da, db, dc, m, n);
            break;

        case 3://Part C: 1 Thread handles 1 element >>
            printf("Chose: Thread handles element\n");
            addMatElementThread<<<1, block_conf>>>(da, db, dc, m, n);
            break;

        default: 
            printf("Bad Option, exiting ...\n");
            exit(EXIT_FAILURE);
            break;
    }

    cudaMemcpy(matC, dc, sizeof(int) * m * n, cudaMemcpyDeviceToHost);
    printf("== Matrix C Elements (computed by choice %d)==\n", choice);
    for ( int i = 0; i < m; i++ ) {
        for ( int j = 0; j < n; j++ ) {
            printf("%d ", matC[i * n + j]);
        }
        printf("\n");
    }

    cudaFree(da);
    cudaFree(db);
    cudaFree(dc);
    free(matA);
    free(matB);
    free(matC);

    return 0;

}
	.file	"tmpxft_002040fd_00000000-6_q2MatrixSummer.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z16addMatRowThreadsPiS_S_iiPiS_S_ii
	.type	_Z42__device_stub__Z16addMatRowThreadsPiS_S_iiPiS_S_ii, @function
_Z42__device_stub__Z16addMatRowThreadsPiS_S_iiPiS_S_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16addMatRowThreadsPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z42__device_stub__Z16addMatRowThreadsPiS_S_iiPiS_S_ii, .-_Z42__device_stub__Z16addMatRowThreadsPiS_S_iiPiS_S_ii
	.globl	_Z16addMatRowThreadsPiS_S_ii
	.type	_Z16addMatRowThreadsPiS_S_ii, @function
_Z16addMatRowThreadsPiS_S_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z16addMatRowThreadsPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE2053:
	.size	_Z16addMatRowThreadsPiS_S_ii, .-_Z16addMatRowThreadsPiS_S_ii
	.globl	_Z42__device_stub__Z16addMatColThreadsPiS_S_iiPiS_S_ii
	.type	_Z42__device_stub__Z16addMatColThreadsPiS_S_iiPiS_S_ii, @function
_Z42__device_stub__Z16addMatColThreadsPiS_S_iiPiS_S_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16addMatColThreadsPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z42__device_stub__Z16addMatColThreadsPiS_S_iiPiS_S_ii, .-_Z42__device_stub__Z16addMatColThreadsPiS_S_iiPiS_S_ii
	.globl	_Z16addMatColThreadsPiS_S_ii
	.type	_Z16addMatColThreadsPiS_S_ii, @function
_Z16addMatColThreadsPiS_S_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z16addMatColThreadsPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE2055:
	.size	_Z16addMatColThreadsPiS_S_ii, .-_Z16addMatColThreadsPiS_S_ii
	.globl	_Z45__device_stub__Z19addMatElementThreadPiS_S_iiPiS_S_ii
	.type	_Z45__device_stub__Z19addMatElementThreadPiS_S_iiPiS_S_ii, @function
_Z45__device_stub__Z19addMatElementThreadPiS_S_iiPiS_S_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19addMatElementThreadPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z45__device_stub__Z19addMatElementThreadPiS_S_iiPiS_S_ii, .-_Z45__device_stub__Z19addMatElementThreadPiS_S_iiPiS_S_ii
	.globl	_Z19addMatElementThreadPiS_S_ii
	.type	_Z19addMatElementThreadPiS_S_ii, @function
_Z19addMatElementThreadPiS_S_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z19addMatElementThreadPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE2057:
	.size	_Z19addMatElementThreadPiS_S_ii, .-_Z19addMatElementThreadPiS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"== Enter Dimension of Matrix A and B (m x n) ==\n"
.LC1:
	.string	"m >> "
.LC2:
	.string	"%d"
.LC3:
	.string	"n >> "
.LC4:
	.string	"== Matrix A Elements ==\n"
.LC5:
	.string	"== Matrix B Elements ==\n"
.LC6:
	.string	"\nChoose a degree of parallelism >> \n"
.LC7:
	.string	"1. Thread handles row\n"
.LC8:
	.string	"2. Thread handles column\n"
.LC9:
	.string	"3. Thread handles element\nChoice >> "
.LC10:
	.string	"Chose: Thread handles row\n"
.LC11:
	.string	"Chose: Thread handles column\n"
.LC12:
	.string	"Chose: Thread handles element\n"
.LC13:
	.string	"Bad Option, exiting ...\n"
.LC14:
	.string	"== Matrix C Elements (computed by choice %d)==\n"
.LC15:
	.string	"%d "
.LC16:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	leaq	.LC2(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	12(%rsp), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	16(%rsp), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movslq	12(%rsp), %rbx
	movslq	16(%rsp), %rax
	imulq	%rax, %rbx
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%r12, %r15
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L19:
	movl	12(%rsp), %eax
	imull	16(%rsp), %eax
	cmpl	%r14d, %eax
	jle	.L36
	movq	%r15, %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	incl	%r14d
	call	__isoc23_scanf@PLT
	addq	$4, %r15
	jmp	.L19
.L36:
	leaq	.LC5(%rip), %rsi
	xorl	%eax, %eax
	movq	%rbp, %r15
	xorl	%r14d, %r14d
	movl	$2, %edi
	call	__printf_chk@PLT
.L21:
	movslq	12(%rsp), %rsi
	movslq	16(%rsp), %rax
	movl	%esi, %edx
	imull	%eax, %edx
	cmpl	%r14d, %edx
	jle	.L37
	movq	%r15, %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	incl	%r14d
	call	__isoc23_scanf@PLT
	addq	$4, %r15
	jmp	.L21
.L37:
	imulq	%rax, %rsi
	leaq	24(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	12(%rsp), %rsi
	movslq	16(%rsp), %rax
	leaq	32(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	12(%rsp), %rsi
	movslq	16(%rsp), %rax
	leaq	40(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	12(%rsp), %rdx
	movslq	16(%rsp), %rax
	movq	%r12, %rsi
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	12(%rsp), %rdx
	movslq	16(%rsp), %rax
	movq	%rbp, %rsi
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	leaq	20(%rsp), %rsi
	movq	%r13, %rdi
	movl	%eax, 20(%rsp)
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movl	16(%rsp), %eax
	movl	$1, 60(%rsp)
	movl	%eax, 52(%rsp)
	movl	12(%rsp), %eax
	movl	%eax, 56(%rsp)
	movl	20(%rsp), %eax
	cmpl	$2, %eax
	je	.L23
	cmpl	$3, %eax
	je	.L24
	decl	%eax
	jne	.L25
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	12(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 72(%rsp)
	movq	%rdi, 80(%rsp)
	movl	84(%rsp), %ecx
	movl	%eax, 76(%rsp)
	movq	76(%rsp), %rdx
	movq	%rdi, 64(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movl	16(%rsp), %r8d
	movl	12(%rsp), %ecx
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z42__device_stub__Z16addMatRowThreadsPiS_S_iiPiS_S_ii
	jmp	.L27
.L23:
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	16(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 72(%rsp)
	movq	%rdi, 80(%rsp)
	movl	84(%rsp), %ecx
	movl	%eax, 76(%rsp)
	movq	76(%rsp), %rdx
	movq	%rdi, 64(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movl	16(%rsp), %r8d
	movl	12(%rsp), %ecx
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z42__device_stub__Z16addMatColThreadsPiS_S_iiPiS_S_ii
	jmp	.L27
.L24:
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	60(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 84(%rsp)
	movq	%rdi, 76(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movl	16(%rsp), %r8d
	movl	12(%rsp), %ecx
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z45__device_stub__Z19addMatElementThreadPiS_S_iiPiS_S_ii
	jmp	.L27
.L25:
	movl	$2, %edi
	leaq	.LC13(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L27:
	movslq	12(%rsp), %rdx
	movslq	16(%rsp), %rax
	movq	%rbx, %rdi
	xorl	%r14d, %r14d
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	leaq	.LC15(%rip), %r13
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	20(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC14(%rip), %rsi
	call	__printf_chk@PLT
.L30:
	cmpl	%r14d, 12(%rsp)
	jle	.L38
	xorl	%r15d, %r15d
.L32:
	movl	16(%rsp), %eax
	cmpl	%r15d, %eax
	jle	.L39
	imull	%r14d, %eax
	movq	%r13, %rsi
	movl	$2, %edi
	addl	%r15d, %eax
	incl	%r15d
	cltq
	movl	(%rbx,%rax,4), %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L32
.L39:
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incl	%r14d
	call	__printf_chk@PLT
	jmp	.L30
.L38:
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC17:
	.string	"_Z19addMatElementThreadPiS_S_ii"
.LC18:
	.string	"_Z16addMatColThreadsPiS_S_ii"
.LC19:
	.string	"_Z16addMatRowThreadsPiS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z19addMatElementThreadPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16addMatColThreadsPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16addMatRowThreadsPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* 
    @Author:    3sne ( Mukur Panchani )
    @FileName:  q2MatrixSummer.cu
    @Task:      CUDA program compute sums of two matrices, using different parallelism techniques.
 */

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>

__global__ void addMatRowThreads(int *a, int *b, int *c, int m, int n) {
    
    int id = threadIdx.x;
    for ( int i = 0; i < n; i++ ) {
        int ind = id * n + i;
        c[ind] = a[ind] + b[ind];
    }

}

__global__ void addMatColThreads(int *a, int *b, int *c, int m, int n) {
    
    int id = threadIdx.x;
    for ( int i = 0; i < m; i++ ) {
        int ind = i * n + id;
        c[ind] = a[ind] + b[ind];
    }

}

__global__ void addMatElementThread(int *a, int *b, int *c, int m, int n) {

    int ci = threadIdx.x;
    int ri = threadIdx.y;
    int id = ri * m + ci;
    c[id] = a[id] + b[id]; 

}

int main() {
    int *matA, *matB, *matC;
    int *da, *db, *dc;
    int m, n;
    printf("== Enter Dimension of Matrix A and B (m x n) ==\n");
    printf("m >> "); scanf("%d", &m);
    printf("n >> "); scanf("%d", &n);

    matA = (int*)malloc(sizeof(int) * m * n);
    matB = (int*)malloc(sizeof(int) * m * n);
    matC = (int*)malloc(sizeof(int) * m * n);

    printf("== Matrix A Elements ==\n");
    for(int i = 0; i < m * n; i++) {
        scanf("%d", &matA[i]);
    }
    printf("== Matrix B Elements ==\n");
    for(int i = 0; i < m * n; i++) {
        scanf("%d", &matB[i]);
    }

    hipMalloc((void **) &da, sizeof(int) * m * n);
    hipMalloc((void **) &db, sizeof(int) * m * n);
    hipMalloc((void **) &dc, sizeof(int) * m * n);

    hipMemcpy(da, matA, sizeof(int) * m * n, hipMemcpyHostToDevice);
    hipMemcpy(db, matB, sizeof(int) * m * n, hipMemcpyHostToDevice);

    printf("\nChoose a degree of parallelism >> \n");
    printf("1. Thread handles row\n");
    printf("2. Thread handles column\n");
    printf("3. Thread handles element\nChoice >> ");
    int choice = 0;
    scanf("%d", &choice);
    dim3 block_conf (n, m);
    switch(choice) {
        case 1://Part A: 1 Thread handles 1 row >>
            printf("Chose: Thread handles row\n");
            addMatRowThreads<<<1,m>>>(da, db, dc, m, n);
            break;

        case 2://Part B: 1 Thread handles 1 column >>
            printf("Chose: Thread handles column\n");
            addMatColThreads<<<1,n>>>(da, db, dc, m, n);
            break;

        case 3://Part C: 1 Thread handles 1 element >>
            printf("Chose: Thread handles element\n");
            addMatElementThread<<<1, block_conf>>>(da, db, dc, m, n);
            break;

        default: 
            printf("Bad Option, exiting ...\n");
            exit(EXIT_FAILURE);
            break;
    }

    hipMemcpy(matC, dc, sizeof(int) * m * n, hipMemcpyDeviceToHost);
    printf("== Matrix C Elements (computed by choice %d)==\n", choice);
    for ( int i = 0; i < m; i++ ) {
        for ( int j = 0; j < n; j++ ) {
            printf("%d ", matC[i * n + j]);
        }
        printf("\n");
    }

    hipFree(da);
    hipFree(db);
    hipFree(dc);
    free(matA);
    free(matB);
    free(matC);

    return 0;

}
	.text
	.file	"q2MatrixSummer.hip"
	.globl	_Z31__device_stub__addMatRowThreadsPiS_S_ii # -- Begin function _Z31__device_stub__addMatRowThreadsPiS_S_ii
	.type	_Z31__device_stub__addMatRowThreadsPiS_S_ii,@function
_Z31__device_stub__addMatRowThreadsPiS_S_ii: # @_Z31__device_stub__addMatRowThreadsPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16addMatRowThreadsPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__addMatRowThreadsPiS_S_ii, .Lfunc_end0-_Z31__device_stub__addMatRowThreadsPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__addMatColThreadsPiS_S_ii # -- Begin function _Z31__device_stub__addMatColThreadsPiS_S_ii
	.type	_Z31__device_stub__addMatColThreadsPiS_S_ii,@function
_Z31__device_stub__addMatColThreadsPiS_S_ii: # @_Z31__device_stub__addMatColThreadsPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16addMatColThreadsPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z31__device_stub__addMatColThreadsPiS_S_ii, .Lfunc_end1-_Z31__device_stub__addMatColThreadsPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__addMatElementThreadPiS_S_ii # -- Begin function _Z34__device_stub__addMatElementThreadPiS_S_ii
	.type	_Z34__device_stub__addMatElementThreadPiS_S_ii,@function
_Z34__device_stub__addMatElementThreadPiS_S_ii: # @_Z34__device_stub__addMatElementThreadPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19addMatElementThreadPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z34__device_stub__addMatElementThreadPiS_S_ii, .Lfunc_end2-_Z34__device_stub__addMatElementThreadPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	4(%rsp), %r12
	movl	$.L.str.2, %edi
	movq	%r12, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movq	%rsp, %r13
	movl	$.L.str.2, %edi
	movq	%r13, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%r12), %rax
	movslq	(%r13), %r15
	imulq	%rax, %r15
	shlq	$2, %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r15
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	(%r13), %eax
	imull	(%r12), %eax
	testl	%eax, %eax
	jle	.LBB3_3
# %bb.1:                                # %.lr.ph.preheader
	movq	%rbx, %r12
	xorl	%r13d, %r13d
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %edi
	movq	%r12, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r13
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rcx
	imulq	%rax, %rcx
	addq	$4, %r12
	cmpq	%rcx, %r13
	jl	.LBB3_2
.LBB3_3:                                # %._crit_edge
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	4(%rsp), %eax
	movl	(%rsp), %ecx
	movl	%ecx, %edx
	imull	%eax, %edx
	testl	%edx, %edx
	jle	.LBB3_6
# %bb.4:                                # %.lr.ph65.preheader
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB3_5:                                # %.lr.ph65
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %edi
	movq	%r12, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r13
	movl	4(%rsp), %eax
	movl	(%rsp), %ecx
	movl	%ecx, %edx
	imull	%eax, %edx
	movslq	%edx, %rdx
	addq	$4, %r12
	cmpq	%rdx, %r13
	jl	.LBB3_5
.LBB3_6:                                # %._crit_edge66
	cltq
	movslq	%ecx, %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	24(%rsp), %r13
	movq	%r13, %rdi
	callq	hipMalloc
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	callq	hipMalloc
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	8(%rsp), %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	movl	$.L.str.9, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	36(%rsp), %r12
	movl	$0, (%r12)
	movl	$.L.str.2, %edi
	movq	%r12, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%r12), %eax
	cmpl	$1, %eax
	je	.LBB3_11
# %bb.7:                                # %._crit_edge66
	cmpl	$2, %eax
	je	.LBB3_13
# %bb.8:                                # %._crit_edge66
	cmpl	$3, %eax
	jne	.LBB3_22
# %bb.9:
	movl	(%rsp), %eax
	movl	4(%rsp), %r12d
	shlq	$32, %r12
	orq	%rax, %r12
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_15
# %bb.10:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	4(%rsp), %ecx
	movl	(%rsp), %r8d
	callq	_Z34__device_stub__addMatElementThreadPiS_S_ii
	jmp	.LBB3_15
.LBB3_13:
	movl	$.Lstr.7, %edi
	callq	puts@PLT
	movl	(%rsp), %eax
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	(%rax,%rdi), %rdx
	decq	%rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_15
# %bb.14:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	4(%rsp), %ecx
	movl	(%rsp), %r8d
	callq	_Z31__device_stub__addMatColThreadsPiS_S_ii
	jmp	.LBB3_15
.LBB3_11:
	movl	$.Lstr.8, %edi
	callq	puts@PLT
	movl	4(%rsp), %eax
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	(%rax,%rdi), %rdx
	decq	%rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_15
# %bb.12:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	4(%rsp), %ecx
	movl	(%rsp), %r8d
	callq	_Z31__device_stub__addMatRowThreadsPiS_S_ii
.LBB3_15:
	movq	8(%rsp), %rsi
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	36(%rsp), %esi
	movl	$.L.str.14, %edi
	xorl	%eax, %eax
	callq	printf
	cmpl	$0, 4(%rsp)
	jle	.LBB3_21
# %bb.16:                               # %.preheader.preheader
	xorl	%ebp, %ebp
.LBB3_17:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_19 Depth 2
	movl	(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB3_20
# %bb.18:                               # %.lr.ph69.preheader
                                        #   in Loop: Header=BB3_17 Depth=1
	xorl	%r12d, %r12d
.LBB3_19:                               # %.lr.ph69
                                        #   Parent Loop BB3_17 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	imull	%ebp, %eax
	cltq
	addq	%r12, %rax
	movl	(%r15,%rax,4), %esi
	movl	$.L.str.15, %edi
	xorl	%eax, %eax
	callq	printf
	movl	(%rsp), %eax
	incq	%r12
	cmpl	%eax, %r12d
	jl	.LBB3_19
.LBB3_20:                               # %._crit_edge70
                                        #   in Loop: Header=BB3_17 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incl	%ebp
	cmpl	4(%rsp), %ebp
	jl	.LBB3_17
.LBB3_21:                               # %._crit_edge72
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_22:
	.cfi_def_cfa_offset 96
	movl	$.Lstr.9, %edi
	callq	puts@PLT
	movl	$1, %edi
	callq	exit
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16addMatRowThreadsPiS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16addMatColThreadsPiS_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19addMatElementThreadPiS_S_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16addMatRowThreadsPiS_S_ii,@object # @_Z16addMatRowThreadsPiS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z16addMatRowThreadsPiS_S_ii
	.p2align	3, 0x0
_Z16addMatRowThreadsPiS_S_ii:
	.quad	_Z31__device_stub__addMatRowThreadsPiS_S_ii
	.size	_Z16addMatRowThreadsPiS_S_ii, 8

	.type	_Z16addMatColThreadsPiS_S_ii,@object # @_Z16addMatColThreadsPiS_S_ii
	.globl	_Z16addMatColThreadsPiS_S_ii
	.p2align	3, 0x0
_Z16addMatColThreadsPiS_S_ii:
	.quad	_Z31__device_stub__addMatColThreadsPiS_S_ii
	.size	_Z16addMatColThreadsPiS_S_ii, 8

	.type	_Z19addMatElementThreadPiS_S_ii,@object # @_Z19addMatElementThreadPiS_S_ii
	.globl	_Z19addMatElementThreadPiS_S_ii
	.p2align	3, 0x0
_Z19addMatElementThreadPiS_S_ii:
	.quad	_Z34__device_stub__addMatElementThreadPiS_S_ii
	.size	_Z19addMatElementThreadPiS_S_ii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"m >> "
	.size	.L.str.1, 6

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d"
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"n >> "
	.size	.L.str.3, 6

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"3. Thread handles element\nChoice >> "
	.size	.L.str.9, 37

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"== Matrix C Elements (computed by choice %d)==\n"
	.size	.L.str.14, 48

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"%d "
	.size	.L.str.15, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16addMatRowThreadsPiS_S_ii"
	.size	.L__unnamed_1, 29

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16addMatColThreadsPiS_S_ii"
	.size	.L__unnamed_2, 29

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z19addMatElementThreadPiS_S_ii"
	.size	.L__unnamed_3, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"== Enter Dimension of Matrix A and B (m x n) =="
	.size	.Lstr, 48

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"== Matrix A Elements =="
	.size	.Lstr.1, 24

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"== Matrix B Elements =="
	.size	.Lstr.2, 24

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"\nChoose a degree of parallelism >> "
	.size	.Lstr.3, 36

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"1. Thread handles row"
	.size	.Lstr.4, 22

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"2. Thread handles column"
	.size	.Lstr.5, 25

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"Chose: Thread handles element"
	.size	.Lstr.6, 30

	.type	.Lstr.7,@object                 # @str.7
.Lstr.7:
	.asciz	"Chose: Thread handles column"
	.size	.Lstr.7, 29

	.type	.Lstr.8,@object                 # @str.8
.Lstr.8:
	.asciz	"Chose: Thread handles row"
	.size	.Lstr.8, 26

	.type	.Lstr.9,@object                 # @str.9
.Lstr.9:
	.asciz	"Bad Option, exiting ..."
	.size	.Lstr.9, 24

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__addMatRowThreadsPiS_S_ii
	.addrsig_sym _Z31__device_stub__addMatColThreadsPiS_S_ii
	.addrsig_sym _Z34__device_stub__addMatElementThreadPiS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16addMatRowThreadsPiS_S_ii
	.addrsig_sym _Z16addMatColThreadsPiS_S_ii
	.addrsig_sym _Z19addMatElementThreadPiS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16addMatRowThreadsPiS_S_ii ; -- Begin function _Z16addMatRowThreadsPiS_S_ii
	.globl	_Z16addMatRowThreadsPiS_S_ii
	.p2align	8
	.type	_Z16addMatRowThreadsPiS_S_ii,@function
_Z16addMatRowThreadsPiS_S_ii:           ; @_Z16addMatRowThreadsPiS_S_ii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_lo_u32 v0, v0, s2
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[4:5], off
	global_load_b32 v7, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v7, v6
	global_store_b32 v[0:1], v6, off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16addMatRowThreadsPiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 10
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16addMatRowThreadsPiS_S_ii, .Lfunc_end0-_Z16addMatRowThreadsPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 12
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16addMatColThreadsPiS_S_ii ; -- Begin function _Z16addMatColThreadsPiS_S_ii
	.globl	_Z16addMatColThreadsPiS_S_ii
	.p2align	8
	.type	_Z16addMatColThreadsPiS_S_ii,@function
_Z16addMatColThreadsPiS_S_ii:           ; @_Z16addMatColThreadsPiS_S_ii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
	s_ashr_i32 s9, s3, 31
	s_mov_b32 s8, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[8:9], 2
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	s_add_i32 s2, s2, -1
	global_load_b32 v6, v[2:3], off
	global_load_b32 v4, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_cmp_eq_u32 s2, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v4, v6
	global_store_b32 v[2:3], v4, off
	s_cbranch_scc0 .LBB1_2
.LBB1_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16addMatColThreadsPiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 10
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16addMatColThreadsPiS_S_ii, .Lfunc_end1-_Z16addMatColThreadsPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 172
; NumSgprs: 12
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19addMatElementThreadPiS_S_ii ; -- Begin function _Z19addMatElementThreadPiS_S_ii
	.globl	_Z19addMatElementThreadPiS_S_ii
	.p2align	8
	.type	_Z19addMatElementThreadPiS_S_ii,@function
_Z19addMatElementThreadPiS_S_ii:        ; @_Z19addMatElementThreadPiS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19addMatElementThreadPiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z19addMatElementThreadPiS_S_ii, .Lfunc_end2-_Z19addMatElementThreadPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 10
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16addMatRowThreadsPiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     12
    .sgpr_spill_count: 0
    .symbol:         _Z16addMatRowThreadsPiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16addMatColThreadsPiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     12
    .sgpr_spill_count: 0
    .symbol:         _Z16addMatColThreadsPiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19addMatElementThreadPiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z19addMatElementThreadPiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
