#include <iostream>
#include <math.h>
#include <stdio.h>
#define TYPE1 float
#define TYPE2 double
#define TYPE3 float
#define TYPE4 double
#define SPEED 0
double fun_ref( double x){
  int k, n = 5;
  double t1;
  double d1 = 1.0;
  t1 = x;
  for ( k = 1; k <= n; k++ )
    {
      d1 = 2.0 * d1;
      t1 = t1+ sin(d1 * x)/d1;
    }
    return t1;
}
__global__ void fun_gpu(double x[], double y[], int nthreads, int speed){
  //y = fun(x)
  //speed = %
  int tid = blockDim.x * blockIdx.x + threadIdx.x;
  if(blockIdx.x < speed){
    int k, n = 5;
    if (tid < nthreads) {
      float t1;
      float d1 = 1.0;
      float x_temp = x[tid];
      t1 = x[tid];
      for ( k = 1; k <= n; k++ )
        {
          d1 = 2.0 * d1;
          float sin_res = sin(d1 * x_temp);
          t1 = t1 + sin_res/d1;
        }
      y[tid] = t1;
    }
  }
  else{
    int k, n = 5;
    if (tid < nthreads) {
      double t1;
      double d1 = 1.0;
      double x_temp = x[tid];
      t1 = x[tid];
      for ( k = 1; k <= n; k++ )
        {
          d1 = 2.0 * d1;
          double sin_res = sin(d1 * x_temp);
          t1 = t1 + sin_res/d1;
        }
      y[tid] = t1;
  }
 }

}


int main( int argc, char **argv) {
  int i,n = 1000000;
  double h, t1, t2, dppi;
  double s1;
  //cuda def
  cudaEvent_t start, stop;
  float elapsedTime;
  int speed = atoi(argv[1]);
  printf("running with speed %d \n", speed);
  double *d_x, *d_y, *h_x, *h_y ;
  size_t size = n*sizeof(double);

  h_x = (double*) malloc(size);
  h_y = (double*) malloc(size);
  cudaMalloc(&d_x, size);
  cudaMalloc(&d_y, size);


  t1 = -1.0;
  dppi = acos(t1);
  s1 = 0.0;
  t1 = 0.0;
  h = dppi / n;
  for ( i = 1; i <= n; i++){
    h_x[i-1] = i * h;
  }
    /* Copy vectors from host memory to device memory */
  cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);

  int threads_per_block = 256;

  int block_count = (n + threads_per_block - 1)/threads_per_block;
  cudaEventCreate(&start);
  cudaEventRecord(start,0);
  for (int i =0;i < 10; i ++)
    fun_gpu<<<block_count, threads_per_block>>>(d_x, d_y, n,speed);

  cudaDeviceSynchronize();
  cudaEventCreate(&stop);
  cudaEventRecord(stop,0);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&elapsedTime, start,stop);
  printf("Elapsed time : %f ms\n" ,elapsedTime);
  cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
  for ( i = 1; i <= n; i++)
    {
      t2 = h_y[i-1];
      s1 = s1 + sqrt(h*h + (t2 - t1) * (t2 - t1));
      t1 = t2;
    }
  double ref_value = 5.7957763224;
  printf("%.10f\n",s1);
  printf("abs err %.8f  rel err %.8f\n", fabs(s1-ref_value), fabs((s1-ref_value)/ref_value) );
  return 0;
}

	.file	"tmpxft_0023eff4_00000000-6_funarc_gpu.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7fun_refd
	.type	_Z7fun_refd, @function
_Z7fun_refd:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movaps	%xmm0, %xmm2
	movaps	%xmm0, %xmm3
	movl	$5, %ebx
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	movsd	.LC0(%rip), %xmm1
.L3:
	addsd	%xmm1, %xmm1
	movaps	%xmm2, %xmm0
	movsd	%xmm3, 24(%rsp)
	movsd	%xmm2, 16(%rsp)
	mulsd	%xmm1, %xmm0
	movsd	%xmm1, 8(%rsp)
	call	sin@PLT
	movsd	8(%rsp), %xmm1
	decl	%ebx
	movsd	24(%rsp), %xmm3
	movsd	16(%rsp), %xmm2
	divsd	%xmm1, %xmm0
	addsd	%xmm0, %xmm3
	jne	.L3
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movaps	%xmm3, %xmm0
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z7fun_refd, .-_Z7fun_refd
	.globl	_Z30__device_stub__Z7fun_gpuPdS_iiPdS_ii
	.type	_Z30__device_stub__Z7fun_gpuPdS_iiPdS_ii, @function
_Z30__device_stub__Z7fun_gpuPdS_iiPdS_ii:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7fun_gpuPdS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L7:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z30__device_stub__Z7fun_gpuPdS_iiPdS_ii, .-_Z30__device_stub__Z7fun_gpuPdS_iiPdS_ii
	.globl	_Z7fun_gpuPdS_ii
	.type	_Z7fun_gpuPdS_ii, @function
_Z7fun_gpuPdS_ii:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z7fun_gpuPdS_iiPdS_ii
	.cfi_endproc
.LFE3662:
	.size	_Z7fun_gpuPdS_ii, .-_Z7fun_gpuPdS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"running with speed %d \n"
.LC4:
	.string	"Elapsed time : %f ms\n"
.LC6:
	.string	"%.10f\n"
.LC9:
	.string	"abs err %.8f  rel err %.8f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	8(%rsi), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	atoi@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movl	%eax, %edx
	movl	%eax, %ebx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$8000000, %edi
	call	malloc@PLT
	movl	$8000000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	leaq	24(%rsp), %rdi
	movl	$8000000, %esi
	movq	%rax, %rbp
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$8000000, %esi
	call	cudaMalloc@PLT
	movsd	.LC3(%rip), %xmm1
	movl	$1, %edx
.L13:
	cvtsi2sdl	%edx, %xmm0
	mulsd	%xmm1, %xmm0
	movsd	%xmm0, -8(%r12,%rdx,8)
	incq	%rdx
	cmpq	$1000001, %rdx
	jne	.L13
	movq	24(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	movl	$8000000, %edx
	movabsq	$4294967552, %r13
	movl	$10, %r12d
	call	cudaMemcpy@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L15:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movl	$1, %ecx
	movabsq	$4294971203, %rdi
	movl	$1, %esi
	movq	%r13, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	%ebx, %ecx
	movl	$1000000, %edx
	call	_Z30__device_stub__Z7fun_gpuPdS_iiPdS_ii
.L14:
	decl	%r12d
	jne	.L15
	call	cudaDeviceSynchronize@PLT
	leaq	56(%rsp), %rdi
	xorl	%ebx, %ebx
	call	cudaEventCreate@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	44(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	44(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	32(%rsp), %rsi
	movl	$2, %ecx
	movl	$8000000, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movq	$0x000000000, (%rsp)
	xorps	%xmm1, %xmm1
.L16:
	movaps	%xmm1, %xmm2
	movsd	0(%rbp,%rbx,8), %xmm1
	incq	%rbx
	movaps	%xmm1, %xmm0
	movsd	%xmm1, 8(%rsp)
	subsd	%xmm2, %xmm0
	mulsd	%xmm0, %xmm0
	addsd	.LC5(%rip), %xmm0
	call	sqrt@PLT
	addsd	(%rsp), %xmm0
	cmpq	$1000000, %rbx
	movsd	8(%rsp), %xmm1
	movsd	%xmm0, (%rsp)
	jne	.L16
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	movsd	.LC7(%rip), %xmm2
	movsd	(%rsp), %xmm0
	movb	$2, %al
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	subsd	%xmm2, %xmm0
	movaps	%xmm0, %xmm1
	divsd	%xmm2, %xmm1
	movq	.LC8(%rip), %xmm2
	andps	%xmm2, %xmm0
	andps	%xmm2, %xmm1
	call	__printf_chk@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z7fun_gpuPdS_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7fun_gpuPdS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1072693248
	.align 8
.LC3:
	.long	-746556290
	.long	1053448836
	.align 8
.LC5:
	.long	-453130698
	.long	1034269719
	.align 8
.LC7:
	.long	-50426242
	.long	1075261151
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC8:
	.long	-1
	.long	2147483647
	.long	0
	.long	0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <stdio.h>
#define TYPE1 float
#define TYPE2 double
#define TYPE3 float
#define TYPE4 double
#define SPEED 0
double fun_ref( double x){
  int k, n = 5;
  double t1;
  double d1 = 1.0;
  t1 = x;
  for ( k = 1; k <= n; k++ )
    {
      d1 = 2.0 * d1;
      t1 = t1+ sin(d1 * x)/d1;
    }
    return t1;
}
__global__ void fun_gpu(double x[], double y[], int nthreads, int speed){
  //y = fun(x)
  //speed = %
  int tid = blockDim.x * blockIdx.x + threadIdx.x;
  if(blockIdx.x < speed){
    int k, n = 5;
    if (tid < nthreads) {
      float t1;
      float d1 = 1.0;
      float x_temp = x[tid];
      t1 = x[tid];
      for ( k = 1; k <= n; k++ )
        {
          d1 = 2.0 * d1;
          float sin_res = sin(d1 * x_temp);
          t1 = t1 + sin_res/d1;
        }
      y[tid] = t1;
    }
  }
  else{
    int k, n = 5;
    if (tid < nthreads) {
      double t1;
      double d1 = 1.0;
      double x_temp = x[tid];
      t1 = x[tid];
      for ( k = 1; k <= n; k++ )
        {
          d1 = 2.0 * d1;
          double sin_res = sin(d1 * x_temp);
          t1 = t1 + sin_res/d1;
        }
      y[tid] = t1;
  }
 }

}


int main( int argc, char **argv) {
  int i,n = 1000000;
  double h, t1, t2, dppi;
  double s1;
  //cuda def
  hipEvent_t start, stop;
  float elapsedTime;
  int speed = atoi(argv[1]);
  printf("running with speed %d \n", speed);
  double *d_x, *d_y, *h_x, *h_y ;
  size_t size = n*sizeof(double);

  h_x = (double*) malloc(size);
  h_y = (double*) malloc(size);
  hipMalloc(&d_x, size);
  hipMalloc(&d_y, size);


  t1 = -1.0;
  dppi = acos(t1);
  s1 = 0.0;
  t1 = 0.0;
  h = dppi / n;
  for ( i = 1; i <= n; i++){
    h_x[i-1] = i * h;
  }
    /* Copy vectors from host memory to device memory */
  hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);

  int threads_per_block = 256;

  int block_count = (n + threads_per_block - 1)/threads_per_block;
  hipEventCreate(&start);
  hipEventRecord(start,0);
  for (int i =0;i < 10; i ++)
    fun_gpu<<<block_count, threads_per_block>>>(d_x, d_y, n,speed);

  hipDeviceSynchronize();
  hipEventCreate(&stop);
  hipEventRecord(stop,0);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&elapsedTime, start,stop);
  printf("Elapsed time : %f ms\n" ,elapsedTime);
  hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
  for ( i = 1; i <= n; i++)
    {
      t2 = h_y[i-1];
      s1 = s1 + sqrt(h*h + (t2 - t1) * (t2 - t1));
      t1 = t2;
    }
  double ref_value = 5.7957763224;
  printf("%.10f\n",s1);
  printf("abs err %.8f  rel err %.8f\n", fabs(s1-ref_value), fabs((s1-ref_value)/ref_value) );
  return 0;
}

	.text
	.file	"funarc_gpu.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z7fun_refd
.LCPI0_0:
	.quad	0x3ff0000000000000              # double 1
	.text
	.globl	_Z7fun_refd
	.type	_Z7fun_refd,@function
_Z7fun_refd:                            # @_Z7fun_refd
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movsd	.LCPI0_0(%rip), %xmm1           # xmm1 = mem[0],zero
	movl	$5, %ebx
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	addsd	%xmm1, %xmm1
	movsd	%xmm1, 24(%rsp)                 # 8-byte Spill
	movapd	%xmm1, %xmm0
	mulsd	16(%rsp), %xmm0                 # 8-byte Folded Reload
	callq	sin
	movsd	24(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	divsd	%xmm1, %xmm0
	movsd	8(%rsp), %xmm2                  # 8-byte Reload
                                        # xmm2 = mem[0],zero
	addsd	%xmm0, %xmm2
	movsd	%xmm2, 8(%rsp)                  # 8-byte Spill
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	decl	%ebx
	jne	.LBB0_1
# %bb.2:
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z7fun_refd, .Lfunc_end0-_Z7fun_refd
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__fun_gpuPdS_ii # -- Begin function _Z22__device_stub__fun_gpuPdS_ii
	.type	_Z22__device_stub__fun_gpuPdS_ii,@function
_Z22__device_stub__fun_gpuPdS_ii:       # @_Z22__device_stub__fun_gpuPdS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7fun_gpuPdS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__fun_gpuPdS_ii, .Lfunc_end1-_Z22__device_stub__fun_gpuPdS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x3eca5a84d380747e              # double 3.1415926535897933E-6
.LCPI2_1:
	.quad	0x3da5b417e4fdc636              # double 9.8696044010893597E-12
.LCPI2_2:
	.quad	0xc0172edffcfe8e7e              # double -5.7957763224000001
.LCPI2_4:
	.quad	0x40172edffcfe8e7e              # double 5.7957763224000001
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI2_3:
	.quad	0x7fffffffffffffff              # double NaN
	.quad	0x7fffffffffffffff              # double NaN
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebp
	xorl	%r14d, %r14d
	movl	$.L.str, %edi
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$8000000, %edi                  # imm = 0x7A1200
	callq	malloc
	movq	%rax, %r15
	movl	$8000000, %edi                  # imm = 0x7A1200
	callq	malloc
	movq	%rax, %rbx
	leaq	8(%rsp), %rdi
	movl	$8000000, %esi                  # imm = 0x7A1200
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$8000000, %esi                  # imm = 0x7A1200
	callq	hipMalloc
	movsd	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	leaq	1(%r14), %rax
	xorps	%xmm1, %xmm1
	cvtsi2sd	%eax, %xmm1
	mulsd	%xmm0, %xmm1
	movsd	%xmm1, (%r15,%r14,8)
	movq	%rax, %r14
	cmpq	$1000000, %rax                  # imm = 0xF4240
	jne	.LBB2_1
# %bb.2:
	movabsq	$4294967552, %r14               # imm = 0x100000100
	movq	8(%rsp), %rdi
	movl	$8000000, %edx                  # imm = 0x7A1200
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$10, %r12d
	leaq	3651(%r14), %r15
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_3 Depth=1
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$1000000, %edx                  # imm = 0xF4240
	movl	%ebp, %ecx
	callq	_Z22__device_stub__fun_gpuPdS_ii
.LBB2_5:                                #   in Loop: Header=BB2_3 Depth=1
	decl	%r12d
	jne	.LBB2_3
# %bb.6:
	callq	hipDeviceSynchronize
	leaq	56(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventCreate
	movq	(%r14), %rdi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r14), %rdi
	callq	hipEventSynchronize
	movq	16(%rsp), %rsi
	movq	(%r14), %rdx
	leaq	28(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	(%rsp), %rsi
	movl	$8000000, %edx                  # imm = 0x7A1200
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorpd	%xmm1, %xmm1
	movsd	.LCPI2_1(%rip), %xmm4           # xmm4 = mem[0],zero
	xorps	%xmm0, %xmm0
.LBB2_7:                                # =>This Inner Loop Header: Depth=1
	movsd	(%rbx,%r15,8), %xmm2            # xmm2 = mem[0],zero
	movapd	%xmm2, %xmm3
	subsd	%xmm1, %xmm3
	mulsd	%xmm3, %xmm3
	addsd	%xmm4, %xmm3
	xorps	%xmm1, %xmm1
	sqrtsd	%xmm3, %xmm1
	addsd	%xmm1, %xmm0
	incq	%r15
	movapd	%xmm2, %xmm1
	cmpq	$1000000, %r15                  # imm = 0xF4240
	jne	.LBB2_7
# %bb.8:
	movl	$.L.str.2, %edi
	movb	$1, %al
	movaps	%xmm0, 32(%rsp)                 # 16-byte Spill
	callq	printf
	movapd	32(%rsp), %xmm2                 # 16-byte Reload
	addsd	.LCPI2_2(%rip), %xmm2
	movapd	.LCPI2_3(%rip), %xmm1           # xmm1 = [NaN,NaN]
	movapd	%xmm2, %xmm0
	andpd	%xmm1, %xmm0
	divsd	.LCPI2_4(%rip), %xmm2
	andpd	%xmm1, %xmm2
	movapd	%xmm2, %xmm1
	movl	$.L.str.3, %edi
	movb	$2, %al
	callq	printf
	xorl	%eax, %eax
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7fun_gpuPdS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7fun_gpuPdS_ii,@object        # @_Z7fun_gpuPdS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z7fun_gpuPdS_ii
	.p2align	3, 0x0
_Z7fun_gpuPdS_ii:
	.quad	_Z22__device_stub__fun_gpuPdS_ii
	.size	_Z7fun_gpuPdS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"running with speed %d \n"
	.size	.L.str, 24

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Elapsed time : %f ms\n"
	.size	.L.str.1, 22

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%.10f\n"
	.size	.L.str.2, 7

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"abs err %.8f  rel err %.8f\n"
	.size	.L.str.3, 28

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7fun_gpuPdS_ii"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__fun_gpuPdS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7fun_gpuPdS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7fun_gpuPdS_ii        ; -- Begin function _Z7fun_gpuPdS_ii
	.globl	_Z7fun_gpuPdS_ii
	.p2align	8
	.type	_Z7fun_gpuPdS_ii,@function
_Z7fun_gpuPdS_ii:                       ; @_Z7fun_gpuPdS_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s8, 0xffff
	s_cmp_ge_u32 s15, s3
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s2, v1
	s_cbranch_scc0 .LBB0_10
; %bb.1:
	s_mov_b32 s33, 0
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s46, s0
	s_cbranch_execz .LBB0_9
; %bb.2:
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s10, 0x6dc9c883
	s_mov_b32 s12, 0x33145c00
	s_mov_b32 s14, 0x252049c0
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_mov_b32 s16, 0x9037ab78
	s_mov_b32 s18, 0x46cc5e42
	s_mov_b32 s20, 0xa17f65f6
	s_mov_b32 s22, 0x19f4ec90
	s_mov_b32 s24, 0x16c16967
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s26, 0x55555555
	s_mov_b32 s28, 0xb42fdfa7
	s_mov_b32 s30, 0xf9a43bb8
	global_load_b64 v[5:6], v[3:4], off
	v_mov_b32_e32 v7, 0
	v_dual_mov_b32 v8, 0x3ff00000 :: v_dual_mov_b32 v9, 0
	s_mov_b32 s34, 0x796cde01
	s_mov_b32 s36, 0x19e83e5c
	s_mov_b32 s38, 0x11110bb3
	s_mov_b32 s47, 5
	s_mov_b32 s3, 0x3ff921fb
	s_mov_b32 s9, 0xbff921fb
	s_mov_b32 s11, 0x3fe45f30
	s_mov_b32 s13, 0xbc91a626
	s_mov_b32 s15, 0xb97b839a
	s_mov_b32 s17, 0x3e21eeb6
	s_mov_b32 s19, 0xbda907db
	s_mov_b32 s21, 0xbe927e4f
	s_mov_b32 s23, 0x3efa01a0
	s_mov_b32 s25, 0xbf56c16c
	s_mov_b32 s27, 0x3fa55555
	s_mov_b32 s29, 0xbe5ae600
	s_mov_b32 s31, 0x3de5e0b2
	s_mov_b32 s35, 0x3ec71de3
	s_mov_b32 s37, 0xbf2a01a0
	s_mov_b32 s39, 0x3f811111
	s_mov_b32 s41, 0x3c91a626
	s_mov_b32 s42, 0x33145c07
	s_mov_b32 s45, 0xbfc55555
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	v_add_f64 v[7:8], v[7:8], v[7:8]
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $vgpr15_vgpr16
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[5:6], v[7:8]
	v_cmpx_ngt_f64_e64 0x41d00000, |v[11:12]|
	s_xor_b32 s40, exec_lo, s2
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	v_ldexp_f64 v[13:14], |v[11:12]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[11:12]|
	v_trig_preop_f64 v[15:16], |v[11:12]|, 0
	v_and_b32_e32 v0, 0x7fffffff, v12
	v_trig_preop_f64 v[17:18], |v[11:12]|, 1
	v_trig_preop_f64 v[27:28], |v[11:12]|, 2
	s_mov_b32 s2, s8
	s_mov_b32 s43, s41
	v_dual_cndmask_b32 v13, v11, v13 :: v_dual_cndmask_b32 v14, v0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[19:20], v[15:16], v[13:14]
	v_mul_f64 v[21:22], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[15:16], v[13:14], -v[19:20]
	v_fma_f64 v[17:18], v[17:18], v[13:14], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[21:22], v[15:16]
	v_add_f64 v[25:26], v[23:24], -v[21:22]
	v_add_f64 v[31:32], v[19:20], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[23:24], -v[25:26]
	v_add_f64 v[15:16], v[15:16], -v[25:26]
	v_ldexp_f64 v[25:26], v[31:32], -2
	v_add_f64 v[19:20], v[31:32], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[21:22], -v[29:30]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[25:26]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[23:24], -v[19:20]
	v_add_f64 v[15:16], v[15:16], v[21:22]
	v_fract_f64_e32 v[21:22], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v21, 0, v21, vcc_lo
	v_mul_f64 v[33:34], v[27:28], v[13:14]
	v_cndmask_b32_e32 v22, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[21:22], v[21:22], 2
	v_add_f64 v[29:30], v[33:34], v[17:18]
	v_fma_f64 v[13:14], v[27:28], v[13:14], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[29:30], v[15:16]
	v_add_f64 v[25:26], v[19:20], v[23:24]
	v_add_f64 v[35:36], v[23:24], -v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[31:32], v[25:26], v[21:22]
	v_add_f64 v[41:42], v[23:24], -v[35:36]
	v_add_f64 v[15:16], v[15:16], -v[35:36]
	v_add_f64 v[19:20], v[25:26], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[31:32]
	v_add_f64 v[31:32], v[29:30], -v[33:34]
	v_add_f64 v[19:20], v[23:24], -v[19:20]
	v_cndmask_b32_e64 v10, 0, 0x40100000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[39:40], v[29:30], -v[31:32]
	v_add_f64 v[17:18], v[17:18], -v[31:32]
	v_add_f64 v[29:30], v[29:30], -v[41:42]
	v_add_f64 v[21:22], v[21:22], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[31:32], v[33:34], -v[39:40]
	v_add_f64 v[15:16], v[15:16], v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[25:26], v[21:22]
	v_add_f64 v[17:18], v[17:18], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v0, v[37:38]
	v_add_f64 v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[35:36], v0
	v_add_f64 v[13:14], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], -v[35:36]
	v_add_f64 v[13:14], v[19:20], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[25:26], v[21:22]
	v_add_f64 v[15:16], v[17:18], -v[21:22]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[25:26], -v[15:16]
	v_cndmask_b32_e64 v10, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v0, s1, 0, v0, vcc_lo
	v_add_f64 v[13:14], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[17:18], -v[9:10]
	v_add_f64 v[17:18], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[19:20], v[17:18], s[2:3]
	v_add_f64 v[15:16], v[17:18], -v[15:16]
	v_fma_f64 v[21:22], v[17:18], s[2:3], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	v_fma_f64 v[15:16], v[17:18], s[42:43], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], s[2:3], v[15:16]
	v_add_f64 v[13:14], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[13:14], -v[19:20]
	v_add_f64 v[15:16], v[15:16], -v[17:18]
.LBB0_5:                                ; %Flow
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_not1_saveexec_b32 s1, s40
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	v_mul_f64 v[13:14], |v[11:12]|, s[10:11]
	s_mov_b32 s40, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[17:18], v[13:14]
	v_fma_f64 v[13:14], v[17:18], s[8:9], |v[11:12]|
	v_mul_f64 v[15:16], v[17:18], s[12:13]
	v_cvt_i32_f64_e32 v0, v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[17:18], s[12:13], v[13:14]
	v_add_f64 v[19:20], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	v_add_f64 v[19:20], v[19:20], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], v[15:16]
	v_fma_f64 v[15:16], v[17:18], s[40:41], v[15:16]
	v_add_f64 v[13:14], v[19:20], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	v_fma_f64 v[15:16], v[17:18], s[14:15], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[21:22], v[15:16]
	v_add_f64 v[19:20], v[13:14], -v[21:22]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[15:16], v[15:16], -v[19:20]
.LBB0_7:                                ; %_ZL3sind.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mul_f64 v[17:18], v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[27:28], v[15:16], 0.5
	s_mov_b32 s44, s26
	v_cmp_class_f64_e64 s1, v[11:12], 0x1f8
	s_add_i32 s47, s47, -1
	s_cmp_lg_u32 s47, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[19:20], v[17:18], s[30:31], s[28:29]
	v_fma_f64 v[21:22], v[17:18], s[18:19], s[16:17]
	v_mul_f64 v[23:24], v[17:18], 0.5
	v_mul_f64 v[29:30], v[13:14], -v[17:18]
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[34:35]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[20:21]
	v_add_f64 v[25:26], -v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[36:37]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[31:32], -v[25:26], 1.0
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[24:25]
	v_add_f64 v[23:24], v[31:32], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[19:20], v[29:30], v[19:20], v[27:28]
	v_mul_f64 v[27:28], v[17:18], v[17:18]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[13:14], -v[15:16], v[23:24]
	v_fma_f64 v[15:16], v[17:18], v[19:20], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[27:28], v[21:22], v[23:24]
	v_fma_f64 v[15:16], v[29:30], s[44:45], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[25:26], v[17:18]
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	v_and_b32_e32 v10, 1, v0
	v_lshlrev_b32_e32 v0, 30, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_xor_b32_e32 v0, v0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v11, v18, v14 :: v_dual_and_b32 v0, 0x80000000, v0
	v_cndmask_b32_e32 v10, v17, v13, vcc_lo
	v_xor_b32_e32 v0, v11, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, 0, v10, s1
	v_cndmask_b32_e64 v11, 0x7ff80000, v0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[12:13], null, v[7:8], v[7:8], v[10:11]
	v_rcp_f64_e32 v[14:15], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_div_scale_f64 v[16:17], vcc_lo, v[10:11], v[7:8], v[10:11]
	v_mul_f64 v[18:19], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[12:13], v[18:19], v[16:17]
	v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[10:11], v[12:13], v[7:8], v[10:11]
	v_add_f64 v[3:4], v[3:4], v[10:11]
	s_cbranch_scc1 .LBB0_3
; %bb.8:                                ; %Flow73
	s_mov_b32 s2, exec_lo
.LBB0_9:                                ; %Flow76
	s_or_b32 exec_lo, exec_lo, s46
	s_branch .LBB0_11
.LBB0_10:
	s_mov_b32 s33, -1
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr3_vgpr4
.LBB0_11:                               ; %Flow75
	s_and_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccz .LBB0_21
; %bb.12:
                                        ; implicit-def: $vgpr3_vgpr4
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_20
; %bb.13:
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v5, 1.0
	s_mov_b32 s8, 0xb94c1982
	s_mov_b32 s9, 0x37d75334
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s4, 5
	s_mov_b32 s5, 0x7fffff
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_f64_e32 v0, v[3:4]
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v6, v0
.LBB0_14:                               ; =>This Inner Loop Header: Depth=1
	v_add_f32_e32 v5, v5, v5
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr3
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v5, v0
	v_and_b32_e32 v8, 0x7fffffff, v7
	v_cmpx_ngt_f32_e64 0x48000000, |v7|
	s_xor_b32 s10, exec_lo, s1
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v14, 23, v8
	v_and_or_b32 v17, v8, s5, 0x800000
	v_add_nc_u32_e32 v15, 0xffffff88, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0xfe5163ab, v17, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v15
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v10 :: v_dual_add_nc_u32 v16, v16, v15
	v_mad_u64_u32 v[10:11], null, 0x3c439041, v17, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 31, v16
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v11 :: v_dual_add_nc_u32 v18, v18, v16
	v_mad_u64_u32 v[11:12], null, 0xdb629599, v17, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v18
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v9, v11, v9, vcc_lo
	v_mad_u64_u32 v[12:13], null, 0xf534ddc0, v17, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v13 :: v_dual_cndmask_b32 v10, v12, v10
	v_mad_u64_u32 v[13:14], null, 0xfc2757d1, v17, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, v10, v9, s0
	v_mov_b32_e32 v3, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, 0x4e441529, v17, v[3:4]
	v_mov_b32_e32 v3, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[15:16], null, 0xa2f9836e, v17, v[3:4]
	v_cndmask_b32_e64 v3, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v17, v14, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v3, v3, v18
	v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
	v_cndmask_b32_e32 v13, v13, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v16, 32, v3
	v_cndmask_b32_e64 v12, v15, v17, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, v14, v15, s0
	v_cndmask_b32_e64 v15, v17, v13, s0
	v_cndmask_b32_e64 v13, v13, v10, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, v14, v12, s1
	v_cndmask_b32_e64 v12, v12, v15, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v13, s1
	v_cndmask_b32_e64 v9, v13, v9, s1
	v_alignbit_b32 v17, v14, v12, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v11, v12, v15, v16
	v_dual_cndmask_b32 v3, v17, v14 :: v_dual_cndmask_b32 v10, v11, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v14, v15, v9, v16
	v_bfe_u32 v11, v3, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v3, v10, 30
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, 0, v11
	v_alignbit_b32 v10, v10, v14, 30
	v_alignbit_b32 v9, v14, v9, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v13
	v_xor_b32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v13
	v_lshrrev_b32_e32 v13, 29, v3
	v_clz_i32_u32_e32 v15, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v13, 31, v13
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v16, 0.5, v13
	v_sub_nc_u32_e32 v14, 31, v15
	v_lshlrev_b32_e32 v17, 23, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v12, v10, v14
	v_alignbit_b32 v9, v10, v9, v14
	v_sub_nc_u32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v10, v12, v9, 9
	v_lshrrev_b32_e32 v12, 9, v12
	v_clz_i32_u32_e32 v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v14, 32, v14
	v_sub_nc_u32_e32 v18, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v10, v9, v18
	v_or_b32_e32 v10, v12, v16
	v_add_lshl_u32 v12, v14, v15, 23
	v_lshrrev_b32_e32 v9, 9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x3fc90fda, v10
	v_sub_nc_u32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3fc90fda, v10, -v14
	v_add_nc_u32_e32 v9, 0x33000000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, 0x33a22168, v10
	v_or_b32_e32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, 0x3fc90fda, v9
	v_lshrrev_b32_e32 v9, 30, v3
	v_add_f32_e32 v3, v14, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v11, v9
.LBB0_16:                               ; %Flow74
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_and_not1_saveexec_b32 s0, s10
; %bb.17:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mul_f32_e64 v3, 0x3f22f983, |v7|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v9, v3
	v_fma_f32 v3, 0xbfc90fda, v9, |v7|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, 0xb3a22168, v9
	v_fmac_f32_e32 v3, 0xa7c234c4, v9
	v_cvt_i32_f32_e32 v9, v9
; %bb.18:                               ; %_ZL3sinf.exit
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v10, v3, v3 :: v_dual_and_b32 v13, 1, v9
	v_xor_b32_e32 v8, v8, v7
	s_add_i32 s4, s4, -1
	v_lshlrev_b32_e32 v9, 30, v9
	v_fmaak_f32 v11, s8, v10, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	s_cmp_lg_u32 s4, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v9, 0x80000000, v9
	v_fmaak_f32 v11, v10, v11, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v12, s9, v10, 0xbab64f3b :: v_dual_mul_f32 v11, v10, v11
	v_dual_fmaak_f32 v12, v10, v12, 0x3d2aabf7 :: v_dual_fmac_f32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v12, v10, v12, 0xbf000004
	v_fma_f32 v10, v10, v12, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v10, v3, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v7, 0x1f8
	v_xor3_b32 v3, v8, v9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
	v_div_scale_f32 v7, null, v5, v5, v3
	v_div_scale_f32 v10, vcc_lo, v3, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v7, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v10, v8
	v_fma_f32 v11, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v11, v8
	v_fma_f32 v7, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v8, v9
	v_div_fixup_f32 v3, v7, v5, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v3
	s_cbranch_scc1 .LBB0_14
; %bb.19:
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[3:4], v6
	s_or_b32 s2, s2, exec_lo
.LBB0_20:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_21:                               ; %Flow77
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_23
; %bb.22:                               ; %.sink.split
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b64 v[0:1], v[3:4], off
.LBB0_23:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7fun_gpuPdS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 43
		.amdhsa_next_free_sgpr 48
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7fun_gpuPdS_ii, .Lfunc_end0-_Z7fun_gpuPdS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2992
; NumSgprs: 50
; NumVgprs: 43
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 50
; NumVGPRsForWavesPerEU: 43
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7fun_gpuPdS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     50
    .sgpr_spill_count: 0
    .symbol:         _Z7fun_gpuPdS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     43
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
