#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>

#define LO8(x)      ((x) & 0x000000FF)
#define MI16(x)		(((x) & 0x0000FFFF) >> 8)
#define HI24(x)     (((x) & 0x00FFFFFF) >> 16)
#define MUL24(x,y)  ((x) * (y))
#define DIVUP(x, y) (((x) + (y) - 1) / (y))
#define MIN(a, b)   ((a) < (b) ? (a) : (b))

__global__ void kSampleMultinomial(int* output, float* distribution, float* random, int k, int n){
	
	const unsigned int id = threadIdx.x + blockIdx.x * blockDim.x;
	
	if(id < n){
		distribution += k * id;
		random += id;
		output += k * id;

		float preSum = 0, nowSum = 0;
		for(int i = 0; i < k; i++){
			nowSum += distribution[i];
			output[i] = random[0] >= preSum && random[0] < nowSum;
			preSum = nowSum;
		}
	}
}

__global__ void kExp(float* output, float* input, unsigned int numElements){
	const unsigned int id = threadIdx.x + blockIdx.x * blockDim.x;
	const unsigned int numThreads = blockDim.x * gridDim.x;

	for(int i = id; i < numElements; i += numThreads)
		output[i] = __expf(input[i]);
}

__global__ void kDivide(float* output, float* leftInput, float* rightInput, unsigned int numElements){
	const unsigned int id = threadIdx.x + blockIdx.x * blockDim.x;
	const unsigned int numThreads = blockDim.x * gridDim.x;

	for(int i = id; i < numElements; i += numThreads)
		output[i] = __fdividef(leftInput[i], rightInput[i]);
}

__global__ void kConvolve_forward(float* targets, float* images, float* filters, 
                                   const int numImages, const int numFilters,
                                   const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int filterSize, const int paddingStart,
                                   const int moduleStride,
                                   const int numModulesZ, const int numModulesY, const int numModulesX, const int imgStride) {
    __shared__ float shFilters[4*1][4 * 4]; // pre-load 4 pixels from 4*4 filters
    __shared__ float shImages[4*1][32 * 1]; // pre-load 4 pixels from 32*2 images
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;
    const int filterPixels = filterSize * filterSize * filterSize;

    const int blocksPerModule = numFilters / (4*4);
    const int moduleIdx = blockIdx.y / blocksPerModule;
    const int blockFilterIdx = blockIdx.y % blocksPerModule;

    const int tidx = threadIdx.y * 32 + threadIdx.x;

    const int imgLoadModPosZ = (moduleIdx / (numModulesX * numModulesY)) * moduleStride;
    const int imgLoadModPosY = ((moduleIdx / numModulesX) % numModulesY )* moduleStride;
    const int imgLoadModPosX = (moduleIdx % numModulesX) * moduleStride;

    const int shFilterLoadY = tidx / (4 * 4);
    const int shFilterLoadX = tidx % (4 * 4);
    const int myImgIdx = blockIdx.x * 32 * 1 + threadIdx.x;
    images += myImgIdx;
    filters += 4 * 4 * blockFilterIdx
             + shFilterLoadY * numFilters + shFilterLoadX;
    targets += moduleIdx * numImages
            + (blockFilterIdx * 4 * 4 + threadIdx.y) * numImages * numModulesZ * numModulesY * numModulesX
            + myImgIdx;


    float prod[4][1];
    #pragma unroll
    for(int f = 0; f < 4; f++) {
        #pragma unroll
        for(int g = 0; g < 1; g++) {
            prod[f][g] = 0;
        }
    }

    for (int p = 0; p < filterPixels; p += 4) {
        /*
         * Load 4 pixels from 4*4 filters
         */
        if (shFilterLoadY < 4) {
            #pragma unroll
            for (int p2 = 0; p2 < 4; p2 += 32/4) {
                if (p + p2 + shFilterLoadY < filterPixels) {
                    #pragma unroll
                    for (int c = 0; c < 1; c++) {
                        shFilters[shFilterLoadY + p2 + c * 4][shFilterLoadX] = filters[(c * filterPixels + p + p2) * numFilters];
                    }
                } else {
                    #pragma unroll
                    for (int c = 0; c < 1; c++) {
                        shFilters[shFilterLoadY + p2 + c * 4][shFilterLoadX] = 0;
                    }
                }
            }
        }

        /*
         * Load 4 pixels from 32*1 images
         */
        const int pixIdx = p + threadIdx.y;
        if (pixIdx < filterPixels) {
            const int x = paddingStart + imgLoadModPosX + pixIdx % filterSize;
            const int y = paddingStart + imgLoadModPosY + (pixIdx / filterSize) % filterSize;
            const int z = paddingStart + imgLoadModPosZ + pixIdx / (filterSize * filterSize);
            if (z >= 0 && z < imgSizeZ && y >= 0 && y < imgSizeY && x >= 0 && x < imgSizeX) {
                #pragma unroll
                for (int i = 0; i < 1; i++) {
                    if (!true || myImgIdx + i * 32 < numImages) {
                        #pragma unroll
                        for (int c = 0; c < 1; c++) {
                            shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = images[imgStride * (c * imgPixels + z * imgSizeX * imgSizeY + y * imgSizeX + x) + i * 32];
                        }
                    } else {
                        #pragma unroll
                        for (int c = 0; c < 1; c++) {
                            shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = 0;
                        }
                    }
                }
            } else { // Padding
                #pragma unroll
                for (int i = 0; i < 1; i++) {
                    #pragma unroll
                    for (int c = 0; c < 1; c++) {
                        shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = 0;
                    }
                }
            }
        }
        __syncthreads();
        #pragma unroll
        for (int i = 0; i < 4*1; i++) {
            #pragma unroll
            for(int f = 0; f < 4; f++) {
                #pragma unroll
                for(int g = 0; g < 1; g++) {
                    prod[f][g] += shImages[i][g * 32 + threadIdx.x] * shFilters[i][threadIdx.y + f * 4];
                }
            }

        }
        __syncthreads();
    }
    
    #pragma unroll
    for (int g = 0; g < 1; g++) {
        if (!true || myImgIdx + g * 32 < numImages) {
            #pragma unroll
            for (int f = 0; f < 4; f++) {
                targets[g * 32 + f * 4 * numImages * numModulesZ * numModulesY * numModulesX] = prod[f][g];
            }
        }
    }
}

__global__ void kConvolve_weight(float* targets, float* images, float* hidActs,
                                   const int numImages, const int numFilters,
                                   const int numModulesZ, const int numModulesY, const int numModulesX,
                                   const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int filterSize,
                                   const int paddingStart, const int moduleStride, const int imgStride,
                                   const int partialSum, const float scaleOutputs) {
    __shared__ float shImages[5 * 8 * 1][32]; // preload 32 cases of 8 * 5 pixels
    __shared__ float shHidActs[16][32 + 1]; // preload 32 cases of 16 hidActs

    const int tidx = 16 * threadIdx.y + threadIdx.x;
    const int loadY = tidx / 32, loadX = tidx % 32;

    const int filterPixels = filterSize * filterSize * filterSize;
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;

    const int filterBlocksPerModule = numFilters / 16;
    const int outputModuleIdx = blockIdx.x / filterBlocksPerModule;
    const int moduleIdx = partialSum * outputModuleIdx;
    const int blockFilterIdx = 16 * (blockIdx.x % filterBlocksPerModule);

//    const int moduleStride = (imgSize - filterSize + 1) / numModulesX; 
    const int numModules = numModulesZ * numModulesY * numModulesX;

    const int blockPixelOffset = blockIdx.y * 8 * 5;

    images += loadX;
    hidActs += moduleIdx * numImages
            + blockFilterIdx * numImages * numModules
            + loadY * numImages * numModules
            + loadX;
    
    targets += (outputModuleIdx * numFilters) * filterPixels * 1
            + blockPixelOffset * numFilters
            + blockFilterIdx
            + threadIdx.y * numFilters + threadIdx.x;

    float* shImgLoad = &shImages[loadY][loadX];
    float* shHidActLoad = &shHidActs[loadY][loadX];

    float prod[1][5];
    #pragma unroll
    for (int c = 0; c < 1; c++) {
        #pragma unroll
        for (int p = 0; p < 5; p++) {
            prod[c][p] = 0;
        }
    }
    
    __shared__ int pxDivs[8*5];
    if (tidx < 8 * 5) {
        pxDivs[tidx] = (((blockPixelOffset + tidx) / (filterSize * filterSize)) << 16) + (((blockPixelOffset + tidx) / filterSize) % filterSize << 8) + ((blockPixelOffset + tidx) % filterSize);
    }
    __syncthreads();
    for (int m = moduleIdx; m < moduleIdx + partialSum; m++) {
        const int imgLoadModPosZ = paddingStart + (m / (numModulesX * numModulesY)) * moduleStride;
        const int imgLoadModPosY = paddingStart + ((m / numModulesX) % numModulesY) * moduleStride;
        const int imgLoadModPosX = paddingStart + (m % numModulesX) * moduleStride;
        for (int caseIdx = 0; caseIdx < numImages; caseIdx += 32) {
            if (loadY < 8 * 5) {
                /*
                 * As long as 8 * 16 is divisible by 32 this will loop the right
                 * number of times.
                 *
                 * This will load some imgGrads from filter pixels that don't exit (it'll set those to 0),
                 * but the code does not produce any output for those pixels (see last lines).
                 */
    //            #pragma unroll
                for (int y = 0; y < 8 * 5; y += (16 * 8) / 32) {
                    // Make sure number of rows in the array is divisible by number of rows filled per iteration
                    if ((8 * 5) % (16 * 8 / 32) == 0 || y + loadY < 8 * 5) {
                        const int pxIdx = loadY + y; // pixel idx in filter

                        if (pxIdx + blockPixelOffset < filterPixels && (!true || caseIdx + loadX < numImages)) {
                            const int pxZ = imgLoadModPosZ + HI24(pxDivs[pxIdx]);
                            const int pxY = imgLoadModPosY + MI16(pxDivs[pxIdx]); // pixel x,y coords in image
                            const int pxX = imgLoadModPosX + LO8(pxDivs[pxIdx]);
                            if (pxZ >= 0 && pxZ < imgSizeZ && pxY >= 0 && pxY < imgSizeY && pxX >= 0 && pxX < imgSizeX) {
                                const int pixIdx = (pxZ * imgSizeX * imgSizeY + pxY * imgSizeX + pxX) * imgStride;
                                #pragma unroll
                                for (int c = 0; c < 1; c++) {
                                    shImgLoad[(y + c * 5 * 8) * 32] = images[caseIdx + c * imgPixels * imgStride + pixIdx];
                                }
                            } else {
                                #pragma unroll
                                for (int c = 0; c < 1; c++) {
                                    shImgLoad[(y + c * 5 * 8) * 32] = 0;
                                }
                            }
                        } else {
                            #pragma unroll
                            for (int c = 0; c < 1; c++) {
                                shImgLoad[(y + c * 5 * 8) * 32] = 0;
                            }
                        }
                    }
                }
            }
            if (loadY < 16 && (!true || caseIdx + loadX < numImages)) {
                #pragma unroll
                for (int y = 0; y < 16; y += (16 * 8) / 32) {
                    // Make sure number of rows in the array is divisible by number of rows filled per iteration
                    if (16 % (16 * 8 / 32) == 0 || y + loadY < 16) {
                        shHidActLoad[y * (32 + 1)] = hidActs[caseIdx + y * numImages * numModules];
                    }
                }
            }

            __syncthreads();
            #pragma unroll
            for (int p = 0; p < 5; p++) {
                #pragma unroll
                for (int i = 0; i < 32; i++) {
                    #pragma unroll
                    for (int c = 0; c < 1; c++) {
                        prod[c][p] += shImages[threadIdx.y + p * 8 + c * 5 * 8][i] * shHidActs[threadIdx.x][i];
                    }
                }
            }
            __syncthreads();
        }
        hidActs += numImages;
    }
    
    #pragma unroll
    for (int p = 0; p < 5; p++) {
        if (blockPixelOffset + p * 8 + threadIdx.y < filterPixels) {
            #pragma unroll
            for (int c = 0; c < 1; c++) {
                targets[p * 8 * numFilters + c * filterPixels * numFilters] = scaleOutputs * prod[c][p];
            }
        }
    }
}

__global__ void kConvolve_backward(float* targets, const float* hidActs, const float* filters, 
                                   const int numModulesZ, const int numModulesY, const int numModulesX, 
                                   const int numImages, const int numFilters, const int filterSize, 
                                   const int imgSizeZ, const int imgSizeY, const int imgSizeX,
                                   const int paddingStart, const int moduleStride) {
    __shared__ float shFilters[1*16][16 + 1]; // load 16 filter one time. See below.
    __shared__ float shHidActs[16][16*2]; // each block deal with 16 * imgPerThread images.

    const int blockCaseIdx = blockIdx.x * 16 * 2;
    const int numRegionsX = DIVUP(imgSizeX, 4);
    const int numRegionsY = DIVUP(imgSizeY, 4);
    const int blockRegionIdx = blockIdx.y;
    const int blockRegionIdxX = blockRegionIdx % numRegionsX;
    const int blockRegionIdxY = (blockRegionIdx / numRegionsX) % numRegionsY;
    const int blockRegionIdxZ = blockRegionIdx / (numRegionsX * numRegionsY);
    const int blockRegionLeft = blockRegionIdxX * 4;
    const int blockRegionTop = blockRegionIdxY * 4;
    const int blockRegionFront = blockRegionIdxZ;
    const int pxYInRegion = threadIdx.y / 4, pxXInRegion = threadIdx.y % 4;
    const int pxZ = blockRegionFront;
    const int pxY = blockRegionTop + pxYInRegion;
    const int pxX = blockRegionLeft + pxXInRegion;
    const int pxIdx = pxZ * imgSizeX * imgSizeY + pxY * imgSizeX + pxX;
    const bool isPxInImg = pxZ < imgSizeZ && pxY < imgSizeY && pxX < imgSizeX;
    const int numModules = numModulesZ * numModulesY * numModulesX;
    const int filterPixels = filterSize * filterSize * filterSize;
    const int imgPixels = imgSizeZ * imgSizeX * imgSizeY;
    const int tidx = threadIdx.y * 16 + threadIdx.x;
    const int loadY = tidx / 32, loadX = tidx % 32; // load 32 cases one time.

    hidActs += blockCaseIdx + loadY * numImages * numModules + loadX;
    filters += threadIdx.x;
    targets += pxIdx * numImages + blockCaseIdx + threadIdx.x;


    float prod[1][2];
    #pragma unroll
    for (int c = 0; c < 1; c++) {
        #pragma unroll
        for (int i = 0; i < 2; i++) {
            prod[c][i] = 0;
        }
    }
    const int startZ = blockRegionFront - paddingStart < filterSize ? 0
                        : 1 + (blockRegionFront - paddingStart -filterSize) / moduleStride;
    const int endZ = MIN(numModulesZ, 1 + (blockRegionFront + 3 - paddingStart) / moduleStride);
    const int startY = blockRegionTop - paddingStart < filterSize ? 0
                        : 1 + (blockRegionTop - paddingStart - filterSize) / moduleStride;
    const int endY = MIN(numModulesY, 1 + (blockRegionTop + 3 - paddingStart) / moduleStride);
    const int startX = blockRegionLeft - paddingStart < filterSize ? 0
                        : 1 + (blockRegionLeft - paddingStart - filterSize) / moduleStride;
    const int endX = MIN(numModulesX, 1 + (blockRegionLeft + 3 - paddingStart) / moduleStride);
    
    float* shilterLoad = &shFilters[threadIdx.y][threadIdx.x];
    float* shHidActLoad = &shHidActs[loadY][loadX];
    for (int mz = startZ; mz  < endZ; mz++){
        const int moduleFront = paddingStart + mz * moduleStride;
        const int pxInModuleZ = pxZ - moduleFront;

        for (int my = startY; my < endY; my++) {
            const int moduleTop = paddingStart + my * moduleStride;
            const int pxInModuleY = pxY - moduleTop;

            for (int mx = startX; mx < endX; mx++) {
                const int moduleIdx = mz * numModulesX * numModulesY + my * numModulesX + mx;
                const int moduleLeft = paddingStart + mx * moduleStride;
                const int pxInModuleX = pxX - moduleLeft;

                const bool isPxInModule = pxInModuleZ >= 0 && pxInModuleZ < filterSize && pxInModuleY >= 0 && pxInModuleY < filterSize && pxInModuleX >= 0 && pxInModuleX < filterSize;
                const int pxIdxInModule = pxInModuleZ * filterSize * filterSize + pxInModuleY * filterSize + pxInModuleX;

                for (int f = 0; f < numFilters; f += 16) { // multiply with 16 filters at a time
                    // Now the threads split up into half-warps, and each half-warp decides if it's interested.
                    const float* hLoad = &hidActs[(moduleIdx + f * numModules) * numImages];
                    #pragma unroll
                    for (int i = 0; i < 2 * 16; i += 32) { // IMAGES
                        if (!true || blockCaseIdx + i + loadX < numImages) {
                            #pragma unroll
                            for (int j = 0; j < 16; j += 8) { // load 16 rows of 2*16 cols, 8 * 32 elements at a time.
                                shHidActLoad[j * 16 * 2 + i] = hLoad[j * numModules * numImages + i];
                            }
                        } else {
                            #pragma unroll
                            for (int j = 0; j < 16; j += 8) { // load 16 rows of 2*16 cols, 8 * 32 elements at a time.
                                shHidActLoad[j * 16 * 2 + i] = 0;
                            }
                        }
                    }
                    
                    if (isPxInImg && isPxInModule) {
                        // This half-warp is interested, so it's going to load the weights from this module to its pixel.
                        // Not fully coalesced read :(
                        // But taking out this read entirely only reduces the runtime by ~2.8%, so it isn't costing me much.
                        const float* fLoad = true ? &filters[pxIdxInModule * numFilters + f]
                                                  : &filters[(moduleIdx * 1 * filterPixels + pxIdxInModule) * numFilters + f];
                        #pragma unroll
                        for (int c = 0; c < 1; c++) {
                            shilterLoad[c * 16 * (16 + 1)] = fLoad[c * filterPixels * numFilters];
                        }

                        
                    }

                    __syncthreads();
                    // Do some actual computation
                    if (isPxInImg && isPxInModule) {
                        #pragma unroll
                        for (int c = 0; c < 1; c++) {
                            #pragma unroll
                            for (int w = 0; w < 16; w++) {
                                #pragma unroll
                                for (int i = 0; i < 2; i++) {
                                    prod[c][i] += shFilters[threadIdx.y + c * 16][w] * shHidActs[w][threadIdx.x + i * 16];
                                }
                            }
                        }
                    }
                    __syncthreads();
                }
            }
        }
    }
    // Not fully coalesced write :(... shmem (and fully coalesced) version is actually slightly slower, though
    if (isPxInImg) {
        #pragma unroll
        for (int i = 0; i < 2; i++) {
            if (!true || blockCaseIdx + threadIdx.x + i * 16 < numImages) {
                #pragma unroll
                for (int c = 0; c < 1; c++) {
                    targets[c * imgPixels * numImages + i * 16] = prod[c][i];
                }
            }
        }
    }
}

__global__ void kConvolve_forward_c(float* targets, float* images, float* filters,
                                       const int numImages, const int numFilters,
                                       const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int filterSize, const int paddingStart,
                                       const int moduleStride,
                                       const int numModulesZ, const int numModulesY, const int numModulesX, const int imgStride, const int numImgColors,
                                       const int numGroups) {
    __shared__ float shFilters[4*2][4 * 8]; // pre-load 4 pixels from 4*8 filters
    __shared__ float shImages[4*2][32 * 1]; // pre-load 4 pixels from 32*1 images
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;
    const int filterPixels = filterSize * filterSize * filterSize;
    const int numFilterColors = numImgColors / numGroups;
    const int blocksPerModule = numFilters / (4*8);
    const int moduleIdx = blockIdx.y / blocksPerModule;
    const int blockFilterIdx = 8 * 4 * (blockIdx.y % blocksPerModule);
    const int numFiltersPerGroup = numFilters / numGroups;
    const int blockGroupIdx = blockFilterIdx / numFiltersPerGroup;

    const int numModules = numModulesX * numModulesY * numModulesZ;
    const int blockColorIdx = numFilterColors * blockGroupIdx;

    const int tidx = threadIdx.y * 32 + threadIdx.x;

    const int imgLoadModPosZ = paddingStart + (moduleIdx / (numModulesX * numModulesY)) * moduleStride;
    const int imgLoadModPosY = paddingStart + ((moduleIdx / numModulesX) % numModulesY) * moduleStride;
    const int imgLoadModPosX = paddingStart + (moduleIdx % numModulesX) * moduleStride;

    const int shFilterLoadY = tidx / (4 * 8);
    const int shFilterLoadX = tidx % (4 * 8);
    const int myImgIdx = blockIdx.x * 32 * 1 + threadIdx.x;

    images += blockColorIdx * imgPixels * imgStride + myImgIdx;
    filters +=blockFilterIdx
            + shFilterLoadY * numFilters + shFilterLoadX;
    targets += moduleIdx * numImages
            + (blockFilterIdx + threadIdx.y) * numImages * numModules
            + myImgIdx;

    float prod[8][1];
    #pragma unroll
    for(int f = 0; f < 8; f++) {
        #pragma unroll
        for(int g = 0; g < 1; g++) {
            prod[f][g] = 0;
        }
    }
//    __shared__ int imgPos[]
    for (int oc = 0; oc < numFilterColors; oc += 2) { // oc stands for outer color (loop)
        for (int p = 0; p < filterPixels; p += 4) {
            /*
             * Load 4 pixels from 4*8 filters
             */
            if (shFilterLoadY < 4) {
                #pragma unroll
                for (int p2 = 0; p2 < 4; p2 += 32/8) {
                    if (p + p2 + shFilterLoadY < filterPixels) {
                        #pragma unroll
                        for (int c = 0; c < 2; c++) {
                            shFilters[shFilterLoadY + p2 + c * 4][shFilterLoadX] = filters[((oc+c) * filterPixels + p + p2) * numFilters];
                        }
                    } else {
                        #pragma unroll
                        for (int c = 0; c < 2; c++) {
                            shFilters[shFilterLoadY + p2 + c * 4][shFilterLoadX] = 0;
                        }
                    }
                }
            }

            /*
             * Load 4 pixels from 32*1 images
             */
            const int pixIdx = p + threadIdx.y;
            if (pixIdx < filterPixels) {
                const int x = imgLoadModPosX + pixIdx % filterSize;
                const int y = imgLoadModPosY + (pixIdx / filterSize) % filterSize;
                const int z = imgLoadModPosZ + pixIdx / (filterSize * filterSize);
                if (z >= 0 && z < imgSizeZ && y >= 0 && y < imgSizeY && x >= 0 && x < imgSizeX) {
                    float* m = &images[imgStride * (oc * imgPixels + z * imgSizeX * imgSizeY + y * imgSizeX + x)];
                    #pragma unroll
                    for (int i = 0; i < 1; i++) {
                        if (!true || myImgIdx + i * 32 < numImages) {
                            #pragma unroll
                            for (int c = 0; c < 2; c++) {
                                shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = m[c * imgStride * imgPixels + i * 32];
                            }
                        } else {
                            #pragma unroll
                            for (int c = 0; c < 2; c++) {
                                shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = 0;
                            }
                        }
                    }
                } else { // Padding
                    #pragma unroll
                    for (int i = 0; i < 1; i++) {
                        #pragma unroll
                        for (int c = 0; c < 2; c++) {
                            shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = 0;
                        }
                    }
                }
            }
            __syncthreads();
            #pragma unroll
            for (int i = 0; i < 4*2; i++) {
                #pragma unroll
                for(int f = 0; f < 8; f++) {
                    #pragma unroll
                    for(int g = 0; g < 1; g++) {
                        prod[f][g] += shImages[i][g * 32 + threadIdx.x] * shFilters[i][threadIdx.y + f * 4];
                    }
                }

            }
            __syncthreads();
        }
    }

    #pragma unroll
    for (int g = 0; g < 1; g++) {
        if (!true || myImgIdx + g * 32 < numImages) {
            #pragma unroll
            for (int f = 0; f < 8; f++) {
                targets[g * 32 + f * 4 * numImages * numModules] =  prod[f][g];
            }
        }
    }
}

__global__ void kConvolve_weight_c(float* targets, float* images, float* hidActs,
                                       const int numImages, const int numFilters,
                                       const int numModulesZ, const int numModulesY, const int numModulesX,
                                       const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int filterSize,
                                       const int paddingStart, const int moduleStride, const int imgStride,
                                       const int numImgColors, const int numGroups, const int partialSum,
                                       const float scaleOutputs) {
    __shared__ float shImages[8 * 8][32]; // preload 32 cases of 4 * pixelsPerThread pixels
    __shared__ float shHidActs[2 * 16][32 + 1]; // preload 32 cases of 32 hidacts

    const int tidx = 16 * threadIdx.y + threadIdx.x;
    const int loadY = tidx / 32, loadX = tidx % 32;

    const int filterPixels = filterSize * filterSize * filterSize;
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;

    const int numFilterBlocks = numFilters / (16 * 2);
    const int outputModuleIdx = blockIdx.x / numFilterBlocks;
    const int moduleIdx = partialSum * outputModuleIdx;
    const int blockFilterIdx = 2 * 16 * (blockIdx.x % numFilterBlocks);
    const int numModules = numModulesZ * numModulesY * numModulesX;
    
    const int numFiltersPerGroup = numFilters / numGroups;
    const int blockGroupIdx = blockFilterIdx / numFiltersPerGroup;
    const int numFilterColors = numImgColors / numGroups;
    
    const int blockPixelOffset = (blockIdx.y / (numFilterColors/8)) * 8;
    const int filterColorIdx = (blockIdx.y % (numFilterColors/8)) * 8;
    const int imgColorIdx = filterColorIdx + blockGroupIdx * numFilterColors;

    images += imgColorIdx * imgPixels * imgStride + loadX;

    hidActs += moduleIdx * numImages
            + blockFilterIdx * numImages * numModules
            + loadY * numImages * numModules
            + loadX;
    
    targets += outputModuleIdx * numFilters * filterPixels * numFilterColors
            + filterColorIdx * filterPixels * numFilters
            + blockPixelOffset * numFilters
            + blockFilterIdx
            + threadIdx.y * numFilters + threadIdx.x;

    float* shHidActLoad = &shHidActs[loadY][loadX];
    float* shImgLoad = &shImages[loadY][loadX];
    float prod[8][2];
    #pragma unroll
    for (int c = 0; c < 8; c++) {
        #pragma unroll
        for (int f = 0; f < 2; f++) {
            prod[c][f] = 0;
        }
    }
    // This avoids doing a division in an inner loop
    __shared__ int pxDivs[8];
    if (tidx < 8) {
        pxDivs[tidx] = (((blockPixelOffset + tidx) / (filterSize * filterSize)) << 16) + (((blockPixelOffset + tidx) / filterSize) % filterSize << 8) + ((blockPixelOffset + tidx) % filterSize);
    }
    __syncthreads();
    for (int m = moduleIdx; m < moduleIdx + partialSum; m++) {
        const int imgLoadModPosZ = paddingStart + (m / (numModulesY * numModulesX)) * moduleStride;
        const int imgLoadModPosY = paddingStart + ((m / numModulesX) % numModulesY) * moduleStride;
        const int imgLoadModPosX = paddingStart + (m % numModulesX) * moduleStride;
        for (int caseIdx = 0; caseIdx < numImages; caseIdx += 32) {
            if (loadY < 8) {
                /*
                 * As long as 4 * 32 is divisible by 32 this will loop the right
                 * number of times.
                 *
                 * This will load some images from filter pixels that don't exist (it'll set those to 0),
                 * but the code does not produce any output for those pixels (see last lines).
                 */
    //            #pragma unroll
                for (int y = 0; y < 8; y += (16 * 8) / 32) {
                    // Make sure number of rows in the array is divisible by number of rows filled per iteration
                    if (8 % (16 * 8 / 32) == 0 || y + loadY < 8) {
                        const int pxIdx = loadY + y; // pixel idx in filter

                        if (pxIdx + blockPixelOffset < filterPixels && (!true || caseIdx + loadX < numImages)) {
                            const int pxZ = imgLoadModPosZ + HI24(pxDivs[pxIdx]);
                            const int pxY = imgLoadModPosY + MI16(pxDivs[pxIdx]);//pxIdx / filterSize; // pixel x,y coords in image
                            const int pxX = imgLoadModPosX + LO8(pxDivs[pxIdx]);
                            if (pxZ >= 0 && pxZ < imgSizeZ && pxY >= 0 && pxY < imgSizeY && pxX >= 0 && pxX < imgSizeX) {
                                const int pixIdx = (pxZ * imgSizeX * imgSizeY + pxY * imgSizeX + pxX) * imgStride; // pixel idx in image
                                #pragma unroll
                                for (int c = 0; c < 8; c++) {
                                    shImgLoad[(y + c * 8) * 32] = images[caseIdx + c * imgPixels * imgStride + pixIdx];
                                }
                            } else {
                                #pragma unroll
                                for (int c = 0; c < 8; c++) {
                                    shImgLoad[(y + c * 8) * 32] = 0;
                                }
                            }
                        } else {
                            #pragma unroll
                            for (int c = 0; c < 8; c++) {
                                shImgLoad[(y + c * 8) * 32] = 0;
                            }
                        }
                    }
                }
            }
            if (loadY < 16 * 2 && (!true || caseIdx + loadX < numImages)) {
                #pragma unroll
                for (int y = 0; y < 16 * 2; y += (16 * 8) / 32) {
                    // Make sure number of rows in the array is divisible by number of rows filled per iteration
                    if ((16 * 2) % (16 * 8 / 32) == 0 || y + loadY < 16 * 2) {
                        shHidActLoad[y * (32 + 1)] = hidActs[caseIdx + y * numImages * numModules];
                    }
                }
            }

            __syncthreads();

            #pragma unroll
            for (int c = 0; c < 8; c++) {
                #pragma unroll
                for (int i = 0; i < 32; i++) {
                    #pragma unroll
                    for (int f = 0; f < 2; f++) {
                        prod[c][f] += shImages[threadIdx.y + c * 8][i] * shHidActs[threadIdx.x + f * 16][i];
                    }
                }
            }
            __syncthreads();
        }
        hidActs += numImages;
    }
    if (blockPixelOffset + threadIdx.y < filterPixels) {
        #pragma unroll
        for (int f = 0; f < 2; f++) {
            #pragma unroll
            for (int c = 0; c < 8; c++) {
                targets[c * filterPixels * numFilters + f * 16] = scaleOutputs * prod[c][f];
            }
        }
    }
}

__global__ void kConvolve_backward_c(float* targets, const float* hidActs, const float* filters, 
                                          const int numModulesZ, const int numModulesY, const int numModulesX, const int numImages, const int numFilters,
                                          const int filterSize, const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int paddingStart, const int moduleStride,
                                          const int numImgColors, const int numGroups) {
    __shared__ float shFilters[4*4][16 + 1]; // TODO: perhaps reconsider this 16
    __shared__ float shHidActs[16][32*1];

    const int numImgBlocks = DIVUP(numImages,32*1);
    const int blockCaseIdx = (blockIdx.x % numImgBlocks) * 32*1;
    
    const int imgColorIdx = (blockIdx.x / numImgBlocks) * 4*4; // color idx globally
    const int numFilterColors = numImgColors / numGroups;
    const int blockGroupIdx = imgColorIdx / numFilterColors;
    const int filterColorIdx = imgColorIdx % numFilterColors; // color idx within group
    const int numFiltersPerGroup = numFilters / numGroups;
    const int blockFilterIdx = blockGroupIdx * numFiltersPerGroup;

    const int blockPixelIdx = blockIdx.y;
    const int blockPixelIdxX = blockPixelIdx % imgSizeX;
    const int blockPixelIdxY = (blockPixelIdx / imgSizeX) % imgSizeY;
    const int blockPixelIdxZ = blockPixelIdx / (imgSizeX * imgSizeY);

    const int filterPixels = filterSize * filterSize * filterSize;
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;
    const int tidx = threadIdx.y * 32 + threadIdx.x;
    const int hidActLoadY = tidx / 32, hidActLoadX = tidx % 32;
    const int filtersLoadY = tidx / 16, filtersLoadX = tidx % 16;
    const int numModules = numModulesZ * numModulesY * numModulesX;

    hidActs += blockCaseIdx + (blockFilterIdx + hidActLoadY) * numImages * numModules + hidActLoadX;
    filters += blockFilterIdx + (filterColorIdx + filtersLoadY) * filterPixels * numFilters + filtersLoadX;
    targets += (imgColorIdx + threadIdx.y) * imgPixels * numImages + blockPixelIdx * numImages + blockCaseIdx + threadIdx.x;

    float prod[4][1];
    #pragma unroll
    for (int c = 0; c < 4; c++) {
        #pragma unroll
        for (int i = 0; i < 1; i++) {
            prod[c][i] = 0;
        }
    }
    const int startZ = blockPixelIdxZ - paddingStart < filterSize ? 0
                        : 1 + (blockPixelIdxZ - paddingStart - filterSize) / moduleStride;
    const int endZ = MIN(numModulesZ, 1 + (blockPixelIdxZ - paddingStart) / moduleStride); 
    const int startY = blockPixelIdxY - paddingStart < filterSize ? 0
                        : 1 + (blockPixelIdxY - paddingStart - filterSize) / moduleStride;
    const int endY = MIN(numModulesY, 1 + (blockPixelIdxY - paddingStart) / moduleStride);
    const int startX = blockPixelIdxX - paddingStart < filterSize ? 0
                        : 1 + (blockPixelIdxX - paddingStart - filterSize) / moduleStride;
    const int endX = MIN(numModulesX, 1 + (blockPixelIdxX - paddingStart) / moduleStride);

    float* shFilterLoad = &shFilters[filtersLoadY][filtersLoadX];
    float* shHidActLoad = &shHidActs[hidActLoadY][hidActLoadX];
    for (int mz = startZ; mz < endZ ; mz++){
        const int moduleFront = paddingStart + mz * moduleStride;
        const int pxInFilterZ = blockPixelIdxZ - moduleFront;

        for (int my = startY; my < endY; my++) {
            const int moduleTop = paddingStart + my * moduleStride;
            const int pxInFilterY = blockPixelIdxY - moduleTop;

            for (int mx = startX; mx < endX; mx++) {
                const int moduleIdx = mz * numModulesX * numModulesY + my * numModulesX + mx;
                const int moduleLeft = paddingStart + mx * moduleStride;
                const int pxInFilterX = blockPixelIdxX - moduleLeft;
                
                const int pxIdxInFilter = pxInFilterZ * filterSize * filterSize + pxInFilterY * filterSize + pxInFilterX;

                for (int f = 0; f < numFiltersPerGroup; f += 16) { // multiply with 16 filters at a time
                    const float* hLoad = &hidActs[(moduleIdx + f * numModules) * numImages];
                    #pragma unroll
                    for (int i = 0; i < 1 * 32; i += 32) {
                        if (!true || blockCaseIdx + hidActLoadX + i < numImages) {
                            #pragma unroll
                            for (int j = 0; j < 16; j += 32*4/32) { // load 16 rows of 1*16 cols, 8 * 32 elements at a time.
                                shHidActLoad[j * 32 * 1 + i] = hLoad[j * numModules * numImages + i];
                            }
                        } else {
                            #pragma unroll
                            for (int j = 0; j < 16; j += 32*4/32) { // load 16 rows of 1*16 cols, 8 * 32 elements at a time.
                                shHidActLoad[j * 32 * 1 + i] = 0;
                            }
                        }
                    }
                    const float* fLoad = true ? &filters[pxIdxInFilter * numFilters + f]
                                              : &filters[moduleIdx * numFilterColors * filterPixels * numFilters + pxIdxInFilter * numFilters + f];
                    #pragma unroll
                    for (int i = 0; i < 4*4; i+= 32*4/16) {
                        if ((4*4) % (32*4/16) == 0 || i + filtersLoadY < 4*4) {
                            shFilterLoad[i * (16 + 1)] = fLoad[i * filterPixels * numFilters];
                        }
                    }
                    
                    __syncthreads();
                    // Do some actual computation
                    #pragma unroll
                    for (int c = 0; c < 4; c++) {
                        #pragma unroll
                        for (int w = 0; w < 16; w++) {
                            #pragma unroll
                            for (int i = 0; i < 1; i++) {
                                prod[c][i] += shFilters[c * 4 + threadIdx.y][w] * shHidActs[w][threadIdx.x + i * 32];
                            }
                        }
                    }
                    __syncthreads();
                }
            }
        }
    }
    #pragma unroll
    for (int i = 0; i < 1; i++) {
        if (!true || blockCaseIdx + threadIdx.x + i * 32 < numImages) {
            #pragma unroll
            for (int c = 0; c < 4; c++) {
                targets[c * 4 * imgPixels * numImages + i * 32] = prod[c][i];
            }
        }
    }
}


	.file	"tmpxft_0035be70_00000000-6_kFunctions.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z45__device_stub__Z18kSampleMultinomialPiPfS0_iiPiPfS0_ii
	.type	_Z45__device_stub__Z18kSampleMultinomialPiPfS0_iiPiPfS0_ii, @function
_Z45__device_stub__Z18kSampleMultinomialPiPfS0_iiPiPfS0_ii:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18kSampleMultinomialPiPfS0_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z45__device_stub__Z18kSampleMultinomialPiPfS0_iiPiPfS0_ii, .-_Z45__device_stub__Z18kSampleMultinomialPiPfS0_iiPiPfS0_ii
	.globl	_Z18kSampleMultinomialPiPfS0_ii
	.type	_Z18kSampleMultinomialPiPfS0_ii, @function
_Z18kSampleMultinomialPiPfS0_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z18kSampleMultinomialPiPfS0_iiPiPfS0_ii
	.cfi_endproc
.LFE2052:
	.size	_Z18kSampleMultinomialPiPfS0_ii, .-_Z18kSampleMultinomialPiPfS0_ii
	.globl	_Z26__device_stub__Z4kExpPfS_jPfS_j
	.type	_Z26__device_stub__Z4kExpPfS_jPfS_j, @function
_Z26__device_stub__Z4kExpPfS_jPfS_j:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z4kExpPfS_j(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z26__device_stub__Z4kExpPfS_jPfS_j, .-_Z26__device_stub__Z4kExpPfS_jPfS_j
	.globl	_Z4kExpPfS_j
	.type	_Z4kExpPfS_j, @function
_Z4kExpPfS_j:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z4kExpPfS_jPfS_j
	.cfi_endproc
.LFE2054:
	.size	_Z4kExpPfS_j, .-_Z4kExpPfS_j
	.globl	_Z31__device_stub__Z7kDividePfS_S_jPfS_S_j
	.type	_Z31__device_stub__Z7kDividePfS_S_jPfS_S_j, @function
_Z31__device_stub__Z7kDividePfS_S_jPfS_S_j:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7kDividePfS_S_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z31__device_stub__Z7kDividePfS_S_jPfS_S_j, .-_Z31__device_stub__Z7kDividePfS_S_jPfS_S_j
	.globl	_Z7kDividePfS_S_j
	.type	_Z7kDividePfS_S_j, @function
_Z7kDividePfS_S_j:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z7kDividePfS_S_jPfS_S_j
	.cfi_endproc
.LFE2056:
	.size	_Z7kDividePfS_S_j, .-_Z7kDividePfS_S_j
	.globl	_Z53__device_stub__Z17kConvolve_forwardPfS_S_iiiiiiiiiiiiPfS_S_iiiiiiiiiiii
	.type	_Z53__device_stub__Z17kConvolve_forwardPfS_S_iiiiiiiiiiiiPfS_S_iiiiiiiiiiii, @function
_Z53__device_stub__Z17kConvolve_forwardPfS_S_iiiiiiiiiiiiPfS_S_iiiiiiiiiiii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	56(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 272
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L18:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z53__device_stub__Z17kConvolve_forwardPfS_S_iiiiiiiiiiiiPfS_S_iiiiiiiiiiii, .-_Z53__device_stub__Z17kConvolve_forwardPfS_S_iiiiiiiiiiiiPfS_S_iiiiiiiiiiii
	.globl	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
	.type	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii, @function
_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z17kConvolve_forwardPfS_S_iiiiiiiiiiiiPfS_S_iiiiiiiiiiii
	.cfi_endproc
.LFE2058:
	.size	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii, .-_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
	.globl	_Z54__device_stub__Z16kConvolve_weightPfS_S_iiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiif
	.type	_Z54__device_stub__Z16kConvolve_weightPfS_S_iiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiif, @function
_Z54__device_stub__Z16kConvolve_weightPfS_S_iiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiif:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	56(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 288
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L23:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z54__device_stub__Z16kConvolve_weightPfS_S_iiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiif, .-_Z54__device_stub__Z16kConvolve_weightPfS_S_iiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiif
	.globl	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.type	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif, @function
_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z16kConvolve_weightPfS_S_iiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiif
	.cfi_endproc
.LFE2060:
	.size	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif, .-_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.globl	_Z55__device_stub__Z18kConvolve_backwardPfPKfS1_iiiiiiiiiiiPfPKfS1_iiiiiiiiiii
	.type	_Z55__device_stub__Z18kConvolve_backwardPfPKfS1_iiiiiiiiiiiPfPKfS1_iiiiiiiiiii, @function
_Z55__device_stub__Z18kConvolve_backwardPfPKfS1_iiiiiiiiiiiPfPKfS1_iiiiiiiiiii:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	64(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 272
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L28:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z55__device_stub__Z18kConvolve_backwardPfPKfS1_iiiiiiiiiiiPfPKfS1_iiiiiiiiiii, .-_Z55__device_stub__Z18kConvolve_backwardPfPKfS1_iiiiiiiiiiiPfPKfS1_iiiiiiiiiii
	.globl	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.type	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii, @function
_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z18kConvolve_backwardPfPKfS1_iiiiiiiiiiiPfPKfS1_iiiiiiiiiii
	.cfi_endproc
.LFE2062:
	.size	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii, .-_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.globl	_Z57__device_stub__Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiiiPfS_S_iiiiiiiiiiiiii
	.type	_Z57__device_stub__Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiiiPfS_S_iiiiiiiiiiiiii, @function
_Z57__device_stub__Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiiiPfS_S_iiiiiiiiiiiiii:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	56(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 288
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L33:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z57__device_stub__Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiiiPfS_S_iiiiiiiiiiiiii, .-_Z57__device_stub__Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiiiPfS_S_iiiiiiiiiiiiii
	.globl	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.type	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii, @function
_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiiiPfS_S_iiiiiiiiiiiiii
	.cfi_endproc
.LFE2064:
	.size	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii, .-_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.globl	_Z58__device_stub__Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiiiif
	.type	_Z58__device_stub__Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiiiif, @function
_Z58__device_stub__Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiiiif:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	360(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	56(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 304
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L38:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z58__device_stub__Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiiiif, .-_Z58__device_stub__Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiiiif
	.globl	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.type	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif, @function
_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiifPfS_S_iiiiiiiiiiiiiiif
	.cfi_endproc
.LFE2066:
	.size	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif, .-_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.globl	_Z59__device_stub__Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiiiPfPKfS1_iiiiiiiiiiiii
	.type	_Z59__device_stub__Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiiiPfPKfS1_iiiiiiiiiiiii, @function
_Z59__device_stub__Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiiiPfPKfS1_iiiiiiiiiiiii:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	64(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 288
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L43:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z59__device_stub__Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiiiPfPKfS1_iiiiiiiiiiiii, .-_Z59__device_stub__Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiiiPfPKfS1_iiiiiiiiiiiii
	.globl	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.type	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii, @function
_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiiiPfPKfS1_iiiiiiiiiiiii
	.cfi_endproc
.LFE2068:
	.size	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii, .-_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii"
.LC1:
	.string	"_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif"
.LC2:
	.string	"_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii"
.LC3:
	.string	"_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii"
.LC4:
	.string	"_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif"
.LC5:
	.string	"_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii"
.LC6:
	.string	"_Z7kDividePfS_S_j"
.LC7:
	.string	"_Z4kExpPfS_j"
.LC8:
	.string	"_Z18kSampleMultinomialPiPfS0_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2070:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7kDividePfS_S_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z4kExpPfS_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z18kSampleMultinomialPiPfS0_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2070:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>

#define LO8(x)      ((x) & 0x000000FF)
#define MI16(x)		(((x) & 0x0000FFFF) >> 8)
#define HI24(x)     (((x) & 0x00FFFFFF) >> 16)
#define MUL24(x,y)  ((x) * (y))
#define DIVUP(x, y) (((x) + (y) - 1) / (y))
#define MIN(a, b)   ((a) < (b) ? (a) : (b))

__global__ void kSampleMultinomial(int* output, float* distribution, float* random, int k, int n){
	
	const unsigned int id = threadIdx.x + blockIdx.x * blockDim.x;
	
	if(id < n){
		distribution += k * id;
		random += id;
		output += k * id;

		float preSum = 0, nowSum = 0;
		for(int i = 0; i < k; i++){
			nowSum += distribution[i];
			output[i] = random[0] >= preSum && random[0] < nowSum;
			preSum = nowSum;
		}
	}
}

__global__ void kExp(float* output, float* input, unsigned int numElements){
	const unsigned int id = threadIdx.x + blockIdx.x * blockDim.x;
	const unsigned int numThreads = blockDim.x * gridDim.x;

	for(int i = id; i < numElements; i += numThreads)
		output[i] = __expf(input[i]);
}

__global__ void kDivide(float* output, float* leftInput, float* rightInput, unsigned int numElements){
	const unsigned int id = threadIdx.x + blockIdx.x * blockDim.x;
	const unsigned int numThreads = blockDim.x * gridDim.x;

	for(int i = id; i < numElements; i += numThreads)
		output[i] = __fdividef(leftInput[i], rightInput[i]);
}

__global__ void kConvolve_forward(float* targets, float* images, float* filters, 
                                   const int numImages, const int numFilters,
                                   const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int filterSize, const int paddingStart,
                                   const int moduleStride,
                                   const int numModulesZ, const int numModulesY, const int numModulesX, const int imgStride) {
    __shared__ float shFilters[4*1][4 * 4]; // pre-load 4 pixels from 4*4 filters
    __shared__ float shImages[4*1][32 * 1]; // pre-load 4 pixels from 32*2 images
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;
    const int filterPixels = filterSize * filterSize * filterSize;

    const int blocksPerModule = numFilters / (4*4);
    const int moduleIdx = blockIdx.y / blocksPerModule;
    const int blockFilterIdx = blockIdx.y % blocksPerModule;

    const int tidx = threadIdx.y * 32 + threadIdx.x;

    const int imgLoadModPosZ = (moduleIdx / (numModulesX * numModulesY)) * moduleStride;
    const int imgLoadModPosY = ((moduleIdx / numModulesX) % numModulesY )* moduleStride;
    const int imgLoadModPosX = (moduleIdx % numModulesX) * moduleStride;

    const int shFilterLoadY = tidx / (4 * 4);
    const int shFilterLoadX = tidx % (4 * 4);
    const int myImgIdx = blockIdx.x * 32 * 1 + threadIdx.x;
    images += myImgIdx;
    filters += 4 * 4 * blockFilterIdx
             + shFilterLoadY * numFilters + shFilterLoadX;
    targets += moduleIdx * numImages
            + (blockFilterIdx * 4 * 4 + threadIdx.y) * numImages * numModulesZ * numModulesY * numModulesX
            + myImgIdx;


    float prod[4][1];
    #pragma unroll
    for(int f = 0; f < 4; f++) {
        #pragma unroll
        for(int g = 0; g < 1; g++) {
            prod[f][g] = 0;
        }
    }

    for (int p = 0; p < filterPixels; p += 4) {
        /*
         * Load 4 pixels from 4*4 filters
         */
        if (shFilterLoadY < 4) {
            #pragma unroll
            for (int p2 = 0; p2 < 4; p2 += 32/4) {
                if (p + p2 + shFilterLoadY < filterPixels) {
                    #pragma unroll
                    for (int c = 0; c < 1; c++) {
                        shFilters[shFilterLoadY + p2 + c * 4][shFilterLoadX] = filters[(c * filterPixels + p + p2) * numFilters];
                    }
                } else {
                    #pragma unroll
                    for (int c = 0; c < 1; c++) {
                        shFilters[shFilterLoadY + p2 + c * 4][shFilterLoadX] = 0;
                    }
                }
            }
        }

        /*
         * Load 4 pixels from 32*1 images
         */
        const int pixIdx = p + threadIdx.y;
        if (pixIdx < filterPixels) {
            const int x = paddingStart + imgLoadModPosX + pixIdx % filterSize;
            const int y = paddingStart + imgLoadModPosY + (pixIdx / filterSize) % filterSize;
            const int z = paddingStart + imgLoadModPosZ + pixIdx / (filterSize * filterSize);
            if (z >= 0 && z < imgSizeZ && y >= 0 && y < imgSizeY && x >= 0 && x < imgSizeX) {
                #pragma unroll
                for (int i = 0; i < 1; i++) {
                    if (!true || myImgIdx + i * 32 < numImages) {
                        #pragma unroll
                        for (int c = 0; c < 1; c++) {
                            shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = images[imgStride * (c * imgPixels + z * imgSizeX * imgSizeY + y * imgSizeX + x) + i * 32];
                        }
                    } else {
                        #pragma unroll
                        for (int c = 0; c < 1; c++) {
                            shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = 0;
                        }
                    }
                }
            } else { // Padding
                #pragma unroll
                for (int i = 0; i < 1; i++) {
                    #pragma unroll
                    for (int c = 0; c < 1; c++) {
                        shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = 0;
                    }
                }
            }
        }
        __syncthreads();
        #pragma unroll
        for (int i = 0; i < 4*1; i++) {
            #pragma unroll
            for(int f = 0; f < 4; f++) {
                #pragma unroll
                for(int g = 0; g < 1; g++) {
                    prod[f][g] += shImages[i][g * 32 + threadIdx.x] * shFilters[i][threadIdx.y + f * 4];
                }
            }

        }
        __syncthreads();
    }
    
    #pragma unroll
    for (int g = 0; g < 1; g++) {
        if (!true || myImgIdx + g * 32 < numImages) {
            #pragma unroll
            for (int f = 0; f < 4; f++) {
                targets[g * 32 + f * 4 * numImages * numModulesZ * numModulesY * numModulesX] = prod[f][g];
            }
        }
    }
}

__global__ void kConvolve_weight(float* targets, float* images, float* hidActs,
                                   const int numImages, const int numFilters,
                                   const int numModulesZ, const int numModulesY, const int numModulesX,
                                   const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int filterSize,
                                   const int paddingStart, const int moduleStride, const int imgStride,
                                   const int partialSum, const float scaleOutputs) {
    __shared__ float shImages[5 * 8 * 1][32]; // preload 32 cases of 8 * 5 pixels
    __shared__ float shHidActs[16][32 + 1]; // preload 32 cases of 16 hidActs

    const int tidx = 16 * threadIdx.y + threadIdx.x;
    const int loadY = tidx / 32, loadX = tidx % 32;

    const int filterPixels = filterSize * filterSize * filterSize;
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;

    const int filterBlocksPerModule = numFilters / 16;
    const int outputModuleIdx = blockIdx.x / filterBlocksPerModule;
    const int moduleIdx = partialSum * outputModuleIdx;
    const int blockFilterIdx = 16 * (blockIdx.x % filterBlocksPerModule);

//    const int moduleStride = (imgSize - filterSize + 1) / numModulesX; 
    const int numModules = numModulesZ * numModulesY * numModulesX;

    const int blockPixelOffset = blockIdx.y * 8 * 5;

    images += loadX;
    hidActs += moduleIdx * numImages
            + blockFilterIdx * numImages * numModules
            + loadY * numImages * numModules
            + loadX;
    
    targets += (outputModuleIdx * numFilters) * filterPixels * 1
            + blockPixelOffset * numFilters
            + blockFilterIdx
            + threadIdx.y * numFilters + threadIdx.x;

    float* shImgLoad = &shImages[loadY][loadX];
    float* shHidActLoad = &shHidActs[loadY][loadX];

    float prod[1][5];
    #pragma unroll
    for (int c = 0; c < 1; c++) {
        #pragma unroll
        for (int p = 0; p < 5; p++) {
            prod[c][p] = 0;
        }
    }
    
    __shared__ int pxDivs[8*5];
    if (tidx < 8 * 5) {
        pxDivs[tidx] = (((blockPixelOffset + tidx) / (filterSize * filterSize)) << 16) + (((blockPixelOffset + tidx) / filterSize) % filterSize << 8) + ((blockPixelOffset + tidx) % filterSize);
    }
    __syncthreads();
    for (int m = moduleIdx; m < moduleIdx + partialSum; m++) {
        const int imgLoadModPosZ = paddingStart + (m / (numModulesX * numModulesY)) * moduleStride;
        const int imgLoadModPosY = paddingStart + ((m / numModulesX) % numModulesY) * moduleStride;
        const int imgLoadModPosX = paddingStart + (m % numModulesX) * moduleStride;
        for (int caseIdx = 0; caseIdx < numImages; caseIdx += 32) {
            if (loadY < 8 * 5) {
                /*
                 * As long as 8 * 16 is divisible by 32 this will loop the right
                 * number of times.
                 *
                 * This will load some imgGrads from filter pixels that don't exit (it'll set those to 0),
                 * but the code does not produce any output for those pixels (see last lines).
                 */
    //            #pragma unroll
                for (int y = 0; y < 8 * 5; y += (16 * 8) / 32) {
                    // Make sure number of rows in the array is divisible by number of rows filled per iteration
                    if ((8 * 5) % (16 * 8 / 32) == 0 || y + loadY < 8 * 5) {
                        const int pxIdx = loadY + y; // pixel idx in filter

                        if (pxIdx + blockPixelOffset < filterPixels && (!true || caseIdx + loadX < numImages)) {
                            const int pxZ = imgLoadModPosZ + HI24(pxDivs[pxIdx]);
                            const int pxY = imgLoadModPosY + MI16(pxDivs[pxIdx]); // pixel x,y coords in image
                            const int pxX = imgLoadModPosX + LO8(pxDivs[pxIdx]);
                            if (pxZ >= 0 && pxZ < imgSizeZ && pxY >= 0 && pxY < imgSizeY && pxX >= 0 && pxX < imgSizeX) {
                                const int pixIdx = (pxZ * imgSizeX * imgSizeY + pxY * imgSizeX + pxX) * imgStride;
                                #pragma unroll
                                for (int c = 0; c < 1; c++) {
                                    shImgLoad[(y + c * 5 * 8) * 32] = images[caseIdx + c * imgPixels * imgStride + pixIdx];
                                }
                            } else {
                                #pragma unroll
                                for (int c = 0; c < 1; c++) {
                                    shImgLoad[(y + c * 5 * 8) * 32] = 0;
                                }
                            }
                        } else {
                            #pragma unroll
                            for (int c = 0; c < 1; c++) {
                                shImgLoad[(y + c * 5 * 8) * 32] = 0;
                            }
                        }
                    }
                }
            }
            if (loadY < 16 && (!true || caseIdx + loadX < numImages)) {
                #pragma unroll
                for (int y = 0; y < 16; y += (16 * 8) / 32) {
                    // Make sure number of rows in the array is divisible by number of rows filled per iteration
                    if (16 % (16 * 8 / 32) == 0 || y + loadY < 16) {
                        shHidActLoad[y * (32 + 1)] = hidActs[caseIdx + y * numImages * numModules];
                    }
                }
            }

            __syncthreads();
            #pragma unroll
            for (int p = 0; p < 5; p++) {
                #pragma unroll
                for (int i = 0; i < 32; i++) {
                    #pragma unroll
                    for (int c = 0; c < 1; c++) {
                        prod[c][p] += shImages[threadIdx.y + p * 8 + c * 5 * 8][i] * shHidActs[threadIdx.x][i];
                    }
                }
            }
            __syncthreads();
        }
        hidActs += numImages;
    }
    
    #pragma unroll
    for (int p = 0; p < 5; p++) {
        if (blockPixelOffset + p * 8 + threadIdx.y < filterPixels) {
            #pragma unroll
            for (int c = 0; c < 1; c++) {
                targets[p * 8 * numFilters + c * filterPixels * numFilters] = scaleOutputs * prod[c][p];
            }
        }
    }
}

__global__ void kConvolve_backward(float* targets, const float* hidActs, const float* filters, 
                                   const int numModulesZ, const int numModulesY, const int numModulesX, 
                                   const int numImages, const int numFilters, const int filterSize, 
                                   const int imgSizeZ, const int imgSizeY, const int imgSizeX,
                                   const int paddingStart, const int moduleStride) {
    __shared__ float shFilters[1*16][16 + 1]; // load 16 filter one time. See below.
    __shared__ float shHidActs[16][16*2]; // each block deal with 16 * imgPerThread images.

    const int blockCaseIdx = blockIdx.x * 16 * 2;
    const int numRegionsX = DIVUP(imgSizeX, 4);
    const int numRegionsY = DIVUP(imgSizeY, 4);
    const int blockRegionIdx = blockIdx.y;
    const int blockRegionIdxX = blockRegionIdx % numRegionsX;
    const int blockRegionIdxY = (blockRegionIdx / numRegionsX) % numRegionsY;
    const int blockRegionIdxZ = blockRegionIdx / (numRegionsX * numRegionsY);
    const int blockRegionLeft = blockRegionIdxX * 4;
    const int blockRegionTop = blockRegionIdxY * 4;
    const int blockRegionFront = blockRegionIdxZ;
    const int pxYInRegion = threadIdx.y / 4, pxXInRegion = threadIdx.y % 4;
    const int pxZ = blockRegionFront;
    const int pxY = blockRegionTop + pxYInRegion;
    const int pxX = blockRegionLeft + pxXInRegion;
    const int pxIdx = pxZ * imgSizeX * imgSizeY + pxY * imgSizeX + pxX;
    const bool isPxInImg = pxZ < imgSizeZ && pxY < imgSizeY && pxX < imgSizeX;
    const int numModules = numModulesZ * numModulesY * numModulesX;
    const int filterPixels = filterSize * filterSize * filterSize;
    const int imgPixels = imgSizeZ * imgSizeX * imgSizeY;
    const int tidx = threadIdx.y * 16 + threadIdx.x;
    const int loadY = tidx / 32, loadX = tidx % 32; // load 32 cases one time.

    hidActs += blockCaseIdx + loadY * numImages * numModules + loadX;
    filters += threadIdx.x;
    targets += pxIdx * numImages + blockCaseIdx + threadIdx.x;


    float prod[1][2];
    #pragma unroll
    for (int c = 0; c < 1; c++) {
        #pragma unroll
        for (int i = 0; i < 2; i++) {
            prod[c][i] = 0;
        }
    }
    const int startZ = blockRegionFront - paddingStart < filterSize ? 0
                        : 1 + (blockRegionFront - paddingStart -filterSize) / moduleStride;
    const int endZ = MIN(numModulesZ, 1 + (blockRegionFront + 3 - paddingStart) / moduleStride);
    const int startY = blockRegionTop - paddingStart < filterSize ? 0
                        : 1 + (blockRegionTop - paddingStart - filterSize) / moduleStride;
    const int endY = MIN(numModulesY, 1 + (blockRegionTop + 3 - paddingStart) / moduleStride);
    const int startX = blockRegionLeft - paddingStart < filterSize ? 0
                        : 1 + (blockRegionLeft - paddingStart - filterSize) / moduleStride;
    const int endX = MIN(numModulesX, 1 + (blockRegionLeft + 3 - paddingStart) / moduleStride);
    
    float* shilterLoad = &shFilters[threadIdx.y][threadIdx.x];
    float* shHidActLoad = &shHidActs[loadY][loadX];
    for (int mz = startZ; mz  < endZ; mz++){
        const int moduleFront = paddingStart + mz * moduleStride;
        const int pxInModuleZ = pxZ - moduleFront;

        for (int my = startY; my < endY; my++) {
            const int moduleTop = paddingStart + my * moduleStride;
            const int pxInModuleY = pxY - moduleTop;

            for (int mx = startX; mx < endX; mx++) {
                const int moduleIdx = mz * numModulesX * numModulesY + my * numModulesX + mx;
                const int moduleLeft = paddingStart + mx * moduleStride;
                const int pxInModuleX = pxX - moduleLeft;

                const bool isPxInModule = pxInModuleZ >= 0 && pxInModuleZ < filterSize && pxInModuleY >= 0 && pxInModuleY < filterSize && pxInModuleX >= 0 && pxInModuleX < filterSize;
                const int pxIdxInModule = pxInModuleZ * filterSize * filterSize + pxInModuleY * filterSize + pxInModuleX;

                for (int f = 0; f < numFilters; f += 16) { // multiply with 16 filters at a time
                    // Now the threads split up into half-warps, and each half-warp decides if it's interested.
                    const float* hLoad = &hidActs[(moduleIdx + f * numModules) * numImages];
                    #pragma unroll
                    for (int i = 0; i < 2 * 16; i += 32) { // IMAGES
                        if (!true || blockCaseIdx + i + loadX < numImages) {
                            #pragma unroll
                            for (int j = 0; j < 16; j += 8) { // load 16 rows of 2*16 cols, 8 * 32 elements at a time.
                                shHidActLoad[j * 16 * 2 + i] = hLoad[j * numModules * numImages + i];
                            }
                        } else {
                            #pragma unroll
                            for (int j = 0; j < 16; j += 8) { // load 16 rows of 2*16 cols, 8 * 32 elements at a time.
                                shHidActLoad[j * 16 * 2 + i] = 0;
                            }
                        }
                    }
                    
                    if (isPxInImg && isPxInModule) {
                        // This half-warp is interested, so it's going to load the weights from this module to its pixel.
                        // Not fully coalesced read :(
                        // But taking out this read entirely only reduces the runtime by ~2.8%, so it isn't costing me much.
                        const float* fLoad = true ? &filters[pxIdxInModule * numFilters + f]
                                                  : &filters[(moduleIdx * 1 * filterPixels + pxIdxInModule) * numFilters + f];
                        #pragma unroll
                        for (int c = 0; c < 1; c++) {
                            shilterLoad[c * 16 * (16 + 1)] = fLoad[c * filterPixels * numFilters];
                        }

                        
                    }

                    __syncthreads();
                    // Do some actual computation
                    if (isPxInImg && isPxInModule) {
                        #pragma unroll
                        for (int c = 0; c < 1; c++) {
                            #pragma unroll
                            for (int w = 0; w < 16; w++) {
                                #pragma unroll
                                for (int i = 0; i < 2; i++) {
                                    prod[c][i] += shFilters[threadIdx.y + c * 16][w] * shHidActs[w][threadIdx.x + i * 16];
                                }
                            }
                        }
                    }
                    __syncthreads();
                }
            }
        }
    }
    // Not fully coalesced write :(... shmem (and fully coalesced) version is actually slightly slower, though
    if (isPxInImg) {
        #pragma unroll
        for (int i = 0; i < 2; i++) {
            if (!true || blockCaseIdx + threadIdx.x + i * 16 < numImages) {
                #pragma unroll
                for (int c = 0; c < 1; c++) {
                    targets[c * imgPixels * numImages + i * 16] = prod[c][i];
                }
            }
        }
    }
}

__global__ void kConvolve_forward_c(float* targets, float* images, float* filters,
                                       const int numImages, const int numFilters,
                                       const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int filterSize, const int paddingStart,
                                       const int moduleStride,
                                       const int numModulesZ, const int numModulesY, const int numModulesX, const int imgStride, const int numImgColors,
                                       const int numGroups) {
    __shared__ float shFilters[4*2][4 * 8]; // pre-load 4 pixels from 4*8 filters
    __shared__ float shImages[4*2][32 * 1]; // pre-load 4 pixels from 32*1 images
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;
    const int filterPixels = filterSize * filterSize * filterSize;
    const int numFilterColors = numImgColors / numGroups;
    const int blocksPerModule = numFilters / (4*8);
    const int moduleIdx = blockIdx.y / blocksPerModule;
    const int blockFilterIdx = 8 * 4 * (blockIdx.y % blocksPerModule);
    const int numFiltersPerGroup = numFilters / numGroups;
    const int blockGroupIdx = blockFilterIdx / numFiltersPerGroup;

    const int numModules = numModulesX * numModulesY * numModulesZ;
    const int blockColorIdx = numFilterColors * blockGroupIdx;

    const int tidx = threadIdx.y * 32 + threadIdx.x;

    const int imgLoadModPosZ = paddingStart + (moduleIdx / (numModulesX * numModulesY)) * moduleStride;
    const int imgLoadModPosY = paddingStart + ((moduleIdx / numModulesX) % numModulesY) * moduleStride;
    const int imgLoadModPosX = paddingStart + (moduleIdx % numModulesX) * moduleStride;

    const int shFilterLoadY = tidx / (4 * 8);
    const int shFilterLoadX = tidx % (4 * 8);
    const int myImgIdx = blockIdx.x * 32 * 1 + threadIdx.x;

    images += blockColorIdx * imgPixels * imgStride + myImgIdx;
    filters +=blockFilterIdx
            + shFilterLoadY * numFilters + shFilterLoadX;
    targets += moduleIdx * numImages
            + (blockFilterIdx + threadIdx.y) * numImages * numModules
            + myImgIdx;

    float prod[8][1];
    #pragma unroll
    for(int f = 0; f < 8; f++) {
        #pragma unroll
        for(int g = 0; g < 1; g++) {
            prod[f][g] = 0;
        }
    }
//    __shared__ int imgPos[]
    for (int oc = 0; oc < numFilterColors; oc += 2) { // oc stands for outer color (loop)
        for (int p = 0; p < filterPixels; p += 4) {
            /*
             * Load 4 pixels from 4*8 filters
             */
            if (shFilterLoadY < 4) {
                #pragma unroll
                for (int p2 = 0; p2 < 4; p2 += 32/8) {
                    if (p + p2 + shFilterLoadY < filterPixels) {
                        #pragma unroll
                        for (int c = 0; c < 2; c++) {
                            shFilters[shFilterLoadY + p2 + c * 4][shFilterLoadX] = filters[((oc+c) * filterPixels + p + p2) * numFilters];
                        }
                    } else {
                        #pragma unroll
                        for (int c = 0; c < 2; c++) {
                            shFilters[shFilterLoadY + p2 + c * 4][shFilterLoadX] = 0;
                        }
                    }
                }
            }

            /*
             * Load 4 pixels from 32*1 images
             */
            const int pixIdx = p + threadIdx.y;
            if (pixIdx < filterPixels) {
                const int x = imgLoadModPosX + pixIdx % filterSize;
                const int y = imgLoadModPosY + (pixIdx / filterSize) % filterSize;
                const int z = imgLoadModPosZ + pixIdx / (filterSize * filterSize);
                if (z >= 0 && z < imgSizeZ && y >= 0 && y < imgSizeY && x >= 0 && x < imgSizeX) {
                    float* m = &images[imgStride * (oc * imgPixels + z * imgSizeX * imgSizeY + y * imgSizeX + x)];
                    #pragma unroll
                    for (int i = 0; i < 1; i++) {
                        if (!true || myImgIdx + i * 32 < numImages) {
                            #pragma unroll
                            for (int c = 0; c < 2; c++) {
                                shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = m[c * imgStride * imgPixels + i * 32];
                            }
                        } else {
                            #pragma unroll
                            for (int c = 0; c < 2; c++) {
                                shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = 0;
                            }
                        }
                    }
                } else { // Padding
                    #pragma unroll
                    for (int i = 0; i < 1; i++) {
                        #pragma unroll
                        for (int c = 0; c < 2; c++) {
                            shImages[threadIdx.y + c * 4][threadIdx.x + i * 32] = 0;
                        }
                    }
                }
            }
            __syncthreads();
            #pragma unroll
            for (int i = 0; i < 4*2; i++) {
                #pragma unroll
                for(int f = 0; f < 8; f++) {
                    #pragma unroll
                    for(int g = 0; g < 1; g++) {
                        prod[f][g] += shImages[i][g * 32 + threadIdx.x] * shFilters[i][threadIdx.y + f * 4];
                    }
                }

            }
            __syncthreads();
        }
    }

    #pragma unroll
    for (int g = 0; g < 1; g++) {
        if (!true || myImgIdx + g * 32 < numImages) {
            #pragma unroll
            for (int f = 0; f < 8; f++) {
                targets[g * 32 + f * 4 * numImages * numModules] =  prod[f][g];
            }
        }
    }
}

__global__ void kConvolve_weight_c(float* targets, float* images, float* hidActs,
                                       const int numImages, const int numFilters,
                                       const int numModulesZ, const int numModulesY, const int numModulesX,
                                       const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int filterSize,
                                       const int paddingStart, const int moduleStride, const int imgStride,
                                       const int numImgColors, const int numGroups, const int partialSum,
                                       const float scaleOutputs) {
    __shared__ float shImages[8 * 8][32]; // preload 32 cases of 4 * pixelsPerThread pixels
    __shared__ float shHidActs[2 * 16][32 + 1]; // preload 32 cases of 32 hidacts

    const int tidx = 16 * threadIdx.y + threadIdx.x;
    const int loadY = tidx / 32, loadX = tidx % 32;

    const int filterPixels = filterSize * filterSize * filterSize;
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;

    const int numFilterBlocks = numFilters / (16 * 2);
    const int outputModuleIdx = blockIdx.x / numFilterBlocks;
    const int moduleIdx = partialSum * outputModuleIdx;
    const int blockFilterIdx = 2 * 16 * (blockIdx.x % numFilterBlocks);
    const int numModules = numModulesZ * numModulesY * numModulesX;
    
    const int numFiltersPerGroup = numFilters / numGroups;
    const int blockGroupIdx = blockFilterIdx / numFiltersPerGroup;
    const int numFilterColors = numImgColors / numGroups;
    
    const int blockPixelOffset = (blockIdx.y / (numFilterColors/8)) * 8;
    const int filterColorIdx = (blockIdx.y % (numFilterColors/8)) * 8;
    const int imgColorIdx = filterColorIdx + blockGroupIdx * numFilterColors;

    images += imgColorIdx * imgPixels * imgStride + loadX;

    hidActs += moduleIdx * numImages
            + blockFilterIdx * numImages * numModules
            + loadY * numImages * numModules
            + loadX;
    
    targets += outputModuleIdx * numFilters * filterPixels * numFilterColors
            + filterColorIdx * filterPixels * numFilters
            + blockPixelOffset * numFilters
            + blockFilterIdx
            + threadIdx.y * numFilters + threadIdx.x;

    float* shHidActLoad = &shHidActs[loadY][loadX];
    float* shImgLoad = &shImages[loadY][loadX];
    float prod[8][2];
    #pragma unroll
    for (int c = 0; c < 8; c++) {
        #pragma unroll
        for (int f = 0; f < 2; f++) {
            prod[c][f] = 0;
        }
    }
    // This avoids doing a division in an inner loop
    __shared__ int pxDivs[8];
    if (tidx < 8) {
        pxDivs[tidx] = (((blockPixelOffset + tidx) / (filterSize * filterSize)) << 16) + (((blockPixelOffset + tidx) / filterSize) % filterSize << 8) + ((blockPixelOffset + tidx) % filterSize);
    }
    __syncthreads();
    for (int m = moduleIdx; m < moduleIdx + partialSum; m++) {
        const int imgLoadModPosZ = paddingStart + (m / (numModulesY * numModulesX)) * moduleStride;
        const int imgLoadModPosY = paddingStart + ((m / numModulesX) % numModulesY) * moduleStride;
        const int imgLoadModPosX = paddingStart + (m % numModulesX) * moduleStride;
        for (int caseIdx = 0; caseIdx < numImages; caseIdx += 32) {
            if (loadY < 8) {
                /*
                 * As long as 4 * 32 is divisible by 32 this will loop the right
                 * number of times.
                 *
                 * This will load some images from filter pixels that don't exist (it'll set those to 0),
                 * but the code does not produce any output for those pixels (see last lines).
                 */
    //            #pragma unroll
                for (int y = 0; y < 8; y += (16 * 8) / 32) {
                    // Make sure number of rows in the array is divisible by number of rows filled per iteration
                    if (8 % (16 * 8 / 32) == 0 || y + loadY < 8) {
                        const int pxIdx = loadY + y; // pixel idx in filter

                        if (pxIdx + blockPixelOffset < filterPixels && (!true || caseIdx + loadX < numImages)) {
                            const int pxZ = imgLoadModPosZ + HI24(pxDivs[pxIdx]);
                            const int pxY = imgLoadModPosY + MI16(pxDivs[pxIdx]);//pxIdx / filterSize; // pixel x,y coords in image
                            const int pxX = imgLoadModPosX + LO8(pxDivs[pxIdx]);
                            if (pxZ >= 0 && pxZ < imgSizeZ && pxY >= 0 && pxY < imgSizeY && pxX >= 0 && pxX < imgSizeX) {
                                const int pixIdx = (pxZ * imgSizeX * imgSizeY + pxY * imgSizeX + pxX) * imgStride; // pixel idx in image
                                #pragma unroll
                                for (int c = 0; c < 8; c++) {
                                    shImgLoad[(y + c * 8) * 32] = images[caseIdx + c * imgPixels * imgStride + pixIdx];
                                }
                            } else {
                                #pragma unroll
                                for (int c = 0; c < 8; c++) {
                                    shImgLoad[(y + c * 8) * 32] = 0;
                                }
                            }
                        } else {
                            #pragma unroll
                            for (int c = 0; c < 8; c++) {
                                shImgLoad[(y + c * 8) * 32] = 0;
                            }
                        }
                    }
                }
            }
            if (loadY < 16 * 2 && (!true || caseIdx + loadX < numImages)) {
                #pragma unroll
                for (int y = 0; y < 16 * 2; y += (16 * 8) / 32) {
                    // Make sure number of rows in the array is divisible by number of rows filled per iteration
                    if ((16 * 2) % (16 * 8 / 32) == 0 || y + loadY < 16 * 2) {
                        shHidActLoad[y * (32 + 1)] = hidActs[caseIdx + y * numImages * numModules];
                    }
                }
            }

            __syncthreads();

            #pragma unroll
            for (int c = 0; c < 8; c++) {
                #pragma unroll
                for (int i = 0; i < 32; i++) {
                    #pragma unroll
                    for (int f = 0; f < 2; f++) {
                        prod[c][f] += shImages[threadIdx.y + c * 8][i] * shHidActs[threadIdx.x + f * 16][i];
                    }
                }
            }
            __syncthreads();
        }
        hidActs += numImages;
    }
    if (blockPixelOffset + threadIdx.y < filterPixels) {
        #pragma unroll
        for (int f = 0; f < 2; f++) {
            #pragma unroll
            for (int c = 0; c < 8; c++) {
                targets[c * filterPixels * numFilters + f * 16] = scaleOutputs * prod[c][f];
            }
        }
    }
}

__global__ void kConvolve_backward_c(float* targets, const float* hidActs, const float* filters, 
                                          const int numModulesZ, const int numModulesY, const int numModulesX, const int numImages, const int numFilters,
                                          const int filterSize, const int imgSizeZ, const int imgSizeY, const int imgSizeX, const int paddingStart, const int moduleStride,
                                          const int numImgColors, const int numGroups) {
    __shared__ float shFilters[4*4][16 + 1]; // TODO: perhaps reconsider this 16
    __shared__ float shHidActs[16][32*1];

    const int numImgBlocks = DIVUP(numImages,32*1);
    const int blockCaseIdx = (blockIdx.x % numImgBlocks) * 32*1;
    
    const int imgColorIdx = (blockIdx.x / numImgBlocks) * 4*4; // color idx globally
    const int numFilterColors = numImgColors / numGroups;
    const int blockGroupIdx = imgColorIdx / numFilterColors;
    const int filterColorIdx = imgColorIdx % numFilterColors; // color idx within group
    const int numFiltersPerGroup = numFilters / numGroups;
    const int blockFilterIdx = blockGroupIdx * numFiltersPerGroup;

    const int blockPixelIdx = blockIdx.y;
    const int blockPixelIdxX = blockPixelIdx % imgSizeX;
    const int blockPixelIdxY = (blockPixelIdx / imgSizeX) % imgSizeY;
    const int blockPixelIdxZ = blockPixelIdx / (imgSizeX * imgSizeY);

    const int filterPixels = filterSize * filterSize * filterSize;
    const int imgPixels = imgSizeZ * imgSizeY * imgSizeX;
    const int tidx = threadIdx.y * 32 + threadIdx.x;
    const int hidActLoadY = tidx / 32, hidActLoadX = tidx % 32;
    const int filtersLoadY = tidx / 16, filtersLoadX = tidx % 16;
    const int numModules = numModulesZ * numModulesY * numModulesX;

    hidActs += blockCaseIdx + (blockFilterIdx + hidActLoadY) * numImages * numModules + hidActLoadX;
    filters += blockFilterIdx + (filterColorIdx + filtersLoadY) * filterPixels * numFilters + filtersLoadX;
    targets += (imgColorIdx + threadIdx.y) * imgPixels * numImages + blockPixelIdx * numImages + blockCaseIdx + threadIdx.x;

    float prod[4][1];
    #pragma unroll
    for (int c = 0; c < 4; c++) {
        #pragma unroll
        for (int i = 0; i < 1; i++) {
            prod[c][i] = 0;
        }
    }
    const int startZ = blockPixelIdxZ - paddingStart < filterSize ? 0
                        : 1 + (blockPixelIdxZ - paddingStart - filterSize) / moduleStride;
    const int endZ = MIN(numModulesZ, 1 + (blockPixelIdxZ - paddingStart) / moduleStride); 
    const int startY = blockPixelIdxY - paddingStart < filterSize ? 0
                        : 1 + (blockPixelIdxY - paddingStart - filterSize) / moduleStride;
    const int endY = MIN(numModulesY, 1 + (blockPixelIdxY - paddingStart) / moduleStride);
    const int startX = blockPixelIdxX - paddingStart < filterSize ? 0
                        : 1 + (blockPixelIdxX - paddingStart - filterSize) / moduleStride;
    const int endX = MIN(numModulesX, 1 + (blockPixelIdxX - paddingStart) / moduleStride);

    float* shFilterLoad = &shFilters[filtersLoadY][filtersLoadX];
    float* shHidActLoad = &shHidActs[hidActLoadY][hidActLoadX];
    for (int mz = startZ; mz < endZ ; mz++){
        const int moduleFront = paddingStart + mz * moduleStride;
        const int pxInFilterZ = blockPixelIdxZ - moduleFront;

        for (int my = startY; my < endY; my++) {
            const int moduleTop = paddingStart + my * moduleStride;
            const int pxInFilterY = blockPixelIdxY - moduleTop;

            for (int mx = startX; mx < endX; mx++) {
                const int moduleIdx = mz * numModulesX * numModulesY + my * numModulesX + mx;
                const int moduleLeft = paddingStart + mx * moduleStride;
                const int pxInFilterX = blockPixelIdxX - moduleLeft;
                
                const int pxIdxInFilter = pxInFilterZ * filterSize * filterSize + pxInFilterY * filterSize + pxInFilterX;

                for (int f = 0; f < numFiltersPerGroup; f += 16) { // multiply with 16 filters at a time
                    const float* hLoad = &hidActs[(moduleIdx + f * numModules) * numImages];
                    #pragma unroll
                    for (int i = 0; i < 1 * 32; i += 32) {
                        if (!true || blockCaseIdx + hidActLoadX + i < numImages) {
                            #pragma unroll
                            for (int j = 0; j < 16; j += 32*4/32) { // load 16 rows of 1*16 cols, 8 * 32 elements at a time.
                                shHidActLoad[j * 32 * 1 + i] = hLoad[j * numModules * numImages + i];
                            }
                        } else {
                            #pragma unroll
                            for (int j = 0; j < 16; j += 32*4/32) { // load 16 rows of 1*16 cols, 8 * 32 elements at a time.
                                shHidActLoad[j * 32 * 1 + i] = 0;
                            }
                        }
                    }
                    const float* fLoad = true ? &filters[pxIdxInFilter * numFilters + f]
                                              : &filters[moduleIdx * numFilterColors * filterPixels * numFilters + pxIdxInFilter * numFilters + f];
                    #pragma unroll
                    for (int i = 0; i < 4*4; i+= 32*4/16) {
                        if ((4*4) % (32*4/16) == 0 || i + filtersLoadY < 4*4) {
                            shFilterLoad[i * (16 + 1)] = fLoad[i * filterPixels * numFilters];
                        }
                    }
                    
                    __syncthreads();
                    // Do some actual computation
                    #pragma unroll
                    for (int c = 0; c < 4; c++) {
                        #pragma unroll
                        for (int w = 0; w < 16; w++) {
                            #pragma unroll
                            for (int i = 0; i < 1; i++) {
                                prod[c][i] += shFilters[c * 4 + threadIdx.y][w] * shHidActs[w][threadIdx.x + i * 32];
                            }
                        }
                    }
                    __syncthreads();
                }
            }
        }
    }
    #pragma unroll
    for (int i = 0; i < 1; i++) {
        if (!true || blockCaseIdx + threadIdx.x + i * 32 < numImages) {
            #pragma unroll
            for (int c = 0; c < 4; c++) {
                targets[c * 4 * imgPixels * numImages + i * 32] = prod[c][i];
            }
        }
    }
}


	.text
	.file	"kFunctions.hip"
	.globl	_Z33__device_stub__kSampleMultinomialPiPfS0_ii # -- Begin function _Z33__device_stub__kSampleMultinomialPiPfS0_ii
	.type	_Z33__device_stub__kSampleMultinomialPiPfS0_ii,@function
_Z33__device_stub__kSampleMultinomialPiPfS0_ii: # @_Z33__device_stub__kSampleMultinomialPiPfS0_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18kSampleMultinomialPiPfS0_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__kSampleMultinomialPiPfS0_ii, .Lfunc_end0-_Z33__device_stub__kSampleMultinomialPiPfS0_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__kExpPfS_j    # -- Begin function _Z19__device_stub__kExpPfS_j
	.type	_Z19__device_stub__kExpPfS_j,@function
_Z19__device_stub__kExpPfS_j:           # @_Z19__device_stub__kExpPfS_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4kExpPfS_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z19__device_stub__kExpPfS_j, .Lfunc_end1-_Z19__device_stub__kExpPfS_j
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__kDividePfS_S_j # -- Begin function _Z22__device_stub__kDividePfS_S_j
	.type	_Z22__device_stub__kDividePfS_S_j,@function
_Z22__device_stub__kDividePfS_S_j:      # @_Z22__device_stub__kDividePfS_S_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7kDividePfS_S_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__kDividePfS_S_j, .Lfunc_end2-_Z22__device_stub__kDividePfS_S_j
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__kConvolve_forwardPfS_S_iiiiiiiiiiii # -- Begin function _Z32__device_stub__kConvolve_forwardPfS_S_iiiiiiiiiiii
	.type	_Z32__device_stub__kConvolve_forwardPfS_S_iiiiiiiiiiii,@function
_Z32__device_stub__kConvolve_forwardPfS_S_iiiiiiiiiiii: # @_Z32__device_stub__kConvolve_forwardPfS_S_iiiiiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z32__device_stub__kConvolve_forwardPfS_S_iiiiiiiiiiii, .Lfunc_end3-_Z32__device_stub__kConvolve_forwardPfS_S_iiiiiiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__kConvolve_weightPfS_S_iiiiiiiiiiiiif # -- Begin function _Z31__device_stub__kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.type	_Z31__device_stub__kConvolve_weightPfS_S_iiiiiiiiiiiiif,@function
_Z31__device_stub__kConvolve_weightPfS_S_iiiiiiiiiiiiif: # @_Z31__device_stub__kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 120(%rbx)
	movq	%r9, 128(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z31__device_stub__kConvolve_weightPfS_S_iiiiiiiiiiiiif, .Lfunc_end4-_Z31__device_stub__kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__kConvolve_backwardPfPKfS1_iiiiiiiiiii # -- Begin function _Z33__device_stub__kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.type	_Z33__device_stub__kConvolve_backwardPfPKfS1_iiiiiiiiiii,@function
_Z33__device_stub__kConvolve_backwardPfPKfS1_iiiiiiiiiii: # @_Z33__device_stub__kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z33__device_stub__kConvolve_backwardPfPKfS1_iiiiiiiiiii, .Lfunc_end5-_Z33__device_stub__kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__kConvolve_forward_cPfS_S_iiiiiiiiiiiiii # -- Begin function _Z34__device_stub__kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.type	_Z34__device_stub__kConvolve_forward_cPfS_S_iiiiiiiiiiiiii,@function
_Z34__device_stub__kConvolve_forward_cPfS_S_iiiiiiiiiiiiii: # @_Z34__device_stub__kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z34__device_stub__kConvolve_forward_cPfS_S_iiiiiiiiiiiiii, .Lfunc_end6-_Z34__device_stub__kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif # -- Begin function _Z33__device_stub__kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.type	_Z33__device_stub__kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif,@function
_Z33__device_stub__kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif: # @_Z33__device_stub__kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	8(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rcx
	movq	%rcx, 48(%rbx)
	leaq	312(%rsp), %rcx
	movq	%rcx, 56(%rbx)
	leaq	320(%rsp), %rcx
	movq	%rcx, 64(%rbx)
	leaq	328(%rsp), %rcx
	movq	%rcx, 72(%rbx)
	leaq	336(%rsp), %rcx
	movq	%rcx, 80(%rbx)
	leaq	344(%rsp), %rcx
	movq	%rcx, 88(%rbx)
	leaq	352(%rsp), %rcx
	movq	%rcx, 96(%rbx)
	leaq	360(%rsp), %rcx
	movq	%rcx, 104(%rbx)
	leaq	368(%rsp), %rcx
	movq	%rcx, 112(%rbx)
	leaq	376(%rsp), %rcx
	movq	%rcx, 120(%rbx)
	leaq	384(%rsp), %rcx
	movq	%rcx, 128(%rbx)
	leaq	392(%rsp), %rcx
	movq	%rcx, 136(%rbx)
	movq	%rax, 144(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z33__device_stub__kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif, .Lfunc_end7-_Z33__device_stub__kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii # -- Begin function _Z35__device_stub__kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.type	_Z35__device_stub__kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii,@function
_Z35__device_stub__kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii: # @_Z35__device_stub__kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z35__device_stub__kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii, .Lfunc_end8-_Z35__device_stub__kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18kSampleMultinomialPiPfS0_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4kExpPfS_j, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7kDividePfS_S_j, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18kSampleMultinomialPiPfS0_ii,@object # @_Z18kSampleMultinomialPiPfS0_ii
	.section	.rodata,"a",@progbits
	.globl	_Z18kSampleMultinomialPiPfS0_ii
	.p2align	3, 0x0
_Z18kSampleMultinomialPiPfS0_ii:
	.quad	_Z33__device_stub__kSampleMultinomialPiPfS0_ii
	.size	_Z18kSampleMultinomialPiPfS0_ii, 8

	.type	_Z4kExpPfS_j,@object            # @_Z4kExpPfS_j
	.globl	_Z4kExpPfS_j
	.p2align	3, 0x0
_Z4kExpPfS_j:
	.quad	_Z19__device_stub__kExpPfS_j
	.size	_Z4kExpPfS_j, 8

	.type	_Z7kDividePfS_S_j,@object       # @_Z7kDividePfS_S_j
	.globl	_Z7kDividePfS_S_j
	.p2align	3, 0x0
_Z7kDividePfS_S_j:
	.quad	_Z22__device_stub__kDividePfS_S_j
	.size	_Z7kDividePfS_S_j, 8

	.type	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii,@object # @_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
	.globl	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
	.p2align	3, 0x0
_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii:
	.quad	_Z32__device_stub__kConvolve_forwardPfS_S_iiiiiiiiiiii
	.size	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii, 8

	.type	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif,@object # @_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.globl	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.p2align	3, 0x0
_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif:
	.quad	_Z31__device_stub__kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.size	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif, 8

	.type	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii,@object # @_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.globl	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.p2align	3, 0x0
_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii:
	.quad	_Z33__device_stub__kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.size	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii, 8

	.type	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii,@object # @_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.globl	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.p2align	3, 0x0
_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii:
	.quad	_Z34__device_stub__kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.size	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii, 8

	.type	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif,@object # @_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.globl	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.p2align	3, 0x0
_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif:
	.quad	_Z33__device_stub__kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.size	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif, 8

	.type	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii,@object # @_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.globl	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.p2align	3, 0x0
_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii:
	.quad	_Z35__device_stub__kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.size	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18kSampleMultinomialPiPfS0_ii"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z4kExpPfS_j"
	.size	.L__unnamed_2, 13

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7kDividePfS_S_j"
	.size	.L__unnamed_3, 18

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii"
	.size	.L__unnamed_4, 40

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif"
	.size	.L__unnamed_5, 41

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii"
	.size	.L__unnamed_6, 42

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii"
	.size	.L__unnamed_7, 44

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif"
	.size	.L__unnamed_8, 45

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii"
	.size	.L__unnamed_9, 46

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__kSampleMultinomialPiPfS0_ii
	.addrsig_sym _Z19__device_stub__kExpPfS_j
	.addrsig_sym _Z22__device_stub__kDividePfS_S_j
	.addrsig_sym _Z32__device_stub__kConvolve_forwardPfS_S_iiiiiiiiiiii
	.addrsig_sym _Z31__device_stub__kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.addrsig_sym _Z33__device_stub__kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.addrsig_sym _Z34__device_stub__kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.addrsig_sym _Z33__device_stub__kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.addrsig_sym _Z35__device_stub__kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18kSampleMultinomialPiPfS0_ii
	.addrsig_sym _Z4kExpPfS_j
	.addrsig_sym _Z7kDividePfS_S_j
	.addrsig_sym _Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
	.addrsig_sym _Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.addrsig_sym _Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.addrsig_sym _Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.addrsig_sym _Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.addrsig_sym _Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18kSampleMultinomialPiPfS0_ii ; -- Begin function _Z18kSampleMultinomialPiPfS0_ii
	.globl	_Z18kSampleMultinomialPiPfS0_ii
	.p2align	8
	.type	_Z18kSampleMultinomialPiPfS0_ii,@function
_Z18kSampleMultinomialPiPfS0_ii:        ; @_Z18kSampleMultinomialPiPfS0_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	s_load_b64 s[4:5], s[0:1], 0x10
	v_mov_b32_e32 v1, 0
	v_mul_lo_u32 v0, v2, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v1
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_load_b128 s[4:7], s[0:1], 0x0
	global_load_b32 v6, v[3:4], off
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v0, v[2:3], off
	v_add_co_u32 v2, s0, v2, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_waitcnt vmcnt(1)
	v_cmp_ge_f32_e32 vcc_lo, v6, v1
	s_add_i32 s2, s2, -1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s0, v6, v0
	v_mov_b32_e32 v1, v0
	s_and_b32 s0, vcc_lo, s0
	s_cmp_lg_u32 s2, 0
	v_cndmask_b32_e64 v0, 0, 1, s0
	global_store_b32 v[4:5], v0, off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_cbranch_scc1 .LBB0_3
.LBB0_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18kSampleMultinomialPiPfS0_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18kSampleMultinomialPiPfS0_ii, .Lfunc_end0-_Z18kSampleMultinomialPiPfS0_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z4kExpPfS_j            ; -- Begin function _Z4kExpPfS_j
	.globl	_Z4kExpPfS_j
	.p2align	8
	.type	_Z4kExpPfS_j,@function
_Z4kExpPfS_j:                           ; @_Z4kExpPfS_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b32 s8, s[0:1], 0x10
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s9, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s9
	s_mov_b32 s2, 0
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_nc_u32_e32 v1, s1, v1
	v_add_co_u32 v4, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v2, s0, s4, v2
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
	global_load_b32 v0, v[4:5], off
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_or_b32 s2, vcc_lo, s2
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, 0x3fb8aa3b, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_exp_f32_e32 v0, v0
	global_store_b32 v[2:3], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %Flow18
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4kExpPfS_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z4kExpPfS_j, .Lfunc_end1-_Z4kExpPfS_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7kDividePfS_S_j       ; -- Begin function _Z7kDividePfS_S_j
	.globl	_Z7kDividePfS_S_j
	.p2align	8
	.type	_Z7kDividePfS_S_j,@function
_Z7kDividePfS_S_j:                      ; @_Z7kDividePfS_S_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s8, s[0:1], 0x18
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s9, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v1
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s10, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s10, s9
	s_mov_b32 s9, 0
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_nc_u32_e32 v1, s1, v1
	v_add_co_u32 v4, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v0, v[4:5], off
	global_load_b32 v4, v[6:7], off
	v_add_co_u32 v2, s0, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v5, null, v4, v4, v0
	v_div_scale_f32 v8, vcc_lo, v0, v4, v0
	v_rcp_f32_e32 v6, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v5, v6, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v6
	v_mul_f32_e32 v7, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v5, v7, v8
	v_fmac_f32_e32 v7, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v5, v7, v8
	v_div_fmas_f32 v5, v5, v6, v7
	v_cmp_le_u32_e32 vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v0, v5, v4, v0
	s_or_b32 s9, vcc_lo, s9
	global_store_b32 v[2:3], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB2_2
.LBB2_3:                                ; %Flow24
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7kDividePfS_S_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z7kDividePfS_S_j, .Lfunc_end2-_Z7kDividePfS_S_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii ; -- Begin function _Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
	.globl	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
	.p2align	8
	.type	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii,@function
_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii: ; @_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
; %bb.0:                                ; %.critedge
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x18
	s_load_b128 s[20:23], s[0:1], 0x38
	v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v5, 0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_lshl_add_u32 v0, s14, 5, v2
	s_mov_b32 s14, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s5, 31
	s_mul_i32 s25, s9, s9
	s_lshr_b32 s2, s2, 28
	s_mul_i32 s26, s25, s9
	s_add_i32 s2, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s24, s2, 4
	v_cvt_f32_u32_e32 v1, s24
	s_sub_i32 s3, 0, s24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v1
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s2, s3
	s_add_i32 s12, s2, s3
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mul_hi_u32 s0, s15, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s24
	s_add_i32 s12, s0, 1
	s_sub_i32 s1, s15, s1
	s_sub_i32 s13, s1, s24
	s_cmp_ge_u32 s1, s24
	s_cselect_b32 s0, s12, s0
	s_cselect_b32 s1, s13, s1
	s_add_i32 s12, s0, 1
	s_cmp_ge_u32 s1, s24
	s_mul_i32 s13, s22, s21
	s_cselect_b32 s12, s12, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s12, s24
	s_sub_i32 s0, s15, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s24, s0, 4
	s_cmp_lt_i32 s26, 1
	s_cbranch_scc1 .LBB3_15
; %bb.1:                                ; %.lr.ph
	s_ashr_i32 s0, s22, 31
	s_ashr_i32 s28, s12, 31
	s_add_i32 s1, s22, s0
	s_add_i32 s29, s12, s28
	s_xor_b32 s1, s1, s0
	s_xor_b32 s29, s29, s28
	v_cvt_f32_u32_e32 v1, s1
	s_sub_i32 s27, 0, s1
	s_xor_b32 s0, s28, s0
	v_lshl_add_u32 v7, v3, 5, v2
	v_cmp_le_i32_e32 vcc_lo, s4, v0
	v_rcp_iflag_f32_e32 v1, v1
	v_lshl_add_u32 v10, v3, 2, 0x200
	v_lshlrev_b32_e32 v8, 2, v2
	v_lshrrev_b32_e32 v9, 4, v7
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v12, v9, s5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s15, v1
	s_mul_i32 s27, s27, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s27, s15, s27
	s_add_i32 s15, s15, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s15, s29, s15
	s_mul_i32 s27, s15, s1
	s_add_i32 s30, s15, 1
	s_sub_i32 s27, s29, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s31, s27, s1
	s_cmp_ge_u32 s27, s1
	s_cselect_b32 s15, s30, s15
	s_cselect_b32 s27, s31, s27
	s_add_i32 s30, s15, 1
	s_cmp_ge_u32 s27, s1
	s_cselect_b32 s1, s30, s15
	s_ashr_i32 s15, s21, 31
	s_xor_b32 s1, s1, s0
	s_add_i32 s21, s21, s15
	s_sub_i32 s0, s1, s0
	s_xor_b32 s15, s21, s15
	s_ashr_i32 s27, s0, 31
	v_cvt_f32_u32_e32 v1, s15
	s_sub_i32 s1, 0, s15
	s_add_i32 s30, s0, s27
	s_mul_i32 s0, s0, s22
	s_xor_b32 s30, s30, s27
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s21, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s21
	s_mul_hi_u32 s1, s21, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s21, s21, s1
	s_mul_hi_u32 s1, s30, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s15
	s_sub_i32 s1, s30, s1
	s_sub_i32 s30, s12, s0
	s_sub_i32 s0, s1, s15
	s_cmp_ge_u32 s1, s15
	s_cselect_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s1, s0, s15
	s_cmp_ge_u32 s0, s15
	s_cselect_b32 s0, s1, s0
	s_ashr_i32 s1, s13, 31
	s_xor_b32 s0, s0, s27
	s_add_i32 s15, s13, s1
	s_xor_b32 s28, s28, s1
	s_xor_b32 s15, s15, s1
	s_sub_i32 s27, s0, s27
	v_cvt_f32_u32_e32 v1, s15
	s_sub_i32 s22, 0, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s21, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_mul_i32 s22, s22, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s22, s21, s22
	s_add_i32 s21, s21, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s21, s29, s21
	s_mul_i32 s1, s21, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s0, s29, s1
	s_add_i32 s1, s21, 1
	s_sub_i32 s22, s0, s15
	s_cmp_ge_u32 s0, s15
	s_cselect_b32 s1, s1, s21
	s_cselect_b32 s0, s22, s0
	s_add_i32 s21, s1, 1
	s_cmp_ge_u32 s0, s15
	s_cselect_b32 s15, s21, s1
	s_ashr_i32 s21, s9, 31
	s_lshl_b32 s5, s5, 2
	s_add_i32 s0, s9, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_xor_b32 s22, s0, s21
	v_cmp_gt_u32_e64 s0, 64, v7
	v_cvt_f32_u32_e32 v4, s22
	v_rcp_iflag_f32_e32 v16, v4
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v11, 15, v2
	v_cvt_f32_u32_e32 v2, s25
	s_delay_alu instid0(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v13, v2
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v16, 0x4f7ffffe, v16 :: v_dual_lshlrev_b32 v15, 2, v11
	v_add3_u32 v14, v12, v11, s24
	v_lshl_add_u32 v11, v3, 7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v18, v16
	v_lshl_or_b32 v7, v9, 6, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_mul_f32_e32 v17, 0x4f7ffffe, v13
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v12, s1, s18, v1
	v_add_co_ci_u32_e64 v13, s1, s19, v2, s1
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_u32_f32_e32 v17, v17
	s_sub_i32 s1, 0, s25
	s_sub_i32 s18, 0, s22
	v_lshlrev_b64 v[1:2], 2, v[14:15]
	v_mul_lo_u32 v20, s18, v18
	v_mul_lo_u32 v19, s1, v17
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v14, 0x200, v7
	v_mov_b32_e32 v7, 0
	v_add_co_u32 v15, s1, s2, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, s1, s3, v2, s1
	v_mul_hi_u32 v1, v17, v19
	v_mul_hi_u32 v2, v18, v20
	s_xor_b32 s1, s15, s28
	s_mul_i32 s18, s30, s11
	s_sub_i32 s1, s1, s28
	s_mul_i32 s19, s27, s11
	s_mul_i32 s1, s1, s11
	s_add_i32 s18, s18, s10
	v_add_nc_u32_e32 v17, v17, v1
	v_add_nc_u32_e32 v18, v18, v2
	s_add_i32 s19, s19, s10
	s_add_i32 s10, s1, s10
	s_mov_b32 s11, 0
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB3_6
; %bb.3:                                ;   in Loop: Header=BB3_2 Depth=1
	v_add_nc_u32_e32 v1, s11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s1, s26, v1
	v_mov_b32_e32 v1, 0
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB3_5
; %bb.4:                                ; %.critedge188
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_ashr_i32 s15, s14, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[28:29], s[14:15], 2
	v_add_co_u32 v1, s1, v15, s28
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s1, s29, v16, s1
	global_load_b32 v1, v[1:2], off
.LBB3_5:                                ; %.critedge186.sink.split
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	ds_store_b32 v14, v1
.LBB3_6:                                ; %Flow314
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v2, s11, v3
	s_mov_b32 s15, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s26, v2
	s_cbranch_execz .LBB3_14
; %bb.7:                                ;   in Loop: Header=BB3_2 Depth=1
	v_ashrrev_i32_e32 v1, 31, v2
	s_mov_b32 s27, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v19, v2, v1
	v_xor_b32_e32 v21, v19, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v19, v21, v17
	v_mul_lo_u32 v20, v19, s25
	v_add_nc_u32_e32 v22, 1, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, v21, v20
	v_subrev_nc_u32_e32 v23, s25, v20
	v_cmp_le_u32_e64 s1, s25, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v22, s1
	v_cndmask_b32_e64 v20, v20, v23, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v22, 1, v19
	v_cmp_le_u32_e64 s1, s25, v20
	v_mov_b32_e32 v20, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, v19, v22, s1
	v_xor_b32_e32 v19, v19, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v19, v19, v1
	v_add_nc_u32_e32 v19, s10, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v19
	s_cbranch_execz .LBB3_13
; %bb.8:                                ;   in Loop: Header=BB3_2 Depth=1
	v_mul_hi_u32 v20, v21, v18
	v_xor_b32_e32 v1, s21, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v22, v20, s22
	v_sub_nc_u32_e32 v21, v21, v22
	v_add_nc_u32_e32 v22, 1, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v23, s22, v21
	v_cmp_le_u32_e64 s1, s22, v21
	v_cndmask_b32_e64 v20, v20, v22, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v21, v21, v23, s1
	v_add_nc_u32_e32 v22, 1, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e64 s1, s22, v21
	v_cndmask_b32_e64 v20, v20, v22, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v20, v20, v1
	v_sub_nc_u32_e32 v21, v20, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v21
	v_add_nc_u32_e32 v20, v21, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v20, v20, v1
	v_mul_hi_u32 v22, v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v22, v22, s22
	v_sub_nc_u32_e32 v20, v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v22, s22, v20
	v_cmp_le_u32_e64 s1, s22, v20
	v_cndmask_b32_e64 v20, v20, v22, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v22, s22, v20
	v_cmp_le_u32_e64 s1, s22, v20
	v_cndmask_b32_e64 v20, v20, v22, s1
	v_cmp_gt_i32_e64 s1, s6, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v20, v20, v1
	v_sub_nc_u32_e32 v1, v20, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v20, 0 :: v_dual_add_nc_u32 v1, s19, v1
	v_cmp_lt_i32_e64 s2, -1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_and_saveexec_b32 s28, s1
	s_cbranch_execz .LBB3_12
; %bb.9:                                ;   in Loop: Header=BB3_2 Depth=1
	v_mul_lo_u32 v20, v21, s9
	v_cmp_le_i32_e64 s1, s7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v20
	v_mov_b32_e32 v20, 0
	v_add_nc_u32_e32 v2, s18, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e64 s2, s8, v2
	v_cmp_gt_i32_e64 s3, 0, v2
	s_or_b32 s1, s1, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, vcc_lo
	s_xor_b32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_11
; %bb.10:                               ; %.critedge195
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mad_u64_u32 v[20:21], null, v19, s7, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, v20, s8, v[2:3]
	v_mul_lo_u32 v1, v21, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s1, v12, v1
	v_add_co_ci_u32_e64 v2, s1, v13, v2, s1
	global_load_b32 v20, v[1:2], off
.LBB3_11:                               ; %Flow
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_12:                               ; %Flow312
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s28
.LBB3_13:                               ; %.critedge193.sink.split
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s27
	s_waitcnt vmcnt(0)
	ds_store_b32 v11, v20
.LBB3_14:                               ; %Flow313
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[1:2], v8 offset1:32
	ds_load_2addr_b32 v[19:20], v10 offset1:4
	ds_load_2addr_b32 v[21:22], v10 offset0:8 offset1:12
	ds_load_2addr_b32 v[23:24], v10 offset0:16 offset1:20
	ds_load_2addr_b32 v[25:26], v10 offset0:24 offset1:28
	ds_load_2addr_b32 v[27:28], v8 offset0:64 offset1:96
	ds_load_2addr_b32 v[29:30], v10 offset0:32 offset1:36
	ds_load_2addr_b32 v[31:32], v10 offset0:40 offset1:44
	ds_load_2addr_b32 v[33:34], v10 offset0:48 offset1:52
	ds_load_2addr_b32 v[35:36], v10 offset0:56 offset1:60
	s_add_i32 s11, s11, 4
	s_add_i32 s14, s14, s5
	s_cmp_lt_i32 s11, s26
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v4, v1, v20
	v_fmac_f32_e32 v7, v1, v19
	v_fmac_f32_e32 v5, v1, v22
	v_fmac_f32_e32 v6, v1, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v4, v2, v24
	v_fmac_f32_e32 v7, v2, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v5, v2, v26
	v_fmac_f32_e32 v6, v2, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v4, v27, v30
	v_fmac_f32_e32 v7, v27, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v5, v27, v32
	v_fmac_f32_e32 v6, v27, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v4, v28, v34
	v_fmac_f32_e32 v7, v28, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v5, v28, v36
	v_fmac_f32_e32 v6, v28, v35
	s_cbranch_scc1 .LBB3_2
.LBB3_15:                               ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB3_17
; %bb.16:                               ; %.preheader
	v_add_nc_u32_e32 v3, s24, v3
	s_mul_i32 s0, s13, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s4
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s2, s1, 3
	v_mad_u64_u32 v[1:2], null, s0, v3, s[12:13]
	s_lshl_b32 s0, s1, 2
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	v_mov_b32_e32 v3, 0
	s_mul_i32 s4, s1, 12
	s_ashr_i32 s1, s0, 31
	s_ashr_i32 s5, s4, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_lshl_b64 s[4:5], s[4:5], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v1, vcc_lo
	s_clause 0x3
	global_store_b32 v[0:1], v7, off
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[8:9], v6, off
	global_store_b32 v[10:11], v5, off
.LBB3_17:                               ; %.critedge205
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
		.amdhsa_group_segment_fixed_size 768
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 72
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii, .Lfunc_end3-_Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2136
; NumSgprs: 34
; NumVgprs: 37
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 768 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif ; -- Begin function _Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.globl	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
	.p2align	8
	.type	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif,@function
_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif: ; @_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
; %bb.0:                                ; %.critedge
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x38
	s_load_b256 s[16:23], s[0:1], 0x18
	s_load_b64 s[12:13], s[0:1], 0x48
	v_bfe_u32 v34, v0, 10, 10
	v_and_b32_e32 v33, 0x3ff, v0
	s_mul_i32 s25, s15, 40
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, v34, 4, v33
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s28, s4, s4
	v_cmpx_gt_u32_e32 40, v1
	s_cbranch_execz .LBB4_2
; %bb.1:
	s_ashr_i32 s2, s4, 31
	v_add_nc_u32_e32 v2, s25, v1
	s_add_i32 s8, s4, s2
	v_cvt_f32_u32_e32 v8, s28
	s_xor_b32 s8, s8, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v2
	v_cvt_f32_u32_e32 v0, s8
	s_sub_i32 s9, 0, s8
	v_add_nc_u32_e32 v5, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v5, v5, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v5, v0
	v_mul_lo_u32 v6, v3, s8
	v_add_nc_u32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v5, v6
	v_cmp_le_u32_e32 vcc_lo, s8, v6
	v_subrev_nc_u32_e32 v9, s8, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	v_rcp_iflag_f32_e32 v7, v8
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	v_xor_b32_e32 v9, s2, v4
	s_sub_i32 s2, 0, s28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x4f7ffffe, v7
	v_cvt_u32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, s2, v6
	v_mul_hi_u32 v7, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v6, v7
	v_mul_hi_u32 v6, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v6, s28
	v_sub_nc_u32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v10, s28, v5
	v_add_nc_u32_e32 v8, 1, v3
	v_cndmask_b32_e32 v3, v3, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s28, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v9
	v_cndmask_b32_e32 v5, v5, v10, vcc_lo
	v_sub_nc_u32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v3
	v_add_nc_u32_e32 v9, v3, v8
	v_mul_lo_u32 v3, v3, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v9, v8
	v_sub_nc_u32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v9, v0
	v_mul_lo_u32 v0, v0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v9, v0
	v_subrev_nc_u32_e32 v9, s8, v0
	v_cmp_le_u32_e64 s2, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, v9, s2
	v_subrev_nc_u32_e32 v9, s8, v0
	v_add_nc_u32_e32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s28, v5
	v_add_nc_u32_e32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v6, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v0
	v_xor_b32_e32 v5, v5, v4
	v_cndmask_b32_e32 v0, v0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v5, v4
	v_xor_b32_e32 v0, v0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v4, 16, v4
	v_sub_nc_u32_e32 v0, v0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v0, 8, v0
	v_add3_u32 v0, v0, v4, v2
	v_lshlrev_b32_e32 v2, 2, v1
	ds_store_b32 v2, v0 offset:7232
.LBB4_2:
	s_or_b32 exec_lo, exec_lo, s3
	s_ashr_i32 s2, s17, 31
	s_mul_i32 s28, s28, s4
	s_lshr_b32 s2, s2, 28
	v_dual_mov_b32 v42, 0 :: v_dual_mov_b32 v35, 0
	s_add_i32 s2, s17, s2
	v_mov_b32_e32 v38, 0
	s_ashr_i32 s2, s2, 4
	v_mov_b32_e32 v36, 0
	v_cvt_f32_u32_e32 v0, s2
	s_sub_i32 s8, 0, s2
	v_mov_b32_e32 v37, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v0
	s_mul_i32 s8, s8, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s8, s3, s8
	s_add_i32 s3, s3, s8
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mul_hi_u32 s3, s14, s3
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s3, s2
	s_add_i32 s15, s3, 1
	s_sub_i32 s4, s14, s4
	s_barrier
	s_sub_i32 s24, s4, s2
	s_cmp_ge_u32 s4, s2
	buffer_gl0_inv
	s_cselect_b32 s3, s15, s3
	s_cselect_b32 s4, s24, s4
	s_add_i32 s15, s3, 1
	s_cmp_ge_u32 s4, s2
	s_cselect_b32 s29, s15, s3
	s_mov_b32 s15, 0
	s_mul_i32 s2, s29, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s2, s14, s2
	s_lshl_b32 s30, s2, 4
	s_cmp_lt_i32 s12, 1
	s_cbranch_scc1 .LBB4_21
; %bb.3:                                ; %.lr.ph241
	v_lshrrev_b32_e32 v5, 5, v1
	s_mul_i32 s2, s20, s19
	s_mul_i32 s24, s29, s12
	s_mul_i32 s3, s2, s18
	v_dual_mov_b32 v35, 0 :: v_dual_and_b32 v0, 31, v1
	v_add_nc_u32_e32 v4, s30, v5
	s_add_i32 s12, s24, s12
	s_cmp_gt_i32 s16, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v37, 0 :: v_dual_lshlrev_b32 v6, 2, v0
	v_mad_u64_u32 v[2:3], null, v4, s3, s[24:25]
	s_cselect_b32 s31, -1, 0
	s_ashr_i32 s33, s2, 31
	s_ashr_i32 s34, s20, 31
	s_add_i32 s2, s2, s33
	s_ashr_i32 s4, s19, 31
	s_xor_b32 s35, s2, s33
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v2, s16, v[0:1]
	v_cvt_f32_u32_e32 v8, s35
	s_add_i32 s14, s20, s34
	s_add_i32 s18, s19, s4
	s_xor_b32 s36, s14, s34
	s_xor_b32 s37, s18, s4
	v_rcp_iflag_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_cvt_f32_u32_e32 v9, s37
	v_add_co_u32 v40, s2, s10, v6
	v_add_co_ci_u32_e64 v41, null, s11, 0, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_cvt_f32_u32_e32 v4, s36
	s_sub_i32 s14, 0, s35
	v_mul_u32_u24_e32 v7, 0x84, v5
	v_add_nc_u32_e32 v49, s25, v5
	s_movk_i32 s4, 0x1400
	v_add_co_u32 v43, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v44, vcc_lo, s1, v3, vcc_lo
	v_rcp_iflag_f32_e32 v2, v4
	v_rcp_iflag_f32_e32 v3, v9
	v_mul_f32_e32 v4, 0x4f7ffffe, v8
	v_cmp_gt_u32_e64 s0, 0x500, v1
	v_cmp_gt_u32_e64 s1, 0x200, v1
	v_mad_u32_u24 v47, 0x84, v33, s4
	v_add3_u32 v45, v7, v6, 0x1400
	v_cvt_u32_f32_e32 v1, v4
	s_mul_i32 s10, s3, s16
	v_lshl_or_b32 v39, v5, 7, v6
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	v_readfirstlane_b32 s11, v1
	s_lshl_b32 s10, s10, 2
	v_lshlrev_b32_e32 v46, 7, v34
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_u32_f32_e32 v1, v2
	v_cvt_u32_f32_e32 v2, v3
	s_mul_i32 s14, s14, s11
	v_lshl_add_u32 v48, v5, 2, 0x1c40
	s_mul_hi_u32 s4, s11, s14
	v_readfirstlane_b32 s14, v1
	v_readfirstlane_b32 s18, v2
	s_add_i32 s38, s11, s4
	s_sub_i32 s11, 0, s37
	s_sub_i32 s4, 0, s36
	v_add_nc_u32_e32 v50, 0x400, v45
	s_mul_i32 s11, s11, s18
	s_mul_i32 s4, s4, s14
	s_mul_hi_u32 s11, s18, s11
	v_mov_b32_e32 v36, 0
	v_mov_b32_e32 v38, 0
	v_mov_b32_e32 v42, 0
	s_ashr_i32 s3, s16, 31
	s_mov_b32 s2, s16
	s_mul_hi_u32 s4, s14, s4
	s_add_i32 s40, s18, s11
	s_ashr_i32 s11, s10, 31
	s_add_i32 s39, s14, s4
	s_lshl_b64 s[18:19], s[2:3], 2
	s_lshl_b64 s[26:27], s[10:11], 2
.LBB4_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_6 Depth 2
                                        ;       Child Loop BB4_8 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccnz .LBB4_20
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB4_4 Depth=1
	s_ashr_i32 s2, s24, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s24, s2
	s_xor_b32 s14, s2, s33
	s_xor_b32 s3, s3, s2
	s_mul_hi_u32 s4, s3, s38
	s_mul_hi_u32 s43, s3, s39
	s_mul_i32 s11, s4, s35
	s_add_i32 s41, s4, 1
	s_sub_i32 s11, s3, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s42, s11, s35
	s_cmp_ge_u32 s11, s35
	s_cselect_b32 s4, s41, s4
	s_cselect_b32 s11, s42, s11
	s_add_i32 s41, s4, 1
	s_cmp_ge_u32 s11, s35
	s_mul_i32 s11, s43, s36
	s_cselect_b32 s4, s41, s4
	s_sub_i32 s3, s3, s11
	s_xor_b32 s4, s4, s14
	s_xor_b32 s2, s2, s34
	s_sub_i32 s4, s4, s14
	s_add_i32 s14, s43, 1
	s_mul_i32 s11, s4, s6
	s_sub_i32 s4, s3, s36
	s_add_i32 s11, s11, s5
	s_cmp_ge_u32 s3, s36
	s_cselect_b32 s14, s14, s43
	s_cselect_b32 s3, s4, s3
	s_add_i32 s4, s14, 1
	s_cmp_ge_u32 s3, s36
	s_cselect_b32 s3, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	s_sub_i32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_add_i32 s4, s2, s3
	s_mul_i32 s2, s2, s20
	s_xor_b32 s4, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s14, s4, s40
	s_mul_i32 s14, s14, s37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s4, s4, s14
	s_sub_i32 s14, s4, s37
	s_cmp_ge_u32 s4, s37
	s_cselect_b32 s4, s14, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s14, s4, s37
	s_cmp_ge_u32 s4, s37
	s_cselect_b32 s4, s14, s4
	s_sub_i32 s2, s24, s2
	s_xor_b32 s4, s4, s3
	s_mul_i32 s41, s2, s6
	s_sub_i32 s3, s4, s3
	s_add_i32 s41, s41, s5
	s_mul_i32 s42, s3, s6
	s_mov_b32 s14, 0
	s_add_i32 s42, s42, s5
.LBB4_6:                                ; %.lr.ph
                                        ;   Parent Loop BB4_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB4_8 Depth 3
	v_or_b32_e32 v3, s14, v0
	s_and_saveexec_b32 s43, s0
	s_cbranch_execz .LBB4_17
; %bb.7:                                ; %.preheader230
                                        ;   in Loop: Header=BB4_6 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s16, v3
	v_dual_mov_b32 v4, v48 :: v_dual_mov_b32 v5, v39
	s_mov_b32 s44, -4
.LBB4_8:                                ;   Parent Loop BB4_4 Depth=1
                                        ;     Parent Loop BB4_6 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, v49, s44, 4
	v_mov_b32_e32 v6, 0
	v_cmp_gt_i32_e64 s2, s28, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s45, s2
	s_cbranch_execz .LBB4_16
; %bb.9:                                ;   in Loop: Header=BB4_8 Depth=3
	ds_load_b32 v2, v4
	s_mov_b32 s46, exec_lo
	v_mov_b32_e32 v6, 0
	s_waitcnt lgkmcnt(0)
	v_bfe_u32 v1, v2, 16, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, s11, v1
	v_cmpx_lt_i32_e32 -1, v7
	s_cbranch_execz .LBB4_15
; %bb.10:                               ;   in Loop: Header=BB4_8 Depth=3
	v_bfe_u32 v1, v2, 8, 8
	v_cmp_gt_i32_e64 s2, s21, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v1, s42, v1
	v_cmp_lt_i32_e64 s3, -1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_and_saveexec_b32 s47, s2
	s_cbranch_execz .LBB4_14
; %bb.11:                               ;   in Loop: Header=BB4_8 Depth=3
	v_and_b32_e32 v2, 0xff, v2
	v_cmp_gt_i32_e64 s2, s22, v1
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s41, v2
	v_cmp_gt_i32_e64 s3, s23, v2
	v_cmp_lt_i32_e64 s4, -1, v2
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB4_13
; %bb.12:                               ; %.critedge210
                                        ;   in Loop: Header=BB4_8 Depth=3
	v_mad_u64_u32 v[8:9], null, v7, s22, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v8, s23, v[2:3]
	v_mad_u64_u32 v[1:2], null, v6, s7, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s2, v40, v1
	v_add_co_ci_u32_e64 v2, s2, v41, v2, s2
	global_load_b32 v6, v[1:2], off
.LBB4_13:                               ; %Flow
                                        ;   in Loop: Header=BB4_8 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
.LBB4_14:                               ; %Flow514
                                        ;   in Loop: Header=BB4_8 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s47
.LBB4_15:                               ; %Flow515
                                        ;   in Loop: Header=BB4_8 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s46
.LBB4_16:                               ; %.critedge212
                                        ;   in Loop: Header=BB4_8 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s45
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v6
	v_add_nc_u32_e32 v5, 0x200, v5
	v_add_nc_u32_e32 v4, 16, v4
	s_add_i32 s44, s44, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s44, 36
	s_cbranch_scc1 .LBB4_8
.LBB4_17:                               ; %Flow517
                                        ;   in Loop: Header=BB4_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s43
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s16, v3
	s_and_b32 s3, s1, vcc_lo
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB4_19
; %bb.18:                               ; %.preheader229.preheader
                                        ;   in Loop: Header=BB4_6 Depth=2
	s_lshl_b64 s[44:45], s[14:15], 2
	s_add_i32 s3, s10, s14
	v_add_co_u32 v1, vcc_lo, v43, s44
	v_add_co_ci_u32_e32 v2, vcc_lo, s45, v44, vcc_lo
	s_add_i32 s44, s3, s10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, s26
	s_ashr_i32 s45, s44, 31
	s_add_i32 s46, s44, s10
	s_lshl_b64 s[44:45], s[44:45], 2
	v_add_co_ci_u32_e32 v4, vcc_lo, s27, v2, vcc_lo
	s_ashr_i32 s47, s46, 31
	v_add_co_u32 v5, vcc_lo, v43, s44
	v_add_co_ci_u32_e32 v6, vcc_lo, s45, v44, vcc_lo
	s_lshl_b64 s[44:45], s[46:47], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v7, vcc_lo, v43, s44
	v_add_co_ci_u32_e32 v8, vcc_lo, s45, v44, vcc_lo
	s_clause 0x3
	global_load_b32 v1, v[1:2], off
	global_load_b32 v2, v[3:4], off
	global_load_b32 v3, v[5:6], off
	global_load_b32 v4, v[7:8], off
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v45, v1, v2 offset1:132
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v50, v3, v4 offset0:8 offset1:140
.LBB4_19:                               ; %.loopexit
                                        ;   in Loop: Header=BB4_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b128 v[1:4], v46
	ds_load_b128 v[5:8], v46 offset:16
	ds_load_b128 v[9:12], v46 offset:32
	ds_load_b128 v[13:16], v46 offset:48
	ds_load_2addr_b32 v[29:30], v47 offset1:1
	ds_load_2addr_b32 v[31:32], v47 offset0:2 offset1:3
	ds_load_2addr_b32 v[25:26], v47 offset0:4 offset1:5
	ds_load_2addr_b32 v[27:28], v47 offset0:6 offset1:7
	ds_load_2addr_b32 v[21:22], v47 offset0:8 offset1:9
	ds_load_2addr_b32 v[23:24], v47 offset0:10 offset1:11
	ds_load_2addr_b32 v[17:18], v47 offset0:12 offset1:13
	ds_load_2addr_b32 v[19:20], v47 offset0:14 offset1:15
	s_add_i32 s14, s14, 32
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_ge_i32 s14, s16
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v42, v1, v29
	v_fmac_f32_e32 v42, v2, v30
	s_waitcnt lgkmcnt(6)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v3, v31
	v_fmac_f32_e32 v42, v4, v32
	s_waitcnt lgkmcnt(5)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v5, v25
	v_fmac_f32_e32 v42, v6, v26
	s_waitcnt lgkmcnt(4)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v7, v27
	v_fmac_f32_e32 v42, v8, v28
	s_waitcnt lgkmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v9, v21
	v_fmac_f32_e32 v42, v10, v22
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v11, v23
	v_fmac_f32_e32 v42, v12, v24
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v13, v17
	v_fmac_f32_e32 v42, v14, v18
	ds_load_b128 v[1:4], v46 offset:64
	ds_load_2addr_b32 v[13:14], v47 offset0:16 offset1:17
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v42, v15, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v16, v20
	ds_load_2addr_b32 v[15:16], v47 offset0:18 offset1:19
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v42, v1, v13
	v_fmac_f32_e32 v42, v2, v14
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v3, v15
	v_fmac_f32_e32 v42, v4, v16
	ds_load_b128 v[1:4], v46 offset:80
	ds_load_2addr_b32 v[9:10], v47 offset0:20 offset1:21
	ds_load_2addr_b32 v[11:12], v47 offset0:22 offset1:23
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v42, v1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v2, v10
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v42, v3, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v42, v4, v12
	ds_load_b128 v[1:4], v46 offset:96
	ds_load_2addr_b32 v[5:6], v47 offset0:24 offset1:25
	ds_load_2addr_b32 v[7:8], v47 offset0:26 offset1:27
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v42, v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v2, v6
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v42, v3, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v42, v4, v8
	ds_load_b128 v[51:54], v46 offset:112
	ds_load_2addr_b32 v[3:4], v47 offset0:28 offset1:29
	ds_load_2addr_b32 v[1:2], v47 offset0:30 offset1:31
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v42, v51, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v52, v4
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v42, v53, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, v54, v2
	ds_load_b128 v[51:54], v46 offset:1024
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v38, v51, v29
	v_fmac_f32_e32 v38, v52, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v53, v31
	v_fmac_f32_e32 v38, v54, v32
	ds_load_b128 v[51:54], v46 offset:1040
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v38, v51, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v52, v26
	v_fmac_f32_e32 v38, v53, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v54, v28
	ds_load_b128 v[51:54], v46 offset:1056
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v38, v51, v21
	v_fmac_f32_e32 v38, v52, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v53, v23
	v_fmac_f32_e32 v38, v54, v24
	ds_load_b128 v[51:54], v46 offset:1072
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v38, v51, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v52, v18
	v_fmac_f32_e32 v38, v53, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v54, v20
	ds_load_b128 v[51:54], v46 offset:1088
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v38, v51, v13
	v_fmac_f32_e32 v38, v52, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v53, v15
	v_fmac_f32_e32 v38, v54, v16
	ds_load_b128 v[51:54], v46 offset:1104
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v38, v51, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v52, v10
	v_fmac_f32_e32 v38, v53, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v54, v12
	ds_load_b128 v[51:54], v46 offset:1120
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v38, v51, v5
	v_fmac_f32_e32 v38, v52, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v53, v7
	v_fmac_f32_e32 v38, v54, v8
	ds_load_b128 v[51:54], v46 offset:1136
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v38, v51, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v52, v4
	v_fmac_f32_e32 v38, v53, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v38, v54, v2
	ds_load_b128 v[51:54], v46 offset:2048
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v37, v51, v29
	v_fmac_f32_e32 v37, v52, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v53, v31
	v_fmac_f32_e32 v37, v54, v32
	ds_load_b128 v[51:54], v46 offset:2064
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v37, v51, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v52, v26
	v_fmac_f32_e32 v37, v53, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v54, v28
	ds_load_b128 v[51:54], v46 offset:2080
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v37, v51, v21
	v_fmac_f32_e32 v37, v52, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v53, v23
	v_fmac_f32_e32 v37, v54, v24
	ds_load_b128 v[51:54], v46 offset:2096
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v37, v51, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v52, v18
	v_fmac_f32_e32 v37, v53, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v54, v20
	ds_load_b128 v[51:54], v46 offset:2112
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v37, v51, v13
	v_fmac_f32_e32 v37, v52, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v53, v15
	v_fmac_f32_e32 v37, v54, v16
	ds_load_b128 v[51:54], v46 offset:2128
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v37, v51, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v52, v10
	v_fmac_f32_e32 v37, v53, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v54, v12
	ds_load_b128 v[51:54], v46 offset:2144
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v37, v51, v5
	v_fmac_f32_e32 v37, v52, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v53, v7
	v_fmac_f32_e32 v37, v54, v8
	ds_load_b128 v[51:54], v46 offset:2160
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v37, v51, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v52, v4
	v_fmac_f32_e32 v37, v53, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v54, v2
	ds_load_b128 v[51:54], v46 offset:3072
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v51, v29
	v_fmac_f32_e32 v36, v52, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v53, v31
	v_fmac_f32_e32 v36, v54, v32
	ds_load_b128 v[51:54], v46 offset:3088
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v51, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v52, v26
	v_fmac_f32_e32 v36, v53, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v54, v28
	ds_load_b128 v[51:54], v46 offset:3104
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v51, v21
	v_fmac_f32_e32 v36, v52, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v53, v23
	v_fmac_f32_e32 v36, v54, v24
	ds_load_b128 v[51:54], v46 offset:3120
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v51, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v52, v18
	v_fmac_f32_e32 v36, v53, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v54, v20
	ds_load_b128 v[51:54], v46 offset:3136
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v51, v13
	v_fmac_f32_e32 v36, v52, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v53, v15
	v_fmac_f32_e32 v36, v54, v16
	ds_load_b128 v[51:54], v46 offset:3152
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v51, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v52, v10
	v_fmac_f32_e32 v36, v53, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v54, v12
	ds_load_b128 v[51:54], v46 offset:3168
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v51, v5
	v_fmac_f32_e32 v36, v52, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v53, v7
	v_fmac_f32_e32 v36, v54, v8
	ds_load_b128 v[51:54], v46 offset:3184
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v36, v51, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v52, v4
	v_fmac_f32_e32 v36, v53, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v54, v2
	ds_load_b128 v[51:54], v46 offset:4096
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v35, v51, v29
	v_fmac_f32_e32 v35, v52, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v53, v31
	v_fmac_f32_e32 v35, v54, v32
	ds_load_b128 v[29:32], v46 offset:4112
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v35, v29, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v30, v26
	v_fmac_f32_e32 v35, v31, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v32, v28
	ds_load_b128 v[25:28], v46 offset:4128
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v35, v25, v21
	v_fmac_f32_e32 v35, v26, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v27, v23
	v_fmac_f32_e32 v35, v28, v24
	ds_load_b128 v[21:24], v46 offset:4144
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v35, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v22, v18
	v_fmac_f32_e32 v35, v23, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v24, v20
	ds_load_b128 v[17:20], v46 offset:4160
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v35, v17, v13
	v_fmac_f32_e32 v35, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v19, v15
	v_fmac_f32_e32 v35, v20, v16
	ds_load_b128 v[13:16], v46 offset:4176
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v35, v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v14, v10
	v_fmac_f32_e32 v35, v15, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v16, v12
	ds_load_b128 v[9:12], v46 offset:4192
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v35, v9, v5
	v_fmac_f32_e32 v35, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v11, v7
	v_fmac_f32_e32 v35, v12, v8
	ds_load_b128 v[5:8], v46 offset:4208
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v35, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v6, v4
	v_fmac_f32_e32 v35, v7, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v35, v8, v2
	s_cbranch_scc0 .LBB4_6
.LBB4_20:                               ; %._crit_edge
                                        ;   in Loop: Header=BB4_4 Depth=1
	v_add_co_u32 v43, vcc_lo, v43, s18
	v_add_co_ci_u32_e32 v44, vcc_lo, s19, v44, vcc_lo
	s_add_i32 s24, s24, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s24, s12
	s_cbranch_scc0 .LBB4_4
.LBB4_21:                               ; %Flow521
	v_add_nc_u32_e32 v2, s25, v34
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s29, s28, v[2:3]
	v_mov_b32_e32 v1, 0
	v_mul_lo_u32 v0, v0, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s30, v33, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	v_cmpx_gt_u32_e64 s28, v2
	s_cbranch_execz .LBB4_23
; %bb.22:                               ; %.critedge220
	v_mul_f32_e32 v3, s13, v42
	global_store_b32 v[0:1], v3, off
.LBB4_23:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v3, 8, v2
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s28, v3
	s_cbranch_execz .LBB4_25
; %bb.24:                               ; %.critedge220.1
	s_lshl_b32 s2, s17, 3
	v_mul_f32_e32 v5, s13, v38
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	v_add_co_u32 v3, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[3:4], v5, off
.LBB4_25:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v3, 16, v2
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s28, v3
	s_cbranch_execz .LBB4_27
; %bb.26:                               ; %.critedge220.2
	s_lshl_b32 s2, s17, 4
	v_mul_f32_e32 v5, s13, v37
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	v_add_co_u32 v3, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[3:4], v5, off
.LBB4_27:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v3, 24, v2
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s28, v3
	s_cbranch_execz .LBB4_29
; %bb.28:                               ; %.critedge220.3
	s_mul_i32 s2, s17, 24
	v_mul_f32_e32 v5, s13, v36
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 2
	v_add_co_u32 v3, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[3:4], v5, off
.LBB4_29:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v2, 32, v2
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s28, v2
	s_cbranch_execz .LBB4_31
; %bb.30:                               ; %.critedge220.4
	s_lshl_b32 s0, s17, 5
	v_mul_f32_e32 v2, s13, v35
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB4_31:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
		.amdhsa_group_segment_fixed_size 7392
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 80
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 55
		.amdhsa_next_free_sgpr 48
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif, .Lfunc_end4-_Z16kConvolve_weightPfS_S_iiiiiiiiiiiiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3940
; NumSgprs: 50
; NumVgprs: 55
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 7392 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 50
; NumVGPRsForWavesPerEU: 55
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii ; -- Begin function _Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.globl	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
	.p2align	8
	.type	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii,@function
_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii: ; @_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
; %bb.0:                                ; %.critedge
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x38
	s_load_b256 s[4:11], s[0:1], 0x18
	s_ashr_i32 s21, s15, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s22, s15, s21
	s_xor_b32 s22, s22, s21
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s16, 3
	s_add_i32 s3, s11, 3
	s_ashr_i32 s12, s2, 31
	s_ashr_i32 s13, s3, 31
	s_lshr_b32 s12, s12, 30
	s_lshr_b32 s13, s13, 30
	s_add_i32 s2, s2, s12
	s_add_i32 s3, s3, s13
	s_ashr_i32 s2, s2, 2
	s_ashr_i32 s20, s3, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s2, s20
	s_ashr_i32 s12, s3, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s12
	s_xor_b32 s3, s3, s12
	s_xor_b32 s12, s21, s12
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s19, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s13, v1
	s_mul_i32 s19, s19, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s19, s13, s19
	s_add_i32 s13, s13, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s13, s22, s13
	s_mul_i32 s19, s13, s3
	s_add_i32 s23, s13, 1
	s_sub_i32 s19, s22, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s24, s19, s3
	s_cmp_ge_u32 s19, s3
	s_cselect_b32 s13, s23, s13
	s_cselect_b32 s19, s24, s19
	s_add_i32 s23, s13, 1
	s_cmp_ge_u32 s19, s3
	s_mov_b32 s19, 0
	s_cselect_b32 s3, s23, s13
	s_mov_b32 s13, 0
	s_xor_b32 s3, s3, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s12, s3, s12
	s_sub_i32 s3, s12, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s3, s9
	s_cbranch_scc1 .LBB5_2
; %bb.1:
	s_ashr_i32 s19, s18, 31
	s_sub_i32 s25, s3, s9
	s_add_i32 s23, s18, s19
	s_ashr_i32 s27, s25, 31
	s_xor_b32 s23, s23, s19
	s_add_i32 s25, s25, s27
	v_cvt_f32_u32_e32 v1, s23
	s_sub_i32 s26, 0, s23
	s_xor_b32 s25, s25, s27
	s_xor_b32 s19, s27, s19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s24, v1
	s_mul_i32 s26, s26, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s26, s24, s26
	s_add_i32 s24, s24, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s24, s25, s24
	s_mul_i32 s26, s24, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s25, s25, s26
	s_add_i32 s26, s24, 1
	s_sub_i32 s27, s25, s23
	s_cmp_ge_u32 s25, s23
	s_cselect_b32 s24, s26, s24
	s_cselect_b32 s25, s27, s25
	s_add_i32 s26, s24, 1
	s_cmp_ge_u32 s25, s23
	s_cselect_b32 s23, s26, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s23, s23, s19
	s_sub_i32 s19, s23, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s19, s19, 1
.LBB5_2:
	s_ashr_i32 s23, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s24, s2, s23
	s_xor_b32 s21, s21, s23
	s_xor_b32 s24, s24, s23
	v_cvt_f32_u32_e32 v1, s24
	s_sub_i32 s26, 0, s24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s25, v1
	s_mul_i32 s26, s26, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s26, s25, s26
	s_add_i32 s25, s25, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s25, s22, s25
	s_mul_i32 s26, s25, s24
	s_add_i32 s23, s25, 1
	s_sub_i32 s22, s22, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s26, s22, s24
	s_cmp_ge_u32 s22, s24
	s_cselect_b32 s23, s23, s25
	s_cselect_b32 s22, s26, s22
	s_add_i32 s25, s23, 1
	s_cmp_ge_u32 s22, s24
	s_cselect_b32 s22, s25, s23
	s_ashr_i32 s23, s20, 31
	s_xor_b32 s22, s22, s21
	s_add_i32 s20, s20, s23
	s_sub_i32 s37, s22, s21
	s_xor_b32 s20, s20, s23
	s_ashr_i32 s36, s37, 31
	v_cvt_f32_u32_e32 v1, s20
	s_sub_i32 s21, 0, s20
	s_add_i32 s22, s37, s36
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s22, s22, s36
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s23, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s21, s21, s23
	s_mul_hi_u32 s21, s23, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s23, s23, s21
	s_mul_hi_u32 s21, s22, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s21, s21, s20
	s_sub_i32 s21, s22, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s22, s21, s20
	s_cmp_ge_u32 s21, s20
	s_cselect_b32 s21, s22, s21
	s_sub_i32 s22, s21, s20
	s_cmp_ge_u32 s21, s20
	s_cselect_b32 s20, s22, s21
	s_ashr_i32 s28, s18, 31
	s_xor_b32 s34, s20, s36
	s_add_i32 s21, s18, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_xor_b32 s27, s21, s28
	s_sub_i32 s21, s34, s36
	v_cvt_f32_u32_e32 v1, s27
	s_sub_i32 s20, 0, s27
	s_lshl_b32 s25, s21, 2
	s_sub_i32 s30, s25, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s29, v1
	s_mul_i32 s20, s20, s29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s20, s29, s20
	s_add_i32 s29, s29, s20
	s_cmp_lt_i32 s30, s9
	s_cbranch_scc1 .LBB5_4
; %bb.3:
	s_sub_i32 s13, s30, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s20, s13, 31
	s_add_i32 s13, s13, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s13, s13, s20
	s_xor_b32 s20, s20, s28
	s_mul_hi_u32 s21, s13, s29
	s_mul_i32 s22, s21, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s13, s13, s22
	s_add_i32 s22, s21, 1
	s_sub_i32 s23, s13, s27
	s_cmp_ge_u32 s13, s27
	s_cselect_b32 s21, s22, s21
	s_cselect_b32 s13, s23, s13
	s_add_i32 s22, s21, 1
	s_cmp_ge_u32 s13, s27
	s_cselect_b32 s13, s22, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s13, s13, s20
	s_sub_i32 s13, s13, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s13, s13, 1
.LBB5_4:
	s_mul_i32 s37, s37, s2
	s_mov_b32 s24, 0
	s_sub_i32 s2, s15, s37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s31, s2, 2
	s_sub_i32 s26, s31, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s26, s9
	s_cbranch_scc1 .LBB5_6
; %bb.5:
	s_sub_i32 s2, s26, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s20, s2, 31
	s_add_i32 s2, s2, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s20
	s_xor_b32 s20, s20, s28
	s_mul_hi_u32 s21, s2, s29
	s_mul_i32 s22, s21, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s2, s2, s22
	s_add_i32 s22, s21, 1
	s_sub_i32 s23, s2, s27
	s_cmp_ge_u32 s2, s27
	s_cselect_b32 s21, s22, s21
	s_cselect_b32 s2, s23, s2
	s_add_i32 s22, s21, 1
	s_cmp_ge_u32 s2, s27
	s_cselect_b32 s2, s22, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s20
	s_sub_i32 s2, s2, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s24, s2, 1
.LBB5_6:
	s_add_i32 s2, s3, 3
	v_lshrrev_b32_e32 v1, 10, v0
	s_ashr_i32 s3, s2, 31
	v_bfe_u32 v12, v0, 10, 2
	s_add_i32 s2, s2, s3
	s_xor_b32 s33, s3, s28
	s_xor_b32 s2, s2, s3
	v_bfe_u32 v7, v1, 2, 8
	s_mul_hi_u32 s20, s2, s29
	v_or_b32_e32 v1, s31, v12
	s_mul_i32 s21, s20, s27
	s_add_i32 s3, s20, 1
	s_sub_i32 s2, s2, s21
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v2, s25, v7
	s_sub_i32 s21, s2, s27
	s_cmp_ge_u32 s2, s27
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v3, 0x3ff, v0
	s_cselect_b32 s3, s3, s20
	s_cselect_b32 s2, s21, s2
	s_add_i32 s20, s3, 1
	s_cmp_ge_u32 s2, s27
	v_cmp_gt_i32_e32 vcc_lo, s11, v2
	s_cselect_b32 s35, s20, s3
	s_clause 0x1
	s_load_b128 s[20:23], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_xor_b32 s0, s35, s33
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s0, s0, s33
	s_add_i32 s1, s0, 1
	s_cmp_lt_i32 s0, s4
	v_cmp_gt_i32_e64 s0, s16, v1
	s_cselect_b32 s25, s1, s4
	s_lshl_b32 s14, s14, 5
	s_cmp_lt_i32 s12, s10
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, vcc_lo
	s_and_b32 s10, s1, s0
	s_cmp_ge_i32 s19, s25
	s_cbranch_scc1 .LBB5_29
; %bb.7:                                ; %.lr.ph306
	s_add_i32 s0, s26, 3
	v_bfe_u32 v6, v0, 10, 10
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s35, s13, s18
	s_add_i32 s0, s0, s1
	v_lshlrev_b32_e32 v0, 2, v3
	s_xor_b32 s0, s0, s1
	s_xor_b32 s1, s1, s28
	s_mul_hi_u32 s26, s0, s29
	v_lshl_add_u32 v5, v6, 4, v3
	s_mul_i32 s31, s26, s27
	s_movk_i32 s38, 0x44
	s_sub_i32 s0, s0, s31
	s_add_i32 s31, s26, 1
	s_sub_i32 s33, s0, s27
	s_cmp_ge_u32 s0, s27
	v_and_b32_e32 v8, 31, v5
	s_cselect_b32 s26, s31, s26
	s_cselect_b32 s0, s33, s0
	s_add_i32 s31, s26, 1
	s_cmp_ge_u32 s0, s27
	s_mul_i32 s33, s6, s5
	s_cselect_b32 s0, s31, s26
	s_mul_i32 s41, s33, s4
	s_xor_b32 s0, s0, s1
	v_lshrrev_b32_e32 v11, 5, v5
	s_sub_i32 s0, s0, s1
	v_or_b32_e32 v5, s14, v8
	s_add_i32 s1, s0, 1
	s_cmp_lt_i32 s0, s6
	s_mul_i32 s41, s41, s7
	s_cselect_b32 s26, s1, s6
	s_add_i32 s0, s30, 3
	v_mad_u64_u32 v[13:14], null, s41, v11, v[5:6]
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s39, s24, s18
	s_add_i32 s0, s0, s1
	s_mul_i32 s40, s9, s9
	s_xor_b32 s0, s0, s1
	s_xor_b32 s1, s1, s28
	s_mul_hi_u32 s29, s0, s29
	v_ashrrev_i32_e32 v14, 31, v13
	s_mul_i32 s30, s29, s27
	s_add_i32 s28, s29, 1
	s_sub_i32 s0, s0, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s30, s0, s27
	s_cmp_ge_u32 s0, s27
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_cselect_b32 s28, s28, s29
	s_cselect_b32 s0, s30, s0
	s_add_i32 s29, s28, 1
	s_cmp_ge_u32 s0, s27
	s_mul_i32 s0, s19, s18
	s_cselect_b32 s27, s29, s28
	s_mul_i32 s29, s7, s6
	s_xor_b32 s27, s27, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s1, s27, s1
	s_mul_i32 s27, s18, s8
	s_add_i32 s28, s1, 1
	s_cmp_lt_i32 s1, s5
	s_mul_i32 s1, s19, s5
	s_cselect_b32 s28, s28, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s13, s28
	s_cselect_b32 s30, -1, 0
	s_cmp_lt_i32 s24, s26
	s_cselect_b32 s31, -1, 0
	s_cmp_gt_i32 s8, 0
	s_cselect_b32 s33, -1, 0
	s_add_i32 s0, s17, s0
	s_lshl_b32 s42, s34, 2
	s_sub_i32 s0, s12, s0
	s_add_i32 s1, s13, s1
	s_mul_i32 s0, s9, s0
	s_mul_i32 s1, s6, s1
	v_add3_u32 v7, s42, s0, v7
	s_add_i32 s0, s17, s35
	s_add_i32 s1, s24, s1
	s_mul_i32 s34, s27, s40
	s_mul_i32 s35, s27, s9
	v_subrev_nc_u32_e32 v7, s0, v7
	s_lshl_b32 s0, s36, 2
	s_mul_i32 s36, s29, s5
	s_mul_i32 s6, s7, s1
	s_mul_i32 s4, s36, s4
	v_subrev_nc_u32_e32 v9, s0, v7
	v_mad_u32_u24 v7, v6, s38, 0x800
	v_lshlrev_b32_e32 v6, 2, v8
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, s0, s2, v0
	v_mul_lo_u32 v15, s9, v9
	s_lshl_b32 s2, s15, 2
	v_add_co_ci_u32_e64 v9, null, s3, 0, s0
	v_cmp_le_i32_e64 s0, s7, v5
	s_lshl_b32 s3, s37, 2
	v_lshl_or_b32 v11, v11, 7, v6
	v_mov_b32_e32 v6, 0
	v_add3_u32 v5, v15, s2, v12
	s_add_i32 s2, s17, s39
	v_add_co_u32 v12, vcc_lo, s22, v13
	v_add_co_ci_u32_e32 v13, vcc_lo, s23, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v5, s3, v5
	s_lshl_b32 s15, s4, 4
	v_subrev_nc_u32_e32 v5, s2, v5
	s_lshl_b32 s2, s41, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s3, s2, 31
	v_mul_lo_u32 v14, s8, v5
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
	v_add_nc_u32_e32 v15, 0x400, v0
	v_add_nc_u32_e32 v10, v7, v0
	s_lshl_b64 s[2:3], s[2:3], 2
.LBB5_8:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_10 Depth 2
                                        ;       Child Loop BB5_12 Depth 3
                                        ;         Child Loop BB5_17 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB5_28
; %bb.9:                                ; %.lr.ph302
                                        ;   in Loop: Header=BB5_8 Depth=1
	s_mul_i32 s1, s19, s18
	v_mov_b32_e32 v16, v14
	s_add_i32 s1, s1, s17
	s_mov_b32 s37, s6
	s_sub_i32 s1, s12, s1
	s_mov_b32 s38, s13
	s_cmp_gt_i32 s1, -1
	s_cselect_b32 s22, -1, 0
	s_cmp_lt_i32 s1, s9
	s_cselect_b32 s23, -1, 0
.LBB5_10:                               ;   Parent Loop BB5_8 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB5_12 Depth 3
                                        ;         Child Loop BB5_17 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s31
	s_cbranch_vccnz .LBB5_27
; %bb.11:                               ; %.lr.ph
                                        ;   in Loop: Header=BB5_10 Depth=2
	s_mul_i32 s1, s38, s18
	s_mov_b32 s39, s37
	s_add_i32 s1, s1, s17
	s_mov_b32 s41, s24
	v_subrev_nc_u32_e32 v17, s1, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v17
	v_cmp_gt_i32_e64 s1, s9, v17
	v_mov_b32_e32 v17, v16
	s_and_b32 s4, s23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s40, s4, s1
.LBB5_12:                               ;   Parent Loop BB5_8 Depth=1
                                        ;     Parent Loop BB5_10 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB5_17 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB5_14
; %bb.13:                               ;   in Loop: Header=BB5_12 Depth=3
	s_mul_i32 s1, s41, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s1, s17
	v_subrev_nc_u32_e32 v18, s1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v18
	v_cmp_gt_i32_e64 s1, s9, v18
	s_and_b32 s4, s40, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s4, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
	s_branch .LBB5_15
.LBB5_14:                               ;   in Loop: Header=BB5_12 Depth=3
	s_mov_b32 s1, 0
.LBB5_15:                               ;   in Loop: Header=BB5_12 Depth=3
	s_and_not1_b32 vcc_lo, exec_lo, s33
	s_cbranch_vccnz .LBB5_26
; %bb.16:                               ; %.critedge263.lr.ph
                                        ;   in Loop: Header=BB5_12 Depth=3
	s_and_b32 s1, s10, s1
	s_mov_b32 s42, 0
	s_mov_b32 s4, s39
.LBB5_17:                               ; %.critedge263
                                        ;   Parent Loop BB5_8 Depth=1
                                        ;     Parent Loop BB5_10 Depth=2
                                        ;       Parent Loop BB5_12 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_and_saveexec_b32 s5, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB5_19
; %bb.18:                               ; %.preheader289.preheader
                                        ;   in Loop: Header=BB5_17 Depth=4
	ds_store_2addr_stride64_b32 v11, v4, v4 offset1:4
.LBB5_19:                               ; %Flow445
                                        ;   in Loop: Header=BB5_17 Depth=4
	s_and_not1_saveexec_b32 s43, s5
	s_cbranch_execz .LBB5_21
; %bb.20:                               ; %.preheader287.preheader
                                        ;   in Loop: Header=BB5_17 Depth=4
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[44:45], s[4:5], 2
	v_add_co_u32 v18, vcc_lo, v12, s44
	v_add_co_ci_u32_e32 v19, vcc_lo, s45, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, v18, s2
	v_add_co_ci_u32_e32 v21, vcc_lo, s3, v19, vcc_lo
	s_clause 0x1
	global_load_b32 v18, v[18:19], off
	global_load_b32 v19, v[20:21], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v11, v18, v19 offset1:4
.LBB5_21:                               ; %.loopexit288
                                        ;   in Loop: Header=BB5_17 Depth=4
	s_or_b32 exec_lo, exec_lo, s43
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB5_23
; %bb.22:                               ; %.critedge267
                                        ;   in Loop: Header=BB5_17 Depth=4
	v_add_nc_u32_e32 v18, s42, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, v8, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, v9, v19, vcc_lo
	global_load_b32 v18, v[18:19], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v18
.LBB5_23:                               ;   in Loop: Header=BB5_17 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB5_25
; %bb.24:                               ; %.preheader285.preheader
                                        ;   in Loop: Header=BB5_17 Depth=4
	ds_load_2addr_b32 v[18:19], v0 offset1:16
	ds_load_2addr_b32 v[20:21], v7 offset1:1
	ds_load_2addr_b32 v[22:23], v0 offset0:32 offset1:48
	ds_load_2addr_b32 v[24:25], v0 offset0:64 offset1:80
	ds_load_2addr_b32 v[26:27], v7 offset0:2 offset1:3
	ds_load_2addr_b32 v[28:29], v0 offset0:96 offset1:112
	ds_load_2addr_b32 v[30:31], v0 offset0:128 offset1:144
	ds_load_2addr_b32 v[32:33], v7 offset0:4 offset1:5
	ds_load_2addr_b32 v[34:35], v7 offset0:6 offset1:7
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v5, v20, v19
	v_fmac_f32_e32 v6, v20, v18
	ds_load_2addr_b32 v[18:19], v0 offset0:160 offset1:176
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v5, v21, v23
	v_fmac_f32_e32 v6, v21, v22
	ds_load_2addr_b32 v[20:21], v0 offset0:192 offset1:208
	ds_load_2addr_b32 v[22:23], v0 offset0:224 offset1:240
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v5, v26, v25
	v_fmac_f32_e32 v6, v26, v24
	ds_load_2addr_b32 v[24:25], v15 offset1:16
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v5, v27, v29
	v_fmac_f32_e32 v6, v27, v28
	ds_load_2addr_b32 v[26:27], v7 offset0:8 offset1:9
	ds_load_2addr_b32 v[28:29], v15 offset0:32 offset1:48
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v5, v32, v31
	v_fmac_f32_e32 v6, v32, v30
	ds_load_2addr_b32 v[30:31], v7 offset0:10 offset1:11
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v5, v33, v19
	v_fmac_f32_e32 v6, v33, v18
	ds_load_2addr_b32 v[18:19], v15 offset0:64 offset1:80
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v5, v34, v21
	v_fmac_f32_e32 v6, v34, v20
	ds_load_2addr_b32 v[20:21], v15 offset0:96 offset1:112
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v5, v35, v23
	v_fmac_f32_e32 v6, v35, v22
	ds_load_2addr_b32 v[22:23], v15 offset0:128 offset1:144
	ds_load_2addr_b32 v[32:33], v7 offset0:12 offset1:13
	ds_load_2addr_b32 v[34:35], v7 offset0:14 offset1:15
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v5, v26, v25
	v_fmac_f32_e32 v6, v26, v24
	ds_load_2addr_b32 v[24:25], v15 offset0:160 offset1:176
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v5, v27, v29
	v_fmac_f32_e32 v6, v27, v28
	ds_load_2addr_b32 v[26:27], v15 offset0:192 offset1:208
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v5, v30, v19
	v_fmac_f32_e32 v6, v30, v18
	ds_load_2addr_b32 v[18:19], v15 offset0:224 offset1:240
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v5, v31, v21
	s_waitcnt lgkmcnt(4)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v6, v31, v20 :: v_dual_fmac_f32 v5, v32, v23
	s_waitcnt lgkmcnt(2)
	v_dual_fmac_f32 v6, v32, v22 :: v_dual_fmac_f32 v5, v33, v25
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v6, v33, v24 :: v_dual_fmac_f32 v5, v34, v27
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v6, v34, v26 :: v_dual_fmac_f32 v5, v35, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v6, v35, v18
.LBB5_25:                               ; %.critedge272
                                        ;   in Loop: Header=BB5_17 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s42, s42, 16
	s_add_i32 s4, s4, s15
	s_cmp_ge_i32 s42, s8
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB5_17
.LBB5_26:                               ; %._crit_edge
                                        ;   in Loop: Header=BB5_12 Depth=3
	v_subrev_nc_u32_e32 v17, s27, v17
	s_add_i32 s41, s41, 1
	s_add_i32 s39, s39, s7
	s_cmp_ge_i32 s41, s26
	s_cbranch_scc0 .LBB5_12
.LBB5_27:                               ; %._crit_edge299
                                        ;   in Loop: Header=BB5_10 Depth=2
	v_subrev_nc_u32_e32 v16, s35, v16
	s_add_i32 s38, s38, 1
	s_add_i32 s37, s37, s29
	s_cmp_ge_i32 s38, s28
	s_cbranch_scc0 .LBB5_10
.LBB5_28:                               ; %._crit_edge303
                                        ;   in Loop: Header=BB5_8 Depth=1
	s_delay_alu instid0(VALU_DEP_4)
	v_subrev_nc_u32_e32 v14, s34, v14
	s_add_i32 s19, s19, 1
	s_add_i32 s6, s6, s36
	s_cmp_ge_i32 s19, s25
	s_cbranch_scc0 .LBB5_8
.LBB5_29:                               ; %._crit_edge307
	s_and_saveexec_b32 s0, s10
	s_cbranch_execz .LBB5_34
; %bb.30:                               ; %.preheader
	v_mad_u64_u32 v[7:8], null, s12, s11, v[2:3]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v7, s16, v[1:2]
	v_add_nc_u32_e32 v2, s14, v3
	v_mad_u64_u32 v[0:1], null, v8, s7, v[2:3]
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB5_32
; %bb.31:                               ; %.critedge274
	global_store_b32 v[0:1], v6, off
.LBB5_32:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v2, 16, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB5_34
; %bb.33:                               ; %.critedge274.1
	global_store_b32 v[0:1], v5, off offset:64
.LBB5_34:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
		.amdhsa_group_segment_fixed_size 3136
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 68
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 46
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii, .Lfunc_end5-_Z18kConvolve_backwardPfPKfS1_iiiiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2756
; NumSgprs: 48
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3136 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 48
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii ; -- Begin function _Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.globl	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
	.p2align	8
	.type	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii,@function
_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii: ; @_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
; %bb.0:                                ; %.critedge
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x48
	s_load_b128 s[20:23], s[0:1], 0x38
	s_load_b256 s[4:11], s[0:1], 0x18
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v4, 0
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, 0
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v3, 0
	v_bfe_u32 v2, v0, 10, 10
	s_mov_b32 s26, 0
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s28, s3, 31
	s_ashr_i32 s12, s2, 31
	s_add_i32 s3, s3, s28
	s_add_i32 s2, s2, s12
	s_xor_b32 s27, s3, s28
	s_xor_b32 s2, s2, s12
	v_cvt_f32_u32_e32 v1, s27
	s_sub_i32 s3, 0, s27
	s_xor_b32 s12, s12, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s29, v1
	s_mul_i32 s3, s3, s29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s29, s3
	s_add_i32 s29, s29, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s3, s2, s29
	s_mul_i32 s13, s3, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s2, s2, s13
	s_add_i32 s13, s3, 1
	s_sub_i32 s16, s2, s27
	s_cmp_ge_u32 s2, s27
	s_cselect_b32 s3, s13, s3
	s_cselect_b32 s2, s16, s2
	s_add_i32 s13, s3, 1
	s_cmp_ge_u32 s2, s27
	s_cselect_b32 s13, s13, s3
	s_ashr_i32 s30, s5, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s30, 27
	s_add_i32 s2, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s24, s2, 5
	v_cvt_f32_u32_e32 v1, s24
	s_sub_i32 s3, 0, s24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v1
	v_and_b32_e32 v1, 0x3ff, v0
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v0, s14, 5, v1
	s_mul_hi_u32 s3, s2, s3
	s_add_i32 s25, s2, s3
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mul_hi_u32 s0, s15, s25
	s_xor_b32 s1, s13, s12
	s_mul_i32 s13, s0, s24
	s_sub_i32 s25, s1, s12
	s_sub_i32 s1, s15, s13
	s_add_i32 s12, s0, 1
	s_sub_i32 s13, s1, s24
	s_cmp_ge_u32 s1, s24
	s_cselect_b32 s0, s12, s0
	s_cselect_b32 s1, s13, s1
	s_add_i32 s12, s0, 1
	s_cmp_ge_u32 s1, s24
	s_cselect_b32 s12, s12, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s0, s12, s24
	s_mul_i32 s24, s22, s21
	s_sub_i32 s0, s15, s0
	s_lshl_b32 s13, s0, 5
	s_cmp_lt_i32 s25, 1
	s_cbranch_scc1 .LBB6_24
; %bb.1:                                ; %.preheader225.lr.ph
	s_add_i32 s0, s5, s30
	s_xor_b32 s15, s30, s28
	s_xor_b32 s0, s0, s30
	v_lshrrev_b32_e32 v9, 5, v1
	s_mul_hi_u32 s1, s0, s29
	s_mul_i32 s33, s8, s7
	s_mul_i32 s14, s1, s27
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v14, v9, v2
	s_sub_i32 s0, s0, s14
	s_add_i32 s14, s1, 1
	s_sub_i32 s28, s0, s27
	s_cmp_ge_u32 s0, s27
	s_mul_i32 s33, s33, s6
	s_cselect_b32 s1, s14, s1
	s_cselect_b32 s0, s28, s0
	s_add_i32 s14, s1, 1
	s_cmp_ge_u32 s0, s27
	v_mul_lo_u32 v16, v14, s5
	s_cselect_b32 s0, s14, s1
	s_ashr_i32 s27, s13, 31
	s_xor_b32 s0, s0, s15
	s_add_i32 s28, s13, s27
	s_sub_i32 s0, s0, s15
	s_xor_b32 s28, s28, s27
	s_ashr_i32 s1, s0, 31
	v_lshl_add_u32 v11, v2, 2, 0x400
	s_add_i32 s0, s0, s1
	v_and_b32_e32 v10, 31, v1
	s_xor_b32 s0, s0, s1
	s_xor_b32 s1, s27, s1
	v_cvt_f32_u32_e32 v3, s0
	s_sub_i32 s15, 0, s0
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v18, 2, v10
	v_add3_u32 v17, v16, v10, s13
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v3, v3
	v_lshlrev_b32_e32 v12, 2, v1
	v_mov_b32_e32 v6, 0
	v_lshl_or_b32 v10, v14, 7, v18
	v_ashrrev_i32_e32 v18, 31, v17
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_add_nc_u32_e32 v16, 0x400, v10
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s14, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s14
	s_mul_hi_u32 s15, s14, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s14, s14, s15
	s_mul_hi_u32 s14, s28, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s14, s0
	s_add_i32 s27, s14, 1
	s_sub_i32 s15, s28, s15
	s_sub_i32 s28, s15, s0
	s_cmp_ge_u32 s15, s0
	s_cselect_b32 s14, s27, s14
	s_cselect_b32 s15, s28, s15
	s_add_i32 s27, s14, 1
	s_cmp_ge_u32 s15, s0
	s_cselect_b32 s0, s27, s14
	s_ashr_i32 s14, s24, 31
	s_ashr_i32 s29, s12, 31
	s_add_i32 s15, s24, s14
	s_add_i32 s30, s12, s29
	s_xor_b32 s15, s15, s14
	s_xor_b32 s30, s30, s29
	v_cvt_f32_u32_e32 v3, s15
	s_sub_i32 s28, 0, s15
	s_xor_b32 s0, s0, s1
	s_xor_b32 s14, s29, s14
	s_sub_i32 s1, s0, s1
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s27, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s28, s28, s27
	s_mul_hi_u32 s28, s27, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s27, s27, s28
	s_mul_hi_u32 s27, s30, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s28, s27, s15
	s_sub_i32 s0, s30, s28
	s_add_i32 s28, s27, 1
	s_sub_i32 s31, s0, s15
	s_cmp_ge_u32 s0, s15
	s_cselect_b32 s27, s28, s27
	s_cselect_b32 s0, s31, s0
	s_add_i32 s28, s27, 1
	s_cmp_ge_u32 s0, s15
	s_cselect_b32 s0, s28, s27
	s_ashr_i32 s15, s22, 31
	s_xor_b32 s0, s0, s14
	s_add_i32 s27, s22, s15
	s_sub_i32 s14, s0, s14
	s_xor_b32 s27, s27, s15
	s_xor_b32 s15, s29, s15
	v_cvt_f32_u32_e32 v3, s27
	s_sub_i32 s31, 0, s27
	s_mul_i32 s14, s14, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s28, v3
	s_mul_i32 s31, s31, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s31, s28, s31
	s_add_i32 s28, s28, s31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s28, s30, s28
	s_mul_i32 s29, s28, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s0, s30, s29
	s_add_i32 s29, s28, 1
	s_sub_i32 s30, s0, s27
	s_cmp_ge_u32 s0, s27
	s_cselect_b32 s28, s29, s28
	s_cselect_b32 s0, s30, s0
	s_add_i32 s29, s28, 1
	s_cmp_ge_u32 s0, s27
	s_cselect_b32 s27, s29, s28
	s_ashr_i32 s0, s21, 31
	s_xor_b32 s27, s27, s15
	s_add_i32 s21, s21, s0
	s_sub_i32 s15, s27, s15
	s_xor_b32 s28, s21, s0
	s_ashr_i32 s30, s15, 31
	v_cvt_f32_u32_e32 v3, s28
	s_sub_i32 s27, 0, s28
	s_add_i32 s31, s15, s30
	s_mul_i32 s15, s15, s22
	s_xor_b32 s31, s31, s30
	v_rcp_iflag_f32_e32 v3, v3
	s_mul_i32 s21, s9, s9
	v_cmp_le_i32_e64 s0, s4, v0
	v_cvt_f32_u32_e32 v1, s21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v4, v3
	v_mov_b32_e32 v3, 0
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s29, v4
	v_mov_b32_e32 v4, 0
	s_mul_i32 s27, s27, s29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s27, s29, s27
	s_add_i32 s29, s29, s27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s27, s31, s29
	s_mul_i32 s27, s27, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s29, s31, s27
	s_mul_i32 s27, s21, s9
	s_sub_i32 s31, s29, s28
	s_cmp_ge_u32 s29, s28
	s_mul_i32 s35, s27, s5
	s_cselect_b32 s29, s31, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s31, s29, s28
	s_cmp_ge_u32 s29, s28
	s_cselect_b32 s22, s31, s29
	s_sub_i32 s15, s12, s15
	s_xor_b32 s28, s22, s30
	s_add_i32 s22, s14, s10
	s_sub_i32 s14, s28, s30
	s_mul_i32 s28, s15, s11
	s_mul_i32 s29, s14, s11
	s_add_i32 s28, s28, s10
	s_add_i32 s29, s29, s10
	s_cmp_gt_i32 s27, 0
	s_cselect_b32 s30, -1, 0
	s_ashr_i32 s31, s9, 31
	s_lshl_b32 s5, s5, 2
	s_add_i32 s10, s9, s31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s34, s10, s31
	s_mul_i32 s10, s33, s23
	v_cvt_f32_u32_e32 v15, s34
	s_mul_i32 s11, s10, s25
	s_sub_i32 s14, 0, s34
	v_mad_u64_u32 v[19:20], null, s11, s1, v[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v21, v15
	v_mov_b32_e32 v7, 0
	v_cvt_u32_f32_e32 v1, v1
	s_sub_i32 s11, 0, s21
	v_lshl_add_u32 v15, v2, 7, v12
	v_cmp_gt_u32_e64 s1, 4, v14
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v26, s11, v1
	s_ashr_i32 s11, s10, 31
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v20, 0x4f7ffffe, v21
	v_lshlrev_b64 v[21:22], 2, v[17:18]
	v_add_nc_u32_e32 v17, 0x600, v10
	s_lshl_b64 s[10:11], s[10:11], 2
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_u32_f32_e32 v25, v20
	v_ashrrev_i32_e32 v20, 31, v19
	v_mul_hi_u32 v10, v1, v26
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v18, vcc_lo, s2, v21
	v_mul_lo_u32 v27, s14, v25
	v_lshlrev_b64 v[23:24], 2, v[19:20]
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v22, vcc_lo
	v_add_nc_u32_e32 v22, v1, v10
	v_mov_b32_e32 v10, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, s18, v23
	v_mul_hi_u32 v26, v25, v27
	v_add_co_ci_u32_e32 v21, vcc_lo, s19, v24, vcc_lo
	s_lshl_b32 s18, s35, 1
	s_mov_b32 s19, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr1
	v_add_nc_u32_e32 v23, v25, v26
.LBB6_2:                                ; %.preheader225
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB6_4 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB6_23
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB6_2 Depth=1
	s_mul_i32 s36, s19, s33
	s_mov_b32 s37, 0
	s_mov_b32 s14, s26
.LBB6_4:                                ;   Parent Loop BB6_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB6_9
; %bb.5:                                ;   in Loop: Header=BB6_4 Depth=2
	v_add_nc_u32_e32 v25, s37, v14
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_i32_e64 s27, v25
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB6_7
; %bb.6:                                ; %.preheader223.preheader
                                        ;   in Loop: Header=BB6_4 Depth=2
	ds_store_b32 v16, v13
	ds_store_b32 v17, v13
.LBB6_7:                                ; %Flow473
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB6_9
; %bb.8:                                ; %.preheader222.preheader
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_ashr_i32 s15, s14, 31
	s_add_i32 s38, s35, s14
	s_lshl_b64 s[40:41], s[14:15], 2
	s_ashr_i32 s39, s38, 31
	v_add_co_u32 v25, vcc_lo, v18, s40
	s_lshl_b64 s[38:39], s[38:39], 2
	v_add_co_ci_u32_e32 v26, vcc_lo, s41, v19, vcc_lo
	v_add_co_u32 v27, vcc_lo, v18, s38
	v_add_co_ci_u32_e32 v28, vcc_lo, s39, v19, vcc_lo
	s_clause 0x1
	global_load_b32 v25, v[25:26], off
	global_load_b32 v26, v[27:28], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v16, v25
	s_waitcnt vmcnt(0)
	ds_store_b32 v17, v26
.LBB6_9:                                ; %.critedge205
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v26, s37, v2
	s_mov_b32 s15, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s27, v26
	s_cbranch_execz .LBB6_22
; %bb.10:                               ;   in Loop: Header=BB6_4 Depth=2
	v_ashrrev_i32_e32 v27, 31, v26
	s_mov_b32 s3, 0
	s_mov_b32 s39, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v25, v26, v27
	v_xor_b32_e32 v28, v25, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v25, v28, v22
	v_mul_lo_u32 v29, v25, s21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v29, v28, v29
	v_subrev_nc_u32_e32 v31, s21, v29
	v_cmp_le_u32_e32 vcc_lo, s21, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v29, v29, v31 :: v_dual_add_nc_u32 v30, 1, v25
	v_cndmask_b32_e32 v25, v25, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s21, v29
	v_add_nc_u32_e32 v30, 1, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v25, v25, v30, vcc_lo
	v_xor_b32_e32 v25, v25, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v25, v25, v27
	v_add_nc_u32_e32 v25, s22, v25
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e64 s38, 0, v25
	v_cmpx_lt_i32_e32 -1, v25
	s_cbranch_execz .LBB6_14
; %bb.11:                               ;   in Loop: Header=BB6_4 Depth=2
	v_mul_hi_u32 v1, v28, v23
	v_xor_b32_e32 v27, s31, v27
	s_mov_b32 s40, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v29, v1, s34
	v_sub_nc_u32_e32 v28, v28, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v30, s34, v28
	v_cmp_le_u32_e32 vcc_lo, s34, v28
	v_dual_cndmask_b32 v28, v28, v30 :: v_dual_add_nc_u32 v29, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v29, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s34, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, 1, v1
	v_cndmask_b32_e32 v1, v1, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v27
	v_sub_nc_u32_e32 v27, v1, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v27
	v_add_nc_u32_e32 v28, v27, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v28, v28, v1
	v_mul_hi_u32 v29, v28, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v29, v29, s34
	v_sub_nc_u32_e32 v28, v28, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v29, s34, v28
	v_cmp_le_u32_e32 vcc_lo, s34, v28
	v_cndmask_b32_e32 v28, v28, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v29, s34, v28
	v_cmp_le_u32_e32 vcc_lo, s34, v28
	v_cndmask_b32_e32 v28, v28, v29, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s6, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v28, v28, v1
	v_sub_nc_u32_e32 v1, v28, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s29, v1
	v_cmp_lt_i32_e64 s2, -1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_xor_b32 s41, s2, -1
	s_and_saveexec_b32 s42, s2
	s_cbranch_execz .LBB6_13
; %bb.12:                               ;   in Loop: Header=BB6_4 Depth=2
	v_mul_lo_u32 v24, v27, s9
	v_cmp_le_i32_e32 vcc_lo, s7, v1
	s_mov_b32 s40, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v24, v26, v24
	v_add_nc_u32_e32 v24, s28, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e64 s2, s8, v24
	v_cmp_gt_i32_e64 s3, 0, v24
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
	s_and_not1_b32 s3, s41, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s41, s3, s2
.LBB6_13:                               ; %Flow469
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s42
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s38, exec_lo
	s_and_b32 s38, s41, exec_lo
	s_and_b32 s3, s40, exec_lo
	s_or_b32 s38, s2, s38
.LBB6_14:                               ; %Flow468
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s39
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s2, s38
	s_cbranch_execz .LBB6_16
; %bb.15:                               ; %.critedge210
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_and_not1_b32 s3, s3, exec_lo
	ds_store_2addr_stride64_b32 v15, v13, v13 offset1:2
.LBB6_16:                               ; %Flow470
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB6_21
; %bb.17:                               ; %.critedge208
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_and_saveexec_b32 s3, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB6_19
; %bb.18:                               ; %.preheader219.preheader
                                        ;   in Loop: Header=BB6_4 Depth=2
	ds_store_2addr_stride64_b32 v15, v13, v13 offset1:2
                                        ; implicit-def: $vgpr25
.LBB6_19:                               ; %Flow
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB6_21
; %bb.20:                               ; %.preheader218.preheader
                                        ;   in Loop: Header=BB6_4 Depth=2
	v_mad_u64_u32 v[26:27], null, v25, s7, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v25, v26, s8
	v_add3_u32 v25, v24, s36, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v25, v25, s23
	v_ashrrev_i32_e32 v26, 31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	v_add_co_u32 v25, vcc_lo, v20, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v26, vcc_lo, v21, v26, vcc_lo
	v_add_co_u32 v27, vcc_lo, v25, s10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v28, vcc_lo, s11, v26, vcc_lo
	s_clause 0x1
	global_load_b32 v25, v[25:26], off
	global_load_b32 v26, v[27:28], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v15, v25, v26 offset1:2
.LBB6_21:                               ; %Flow471
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
.LBB6_22:                               ; %.loopexit
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s15
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[25:26], v12 offset1:32
	ds_load_2addr_b32 v[27:28], v11 offset1:4
	ds_load_2addr_b32 v[29:30], v11 offset0:8 offset1:12
	ds_load_2addr_b32 v[31:32], v11 offset0:16 offset1:20
	ds_load_2addr_b32 v[33:34], v11 offset0:24 offset1:28
	ds_load_2addr_b32 v[35:36], v11 offset0:32 offset1:36
	ds_load_2addr_b32 v[37:38], v11 offset0:40 offset1:44
	ds_load_2addr_b32 v[39:40], v11 offset0:48 offset1:52
	ds_load_2addr_b32 v[41:42], v11 offset0:56 offset1:60
	ds_load_2addr_b32 v[43:44], v12 offset0:64 offset1:96
	ds_load_2addr_b32 v[45:46], v11 offset0:64 offset1:68
	ds_load_2addr_b32 v[47:48], v11 offset0:72 offset1:76
	ds_load_2addr_b32 v[49:50], v11 offset0:80 offset1:84
	s_add_i32 s37, s37, 4
	s_add_i32 s14, s14, s5
	s_cmp_ge_i32 s37, s27
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v9, v25, v28
	v_fmac_f32_e32 v10, v25, v27
	ds_load_2addr_b32 v[27:28], v11 offset0:88 offset1:92
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v7, v25, v30
	v_fmac_f32_e32 v8, v25, v29
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v4, v25, v32
	v_fmac_f32_e32 v5, v25, v31
	ds_load_2addr_b32 v[29:30], v11 offset0:96 offset1:100
	ds_load_2addr_b32 v[31:32], v11 offset0:104 offset1:108
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v3, v25, v34
	s_waitcnt lgkmcnt(10)
	v_dual_fmac_f32 v6, v25, v33 :: v_dual_fmac_f32 v9, v26, v36
	v_fmac_f32_e32 v10, v26, v35
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v7, v26, v38
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v3, v26, v42
	v_fmac_f32_e32 v8, v26, v37
	v_fmac_f32_e32 v6, v26, v41
	ds_load_2addr_b32 v[33:34], v11 offset0:112 offset1:116
	v_fmac_f32_e32 v4, v26, v40
	v_fmac_f32_e32 v5, v26, v39
	ds_load_2addr_b32 v[25:26], v11 offset0:120 offset1:124
	ds_load_2addr_b32 v[35:36], v12 offset0:128 offset1:160
	ds_load_2addr_b32 v[37:38], v11 offset0:128 offset1:132
	ds_load_2addr_b32 v[39:40], v11 offset0:136 offset1:140
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v9, v43, v46
	v_fmac_f32_e32 v10, v43, v45
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v7, v43, v48
	v_fmac_f32_e32 v8, v43, v47
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v3, v43, v28
	v_fmac_f32_e32 v6, v43, v27
	ds_load_2addr_b32 v[27:28], v11 offset0:144 offset1:148
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v9, v44, v30
	v_fmac_f32_e32 v10, v44, v29
	ds_load_2addr_b32 v[29:30], v11 offset0:152 offset1:156
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v7, v44, v32
	v_fmac_f32_e32 v8, v44, v31
	ds_load_2addr_b32 v[31:32], v11 offset0:160 offset1:164
	v_fmac_f32_e32 v4, v43, v50
	v_fmac_f32_e32 v5, v43, v49
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v3, v44, v26
	v_fmac_f32_e32 v6, v44, v25
	v_fmac_f32_e32 v4, v44, v34
	v_fmac_f32_e32 v5, v44, v33
	ds_load_2addr_b32 v[25:26], v11 offset0:168 offset1:172
	ds_load_2addr_b32 v[33:34], v11 offset0:176 offset1:180
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v9, v35, v38
	v_fmac_f32_e32 v10, v35, v37
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v7, v35, v40
	v_fmac_f32_e32 v8, v35, v39
	ds_load_2addr_b32 v[37:38], v11 offset0:184 offset1:188
	ds_load_2addr_b32 v[39:40], v12 offset0:192 offset1:224
	ds_load_2addr_b32 v[41:42], v11 offset0:192 offset1:196
	ds_load_2addr_b32 v[43:44], v11 offset0:200 offset1:204
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v4, v35, v28
	v_fmac_f32_e32 v5, v35, v27
	ds_load_2addr_b32 v[27:28], v11 offset0:208 offset1:212
	ds_load_2addr_b32 v[45:46], v11 offset0:216 offset1:220
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v3, v35, v30
	v_fmac_f32_e32 v6, v35, v29
	ds_load_2addr_b32 v[29:30], v11 offset0:224 offset1:228
	ds_load_2addr_b32 v[47:48], v11 offset0:232 offset1:236
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v9, v36, v32
	v_fmac_f32_e32 v10, v36, v31
	ds_load_2addr_b32 v[31:32], v11 offset0:240 offset1:244
	ds_load_2addr_b32 v[49:50], v11 offset0:248 offset1:252
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v7, v36, v26
	v_fmac_f32_e32 v8, v36, v25
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v4, v36, v34
	v_fmac_f32_e32 v5, v36, v33
	s_waitcnt lgkmcnt(9)
	v_fmac_f32_e32 v3, v36, v38
	s_waitcnt lgkmcnt(7)
	v_dual_fmac_f32 v6, v36, v37 :: v_dual_fmac_f32 v9, v39, v42
	v_fmac_f32_e32 v10, v39, v41
	s_waitcnt lgkmcnt(6)
	v_fmac_f32_e32 v7, v39, v44
	v_fmac_f32_e32 v8, v39, v43
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v4, v39, v28
	v_fmac_f32_e32 v5, v39, v27
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v3, v39, v46
	s_waitcnt lgkmcnt(3)
	v_dual_fmac_f32 v6, v39, v45 :: v_dual_fmac_f32 v9, v40, v30
	v_fmac_f32_e32 v10, v40, v29
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v7, v40, v48
	v_fmac_f32_e32 v8, v40, v47
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v4, v40, v32
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v40, v50
	v_fmac_f32_e32 v5, v40, v31
	v_fmac_f32_e32 v6, v40, v49
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB6_4
.LBB6_23:                               ; %._crit_edge
                                        ;   in Loop: Header=BB6_2 Depth=1
	s_add_i32 s19, s19, 2
	s_add_i32 s26, s26, s18
	s_cmp_ge_i32 s19, s25
	s_cbranch_scc0 .LBB6_2
.LBB6_24:                               ; %._crit_edge237
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB6_26
; %bb.25:                               ; %.preheader
	v_add_nc_u32_e32 v11, s13, v2
	s_mul_i32 s0, s24, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s8, s0, s4
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s2, s8, 3
	v_mad_u64_u32 v[1:2], null, v11, s0, s[12:13]
	s_lshl_b32 s0, s8, 2
	s_ashr_i32 s3, s2, 31
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[2:3], s[2:3], 2
	s_lshl_b64 s[0:1], s[0:1], 2
	s_lshl_b32 s6, s8, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[11:12], null, v1, s4, v[0:1]
	v_mov_b32_e32 v12, 0
	s_mul_i32 s4, s8, 12
	s_ashr_i32 s7, s6, 31
	s_ashr_i32 s5, s4, 31
	s_lshl_b64 s[4:5], s[4:5], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[11:12]
	v_add_co_u32 v0, vcc_lo, s16, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	global_store_b32 v[0:1], v10, off
	v_add_co_u32 v10, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v12, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v14, vcc_lo, v0, s4
	s_mul_i32 s0, s8, 20
	s_lshl_b64 s[2:3], s[6:7], 2
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v1, vcc_lo
	s_ashr_i32 s1, s0, 31
	s_clause 0x1
	global_store_b32 v[10:11], v9, off
	global_store_b32 v[12:13], v8, off
	v_add_co_u32 v8, vcc_lo, v0, s2
	s_mul_i32 s2, s8, 24
	s_lshl_b64 s[0:1], s[0:1], 2
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v1, vcc_lo
	s_ashr_i32 s3, s2, 31
	v_add_co_u32 v10, vcc_lo, v0, s0
	s_mul_i32 s0, s8, 28
	s_lshl_b64 s[2:3], s[2:3], 2
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v1, vcc_lo
	s_ashr_i32 s1, s0, 31
	v_add_co_u32 v12, vcc_lo, v0, s2
	s_lshl_b64 s[0:1], s[0:1], 2
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_clause 0x4
	global_store_b32 v[14:15], v7, off
	global_store_b32 v[8:9], v5, off
	global_store_b32 v[10:11], v4, off
	global_store_b32 v[12:13], v6, off
	global_store_b32 v[0:1], v3, off
.LBB6_26:                               ; %.critedge214
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 80
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 51
		.amdhsa_next_free_sgpr 43
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii, .Lfunc_end6-_Z19kConvolve_forward_cPfS_S_iiiiiiiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3340
; NumSgprs: 45
; NumVgprs: 51
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 45
; NumVGPRsForWavesPerEU: 51
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif ; -- Begin function _Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.globl	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
	.p2align	8
	.type	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif,@function
_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif: ; @_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
; %bb.0:                                ; %.preheader250
	s_load_b512 s[16:31], s[0:1], 0x18
	v_bfe_u32 v72, v0, 10, 10
	v_and_b32_e32 v71, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v0, v72, 4, v71
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s12, s29, 31
	s_ashr_i32 s3, s28, 31
	s_add_i32 s2, s29, s12
	s_add_i32 s4, s28, s3
	s_xor_b32 s8, s2, s12
	s_mul_i32 s29, s24, s24
	v_cvt_f32_u32_e32 v1, s8
	s_sub_i32 s2, 0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s13, v1
	s_mul_i32 s2, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s2, s13, s2
	s_add_i32 s13, s13, s2
	s_xor_b32 s2, s4, s3
	s_xor_b32 s3, s3, s12
	s_mul_hi_u32 s4, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s4, s8
	s_sub_i32 s2, s2, s5
	s_add_i32 s5, s4, 1
	s_sub_i32 s6, s2, s8
	s_cmp_ge_u32 s2, s8
	s_cselect_b32 s4, s5, s4
	s_cselect_b32 s2, s6, s2
	s_add_i32 s5, s4, 1
	s_cmp_ge_u32 s2, s8
	s_cselect_b32 s2, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s3
	s_sub_i32 s11, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s2, s11, 31
	s_lshr_b32 s2, s2, 29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s11, s2
	s_ashr_i32 s9, s2, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s9
	s_sub_i32 s3, 0, s9
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s2
	s_mul_hi_u32 s3, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s3
	s_mul_hi_u32 s2, s15, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s2, s9
	s_add_i32 s4, s2, 1
	s_sub_i32 s3, s15, s3
	s_sub_i32 s5, s3, s9
	s_cmp_ge_u32 s3, s9
	s_cselect_b32 s2, s4, s2
	s_cselect_b32 s3, s5, s3
	s_add_i32 s4, s2, 1
	s_cmp_ge_u32 s3, s9
	s_mov_b32 s3, exec_lo
	s_cselect_b32 s10, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s28, s10, 3
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB7_2
; %bb.1:
	s_ashr_i32 s2, s24, 31
	v_or_b32_e32 v2, s28, v0
	s_add_i32 s4, s24, s2
	v_cvt_f32_u32_e32 v7, s29
	s_xor_b32 s4, s4, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v2
	v_cvt_f32_u32_e32 v1, s4
	s_sub_i32 s5, 0, s4
	v_add_nc_u32_e32 v5, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	v_xor_b32_e32 v5, v5, v4
	v_xor_b32_e32 v4, s2, v4
	s_sub_i32 s2, 0, s29
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v3, s5, v1
	s_ashr_i32 s5, s28, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v1, v3
	v_add_nc_u32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v5, v1
	v_mul_lo_u32 v6, v3, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v6
	v_add_nc_u32_e32 v6, 1, v3
	v_subrev_nc_u32_e32 v8, s4, v5
	v_cmp_le_u32_e32 vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_rcp_iflag_f32_e32 v6, v7
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s4, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v6
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	v_add_nc_u32_e32 v7, s5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v5, v5
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v7, s5, v7
	v_sub_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s2, v5
	v_ashrrev_i32_e32 v6, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v5, v4
	v_add_nc_u32_e32 v8, v3, v6
	v_mul_lo_u32 v3, v3, s24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v8, v6
	v_add_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v2, v2, v3
	v_mul_hi_u32 v1, v8, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v7, v4
	v_mul_lo_u32 v1, v1, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v4, s29
	v_sub_nc_u32_e32 v1, v8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v7, v5
	v_add_nc_u32_e32 v7, 1, v4
	v_subrev_nc_u32_e32 v8, s4, v1
	v_cmp_le_u32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v9, s29, v5
	v_cmp_le_u32_e32 vcc_lo, s29, v5
	v_cndmask_b32_e64 v1, v1, v8, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v5, v5, v9
	v_subrev_nc_u32_e32 v8, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, 1, v4
	v_cmp_le_u32_e32 vcc_lo, s29, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v1
	v_xor_b32_e32 v4, s5, v4
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s5, v4
	v_xor_b32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v4, 16, v4
	v_sub_nc_u32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 8, v1
	v_add3_u32 v1, v1, v4, v2
	v_lshlrev_b32_e32 v2, 2, v0
	ds_store_b32 v2, v1 offset:12416
.LBB7_2:
	s_or_b32 exec_lo, exec_lo, s3
	s_ashr_i32 s35, s17, 31
	s_mul_i32 s24, s29, s24
	s_lshr_b32 s2, s35, 27
	s_mul_i32 s10, s10, s9
	s_add_i32 s2, s17, s2
	v_dual_mov_b32 v91, 0 :: v_dual_mov_b32 v82, 0
	s_ashr_i32 s34, s2, 5
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_cvt_f32_u32_e32 v1, s34
	s_sub_i32 s1, 0, s34
	v_dual_mov_b32 v83, 0 :: v_dual_mov_b32 v88, 0
	v_dual_mov_b32 v80, 0 :: v_dual_mov_b32 v87, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_iflag_f32_e32 v1, v1
	v_dual_mov_b32 v79, 0 :: v_dual_mov_b32 v86, 0
	v_dual_mov_b32 v78, 0 :: v_dual_mov_b32 v77, 0
	v_dual_mov_b32 v84, 0 :: v_dual_mov_b32 v75, 0
	v_dual_mov_b32 v74, 0 :: v_dual_mov_b32 v73, 0
	s_waitcnt_depctr 0xfff
	v_dual_mov_b32 v90, 0 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
	v_mov_b32_e32 v76, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	s_mul_i32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s1, s0, s1
	s_add_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s0, s14, s0
	s_mul_i32 s1, s0, s34
	s_add_i32 s9, s0, 1
	s_sub_i32 s1, s14, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s29, s1, s34
	s_cmp_ge_u32 s1, s34
	s_cselect_b32 s0, s9, s0
	s_cselect_b32 s1, s29, s1
	s_add_i32 s9, s0, 1
	s_cmp_ge_u32 s1, s34
	s_cselect_b32 s33, s9, s0
	s_sub_i32 s1, s15, s10
	s_mul_i32 s0, s33, s34
	s_lshl_b32 s34, s1, 3
	s_sub_i32 s0, s14, s0
	s_mov_b32 s9, 0
	s_lshl_b32 s29, s0, 5
	s_cmp_lt_i32 s30, 1
	s_cbranch_scc1 .LBB7_25
; %bb.3:                                ; %.lr.ph265
	s_add_i32 s0, s17, s35
	s_mul_i32 s10, s33, s30
	s_xor_b32 s0, s0, s35
	s_xor_b32 s12, s35, s12
	s_mul_hi_u32 s1, s0, s13
	s_add_i32 s30, s10, s30
	s_mul_i32 s13, s1, s8
	v_lshrrev_b32_e32 v81, 5, v0
	s_sub_i32 s0, s0, s13
	s_add_i32 s13, s1, 1
	s_sub_i32 s14, s0, s8
	s_cmp_ge_u32 s0, s8
	v_dual_mov_b32 v73, 0 :: v_dual_and_b32 v4, 31, v0
	s_cselect_b32 s1, s13, s1
	s_cselect_b32 s0, s14, s0
	s_add_i32 s13, s1, 1
	s_cmp_ge_u32 s0, s8
	s_movk_i32 s15, 0x2000
	s_cselect_b32 s0, s13, s1
	v_cmp_gt_u32_e64 s1, 0x400, v0
	s_xor_b32 s0, s0, s12
	v_mad_u32_u24 v92, 0x84, v71, s15
	s_sub_i32 s0, s0, s12
	s_ashr_i32 s37, s29, 31
	s_ashr_i32 s8, s0, 31
	s_add_i32 s38, s29, s37
	s_add_i32 s0, s0, s8
	s_xor_b32 s38, s38, s37
	s_xor_b32 s12, s0, s8
	v_cmp_gt_u32_e64 s0, 0x100, v0
	v_cvt_f32_u32_e32 v1, s12
	s_sub_i32 s15, 0, s12
	s_xor_b32 s8, s37, s8
	v_dual_mov_b32 v77, 0 :: v_dual_add_nc_u32 v2, s29, v81
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v1, v1
	s_mul_i32 s13, s20, s19
	v_mul_u32_u24_e32 v5, 0x84, v81
	s_mul_i32 s18, s13, s18
	v_lshlrev_b32_e32 v3, 2, v4
	s_mul_i32 s35, s23, s22
	v_dual_mov_b32 v89, 0 :: v_dual_mov_b32 v76, 0
	s_mul_i32 s35, s35, s21
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v0, 0x4f7ffffe, v1 :: v_dual_lshlrev_b32 v85, 7, v72
	v_add3_u32 v93, v5, v3, 0x2000
	v_dual_mov_b32 v75, 0 :: v_dual_mov_b32 v74, 0
	v_dual_mov_b32 v86, 0 :: v_dual_mov_b32 v79, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v0, v0
	v_dual_mov_b32 v87, 0 :: v_dual_mov_b32 v80, 0
	v_dual_mov_b32 v88, 0 :: v_dual_mov_b32 v83, 0
	v_readfirstlane_b32 s36, v0
	v_mad_u64_u32 v[0:1], null, v2, s18, s[10:11]
	v_dual_mov_b32 v82, 0 :: v_dual_mov_b32 v91, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_mul_i32 s15, s15, s36
	v_mov_b32_e32 v90, 0
	s_mul_hi_u32 s15, s36, s15
	s_mov_b32 s14, s16
	s_add_i32 s36, s36, s15
	v_mad_u64_u32 v[1:2], null, v0, s16, v[4:5]
	s_mul_hi_u32 s15, s38, s36
	v_mov_b32_e32 v78, 0
	s_mul_i32 s36, s15, s12
	s_add_i32 s37, s15, 1
	s_sub_i32 s36, s38, s36
	v_mov_b32_e32 v84, 0
	s_sub_i32 s38, s36, s12
	s_cmp_ge_u32 s36, s12
	v_ashrrev_i32_e32 v2, 31, v1
	s_cselect_b32 s15, s37, s15
	s_cselect_b32 s36, s38, s36
	s_add_i32 s37, s15, 1
	s_cmp_ge_u32 s36, s12
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_cselect_b32 s12, s37, s15
	s_mul_i32 s15, s35, s27
	s_xor_b32 s12, s12, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, s12, s8
	s_mul_i32 s12, s18, s16
	s_mul_i32 s8, s11, s8
	v_add_co_u32 v95, vcc_lo, s2, v0
	s_add_i32 s8, s34, s8
	s_cmp_gt_i32 s16, 0
	v_add_co_ci_u32_e32 v96, vcc_lo, s3, v1, vcc_lo
	s_cselect_b32 s18, -1, 0
	s_ashr_i32 s36, s13, 31
	s_ashr_i32 s39, s19, 31
	s_add_i32 s13, s13, s36
	s_add_i32 s40, s19, s39
	s_xor_b32 s19, s13, s36
	s_xor_b32 s39, s40, s39
	v_cvt_f32_u32_e32 v5, s19
	s_ashr_i32 s37, s20, 31
	v_cvt_f32_u32_e32 v7, s39
	s_add_i32 s38, s20, s37
	s_sub_i32 s2, 0, s19
	v_rcp_iflag_f32_e32 v2, v5
	s_xor_b32 s38, s38, s37
	v_rcp_iflag_f32_e32 v5, v7
	v_cvt_f32_u32_e32 v6, s38
	s_sub_i32 s3, 0, s38
	s_lshl_b32 s12, s12, 2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_lshl_or_b32 v94, v81, 7, v3
	v_rcp_iflag_f32_e32 v3, v6
	v_mad_u64_u32 v[0:1], null, s15, s8, v[4:5]
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_cvt_u32_f32_e32 v2, v2
	s_sub_i32 s8, 0, s39
	s_ashr_i32 s15, s16, 31
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v5, v5
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_readfirstlane_b32 s13, v2
	v_readfirstlane_b32 s42, v5
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v3, v3
	s_mul_i32 s2, s2, s13
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_mul_i32 s8, s8, s42
	s_mul_hi_u32 s2, s13, s2
	v_readfirstlane_b32 s41, v3
	v_add_co_u32 v97, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v98, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	s_mul_i32 s3, s3, s41
	s_mul_hi_u32 s6, s42, s8
	s_mul_hi_u32 s3, s41, s3
	s_add_i32 s40, s13, s2
	s_add_i32 s41, s41, s3
	s_add_i32 s42, s42, s6
	s_ashr_i32 s13, s12, 31
	s_lshl_b64 s[6:7], s[14:15], 2
.LBB7_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB7_6 Depth 2
                                        ;       Child Loop BB7_8 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB7_24
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB7_4 Depth=1
	s_ashr_i32 s2, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s10, s2
	s_xor_b32 s15, s2, s36
	s_xor_b32 s3, s3, s2
	s_mul_hi_u32 s8, s3, s40
	s_mul_hi_u32 s45, s3, s41
	s_mul_i32 s14, s8, s19
	s_add_i32 s43, s8, 1
	s_sub_i32 s14, s3, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s44, s14, s19
	s_cmp_ge_u32 s14, s19
	s_cselect_b32 s8, s43, s8
	s_cselect_b32 s14, s44, s14
	s_add_i32 s43, s8, 1
	s_cmp_ge_u32 s14, s19
	s_mul_i32 s14, s45, s38
	s_cselect_b32 s8, s43, s8
	s_sub_i32 s3, s3, s14
	s_xor_b32 s8, s8, s15
	s_xor_b32 s2, s2, s37
	s_sub_i32 s8, s8, s15
	s_add_i32 s15, s45, 1
	s_mul_i32 s14, s8, s26
	s_sub_i32 s8, s3, s38
	s_add_i32 s14, s14, s25
	s_cmp_ge_u32 s3, s38
	s_cselect_b32 s15, s15, s45
	s_cselect_b32 s3, s8, s3
	s_add_i32 s8, s15, 1
	s_cmp_ge_u32 s3, s38
	s_cselect_b32 s3, s8, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	s_sub_i32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_add_i32 s8, s2, s3
	s_mul_i32 s2, s2, s20
	s_xor_b32 s8, s8, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s15, s8, s42
	s_mul_i32 s15, s15, s39
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s8, s8, s15
	s_sub_i32 s15, s8, s39
	s_cmp_ge_u32 s8, s39
	s_cselect_b32 s8, s15, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s15, s8, s39
	s_cmp_ge_u32 s8, s39
	s_cselect_b32 s8, s15, s8
	s_sub_i32 s2, s10, s2
	s_xor_b32 s8, s8, s3
	s_mul_i32 s15, s2, s26
	s_sub_i32 s3, s8, s3
	s_add_i32 s15, s15, s25
	s_mul_i32 s43, s3, s26
	s_mov_b32 s8, 0
	s_add_i32 s43, s43, s25
.LBB7_6:                                ; %.lr.ph
                                        ;   Parent Loop BB7_4 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB7_8 Depth 3
	v_or_b32_e32 v0, s8, v4
	s_and_saveexec_b32 s44, s0
	s_cbranch_execz .LBB7_21
; %bb.7:                                ; %.preheader248
                                        ;   in Loop: Header=BB7_6 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s16, v0
	s_mov_b32 s2, 0
	s_mov_b32 s46, -1
	s_xor_b32 s45, vcc_lo, -1
.LBB7_8:                                ;   Parent Loop BB7_4 Depth=1
                                        ;     Parent Loop BB7_6 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v2, s2, v81
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s28, v2
	v_cmp_le_i32_e32 vcc_lo, s24, v1
	v_lshl_add_u32 v1, s2, 7, v94
	s_or_b32 s2, vcc_lo, s45
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_xor_b32 s2, exec_lo, s3
	s_cbranch_execz .LBB7_10
; %bb.9:                                ; %.preheader244
                                        ;   in Loop: Header=BB7_8 Depth=3
	ds_store_2addr_stride64_b32 v1, v89, v89 offset1:4
	ds_store_2addr_stride64_b32 v1, v89, v89 offset0:8 offset1:12
	ds_store_2addr_stride64_b32 v1, v89, v89 offset0:16 offset1:20
	ds_store_2addr_stride64_b32 v1, v89, v89 offset0:24 offset1:28
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr2
.LBB7_10:                               ; %Flow1252
                                        ;   in Loop: Header=BB7_8 Depth=3
	s_and_not1_saveexec_b32 s47, s2
	s_cbranch_execz .LBB7_20
; %bb.11:                               ;   in Loop: Header=BB7_8 Depth=3
	v_lshlrev_b32_e32 v2, 2, v2
	s_mov_b32 s3, 0
	s_mov_b32 s49, exec_lo
	ds_load_b32 v3, v2 offset:12416
	s_waitcnt lgkmcnt(0)
	v_bfe_u32 v2, v3, 16, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s14, v2
	v_cmp_gt_i32_e64 s48, 0, v2
	v_cmpx_lt_i32_e32 -1, v2
	s_cbranch_execz .LBB7_15
; %bb.12:                               ;   in Loop: Header=BB7_8 Depth=3
	v_bfe_u32 v6, v3, 8, 8
	v_cmp_gt_i32_e32 vcc_lo, s21, v2
	s_mov_b32 s50, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s43, v6
	v_cmp_lt_i32_e64 s2, -1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_xor_b32 s51, s2, -1
	s_and_saveexec_b32 s52, s2
; %bb.13:                               ;   in Loop: Header=BB7_8 Depth=3
	v_and_b32_e32 v3, 0xff, v3
	v_cmp_le_i32_e32 vcc_lo, s22, v6
	s_mov_b32 s50, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s15, v3
	v_cmp_le_i32_e64 s2, s23, v5
	v_cmp_gt_i32_e64 s3, 0, v5
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
	s_and_not1_b32 s3, s51, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s51, s3, s2
; %bb.14:                               ; %Flow1249
                                        ;   in Loop: Header=BB7_8 Depth=3
	s_or_b32 exec_lo, exec_lo, s52
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s48, exec_lo
	s_and_b32 s48, s51, exec_lo
	s_and_b32 s3, s50, exec_lo
	s_or_b32 s48, s2, s48
.LBB7_15:                               ; %Flow
                                        ;   in Loop: Header=BB7_8 Depth=3
	s_or_b32 exec_lo, exec_lo, s49
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s2, s48
	s_cbranch_execz .LBB7_17
; %bb.16:                               ; %.loopexit242.loopexit269
                                        ;   in Loop: Header=BB7_8 Depth=3
	s_and_not1_b32 s3, s3, exec_lo
	ds_store_2addr_stride64_b32 v1, v89, v89 offset1:4
	ds_store_2addr_stride64_b32 v1, v89, v89 offset0:8 offset1:12
	ds_store_2addr_stride64_b32 v1, v89, v89 offset0:16 offset1:20
	ds_store_2addr_stride64_b32 v1, v89, v89 offset0:24 offset1:28
.LBB7_17:                               ; %Flow1250
                                        ;   in Loop: Header=BB7_8 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB7_19
; %bb.18:                               ; %.loopexit242.loopexit
                                        ;   in Loop: Header=BB7_8 Depth=3
	v_mad_u64_u32 v[7:8], null, v2, s22, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, s23, v[5:6]
	v_add_nc_u32_e32 v9, s35, v2
	v_mad_u64_u32 v[7:8], null, v2, s27, s[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, v9, s27, s[8:9]
	v_add_nc_u32_e32 v3, s35, v9
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[9:10], null, v3, s27, s[8:9]
	v_add_nc_u32_e32 v10, s35, v3
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[11:12], null, v10, s27, s[8:9]
	v_add_nc_u32_e32 v12, s35, v10
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v7, vcc_lo, v97, v7
	v_mad_u64_u32 v[13:14], null, v12, s27, s[8:9]
	v_add_nc_u32_e32 v14, s35, v12
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_ci_u32_e32 v8, vcc_lo, v98, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[15:16], null, v14, s27, s[8:9]
	v_add_nc_u32_e32 v16, s35, v14
	v_ashrrev_i32_e32 v14, 31, v13
	v_add_co_u32 v2, vcc_lo, v97, v2
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_mad_u64_u32 v[17:18], null, v16, s27, s[8:9]
	v_add_nc_u32_e32 v18, s35, v16
	v_ashrrev_i32_e32 v16, 31, v15
	v_add_co_ci_u32_e32 v3, vcc_lo, v98, v3, vcc_lo
	v_add_co_u32 v9, vcc_lo, v97, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[19:20], null, v18, s27, s[8:9]
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_ci_u32_e32 v10, vcc_lo, v98, v10, vcc_lo
	v_add_co_u32 v11, vcc_lo, v97, v11
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	v_ashrrev_i32_e32 v20, 31, v19
	v_add_co_ci_u32_e32 v12, vcc_lo, v98, v12, vcc_lo
	v_add_co_u32 v13, vcc_lo, v97, v13
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_add_co_ci_u32_e32 v14, vcc_lo, v98, v14, vcc_lo
	v_add_co_u32 v15, vcc_lo, v97, v15
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	v_add_co_ci_u32_e32 v16, vcc_lo, v98, v16, vcc_lo
	v_add_co_u32 v17, vcc_lo, v97, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, v98, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v19, vcc_lo, v97, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, v98, v20, vcc_lo
	s_clause 0x7
	global_load_b32 v7, v[7:8], off
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[9:10], off
	global_load_b32 v8, v[11:12], off
	global_load_b32 v9, v[13:14], off
	global_load_b32 v10, v[15:16], off
	global_load_b32 v11, v[17:18], off
	global_load_b32 v12, v[19:20], off
	s_waitcnt vmcnt(6)
	ds_store_2addr_stride64_b32 v1, v7, v2 offset1:4
	s_waitcnt vmcnt(4)
	ds_store_2addr_stride64_b32 v1, v3, v8 offset0:8 offset1:12
	s_waitcnt vmcnt(2)
	ds_store_2addr_stride64_b32 v1, v9, v10 offset0:16 offset1:20
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v1, v11, v12 offset0:24 offset1:28
.LBB7_19:                               ; %Flow1251
                                        ;   in Loop: Header=BB7_8 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
.LBB7_20:                               ; %.loopexit242
                                        ;   in Loop: Header=BB7_8 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s47
	s_xor_b32 s3, s46, -1
	s_mov_b32 s2, 4
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_mov_b32 s46, 0
	s_cbranch_vccnz .LBB7_8
.LBB7_21:                               ; %Flow1255
                                        ;   in Loop: Header=BB7_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s44
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s16, v0
	s_and_b32 s3, s1, vcc_lo
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB7_23
; %bb.22:                               ; %.preheader246.preheader
                                        ;   in Loop: Header=BB7_6 Depth=2
	s_lshl_b64 s[44:45], s[8:9], 2
	s_add_i32 s3, s12, s8
	v_add_co_u32 v0, vcc_lo, v95, s44
	v_add_co_ci_u32_e32 v1, vcc_lo, s45, v96, vcc_lo
	s_add_i32 s46, s3, s12
	s_lshl_b64 s[44:45], s[12:13], 2
	s_ashr_i32 s47, s46, 31
	v_add_co_u32 v2, vcc_lo, v0, s44
	s_add_i32 s44, s46, s12
	s_lshl_b64 s[46:47], s[46:47], 2
	v_add_co_ci_u32_e32 v3, vcc_lo, s45, v1, vcc_lo
	s_ashr_i32 s45, s44, 31
	v_add_co_u32 v7, vcc_lo, v95, s46
	v_add_co_ci_u32_e32 v8, vcc_lo, s47, v96, vcc_lo
	s_lshl_b64 s[46:47], s[44:45], 2
	s_add_i32 s44, s44, s12
	v_add_co_u32 v9, vcc_lo, v95, s46
	s_ashr_i32 s45, s44, 31
	s_add_i32 s46, s44, s12
	s_lshl_b64 s[44:45], s[44:45], 2
	v_add_co_ci_u32_e32 v10, vcc_lo, s47, v96, vcc_lo
	s_ashr_i32 s47, s46, 31
	v_add_co_u32 v11, vcc_lo, v95, s44
	v_add_co_ci_u32_e32 v12, vcc_lo, s45, v96, vcc_lo
	s_lshl_b64 s[44:45], s[46:47], 2
	s_add_i32 s46, s46, s12
	v_add_co_u32 v13, vcc_lo, v95, s44
	s_ashr_i32 s47, s46, 31
	s_add_i32 s44, s46, s12
	s_lshl_b64 s[46:47], s[46:47], 2
	v_add_co_ci_u32_e32 v14, vcc_lo, s45, v96, vcc_lo
	s_ashr_i32 s45, s44, 31
	v_add_co_u32 v15, vcc_lo, v95, s46
	s_lshl_b64 s[44:45], s[44:45], 2
	v_add_co_ci_u32_e32 v16, vcc_lo, s47, v96, vcc_lo
	v_add_co_u32 v17, vcc_lo, v95, s44
	v_add_co_ci_u32_e32 v18, vcc_lo, s45, v96, vcc_lo
	s_clause 0x7
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[2:3], off
	global_load_b32 v2, v[7:8], off
	global_load_b32 v3, v[9:10], off
	global_load_b32 v7, v[11:12], off
	global_load_b32 v8, v[13:14], off
	global_load_b32 v9, v[15:16], off
	global_load_b32 v10, v[17:18], off
	v_add_nc_u32_e32 v11, 0x400, v93
	v_add_nc_u32_e32 v12, 0x800, v93
	v_add_nc_u32_e32 v13, 0xc00, v93
	s_waitcnt vmcnt(6)
	ds_store_2addr_b32 v93, v0, v1 offset1:132
	s_waitcnt vmcnt(4)
	ds_store_2addr_b32 v11, v2, v3 offset0:8 offset1:140
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v12, v7, v8 offset0:16 offset1:148
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v13, v9, v10 offset0:24 offset1:156
.LBB7_23:                               ; %.loopexit247
                                        ;   in Loop: Header=BB7_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v7, 0x840, v92
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b128 v[0:3], v85
	ds_load_2addr_b32 v[19:20], v92 offset1:1
	ds_load_2addr_b32 v[17:18], v7 offset1:1
	v_add_nc_u32_e32 v7, 0x848, v92
	v_add_nc_u32_e32 v8, 0x858, v92
	ds_load_2addr_b32 v[21:22], v92 offset0:2 offset1:3
	ds_load_2addr_b32 v[15:16], v7 offset1:1
	v_add_nc_u32_e32 v7, 0x850, v92
	s_add_i32 s8, s8, 32
	v_add_nc_u32_e32 v36, 0x868, v92
	s_cmp_ge_i32 s8, s16
	v_add_nc_u32_e32 v46, 0x870, v92
	s_waitcnt lgkmcnt(3)
	v_dual_fmac_f32 v91, v0, v19 :: v_dual_add_nc_u32 v48, 0x880, v92
	ds_load_b128 v[32:35], v85 offset:16
	ds_load_2addr_b32 v[13:14], v92 offset0:4 offset1:5
	ds_load_2addr_b32 v[9:10], v92 offset0:6 offset1:7
	ds_load_2addr_b32 v[11:12], v7 offset1:1
	ds_load_2addr_b32 v[7:8], v8 offset1:1
	ds_load_b128 v[38:41], v85 offset:1024
	ds_load_b128 v[42:45], v85 offset:32
	ds_load_b128 v[52:55], v85 offset:48
	s_waitcnt lgkmcnt(10)
	v_fmac_f32_e32 v83, v0, v17
	ds_load_2addr_b32 v[29:30], v92 offset0:8 offset1:9
	ds_load_2addr_b32 v[27:28], v92 offset0:10 offset1:11
	ds_load_2addr_b32 v[25:26], v92 offset0:12 offset1:13
	ds_load_2addr_b32 v[23:24], v92 offset0:14 offset1:15
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v83, v1, v18 :: v_dual_fmac_f32 v90, v38, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v83, v2, v15
	v_fmac_f32_e32 v82, v38, v17
	v_fmac_f32_e32 v90, v39, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v91, v1, v20 :: v_dual_fmac_f32 v82, v39, v18
	v_dual_fmac_f32 v90, v40, v21 :: v_dual_add_nc_u32 v31, 0x860, v92
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v91, v2, v21
	v_dual_fmac_f32 v83, v3, v16 :: v_dual_fmac_f32 v82, v40, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v90, v41, v22
	v_fmac_f32_e32 v91, v3, v22
	ds_load_b128 v[0:3], v85 offset:1040
	v_dual_fmac_f32 v82, v41, v16 :: v_dual_fmac_f32 v83, v32, v11
	v_fmac_f32_e32 v91, v32, v13
	ds_load_2addr_b32 v[31:32], v31 offset1:1
	v_add_nc_u32_e32 v47, 0x878, v92
	v_add_nc_u32_e32 v51, 0x888, v92
	ds_load_b128 v[56:59], v85 offset:64
	ds_load_b128 v[60:63], v85 offset:80
	ds_load_2addr_b32 v[37:38], v36 offset1:1
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v82, v0, v11
	v_fmac_f32_e32 v90, v0, v13
	v_add_nc_u32_e32 v0, 0x898, v92
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v82, v1, v12
	v_fmac_f32_e32 v83, v33, v12
	v_fmac_f32_e32 v90, v1, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v91, v33, v14 :: v_dual_fmac_f32 v82, v2, v7
	v_fmac_f32_e32 v83, v34, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v90, v2, v9
	v_dual_fmac_f32 v91, v34, v9 :: v_dual_fmac_f32 v82, v3, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v83, v35, v8
	v_fmac_f32_e32 v90, v3, v10
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v91, v35, v10
	ds_load_2addr_b32 v[35:36], v46 offset1:1
	ds_load_2addr_b32 v[33:34], v47 offset1:1
	ds_load_b128 v[64:67], v85 offset:1056
	ds_load_b128 v[99:102], v85 offset:1072
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v90, v64, v29
	v_dual_fmac_f32 v91, v42, v29 :: v_dual_fmac_f32 v82, v64, v31
	v_dual_fmac_f32 v83, v42, v31 :: v_dual_add_nc_u32 v64, 0x8a0, v92
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v90, v65, v30
	v_dual_fmac_f32 v91, v43, v30 :: v_dual_fmac_f32 v82, v65, v32
	v_add_nc_u32_e32 v47, 0x890, v92
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v83, v43, v32 :: v_dual_fmac_f32 v90, v66, v27
	v_dual_fmac_f32 v91, v44, v27 :: v_dual_fmac_f32 v82, v66, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v83, v44, v37 :: v_dual_fmac_f32 v90, v67, v28
	v_dual_fmac_f32 v91, v45, v28 :: v_dual_fmac_f32 v82, v67, v38
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v83, v45, v38 :: v_dual_fmac_f32 v90, v99, v25
	v_dual_fmac_f32 v91, v52, v25 :: v_dual_fmac_f32 v82, v99, v35
	ds_load_2addr_b32 v[43:44], v92 offset0:16 offset1:17
	ds_load_2addr_b32 v[45:46], v92 offset0:18 offset1:19
	ds_load_2addr_b32 v[41:42], v92 offset0:20 offset1:21
	ds_load_2addr_b32 v[39:40], v92 offset0:22 offset1:23
	ds_load_2addr_b32 v[49:50], v48 offset1:1
	v_fmac_f32_e32 v90, v100, v26
	v_dual_fmac_f32 v91, v53, v26 :: v_dual_fmac_f32 v82, v100, v36
	v_fmac_f32_e32 v83, v52, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v90, v101, v23
	v_fmac_f32_e32 v82, v101, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v83, v53, v36
	v_fmac_f32_e32 v90, v102, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v82, v102, v34
	v_fmac_f32_e32 v91, v54, v23
	v_fmac_f32_e32 v83, v54, v33
	ds_load_2addr_b32 v[53:54], v51 offset1:1
	ds_load_2addr_b32 v[51:52], v47 offset1:1
	ds_load_2addr_b32 v[47:48], v0 offset1:1
	ds_load_b128 v[0:3], v85 offset:1088
	ds_load_b128 v[103:106], v85 offset:96
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v83, v55, v34 :: v_dual_fmac_f32 v82, v0, v49
	v_dual_fmac_f32 v91, v55, v24 :: v_dual_fmac_f32 v90, v0, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v83, v56, v49 :: v_dual_add_nc_u32 v0, 0x8a8, v92
	v_dual_fmac_f32 v82, v1, v50 :: v_dual_fmac_f32 v91, v56, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v90, v1, v44
	v_dual_fmac_f32 v83, v57, v50 :: v_dual_fmac_f32 v82, v2, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v91, v57, v44 :: v_dual_fmac_f32 v90, v2, v45
	v_dual_fmac_f32 v83, v58, v53 :: v_dual_fmac_f32 v82, v3, v54
	s_delay_alu instid0(VALU_DEP_2)
	v_fmac_f32_e32 v91, v58, v45
	ds_load_2addr_b32 v[57:58], v92 offset0:24 offset1:25
	ds_load_2addr_b32 v[55:56], v92 offset0:26 offset1:27
	ds_load_b128 v[99:102], v85 offset:2048
	ds_load_b128 v[107:110], v85 offset:1104
	ds_load_b128 v[111:114], v85 offset:112
	v_fmac_f32_e32 v91, v59, v46
	v_fmac_f32_e32 v90, v3, v46
	ds_load_2addr_b32 v[69:70], v0 offset1:1
	v_add_nc_u32_e32 v0, 0x8b0, v92
	v_add_nc_u32_e32 v1, 0x8b8, v92
	s_waitcnt lgkmcnt(3)
	v_dual_fmac_f32 v91, v60, v41 :: v_dual_fmac_f32 v88, v99, v19
	v_fmac_f32_e32 v83, v59, v54
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_fmac_f32 v91, v61, v42 :: v_dual_fmac_f32 v80, v99, v17
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v90, v107, v41
	v_fmac_f32_e32 v88, v100, v20
	v_fmac_f32_e32 v83, v60, v51
	ds_load_2addr_b32 v[59:60], v64 offset1:1
	v_fmac_f32_e32 v91, v62, v39
	v_fmac_f32_e32 v82, v107, v51
	v_dual_fmac_f32 v80, v100, v18 :: v_dual_fmac_f32 v83, v61, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v88, v101, v21 :: v_dual_fmac_f32 v91, v63, v40
	v_fmac_f32_e32 v90, v108, v42
	v_dual_fmac_f32 v82, v108, v52 :: v_dual_fmac_f32 v83, v62, v47
	ds_load_2addr_b32 v[65:66], v92 offset0:28 offset1:29
	ds_load_2addr_b32 v[61:62], v92 offset0:30 offset1:31
	v_dual_fmac_f32 v91, v103, v57 :: v_dual_fmac_f32 v80, v101, v15
	v_dual_fmac_f32 v88, v102, v22 :: v_dual_fmac_f32 v83, v63, v48
	ds_load_2addr_b32 v[67:68], v0 offset1:1
	ds_load_2addr_b32 v[63:64], v1 offset1:1
	ds_load_b128 v[115:118], v85 offset:2064
	v_dual_fmac_f32 v91, v104, v58 :: v_dual_fmac_f32 v90, v109, v39
	s_waitcnt lgkmcnt(5)
	v_dual_fmac_f32 v80, v102, v16 :: v_dual_fmac_f32 v83, v103, v59
	ds_load_b128 v[99:102], v85 offset:2080
	v_fmac_f32_e32 v91, v105, v55
	v_fmac_f32_e32 v82, v109, v47
	v_fmac_f32_e32 v90, v110, v40
	v_fmac_f32_e32 v83, v104, v60
	ds_load_b128 v[0:3], v85 offset:1120
	v_fmac_f32_e32 v91, v106, v56
	v_fmac_f32_e32 v82, v110, v48
	ds_load_b128 v[107:110], v85 offset:1136
	v_fmac_f32_e32 v83, v105, v69
	ds_load_b128 v[119:122], v85 offset:5120
	s_waitcnt lgkmcnt(8)
	v_fmac_f32_e32 v91, v111, v65
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v88, v115, v13
	v_dual_fmac_f32 v80, v115, v11 :: v_dual_fmac_f32 v83, v106, v70
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v91, v112, v66
	ds_load_b128 v[103:106], v85 offset:3072
	v_fmac_f32_e32 v88, v116, v14
	v_dual_fmac_f32 v80, v116, v12 :: v_dual_fmac_f32 v83, v111, v67
	v_fmac_f32_e32 v91, v113, v61
	v_fmac_f32_e32 v88, v117, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v80, v117, v7 :: v_dual_fmac_f32 v83, v112, v68
	v_fmac_f32_e32 v91, v114, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v88, v118, v10
	v_dual_fmac_f32 v80, v118, v8 :: v_dual_fmac_f32 v83, v113, v63
	ds_load_b128 v[115:118], v85 offset:2096
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v90, v0, v57
	v_fmac_f32_e32 v88, v99, v29
	v_dual_fmac_f32 v80, v99, v31 :: v_dual_fmac_f32 v83, v114, v64
	ds_load_b128 v[111:114], v85 offset:3088
	v_fmac_f32_e32 v88, v100, v30
	v_fmac_f32_e32 v80, v100, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v88, v101, v27
	v_fmac_f32_e32 v80, v101, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v88, v102, v28
	v_fmac_f32_e32 v80, v102, v38
	ds_load_b128 v[99:102], v85 offset:2112
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v88, v115, v25
	v_fmac_f32_e32 v80, v115, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v88, v116, v26
	v_fmac_f32_e32 v80, v116, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v88, v117, v23
	v_fmac_f32_e32 v80, v117, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v88, v118, v24
	v_fmac_f32_e32 v80, v118, v34
	ds_load_b128 v[115:118], v85 offset:2160
	v_dual_fmac_f32 v82, v0, v59 :: v_dual_fmac_f32 v79, v103, v17
	v_fmac_f32_e32 v87, v103, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v79, v104, v18
	v_fmac_f32_e32 v87, v104, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v79, v105, v15
	v_fmac_f32_e32 v90, v1, v58
	v_fmac_f32_e32 v87, v105, v21
	v_fmac_f32_e32 v82, v1, v60
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v79, v106, v16
	v_fmac_f32_e32 v87, v106, v22
	v_fmac_f32_e32 v90, v2, v55
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v82, v2, v69
	ds_load_b128 v[103:106], v85 offset:2128
	v_fmac_f32_e32 v90, v3, v56
	v_fmac_f32_e32 v82, v3, v70
	ds_load_b128 v[0:3], v85 offset:3104
	s_waitcnt lgkmcnt(4)
	v_fmac_f32_e32 v87, v111, v13
	v_fmac_f32_e32 v79, v111, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v87, v112, v14
	v_fmac_f32_e32 v79, v112, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v87, v113, v9
	v_fmac_f32_e32 v79, v113, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v87, v114, v10
	v_fmac_f32_e32 v79, v114, v8
	ds_load_b128 v[111:114], v85 offset:3120
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v87, v0, v29
	v_fmac_f32_e32 v79, v0, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v87, v1, v30 :: v_dual_fmac_f32 v90, v107, v65
	v_fmac_f32_e32 v79, v1, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v87, v2, v27
	v_fmac_f32_e32 v79, v2, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v87, v3, v28
	v_fmac_f32_e32 v79, v3, v38
	ds_load_b128 v[0:3], v85 offset:3136
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v87, v111, v25
	v_fmac_f32_e32 v88, v99, v43
	v_fmac_f32_e32 v79, v111, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v80, v99, v49 :: v_dual_fmac_f32 v87, v112, v26
	v_fmac_f32_e32 v88, v100, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v79, v112, v36
	v_fmac_f32_e32 v80, v100, v50
	v_fmac_f32_e32 v82, v107, v67
	v_dual_fmac_f32 v87, v113, v23 :: v_dual_fmac_f32 v90, v108, v66
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v79, v113, v33
	v_dual_fmac_f32 v88, v101, v45 :: v_dual_fmac_f32 v87, v114, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v80, v101, v53 :: v_dual_fmac_f32 v79, v114, v34
	v_fmac_f32_e32 v88, v102, v46
	ds_load_b128 v[111:114], v85 offset:4112
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v87, v0, v43 :: v_dual_fmac_f32 v80, v102, v54
	ds_load_b128 v[99:102], v85 offset:2144
	v_fmac_f32_e32 v79, v0, v49
	v_fmac_f32_e32 v82, v108, v68
	v_dual_fmac_f32 v87, v1, v44 :: v_dual_fmac_f32 v80, v103, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v79, v1, v50
	v_fmac_f32_e32 v87, v2, v45
	v_fmac_f32_e32 v90, v109, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v79, v2, v53 :: v_dual_fmac_f32 v80, v104, v52
	v_dual_fmac_f32 v87, v3, v46 :: v_dual_fmac_f32 v82, v109, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v90, v110, v62
	v_fmac_f32_e32 v79, v3, v54
	ds_load_b128 v[0:3], v85 offset:3184
	v_fmac_f32_e32 v82, v110, v64
	ds_load_b128 v[107:110], v85 offset:3152
	v_fmac_f32_e32 v88, v103, v41
	v_fmac_f32_e32 v80, v105, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v88, v104, v42
	v_fmac_f32_e32 v80, v106, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v88, v105, v39
	v_fmac_f32_e32 v88, v106, v40
	ds_load_b128 v[103:106], v85 offset:4096
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v86, v103, v19
	v_fmac_f32_e32 v78, v103, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v86, v104, v20
	v_fmac_f32_e32 v78, v104, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v86, v105, v21
	v_fmac_f32_e32 v78, v105, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v86, v106, v22
	v_fmac_f32_e32 v78, v106, v16
	ds_load_b128 v[103:106], v85 offset:3168
	v_fmac_f32_e32 v87, v107, v41
	v_fmac_f32_e32 v79, v107, v51
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v87, v108, v42
	v_dual_fmac_f32 v79, v108, v52 :: v_dual_fmac_f32 v88, v99, v57
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v87, v109, v39
	v_fmac_f32_e32 v79, v109, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v80, v99, v59 :: v_dual_fmac_f32 v87, v110, v40
	v_dual_fmac_f32 v79, v110, v48 :: v_dual_fmac_f32 v88, v100, v58
	ds_load_b128 v[107:110], v85 offset:5136
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v87, v103, v57
	v_fmac_f32_e32 v79, v103, v59
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v88, v101, v55 :: v_dual_fmac_f32 v87, v104, v58
	v_fmac_f32_e32 v79, v104, v60
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v80, v100, v60 :: v_dual_fmac_f32 v87, v105, v55
	v_fmac_f32_e32 v79, v105, v69
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v80, v101, v69 :: v_dual_fmac_f32 v87, v106, v56
	v_fmac_f32_e32 v79, v106, v70
	v_fmac_f32_e32 v88, v102, v56
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v80, v102, v70
	ds_load_b128 v[99:102], v85 offset:4128
	v_fmac_f32_e32 v87, v0, v65
	v_fmac_f32_e32 v79, v0, v67
	ds_load_b128 v[103:106], v85 offset:5168
	v_fmac_f32_e32 v87, v1, v66
	v_fmac_f32_e32 v79, v1, v68
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v87, v2, v61
	v_fmac_f32_e32 v79, v2, v63
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v87, v3, v62
	v_fmac_f32_e32 v78, v111, v11
	v_fmac_f32_e32 v79, v3, v64
	v_fmac_f32_e32 v86, v111, v13
	ds_load_b128 v[0:3], v85 offset:6160
	v_fmac_f32_e32 v78, v112, v12
	v_fmac_f32_e32 v86, v112, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v113, v7
	v_fmac_f32_e32 v86, v113, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v114, v8
	v_fmac_f32_e32 v86, v114, v10
	ds_load_b128 v[111:114], v85 offset:4144
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v78, v99, v31
	v_fmac_f32_e32 v86, v99, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v100, v32
	v_fmac_f32_e32 v86, v100, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v101, v37
	v_fmac_f32_e32 v86, v101, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v102, v38
	v_fmac_f32_e32 v86, v102, v28
	ds_load_b128 v[99:102], v85 offset:4160
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v78, v111, v35
	v_fmac_f32_e32 v86, v111, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v112, v36
	v_fmac_f32_e32 v86, v112, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v113, v33
	v_fmac_f32_e32 v86, v113, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v114, v34
	v_fmac_f32_e32 v86, v114, v24
	ds_load_b128 v[111:114], v85 offset:4176
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v78, v99, v49
	v_fmac_f32_e32 v86, v99, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v100, v50
	v_fmac_f32_e32 v86, v100, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v101, v53
	v_fmac_f32_e32 v86, v101, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v102, v54
	v_fmac_f32_e32 v86, v102, v46
	ds_load_b128 v[99:102], v85 offset:4192
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v78, v111, v51
	v_fmac_f32_e32 v86, v111, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v112, v52
	v_fmac_f32_e32 v86, v112, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v113, v47
	v_fmac_f32_e32 v86, v113, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v114, v48
	v_fmac_f32_e32 v86, v114, v40
	ds_load_b128 v[111:114], v85 offset:4208
	v_fmac_f32_e32 v74, v119, v17
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v78, v99, v59
	v_fmac_f32_e32 v86, v99, v57
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v100, v60
	v_fmac_f32_e32 v86, v100, v58
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v101, v69
	v_fmac_f32_e32 v86, v101, v55
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v78, v102, v70
	v_fmac_f32_e32 v86, v102, v56
	ds_load_b128 v[99:102], v85 offset:6144
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v77, v99, v19
	v_fmac_f32_e32 v88, v115, v65
	v_fmac_f32_e32 v75, v99, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v80, v115, v67 :: v_dual_fmac_f32 v77, v100, v20
	v_fmac_f32_e32 v88, v116, v66
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v75, v100, v18
	v_dual_fmac_f32 v80, v116, v68 :: v_dual_fmac_f32 v77, v101, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v88, v117, v61
	v_fmac_f32_e32 v75, v101, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v80, v117, v63 :: v_dual_fmac_f32 v77, v102, v22
	v_fmac_f32_e32 v88, v118, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v75, v102, v16
	ds_load_b128 v[99:102], v85 offset:7200
	v_fmac_f32_e32 v74, v120, v18
	v_fmac_f32_e32 v77, v0, v13
	v_fmac_f32_e32 v75, v0, v11
	v_fmac_f32_e32 v74, v121, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v77, v1, v14
	v_fmac_f32_e32 v75, v1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v77, v2, v9
	v_fmac_f32_e32 v80, v118, v64
	v_fmac_f32_e32 v75, v2, v7
	ds_load_b128 v[115:118], v85 offset:5152
	v_fmac_f32_e32 v77, v3, v10
	v_fmac_f32_e32 v84, v119, v19
	v_fmac_f32_e32 v75, v3, v8
	ds_load_b128 v[0:3], v85 offset:6192
	v_fmac_f32_e32 v74, v122, v16
	v_fmac_f32_e32 v84, v120, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v107, v11
	v_fmac_f32_e32 v84, v121, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v108, v12
	v_fmac_f32_e32 v84, v122, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v109, v7
	v_fmac_f32_e32 v84, v107, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v110, v8
	v_fmac_f32_e32 v84, v108, v14
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v115, v31
	v_fmac_f32_e32 v84, v109, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v116, v32
	v_fmac_f32_e32 v84, v110, v10
	ds_load_b128 v[107:110], v85 offset:5184
	v_fmac_f32_e32 v74, v117, v37
	v_fmac_f32_e32 v84, v115, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v118, v38
	v_fmac_f32_e32 v84, v116, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v103, v35
	v_fmac_f32_e32 v84, v117, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v104, v36
	v_fmac_f32_e32 v84, v118, v28
	ds_load_b128 v[115:118], v85 offset:7168
	v_fmac_f32_e32 v74, v105, v33
	v_fmac_f32_e32 v84, v103, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v106, v34
	v_fmac_f32_e32 v84, v104, v26
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v107, v49
	v_fmac_f32_e32 v84, v105, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v108, v50
	v_fmac_f32_e32 v84, v106, v24
	ds_load_b128 v[103:106], v85 offset:5200
	v_fmac_f32_e32 v74, v109, v53
	v_fmac_f32_e32 v84, v107, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v74, v110, v54
	v_fmac_f32_e32 v84, v108, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v84, v109, v45
	v_fmac_f32_e32 v84, v110, v46
	ds_load_b128 v[107:110], v85 offset:7184
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v76, v115, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v73, v115, v17 :: v_dual_fmac_f32 v76, v116, v20
	v_fmac_f32_e32 v73, v116, v18
	ds_load_b128 v[17:20], v85 offset:6176
	v_fmac_f32_e32 v76, v117, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v73, v117, v15 :: v_dual_fmac_f32 v76, v118, v22
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v73, v118, v16 :: v_dual_fmac_f32 v76, v107, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v73, v107, v11 :: v_dual_fmac_f32 v76, v108, v14
	ds_load_b128 v[13:16], v85 offset:5216
	v_fmac_f32_e32 v84, v103, v41
	v_dual_fmac_f32 v74, v103, v51 :: v_dual_fmac_f32 v73, v108, v12
	v_fmac_f32_e32 v76, v109, v9
	v_fmac_f32_e32 v84, v104, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v74, v104, v52 :: v_dual_fmac_f32 v73, v109, v7
	v_fmac_f32_e32 v76, v110, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v84, v105, v39
	v_dual_fmac_f32 v74, v105, v47 :: v_dual_fmac_f32 v73, v110, v8
	ds_load_b128 v[7:10], v85 offset:7216
	v_fmac_f32_e32 v84, v106, v40
	v_fmac_f32_e32 v74, v106, v48
	ds_load_b128 v[103:106], v85 offset:5232
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v77, v17, v29
	v_fmac_f32_e32 v75, v17, v31
	s_waitcnt lgkmcnt(2)
	v_fmac_f32_e32 v84, v13, v57
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v74, v13, v59 :: v_dual_fmac_f32 v77, v18, v30
	v_fmac_f32_e32 v75, v18, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v84, v14, v58
	v_fmac_f32_e32 v74, v14, v60
	ds_load_b128 v[11:14], v85 offset:6240
	v_fmac_f32_e32 v77, v19, v27
	v_fmac_f32_e32 v75, v19, v37
	v_fmac_f32_e32 v84, v15, v55
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v74, v15, v69 :: v_dual_fmac_f32 v77, v20, v28
	v_fmac_f32_e32 v75, v20, v38
	ds_load_b128 v[17:20], v85 offset:6208
	v_fmac_f32_e32 v84, v16, v56
	v_fmac_f32_e32 v74, v16, v70
	v_fmac_f32_e32 v77, v0, v25
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v75, v0, v35 :: v_dual_fmac_f32 v84, v103, v65
	v_dual_fmac_f32 v74, v103, v67 :: v_dual_fmac_f32 v77, v1, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v75, v1, v36 :: v_dual_fmac_f32 v84, v104, v66
	v_dual_fmac_f32 v74, v104, v68 :: v_dual_fmac_f32 v77, v2, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v75, v2, v33
	v_fmac_f32_e32 v84, v105, v61
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v74, v105, v63 :: v_dual_fmac_f32 v77, v3, v24
	v_fmac_f32_e32 v75, v3, v34
	ds_load_b128 v[0:3], v85 offset:6224
	v_fmac_f32_e32 v84, v106, v62
	s_waitcnt lgkmcnt(1)
	v_dual_fmac_f32 v74, v106, v64 :: v_dual_fmac_f32 v77, v17, v43
	v_fmac_f32_e32 v75, v17, v49
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v77, v18, v44
	v_fmac_f32_e32 v75, v18, v50
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v77, v19, v45
	v_fmac_f32_e32 v75, v19, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v77, v20, v46
	v_fmac_f32_e32 v75, v20, v54
	ds_load_b128 v[17:20], v85 offset:7264
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v77, v0, v41
	v_fmac_f32_e32 v75, v0, v51
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v77, v1, v42
	v_fmac_f32_e32 v75, v1, v52
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v77, v2, v39
	v_fmac_f32_e32 v75, v2, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v77, v3, v40
	v_fmac_f32_e32 v75, v3, v48
	ds_load_b128 v[0:3], v85 offset:6256
	v_fmac_f32_e32 v73, v99, v31
	v_fmac_f32_e32 v76, v99, v29
	v_fmac_f32_e32 v77, v11, v57
	v_fmac_f32_e32 v75, v11, v59
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, v100, v32
	v_fmac_f32_e32 v76, v100, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v77, v12, v58
	v_fmac_f32_e32 v75, v12, v60
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, v101, v37
	v_fmac_f32_e32 v76, v101, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v77, v13, v55
	v_fmac_f32_e32 v75, v13, v69
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, v102, v38
	v_fmac_f32_e32 v76, v102, v28
	ds_load_b128 v[27:30], v85 offset:7232
	v_fmac_f32_e32 v75, v14, v70
	v_fmac_f32_e32 v77, v14, v56
	v_fmac_f32_e32 v73, v7, v35
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v76, v7, v25 :: v_dual_fmac_f32 v75, v0, v67
	v_fmac_f32_e32 v77, v0, v65
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v73, v8, v36
	v_dual_fmac_f32 v76, v8, v26 :: v_dual_fmac_f32 v75, v1, v68
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v77, v1, v66
	v_fmac_f32_e32 v73, v9, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v76, v9, v23
	v_fmac_f32_e32 v75, v2, v63
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v77, v2, v61
	v_fmac_f32_e32 v73, v10, v34
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v76, v10, v24
	ds_load_b128 v[7:10], v85 offset:7248
	v_fmac_f32_e32 v75, v3, v64
	v_fmac_f32_e32 v77, v3, v62
	s_waitcnt lgkmcnt(1)
	v_fmac_f32_e32 v73, v27, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v76, v27, v43 :: v_dual_fmac_f32 v73, v28, v50
	v_dual_fmac_f32 v76, v28, v44 :: v_dual_fmac_f32 v73, v29, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v76, v29, v45 :: v_dual_fmac_f32 v73, v30, v54
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v76, v30, v46 :: v_dual_fmac_f32 v73, v7, v51
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v76, v7, v41 :: v_dual_fmac_f32 v73, v8, v52
	v_dual_fmac_f32 v76, v8, v42 :: v_dual_fmac_f32 v73, v9, v47
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v76, v9, v39 :: v_dual_fmac_f32 v73, v10, v48
	v_fmac_f32_e32 v76, v10, v40
	ds_load_b128 v[7:10], v85 offset:7280
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_fmac_f32_e32 v73, v17, v59
	v_fmac_f32_e32 v76, v17, v57
	buffer_gl0_inv
	v_fmac_f32_e32 v73, v18, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v76, v18, v58 :: v_dual_fmac_f32 v73, v19, v69
	v_dual_fmac_f32 v76, v19, v55 :: v_dual_fmac_f32 v73, v20, v70
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v76, v20, v56 :: v_dual_fmac_f32 v73, v7, v67
	v_fmac_f32_e32 v86, v111, v65
	v_dual_fmac_f32 v76, v7, v65 :: v_dual_fmac_f32 v73, v8, v68
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v86, v112, v66
	v_dual_fmac_f32 v76, v8, v66 :: v_dual_fmac_f32 v73, v9, v63
	v_fmac_f32_e32 v78, v111, v67
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v86, v113, v61
	v_dual_fmac_f32 v76, v9, v61 :: v_dual_fmac_f32 v73, v10, v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v78, v112, v68
	v_fmac_f32_e32 v86, v114, v62
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v76, v10, v62
	v_fmac_f32_e32 v78, v113, v63
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v78, v114, v64
	s_cbranch_scc0 .LBB7_6
.LBB7_24:                               ; %._crit_edge
                                        ;   in Loop: Header=BB7_4 Depth=1
	v_add_co_u32 v95, vcc_lo, v95, s6
	v_add_co_ci_u32_e32 v96, vcc_lo, s7, v96, vcc_lo
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s10, s30
	s_cbranch_scc0 .LBB7_4
.LBB7_25:                               ; %._crit_edge266
	v_add_nc_u32_e32 v0, s28, v72
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s24, v0
	s_cbranch_execz .LBB7_27
; %bb.26:                               ; %.preheader239
	s_mul_i32 s11, s11, s33
	s_mul_i32 s0, s24, s17
	s_add_i32 s34, s34, s11
	s_ashr_i32 s1, s0, 31
	v_mad_u64_u32 v[1:2], null, s34, s24, v[0:1]
	s_lshl_b32 s2, s0, 1
	s_lshl_b64 s[10:11], s[0:1], 2
	s_ashr_i32 s3, s2, 31
	s_mul_i32 s6, s0, 3
	s_lshl_b64 s[2:3], s[2:3], 2
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v0, v1, s17
	v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v2, s31, v91
	s_lshl_b32 s8, s0, 2
	v_dual_mul_f32 v8, s31, v90 :: v_dual_mul_f32 v13, s31, v87
	s_ashr_i32 s9, s8, 31
	v_dual_mul_f32 v12, s31, v88 :: v_dual_mul_f32 v19, s31, v82
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v0, s29, v71, v0
	v_dual_mul_f32 v14, s31, v86 :: v_dual_mul_f32 v15, s31, v84
	v_dual_mul_f32 v16, s31, v77 :: v_dual_mul_f32 v17, s31, v76
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_mul_f32_e32 v18, s31, v83
	v_mul_f32_e32 v20, s31, v80
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_lshl_b64 s[4:5], s[6:7], 2
	global_store_b32 v[0:1], v2, off
	v_add_co_u32 v2, vcc_lo, v0, s10
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, v0, s4
	s_lshl_b64 s[2:3], s[8:9], 2
	s_mul_i32 s4, s0, 5
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[2:3], v8, off
	v_add_co_u32 v8, vcc_lo, v0, s2
	s_ashr_i32 s5, s4, 31
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v1, vcc_lo
	s_lshl_b64 s[2:3], s[4:5], 2
	s_clause 0x2
	global_store_b32 v[4:5], v12, off
	global_store_b32 v[6:7], v13, off
	global_store_b32 v[8:9], v14, off
	v_add_co_u32 v10, vcc_lo, v0, s2
	s_mul_i32 s2, s0, 6
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v1, vcc_lo
	s_ashr_i32 s3, s2, 31
	s_mul_i32 s0, s0, 7
	s_lshl_b64 s[2:3], s[2:3], 2
	s_ashr_i32 s1, s0, 31
	v_add_co_u32 v12, vcc_lo, v0, s2
	s_lshl_b64 s[0:1], s[0:1], 2
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v14, vcc_lo, v0, s0
	global_store_b32 v[10:11], v15, off
	v_add_co_ci_u32_e32 v15, vcc_lo, s1, v1, vcc_lo
	s_clause 0x4
	global_store_b32 v[12:13], v16, off
	global_store_b32 v[14:15], v17, off
	global_store_b32 v[0:1], v18, off offset:64
	global_store_b32 v[2:3], v19, off offset:64
	global_store_b32 v[4:5], v20, off offset:64
	v_mul_f32_e32 v3, s31, v75
	v_dual_mul_f32 v0, s31, v79 :: v_dual_mul_f32 v1, s31, v78
	v_mul_f32_e32 v2, s31, v74
	v_mul_f32_e32 v4, s31, v73
	s_clause 0x4
	global_store_b32 v[6:7], v0, off offset:64
	global_store_b32 v[8:9], v1, off offset:64
	global_store_b32 v[10:11], v2, off offset:64
	global_store_b32 v[12:13], v3, off offset:64
	global_store_b32 v[14:15], v4, off offset:64
.LBB7_27:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
		.amdhsa_group_segment_fixed_size 12448
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 88
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 123
		.amdhsa_next_free_sgpr 53
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif, .Lfunc_end7-_Z18kConvolve_weight_cPfS_S_iiiiiiiiiiiiiiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7412
; NumSgprs: 55
; NumVgprs: 123
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 12448 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 15
; NumSGPRsForWavesPerEU: 55
; NumVGPRsForWavesPerEU: 123
; Occupancy: 10
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii ; -- Begin function _Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.globl	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
	.p2align	8
	.type	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii,@function
_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii: ; @_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
; %bb.0:                                ; %.critedge
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x18
	s_load_b128 s[20:23], s[0:1], 0x38
	s_mov_b32 s2, s15
	s_mov_b32 s25, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s20, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s12, s3, 31
	s_add_i32 s13, s3, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s15, s13, s12
	s_ashr_i32 s13, s2, 31
	v_cvt_f32_u32_e32 v1, s15
	s_sub_i32 s16, 0, s15
	s_add_i32 s18, s2, s13
	s_xor_b32 s12, s13, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s17, v1
	s_mul_i32 s16, s16, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s19, s17, s16
	s_xor_b32 s16, s18, s13
	s_add_i32 s17, s17, s19
	s_mul_hi_u32 s17, s16, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s18, s17, s15
	s_add_i32 s19, s17, 1
	s_sub_i32 s18, s16, s18
	s_sub_i32 s24, s18, s15
	s_cmp_ge_u32 s18, s15
	s_cselect_b32 s17, s19, s17
	s_cselect_b32 s18, s24, s18
	s_add_i32 s19, s17, 1
	s_cmp_ge_u32 s18, s15
	s_mov_b32 s24, 0
	s_cselect_b32 s15, s19, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s15, s15, s12
	s_sub_i32 s15, s15, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s12, s15, s21
	s_cmp_lt_i32 s12, s9
	s_cbranch_scc1 .LBB8_2
; %bb.1:
	s_ashr_i32 s17, s22, 31
	s_sub_i32 s25, s12, s9
	s_add_i32 s18, s22, s17
	s_ashr_i32 s27, s25, 31
	s_xor_b32 s18, s18, s17
	s_add_i32 s25, s25, s27
	v_cvt_f32_u32_e32 v1, s18
	s_sub_i32 s26, 0, s18
	s_xor_b32 s25, s25, s27
	s_xor_b32 s17, s27, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s19, v1
	s_mul_i32 s26, s26, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s26, s19, s26
	s_add_i32 s19, s19, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s19, s25, s19
	s_mul_i32 s26, s19, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s25, s25, s26
	s_add_i32 s26, s19, 1
	s_sub_i32 s27, s25, s18
	s_cmp_ge_u32 s25, s18
	s_cselect_b32 s19, s26, s19
	s_cselect_b32 s25, s27, s25
	s_add_i32 s26, s19, 1
	s_cmp_ge_u32 s25, s18
	s_cselect_b32 s18, s26, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s18, s18, s17
	s_sub_i32 s17, s18, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s25, s17, 1
.LBB8_2:
	s_ashr_i32 s17, s20, 31
	s_load_b32 s29, s[0:1], 0x48
	s_add_i32 s18, s20, s17
	s_xor_b32 s13, s13, s17
	s_xor_b32 s18, s18, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s18
	s_sub_i32 s26, 0, s18
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s19, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s26, s26, s19
	s_mul_hi_u32 s26, s19, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s19, s19, s26
	s_mul_hi_u32 s19, s16, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s26, s19, s18
	s_add_i32 s17, s19, 1
	s_sub_i32 s16, s16, s26
	s_sub_i32 s26, s16, s18
	s_cmp_ge_u32 s16, s18
	s_cselect_b32 s17, s17, s19
	s_cselect_b32 s16, s26, s16
	s_add_i32 s19, s17, 1
	s_cmp_ge_u32 s16, s18
	s_cselect_b32 s16, s19, s17
	s_ashr_i32 s17, s11, 31
	s_xor_b32 s16, s16, s13
	s_add_i32 s11, s11, s17
	s_sub_i32 s39, s16, s13
	s_xor_b32 s11, s11, s17
	s_ashr_i32 s37, s39, 31
	v_cvt_f32_u32_e32 v1, s11
	s_sub_i32 s13, 0, s11
	s_add_i32 s16, s39, s37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s16, s16, s37
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s13, s13, s17
	s_mul_hi_u32 s13, s17, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s17, s17, s13
	s_mul_hi_u32 s13, s16, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s13, s13, s11
	s_sub_i32 s13, s16, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s16, s13, s11
	s_cmp_ge_u32 s13, s11
	s_cselect_b32 s13, s16, s13
	s_sub_i32 s16, s13, s11
	s_cmp_ge_u32 s13, s11
	s_cselect_b32 s11, s16, s13
	s_ashr_i32 s30, s22, 31
	s_xor_b32 s38, s11, s37
	s_add_i32 s13, s22, s30
	s_sub_i32 s11, s38, s37
	s_xor_b32 s28, s13, s30
	s_sub_i32 s33, s11, s21
	v_cvt_f32_u32_e32 v1, s28
	s_sub_i32 s13, 0, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s31, v1
	s_mul_i32 s13, s13, s31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s13, s31, s13
	s_add_i32 s31, s31, s13
	s_cmp_lt_i32 s33, s9
	s_cbranch_scc1 .LBB8_4
; %bb.3:
	s_sub_i32 s11, s33, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s13, s11, 31
	s_add_i32 s11, s11, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s11, s11, s13
	s_xor_b32 s13, s13, s30
	s_mul_hi_u32 s16, s11, s31
	s_mul_i32 s17, s16, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s11, s11, s17
	s_add_i32 s17, s16, 1
	s_sub_i32 s18, s11, s28
	s_cmp_ge_u32 s11, s28
	s_cselect_b32 s16, s17, s16
	s_cselect_b32 s11, s18, s11
	s_add_i32 s17, s16, 1
	s_cmp_ge_u32 s11, s28
	s_cselect_b32 s11, s17, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s11, s11, s13
	s_sub_i32 s11, s11, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s24, s11, 1
.LBB8_4:
	s_mul_i32 s39, s39, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s11, s2, s39
	s_sub_i32 s27, s11, s21
	s_mov_b32 s11, 0
	s_cmp_lt_i32 s27, s9
	s_cbranch_scc1 .LBB8_6
; %bb.5:
	s_sub_i32 s11, s27, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s13, s11, 31
	s_add_i32 s11, s11, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s11, s11, s13
	s_xor_b32 s13, s13, s30
	s_mul_hi_u32 s16, s11, s31
	s_mul_i32 s17, s16, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s11, s11, s17
	s_add_i32 s17, s16, 1
	s_sub_i32 s18, s11, s28
	s_cmp_ge_u32 s11, s28
	s_cselect_b32 s16, s17, s16
	s_cselect_b32 s11, s18, s11
	s_add_i32 s17, s16, 1
	s_cmp_ge_u32 s11, s28
	s_cselect_b32 s11, s17, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s11, s11, s13
	s_sub_i32 s11, s11, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s11, s11, 1
.LBB8_6:
	s_ashr_i32 s13, s12, 31
	v_mov_b32_e32 v4, 0
	s_add_i32 s12, s12, s13
	v_mov_b32_e32 v2, 0
	s_xor_b32 s12, s12, s13
	s_xor_b32 s13, s13, s30
	s_mul_hi_u32 s16, s12, s31
	v_mov_b32_e32 v8, 0
	s_mul_i32 s17, s16, s28
	v_mov_b32_e32 v3, 0
	s_sub_i32 s12, s12, s17
	s_add_i32 s17, s16, 1
	s_sub_i32 s18, s12, s28
	s_cmp_ge_u32 s12, s28
	s_cselect_b32 s16, s17, s16
	s_cselect_b32 s12, s18, s12
	s_add_i32 s17, s16, 1
	s_cmp_ge_u32 s12, s28
	s_cselect_b32 s12, s17, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s12, s12, s13
	s_sub_i32 s12, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_add_i32 s13, s12, 1
	s_cmp_lt_i32 s12, s4
	s_cselect_b32 s20, s13, s4
	s_add_i32 s12, s7, 31
	s_ashr_i32 s13, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s13, s13, 27
	s_add_i32 s12, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s26, s12, 5
	v_cvt_f32_u32_e32 v1, s26
	s_sub_i32 s13, 0, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s12, v1
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mul_i32 s13, s13, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s13, s12, s13
	s_add_i32 s12, s12, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_hi_u32 s34, s14, s12
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	s_mul_i32 s0, s34, s26
	s_add_i32 s1, s34, 1
	s_sub_i32 s0, s14, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s35, s0, s26
	s_cmp_ge_u32 s0, s26
	s_cselect_b32 s1, s1, s34
	s_cselect_b32 s0, s35, s0
	s_add_i32 s34, s1, 1
	s_cmp_ge_u32 s0, s26
	s_cselect_b32 s0, s34, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s26
	s_sub_i32 s1, s14, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s26, s1, 5
	s_lshl_b32 s1, s0, 4
	s_cmp_ge_i32 s25, s20
	s_cbranch_scc1 .LBB8_20
; %bb.7:                                ; %.lr.ph278
	s_ashr_i32 s0, s27, 31
	s_mul_i32 s46, s25, s5
	s_add_i32 s27, s27, s0
	v_lshl_add_u32 v8, v1, 5, v0
	s_xor_b32 s14, s27, s0
	s_xor_b32 s0, s0, s30
	s_mul_hi_u32 s27, s14, s31
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v12, 15, v0
	s_mul_i32 s34, s27, s28
	v_lshrrev_b32_e32 v11, 4, v8
	s_sub_i32 s14, s14, s34
	s_add_i32 s34, s27, 1
	s_sub_i32 s35, s14, s28
	s_cmp_ge_u32 s14, s28
	v_lshlrev_b32_e32 v14, 2, v12
	s_cselect_b32 s27, s34, s27
	s_cselect_b32 s14, s35, s14
	s_add_i32 s34, s27, 1
	s_cmp_ge_u32 s14, s28
	v_mul_u32_u24_e32 v15, 0x44, v11
	s_cselect_b32 s14, s34, s27
	v_lshlrev_b32_e32 v5, 2, v0
	s_xor_b32 s14, s14, s0
	v_lshrrev_b32_e32 v13, 5, v8
	s_sub_i32 s0, s14, s0
	s_mul_i32 s43, s25, s22
	s_add_i32 s14, s0, 1
	s_cmp_lt_i32 s0, s6
	s_mul_i32 s44, s24, s22
	s_cselect_b32 s27, s14, s6
	s_ashr_i32 s0, s33, 31
	s_mul_i32 s45, s11, s22
	s_add_i32 s33, s33, s0
	s_mul_i32 s22, s22, s8
	s_xor_b32 s14, s33, s0
	s_xor_b32 s0, s0, s30
	s_mul_hi_u32 s31, s14, s31
	v_and_b32_e32 v9, 31, v0
	s_mul_i32 s33, s31, s28
	s_add_i32 s30, s31, 1
	s_sub_i32 s14, s14, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s33, s14, s28
	s_cmp_ge_u32 s14, s28
	v_or_b32_e32 v8, s26, v9
	s_cselect_b32 s30, s30, s31
	s_cselect_b32 s14, s33, s14
	s_add_i32 s31, s30, 1
	s_cmp_ge_u32 s14, s28
	s_cselect_b32 s14, s31, s30
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s14, s14, s0
	s_sub_i32 s0, s14, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s14, s0, 1
	s_cmp_lt_i32 s0, s5
	s_cselect_b32 s28, s14, s5
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s14, s29, 31
	s_ashr_i32 s30, s23, 31
	s_add_i32 s29, s29, s14
	s_add_i32 s23, s23, s30
	s_xor_b32 s0, s29, s14
	s_xor_b32 s23, s23, s30
	v_cvt_f32_u32_e32 v2, s0
	s_sub_i32 s29, 0, s0
	s_xor_b32 s30, s30, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s33, v2
	s_mul_i32 s29, s29, s33
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s29, s33, s29
	s_add_i32 s33, s33, s29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s29, s23, s33
	s_mul_i32 s31, s29, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s23, s23, s31
	s_add_i32 s31, s29, 1
	s_sub_i32 s34, s23, s0
	s_cmp_ge_u32 s23, s0
	s_cselect_b32 s29, s31, s29
	s_cselect_b32 s23, s34, s23
	s_add_i32 s31, s29, 1
	s_cmp_ge_u32 s23, s0
	s_cselect_b32 s23, s31, s29
	s_mul_i32 s31, s6, s5
	s_xor_b32 s23, s23, s30
	s_mul_i32 s41, s31, s4
	s_sub_i32 s34, s23, s30
	s_mul_i32 s30, s9, s9
	s_ashr_i32 s35, s34, 31
	s_mul_i32 s40, s30, s9
	s_add_i32 s23, s34, s35
	s_mul_i32 s47, s40, s8
	s_xor_b32 s36, s23, s35
	s_mul_i32 s23, s7, s6
	v_cvt_f32_u32_e32 v2, s36
	s_mul_i32 s31, s23, s5
	s_sub_i32 s40, 0, s36
	s_mul_i32 s48, s31, s4
	s_mul_i32 s5, s41, s7
	v_rcp_iflag_f32_e32 v10, v2
	s_ashr_i32 s41, s1, 31
	v_mov_b32_e32 v2, 0
	s_add_i32 s42, s1, s41
	s_xor_b32 s35, s41, s35
	s_xor_b32 s42, s42, s41
	v_mov_b32_e32 v6, 0
	s_movk_i32 s29, 0x800
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v7, 0x44, v1, s29
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x4f7ffffe, v10
	s_mul_i32 s29, s22, s30
	s_mul_i32 s30, s22, s9
	v_cvt_u32_f32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s4, v10
	v_lshlrev_b32_e32 v10, 2, v9
	v_add_nc_u32_e32 v9, 0x400, v5
	s_mul_i32 s40, s40, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshl_or_b32 v10, v13, 7, v10
	s_mul_hi_u32 s40, s4, s40
	s_add_i32 s4, s4, s40
	s_mul_i32 s40, s5, 12
	s_mul_hi_u32 s4, s42, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s49, s4, s36
	s_sub_i32 s41, s42, s49
	s_add_i32 s42, s4, 1
	s_sub_i32 s49, s41, s36
	s_cmp_ge_u32 s41, s36
	s_cselect_b32 s4, s42, s4
	s_cselect_b32 s41, s49, s41
	s_add_i32 s42, s4, 1
	s_cmp_ge_u32 s41, s36
	s_cselect_b32 s4, s42, s4
	s_ashr_i32 s36, s8, 31
	s_xor_b32 s4, s4, s35
	s_add_i32 s41, s8, s36
	s_xor_b32 s14, s36, s14
	s_xor_b32 s36, s41, s36
	s_sub_i32 s4, s4, s35
	s_mul_hi_u32 s33, s36, s33
	s_mul_i32 s34, s4, s34
	s_mul_i32 s35, s33, s0
	s_sub_i32 s34, s1, s34
	s_sub_i32 s35, s36, s35
	s_add_i32 s36, s33, 1
	s_sub_i32 s41, s35, s0
	s_cmp_ge_u32 s35, s0
	v_add_nc_u32_e32 v16, s34, v11
	s_cselect_b32 s33, s36, s33
	s_cselect_b32 s34, s41, s35
	s_add_i32 s35, s33, 1
	s_cmp_ge_u32 s34, s0
	v_add3_u32 v11, v15, v14, 0x800
	s_cselect_b32 s33, s35, s33
	v_mul_lo_u32 v14, s47, v16
	s_xor_b32 s33, s33, s14
	v_cmp_le_i32_e64 s0, s7, v8
	s_sub_i32 s33, s33, s14
	s_cmp_lt_i32 s24, s28
	s_mul_i32 s4, s33, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v13, s4, v13
	s_cselect_b32 s34, -1, 0
	s_cmp_lt_i32 s11, s27
	v_add3_u32 v12, s4, v12, v14
	s_cselect_b32 s35, -1, 0
	v_mad_u64_u32 v[14:15], null, s5, v13, v[8:9]
	s_cmp_gt_i32 s33, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_ashrrev_i32_e32 v13, 31, v12
	s_cselect_b32 s36, -1, 0
	s_lshl_b32 s14, s47, 3
	s_add_i32 s47, s21, s43
	s_add_i32 s44, s21, s44
	s_sub_i32 s47, s15, s47
	v_ashrrev_i32_e32 v15, 31, v14
	s_mul_i32 s47, s9, s47
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_add_i32 s38, s38, s47
	s_add_i32 s46, s24, s46
	s_sub_i32 s37, s38, s37
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_sub_i32 s37, s37, s44
	v_add_co_u32 v12, vcc_lo, s12, v12
	s_mul_i32 s9, s9, s37
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
	s_add_i32 s9, s2, s9
	v_add_co_u32 v14, vcc_lo, s18, v14
	s_lshl_b32 s4, s5, 2
	s_lshl_b32 s42, s5, 3
	s_add_i32 s45, s21, s45
	s_mul_i32 s6, s6, s46
	s_sub_i32 s9, s9, s39
	v_add_co_ci_u32_e32 v15, vcc_lo, s19, v15, vcc_lo
	v_mov_b32_e32 v8, 0
	s_ashr_i32 s41, s40, 31
	s_ashr_i32 s5, s4, 31
	s_ashr_i32 s43, s42, 31
	s_ashr_i32 s15, s14, 31
	s_add_i32 s6, s11, s6
	s_sub_i32 s9, s9, s45
	s_lshl_b32 s21, s48, 4
	s_lshl_b64 s[4:5], s[4:5], 2
	s_mul_i32 s6, s7, s6
	s_mul_i32 s37, s8, s9
	s_lshl_b64 s[8:9], s[42:43], 2
	s_lshl_b64 s[12:13], s[40:41], 2
	s_lshl_b64 s[14:15], s[14:15], 2
.LBB8_8:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB8_9 Depth 2
                                        ;       Child Loop BB8_10 Depth 3
                                        ;         Child Loop BB8_12 Depth 4
	s_mov_b32 s38, s6
	s_and_not1_b32 vcc_lo, exec_lo, s34
	s_mov_b32 s39, s37
	s_mov_b32 s40, s24
	s_cbranch_vccnz .LBB8_19
.LBB8_9:                                ;   Parent Loop BB8_8 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB8_10 Depth 3
                                        ;         Child Loop BB8_12 Depth 4
	s_mov_b32 s41, s38
	s_and_not1_b32 vcc_lo, exec_lo, s35
	s_mov_b32 s42, s39
	s_mov_b32 s43, s11
	s_cbranch_vccnz .LBB8_18
.LBB8_10:                               ;   Parent Loop BB8_8 Depth=1
                                        ;     Parent Loop BB8_9 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB8_12 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s36
	s_cbranch_vccnz .LBB8_17
; %bb.11:                               ; %.critedge247.lr.ph
                                        ;   in Loop: Header=BB8_10 Depth=3
	s_mov_b32 s44, 0
	s_mov_b32 s18, s41
.LBB8_12:                               ; %.critedge247
                                        ;   Parent Loop BB8_8 Depth=1
                                        ;     Parent Loop BB8_9 Depth=2
                                        ;       Parent Loop BB8_10 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_and_saveexec_b32 s19, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s19, exec_lo, s19
	s_cbranch_execz .LBB8_14
; %bb.13:                               ; %.preheader260.preheader
                                        ;   in Loop: Header=BB8_12 Depth=4
	ds_store_2addr_stride64_b32 v10, v6, v6 offset1:2
	ds_store_2addr_stride64_b32 v10, v6, v6 offset0:4 offset1:6
.LBB8_14:                               ; %Flow
                                        ;   in Loop: Header=BB8_12 Depth=4
	s_and_not1_saveexec_b32 s45, s19
	s_cbranch_execz .LBB8_16
; %bb.15:                               ; %.preheader259.preheader
                                        ;   in Loop: Header=BB8_12 Depth=4
	s_ashr_i32 s19, s18, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[46:47], s[18:19], 2
	v_add_co_u32 v16, vcc_lo, v14, s46
	v_add_co_ci_u32_e32 v17, vcc_lo, s47, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, v16, s4
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v17, vcc_lo
	v_add_co_u32 v20, vcc_lo, v16, s8
	v_add_co_ci_u32_e32 v21, vcc_lo, s9, v17, vcc_lo
	v_add_co_u32 v22, vcc_lo, v16, s12
	v_add_co_ci_u32_e32 v23, vcc_lo, s13, v17, vcc_lo
	s_clause 0x3
	global_load_b32 v16, v[16:17], off
	global_load_b32 v17, v[18:19], off
	global_load_b32 v18, v[20:21], off
	global_load_b32 v19, v[22:23], off
	s_waitcnt vmcnt(2)
	ds_store_2addr_stride64_b32 v10, v16, v17 offset1:2
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v10, v18, v19 offset0:4 offset1:6
.LBB8_16:                               ; %.loopexit
                                        ;   in Loop: Header=BB8_12 Depth=4
	s_or_b32 exec_lo, exec_lo, s45
	s_add_i32 s46, s42, s44
	s_add_i32 s44, s44, 16
	s_ashr_i32 s47, s46, 31
	s_add_i32 s18, s18, s21
	s_lshl_b64 s[46:47], s[46:47], 2
	s_cmp_ge_i32 s44, s33
	v_add_co_u32 v16, vcc_lo, v12, s46
	v_add_co_ci_u32_e32 v17, vcc_lo, s47, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, v16, s14
	v_add_co_ci_u32_e32 v19, vcc_lo, s15, v17, vcc_lo
	s_clause 0x1
	global_load_b32 v16, v[16:17], off
	global_load_b32 v17, v[18:19], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v11, v16, v17 offset1:136
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[16:17], v5 offset1:32
	ds_load_2addr_b32 v[18:19], v7 offset1:1
	ds_load_2addr_b32 v[20:21], v5 offset0:64 offset1:96
	ds_load_2addr_b32 v[22:23], v7 offset0:68 offset1:69
	ds_load_2addr_b32 v[24:25], v7 offset0:136 offset1:137
	ds_load_2addr_b32 v[26:27], v7 offset0:204 offset1:205
	ds_load_2addr_b32 v[28:29], v5 offset0:128 offset1:160
	ds_load_2addr_b32 v[30:31], v7 offset0:2 offset1:3
	ds_load_2addr_b32 v[32:33], v7 offset0:4 offset1:5
	ds_load_2addr_b32 v[34:35], v7 offset0:6 offset1:7
	ds_load_2addr_b32 v[36:37], v5 offset0:192 offset1:224
	ds_load_2addr_b32 v[38:39], v9 offset1:32
	ds_load_2addr_b32 v[40:41], v9 offset0:64 offset1:96
	ds_load_2addr_b32 v[42:43], v7 offset0:70 offset1:71
	ds_load_2addr_b32 v[44:45], v7 offset0:72 offset1:73
	ds_load_2addr_b32 v[46:47], v7 offset0:74 offset1:75
	ds_load_2addr_b32 v[48:49], v7 offset0:206 offset1:207
	ds_load_2addr_b32 v[50:51], v7 offset0:138 offset1:139
	ds_load_2addr_b32 v[52:53], v7 offset0:140 offset1:141
	ds_load_2addr_b32 v[54:55], v7 offset0:142 offset1:143
	ds_load_2addr_b32 v[56:57], v7 offset0:208 offset1:209
	ds_load_2addr_b32 v[58:59], v7 offset0:210 offset1:211
	s_waitcnt lgkmcnt(17)
	v_fmac_f32_e32 v3, v24, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v8, v18, v16 :: v_dual_fmac_f32 v3, v25, v17
	v_fmac_f32_e32 v8, v19, v17
	ds_load_2addr_b32 v[18:19], v9 offset0:128 offset1:160
	s_waitcnt lgkmcnt(5)
	v_fmac_f32_e32 v3, v50, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v4, v22, v16 :: v_dual_fmac_f32 v3, v51, v21
	s_waitcnt lgkmcnt(4)
	v_dual_fmac_f32 v4, v23, v17 :: v_dual_fmac_f32 v3, v52, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v2, v26, v16 :: v_dual_fmac_f32 v3, v53, v29
	v_fmac_f32_e32 v2, v27, v17
	ds_load_2addr_b32 v[16:17], v7 offset0:8 offset1:9
	ds_load_2addr_b32 v[22:23], v7 offset0:10 offset1:11
	ds_load_2addr_b32 v[24:25], v7 offset0:12 offset1:13
	ds_load_2addr_b32 v[26:27], v7 offset0:14 offset1:15
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v3, v54, v36
	v_fmac_f32_e32 v8, v30, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v2, v48, v20 :: v_dual_fmac_f32 v3, v55, v37
	v_fmac_f32_e32 v4, v42, v20
	v_fmac_f32_e32 v8, v31, v21
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v2, v49, v21
	ds_load_2addr_b32 v[30:31], v7 offset0:76 offset1:77
	ds_load_2addr_b32 v[60:61], v7 offset0:78 offset1:79
	ds_load_2addr_b32 v[62:63], v7 offset0:80 offset1:81
	ds_load_2addr_b32 v[64:65], v7 offset0:82 offset1:83
	v_fmac_f32_e32 v4, v43, v21
	v_fmac_f32_e32 v8, v32, v28
	ds_load_2addr_b32 v[20:21], v7 offset0:212 offset1:213
	s_waitcnt lgkmcnt(11)
	v_fmac_f32_e32 v2, v56, v28
	v_fmac_f32_e32 v4, v44, v28
	v_fmac_f32_e32 v8, v33, v29
	ds_load_2addr_b32 v[32:33], v7 offset0:144 offset1:145
	v_fmac_f32_e32 v2, v57, v29
	v_fmac_f32_e32 v4, v45, v29
	ds_load_2addr_b32 v[28:29], v7 offset0:146 offset1:147
	ds_load_2addr_b32 v[42:43], v7 offset0:148 offset1:149
	ds_load_2addr_b32 v[44:45], v7 offset0:150 offset1:151
	v_fmac_f32_e32 v8, v34, v36
	s_waitcnt lgkmcnt(14)
	v_fmac_f32_e32 v2, v58, v36
	ds_load_2addr_b32 v[48:49], v7 offset0:214 offset1:215
	v_fmac_f32_e32 v4, v46, v36
	v_fmac_f32_e32 v8, v35, v37
	v_fmac_f32_e32 v2, v59, v37
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v4, v47, v37
	ds_load_2addr_b32 v[34:35], v7 offset0:216 offset1:217
	ds_load_2addr_b32 v[36:37], v7 offset0:218 offset1:219
	s_waitcnt lgkmcnt(15)
	v_fmac_f32_e32 v8, v16, v38
	s_waitcnt lgkmcnt(7)
	v_fmac_f32_e32 v2, v20, v38
	v_fmac_f32_e32 v4, v30, v38
	s_waitcnt lgkmcnt(6)
	v_dual_fmac_f32 v3, v32, v38 :: v_dual_fmac_f32 v8, v17, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v2, v21, v39
	v_fmac_f32_e32 v4, v31, v39
	ds_load_2addr_b32 v[16:17], v9 offset0:192 offset1:224
	v_dual_fmac_f32 v3, v33, v39 :: v_dual_fmac_f32 v8, v22, v40
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v2, v48, v40
	v_fmac_f32_e32 v4, v60, v40
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v3, v28, v40 :: v_dual_fmac_f32 v8, v23, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v2, v49, v41
	v_fmac_f32_e32 v4, v61, v41
	s_barrier
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v3, v29, v41 :: v_dual_fmac_f32 v8, v24, v18
	v_fmac_f32_e32 v2, v34, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v4, v62, v18
	buffer_gl0_inv
	v_dual_fmac_f32 v3, v42, v18 :: v_dual_fmac_f32 v8, v25, v19
	v_fmac_f32_e32 v2, v35, v19
	v_fmac_f32_e32 v4, v63, v19
	v_dual_fmac_f32 v3, v43, v19 :: v_dual_fmac_f32 v8, v26, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v2, v36, v16
	v_fmac_f32_e32 v4, v64, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v3, v44, v16 :: v_dual_fmac_f32 v8, v27, v17
	v_fmac_f32_e32 v2, v37, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v4, v65, v17
	v_fmac_f32_e32 v3, v45, v17
	s_cbranch_scc0 .LBB8_12
.LBB8_17:                               ; %._crit_edge
                                        ;   in Loop: Header=BB8_10 Depth=3
	s_add_i32 s43, s43, 1
	s_sub_i32 s42, s42, s22
	s_add_i32 s41, s41, s7
	s_cmp_ge_i32 s43, s27
	s_cbranch_scc0 .LBB8_10
.LBB8_18:                               ; %._crit_edge271
                                        ;   in Loop: Header=BB8_9 Depth=2
	s_add_i32 s40, s40, 1
	s_sub_i32 s39, s39, s30
	s_add_i32 s38, s38, s23
	s_cmp_ge_i32 s40, s28
	s_cbranch_scc0 .LBB8_9
.LBB8_19:                               ; %._crit_edge275
                                        ;   in Loop: Header=BB8_8 Depth=1
	s_add_i32 s25, s25, 1
	s_sub_i32 s37, s37, s29
	s_add_i32 s6, s6, s31
	s_cmp_ge_i32 s25, s20
	s_cbranch_scc0 .LBB8_8
.LBB8_20:                               ; %._crit_edge279
	v_add_nc_u32_e32 v0, s26, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v0
	s_cbranch_execz .LBB8_22
; %bb.21:                               ; %.preheader
	v_add_nc_u32_e32 v1, s1, v1
	s_mul_i32 s3, s3, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s7, s3
	s_lshl_b32 s0, s1, 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, s3, s[2:3]
	s_lshl_b32 s2, s1, 3
	s_mul_i32 s4, s1, 12
	s_ashr_i32 s1, s0, 31
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[6:7], null, v5, s7, v[0:1]
	v_mov_b32_e32 v7, 0
	s_ashr_i32 s5, s4, 31
	s_lshl_b64 s[4:5], s[4:5], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s16, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v5, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v11, vcc_lo, v0, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v1, vcc_lo
	s_clause 0x3
	global_store_b32 v[0:1], v8, off
	global_store_b32 v[5:6], v4, off
	global_store_b32 v[9:10], v3, off
	global_store_b32 v[11:12], v2, off
.LBB8_22:                               ; %.critedge251
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
		.amdhsa_group_segment_fixed_size 3136
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 76
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 66
		.amdhsa_next_free_sgpr 50
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii, .Lfunc_end8-_Z20kConvolve_backward_cPfPKfS1_iiiiiiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3504
; NumSgprs: 52
; NumVgprs: 66
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3136 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 52
; NumVGPRsForWavesPerEU: 66
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18kSampleMultinomialPiPfS0_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18kSampleMultinomialPiPfS0_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4kExpPfS_j
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4kExpPfS_j.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7kDividePfS_S_j
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7kDividePfS_S_j.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 768
    .kernarg_segment_align: 8
    .kernarg_segment_size: 72
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17kConvolve_forwardPfS_S_iiiiiiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z17kConvolve_forwardPfS_S_iiiiiiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
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