#include "includes.h"
__device__ double min2(double a, double b)
{
if (b < a) return b;
return a;
}
__device__ double max2(double a, double b)
{
if (b > a) return b;
return a;
}
__global__ void ConditionCFLKernel2D1 (double *Rsup, double *Rinf, double *Rmed, int nsec, int nrad, double *Vresidual, double *Vtheta, double *Vmoy, int FastTransport, double *SoundSpeed, double *Vrad, double *DT2D)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;

double dxrad, dxtheta, invdt1, invdt2, invdt3, invdt4, dvr, dvt, dt;

if (i > 0 && i<nrad && j<nsec){
dxrad = Rsup[i]-Rinf[i];
dxtheta = Rmed[i]*2.0*PI/(double)nsec;
if (FastTransport) Vresidual[i*nsec + j] = Vtheta[i*nsec + j]-Vmoy[i]; /* Fargo algorithm */
else Vresidual[i*nsec + j] = Vtheta[i*nsec + j];                       /* Standard algorithm */
//Vresidual[i*nsec + nsec] = Vresidual[i*nsec];
invdt1 = SoundSpeed[i*nsec + j]/(min2(dxrad,dxtheta));
invdt2 = fabs(Vrad[i*nsec + j])/dxrad;
invdt3 = fabs(Vresidual[i*nsec + j])/dxtheta;
dvr = Vrad[(i+1)*nsec + j]-Vrad[i*nsec + j];
dvt = Vtheta[i*nsec + (j+1)%nsec]-Vtheta[i*nsec + j];
if (dvr >= 0.0) dvr = 1e-10;
else dvr = -dvr;
if (dvt >= 0.0) dvt = 1e-10;
else dvt = -dvt;
invdt4 = max2(dvr/dxrad, dvt/dxtheta);
invdt4*= 4.0*CVNR*CVNR;
dt = CFLSECURITY/sqrt(invdt1*invdt1+invdt2*invdt2+invdt3*invdt3+invdt4*invdt4);
DT2D[i*nsec + j] = dt; // array nrad*nsec size dt
}
}
	.file	"tmpxft_0037c496_00000000-6_ConditionCFLKernel2D1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4min2dd
	.type	_Z4min2dd, @function
_Z4min2dd:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z4min2dd, .-_Z4min2dd
	.globl	_Z4max2dd
	.type	_Z4max2dd, @function
_Z4max2dd:
.LFB2154:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z4min2dd
	.cfi_endproc
.LFE2154:
	.size	_Z4max2dd, .-_Z4max2dd
	.globl	_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_
	.type	_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_, @function
_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 32(%rsp)
	movq	280(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	296(%rsp), %rax
	movl	%ecx, 52(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 16(%rsp)
	movq	304(%rsp), %rax
	movl	%r8d, 48(%rsp)
	movq	%rax, 8(%rsp)
	movq	312(%rsp), %rax
	movq	%r9, 40(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	96(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 288
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L6:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_, .-_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_
	.globl	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.type	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, @function
_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_PdS_S_iiS_S_S_iS_S_S_
	.cfi_endproc
.LFE2035:
	.size	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, .-_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ double min2(double a, double b)
{
if (b < a) return b;
return a;
}
__device__ double max2(double a, double b)
{
if (b > a) return b;
return a;
}
__global__ void ConditionCFLKernel2D1 (double *Rsup, double *Rinf, double *Rmed, int nsec, int nrad, double *Vresidual, double *Vtheta, double *Vmoy, int FastTransport, double *SoundSpeed, double *Vrad, double *DT2D)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;

double dxrad, dxtheta, invdt1, invdt2, invdt3, invdt4, dvr, dvt, dt;

if (i > 0 && i<nrad && j<nsec){
dxrad = Rsup[i]-Rinf[i];
dxtheta = Rmed[i]*2.0*PI/(double)nsec;
if (FastTransport) Vresidual[i*nsec + j] = Vtheta[i*nsec + j]-Vmoy[i]; /* Fargo algorithm */
else Vresidual[i*nsec + j] = Vtheta[i*nsec + j];                       /* Standard algorithm */
//Vresidual[i*nsec + nsec] = Vresidual[i*nsec];
invdt1 = SoundSpeed[i*nsec + j]/(min2(dxrad,dxtheta));
invdt2 = fabs(Vrad[i*nsec + j])/dxrad;
invdt3 = fabs(Vresidual[i*nsec + j])/dxtheta;
dvr = Vrad[(i+1)*nsec + j]-Vrad[i*nsec + j];
dvt = Vtheta[i*nsec + (j+1)%nsec]-Vtheta[i*nsec + j];
if (dvr >= 0.0) dvr = 1e-10;
else dvr = -dvr;
if (dvt >= 0.0) dvt = 1e-10;
else dvt = -dvt;
invdt4 = max2(dvr/dxrad, dvt/dxtheta);
invdt4*= 4.0*CVNR*CVNR;
dt = CFLSECURITY/sqrt(invdt1*invdt1+invdt2*invdt2+invdt3*invdt3+invdt4*invdt4);
DT2D[i*nsec + j] = dt; // array nrad*nsec size dt
}
}
	.text
	.file	"ConditionCFLKernel2D1.hip"
	.globl	_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_ # -- Begin function _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.type	_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_,@function
_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_: # @_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, .Lfunc_end0-_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_,@object # @_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.p2align	3, 0x0
_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_:
	.quad	_Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.size	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_"
	.size	.L__unnamed_1, 47

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_ ; -- Begin function _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.globl	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
	.p2align	8
	.type	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_,@function
_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_: ; @_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x64
	s_load_b64 s[8:9], s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[4:5], null, s14, s2, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s9, v0
	v_cmp_lt_i32_e64 s3, 0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s8, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_7
; %bb.1:
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mul_lo_u32 v16, v0, s8
	v_mov_b32_e32 v1, 0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x20
	s_load_b32 s9, s[0:1], 0x38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	v_add_nc_u32_e32 v9, v16, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[0:1], 3, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s12, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v3, vcc_lo
	v_add_co_u32 v7, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v3, vcc_lo
	v_add_co_u32 v12, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[14:15], v[10:11], off
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_3
; %bb.2:
	s_load_b64 s[2:3], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v17, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_mov_b32 s2, 0
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[14:15], -v[2:3]
	global_store_b64 v[17:18], v[2:3], off
	global_load_b64 v[10:11], v[10:11], off
	s_branch .LBB0_4
.LBB0_3:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr10_vgpr11
.LBB0_4:                                ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_6
; %bb.5:
	v_add_co_u32 v17, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v10, v14 :: v_dual_mov_b32 v11, v15
	v_dual_mov_b32 v2, v14 :: v_dual_mov_b32 v3, v15
	global_store_b64 v[17:18], v[14:15], off
.LBB0_6:
	s_waitcnt vmcnt(1)
	v_add_f64 v[12:13], v[12:13], v[12:13]
	s_ashr_i32 s2, s8, 31
	v_add_nc_u32_e32 v4, 1, v4
	s_add_i32 s3, s8, s2
	s_load_b128 s[12:15], s[0:1], 0x40
	s_xor_b32 s4, s3, s2
	s_mov_b32 s2, 0x54442d18
	s_waitcnt vmcnt(0)
	v_cvt_f32_u32_e32 v14, s4
	s_mov_b32 s3, 0x400921fb
	s_sub_i32 s5, 0, s4
	v_ashrrev_i32_e32 v20, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v14, v14
	v_add_nc_u32_e32 v4, v4, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v20
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v14, 0x4f7ffffe, v14
	v_cvt_u32_f32_e32 v17, v14
	v_cvt_f64_i32_e32 v[14:15], s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v18, s5, v17
	v_mul_f64 v[12:13], v[12:13], s[2:3]
	v_mul_hi_u32 v18, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v17, v17, v18
	v_mul_hi_u32 v17, v4, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v17, s4
	v_sub_nc_u32_e32 v4, v4, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v19, s4, v4
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	v_div_scale_f64 v[17:18], null, v[14:15], v[14:15], v[12:13]
	v_cndmask_b32_e32 v4, v4, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v19, s4, v4
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	s_load_b64 s[4:5], s[0:1], 0x50
	v_dual_cndmask_b32 v4, v4, v19 :: v_dual_add_nc_u32 v19, s8, v9
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v25, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v26, vcc_lo, s15, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v20
	v_sub_nc_u32_e32 v4, v4, v20
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v21, v4, v16
	v_lshlrev_b64 v[19:20], 3, v[19:20]
	v_add_f64 v[4:5], v[5:6], -v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v22, 31, v21
	v_add_co_u32 v19, vcc_lo, s14, v19
	v_rcp_f64_e32 v[23:24], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[21:22], 3, v[21:22]
	v_add_co_ci_u32_e32 v20, vcc_lo, s15, v20, vcc_lo
	v_add_co_u32 v21, vcc_lo, s6, v21
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v22, vcc_lo, s7, v22, vcc_lo
	s_clause 0x1
	global_load_b64 v[25:26], v[25:26], off
	global_load_b64 v[19:20], v[19:20], off
	global_load_b64 v[21:22], v[21:22], off
	v_add_co_u32 v29, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v30, vcc_lo, s13, v1, vcc_lo
	v_div_scale_f64 v[31:32], vcc_lo, v[12:13], v[14:15], v[12:13]
	global_load_b64 v[29:30], v[29:30], off
	v_fma_f64 v[27:28], -v[17:18], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_fma_f64 v[27:28], -v[17:18], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_mul_f64 v[27:28], v[31:32], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[17:18], v[27:28], v[31:32]
	v_div_fmas_f64 v[16:17], v[16:17], v[23:24], v[27:28]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[6:7], v[16:17], v[14:15], v[12:13]
	s_waitcnt vmcnt(3)
	v_and_b32_e32 v14, 0x7fffffff, v26
	s_waitcnt vmcnt(2)
	v_add_f64 v[8:9], v[19:20], -v[25:26]
	s_waitcnt vmcnt(1)
	v_add_f64 v[10:11], v[21:22], -v[10:11]
	v_mov_b32_e32 v13, v25
	v_dual_mov_b32 v19, v2 :: v_dual_and_b32 v20, 0x7fffffff, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_div_scale_f64 v[17:18], null, v[4:5], v[4:5], v[13:14]
	v_cmp_lt_f64_e32 vcc_lo, v[6:7], v[4:5]
	v_cmp_nle_f64_e64 s0, 0, v[8:9]
	v_cmp_nle_f64_e64 s1, 0, v[10:11]
	v_xor_b32_e32 v23, 0x80000000, v11
	v_xor_b32_e32 v21, 0x80000000, v9
	v_rcp_f64_e32 v[35:36], v[17:18]
	v_dual_cndmask_b32 v12, v5, v7 :: v_dual_cndmask_b32 v11, v4, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_div_scale_f64 v[15:16], null, v[11:12], v[11:12], v[29:30]
	v_div_scale_f64 v[53:54], vcc_lo, v[29:30], v[11:12], v[29:30]
	v_cndmask_b32_e64 v9, 0x3ddb7cdf, v21, s0
	v_cndmask_b32_e64 v8, 0xd9d7bdbb, v8, s0
	v_cndmask_b32_e64 v24, 0x3ddb7cdf, v23, s1
	v_cndmask_b32_e64 v23, 0xd9d7bdbb, v10, s1
	v_div_scale_f64 v[21:22], null, v[6:7], v[6:7], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[27:28], null, v[4:5], v[4:5], v[8:9]
	v_div_scale_f64 v[31:32], null, v[6:7], v[6:7], v[23:24]
	s_delay_alu instid0(TRANS32_DEP_1)
	v_fma_f64 v[45:46], -v[17:18], v[35:36], 1.0
	v_div_scale_f64 v[13:14], s0, v[13:14], v[4:5], v[13:14]
	v_div_scale_f64 v[19:20], s1, v[19:20], v[6:7], v[19:20]
	v_rcp_f64_e32 v[33:34], v[15:16]
	v_rcp_f64_e32 v[37:38], v[21:22]
	v_rcp_f64_e32 v[39:40], v[27:28]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[41:42], v[31:32]
	v_fma_f64 v[35:36], v[35:36], v[45:46], v[35:36]
	v_fma_f64 v[43:44], -v[15:16], v[33:34], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[47:48], -v[21:22], v[37:38], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[49:50], -v[27:28], v[39:40], 1.0
	v_fma_f64 v[51:52], -v[31:32], v[41:42], 1.0
	v_fma_f64 v[45:46], -v[17:18], v[35:36], 1.0
	v_fma_f64 v[33:34], v[33:34], v[43:44], v[33:34]
	v_fma_f64 v[37:38], v[37:38], v[47:48], v[37:38]
	v_fma_f64 v[39:40], v[39:40], v[49:50], v[39:40]
	v_fma_f64 v[41:42], v[41:42], v[51:52], v[41:42]
	v_fma_f64 v[35:36], v[35:36], v[45:46], v[35:36]
	v_div_scale_f64 v[45:46], s3, v[23:24], v[6:7], v[23:24]
	v_fma_f64 v[43:44], -v[15:16], v[33:34], 1.0
	v_fma_f64 v[47:48], -v[21:22], v[37:38], 1.0
	v_fma_f64 v[49:50], -v[27:28], v[39:40], 1.0
	v_fma_f64 v[51:52], -v[31:32], v[41:42], 1.0
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[33:34], v[33:34], v[43:44], v[33:34]
	v_div_scale_f64 v[43:44], s2, v[8:9], v[4:5], v[8:9]
	v_fma_f64 v[37:38], v[37:38], v[47:48], v[37:38]
	v_fma_f64 v[39:40], v[39:40], v[49:50], v[39:40]
	v_mul_f64 v[49:50], v[13:14], v[35:36]
	v_fma_f64 v[41:42], v[41:42], v[51:52], v[41:42]
	v_mul_f64 v[47:48], v[53:54], v[33:34]
	v_mul_f64 v[51:52], v[19:20], v[37:38]
	v_mul_f64 v[55:56], v[43:44], v[39:40]
	v_fma_f64 v[13:14], -v[17:18], v[49:50], v[13:14]
	v_mul_f64 v[57:58], v[45:46], v[41:42]
	v_fma_f64 v[15:16], -v[15:16], v[47:48], v[53:54]
	v_fma_f64 v[17:18], -v[21:22], v[51:52], v[19:20]
	v_fma_f64 v[19:20], -v[27:28], v[55:56], v[43:44]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], -v[31:32], v[57:58], v[45:46]
	v_div_fmas_f64 v[15:16], v[15:16], v[33:34], v[47:48]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[13:14], v[13:14], v[35:36], v[49:50]
	s_mov_b32 vcc_lo, s1
	s_mov_b32 s0, 0xf212d772
	s_mov_b32 s1, 0x401fcf41
	v_div_fmas_f64 v[17:18], v[17:18], v[37:38], v[51:52]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[19:20], v[19:20], v[39:40], v[55:56]
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f64 v[21:22], v[21:22], v[41:42], v[57:58]
	v_div_fixup_f64 v[10:11], v[15:16], v[11:12], v[29:30]
	v_div_fixup_f64 v[13:14], v[13:14], v[4:5], |v[25:26]|
	v_div_fixup_f64 v[2:3], v[17:18], v[6:7], |v[2:3]|
	v_div_fixup_f64 v[4:5], v[19:20], v[4:5], v[8:9]
	v_div_fixup_f64 v[8:9], v[21:22], v[6:7], v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[12:13], v[13:14], v[13:14]
	v_cmp_gt_f64_e32 vcc_lo, v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[10:11], v[10:11], v[12:13]
	v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
	v_mul_f64 v[4:5], v[4:5], s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], v[2:3], v[6:7]
	v_fma_f64 v[2:3], v[4:5], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[2:3]
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v4, 8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[2:3], v[2:3], v4
	v_rsq_f64_e32 v[4:5], v[2:3]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[6:7], v[2:3], v[4:5]
	v_mul_f64 v[4:5], v[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 0.5
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
	v_fma_f64 v[6:7], v[8:9], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
	v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
	v_cndmask_b32_e64 v6, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[4:5], v[4:5], v6
	v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 0.5
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_div_scale_f64 v[8:9], vcc_lo, 0.5, v[2:3], 0.5
	v_mul_f64 v[10:11], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 0.5
	global_store_b64 v[0:1], v[2:3], off
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 59
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_, .Lfunc_end0-_Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1912
; NumSgprs: 18
; NumVgprs: 59
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 59
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21ConditionCFLKernel2D1PdS_S_iiS_S_S_iS_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     59
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
