// Author: Amandeep Kaur (2018014)
// As part of assignment 1 in CSE:560 GPU computing course
// Code adapted from given code file ahe_cpu.cpp provided by Prof. Ojaswa Sharma

#include <stdio.h>
#include <iostream>
#include <time.h>

#define TILE_SIZE_X 1024
#define TILE_SIZE_Y 1024

__constant__ unsigned char const_mappings[65536];

__global__ void findEqualizationMappings(unsigned char* img_in, int width, int height, unsigned char *mappings, int *pdf, int *cdf)
{
	int ntiles_x = (width / TILE_SIZE_X);

	int ty = threadIdx.y;
	int tx = threadIdx.x;
	int by = blockIdx.y;
	int bx = blockIdx.x;

	int row = by * blockDim.y + ty;
    int col = bx * blockDim.x + tx;
    
    if (row<height && col<width){
		int tile_i = (col)/TILE_SIZE_X; //0-indexed
		int tile_j = (row)/TILE_SIZE_Y;
		int offset = 256*(tile_i + tile_j * ntiles_x);
		atomicAdd(&pdf[offset + img_in[col+row*width]],1);
		__syncthreads();

		if ((row+1)%TILE_SIZE_Y==0 && (col + 1)%TILE_SIZE_X==0){ //one thread from each block
			int cdf_min = TILE_SIZE_X*TILE_SIZE_Y+1; // minimum non-zero value 
			cdf[offset]=pdf[offset];
			for(int i=1; i< 256; i++)
				cdf[offset+i] = cdf[offset+i-1] + pdf[offset+i];
			for(int i=0; i<256; i++)
				if(cdf[offset+i] != 0) {cdf_min = cdf[offset+i]; break;}
		
			for (int i=0;i<256;i++){
				mappings[i + offset] = (unsigned char)round(255.0 * float(cdf[offset+i] - cdf_min)/float(TILE_SIZE_X*TILE_SIZE_Y - cdf_min));
				}
			}
	}
}

__global__ void performAdaptiveEqualization(unsigned char* img_in, unsigned char* img_out, int width, int height){

	int ntiles_x = (width / TILE_SIZE_X);
	int ntiles_y = (height / TILE_SIZE_Y);

	int ty = threadIdx.y;
	int tx = threadIdx.x;
	int by = blockIdx.y;
	int bx = blockIdx.x;

	int row = by * blockDim.y + ty;
    int col = bx * blockDim.x + tx;

    if (row<height && col<width){

		// FINDING TILE CENTERS FOR INTERPOLATION
		int tile_i0, tile_j0, tile_i1, tile_j1;
		tile_i0 = (col - TILE_SIZE_X/2) / TILE_SIZE_X;
		if(tile_i0 < 0) tile_i0 = 0;
		tile_j0 = (row - TILE_SIZE_Y/2) / TILE_SIZE_Y;
		if(tile_j0 < 0) tile_j0 = 0;
		tile_i1 = (col + TILE_SIZE_X/2) / TILE_SIZE_X;
		if(tile_i1 >= ntiles_x) tile_i1 = ntiles_x - 1;
		tile_j1 = (row + TILE_SIZE_Y/2) / TILE_SIZE_Y;
		if(tile_j1 >= ntiles_y) tile_j1 = ntiles_y - 1;

		// OFFSETS IN INTERMEDIATE ARRAYS CORRESPONDING TO TILE CENTERS
		int offset00 = 256*(tile_i0 + tile_j0*ntiles_x);
		int offset01 = 256*(tile_i0 + tile_j1*ntiles_x);
		int offset10 = 256*(tile_i1 + tile_j0*ntiles_x);
		int offset11 = 256*(tile_i1 + tile_j1*ntiles_x);

	    unsigned char v00, v01, v10, v11;
		v00 = const_mappings[img_in[col+row*width] + offset00];
		v01 = const_mappings[img_in[col+row*width] + offset01];
		v10 = const_mappings[img_in[col+row*width] + offset10];
		v11 = const_mappings[img_in[col+row*width] + offset11];

		float x_frac = float(col - tile_i0*TILE_SIZE_X - TILE_SIZE_X/2)/float(TILE_SIZE_X);
		float y_frac = float(row - tile_j0*TILE_SIZE_Y - TILE_SIZE_Y/2)/float(TILE_SIZE_Y);
		
		//PERFORMING BILINEAR INTERPOLATION
	  	float v0 = v00*(1 - x_frac) + v10*x_frac;
		float v1 = v01*(1 - x_frac) + v11*x_frac;
	    float v= v0*(1 - y_frac) + v1*y_frac;

		if (v < 0) v = 0;
		if (v > 255) v = 255;

	    img_out[col+row*width] = (unsigned char)(v);
	}
}

extern "C" void run_sampleKernel(unsigned char* img_in, unsigned char* img_out, int width, int height)
{
  int ntiles_x = (width / TILE_SIZE_X);
  int ntiles_y = (height / TILE_SIZE_Y);
  int ntiles = (ntiles_x * ntiles_y);

// INITIALIZING REQUIREMENTS
  int *dpdf;
  int *dcdf;
  cudaMalloc((void**)&dpdf, 256*ntiles*sizeof(int));
  cudaMalloc((void**)&dcdf, 256*ntiles*sizeof(int));
  cudaMemset(dpdf, 0, 256*ntiles*sizeof(int));
  unsigned char *dmappings;
  cudaMalloc((void**)&dmappings, 256*ntiles*sizeof(unsigned char));

// WRITING INPUT IMAGE TO DEVICE MEMORY
  unsigned char * dimg_in;
  cudaMalloc((void**)&dimg_in, height*width*sizeof(unsigned char));
  cudaMemcpy(dimg_in,img_in, height*width*sizeof(unsigned char),cudaMemcpyHostToDevice);
  
// INITIALIZING OUTPUT IMAGE SPACE IN DEVICE MEMORY
  unsigned char * dimg_out;
  cudaMalloc((void**)&dimg_out, height*width*sizeof(unsigned char));

// SETTING UP LAUNCH CONFIGURATION
  dim3 grid,block;
  block.x = 32;
  block.y = 32;
  int req = (height*width)/(32*32);
  grid.x = pow(req,0.5);
  grid.y = pow(req,0.5);

// TIMER
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);

  //STEP 1
  findEqualizationMappings<<<grid,block>>>(dimg_in, width, height, dmappings, dpdf, dcdf);
  
 // cudaDeviceSynchronize();
 
 // COPYING MAPPINGS TO CONST_MAPPINGS (TO USE CONSTANT MEMORY)
 int *mappings;
 mappings = (int *)malloc(256*ntiles*sizeof(unsigned char));
 cudaMemcpy(mappings, dmappings, 256*ntiles*sizeof(unsigned char),cudaMemcpyDeviceToHost);
 cudaMemcpyToSymbol(const_mappings, mappings, ntiles*256*sizeof(unsigned char));

//STEP 2
  performAdaptiveEqualization<<<grid,block>>>(dimg_in, dimg_out, width, height);

cudaDeviceSynchronize();
cudaEventRecord(stop);

// WRITING OUTPUT IMAGE TO HOST MEMORY  
  cudaMemcpy(img_out, dimg_out, height*width*sizeof(unsigned char),cudaMemcpyDeviceToHost);

cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout  << "Time taken : " << milliseconds << std::endl;

// CLEANUP
  cudaFree(dpdf);
  cudaFree(dcdf);
  cudaFree(dmappings);
  cudaFree(dimg_out);
  cudaFree(dimg_in);
  cudaFree(const_mappings);
}

	.file	"tmpxft_003352ea_00000000-6_ahe_gpu_kernels.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z24findEqualizationMappingsPhiiS_PiS0_PhiiS_PiS0_
	.type	_Z53__device_stub__Z24findEqualizationMappingsPhiiS_PiS0_PhiiS_PiS0_, @function
_Z53__device_stub__Z24findEqualizationMappingsPhiiS_PiS0_PhiiS_PiS0_:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z24findEqualizationMappingsPhiiS_PiS0_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z53__device_stub__Z24findEqualizationMappingsPhiiS_PiS0_PhiiS_PiS0_, .-_Z53__device_stub__Z24findEqualizationMappingsPhiiS_PiS0_PhiiS_PiS0_
	.globl	_Z24findEqualizationMappingsPhiiS_PiS0_
	.type	_Z24findEqualizationMappingsPhiiS_PiS0_, @function
_Z24findEqualizationMappingsPhiiS_PiS0_:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z24findEqualizationMappingsPhiiS_PiS0_PhiiS_PiS0_
	.cfi_endproc
.LFE3661:
	.size	_Z24findEqualizationMappingsPhiiS_PiS0_, .-_Z24findEqualizationMappingsPhiiS_PiS0_
	.globl	_Z51__device_stub__Z27performAdaptiveEqualizationPhS_iiPhS_ii
	.type	_Z51__device_stub__Z27performAdaptiveEqualizationPhS_iiPhS_ii, @function
_Z51__device_stub__Z27performAdaptiveEqualizationPhS_iiPhS_ii:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z27performAdaptiveEqualizationPhS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z51__device_stub__Z27performAdaptiveEqualizationPhS_iiPhS_ii, .-_Z51__device_stub__Z27performAdaptiveEqualizationPhS_iiPhS_ii
	.globl	_Z27performAdaptiveEqualizationPhS_ii
	.type	_Z27performAdaptiveEqualizationPhS_ii, @function
_Z27performAdaptiveEqualizationPhS_ii:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z27performAdaptiveEqualizationPhS_iiPhS_ii
	.cfi_endproc
.LFE3663:
	.size	_Z27performAdaptiveEqualizationPhS_ii, .-_Z27performAdaptiveEqualizationPhS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"Time taken : "
	.text
	.globl	run_sampleKernel
	.type	run_sampleKernel, @function
run_sampleKernel:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	$1024, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%rsi, 8(%rsp)
	leaq	24(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	%edx, %eax
	cltd
	idivl	%r14d
	movl	%eax, %ebx
	movl	%ecx, %eax
	cltd
	idivl	%r14d
	imull	%eax, %ebx
	sall	$8, %ebx
	movslq	%ebx, %rbx
	leaq	0(,%rbx,4), %r13
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	movq	%r13, %rsi
	leaq	32(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%r13, %rdx
	movl	%ebp, %r13d
	movq	24(%rsp), %rdi
	imull	%r12d, %r13d
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movslq	%r13d, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movq	48(%rsp), %rdi
	movslq	%r13d, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movslq	%r13d, %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movsd	.LC0(%rip), %xmm1
	movabsq	$137438953504, %rax
	movl	$1, 88(%rsp)
	movq	%rax, 92(%rsp)
	movl	%r13d, %eax
	cltd
	movl	$1, 100(%rsp)
	idivl	%r14d
	cvtsi2sdl	%eax, %xmm2
	movaps	%xmm2, %xmm0
	movq	%xmm2, %r13
	call	pow@PLT
	movsd	.LC0(%rip), %xmm1
	cvttsd2siq	%xmm0, %rax
	movq	%r13, %xmm0
	movl	%eax, 80(%rsp)
	call	pow@PLT
	leaq	64(%rsp), %rdi
	cvttsd2siq	%xmm0, %rax
	movl	%eax, 84(%rsp)
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	32(%rsp), %r9
	movq	24(%rsp), %r8
	movl	%r12d, %edx
	movl	%ebp, %esi
	movq	40(%rsp), %rcx
	movq	48(%rsp), %rdi
	call	_Z53__device_stub__Z24findEqualizationMappingsPhiiS_PiS0_PhiiS_PiS0_
.L14:
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	40(%rsp), %rsi
	movq	%rbx, %rdx
	movl	$2, %ecx
	movq	%rax, %rdi
	movq	%rax, %r13
	call	cudaMemcpy@PLT
	movq	%rbx, %rdx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	leaq	_ZL14const_mappings(%rip), %rbx
	movq	%r13, %rsi
	movq	%rbx, %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	100(%rsp), %ecx
	movl	88(%rsp), %esi
	xorl	%r9d, %r9d
	movq	92(%rsp), %rdx
	movq	80(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z51__device_stub__Z27performAdaptiveEqualizationPhS_iiPhS_ii
.L15:
	call	cudaDeviceSynchronize@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	leaq	20(%rsp), %rdi
	movl	$0x00000000, 20(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	20(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	run_sampleKernel, .-run_sampleKernel
	.section	.rodata.str1.1
.LC3:
	.string	"_Z27performAdaptiveEqualizationPhS_ii"
.LC4:
	.string	"_Z24findEqualizationMappingsPhiiS_PiS0_"
.LC5:
	.string	"const_mappings"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z27performAdaptiveEqualizationPhS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z24findEqualizationMappingsPhiiS_PiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movl	$65536, %r9d
	leaq	_ZL14const_mappings(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL14const_mappings
	.comm	_ZL14const_mappings,65536,32
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1071644672
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Author: Amandeep Kaur (2018014)
// As part of assignment 1 in CSE:560 GPU computing course
// Code adapted from given code file ahe_cpu.cpp provided by Prof. Ojaswa Sharma


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <time.h>

#define TILE_SIZE_X 1024
#define TILE_SIZE_Y 1024

__constant__ unsigned char const_mappings[65536];

__global__ void findEqualizationMappings(unsigned char* img_in, int width, int height, unsigned char *mappings, int *pdf, int *cdf)
{
	int ntiles_x = (width / TILE_SIZE_X);

	int ty = threadIdx.y;
	int tx = threadIdx.x;
	int by = blockIdx.y;
	int bx = blockIdx.x;

	int row = by * blockDim.y + ty;
    int col = bx * blockDim.x + tx;
    
    if (row<height && col<width){
		int tile_i = (col)/TILE_SIZE_X; //0-indexed
		int tile_j = (row)/TILE_SIZE_Y;
		int offset = 256*(tile_i + tile_j * ntiles_x);
		atomicAdd(&pdf[offset + img_in[col+row*width]],1);
		__syncthreads();

		if ((row+1)%TILE_SIZE_Y==0 && (col + 1)%TILE_SIZE_X==0){ //one thread from each block
			int cdf_min = TILE_SIZE_X*TILE_SIZE_Y+1; // minimum non-zero value 
			cdf[offset]=pdf[offset];
			for(int i=1; i< 256; i++)
				cdf[offset+i] = cdf[offset+i-1] + pdf[offset+i];
			for(int i=0; i<256; i++)
				if(cdf[offset+i] != 0) {cdf_min = cdf[offset+i]; break;}
		
			for (int i=0;i<256;i++){
				mappings[i + offset] = (unsigned char)round(255.0 * float(cdf[offset+i] - cdf_min)/float(TILE_SIZE_X*TILE_SIZE_Y - cdf_min));
				}
			}
	}
}

__global__ void performAdaptiveEqualization(unsigned char* img_in, unsigned char* img_out, int width, int height){

	int ntiles_x = (width / TILE_SIZE_X);
	int ntiles_y = (height / TILE_SIZE_Y);

	int ty = threadIdx.y;
	int tx = threadIdx.x;
	int by = blockIdx.y;
	int bx = blockIdx.x;

	int row = by * blockDim.y + ty;
    int col = bx * blockDim.x + tx;

    if (row<height && col<width){

		// FINDING TILE CENTERS FOR INTERPOLATION
		int tile_i0, tile_j0, tile_i1, tile_j1;
		tile_i0 = (col - TILE_SIZE_X/2) / TILE_SIZE_X;
		if(tile_i0 < 0) tile_i0 = 0;
		tile_j0 = (row - TILE_SIZE_Y/2) / TILE_SIZE_Y;
		if(tile_j0 < 0) tile_j0 = 0;
		tile_i1 = (col + TILE_SIZE_X/2) / TILE_SIZE_X;
		if(tile_i1 >= ntiles_x) tile_i1 = ntiles_x - 1;
		tile_j1 = (row + TILE_SIZE_Y/2) / TILE_SIZE_Y;
		if(tile_j1 >= ntiles_y) tile_j1 = ntiles_y - 1;

		// OFFSETS IN INTERMEDIATE ARRAYS CORRESPONDING TO TILE CENTERS
		int offset00 = 256*(tile_i0 + tile_j0*ntiles_x);
		int offset01 = 256*(tile_i0 + tile_j1*ntiles_x);
		int offset10 = 256*(tile_i1 + tile_j0*ntiles_x);
		int offset11 = 256*(tile_i1 + tile_j1*ntiles_x);

	    unsigned char v00, v01, v10, v11;
		v00 = const_mappings[img_in[col+row*width] + offset00];
		v01 = const_mappings[img_in[col+row*width] + offset01];
		v10 = const_mappings[img_in[col+row*width] + offset10];
		v11 = const_mappings[img_in[col+row*width] + offset11];

		float x_frac = float(col - tile_i0*TILE_SIZE_X - TILE_SIZE_X/2)/float(TILE_SIZE_X);
		float y_frac = float(row - tile_j0*TILE_SIZE_Y - TILE_SIZE_Y/2)/float(TILE_SIZE_Y);
		
		//PERFORMING BILINEAR INTERPOLATION
	  	float v0 = v00*(1 - x_frac) + v10*x_frac;
		float v1 = v01*(1 - x_frac) + v11*x_frac;
	    float v= v0*(1 - y_frac) + v1*y_frac;

		if (v < 0) v = 0;
		if (v > 255) v = 255;

	    img_out[col+row*width] = (unsigned char)(v);
	}
}

extern "C" void run_sampleKernel(unsigned char* img_in, unsigned char* img_out, int width, int height)
{
  int ntiles_x = (width / TILE_SIZE_X);
  int ntiles_y = (height / TILE_SIZE_Y);
  int ntiles = (ntiles_x * ntiles_y);

// INITIALIZING REQUIREMENTS
  int *dpdf;
  int *dcdf;
  hipMalloc((void**)&dpdf, 256*ntiles*sizeof(int));
  hipMalloc((void**)&dcdf, 256*ntiles*sizeof(int));
  hipMemset(dpdf, 0, 256*ntiles*sizeof(int));
  unsigned char *dmappings;
  hipMalloc((void**)&dmappings, 256*ntiles*sizeof(unsigned char));

// WRITING INPUT IMAGE TO DEVICE MEMORY
  unsigned char * dimg_in;
  hipMalloc((void**)&dimg_in, height*width*sizeof(unsigned char));
  hipMemcpy(dimg_in,img_in, height*width*sizeof(unsigned char),hipMemcpyHostToDevice);
  
// INITIALIZING OUTPUT IMAGE SPACE IN DEVICE MEMORY
  unsigned char * dimg_out;
  hipMalloc((void**)&dimg_out, height*width*sizeof(unsigned char));

// SETTING UP LAUNCH CONFIGURATION
  dim3 grid,block;
  block.x = 32;
  block.y = 32;
  int req = (height*width)/(32*32);
  grid.x = pow(req,0.5);
  grid.y = pow(req,0.5);

// TIMER
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);

  //STEP 1
  findEqualizationMappings<<<grid,block>>>(dimg_in, width, height, dmappings, dpdf, dcdf);
  
 // cudaDeviceSynchronize();
 
 // COPYING MAPPINGS TO CONST_MAPPINGS (TO USE CONSTANT MEMORY)
 int *mappings;
 mappings = (int *)malloc(256*ntiles*sizeof(unsigned char));
 hipMemcpy(mappings, dmappings, 256*ntiles*sizeof(unsigned char),hipMemcpyDeviceToHost);
 hipMemcpyToSymbol(HIP_SYMBOL(const_mappings), mappings, ntiles*256*sizeof(unsigned char));

//STEP 2
  performAdaptiveEqualization<<<grid,block>>>(dimg_in, dimg_out, width, height);

hipDeviceSynchronize();
hipEventRecord(stop);

// WRITING OUTPUT IMAGE TO HOST MEMORY  
  hipMemcpy(img_out, dimg_out, height*width*sizeof(unsigned char),hipMemcpyDeviceToHost);

hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout  << "Time taken : " << milliseconds << std::endl;

// CLEANUP
  hipFree(dpdf);
  hipFree(dcdf);
  hipFree(dmappings);
  hipFree(dimg_out);
  hipFree(dimg_in);
  hipFree(const_mappings);
}

	.text
	.file	"ahe_gpu_kernels.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_ # -- Begin function _Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_
	.type	_Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_,@function
_Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_: # @_Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24findEqualizationMappingsPhiiS_PiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_, .Lfunc_end0-_Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__performAdaptiveEqualizationPhS_ii # -- Begin function _Z42__device_stub__performAdaptiveEqualizationPhS_ii
	.type	_Z42__device_stub__performAdaptiveEqualizationPhS_ii,@function
_Z42__device_stub__performAdaptiveEqualizationPhS_ii: # @_Z42__device_stub__performAdaptiveEqualizationPhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27performAdaptiveEqualizationPhS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z42__device_stub__performAdaptiveEqualizationPhS_ii, .Lfunc_end1-_Z42__device_stub__performAdaptiveEqualizationPhS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function run_sampleKernel
.LCPI2_0:
	.quad	0x7fffffffffffffff              # double NaN
	.quad	0x7fffffffffffffff              # double NaN
	.text
	.globl	run_sampleKernel
	.type	run_sampleKernel,@function
run_sampleKernel:                       # @run_sampleKernel
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movq	%rsi, 80(%rsp)                  # 8-byte Spill
	movq	%rdi, 48(%rsp)                  # 8-byte Spill
	movl	$1023, %ebx                     # imm = 0x3FF
	leal	(%r15,%rbx), %eax
	testl	%edx, %edx
	cmovnsl	%edx, %eax
	sarl	$10, %eax
	leal	(%r14,%rbx), %ecx
	testl	%r14d, %r14d
	cmovnsl	%r14d, %ecx
	sarl	$10, %ecx
	imull	%eax, %ecx
	shll	$8, %ecx
	movslq	%ecx, %r13
	leaq	(,%r13,4), %r12
	leaq	40(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	hipMemset
	leaq	24(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movl	%r14d, %eax
	imull	%r15d, %eax
	movslq	%eax, %r12
	leaq	16(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	addl	%r12d, %ebx
	testl	%r12d, %r12d
	cmovnsl	%r12d, %ebx
	sarl	$10, %ebx
	cvtsi2sd	%ebx, %xmm2
	sqrtsd	%xmm2, %xmm1
	xorpd	%xmm3, %xmm3
	ucomisd	%xmm3, %xmm2
	movapd	%xmm1, %xmm0
	jae	.LBB2_2
# %bb.1:                                # %call.sqrt
	movapd	%xmm2, %xmm0
	movapd	%xmm1, 48(%rsp)                 # 16-byte Spill
	movsd	%xmm2, 72(%rsp)                 # 8-byte Spill
	callq	sqrt@PLT
	xorpd	%xmm3, %xmm3
	movsd	72(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	movapd	48(%rsp), %xmm1                 # 16-byte Reload
.LBB2_2:                                # %.split
	andpd	.LCPI2_0(%rip), %xmm0
	cvttsd2si	%xmm0, %rax
	movl	%eax, %ebp
	ucomisd	%xmm3, %xmm2
	jae	.LBB2_4
# %bb.3:                                # %call.sqrt65
	movapd	%xmm2, %xmm0
	callq	sqrt@PLT
	movapd	%xmm0, %xmm1
.LBB2_4:                                # %.split.split
	andpd	.LCPI2_0(%rip), %xmm1
	cvttsd2si	%xmm1, %rbx
	shlq	$32, %rbx
	orq	%rbp, %rbx
	leaq	88(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%rbx, %rdi
	movl	$1, %esi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rcx
	movq	40(%rsp), %r8
	movq	32(%rsp), %r9
	movl	%r15d, %esi
	movl	%r14d, %edx
	callq	_Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_
.LBB2_6:
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %rbp
	movq	24(%rsp), %rsi
	movq	%rax, %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$const_mappings, %edi
	movq	%rbp, %rsi
	movq	%r13, %rdx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movq	%rbx, %rdi
	movl	$1, %esi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	callq	_Z42__device_stub__performAdaptiveEqualizationPhS_ii
.LBB2_8:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rsi
	movq	80(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	100(%rsp), %rbx
	movl	$0, (%rbx)
	movq	88(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$13, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movl	$const_mappings, %edi
	callq	hipFree
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	run_sampleKernel, .Lfunc_end2-run_sampleKernel
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24findEqualizationMappingsPhiiS_PiS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27performAdaptiveEqualizationPhS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$const_mappings, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$65536, %r9d                    # imm = 0x10000
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	const_mappings,@object          # @const_mappings
	.local	const_mappings
	.comm	const_mappings,65536,16
	.type	_Z24findEqualizationMappingsPhiiS_PiS0_,@object # @_Z24findEqualizationMappingsPhiiS_PiS0_
	.section	.rodata,"a",@progbits
	.globl	_Z24findEqualizationMappingsPhiiS_PiS0_
	.p2align	3, 0x0
_Z24findEqualizationMappingsPhiiS_PiS0_:
	.quad	_Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_
	.size	_Z24findEqualizationMappingsPhiiS_PiS0_, 8

	.type	_Z27performAdaptiveEqualizationPhS_ii,@object # @_Z27performAdaptiveEqualizationPhS_ii
	.globl	_Z27performAdaptiveEqualizationPhS_ii
	.p2align	3, 0x0
_Z27performAdaptiveEqualizationPhS_ii:
	.quad	_Z42__device_stub__performAdaptiveEqualizationPhS_ii
	.size	_Z27performAdaptiveEqualizationPhS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Time taken : "
	.size	.L.str, 14

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z24findEqualizationMappingsPhiiS_PiS0_"
	.size	.L__unnamed_1, 40

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z27performAdaptiveEqualizationPhS_ii"
	.size	.L__unnamed_2, 38

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"const_mappings"
	.size	.L__unnamed_3, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__findEqualizationMappingsPhiiS_PiS0_
	.addrsig_sym _Z42__device_stub__performAdaptiveEqualizationPhS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym const_mappings
	.addrsig_sym _Z24findEqualizationMappingsPhiiS_PiS0_
	.addrsig_sym _Z27performAdaptiveEqualizationPhS_ii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24findEqualizationMappingsPhiiS_PiS0_ ; -- Begin function _Z24findEqualizationMappingsPhiiS_PiS0_
	.globl	_Z24findEqualizationMappingsPhiiS_PiS0_
	.p2align	8
	.type	_Z24findEqualizationMappingsPhiiS_PiS0_,@function
_Z24findEqualizationMappingsPhiiS_PiS0_: ; @_Z24findEqualizationMappingsPhiiS_PiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x8
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s3, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_cmp_gt_i32_e32 vcc_lo, s9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s8, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_11
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x10
	v_mad_u64_u32 v[1:2], null, v3, s8, v[0:1]
	v_ashrrev_i32_e32 v4, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v4, 22, v4
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v0, v4
	v_ashrrev_i32_e32 v6, 10, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	s_ashr_i32 s2, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s2, s2, 22
	global_load_u8 v1, v[1:2], off
	v_ashrrev_i32_e32 v2, 31, v3
	s_add_i32 s2, s8, s2
	s_ashr_i32 s2, s2, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 22, v2
	v_add_nc_u32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 10, v2
	v_mul_i32_i24_e32 v7, s2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v2, v6, v7, 8
	s_waitcnt vmcnt(0)
	v_or_b32_e32 v4, v2, v1
	v_mov_b32_e32 v1, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_atomic_add_u32 v[4:5], v1, off
	v_add_nc_u32_e32 v1, 1, v3
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_and_b32_e32 v1, 0x3ff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.2:
	v_add_nc_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 0x3ff, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.3:
	v_ashrrev_i32_e32 v3, 31, v2
	s_load_b64 s[0:1], s[0:1], 0x20
	s_mov_b64 s[2:3], 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v4, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v8, v[4:5], off
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v8, off
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v9, vcc_lo, v4, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v11, v[9:10], off
	v_add_co_u32 v9, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v1, vcc_lo
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmpk_lg_i32 s2, 0x400
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, v11, v8
	global_store_b32 v[9:10], v8, off
	s_cbranch_scc1 .LBB0_4
; %bb.5:                                ; %.preheader.preheader
	v_lshlrev_b32_e32 v4, 8, v6
	s_mov_b32 s2, 0
	s_mov_b32 s3, 0
                                        ; implicit-def: $sgpr6
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v4, v7, 8, v4
.LBB0_6:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s3, v4
	s_or_b32 s6, s6, exec_lo
	s_mov_b32 s7, exec_lo
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v6, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v6
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	s_add_i32 s3, s3, 1
	v_mov_b32_e32 v6, 0x100001
	s_cmpk_eq_i32 s3, 0x100
	s_cselect_b32 s8, -1, 0
	s_and_not1_b32 s6, s6, exec_lo
	s_and_b32 s8, s8, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s6, s8
; %bb.8:                                ; %Flow117
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, exec_lo, s6
	s_or_b32 s2, s7, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_6
; %bb.9:
	s_or_b32 exec_lo, exec_lo, s2
	v_sub_nc_u32_e32 v4, 0x100000, v6
	v_add_co_u32 v7, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v4, v4
	v_mov_b32_e32 v2, 0
	s_mov_b64 s[0:1], 0
	v_cvt_f64_f32_e32 v[4:5], v4
.LBB0_10:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_cvt_f64_f32_e32 v[9:10], v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], 0x406fe000, v[9:10]
	v_div_scale_f64 v[11:12], null, v[4:5], v[4:5], v[9:10]
	v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[4:5], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[13:14], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
	v_div_fixup_f64 v[9:10], v[11:12], v[4:5], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f64_e32 v[11:12], v[9:10]
	v_add_f64 v[13:14], v[9:10], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f64_e64 s2, |v[13:14]|, 0.5
	v_cndmask_b32_e64 v3, 0, 0x3ff00000, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v3, 0x7fffffff, v3, v10
	v_add_f64 v[9:10], v[11:12], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_i32_f64_e32 v3, v[9:10]
	v_add_co_u32 v9, vcc_lo, v7, s0
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v8, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmpk_lg_i32 s0, 0x100
	global_store_b8 v[9:10], v3, off
	s_cbranch_scc1 .LBB0_10
.LBB0_11:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24findEqualizationMappingsPhiiS_PiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24findEqualizationMappingsPhiiS_PiS0_, .Lfunc_end0-_Z24findEqualizationMappingsPhiiS_PiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 988
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27performAdaptiveEqualizationPhS_ii ; -- Begin function _Z27performAdaptiveEqualizationPhS_ii
	.globl	_Z27performAdaptiveEqualizationPhS_ii
	.p2align	8
	.type	_Z27performAdaptiveEqualizationPhS_ii,@function
_Z27performAdaptiveEqualizationPhS_ii:  ; @_Z27performAdaptiveEqualizationPhS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s4, v1
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
	v_add_nc_u32_e32 v9, 0xfffffe00, v0
	v_add_nc_u32_e32 v0, 0x200, v0
	v_add_nc_u32_e32 v8, 0xfffffe00, v1
	v_add_nc_u32_e32 v1, 0x200, v1
	v_ashrrev_i32_e32 v5, 31, v9
	v_ashrrev_i32_e32 v7, 31, v2
	v_ashrrev_i32_e32 v6, 31, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v10, 31, v1
	v_lshrrev_b32_e32 v5, 22, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v6, 22, v6
	v_lshrrev_b32_e32 v10, 22, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v0, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v7, vcc_lo
	s_ashr_i32 s0, s5, 31
	v_add_nc_u32_e32 v1, v1, v10
	s_lshr_b32 s0, s0, 22
	global_load_u8 v3, v[3:4], off
	v_ashrrev_i32_e32 v4, 31, v8
	v_ashrrev_i32_e32 v0, 10, v0
	s_add_i32 s0, s5, s0
	s_ashr_i32 s1, s4, 31
	s_ashr_i32 s0, s0, 10
	s_lshr_b32 s1, s1, 22
	v_lshrrev_b32_e32 v4, 22, v4
	v_ashrrev_i32_e32 v1, 10, v1
	v_cmp_gt_i32_e32 vcc_lo, s0, v0
	s_add_i32 s1, s4, s1
	s_add_i32 s5, s0, -1
	s_ashr_i32 s1, s1, 10
	v_dual_cndmask_b32 v0, s5, v0 :: v_dual_add_nc_u32 v5, v9, v5
	s_add_i32 s4, s1, -1
	v_cmp_gt_i32_e32 vcc_lo, s1, v1
	v_add_nc_u32_e32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 10, v5
	v_cndmask_b32_e32 v1, s4, v1, vcc_lo
	v_ashrrev_i32_e32 v4, 10, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v11, 0, v5
	v_max_i32_e32 v10, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_i32_i24 v6, v11, s1, v1
	v_mad_i32_i24 v5, v0, s1, v10
	v_mad_i32_i24 v4, v11, s1, v10
	v_mad_i32_i24 v0, v0, s1, v1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, const_mappings@rel32@lo+4
	s_addc_u32 s1, s1, const_mappings@rel32@hi+12
	s_waitcnt vmcnt(0)
	v_lshl_or_b32 v1, v5, 8, v3
	v_lshl_or_b32 v12, v4, 8, v3
	v_lshl_or_b32 v5, v6, 8, v3
	v_lshl_or_b32 v3, v0, 8, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v1
	v_add_co_u32 v0, vcc_lo, v1, s0
	v_ashrrev_i32_e32 v14, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v14, vcc_lo
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_u32 v5, vcc_lo, v5, s0
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_u8 v14, v[3:4], off
	v_add_co_u32 v3, vcc_lo, v12, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v13, vcc_lo
	s_clause 0x2
	global_load_u8 v5, v[5:6], off
	global_load_u8 v0, v[0:1], off
	global_load_u8 v1, v[3:4], off
	v_lshlrev_b32_e32 v3, 10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v8, v3
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v6, 0x3a800000, v3
	v_fma_f32 v3, 0xba800000, v3, 1.0
	s_waitcnt vmcnt(3)
	v_cvt_f32_ubyte0_e32 v8, v14
	s_waitcnt vmcnt(2)
	v_cvt_f32_ubyte0_e32 v5, v5
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte0_e32 v0, v0
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v1, v1
	v_mul_f32_e32 v8, v6, v8
	v_dual_mul_f32 v5, v6, v5 :: v_dual_lshlrev_b32 v4, 10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v5, v3, v1
	v_sub_nc_u32_e32 v4, v9, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v3, v0
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, 0x3a800000, v4
	v_fma_f32 v0, 0xba800000, v4, 1.0
	v_mul_f32_e32 v1, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, v0, v5
	v_cmp_ngt_f32_e32 vcc_lo, 0, v1
	v_cndmask_b32_e32 v0, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v0
	v_cndmask_b32_e32 v0, 0x437f0000, v0, vcc_lo
	v_cvt_i32_f32_e32 v3, v0
	v_add_co_u32 v0, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
	global_store_b8 v[0:1], v3, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27performAdaptiveEqualizationPhS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z27performAdaptiveEqualizationPhS_ii, .Lfunc_end1-_Z27performAdaptiveEqualizationPhS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 740
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	const_mappings          ; @const_mappings
	.type	const_mappings,@object
	.section	.bss,"aw",@nobits
	.globl	const_mappings
	.p2align	4, 0x0
const_mappings:
	.zero	65536
	.size	const_mappings, 65536

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym const_mappings
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24findEqualizationMappingsPhiiS_PiS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24findEqualizationMappingsPhiiS_PiS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27performAdaptiveEqualizationPhS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z27performAdaptiveEqualizationPhS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
