#include "matmul.hh"
#include "../runtime/node.hh"


namespace gpu
{

    namespace
    {

        __global__
        void matmul(const dbl_t* a, const dbl_t* b, dbl_t* out,
                    std::size_t arows, std::size_t acols, std::size_t bcols)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= arows || col >= bcols)
                return;

            dbl_t x = 0;
            for (std::size_t i = 0; i < acols; ++i)
                x += a[row * acols + i] * b[i * bcols + col];
            out[row * bcols + col] = x;
        }

        __global__
        void mvrow_add(const dbl_t* a, const dbl_t* b, dbl_t* out,
                       std::size_t rows, std::size_t cols)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= rows || col >= cols)
                return;

            out[row * cols + col] = a[row * cols + col] + b[col];
        }

        __global__
        void matmul_add(const dbl_t* a, const dbl_t* b, const dbl_t* c, dbl_t* out,
                        std::size_t arows, std::size_t acols, std::size_t bcols)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= arows || col >= bcols)
                return;

            dbl_t x = 0;
            for (std::size_t i = 0; i < acols; ++i)
                x += a[row * acols + i] * b[i * bcols + col];
            out[row * bcols + col] = x + c[col];
        }

        __global__
        void tmat_mat_mul(const dbl_t* a, const dbl_t* b, dbl_t* out,
                          std::size_t acols, std::size_t arows, std::size_t bcols)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= acols || col >= bcols)
                return;

            dbl_t x = 0;
            for (std::size_t i = 0; i < arows; ++i)
                x += a[i * acols + row] * b[i * bcols + col];
            out[row * bcols + col] = x;
        }

        __global__
        void mat_tmat_mul(const dbl_t* a, const dbl_t* b, dbl_t* out,
                          std::size_t arows, std::size_t acols, std::size_t brows)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= arows || col >= brows)
                return;

            dbl_t x = 0;
            for (std::size_t i = 0; i < acols; ++i)
                x += a[row * acols + i] * b[col * acols + i];
            out[row * brows + col] = x;
        }
    }
        

    void kernel_mat_mat_mul(rt::Node* node)
    {
        std::size_t arows = node->len1;
        std::size_t acols = node->len2;
        std::size_t bcols = node->len3;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (arows + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (bcols + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        matmul<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->out1,
                                                       arows, acols, bcols);
    }

    void kernel_mat_rvect_add(rt::Node* node)
    {
        std::size_t rows = node->len1;
        std::size_t cols = node->len2;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (rows + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (cols + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        mvrow_add<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->out1,
                                                          rows, cols);
    }

    void kernel_mat_mul_add(rt::Node* node)
    {
        
        std::size_t arows = node->len1;
        std::size_t acols = node->len2;
        std::size_t bcols = node->len3;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (arows + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (bcols + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        matmul_add<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->in3,
                                                           node->out1,
                                                           arows, acols, bcols);
    }

    void kernel_tmat_mat_mul(rt::Node* node)
    {
        std::size_t acols = node->len1;
        std::size_t arows = node->len2;
        std::size_t bcols = node->len3;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (acols + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (bcols + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        tmat_mat_mul<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->out1,
                                                             acols, arows, bcols);
    }

    void kernel_mat_tmat_mul(rt::Node* node)
    {
        std::size_t arows = node->len1;
        std::size_t acols = node->len2;
        std::size_t brows = node->len3;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (arows + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (brows + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        mat_tmat_mul<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->out1,
                                                             arows, acols, brows);
    }

}

	.file	"tmpxft_0034393f_00000000-6_matmul.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2884:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2884:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z83__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_PfmmmPKfS0_Pfmmm
	.hidden	_Z83__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_PfmmmPKfS0_Pfmmm
	.type	_Z83__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_PfmmmPKfS0_Pfmmm, @function
_Z83__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_PfmmmPKfS0_Pfmmm:
.LFB2906:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_Pfmmm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2906:
	.size	_Z83__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_PfmmmPKfS0_Pfmmm, .-_Z83__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_PfmmmPKfS0_Pfmmm
	.globl	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_Pfmmm
	.hidden	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_Pfmmm
	.type	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_Pfmmm, @function
_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_Pfmmm:
.LFB2907:
	.cfi_startproc
	endbr64
	jmp	_Z83__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_PfmmmPKfS0_Pfmmm
	.cfi_endproc
.LFE2907:
	.size	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_Pfmmm, .-_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_Pfmmm
	.globl	_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE
	.type	_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE, @function
_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE:
.LFB2877:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$1, %esi
	movabsq	$137438953504, %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rdi, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	120(%rdi), %r12
	movq	136(%rdi), %r13
	movq	128(%rdi), %rbp
	leaq	31(%r12), %rax
	shrq	$5, %rax
	movl	%eax, 20(%rsp)
	leaq	31(%r13), %rax
	shrq	$5, %rax
	movl	%eax, 24(%rsp)
	movq	20(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	movq	88(%rbx), %rdx
	movq	72(%rbx), %rsi
	movq	%r13, %r9
	movq	%rbp, %r8
	movq	64(%rbx), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movq	%r12, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z83__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_PfmmmPKfS0_Pfmmm
.L8:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2877:
	.size	_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE, .-_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE
	.globl	_Z85__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_PfmmPKfS0_Pfmm
	.hidden	_Z85__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_PfmmPKfS0_Pfmm
	.type	_Z85__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_PfmmPKfS0_Pfmm, @function
_Z85__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_PfmmPKfS0_Pfmm:
.LFB2908:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_Pfmm(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L11:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2908:
	.size	_Z85__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_PfmmPKfS0_Pfmm, .-_Z85__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_PfmmPKfS0_Pfmm
	.globl	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_Pfmm
	.hidden	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_Pfmm
	.type	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_Pfmm, @function
_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_Pfmm:
.LFB2909:
	.cfi_startproc
	endbr64
	jmp	_Z85__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_PfmmPKfS0_Pfmm
	.cfi_endproc
.LFE2909:
	.size	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_Pfmm, .-_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_Pfmm
	.globl	_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE
	.type	_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE, @function
_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE:
.LFB2878:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	120(%rdi), %rbp
	movq	128(%rdi), %r12
	leaq	31(%rbp), %rax
	shrq	$5, %rax
	movl	%eax, 20(%rsp)
	leaq	31(%r12), %rax
	shrq	$5, %rax
	movl	%eax, 24(%rsp)
	movq	20(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	88(%rbx), %rdx
	movq	72(%rbx), %rsi
	movq	%r12, %r8
	movq	%rbp, %rcx
	movq	64(%rbx), %rdi
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z85__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_PfmmPKfS0_Pfmm
.L16:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2878:
	.size	_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE, .-_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE
	.globl	_Z91__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_PfmmmPKfS0_S0_Pfmmm
	.hidden	_Z91__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_PfmmmPKfS0_S0_Pfmmm
	.type	_Z91__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_PfmmmPKfS0_S0_Pfmmm, @function
_Z91__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_PfmmmPKfS0_S0_Pfmmm:
.LFB2910:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_Pfmmm(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L19:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2910:
	.size	_Z91__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_PfmmmPKfS0_S0_Pfmmm, .-_Z91__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_PfmmmPKfS0_S0_Pfmmm
	.globl	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_Pfmmm
	.hidden	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_Pfmmm
	.type	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_Pfmmm, @function
_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_Pfmmm:
.LFB2911:
	.cfi_startproc
	endbr64
	jmp	_Z91__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_PfmmmPKfS0_S0_Pfmmm
	.cfi_endproc
.LFE2911:
	.size	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_Pfmmm, .-_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_Pfmmm
	.globl	_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE
	.type	_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE, @function
_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE:
.LFB2879:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$1, %esi
	movabsq	$137438953504, %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rdi, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	120(%rdi), %r12
	movq	136(%rdi), %r13
	movq	128(%rdi), %rbp
	leaq	31(%r12), %rax
	shrq	$5, %rax
	movl	%eax, 20(%rsp)
	leaq	31(%r13), %rax
	shrq	$5, %rax
	movl	%eax, 24(%rsp)
	movq	20(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	88(%rbx), %rcx
	movq	80(%rbx), %rdx
	movq	%rbp, %r9
	movq	%r12, %r8
	movq	72(%rbx), %rsi
	movq	64(%rbx), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 88
	pushq	%r13
	.cfi_def_cfa_offset 96
	call	_Z91__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_PfmmmPKfS0_S0_Pfmmm
	popq	%rdx
	.cfi_def_cfa_offset 88
	popq	%rcx
	.cfi_def_cfa_offset 80
.L24:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2879:
	.size	_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE, .-_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE
	.globl	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_PfmmmPKfS0_Pfmmm
	.hidden	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_PfmmmPKfS0_Pfmmm
	.type	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_PfmmmPKfS0_Pfmmm, @function
_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_PfmmmPKfS0_Pfmmm:
.LFB2912:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_Pfmmm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L27:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2912:
	.size	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_PfmmmPKfS0_Pfmmm, .-_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_PfmmmPKfS0_Pfmmm
	.globl	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_Pfmmm
	.hidden	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_Pfmmm
	.type	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_Pfmmm, @function
_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_Pfmmm:
.LFB2913:
	.cfi_startproc
	endbr64
	jmp	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_PfmmmPKfS0_Pfmmm
	.cfi_endproc
.LFE2913:
	.size	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_Pfmmm, .-_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_Pfmmm
	.globl	_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE
	.type	_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE, @function
_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE:
.LFB2880:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$1, %esi
	movabsq	$137438953504, %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rdi, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	120(%rdi), %r12
	movq	136(%rdi), %r13
	movq	128(%rdi), %rbp
	leaq	31(%r12), %rax
	shrq	$5, %rax
	movl	%eax, 20(%rsp)
	leaq	31(%r13), %rax
	shrq	$5, %rax
	movl	%eax, 24(%rsp)
	movq	20(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	88(%rbx), %rdx
	movq	72(%rbx), %rsi
	movq	%r13, %r9
	movq	%rbp, %r8
	movq	64(%rbx), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movq	%r12, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_PfmmmPKfS0_Pfmmm
.L32:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2880:
	.size	_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE, .-_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE
	.globl	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_PfmmmPKfS0_Pfmmm
	.hidden	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_PfmmmPKfS0_Pfmmm
	.type	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_PfmmmPKfS0_Pfmmm, @function
_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_PfmmmPKfS0_Pfmmm:
.LFB2914:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_Pfmmm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L35:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2914:
	.size	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_PfmmmPKfS0_Pfmmm, .-_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_PfmmmPKfS0_Pfmmm
	.globl	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_Pfmmm
	.hidden	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_Pfmmm
	.type	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_Pfmmm, @function
_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_Pfmmm:
.LFB2915:
	.cfi_startproc
	endbr64
	jmp	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_PfmmmPKfS0_Pfmmm
	.cfi_endproc
.LFE2915:
	.size	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_Pfmmm, .-_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_Pfmmm
	.globl	_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE
	.type	_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE, @function
_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE:
.LFB2881:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	$1, %esi
	movabsq	$137438953504, %rdx
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rdi, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	120(%rdi), %r12
	movq	136(%rdi), %r13
	movq	128(%rdi), %rbp
	leaq	31(%r12), %rax
	shrq	$5, %rax
	movl	%eax, 20(%rsp)
	leaq	31(%r13), %rax
	shrq	$5, %rax
	movl	%eax, 24(%rsp)
	movq	20(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	88(%rbx), %rdx
	movq	72(%rbx), %rsi
	movq	%r13, %r9
	movq	%rbp, %r8
	movq	64(%rbx), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movq	%r12, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z90__device_stub__ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_PfmmmPKfS0_Pfmmm
.L40:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2881:
	.size	_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE, .-_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_Pfmmm"
.LC1:
	.string	"_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_Pfmmm"
.LC2:
	.string	"_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_Pfmmm"
.LC3:
	.string	"_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_Pfmm"
.LC4:
	.string	"_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_Pfmmm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2917:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512mat_tmat_mulEPKfS2_Pfmmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf512tmat_mat_mulEPKfS2_Pfmmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf510matmul_addEPKfS2_S2_Pfmmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf59mvrow_addEPKfS2_Pfmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN3gpu41_GLOBAL__N__c0c12259_9_matmul_cu_e893ecf56matmulEPKfS2_Pfmmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2917:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "matmul.hh"
#include "../runtime/node.hh"


namespace gpu
{

    namespace
    {

        __global__
        void matmul(const dbl_t* a, const dbl_t* b, dbl_t* out,
                    std::size_t arows, std::size_t acols, std::size_t bcols)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= arows || col >= bcols)
                return;

            dbl_t x = 0;
            for (std::size_t i = 0; i < acols; ++i)
                x += a[row * acols + i] * b[i * bcols + col];
            out[row * bcols + col] = x;
        }

        __global__
        void mvrow_add(const dbl_t* a, const dbl_t* b, dbl_t* out,
                       std::size_t rows, std::size_t cols)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= rows || col >= cols)
                return;

            out[row * cols + col] = a[row * cols + col] + b[col];
        }

        __global__
        void matmul_add(const dbl_t* a, const dbl_t* b, const dbl_t* c, dbl_t* out,
                        std::size_t arows, std::size_t acols, std::size_t bcols)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= arows || col >= bcols)
                return;

            dbl_t x = 0;
            for (std::size_t i = 0; i < acols; ++i)
                x += a[row * acols + i] * b[i * bcols + col];
            out[row * bcols + col] = x + c[col];
        }

        __global__
        void tmat_mat_mul(const dbl_t* a, const dbl_t* b, dbl_t* out,
                          std::size_t acols, std::size_t arows, std::size_t bcols)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= acols || col >= bcols)
                return;

            dbl_t x = 0;
            for (std::size_t i = 0; i < arows; ++i)
                x += a[i * acols + row] * b[i * bcols + col];
            out[row * bcols + col] = x;
        }

        __global__
        void mat_tmat_mul(const dbl_t* a, const dbl_t* b, dbl_t* out,
                          std::size_t arows, std::size_t acols, std::size_t brows)
        {
            std::size_t row = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t col = blockIdx.y * blockDim.y + threadIdx.y;

            if (row >= arows || col >= brows)
                return;

            dbl_t x = 0;
            for (std::size_t i = 0; i < acols; ++i)
                x += a[row * acols + i] * b[col * acols + i];
            out[row * brows + col] = x;
        }
    }
        

    void kernel_mat_mat_mul(rt::Node* node)
    {
        std::size_t arows = node->len1;
        std::size_t acols = node->len2;
        std::size_t bcols = node->len3;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (arows + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (bcols + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        matmul<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->out1,
                                                       arows, acols, bcols);
    }

    void kernel_mat_rvect_add(rt::Node* node)
    {
        std::size_t rows = node->len1;
        std::size_t cols = node->len2;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (rows + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (cols + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        mvrow_add<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->out1,
                                                          rows, cols);
    }

    void kernel_mat_mul_add(rt::Node* node)
    {
        
        std::size_t arows = node->len1;
        std::size_t acols = node->len2;
        std::size_t bcols = node->len3;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (arows + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (bcols + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        matmul_add<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->in3,
                                                           node->out1,
                                                           arows, acols, bcols);
    }

    void kernel_tmat_mat_mul(rt::Node* node)
    {
        std::size_t acols = node->len1;
        std::size_t arows = node->len2;
        std::size_t bcols = node->len3;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (acols + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (bcols + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        tmat_mat_mul<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->out1,
                                                             acols, arows, bcols);
    }

    void kernel_mat_tmat_mul(rt::Node* node)
    {
        std::size_t arows = node->len1;
        std::size_t acols = node->len2;
        std::size_t brows = node->len3;

        std::size_t block_size = 32;
        dim3 threads_per_block (block_size, block_size);
        std::size_t nb_blocks_x = (arows + block_size - 1) / block_size;
        std::size_t nb_blocks_y = (brows + block_size - 1) / block_size;
        dim3 blocks_per_grid (nb_blocks_x, nb_blocks_y);

        mat_tmat_mul<<<blocks_per_grid, threads_per_block>>>(node->in1, node->in2, node->out1,
                                                             arows, acols, brows);
    }

}

	.text
	.file	"matmul.hip"
	.globl	_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE # -- Begin function _ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE
	.type	_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE,@function
_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE: # @_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %r12
	movq	120(%rdi), %rbx
	movq	128(%rdi), %r14
	movq	136(%rdi), %r15
	leaq	31(%rbx), %rax
	shrq	$5, %rax
	movl	%eax, %eax
	movq	%r15, %rcx
	shlq	$27, %rcx
	movl	$4160749568, %edx               # imm = 0xF8000000
	addq	%rcx, %rdx
	movabsq	$-4294967296, %rdi              # imm = 0xFFFFFFFF00000000
	andq	%rdx, %rdi
	orq	%rax, %rdi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB0_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 48
	movq	64(%r12), %rdi
	movq	72(%r12), %rsi
	movq	88(%r12), %rdx
	movq	%rbx, %rcx
	movq	%r14, %r8
	movq	%r15, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_121__device_stub__matmulEPKfS2_Pfmmm # TAILCALL
.Lfunc_end0:
	.size	_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE, .Lfunc_end0-_ZN3gpu18kernel_mat_mat_mulEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_121__device_stub__matmulEPKfS2_Pfmmm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_121__device_stub__matmulEPKfS2_Pfmmm
_ZN3gpu12_GLOBAL__N_121__device_stub__matmulEPKfS2_Pfmmm: # @_ZN3gpu12_GLOBAL__N_121__device_stub__matmulEPKfS2_Pfmmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN3gpu12_GLOBAL__N_121__device_stub__matmulEPKfS2_Pfmmm, .Lfunc_end1-_ZN3gpu12_GLOBAL__N_121__device_stub__matmulEPKfS2_Pfmmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE # -- Begin function _ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE
	.type	_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE,@function
_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE: # @_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %r15
	movq	120(%rdi), %rbx
	movq	128(%rdi), %r14
	leaq	31(%rbx), %rax
	shrq	$5, %rax
	movl	%eax, %eax
	movq	%r14, %rcx
	shlq	$27, %rcx
	movl	$4160749568, %edx               # imm = 0xF8000000
	addq	%rcx, %rdx
	movabsq	$-4294967296, %rdi              # imm = 0xFFFFFFFF00000000
	andq	%rdx, %rdi
	orq	%rax, %rdi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 32
	movq	64(%r15), %rdi
	movq	72(%r15), %rsi
	movq	88(%r15), %rdx
	movq	%rbx, %rcx
	movq	%r14, %r8
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_124__device_stub__mvrow_addEPKfS2_Pfmm # TAILCALL
.Lfunc_end2:
	.size	_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE, .Lfunc_end2-_ZN3gpu20kernel_mat_rvect_addEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_124__device_stub__mvrow_addEPKfS2_Pfmm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_124__device_stub__mvrow_addEPKfS2_Pfmm
_ZN3gpu12_GLOBAL__N_124__device_stub__mvrow_addEPKfS2_Pfmm: # @_ZN3gpu12_GLOBAL__N_124__device_stub__mvrow_addEPKfS2_Pfmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZN3gpu12_GLOBAL__N_124__device_stub__mvrow_addEPKfS2_Pfmm, .Lfunc_end3-_ZN3gpu12_GLOBAL__N_124__device_stub__mvrow_addEPKfS2_Pfmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE # -- Begin function _ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE
	.type	_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE,@function
_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE: # @_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %r15
	movq	120(%rdi), %rbx
	movq	128(%rdi), %r14
	movq	136(%rdi), %r12
	leaq	31(%rbx), %rax
	shrq	$5, %rax
	movl	%eax, %eax
	movq	%r12, %rcx
	shlq	$27, %rcx
	movl	$4160749568, %edx               # imm = 0xF8000000
	addq	%rcx, %rdx
	movabsq	$-4294967296, %rdi              # imm = 0xFFFFFFFF00000000
	andq	%rdx, %rdi
	orq	%rax, %rdi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	64(%r15), %rdi
	movq	72(%r15), %rsi
	movq	80(%r15), %rdx
	movq	88(%r15), %rcx
	movq	%r12, (%rsp)
	movq	%rbx, %r8
	movq	%r14, %r9
	callq	_ZN3gpu12_GLOBAL__N_125__device_stub__matmul_addEPKfS2_S2_Pfmmm
.LBB4_2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE, .Lfunc_end4-_ZN3gpu18kernel_mat_mul_addEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_125__device_stub__matmul_addEPKfS2_S2_Pfmmm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_125__device_stub__matmul_addEPKfS2_S2_Pfmmm
_ZN3gpu12_GLOBAL__N_125__device_stub__matmul_addEPKfS2_S2_Pfmmm: # @_ZN3gpu12_GLOBAL__N_125__device_stub__matmul_addEPKfS2_S2_Pfmmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZN3gpu12_GLOBAL__N_125__device_stub__matmul_addEPKfS2_S2_Pfmmm, .Lfunc_end5-_ZN3gpu12_GLOBAL__N_125__device_stub__matmul_addEPKfS2_S2_Pfmmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE # -- Begin function _ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE
	.type	_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE,@function
_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE: # @_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %r12
	movq	120(%rdi), %rbx
	movq	128(%rdi), %r14
	movq	136(%rdi), %r15
	leaq	31(%rbx), %rax
	shrq	$5, %rax
	movl	%eax, %eax
	movq	%r15, %rcx
	shlq	$27, %rcx
	movl	$4160749568, %edx               # imm = 0xF8000000
	addq	%rcx, %rdx
	movabsq	$-4294967296, %rdi              # imm = 0xFFFFFFFF00000000
	andq	%rdx, %rdi
	orq	%rax, %rdi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB6_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB6_2:
	.cfi_def_cfa_offset 48
	movq	64(%r12), %rdi
	movq	72(%r12), %rsi
	movq	88(%r12), %rdx
	movq	%rbx, %rcx
	movq	%r14, %r8
	movq	%r15, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_127__device_stub__tmat_mat_mulEPKfS2_Pfmmm # TAILCALL
.Lfunc_end6:
	.size	_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE, .Lfunc_end6-_ZN3gpu19kernel_tmat_mat_mulEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_127__device_stub__tmat_mat_mulEPKfS2_Pfmmm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_127__device_stub__tmat_mat_mulEPKfS2_Pfmmm
_ZN3gpu12_GLOBAL__N_127__device_stub__tmat_mat_mulEPKfS2_Pfmmm: # @_ZN3gpu12_GLOBAL__N_127__device_stub__tmat_mat_mulEPKfS2_Pfmmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_ZN3gpu12_GLOBAL__N_127__device_stub__tmat_mat_mulEPKfS2_Pfmmm, .Lfunc_end7-_ZN3gpu12_GLOBAL__N_127__device_stub__tmat_mat_mulEPKfS2_Pfmmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE # -- Begin function _ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE
	.type	_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE,@function
_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE: # @_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %r12
	movq	120(%rdi), %rbx
	movq	128(%rdi), %r14
	movq	136(%rdi), %r15
	leaq	31(%rbx), %rax
	shrq	$5, %rax
	movl	%eax, %eax
	movq	%r15, %rcx
	shlq	$27, %rcx
	movl	$4160749568, %edx               # imm = 0xF8000000
	addq	%rcx, %rdx
	movabsq	$-4294967296, %rdi              # imm = 0xFFFFFFFF00000000
	andq	%rdx, %rdi
	orq	%rax, %rdi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB8_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB8_2:
	.cfi_def_cfa_offset 48
	movq	64(%r12), %rdi
	movq	72(%r12), %rsi
	movq	88(%r12), %rdx
	movq	%rbx, %rcx
	movq	%r14, %r8
	movq	%r15, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_tmat_mulEPKfS2_Pfmmm # TAILCALL
.Lfunc_end8:
	.size	_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE, .Lfunc_end8-_ZN3gpu19kernel_mat_tmat_mulEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_tmat_mulEPKfS2_Pfmmm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_127__device_stub__mat_tmat_mulEPKfS2_Pfmmm
_ZN3gpu12_GLOBAL__N_127__device_stub__mat_tmat_mulEPKfS2_Pfmmm: # @_ZN3gpu12_GLOBAL__N_127__device_stub__mat_tmat_mulEPKfS2_Pfmmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_tmat_mulEPKfS2_Pfmmm, .Lfunc_end9-_ZN3gpu12_GLOBAL__N_127__device_stub__mat_tmat_mulEPKfS2_Pfmmm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB10_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB10_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end10:
	.size	__hip_module_ctor, .Lfunc_end10-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB11_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB11_2:
	retq
.Lfunc_end11:
	.size	__hip_module_dtor, .Lfunc_end11-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm,@object # @_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm:
	.quad	_ZN3gpu12_GLOBAL__N_121__device_stub__matmulEPKfS2_Pfmmm
	.size	_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm, 8

	.type	_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm,@object # @_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm:
	.quad	_ZN3gpu12_GLOBAL__N_124__device_stub__mvrow_addEPKfS2_Pfmm
	.size	_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm, 8

	.type	_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm,@object # @_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm:
	.quad	_ZN3gpu12_GLOBAL__N_125__device_stub__matmul_addEPKfS2_S2_Pfmmm
	.size	_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm, 8

	.type	_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm,@object # @_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm:
	.quad	_ZN3gpu12_GLOBAL__N_127__device_stub__tmat_mat_mulEPKfS2_Pfmmm
	.size	_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm, 8

	.type	_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm,@object # @_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm:
	.quad	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_tmat_mulEPKfS2_Pfmmm
	.size	_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm"
	.size	.L__unnamed_1, 41

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm"
	.size	.L__unnamed_2, 43

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm"
	.size	.L__unnamed_3, 49

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm"
	.size	.L__unnamed_4, 48

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm"
	.size	.L__unnamed_5, 48

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN3gpu12_GLOBAL__N_121__device_stub__matmulEPKfS2_Pfmmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_124__device_stub__mvrow_addEPKfS2_Pfmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_125__device_stub__matmul_addEPKfS2_S2_Pfmmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_127__device_stub__tmat_mat_mulEPKfS2_Pfmmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_127__device_stub__mat_tmat_mulEPKfS2_Pfmmm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm ; -- Begin function _ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm,@function
_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm: ; @_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s2, 0xffff
	s_lshr_b32 s0, s2, 16
	v_mad_u64_u32 v[0:1], null, s14, s1, v[2:3]
	v_mov_b32_e32 v1, 0
	v_mad_u64_u32 v[2:3], null, s15, s0, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v3, v1
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s0, s[18:19], v[2:3]
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	s_cmp_eq_u64 s[16:17], 0
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_mad_u64_u32 v[3:4], null, v0, s16, 0
	s_lshl_b64 s[0:1], s[18:19], 2
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v0, s17, v[4:5]
	v_mov_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v8, v[5:6], off
	global_load_b32 v9, v[3:4], off
	v_add_co_u32 v3, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, 4
	s_add_u32 s16, s16, -1
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_addc_u32 s17, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[16:17], 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v7, v8, v9
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v7, 0
.LBB0_5:                                ; %Flow55
	v_mad_u64_u32 v[3:4], null, v0, s18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v0, s19, v[4:5]
	v_mov_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v0, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v2, vcc_lo
	global_store_b32 v[0:1], v7, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm,comdat
.Lfunc_end0:
	.size	_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm, .Lfunc_end0-_ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 372
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm ; -- Begin function _ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm,@function
_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm: ; @_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm
; %bb.0:
	s_clause 0x2
	s_load_b32 s12, s[0:1], 0x34
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x20
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s12, 0xffff
	s_lshr_b32 s0, s12, 16
	v_mad_u64_u32 v[2:3], null, s14, s1, v[1:2]
	v_mov_b32_e32 v3, 0
	v_mad_u64_u32 v[0:1], null, s15, s0, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v1, v3
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s0, s[2:3], v[0:1]
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v2, s2, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_mad_u64_u32 v[5:6], null, v2, s3, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	v_mov_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v1, v0
	v_add_co_u32 v0, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm,comdat
.Lfunc_end1:
	.size	_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm, .Lfunc_end1-_ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 252
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm ; -- Begin function _ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm,@function
_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm: ; @_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mov_b32_e32 v1, 0
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
	v_cmp_gt_u64_e64 s2, s[8:9], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_6
; %bb.1:                                ; %.preheader
	s_load_b256 s[12:19], s[0:1], 0x0
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	s_cmp_eq_u64 s[6:7], 0
	s_cbranch_scc1 .LBB2_4
; %bb.2:                                ; %.lr.ph
	v_mad_u64_u32 v[3:4], null, v0, s6, 0
	s_lshl_b64 s[0:1], s[8:9], 2
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v0, s7, v[4:5]
	v_mov_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s14, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v8, v[5:6], off
	global_load_b32 v9, v[3:4], off
	v_add_co_u32 v3, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, 4
	s_add_u32 s6, s6, -1
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_addc_u32 s7, s7, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[6:7], 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v7, v8, v9
	s_cbranch_scc0 .LBB2_3
	s_branch .LBB2_5
.LBB2_4:
	v_mov_b32_e32 v7, 0
.LBB2_5:                                ; %Flow61
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, s16, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v2, vcc_lo
	global_load_b32 v8, v[3:4], off
	v_mad_u64_u32 v[3:4], null, v0, s8, 0
	v_mad_u64_u32 v[5:6], null, v0, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v4, v5
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v7, v8
	global_store_b32 v[0:1], v4, off
.LBB2_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm,comdat
.Lfunc_end2:
	.size	_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm, .Lfunc_end2-_ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm ; -- Begin function _ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm,@function
_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm: ; @_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s2, 0xffff
	s_lshr_b32 s0, s2, 16
	v_mad_u64_u32 v[0:1], null, s14, s1, v[2:3]
	v_mov_b32_e32 v1, 0
	v_mad_u64_u32 v[2:3], null, s15, s0, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v3, v1
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s0, s[18:19], v[2:3]
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB3_6
; %bb.1:                                ; %.preheader
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_cmp_eq_u64 s[16:17], 0
	s_cbranch_scc1 .LBB3_4
; %bb.2:                                ; %.lr.ph.preheader
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[18:19], 2
	s_lshl_b64 s[2:3], s[10:11], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
.LBB3_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v8, v[4:5], off
	global_load_b32 v9, v[6:7], off
	v_add_co_u32 v6, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, s2
	s_add_u32 s16, s16, -1
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_addc_u32 s17, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[16:17], 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v1, v8, v9
	s_cbranch_scc0 .LBB3_3
	s_branch .LBB3_5
.LBB3_4:
	v_mov_b32_e32 v1, 0
.LBB3_5:                                ; %Flow57
	v_mad_u64_u32 v[4:5], null, v0, s18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v0, s19, v[5:6]
	v_mov_b32_e32 v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v0, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v3, vcc_lo
	global_store_b32 v[2:3], v1, off
.LBB3_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm,comdat
.Lfunc_end3:
	.size	_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm, .Lfunc_end3-_ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 348
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm ; -- Begin function _ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm,@function
_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm: ; @_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x20
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s2, 0xffff
	s_lshr_b32 s0, s2, 16
	v_mad_u64_u32 v[2:3], null, s14, s1, v[1:2]
	v_mov_b32_e32 v3, 0
	v_mad_u64_u32 v[0:1], null, s15, s0, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v1, v3
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s0, s[18:19], v[0:1]
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_6
; %bb.1:                                ; %.preheader
	s_cmp_eq_u64 s[16:17], 0
	s_cbranch_scc1 .LBB4_4
; %bb.2:                                ; %.lr.ph
	v_mad_u64_u32 v[3:4], null, v2, s16, 0
	v_mad_u64_u32 v[5:6], null, v0, s16, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v2, s17, v[4:5]
	v_mad_u64_u32 v[8:9], null, v0, s17, v[6:7]
	v_dual_mov_b32 v4, v7 :: v_dual_mov_b32 v7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_mov_b32_e32 v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
.LBB4_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v8, v[3:4], off
	global_load_b32 v9, v[5:6], off
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, 4
	s_add_u32 s16, s16, -1
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_addc_u32 s17, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[16:17], 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v7, v8, v9
	s_cbranch_scc0 .LBB4_3
	s_branch .LBB4_5
.LBB4_4:
	v_mov_b32_e32 v7, 0
.LBB4_5:                                ; %Flow55
	v_mad_u64_u32 v[3:4], null, v2, s18, 0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v2, s19, v[4:5]
	v_mov_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	global_store_b32 v[0:1], v7, off
.LBB4_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm,comdat
.Lfunc_end4:
	.size	_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm, .Lfunc_end4-_ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 404
; NumSgprs: 22
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _ZN3gpu12_GLOBAL__N_16matmulEPKfS2_Pfmmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN3gpu12_GLOBAL__N_19mvrow_addEPKfS2_Pfmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _ZN3gpu12_GLOBAL__N_110matmul_addEPKfS2_S2_Pfmmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _ZN3gpu12_GLOBAL__N_112tmat_mat_mulEPKfS2_Pfmmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _ZN3gpu12_GLOBAL__N_112mat_tmat_mulEPKfS2_Pfmmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
