/*
 ============================================================================
 Name        : binconnected_components.cu
 Author      : Diptanshu, Gaurav
 Version     :
 Copyright   : (c) 2018
 Description : CUDA compute reciprocals
 ============================================================================
 */
#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define SWAP(a, b) {int swp=a; a=b; b=swp;}
#define MAX_HEIGHT 10

int numIterations;

/*
 * */
__global__ void bfs(int *adjList, int *offset, int *inpFrontier, int *outFrontier,
					int *parent, int *visited, int *treeEdges, int *s1, int *s2)
{
    int tid = blockIdx.x * blockDim.x + threadIdx.x;

    if (tid < *s1 && visited[inpFrontier[tid]] == 0) {
    	int v = inpFrontier[tid];	// Current vertex
    	// Put all the unvisited neighbors into outFrontier
    	for (int i = offset[v]; i < offset[v + 1]; i++) {
    		if (!visited[adjList[i]] && atomicCAS(&parent[adjList[i]], -1, v) == -1) {
				int old = atomicAdd(s2, 1);
				outFrontier[old] = adjList[i];
				treeEdges[i] = -1;
    		}
    		else if (adjList[i] == parent[v]) {
				treeEdges[i] = -2;
				// Place the parent as the first element in adjList
				if (i != offset[v]) {
					SWAP(adjList[offset[v]], adjList[i]);
					SWAP(treeEdges[offset[v]], treeEdges[i]);
				}
			}
    		else if (v < adjList[i]) {
    			// Non tree edge, mark only in one direction such that a < b for any non-tree edge a->b.
    			treeEdges[i] = v;
    		}
    		else {
    			treeEdges[i] = -2;
    		}
    	}
    	visited[v] = 1;
    }
}

/*
 *
 * */
__global__ void lca(int *adjList, int *offset, int *parent, int *nonTreeEdges,
                    int *unfinished, int *threadEdge, int *lcaThread, int *auxAdjList,
                    int vertexCount)
{
	int tid = blockIdx.x * blockDim.x + threadIdx.x, i = 0, len1, len2;
	int a = nonTreeEdges[3 * tid];
	int b = nonTreeEdges[3 * tid + 1];
	int eid = nonTreeEdges[3 * tid + 2];
	int path_a[MAX_HEIGHT], path_b[MAX_HEIGHT];

	while (a != 0)
	{
		path_a[i++] = a;
		a = parent[a];
	}
	path_a[i++] = 0;
	len1 = i;
	i = 0;

	while (b != 0)
	{
		path_b[i++] = b;
		b = parent[b];
	}
	path_b[i++] = 0;
	len2 = i;

	i = 0;
	while (i < len1 && i < len2 && path_a[len1 - i - 1] == path_b[len2 - i - 1])
		i++;

	int lcaVertex = path_a[len1 - i];
	//printf("Edge %d: %d %d LCA %d\n", eid, nonTreeEdges[3 * tid], nonTreeEdges[3 * tid + 1], lcaVertex);


	len1 -= i;
	len2 -= i;
	lcaThread[tid] = lcaVertex;


	// Mark the non-tree edge visited
	threadEdge[eid] = tid;

	// Mark the rest of the edges visited and the vertices as part of unfinished traversal
	for (i = 0; i < len1; i++) {
		threadEdge[offset[path_a[i]]] = tid;
		if (i != len1 - 1)
			unfinished[path_a[i]] = 1;
	}


	for (i = 0; i < len2; i++) {
		threadEdge[offset[path_b[i]]] = tid;
		if (i != len2 - 1)
			unfinished[path_b[i]] = 1;
	}

	__syncthreads();

	// Create auxiliary vertex
	// Special case for root vertex
	// As root vertex doesn't have any parent, we don't set its parent.
	if (lcaVertex != 0)
		auxAdjList[2 * lcaVertex] = adjList[offset[lcaVertex]];
	auxAdjList[2 * lcaVertex + 1] = lcaVertex;

}

__global__ void lca1(int *adjList, int *offset, int *parent, int *nonTreeEdges,
                    int *unfinished, int *threadEdge, int *lcaThread, int *auxAdjList,
                    int vertexCount, int edgeCount)
{
	int tid = blockIdx.x * blockDim.x + threadIdx.x, i = 0, len1, len2;
	int a = nonTreeEdges[3 * tid];
	int b = nonTreeEdges[3 * tid + 1];
	if (auxAdjList[2 * a + 1] != -1)
		a += vertexCount;
	if (auxAdjList[2 * b + 1] != -1)
			b += vertexCount;

	int eid = nonTreeEdges[3 * tid + 2];
	int path_a[MAX_HEIGHT], path_b[MAX_HEIGHT];

	while (a != 0)
	{
		path_a[i++] = a;
		if (a < vertexCount && auxAdjList[2 * a + 1] != -1)
			a = vertexCount + a;
		else if (a >= vertexCount)
			a = parent[a - vertexCount];
		else
			a = parent[a];
	}
	path_a[i++] = 0;
	len1 = i;
	i = 0;

	while (b != 0)
	{
		path_b[i++] = b;
		if (b < vertexCount && auxAdjList[2 * b + 1] != -1)
			b = vertexCount + b;
		else if (b >= vertexCount)
			b = parent[b - vertexCount];
		else
			b = parent[b];
	}
	path_b[i++] = 0;
	len2 = i;

	i = 0;
	while (i < len1 && i < len2 && path_a[len1 - i - 1] == path_b[len2 - i - 1])
		i++;

	//int lcaVertex = path_a[len1 - i];
	//printf("Edge %d: %d %d LCA %d\n", eid, nonTreeEdges[3 * tid], nonTreeEdges[3 * tid + 1], lcaVertex);


	len1 -= i;
	len2 -= i;



	// Mark the non-tree edge visited
	threadEdge[eid] = tid;

	for (i = 0; i < len1; i++) {
		if (path_a[i] >= vertexCount) {
			threadEdge[edgeCount + path_a[i] - vertexCount] = tid;

		}
		else {
			threadEdge[offset[path_a[i]]] = tid;
		}
	}


	for (i = 0; i < len2; i++) {
		if (path_b[i] >= vertexCount) {
			threadEdge[edgeCount + path_b[i] - vertexCount] = tid;
		}
		else {
			threadEdge[offset[path_b[i]]] = tid;

		}
	}


}

__global__ void auxGraph(int *adjList, int *offset, int *lcaThread, int vertexCount,
		int *rootLCACount, int *auxAdjList) {
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int lcaVertex = lcaThread[tid];

	if (lcaVertex != 0)
		adjList[offset[lcaVertex]] = vertexCount + lcaVertex;
	else
		atomicAdd(rootLCACount, 1);

	// Update grandParent's child
	int grandParent = auxAdjList[2 * lcaVertex];
	for (int i = offset[grandParent]; i < offset[grandParent + 1]; i++) {
		if (adjList[i] == lcaVertex) {
			adjList[i] = vertexCount + lcaVertex;
			break;
		}
	}

}


__global__ void markArtPoint(int *adjList, int *offset, int *lcaThread, int *artPoint,
							int *unfinished, int *rootLCACount) {
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int lcaVertex = lcaThread[tid];
	bool bridge = false;


	for (int i = offset[lcaVertex]; i < offset[lcaVertex + 1]; i++) {
		if (!unfinished[adjList[i]]) {
			bridge = true;
			break;
		}
	}

	printf("vertex %d rootLCACOUnt %d bridge %d\n", lcaVertex, *rootLCACount, bridge);
	if (lcaVertex != 0 && bridge)
		artPoint[lcaVertex] = 1;
	else if (lcaVertex == 0 && bridge && *rootLCACount > 1)
		artPoint[0] = 1;
}
/*
 * Finds BCC Id for each edge. If an edge was part of the path to an LCA and
 * that LCA happens to be an articulation point, we assign the LCA's vertex ID as BCC id to the edge.
 * Otherwise, we traverse up the tree to find an LCA which is an articulation point.
 */
__global__ void findBCC(int *adjList, int *offset, int *threadEdge, int *lcaThread,
						int *artPoint, int *bccId) {
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int lcaVertex = threadEdge[tid];

	// TODO: Unfinished implementation
	// Note: For each undirected edge b/w a-b, only one direction is marked in the threadEdge
	if (lcaVertex != -1) {
		while (!artPoint[lcaVertex]) {
			//lcaVertex = adjList[offset[lcaVertex]];
		}

		bccId[tid] = lcaVertex;
	}

}

int main(int argc, char **argv)
{
	char* edgeListFile = argv[1];
	FILE *fp;
	fp = fopen(edgeListFile, "r");
	if (fp == NULL) {
		printf("ERROR: File does not exist!\n");
		return 1;
	}

	int vertexCount, edgeCount;
	fscanf(fp, "%d", &vertexCount);
	fscanf(fp, "%d", &edgeCount);
	printf("VertexCount %d\n", vertexCount);
	printf("EdgeCount %d\n", edgeCount);

	// Data structure to represent the graph in CSR format
	int *adjList;		// Concatenated adjacency list
	int *offset;		// Stores offset of each vertex's adjacency list

	size_t adjListSize = edgeCount * sizeof(int);
	size_t offsetSize = (vertexCount + 1) * sizeof(int);
	size_t verticesSize = vertexCount * sizeof(int);

	adjList = (int *)malloc(adjListSize);
	offset = (int *)malloc(offsetSize);

	int edgeCounter = 0, vertexCounter = 0;
	int prevSource, source, dest;
	fscanf(fp, "%d %d", &prevSource, &dest);

	// Convert the graph to CSR format
	while (edgeCounter != edgeCount) {
		while (vertexCounter <= prevSource)			// Includes the vertices with no edges
			offset[vertexCounter++] = edgeCounter;
		adjList[edgeCounter++] = dest;
		while (fscanf(fp, "%d %d", &source, &dest) == 2 && source == prevSource)
			adjList[edgeCounter++] = dest;
		prevSource = source;
	}

	// Mark the sentinel values so that the degree of any vertex i = offset[i + 1] - offset[i]
	while (vertexCounter <= vertexCount)
		offset[vertexCounter++] = edgeCount;


//	printf("Adjacency List\n");
//	for(int i = 0; i < edgeCount; i++) {
//		printf("%d ", adjList[i]);
//	}
//
//	printf("\nOffsets\n");
//	for(int i = 0; i < vertexCount + 1; i++) {
//		printf("%d ", offset[i]);
//	}
//	printf("\n");

	// Initialize other data structure to be used for bfs
	int *inpFrontier, *outFrontier, *visited, *parent, *treeEdges;
	int s1, s2;					// Size of input and output frontiers
	int treeEdgeCount = 0;

	inpFrontier = (int *)calloc(vertexCount, sizeof(int));
	outFrontier = (int *)calloc(vertexCount, sizeof(int));
	visited = (int *)calloc(vertexCount, sizeof(int));
	treeEdges = (int *)calloc(edgeCount, sizeof(int));
	parent = (int *)malloc(verticesSize);
	memset(parent, -1, verticesSize);
	s1 = 1; s2 = 0;
	inpFrontier[0] = 0;	// Inserting source vertex

	// Corresponding device data
	int *d_adjList, *d_offset;
	int *d_inpFrontier, *d_outFrontier, *d_visited, *d_parent, *d_treeEdges;
	int *d_s1, *d_s2;

	cudaMalloc(&d_adjList, adjListSize);
	cudaMalloc(&d_offset, offsetSize);
	cudaMalloc(&d_inpFrontier, verticesSize);
	cudaMalloc(&d_outFrontier, verticesSize);
	cudaMalloc(&d_visited, verticesSize);
	cudaMalloc(&d_treeEdges, edgeCount * sizeof(int));
	cudaMalloc(&d_parent, verticesSize);
	cudaMalloc(&d_s1, sizeof(int));
	cudaMalloc(&d_s2, sizeof(int));

	cudaMemcpy(d_adjList, adjList, adjListSize, cudaMemcpyHostToDevice);
	cudaMemcpy(d_offset, offset, offsetSize, cudaMemcpyHostToDevice);
	cudaMemcpy(d_inpFrontier, inpFrontier, verticesSize, cudaMemcpyHostToDevice);
	cudaMemcpy(d_outFrontier, outFrontier, verticesSize, cudaMemcpyHostToDevice);
	cudaMemcpy(d_visited, visited, verticesSize, cudaMemcpyHostToDevice);
	cudaMemcpy(d_treeEdges, treeEdges, edgeCount * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_parent, parent, verticesSize, cudaMemcpyHostToDevice);
	cudaMemcpy(d_s1, &s1, sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_s2, &s2, sizeof(int), cudaMemcpyHostToDevice);

	// Start the bfs
	bool odd = true;
	int inpQSize = s1;
	numIterations = 0;
	while (inpQSize != 0) {
		dim3 blocksPerGrid ((inpQSize + 1023) / 1024);
		dim3 threadsPerBlock ((inpQSize > 1024) ? 1024 : inpQSize);
		if (odd) {
			bfs<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_inpFrontier, d_outFrontier,
													d_parent, d_visited, d_treeEdges, d_s1, d_s2);
			cudaMemcpy(&inpQSize, d_s2, sizeof(int), cudaMemcpyDeviceToHost);
			s1 = 0;
			cudaMemcpy(d_s1, &s1, sizeof(int), cudaMemcpyHostToDevice);

		}
		else {
			bfs<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_outFrontier, d_inpFrontier,
													d_parent, d_visited, d_treeEdges, d_s2, d_s1);
			cudaMemcpy(&inpQSize, d_s1, sizeof(int), cudaMemcpyDeviceToHost);
			s2 = 0;
			cudaMemcpy(d_s2, &s2, sizeof(int), cudaMemcpyHostToDevice);
		}
		odd = !odd;
		numIterations++;
		treeEdgeCount += inpQSize;
	}

	cudaMemcpy(visited, d_visited, verticesSize, cudaMemcpyDeviceToHost);
	cudaMemcpy(parent, d_parent, verticesSize, cudaMemcpyDeviceToHost);
	cudaMemcpy(treeEdges, d_treeEdges, edgeCount * sizeof(int), cudaMemcpyDeviceToHost);
	cudaMemcpy(adjList, d_adjList, edgeCount * sizeof(int), cudaMemcpyDeviceToHost);



//	printf("Parent array\n");
//	for (int i = 0; i < vertexCount; i++)
//			printf("%d ", parent[i]);
//	printf("\n");
//
//	printf("Adjacency List\n");
//	for(int i = 0; i < edgeCount; i++) {
//		printf("(%d %d) ", i, adjList[i]);
//	}
//	printf("\n");
//
//	for (int i = 0; i < vertexCount; i++) {
//		if (parent[i] != adjList[offset[i]])
//			printf("WRONG %d\n", i);
//	}
//
//	printf("Number of iterations %d \n", numIterations);
//	printf("Visited array\n");
//	for (int i = 0; i < vertexCount; i++)
//		printf("%d ", visited[i]);
//	printf("\n");

//	printf("Tree Edges\n");
//	for (int i = 0; i < edgeCount; i++)
//		printf("%d ", treeEdges[i]);
//	printf("\n");

	int nonTreeEdgeCount = (edgeCount - 2 * treeEdgeCount) / 2;
//	printf("treeEdgecount %d\n", treeEdgeCount);
//	printf("Non-tree edges count %d\n", nonTreeEdgeCount);


	dim3 blocksPerGrid ((nonTreeEdgeCount + 1023) / 1024);
	dim3 threadsPerBlock ((nonTreeEdgeCount > 1024) ? 1024 : nonTreeEdgeCount);

	int threadCount = blocksPerGrid.x * threadsPerBlock.x;

	//printf("ThreadCount = %d\n", threadCount);

	// Data structure to represent non tree edges
	// a b i : edge a->b with edge id i
	int *nonTreeEdges = (int *) calloc(3 * nonTreeEdgeCount, sizeof(int));
	int *lcaThread = (int *) calloc(threadCount, sizeof(int));
	int *threadEdge = (int *) malloc(edgeCount * sizeof(int));
	memset(threadEdge, -1, edgeCount * sizeof(int));
	int *unfinished = (int *) calloc(vertexCount, sizeof(int));
	int *auxAdjList = (int *) malloc(2 * vertexCount * sizeof(int));
	memset(auxAdjList, -1, 2 * vertexCount * sizeof(int));
	int *artPoint = (int *) calloc(vertexCount, sizeof(int));
	int rootLCACount = 0;

	// Populate non tree edges
	for (int i = 0, j = 0; i < edgeCount; i++) {
		if (treeEdges[i] >= 0) {
			nonTreeEdges[j++] = treeEdges[i];
			nonTreeEdges[j++] = adjList[i];
			nonTreeEdges[j++] = i;
		}
	}
	/*
	printf("Non tree edges\n");
	for (int i = 0; i < 3 * nonTreeEdgeCount; i+=3) {
		printf("%d %d %d\n", nonTreeEdges[i], nonTreeEdges[i + 1], nonTreeEdges[i + 2]);
	}*/

	int *d_nonTreeEdges, *d_lcaThread, *d_threadEdge, *d_unfinished, *d_auxAdjList, *d_artPoint, *d_rootLCACount;

	cudaMalloc(&d_nonTreeEdges, 3 * nonTreeEdgeCount * sizeof(int));
	cudaMalloc(&d_lcaThread, threadCount * sizeof(int));
	cudaMalloc(&d_threadEdge, edgeCount * sizeof(int));
	cudaMalloc(&d_unfinished, vertexCount * sizeof(int));
	cudaMalloc(&d_auxAdjList, 2 * vertexCount * sizeof(int));
	cudaMalloc(&d_artPoint, vertexCount * sizeof(int));
	cudaMalloc(&d_rootLCACount, sizeof(int));

	cudaMemcpy(d_nonTreeEdges, nonTreeEdges, 3 * nonTreeEdgeCount * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_lcaThread, lcaThread, threadCount * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_threadEdge, threadEdge, edgeCount * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_unfinished, unfinished, vertexCount * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_auxAdjList, auxAdjList, 2 * vertexCount * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_artPoint, artPoint, vertexCount * sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_rootLCACount, &rootLCACount, sizeof(int), cudaMemcpyHostToDevice);


	lca<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_parent, d_nonTreeEdges,
											d_unfinished, d_threadEdge, d_lcaThread, d_auxAdjList,
											vertexCount);


	auxGraph<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_lcaThread, vertexCount, d_rootLCACount, d_auxAdjList);

	int *threadEdge1 = (int *) malloc((edgeCount + vertexCount) * sizeof(int));
	memset(threadEdge1, -1, (edgeCount + vertexCount) * sizeof(int));

	int *d_threadEdge1;
	cudaMalloc(&d_threadEdge1, (edgeCount + vertexCount) * sizeof(int));
	cudaMemcpy(d_threadEdge1, threadEdge1, (edgeCount + vertexCount) * sizeof(int), cudaMemcpyHostToDevice);

	lca1<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_parent, d_nonTreeEdges,
												d_unfinished, d_threadEdge1, d_lcaThread, d_auxAdjList,
												vertexCount, edgeCount);


	cudaMemcpy(threadEdge1, d_threadEdge1, (edgeCount + vertexCount) * sizeof(int), cudaMemcpyDeviceToHost);

	cudaMemcpy(lcaThread, d_lcaThread, threadCount * sizeof(int), cudaMemcpyDeviceToHost);
	cudaMemcpy(threadEdge, d_threadEdge, edgeCount * sizeof(int), cudaMemcpyDeviceToHost);

	cudaMemcpy(unfinished, d_unfinished, vertexCount * sizeof(int), cudaMemcpyDeviceToHost);
	cudaMemcpy(adjList, d_adjList, edgeCount * sizeof(int), cudaMemcpyDeviceToHost);
	cudaMemcpy(auxAdjList, d_auxAdjList, 2 * vertexCount * sizeof(int), cudaMemcpyDeviceToHost);
	cudaMemcpy(artPoint, d_artPoint, vertexCount * sizeof(int), cudaMemcpyDeviceToHost);

/*
	printf("LCA Thread\n");
	for (int i = 0; i < threadCount; i++)
		printf("%d ", lcaThread[i]);

	printf("\nthread Edge\n");
	for (int i = 0; i < edgeCount; i++)
		printf("%d ", threadEdge[i]);

	printf("\n unfinished \n");
	for (int i = 0; i < vertexCount; i++)
		printf("%d ", unfinished[i]);

	printf("\n Adj List\n");
	for (int i = 0; i < edgeCount; i++)
		printf("%d ", adjList[i]);

	printf("\n Aux Adj List \n");
	for (int i = 0; i < 2 * vertexCount; i+=2)
		printf("%d %d\n", auxAdjList[i], auxAdjList[i + 1]);


	printf("\n Art Point \n");
	for (int i = 0; i < vertexCount; i++)
		printf("%d %d\n", i, artPoint[i]);


	printf("\n THREAD EDGE\n");
	for (int i = 0; i < (edgeCount + vertexCount); i++)
		printf("%d ", threadEdge1[i]);

*/
	printf("\n");
	for (int i = 0; i < threadCount; i++) {
		if (threadEdge1[offset[lcaThread[i]]] == -1)
			printf("%d ", lcaThread[i]);
	}
	printf("\n");

	// Free allocated memory on device and host
	cudaFree(d_adjList);
	cudaFree(d_offset);
	cudaFree(d_inpFrontier);
	cudaFree(d_outFrontier);
	cudaFree(d_visited);
	cudaFree(d_treeEdges);
	cudaFree(d_parent);
	cudaFree(d_s1);
	cudaFree(d_s2);
	cudaFree(d_nonTreeEdges);
	cudaFree(d_lcaThread);
	cudaFree(d_threadEdge);
	cudaFree(d_unfinished);
	cudaFree(d_artPoint);
	cudaFree(d_rootLCACount);

	free(inpFrontier);
	free(outFrontier);
	free(visited);
	free(treeEdges);
	free(parent);
	free(nonTreeEdges);
	free(lcaThread);
	free(threadEdge);
	free(unfinished);
	free(artPoint);

    return 0;
}

	.file	"tmpxft_003169bb_00000000-6_binconnected_components.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0:
.LFB2182:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2182:
	.size	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	.globl	_Z38__device_stub__Z3bfsPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_
	.type	_Z38__device_stub__Z3bfsPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_, @function
_Z38__device_stub__Z3bfsPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	256(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z3bfsPiS_S_S_S_S_S_S_S_(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L3:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z38__device_stub__Z3bfsPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_, .-_Z38__device_stub__Z3bfsPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_
	.globl	_Z3bfsPiS_S_S_S_S_S_S_S_
	.type	_Z3bfsPiS_S_S_S_S_S_S_S_, @function
_Z3bfsPiS_S_S_S_S_S_S_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z3bfsPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2053:
	.size	_Z3bfsPiS_S_S_S_S_S_S_S_, .-_Z3bfsPiS_S_S_S_S_S_S_S_
	.globl	_Z37__device_stub__Z3lcaPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_i
	.type	_Z37__device_stub__Z3lcaPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_i, @function
_Z37__device_stub__Z3lcaPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movq	%rsp, %rax
	movq	%rax, 184(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z3lcaPiS_S_S_S_S_S_S_i(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L9:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z37__device_stub__Z3lcaPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_i, .-_Z37__device_stub__Z3lcaPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_i
	.globl	_Z3lcaPiS_S_S_S_S_S_S_i
	.type	_Z3lcaPiS_S_S_S_S_S_S_i, @function
_Z3lcaPiS_S_S_S_S_S_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z3lcaPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_i
	.cfi_endproc
.LFE2055:
	.size	_Z3lcaPiS_S_S_S_S_S_S_i, .-_Z3lcaPiS_S_S_S_S_S_S_i
	.globl	_Z39__device_stub__Z4lca1PiS_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_ii
	.type	_Z39__device_stub__Z4lca1PiS_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_ii, @function
_Z39__device_stub__Z4lca1PiS_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z4lca1PiS_S_S_S_S_S_S_ii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L14:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z39__device_stub__Z4lca1PiS_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_ii, .-_Z39__device_stub__Z4lca1PiS_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_ii
	.globl	_Z4lca1PiS_S_S_S_S_S_S_ii
	.type	_Z4lca1PiS_S_S_S_S_S_S_ii, @function
_Z4lca1PiS_S_S_S_S_S_S_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z4lca1PiS_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_ii
	.cfi_endproc
.LFE2057:
	.size	_Z4lca1PiS_S_S_S_S_S_S_ii, .-_Z4lca1PiS_S_S_S_S_S_S_ii
	.globl	_Z36__device_stub__Z8auxGraphPiS_S_iS_S_PiS_S_iS_S_
	.type	_Z36__device_stub__Z8auxGraphPiS_S_iS_S_PiS_S_iS_S_, @function
_Z36__device_stub__Z8auxGraphPiS_S_iS_S_PiS_S_iS_S_:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z8auxGraphPiS_S_iS_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L19:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z36__device_stub__Z8auxGraphPiS_S_iS_S_PiS_S_iS_S_, .-_Z36__device_stub__Z8auxGraphPiS_S_iS_S_PiS_S_iS_S_
	.globl	_Z8auxGraphPiS_S_iS_S_
	.type	_Z8auxGraphPiS_S_iS_S_, @function
_Z8auxGraphPiS_S_iS_S_:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z8auxGraphPiS_S_iS_S_PiS_S_iS_S_
	.cfi_endproc
.LFE2059:
	.size	_Z8auxGraphPiS_S_iS_S_, .-_Z8auxGraphPiS_S_iS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"ERROR: File does not exist!\n"
.LC2:
	.string	"%d"
.LC3:
	.string	"VertexCount %d\n"
.LC4:
	.string	"EdgeCount %d\n"
.LC5:
	.string	"%d %d"
.LC6:
	.string	"\n"
.LC7:
	.string	"%d "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$328, %rsp
	.cfi_def_cfa_offset 384
	movq	8(%rsi), %rdi
	leaq	.LC0(%rip), %rsi
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	testq	%rax, %rax
	jne	.L25
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movl	$1, %ebp
	call	__printf_chk@PLT
	jmp	.L24
.L25:
	leaq	.LC2(%rip), %rbx
	movq	%rax, %rbp
	leaq	116(%rsp), %rdx
	movq	%rax, %rdi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	leaq	132(%rsp), %r13
	call	__isoc23_fscanf@PLT
	movq	%rbx, %rsi
	leaq	120(%rsp), %rdx
	movq	%rbp, %rdi
	xorl	%eax, %eax
	leaq	.LC5(%rip), %r14
	call	__isoc23_fscanf@PLT
	movl	116(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rsi
	call	__printf_chk@PLT
	movl	120(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC4(%rip), %rsi
	call	__printf_chk@PLT
	movslq	120(%rsp), %r12
	leaq	0(,%r12,4), %rax
	xorl	%r12d, %r12d
	movq	%rax, 32(%rsp)
	movl	116(%rsp), %eax
	movq	32(%rsp), %rdi
	leal	1(%rax), %ebx
	movslq	%ebx, %rbx
	salq	$2, %rbx
	leaq	-4(%rbx), %rax
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r15
	call	malloc@PLT
	leaq	124(%rsp), %rdx
	movq	%r13, %rcx
	movq	%r14, %rsi
	movq	%rax, 8(%rsp)
	movq	%rbp, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	leaq	128(%rsp), %rax
	xorl	%r8d, %r8d
	movq	%rax, 16(%rsp)
.L27:
	cmpl	%r12d, 120(%rsp)
	movslq	%r8d, %r8
	je	.L31
	movl	124(%rsp), %eax
.L32:
	cmpl	%r8d, %eax
	jl	.L53
	movq	8(%rsp), %rcx
	movl	%r12d, (%rcx,%r8,4)
	incq	%r8
	jmp	.L32
.L53:
	movl	132(%rsp), %ecx
	movslq	%r12d, %rax
	leal	1(%r12), %edx
	movslq	%edx, %r12
	movl	%ecx, (%r15,%rax,4)
.L30:
	movq	16(%rsp), %rdx
	xorl	%eax, %eax
	movq	%r13, %rcx
	movq	%r14, %rsi
	movq	%rbp, %rdi
	movq	%r8, 24(%rsp)
	call	__isoc23_fscanf@PLT
	movq	24(%rsp), %r8
	cmpl	$2, %eax
	movl	128(%rsp), %eax
	jne	.L29
	cmpl	124(%rsp), %eax
	jne	.L29
	movl	132(%rsp), %eax
	movl	%eax, (%r15,%r12,4)
	incq	%r12
	jmp	.L30
.L29:
	movl	%eax, 124(%rsp)
	jmp	.L27
.L31:
	movslq	116(%rsp), %rbp
.L33:
	cmpl	%r8d, %ebp
	jl	.L54
	movq	8(%rsp), %rax
	movl	%r12d, (%rax,%r8,4)
	incq	%r8
	jmp	.L33
.L54:
	movl	$4, %esi
	movq	%rbp, %rdi
	movabsq	$4294967297, %r13
	call	calloc@PLT
	movl	$4, %esi
	movq	%rbp, %rdi
	movq	%rax, 48(%rsp)
	call	calloc@PLT
	movl	$4, %esi
	movq	%rbp, %rdi
	movq	%rax, 80(%rsp)
	call	calloc@PLT
	movslq	%r12d, %rdi
	movl	$4, %esi
	movb	$1, %r12b
	movq	%rax, 56(%rsp)
	call	calloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movq	(%rsp), %rcx
	orl	$-1, %esi
	movq	%rax, %rdi
	movq	%rax, 24(%rsp)
	movq	%rcx, %rdx
	call	__memset_chk@PLT
	movq	48(%rsp), %rax
	xorl	%r10d, %r10d
	xorl	%r9d, %r9d
	movq	32(%rsp), %rsi
	leaq	152(%rsp), %rdi
	movl	%r9d, 140(%rsp)
	movl	%r10d, (%rax)
	movl	$1, 136(%rsp)
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	%rbx, %rsi
	leaq	160(%rsp), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	(%rsp), %rsi
	leaq	168(%rsp), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	(%rsp), %rsi
	leaq	176(%rsp), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	(%rsp), %rsi
	leaq	184(%rsp), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movslq	120(%rsp), %rsi
	leaq	200(%rsp), %rdi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	(%rsp), %rsi
	leaq	192(%rsp), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	208(%rsp), %rdi
	movl	$4, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	216(%rsp), %rdi
	movl	$4, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	32(%rsp), %rdx
	movl	$1, %ecx
	movq	%r15, %rsi
	movq	152(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	movq	%rbx, %rdx
	movq	160(%rsp), %rdi
	movl	$1, %ecx
	xorl	%ebx, %ebx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	168(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	$1, %ecx
	movq	176(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$1, %ecx
	movq	184(%rsp), %rdi
	call	cudaMemcpy@PLT
	movslq	120(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	200(%rsp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	192(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$4, %edx
	movq	208(%rsp), %rdi
	leaq	136(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$4, %edx
	movq	216(%rsp), %rdi
	leaq	140(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	136(%rsp), %eax
	xorl	%r11d, %r11d
	movl	%r11d, numIterations(%rip)
	movl	%eax, 144(%rsp)
.L35:
	movl	144(%rsp), %ebp
	testl	%ebp, %ebp
	je	.L55
	leal	1023(%rbp), %eax
	movl	$1024, %ecx
	movq	%r13, 292(%rsp)
	movl	296(%rsp), %esi
	cltd
	movq	%r13, 304(%rsp)
	idivl	%ecx
	movl	308(%rsp), %ecx
	movl	%eax, 288(%rsp)
	movl	$1024, %eax
	movq	288(%rsp), %rdi
	cmpl	%eax, %ebp
	cmovle	%ebp, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	testb	%r12b, %r12b
	movl	%eax, 300(%rsp)
	movq	300(%rsp), %rdx
	je	.L36
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	pushq	%r8
	.cfi_def_cfa_offset 392
	pushq	224(%rsp)
	.cfi_def_cfa_offset 400
	pushq	224(%rsp)
	.cfi_def_cfa_offset 408
	pushq	224(%rsp)
	.cfi_def_cfa_offset 416
	movq	216(%rsp), %r9
	movq	224(%rsp), %r8
	movq	208(%rsp), %rcx
	movq	200(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	184(%rsp), %rdi
	call	_Z38__device_stub__Z3bfsPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 384
.L37:
	movq	216(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	leaq	144(%rsp), %rdi
	call	cudaMemcpy@PLT
	xorl	%edi, %edi
	movl	$1, %ecx
	leaq	136(%rsp), %rsi
	movl	%edi, 136(%rsp)
	movl	$4, %edx
	movq	208(%rsp), %rdi
	jmp	.L52
.L36:
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	%rsi
	.cfi_def_cfa_offset 392
	pushq	216(%rsp)
	.cfi_def_cfa_offset 400
	pushq	232(%rsp)
	.cfi_def_cfa_offset 408
	pushq	224(%rsp)
	.cfi_def_cfa_offset 416
	movq	216(%rsp), %r9
	movq	224(%rsp), %r8
	movq	200(%rsp), %rcx
	movq	208(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	184(%rsp), %rdi
	call	_Z38__device_stub__Z3bfsPiS_S_S_S_S_S_S_S_PiS_S_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 384
.L39:
	movq	208(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	leaq	144(%rsp), %rdi
	call	cudaMemcpy@PLT
	xorl	%ecx, %ecx
	movl	$4, %edx
	movq	216(%rsp), %rdi
	movl	%ecx, 140(%rsp)
	leaq	140(%rsp), %rsi
	movl	$1, %ecx
.L52:
	call	cudaMemcpy@PLT
	xorl	$1, %r12d
	incl	numIterations(%rip)
	addl	144(%rsp), %ebx
	jmp	.L35
.L55:
	movq	(%rsp), %rdx
	movq	56(%rsp), %rdi
	movl	$2, %ecx
	addl	%ebx, %ebx
	movq	184(%rsp), %rsi
	movl	$1024, %r12d
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movq	192(%rsp), %rsi
	call	cudaMemcpy@PLT
	movslq	120(%rsp), %rdx
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movq	200(%rsp), %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	120(%rsp), %rdx
	movl	$2, %ecx
	movq	%r15, %rdi
	movq	152(%rsp), %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	120(%rsp), %r14
	movl	$2, %ecx
	movl	$4, %esi
	movl	$1, 292(%rsp)
	movl	$1, 296(%rsp)
	movl	%r14d, %eax
	movl	$1, 304(%rsp)
	subl	%ebx, %eax
	movl	$1, 308(%rsp)
	cltd
	idivl	%ecx
	movl	$1024, %ecx
	movl	%eax, %ebx
	leal	1023(%rax), %eax
	cltd
	idivl	%ecx
	cmpl	%r12d, %ebx
	cmovle	%ebx, %r12d
	leal	(%rbx,%rbx,2), %ebx
	salq	$2, %r14
	movslq	%ebx, %rbx
	movq	%rbx, %rdi
	movl	%eax, 92(%rsp)
	imull	%r12d, %eax
	movl	%eax, 88(%rsp)
	call	calloc@PLT
	movl	$4, %esi
	movq	%rax, %r13
	movslq	88(%rsp), %rax
	movq	%rax, %rdi
	movq	%rax, 40(%rsp)
	call	calloc@PLT
	movq	%r14, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	%r14, %rcx
	movq	%r14, %rdx
	orl	$-1, %esi
	movq	%rax, %rdi
	movq	%rax, 32(%rsp)
	call	__memset_chk@PLT
	movslq	116(%rsp), %rax
	movl	$4, %esi
	movq	%rax, %r14
	movq	%rax, %rdi
	movq	%rax, 96(%rsp)
	call	calloc@PLT
	leal	(%r14,%r14), %edx
	movslq	%edx, %rdx
	movq	%rax, 64(%rsp)
	salq	$2, %rdx
	movq	%rdx, %rdi
	movq	%rdx, 104(%rsp)
	call	malloc@PLT
	movq	104(%rsp), %rdx
	orl	$-1, %esi
	movq	%rax, %rdi
	movq	%rax, 72(%rsp)
	movq	%rdx, %rcx
	call	__memset_chk@PLT
	movq	96(%rsp), %rdi
	movl	$4, %esi
	call	calloc@PLT
	xorl	%edx, %edx
	movl	%edx, 148(%rsp)
	movq	%rax, %r14
	xorl	%edx, %edx
	xorl	%eax, %eax
.L41:
	cmpl	%eax, 120(%rsp)
	jle	.L56
	movq	16(%rsp), %rcx
	movl	(%rcx,%rax,4), %edi
	testl	%edi, %edi
	js	.L42
	movslq	%edx, %rsi
	addl	$3, %edx
	movl	%edi, 0(%r13,%rsi,4)
	leaq	0(,%rsi,4), %rcx
	movl	(%r15,%rax,4), %esi
	movl	%eax, 8(%r13,%rcx)
	movl	%esi, 4(%r13,%rcx)
.L42:
	incq	%rax
	jmp	.L41
.L56:
	salq	$2, %rbx
	leaq	224(%rsp), %rdi
	movq	%rbx, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	40(%rsp), %rax
	leaq	232(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 40(%rsp)
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movslq	120(%rsp), %rsi
	leaq	240(%rsp), %rdi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movslq	116(%rsp), %rsi
	leaq	248(%rsp), %rdi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	116(%rsp), %eax
	leaq	256(%rsp), %rdi
	leal	(%rax,%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movslq	116(%rsp), %rsi
	leaq	264(%rsp), %rdi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	272(%rsp), %rdi
	movl	$4, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	$1, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movq	224(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdx
	movq	(%rsp), %rsi
	movl	$1, %ecx
	movq	232(%rsp), %rdi
	call	cudaMemcpy@PLT
	movslq	120(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	240(%rsp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	116(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$1, %ecx
	movq	248(%rsp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	116(%rsp), %eax
	movq	72(%rsp), %rsi
	movl	$1, %ecx
	movq	256(%rsp), %rdi
	leal	(%rax,%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	116(%rsp), %rdx
	movl	$1, %ecx
	movq	%r14, %rsi
	movq	264(%rsp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$4, %edx
	movq	272(%rsp), %rdi
	leaq	148(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	92(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%r12d, 300(%rsp)
	movl	308(%rsp), %ecx
	movl	%eax, 288(%rsp)
	movq	300(%rsp), %rdx
	movq	288(%rsp), %rdi
	movl	296(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	%rax
	.cfi_def_cfa_offset 392
	movl	124(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 400
	pushq	272(%rsp)
	.cfi_def_cfa_offset 408
	pushq	256(%rsp)
	.cfi_def_cfa_offset 416
	movq	272(%rsp), %r9
	movq	280(%rsp), %r8
	movq	256(%rsp), %rcx
	movq	224(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	184(%rsp), %rdi
	call	_Z37__device_stub__Z3lcaPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_i
	addq	$32, %rsp
	.cfi_def_cfa_offset 384
.L44:
	movl	308(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	300(%rsp), %rdx
	movq	288(%rsp), %rdi
	movl	296(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	movq	256(%rsp), %r9
	movq	272(%rsp), %r8
	movl	116(%rsp), %ecx
	movq	232(%rsp), %rdx
	movq	160(%rsp), %rsi
	movq	152(%rsp), %rdi
	call	_Z36__device_stub__Z8auxGraphPiS_S_iS_S_PiS_S_iS_S_
.L45:
	movl	116(%rsp), %ebx
	addl	120(%rsp), %ebx
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rcx
	movq	%rbx, %rdx
	orl	$-1, %esi
	movq	%rax, %rdi
	movq	%rax, %r12
	call	__memset_chk@PLT
	leaq	280(%rsp), %rdi
	movq	%rbx, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	116(%rsp), %edx
	addl	120(%rsp), %edx
	movq	%r12, %rsi
	movq	280(%rsp), %rdi
	movslq	%edx, %rdx
	movl	$1, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	308(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	300(%rsp), %rdx
	movq	288(%rsp), %rdi
	movl	296(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	movl	120(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 392
	movl	124(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 400
	pushq	272(%rsp)
	.cfi_def_cfa_offset 408
	pushq	256(%rsp)
	.cfi_def_cfa_offset 416
	movq	312(%rsp), %r9
	movq	280(%rsp), %r8
	movq	256(%rsp), %rcx
	movq	224(%rsp), %rdx
	movq	192(%rsp), %rsi
	movq	184(%rsp), %rdi
	call	_Z39__device_stub__Z4lca1PiS_S_S_S_S_S_S_iiPiS_S_S_S_S_S_S_ii
	addq	$32, %rsp
	.cfi_def_cfa_offset 384
.L46:
	movl	116(%rsp), %edx
	addl	120(%rsp), %edx
	movl	$2, %ecx
	movq	%r12, %rdi
	movq	280(%rsp), %rsi
	movslq	%edx, %rdx
	leaq	.LC6(%rip), %rbx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdx
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movq	232(%rsp), %rsi
	call	cudaMemcpy@PLT
	movslq	120(%rsp), %rdx
	movq	32(%rsp), %rdi
	movl	$2, %ecx
	movq	240(%rsp), %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	116(%rsp), %rdx
	movq	64(%rsp), %rdi
	movl	$2, %ecx
	movq	248(%rsp), %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	120(%rsp), %rdx
	movq	%r15, %rdi
	movq	152(%rsp), %rsi
	movl	$2, %ecx
	xorl	%r15d, %r15d
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	116(%rsp), %eax
	movq	72(%rsp), %rdi
	movl	$2, %ecx
	movq	256(%rsp), %rsi
	leal	(%rax,%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	116(%rsp), %rdx
	movl	$2, %ecx
	movq	%r14, %rdi
	movq	264(%rsp), %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L47:
	cmpl	%r15d, 88(%rsp)
	jle	.L57
	movq	(%rsp), %rax
	movq	8(%rsp), %rcx
	movslq	(%rax,%r15,4), %rax
	movq	%rax, %rdx
	movslq	(%rcx,%rax,4), %rax
	cmpl	$-1, (%r12,%rax,4)
	jne	.L48
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L48:
	incq	%r15
	jmp	.L47
.L57:
	movq	%rbx, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rdi
	call	cudaFree@PLT
	movq	176(%rsp), %rdi
	call	cudaFree@PLT
	movq	184(%rsp), %rdi
	call	cudaFree@PLT
	movq	200(%rsp), %rdi
	call	cudaFree@PLT
	movq	192(%rsp), %rdi
	call	cudaFree@PLT
	movq	208(%rsp), %rdi
	call	cudaFree@PLT
	movq	216(%rsp), %rdi
	call	cudaFree@PLT
	movq	224(%rsp), %rdi
	call	cudaFree@PLT
	movq	232(%rsp), %rdi
	call	cudaFree@PLT
	movq	240(%rsp), %rdi
	call	cudaFree@PLT
	movq	248(%rsp), %rdi
	call	cudaFree@PLT
	movq	264(%rsp), %rdi
	call	cudaFree@PLT
	movq	272(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	free@PLT
	movq	80(%rsp), %rdi
	call	free@PLT
	movq	56(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	free@PLT
	movq	64(%rsp), %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
.L24:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$328, %rsp
	.cfi_def_cfa_offset 56
	movl	%ebp, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.text
	.globl	_Z42__device_stub__Z12markArtPointPiS_S_S_S_S_PiS_S_S_S_S_
	.type	_Z42__device_stub__Z12markArtPointPiS_S_S_S_S_PiS_S_S_S_S_, @function
_Z42__device_stub__Z12markArtPointPiS_S_S_S_S_PiS_S_S_S_S_:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L58
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12markArtPointPiS_S_S_S_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L58:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L60
	call	__stack_chk_fail@PLT
.L60:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z42__device_stub__Z12markArtPointPiS_S_S_S_S_PiS_S_S_S_S_, .-_Z42__device_stub__Z12markArtPointPiS_S_S_S_S_PiS_S_S_S_S_
	.globl	_Z12markArtPointPiS_S_S_S_S_
	.type	_Z12markArtPointPiS_S_S_S_S_, @function
_Z12markArtPointPiS_S_S_S_S_:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z12markArtPointPiS_S_S_S_S_PiS_S_S_S_S_
	.cfi_endproc
.LFE2061:
	.size	_Z12markArtPointPiS_S_S_S_S_, .-_Z12markArtPointPiS_S_S_S_S_
	.globl	_Z36__device_stub__Z7findBCCPiS_S_S_S_S_PiS_S_S_S_S_
	.type	_Z36__device_stub__Z7findBCCPiS_S_S_S_S_PiS_S_S_S_S_, @function
_Z36__device_stub__Z7findBCCPiS_S_S_S_S_PiS_S_S_S_S_:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L63
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7findBCCPiS_S_S_S_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L63:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L65
	call	__stack_chk_fail@PLT
.L65:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z36__device_stub__Z7findBCCPiS_S_S_S_S_PiS_S_S_S_S_, .-_Z36__device_stub__Z7findBCCPiS_S_S_S_S_PiS_S_S_S_S_
	.globl	_Z7findBCCPiS_S_S_S_S_
	.type	_Z7findBCCPiS_S_S_S_S_, @function
_Z7findBCCPiS_S_S_S_S_:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z7findBCCPiS_S_S_S_S_PiS_S_S_S_S_
	.cfi_endproc
.LFE2063:
	.size	_Z7findBCCPiS_S_S_S_S_, .-_Z7findBCCPiS_S_S_S_S_
	.section	.rodata.str1.1
.LC8:
	.string	"_Z7findBCCPiS_S_S_S_S_"
.LC9:
	.string	"_Z12markArtPointPiS_S_S_S_S_"
.LC10:
	.string	"_Z8auxGraphPiS_S_iS_S_"
.LC11:
	.string	"_Z4lca1PiS_S_S_S_S_S_S_ii"
.LC12:
	.string	"_Z3lcaPiS_S_S_S_S_S_S_i"
.LC13:
	.string	"_Z3bfsPiS_S_S_S_S_S_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7findBCCPiS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12markArtPointPiS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8auxGraphPiS_S_iS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z4lca1PiS_S_S_S_S_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3lcaPiS_S_S_S_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3bfsPiS_S_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2065:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	numIterations
	.bss
	.align 4
	.type	numIterations, @object
	.size	numIterations, 4
numIterations:
	.zero	4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 ============================================================================
 Name        : binconnected_components.cu
 Author      : Diptanshu, Gaurav
 Version     :
 Copyright   : (c) 2018
 Description : CUDA compute reciprocals
 ============================================================================
 */

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>

#define SWAP(a, b) {int swp=a; a=b; b=swp;}
#define MAX_HEIGHT 10

int numIterations;

/*
 * */
__global__ void bfs(int *adjList, int *offset, int *inpFrontier, int *outFrontier,
					int *parent, int *visited, int *treeEdges, int *s1, int *s2)
{
    int tid = blockIdx.x * blockDim.x + threadIdx.x;

    if (tid < *s1 && visited[inpFrontier[tid]] == 0) {
    	int v = inpFrontier[tid];	// Current vertex
    	// Put all the unvisited neighbors into outFrontier
    	for (int i = offset[v]; i < offset[v + 1]; i++) {
    		if (!visited[adjList[i]] && atomicCAS(&parent[adjList[i]], -1, v) == -1) {
				int old = atomicAdd(s2, 1);
				outFrontier[old] = adjList[i];
				treeEdges[i] = -1;
    		}
    		else if (adjList[i] == parent[v]) {
				treeEdges[i] = -2;
				// Place the parent as the first element in adjList
				if (i != offset[v]) {
					SWAP(adjList[offset[v]], adjList[i]);
					SWAP(treeEdges[offset[v]], treeEdges[i]);
				}
			}
    		else if (v < adjList[i]) {
    			// Non tree edge, mark only in one direction such that a < b for any non-tree edge a->b.
    			treeEdges[i] = v;
    		}
    		else {
    			treeEdges[i] = -2;
    		}
    	}
    	visited[v] = 1;
    }
}

/*
 *
 * */
__global__ void lca(int *adjList, int *offset, int *parent, int *nonTreeEdges,
                    int *unfinished, int *threadEdge, int *lcaThread, int *auxAdjList,
                    int vertexCount)
{
	int tid = blockIdx.x * blockDim.x + threadIdx.x, i = 0, len1, len2;
	int a = nonTreeEdges[3 * tid];
	int b = nonTreeEdges[3 * tid + 1];
	int eid = nonTreeEdges[3 * tid + 2];
	int path_a[MAX_HEIGHT], path_b[MAX_HEIGHT];

	while (a != 0)
	{
		path_a[i++] = a;
		a = parent[a];
	}
	path_a[i++] = 0;
	len1 = i;
	i = 0;

	while (b != 0)
	{
		path_b[i++] = b;
		b = parent[b];
	}
	path_b[i++] = 0;
	len2 = i;

	i = 0;
	while (i < len1 && i < len2 && path_a[len1 - i - 1] == path_b[len2 - i - 1])
		i++;

	int lcaVertex = path_a[len1 - i];
	//printf("Edge %d: %d %d LCA %d\n", eid, nonTreeEdges[3 * tid], nonTreeEdges[3 * tid + 1], lcaVertex);


	len1 -= i;
	len2 -= i;
	lcaThread[tid] = lcaVertex;


	// Mark the non-tree edge visited
	threadEdge[eid] = tid;

	// Mark the rest of the edges visited and the vertices as part of unfinished traversal
	for (i = 0; i < len1; i++) {
		threadEdge[offset[path_a[i]]] = tid;
		if (i != len1 - 1)
			unfinished[path_a[i]] = 1;
	}


	for (i = 0; i < len2; i++) {
		threadEdge[offset[path_b[i]]] = tid;
		if (i != len2 - 1)
			unfinished[path_b[i]] = 1;
	}

	__syncthreads();

	// Create auxiliary vertex
	// Special case for root vertex
	// As root vertex doesn't have any parent, we don't set its parent.
	if (lcaVertex != 0)
		auxAdjList[2 * lcaVertex] = adjList[offset[lcaVertex]];
	auxAdjList[2 * lcaVertex + 1] = lcaVertex;

}

__global__ void lca1(int *adjList, int *offset, int *parent, int *nonTreeEdges,
                    int *unfinished, int *threadEdge, int *lcaThread, int *auxAdjList,
                    int vertexCount, int edgeCount)
{
	int tid = blockIdx.x * blockDim.x + threadIdx.x, i = 0, len1, len2;
	int a = nonTreeEdges[3 * tid];
	int b = nonTreeEdges[3 * tid + 1];
	if (auxAdjList[2 * a + 1] != -1)
		a += vertexCount;
	if (auxAdjList[2 * b + 1] != -1)
			b += vertexCount;

	int eid = nonTreeEdges[3 * tid + 2];
	int path_a[MAX_HEIGHT], path_b[MAX_HEIGHT];

	while (a != 0)
	{
		path_a[i++] = a;
		if (a < vertexCount && auxAdjList[2 * a + 1] != -1)
			a = vertexCount + a;
		else if (a >= vertexCount)
			a = parent[a - vertexCount];
		else
			a = parent[a];
	}
	path_a[i++] = 0;
	len1 = i;
	i = 0;

	while (b != 0)
	{
		path_b[i++] = b;
		if (b < vertexCount && auxAdjList[2 * b + 1] != -1)
			b = vertexCount + b;
		else if (b >= vertexCount)
			b = parent[b - vertexCount];
		else
			b = parent[b];
	}
	path_b[i++] = 0;
	len2 = i;

	i = 0;
	while (i < len1 && i < len2 && path_a[len1 - i - 1] == path_b[len2 - i - 1])
		i++;

	//int lcaVertex = path_a[len1 - i];
	//printf("Edge %d: %d %d LCA %d\n", eid, nonTreeEdges[3 * tid], nonTreeEdges[3 * tid + 1], lcaVertex);


	len1 -= i;
	len2 -= i;



	// Mark the non-tree edge visited
	threadEdge[eid] = tid;

	for (i = 0; i < len1; i++) {
		if (path_a[i] >= vertexCount) {
			threadEdge[edgeCount + path_a[i] - vertexCount] = tid;

		}
		else {
			threadEdge[offset[path_a[i]]] = tid;
		}
	}


	for (i = 0; i < len2; i++) {
		if (path_b[i] >= vertexCount) {
			threadEdge[edgeCount + path_b[i] - vertexCount] = tid;
		}
		else {
			threadEdge[offset[path_b[i]]] = tid;

		}
	}


}

__global__ void auxGraph(int *adjList, int *offset, int *lcaThread, int vertexCount,
		int *rootLCACount, int *auxAdjList) {
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int lcaVertex = lcaThread[tid];

	if (lcaVertex != 0)
		adjList[offset[lcaVertex]] = vertexCount + lcaVertex;
	else
		atomicAdd(rootLCACount, 1);

	// Update grandParent's child
	int grandParent = auxAdjList[2 * lcaVertex];
	for (int i = offset[grandParent]; i < offset[grandParent + 1]; i++) {
		if (adjList[i] == lcaVertex) {
			adjList[i] = vertexCount + lcaVertex;
			break;
		}
	}

}


__global__ void markArtPoint(int *adjList, int *offset, int *lcaThread, int *artPoint,
							int *unfinished, int *rootLCACount) {
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int lcaVertex = lcaThread[tid];
	bool bridge = false;


	for (int i = offset[lcaVertex]; i < offset[lcaVertex + 1]; i++) {
		if (!unfinished[adjList[i]]) {
			bridge = true;
			break;
		}
	}

	printf("vertex %d rootLCACOUnt %d bridge %d\n", lcaVertex, *rootLCACount, bridge);
	if (lcaVertex != 0 && bridge)
		artPoint[lcaVertex] = 1;
	else if (lcaVertex == 0 && bridge && *rootLCACount > 1)
		artPoint[0] = 1;
}
/*
 * Finds BCC Id for each edge. If an edge was part of the path to an LCA and
 * that LCA happens to be an articulation point, we assign the LCA's vertex ID as BCC id to the edge.
 * Otherwise, we traverse up the tree to find an LCA which is an articulation point.
 */
__global__ void findBCC(int *adjList, int *offset, int *threadEdge, int *lcaThread,
						int *artPoint, int *bccId) {
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int lcaVertex = threadEdge[tid];

	// TODO: Unfinished implementation
	// Note: For each undirected edge b/w a-b, only one direction is marked in the threadEdge
	if (lcaVertex != -1) {
		while (!artPoint[lcaVertex]) {
			//lcaVertex = adjList[offset[lcaVertex]];
		}

		bccId[tid] = lcaVertex;
	}

}

int main(int argc, char **argv)
{
	char* edgeListFile = argv[1];
	FILE *fp;
	fp = fopen(edgeListFile, "r");
	if (fp == NULL) {
		printf("ERROR: File does not exist!\n");
		return 1;
	}

	int vertexCount, edgeCount;
	fscanf(fp, "%d", &vertexCount);
	fscanf(fp, "%d", &edgeCount);
	printf("VertexCount %d\n", vertexCount);
	printf("EdgeCount %d\n", edgeCount);

	// Data structure to represent the graph in CSR format
	int *adjList;		// Concatenated adjacency list
	int *offset;		// Stores offset of each vertex's adjacency list

	size_t adjListSize = edgeCount * sizeof(int);
	size_t offsetSize = (vertexCount + 1) * sizeof(int);
	size_t verticesSize = vertexCount * sizeof(int);

	adjList = (int *)malloc(adjListSize);
	offset = (int *)malloc(offsetSize);

	int edgeCounter = 0, vertexCounter = 0;
	int prevSource, source, dest;
	fscanf(fp, "%d %d", &prevSource, &dest);

	// Convert the graph to CSR format
	while (edgeCounter != edgeCount) {
		while (vertexCounter <= prevSource)			// Includes the vertices with no edges
			offset[vertexCounter++] = edgeCounter;
		adjList[edgeCounter++] = dest;
		while (fscanf(fp, "%d %d", &source, &dest) == 2 && source == prevSource)
			adjList[edgeCounter++] = dest;
		prevSource = source;
	}

	// Mark the sentinel values so that the degree of any vertex i = offset[i + 1] - offset[i]
	while (vertexCounter <= vertexCount)
		offset[vertexCounter++] = edgeCount;


//	printf("Adjacency List\n");
//	for(int i = 0; i < edgeCount; i++) {
//		printf("%d ", adjList[i]);
//	}
//
//	printf("\nOffsets\n");
//	for(int i = 0; i < vertexCount + 1; i++) {
//		printf("%d ", offset[i]);
//	}
//	printf("\n");

	// Initialize other data structure to be used for bfs
	int *inpFrontier, *outFrontier, *visited, *parent, *treeEdges;
	int s1, s2;					// Size of input and output frontiers
	int treeEdgeCount = 0;

	inpFrontier = (int *)calloc(vertexCount, sizeof(int));
	outFrontier = (int *)calloc(vertexCount, sizeof(int));
	visited = (int *)calloc(vertexCount, sizeof(int));
	treeEdges = (int *)calloc(edgeCount, sizeof(int));
	parent = (int *)malloc(verticesSize);
	memset(parent, -1, verticesSize);
	s1 = 1; s2 = 0;
	inpFrontier[0] = 0;	// Inserting source vertex

	// Corresponding device data
	int *d_adjList, *d_offset;
	int *d_inpFrontier, *d_outFrontier, *d_visited, *d_parent, *d_treeEdges;
	int *d_s1, *d_s2;

	hipMalloc(&d_adjList, adjListSize);
	hipMalloc(&d_offset, offsetSize);
	hipMalloc(&d_inpFrontier, verticesSize);
	hipMalloc(&d_outFrontier, verticesSize);
	hipMalloc(&d_visited, verticesSize);
	hipMalloc(&d_treeEdges, edgeCount * sizeof(int));
	hipMalloc(&d_parent, verticesSize);
	hipMalloc(&d_s1, sizeof(int));
	hipMalloc(&d_s2, sizeof(int));

	hipMemcpy(d_adjList, adjList, adjListSize, hipMemcpyHostToDevice);
	hipMemcpy(d_offset, offset, offsetSize, hipMemcpyHostToDevice);
	hipMemcpy(d_inpFrontier, inpFrontier, verticesSize, hipMemcpyHostToDevice);
	hipMemcpy(d_outFrontier, outFrontier, verticesSize, hipMemcpyHostToDevice);
	hipMemcpy(d_visited, visited, verticesSize, hipMemcpyHostToDevice);
	hipMemcpy(d_treeEdges, treeEdges, edgeCount * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_parent, parent, verticesSize, hipMemcpyHostToDevice);
	hipMemcpy(d_s1, &s1, sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_s2, &s2, sizeof(int), hipMemcpyHostToDevice);

	// Start the bfs
	bool odd = true;
	int inpQSize = s1;
	numIterations = 0;
	while (inpQSize != 0) {
		dim3 blocksPerGrid ((inpQSize + 1023) / 1024);
		dim3 threadsPerBlock ((inpQSize > 1024) ? 1024 : inpQSize);
		if (odd) {
			bfs<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_inpFrontier, d_outFrontier,
													d_parent, d_visited, d_treeEdges, d_s1, d_s2);
			hipMemcpy(&inpQSize, d_s2, sizeof(int), hipMemcpyDeviceToHost);
			s1 = 0;
			hipMemcpy(d_s1, &s1, sizeof(int), hipMemcpyHostToDevice);

		}
		else {
			bfs<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_outFrontier, d_inpFrontier,
													d_parent, d_visited, d_treeEdges, d_s2, d_s1);
			hipMemcpy(&inpQSize, d_s1, sizeof(int), hipMemcpyDeviceToHost);
			s2 = 0;
			hipMemcpy(d_s2, &s2, sizeof(int), hipMemcpyHostToDevice);
		}
		odd = !odd;
		numIterations++;
		treeEdgeCount += inpQSize;
	}

	hipMemcpy(visited, d_visited, verticesSize, hipMemcpyDeviceToHost);
	hipMemcpy(parent, d_parent, verticesSize, hipMemcpyDeviceToHost);
	hipMemcpy(treeEdges, d_treeEdges, edgeCount * sizeof(int), hipMemcpyDeviceToHost);
	hipMemcpy(adjList, d_adjList, edgeCount * sizeof(int), hipMemcpyDeviceToHost);



//	printf("Parent array\n");
//	for (int i = 0; i < vertexCount; i++)
//			printf("%d ", parent[i]);
//	printf("\n");
//
//	printf("Adjacency List\n");
//	for(int i = 0; i < edgeCount; i++) {
//		printf("(%d %d) ", i, adjList[i]);
//	}
//	printf("\n");
//
//	for (int i = 0; i < vertexCount; i++) {
//		if (parent[i] != adjList[offset[i]])
//			printf("WRONG %d\n", i);
//	}
//
//	printf("Number of iterations %d \n", numIterations);
//	printf("Visited array\n");
//	for (int i = 0; i < vertexCount; i++)
//		printf("%d ", visited[i]);
//	printf("\n");

//	printf("Tree Edges\n");
//	for (int i = 0; i < edgeCount; i++)
//		printf("%d ", treeEdges[i]);
//	printf("\n");

	int nonTreeEdgeCount = (edgeCount - 2 * treeEdgeCount) / 2;
//	printf("treeEdgecount %d\n", treeEdgeCount);
//	printf("Non-tree edges count %d\n", nonTreeEdgeCount);


	dim3 blocksPerGrid ((nonTreeEdgeCount + 1023) / 1024);
	dim3 threadsPerBlock ((nonTreeEdgeCount > 1024) ? 1024 : nonTreeEdgeCount);

	int threadCount = blocksPerGrid.x * threadsPerBlock.x;

	//printf("ThreadCount = %d\n", threadCount);

	// Data structure to represent non tree edges
	// a b i : edge a->b with edge id i
	int *nonTreeEdges = (int *) calloc(3 * nonTreeEdgeCount, sizeof(int));
	int *lcaThread = (int *) calloc(threadCount, sizeof(int));
	int *threadEdge = (int *) malloc(edgeCount * sizeof(int));
	memset(threadEdge, -1, edgeCount * sizeof(int));
	int *unfinished = (int *) calloc(vertexCount, sizeof(int));
	int *auxAdjList = (int *) malloc(2 * vertexCount * sizeof(int));
	memset(auxAdjList, -1, 2 * vertexCount * sizeof(int));
	int *artPoint = (int *) calloc(vertexCount, sizeof(int));
	int rootLCACount = 0;

	// Populate non tree edges
	for (int i = 0, j = 0; i < edgeCount; i++) {
		if (treeEdges[i] >= 0) {
			nonTreeEdges[j++] = treeEdges[i];
			nonTreeEdges[j++] = adjList[i];
			nonTreeEdges[j++] = i;
		}
	}
	/*
	printf("Non tree edges\n");
	for (int i = 0; i < 3 * nonTreeEdgeCount; i+=3) {
		printf("%d %d %d\n", nonTreeEdges[i], nonTreeEdges[i + 1], nonTreeEdges[i + 2]);
	}*/

	int *d_nonTreeEdges, *d_lcaThread, *d_threadEdge, *d_unfinished, *d_auxAdjList, *d_artPoint, *d_rootLCACount;

	hipMalloc(&d_nonTreeEdges, 3 * nonTreeEdgeCount * sizeof(int));
	hipMalloc(&d_lcaThread, threadCount * sizeof(int));
	hipMalloc(&d_threadEdge, edgeCount * sizeof(int));
	hipMalloc(&d_unfinished, vertexCount * sizeof(int));
	hipMalloc(&d_auxAdjList, 2 * vertexCount * sizeof(int));
	hipMalloc(&d_artPoint, vertexCount * sizeof(int));
	hipMalloc(&d_rootLCACount, sizeof(int));

	hipMemcpy(d_nonTreeEdges, nonTreeEdges, 3 * nonTreeEdgeCount * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_lcaThread, lcaThread, threadCount * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_threadEdge, threadEdge, edgeCount * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_unfinished, unfinished, vertexCount * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_auxAdjList, auxAdjList, 2 * vertexCount * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_artPoint, artPoint, vertexCount * sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_rootLCACount, &rootLCACount, sizeof(int), hipMemcpyHostToDevice);


	lca<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_parent, d_nonTreeEdges,
											d_unfinished, d_threadEdge, d_lcaThread, d_auxAdjList,
											vertexCount);


	auxGraph<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_lcaThread, vertexCount, d_rootLCACount, d_auxAdjList);

	int *threadEdge1 = (int *) malloc((edgeCount + vertexCount) * sizeof(int));
	memset(threadEdge1, -1, (edgeCount + vertexCount) * sizeof(int));

	int *d_threadEdge1;
	hipMalloc(&d_threadEdge1, (edgeCount + vertexCount) * sizeof(int));
	hipMemcpy(d_threadEdge1, threadEdge1, (edgeCount + vertexCount) * sizeof(int), hipMemcpyHostToDevice);

	lca1<<<blocksPerGrid, threadsPerBlock>>>(d_adjList, d_offset, d_parent, d_nonTreeEdges,
												d_unfinished, d_threadEdge1, d_lcaThread, d_auxAdjList,
												vertexCount, edgeCount);


	hipMemcpy(threadEdge1, d_threadEdge1, (edgeCount + vertexCount) * sizeof(int), hipMemcpyDeviceToHost);

	hipMemcpy(lcaThread, d_lcaThread, threadCount * sizeof(int), hipMemcpyDeviceToHost);
	hipMemcpy(threadEdge, d_threadEdge, edgeCount * sizeof(int), hipMemcpyDeviceToHost);

	hipMemcpy(unfinished, d_unfinished, vertexCount * sizeof(int), hipMemcpyDeviceToHost);
	hipMemcpy(adjList, d_adjList, edgeCount * sizeof(int), hipMemcpyDeviceToHost);
	hipMemcpy(auxAdjList, d_auxAdjList, 2 * vertexCount * sizeof(int), hipMemcpyDeviceToHost);
	hipMemcpy(artPoint, d_artPoint, vertexCount * sizeof(int), hipMemcpyDeviceToHost);

/*
	printf("LCA Thread\n");
	for (int i = 0; i < threadCount; i++)
		printf("%d ", lcaThread[i]);

	printf("\nthread Edge\n");
	for (int i = 0; i < edgeCount; i++)
		printf("%d ", threadEdge[i]);

	printf("\n unfinished \n");
	for (int i = 0; i < vertexCount; i++)
		printf("%d ", unfinished[i]);

	printf("\n Adj List\n");
	for (int i = 0; i < edgeCount; i++)
		printf("%d ", adjList[i]);

	printf("\n Aux Adj List \n");
	for (int i = 0; i < 2 * vertexCount; i+=2)
		printf("%d %d\n", auxAdjList[i], auxAdjList[i + 1]);


	printf("\n Art Point \n");
	for (int i = 0; i < vertexCount; i++)
		printf("%d %d\n", i, artPoint[i]);


	printf("\n THREAD EDGE\n");
	for (int i = 0; i < (edgeCount + vertexCount); i++)
		printf("%d ", threadEdge1[i]);

*/
	printf("\n");
	for (int i = 0; i < threadCount; i++) {
		if (threadEdge1[offset[lcaThread[i]]] == -1)
			printf("%d ", lcaThread[i]);
	}
	printf("\n");

	// Free allocated memory on device and host
	hipFree(d_adjList);
	hipFree(d_offset);
	hipFree(d_inpFrontier);
	hipFree(d_outFrontier);
	hipFree(d_visited);
	hipFree(d_treeEdges);
	hipFree(d_parent);
	hipFree(d_s1);
	hipFree(d_s2);
	hipFree(d_nonTreeEdges);
	hipFree(d_lcaThread);
	hipFree(d_threadEdge);
	hipFree(d_unfinished);
	hipFree(d_artPoint);
	hipFree(d_rootLCACount);

	free(inpFrontier);
	free(outFrontier);
	free(visited);
	free(treeEdges);
	free(parent);
	free(nonTreeEdges);
	free(lcaThread);
	free(threadEdge);
	free(unfinished);
	free(artPoint);

    return 0;
}

	.text
	.file	"binconnected_components.hip"
	.globl	_Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_ # -- Begin function _Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_
	.type	_Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_,@function
_Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_: # @_Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3bfsPiS_S_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__lcaPiS_S_S_S_S_S_S_i # -- Begin function _Z18__device_stub__lcaPiS_S_S_S_S_S_S_i
	.type	_Z18__device_stub__lcaPiS_S_S_S_S_S_S_i,@function
_Z18__device_stub__lcaPiS_S_S_S_S_S_S_i: # @_Z18__device_stub__lcaPiS_S_S_S_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3lcaPiS_S_S_S_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__lcaPiS_S_S_S_S_S_S_i, .Lfunc_end1-_Z18__device_stub__lcaPiS_S_S_S_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii # -- Begin function _Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii
	.type	_Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii,@function
_Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii: # @_Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4lca1PiS_S_S_S_S_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii, .Lfunc_end2-_Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__auxGraphPiS_S_iS_S_ # -- Begin function _Z23__device_stub__auxGraphPiS_S_iS_S_
	.type	_Z23__device_stub__auxGraphPiS_S_iS_S_,@function
_Z23__device_stub__auxGraphPiS_S_iS_S_: # @_Z23__device_stub__auxGraphPiS_S_iS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8auxGraphPiS_S_iS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z23__device_stub__auxGraphPiS_S_iS_S_, .Lfunc_end3-_Z23__device_stub__auxGraphPiS_S_iS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__markArtPointPiS_S_S_S_S_ # -- Begin function _Z27__device_stub__markArtPointPiS_S_S_S_S_
	.type	_Z27__device_stub__markArtPointPiS_S_S_S_S_,@function
_Z27__device_stub__markArtPointPiS_S_S_S_S_: # @_Z27__device_stub__markArtPointPiS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12markArtPointPiS_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z27__device_stub__markArtPointPiS_S_S_S_S_, .Lfunc_end4-_Z27__device_stub__markArtPointPiS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__findBCCPiS_S_S_S_S_ # -- Begin function _Z22__device_stub__findBCCPiS_S_S_S_S_
	.type	_Z22__device_stub__findBCCPiS_S_S_S_S_,@function
_Z22__device_stub__findBCCPiS_S_S_S_S_: # @_Z22__device_stub__findBCCPiS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7findBCCPiS_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z22__device_stub__findBCCPiS_S_S_S_S_, .Lfunc_end5-_Z22__device_stub__findBCCPiS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$312, %rsp                      # imm = 0x138
	.cfi_def_cfa_offset 368
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	8(%rsi), %rdi
	movl	$.L.str, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB6_1
# %bb.2:
	movq	%rax, %r12
	xorl	%r13d, %r13d
	leaq	8(%rsp), %rbx
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	movq	%rbx, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	leaq	12(%rsp), %r15
	movl	$.L.str.2, %esi
	movq	%r12, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	(%rbx), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movl	(%r15), %esi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movslq	(%r15), %rdi
	shlq	$2, %rdi
	movslq	(%rbx), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	leaq	4(,%rax,4), %rbx
	movq	%rdi, 104(%rsp)                 # 8-byte Spill
	callq	malloc
	movq	%rax, %r14
	movq	%rbx, 112(%rsp)                 # 8-byte Spill
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	leaq	28(%rsp), %rdx
	leaq	68(%rsp), %rcx
	movl	$.L.str.5, %esi
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	cmpl	$0, (%r15)
	movl	$0, %ebx
	je	.LBB6_14
# %bb.3:                                # %.preheader192.preheader
	movl	28(%rsp), %ecx
	leaq	156(%rsp), %r15
	leaq	68(%rsp), %rbp
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
	movq	%r14, 72(%rsp)                  # 8-byte Spill
.LBB6_4:                                # %.preheader192
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_6 Depth 2
                                        #     Child Loop BB6_11 Depth 2
	cmpl	%ecx, %r13d
	jg	.LBB6_8
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB6_4 Depth=1
	movslq	%r13d, %rax
	incl	%ecx
	movq	160(%rsp), %rdx                 # 8-byte Reload
	leaq	(%rdx,%rax,4), %rax
	movl	%ecx, %edx
	subl	%r13d, %edx
	xorl	%esi, %esi
.LBB6_6:                                # %.lr.ph
                                        #   Parent Loop BB6_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%ebx, (%rax,%rsi,4)
	incq	%rsi
	cmpl	%esi, %edx
	jne	.LBB6_6
# %bb.7:                                #   in Loop: Header=BB6_4 Depth=1
	movl	%ecx, %r13d
.LBB6_8:                                # %._crit_edge
                                        #   in Loop: Header=BB6_4 Depth=1
	movl	68(%rsp), %eax
	movslq	%ebx, %rcx
	movl	%eax, (%r14,%rcx,4)
	incl	%ebx
	movl	$.L.str.5, %esi
	movq	%r12, %rdi
	movq	%r15, %rdx
	movq	%rbp, %rcx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	156(%rsp), %ecx
	cmpl	$2, %eax
	jne	.LBB6_13
# %bb.9:                                # %._crit_edge
                                        #   in Loop: Header=BB6_4 Depth=1
	cmpl	28(%rsp), %ecx
	jne	.LBB6_13
# %bb.10:                               # %.lr.ph200.preheader
                                        #   in Loop: Header=BB6_4 Depth=1
	movslq	%ebx, %rax
	leaq	(%r14,%rax,4), %r14
.LBB6_11:                               # %.lr.ph200
                                        #   Parent Loop BB6_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	68(%rsp), %eax
	movl	%eax, (%r14)
	movl	$.L.str.5, %esi
	movq	%r12, %rdi
	movq	%r15, %rdx
	movq	%rbp, %rcx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	incl	%ebx
	movl	156(%rsp), %ecx
	cmpl	$2, %eax
	jne	.LBB6_13
# %bb.12:                               # %.lr.ph200
                                        #   in Loop: Header=BB6_11 Depth=2
	addq	$4, %r14
	cmpl	28(%rsp), %ecx
	je	.LBB6_11
.LBB6_13:                               # %._crit_edge201
                                        #   in Loop: Header=BB6_4 Depth=1
	movl	%ecx, 28(%rsp)
	cmpl	12(%rsp), %ebx
	movq	72(%rsp), %r14                  # 8-byte Reload
	jne	.LBB6_4
.LBB6_14:                               # %.preheader
	shlq	$2, 32(%rsp)                    # 8-byte Folded Spill
	movslq	8(%rsp), %r15
	cmpl	%r15d, %r13d
	jg	.LBB6_17
# %bb.15:                               # %.lr.ph211.preheader
	movslq	%r13d, %rax
	movq	160(%rsp), %rcx                 # 8-byte Reload
	leaq	(%rcx,%rax,4), %rax
	movl	%r15d, %ecx
	subl	%r13d, %ecx
	incl	%ecx
	xorl	%edx, %edx
.LBB6_16:                               # %.lr.ph211
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebx, (%rax,%rdx,4)
	incq	%rdx
	cmpl	%edx, %ecx
	jne	.LBB6_16
.LBB6_17:                               # %._crit_edge212
	movabsq	$4294967296, %r12               # imm = 0x100000000
	movl	$4, %esi
	movq	%r15, %rdi
	callq	calloc
	movq	%rax, 272(%rsp)                 # 8-byte Spill
	movl	$4, %esi
	movq	%r15, %rdi
	callq	calloc
	movq	%rax, 264(%rsp)                 # 8-byte Spill
	movl	$4, %esi
	movq	%r15, %rdi
	callq	calloc
	movq	%rax, 216(%rsp)                 # 8-byte Spill
	movslq	%ebx, %rdi
	movl	$4, %esi
	callq	calloc
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	32(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, 208(%rsp)                 # 8-byte Spill
	movq	%rax, %rdi
	movl	$255, %esi
	movq	%rbp, %rdx
	callq	memset@PLT
	leaq	64(%rsp), %rax
	movl	$1, (%rax)
	xorl	%ebx, %ebx
	leaq	60(%rsp), %rax
	movl	%ebx, (%rax)
	leaq	16(%rsp), %rdi
	movq	104(%rsp), %r15                 # 8-byte Reload
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movq	112(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	192(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	184(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	144(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movslq	12(%rsp), %rsi
	shlq	$2, %rsi
	leaq	136(%rsp), %rdi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	96(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	leaq	88(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	48(%rsp), %rax
	movq	(%rax), %rdi
	movq	160(%rsp), %rsi                 # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	192(%rsp), %rax
	movq	(%rax), %rdi
	movq	272(%rsp), %rsi                 # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	184(%rsp), %rax
	movq	(%rax), %rdi
	movq	264(%rsp), %rsi                 # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	144(%rsp), %rax
	movq	(%rax), %rdi
	movq	216(%rsp), %rsi                 # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	136(%rsp), %rax
	movq	(%rax), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	208(%rsp), %rsi                 # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	96(%rsp), %rax
	movq	(%rax), %rdi
	movl	$4, %edx
	leaq	64(%rsp), %r15
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	88(%rsp), %rax
	movq	(%rax), %rdi
	movl	$4, %edx
	leaq	60(%rsp), %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	(%r15), %edx
	movl	%edx, 152(%rsp)
	movl	%ebx, numIterations(%rip)
	testl	%edx, %edx
	je	.LBB6_28
# %bb.18:                               # %.lr.ph218.preheader
	movb	$1, %bpl
	xorl	%eax, %eax
	movl	$1024, %r15d                    # imm = 0x400
	leaq	152(%rsp), %r13
.LBB6_19:                               # %.lr.ph218
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %ebx
	leal	1023(%rdx), %eax
	leal	2046(%rdx), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$10, %edi
	orq	%r12, %rdi
	cmpl	%r15d, %edx
	cmovgel	%r15d, %edx
	orq	%r12, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testb	$1, %bpl
	je	.LBB6_23
# %bb.20:                               #   in Loop: Header=BB6_19 Depth=1
	testl	%eax, %eax
	jne	.LBB6_22
# %bb.21:                               #   in Loop: Header=BB6_19 Depth=1
	movq	16(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	192(%rsp), %rdx
	movq	184(%rsp), %rcx
	movq	40(%rsp), %r8
	movq	144(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB6_22:                               #   in Loop: Header=BB6_19 Depth=1
	movq	88(%rsp), %rsi
	movl	$4, %edx
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$0, 64(%rsp)
	movq	96(%rsp), %rdi
	movl	$4, %edx
	leaq	64(%rsp), %rsi
	jmp	.LBB6_26
.LBB6_23:                               #   in Loop: Header=BB6_19 Depth=1
	testl	%eax, %eax
	jne	.LBB6_25
# %bb.24:                               #   in Loop: Header=BB6_19 Depth=1
	movq	16(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	184(%rsp), %rdx
	movq	192(%rsp), %rcx
	movq	40(%rsp), %r8
	movq	144(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB6_25:                               #   in Loop: Header=BB6_19 Depth=1
	movq	96(%rsp), %rsi
	movl	$4, %edx
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$0, 60(%rsp)
	movq	88(%rsp), %rdi
	movl	$4, %edx
	leaq	60(%rsp), %rsi
.LBB6_26:                               #   in Loop: Header=BB6_19 Depth=1
	movl	$1, %ecx
	callq	hipMemcpy
	incl	numIterations(%rip)
	xorb	$1, %bpl
	movl	152(%rsp), %edx
	leal	(%rdx,%rbx), %eax
	testl	%edx, %edx
	jne	.LBB6_19
# %bb.27:                               # %._crit_edge219.loopexit
	addl	%ebx, %ebx
.LBB6_28:                               # %._crit_edge219
	movq	144(%rsp), %rsi
	movq	216(%rsp), %rdi                 # 8-byte Reload
	movq	32(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rsi
	movq	208(%rsp), %rdi                 # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	136(%rsp), %rsi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	72(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movslq	12(%rsp), %r15
	movl	%r15d, %eax
	subl	%ebx, %eax
	movl	%eax, %ecx
	shrl	$31, %ecx
	addl	%eax, %ecx
	sarl	%ecx
	leal	1023(%rcx), %eax
	leal	2046(%rcx), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	sarl	$10, %edx
	movq	%rdx, %rax
	orq	%r12, %rax
	movq	%rax, 240(%rsp)                 # 8-byte Spill
	movl	$1024, %ebx                     # imm = 0x400
	cmpl	%ebx, %ecx
	cmovll	%ecx, %ebx
	orq	%rbx, %r12
	imull	%edx, %ebx
	leal	(%rcx,%rcx,2), %eax
	movslq	%eax, %rdi
	movl	$4, %esi
	movq	%rdi, 296(%rsp)                 # 8-byte Spill
	callq	calloc
	movq	%rax, %r13
	movq	%rbx, 304(%rsp)                 # 8-byte Spill
	movslq	%ebx, %rdi
	movl	$4, %esi
	movq	%rdi, 200(%rsp)                 # 8-byte Spill
	callq	calloc
	movq	%rax, 256(%rsp)                 # 8-byte Spill
	leaq	(,%r15,4), %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	%rax, %rdi
	movl	$255, %esi
	movq	%rbx, %rdx
	callq	memset@PLT
	movslq	8(%rsp), %rbx
	movl	$4, %esi
	movq	%rbx, %rdi
	callq	calloc
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	leaq	(,%rbx,8), %rbp
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, 248(%rsp)                 # 8-byte Spill
	movq	%rax, %rdi
	movl	$255, %esi
	movq	%rbp, %rdx
	callq	memset@PLT
	movl	$4, %esi
	movq	%rbx, %rdi
	callq	calloc
	movq	72(%rsp), %r8                   # 8-byte Reload
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movl	$0, 236(%rsp)
	testq	%r15, %r15
	jle	.LBB6_33
# %bb.29:                               # %.lr.ph224.preheader
	movl	%r15d, %eax
	xorl	%ecx, %ecx
	xorl	%edx, %edx
.LBB6_30:                               # %.lr.ph224
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r8,%rcx,4), %esi
	testl	%esi, %esi
	js	.LBB6_32
# %bb.31:                               #   in Loop: Header=BB6_30 Depth=1
	movslq	%edx, %rdi
	movl	%esi, (%r13,%rdi,4)
	movl	(%r14,%rcx,4), %edx
	movl	%edx, 4(%r13,%rdi,4)
	leal	3(%rdi), %edx
	movl	%ecx, 8(%r13,%rdi,4)
.LBB6_32:                               #   in Loop: Header=BB6_30 Depth=1
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB6_30
.LBB6_33:                               # %._crit_edge225
	movq	296(%rsp), %r15                 # 8-byte Reload
	shlq	$2, %r15
	leaq	176(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	200(%rsp), %rbx                 # 8-byte Reload
	shlq	$2, %rbx
	leaq	80(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movslq	12(%rsp), %rsi
	shlq	$2, %rsi
	leaq	168(%rsp), %rdi
	callq	hipMalloc
	movslq	8(%rsp), %rsi
	shlq	$2, %rsi
	leaq	128(%rsp), %rdi
	callq	hipMalloc
	movslq	8(%rsp), %rsi
	shlq	$3, %rsi
	leaq	120(%rsp), %rdi
	callq	hipMalloc
	movslq	8(%rsp), %rsi
	shlq	$2, %rsi
	leaq	224(%rsp), %rdi
	callq	hipMalloc
	leaq	288(%rsp), %rbp
	movl	$4, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	176(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r13, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	80(%rsp), %rax
	movq	(%rax), %rdi
	movq	256(%rsp), %rsi                 # 8-byte Reload
	movq	%rbx, 200(%rsp)                 # 8-byte Spill
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	168(%rsp), %rax
	movq	(%rax), %rdi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	128(%rsp), %rax
	movq	(%rax), %rdi
	movslq	8(%rsp), %rdx
	shlq	$2, %rdx
	movq	112(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	120(%rsp), %rax
	movq	(%rax), %rdi
	movslq	8(%rsp), %rdx
	shlq	$3, %rdx
	movq	248(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	224(%rsp), %rax
	movq	(%rax), %rdi
	movslq	8(%rsp), %rdx
	shlq	$2, %rdx
	movq	104(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	leaq	236(%rsp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	240(%rsp), %rbx                 # 8-byte Reload
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_35
# %bb.34:
	movq	16(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	176(%rsp), %rcx
	movq	128(%rsp), %r8
	movq	168(%rsp), %r9
	movl	8(%rsp), %eax
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z18__device_stub__lcaPiS_S_S_S_S_S_S_i
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB6_35:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_37
# %bb.36:
	movq	16(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	80(%rsp), %rdx
	movl	8(%rsp), %ecx
	movq	288(%rsp), %r8
	movq	120(%rsp), %r9
	callq	_Z23__device_stub__auxGraphPiS_S_iS_S_
.LBB6_37:
	movslq	12(%rsp), %rax
	movslq	8(%rsp), %rbx
	addq	%rax, %rbx
	shlq	$2, %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %rbp
	movq	%rax, %rdi
	movl	$255, %esi
	movq	%rbx, %rdx
	callq	memset@PLT
	leaq	280(%rsp), %r15
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movslq	12(%rsp), %rax
	movslq	8(%rsp), %rdx
	addq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	240(%rsp), %rdi                 # 8-byte Reload
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_39
# %bb.38:
	movq	16(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	176(%rsp), %rcx
	movq	128(%rsp), %r8
	movq	280(%rsp), %r9
	movl	8(%rsp), %eax
	movl	12(%rsp), %r10d
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB6_39:
	movq	280(%rsp), %rsi
	movslq	12(%rsp), %rax
	movslq	8(%rsp), %rdx
	addq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	80(%rsp), %rsi
	movq	256(%rsp), %r12                 # 8-byte Reload
	movq	%r12, %rdi
	movq	200(%rsp), %rdx                 # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	168(%rsp), %rsi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	128(%rsp), %rsi
	movslq	8(%rsp), %rdx
	shlq	$2, %rdx
	movq	112(%rsp), %rdi                 # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movslq	12(%rsp), %rdx
	shlq	$2, %rdx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	120(%rsp), %rsi
	movslq	8(%rsp), %rdx
	shlq	$3, %rdx
	movq	248(%rsp), %rdi                 # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	224(%rsp), %rsi
	movslq	8(%rsp), %rdx
	shlq	$2, %rdx
	movq	104(%rsp), %rdi                 # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$10, %edi
	callq	putchar@PLT
	movq	304(%rsp), %rax                 # 8-byte Reload
	testl	%eax, %eax
	movq	160(%rsp), %r15                 # 8-byte Reload
	jle	.LBB6_44
# %bb.40:                               # %.lr.ph228.preheader
	movl	%eax, %ebx
	xorl	%r14d, %r14d
.LBB6_41:                               # %.lr.ph228
                                        # =>This Inner Loop Header: Depth=1
	movslq	(%r12,%r14,4), %rsi
	movslq	(%r15,%rsi,4), %rax
	cmpl	$-1, (%rbp,%rax,4)
	jne	.LBB6_43
# %bb.42:                               #   in Loop: Header=BB6_41 Depth=1
	movl	$.L.str.7, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
.LBB6_43:                               #   in Loop: Header=BB6_41 Depth=1
	incq	%r14
	cmpq	%r14, %rbx
	jne	.LBB6_41
.LBB6_44:                               # %._crit_edge229
	movl	$10, %edi
	callq	putchar@PLT
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	192(%rsp), %rdi
	callq	hipFree
	movq	184(%rsp), %rdi
	callq	hipFree
	movq	144(%rsp), %rdi
	callq	hipFree
	movq	136(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	96(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	176(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	168(%rsp), %rdi
	callq	hipFree
	movq	128(%rsp), %rdi
	callq	hipFree
	movq	224(%rsp), %rdi
	callq	hipFree
	movq	288(%rsp), %rdi
	callq	hipFree
	movq	272(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	264(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	216(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	72(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	208(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	32(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	112(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	104(%rsp), %rdi                 # 8-byte Reload
	callq	free
	xorl	%eax, %eax
	jmp	.LBB6_45
.LBB6_1:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$1, %eax
.LBB6_45:
	addq	$312, %rsp                      # imm = 0x138
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB7_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB7_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3bfsPiS_S_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3lcaPiS_S_S_S_S_S_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4lca1PiS_S_S_S_S_S_S_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8auxGraphPiS_S_iS_S_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12markArtPointPiS_S_S_S_S_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7findBCCPiS_S_S_S_S_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end7:
	.size	__hip_module_ctor, .Lfunc_end7-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB8_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB8_2:
	retq
.Lfunc_end8:
	.size	__hip_module_dtor, .Lfunc_end8-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	numIterations,@object           # @numIterations
	.bss
	.globl	numIterations
	.p2align	2, 0x0
numIterations:
	.long	0                               # 0x0
	.size	numIterations, 4

	.type	_Z3bfsPiS_S_S_S_S_S_S_S_,@object # @_Z3bfsPiS_S_S_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z3bfsPiS_S_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z3bfsPiS_S_S_S_S_S_S_S_:
	.quad	_Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_
	.size	_Z3bfsPiS_S_S_S_S_S_S_S_, 8

	.type	_Z3lcaPiS_S_S_S_S_S_S_i,@object # @_Z3lcaPiS_S_S_S_S_S_S_i
	.globl	_Z3lcaPiS_S_S_S_S_S_S_i
	.p2align	3, 0x0
_Z3lcaPiS_S_S_S_S_S_S_i:
	.quad	_Z18__device_stub__lcaPiS_S_S_S_S_S_S_i
	.size	_Z3lcaPiS_S_S_S_S_S_S_i, 8

	.type	_Z4lca1PiS_S_S_S_S_S_S_ii,@object # @_Z4lca1PiS_S_S_S_S_S_S_ii
	.globl	_Z4lca1PiS_S_S_S_S_S_S_ii
	.p2align	3, 0x0
_Z4lca1PiS_S_S_S_S_S_S_ii:
	.quad	_Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii
	.size	_Z4lca1PiS_S_S_S_S_S_S_ii, 8

	.type	_Z8auxGraphPiS_S_iS_S_,@object  # @_Z8auxGraphPiS_S_iS_S_
	.globl	_Z8auxGraphPiS_S_iS_S_
	.p2align	3, 0x0
_Z8auxGraphPiS_S_iS_S_:
	.quad	_Z23__device_stub__auxGraphPiS_S_iS_S_
	.size	_Z8auxGraphPiS_S_iS_S_, 8

	.type	_Z12markArtPointPiS_S_S_S_S_,@object # @_Z12markArtPointPiS_S_S_S_S_
	.globl	_Z12markArtPointPiS_S_S_S_S_
	.p2align	3, 0x0
_Z12markArtPointPiS_S_S_S_S_:
	.quad	_Z27__device_stub__markArtPointPiS_S_S_S_S_
	.size	_Z12markArtPointPiS_S_S_S_S_, 8

	.type	_Z7findBCCPiS_S_S_S_S_,@object  # @_Z7findBCCPiS_S_S_S_S_
	.globl	_Z7findBCCPiS_S_S_S_S_
	.p2align	3, 0x0
_Z7findBCCPiS_S_S_S_S_:
	.quad	_Z22__device_stub__findBCCPiS_S_S_S_S_
	.size	_Z7findBCCPiS_S_S_S_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"r"
	.size	.L.str, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d"
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"VertexCount %d\n"
	.size	.L.str.3, 16

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"EdgeCount %d\n"
	.size	.L.str.4, 14

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%d %d"
	.size	.L.str.5, 6

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%d "
	.size	.L.str.7, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3bfsPiS_S_S_S_S_S_S_S_"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z3lcaPiS_S_S_S_S_S_S_i"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z4lca1PiS_S_S_S_S_S_S_ii"
	.size	.L__unnamed_3, 26

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z8auxGraphPiS_S_iS_S_"
	.size	.L__unnamed_4, 23

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z12markArtPointPiS_S_S_S_S_"
	.size	.L__unnamed_5, 29

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z7findBCCPiS_S_S_S_S_"
	.size	.L__unnamed_6, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"ERROR: File does not exist!"
	.size	.Lstr, 28

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__bfsPiS_S_S_S_S_S_S_S_
	.addrsig_sym _Z18__device_stub__lcaPiS_S_S_S_S_S_S_i
	.addrsig_sym _Z19__device_stub__lca1PiS_S_S_S_S_S_S_ii
	.addrsig_sym _Z23__device_stub__auxGraphPiS_S_iS_S_
	.addrsig_sym _Z27__device_stub__markArtPointPiS_S_S_S_S_
	.addrsig_sym _Z22__device_stub__findBCCPiS_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3bfsPiS_S_S_S_S_S_S_S_
	.addrsig_sym _Z3lcaPiS_S_S_S_S_S_S_i
	.addrsig_sym _Z4lca1PiS_S_S_S_S_S_S_ii
	.addrsig_sym _Z8auxGraphPiS_S_iS_S_
	.addrsig_sym _Z12markArtPointPiS_S_S_S_S_
	.addrsig_sym _Z7findBCCPiS_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3bfsPiS_S_S_S_S_S_S_S_ ; -- Begin function _Z3bfsPiS_S_S_S_S_S_S_S_
	.globl	_Z3bfsPiS_S_S_S_S_S_S_S_
	.p2align	8
	.type	_Z3bfsPiS_S_S_S_S_S_S_S_,@function
_Z3bfsPiS_S_S_S_S_S_S_S_:               ; @_Z3bfsPiS_S_S_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b512 s[16:31], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x54
	s_waitcnt lgkmcnt(0)
	s_load_b32 s3, s[30:31], 0x0
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_24
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s26, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s27, v9, vcc_lo
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_24
; %bb.2:
	v_add_co_u32 v4, vcc_lo, s18, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s19, v9, vcc_lo
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v6, v7
	s_cbranch_execz .LBB0_23
; %bb.3:                                ; %.lr.ph
	v_ashrrev_i32_e32 v7, 31, v6
	s_load_b64 s[2:3], s[0:1], 0x40
	v_dual_mov_b32 v16, -2 :: v_dual_mov_b32 v17, 0
	v_mov_b32_e32 v3, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[11:12], 2, v[6:7]
	v_add_co_u32 v7, vcc_lo, s24, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, s25, v9, vcc_lo
	s_mov_b32 s1, 0
	v_add_co_u32 v9, vcc_lo, s16, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v12, vcc_lo
	v_add_co_u32 v11, vcc_lo, s28, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s29, v12, vcc_lo
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v13, v[9:10], off
	s_mov_b32 s6, -1
	s_mov_b32 s0, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[13:14]
	v_add_co_u32 v18, vcc_lo, s26, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, s27, v15, vcc_lo
	global_load_b32 v18, v[18:19], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v18
	s_cbranch_execz .LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v13, vcc_lo, s24, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, s25, v15, vcc_lo
	s_mov_b32 s6, 0
	s_mov_b32 s0, -1
	global_atomic_cmpswap_b32 v13, v[13:14], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, -1, v13
                                        ; implicit-def: $vgpr13
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB0_7
; %bb.6:                                ; %._crit_edge82
                                        ;   in Loop: Header=BB0_4 Depth=1
	global_load_b32 v13, v[9:10], off
	s_mov_b32 s6, exec_lo
	s_xor_b32 s0, exec_lo, -1
.LBB0_7:                                ; %Flow117
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_or_not1_b32 s6, s6, exec_lo
.LBB0_8:                                ; %Flow116
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_and_saveexec_b32 s5, s6
	s_cbranch_execz .LBB0_18
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	global_load_b32 v14, v[7:8], off
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e64 v13, v14
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_15
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s7, exec_lo
	v_cmpx_ge_i32_e64 v2, v13
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_4 Depth=1
	global_store_b32 v[11:12], v16, off
.LBB0_12:                               ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_4 Depth=1
	global_store_b32 v[11:12], v2, off
.LBB0_14:                               ; %Flow112
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_15:                               ; %Flow114
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_18
; %bb.16:                               ;   in Loop: Header=BB0_4 Depth=1
	global_store_b32 v[11:12], v16, off
	global_load_b32 v13, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v6, v13
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_4 Depth=1
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v13, vcc_lo, s16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s17, v14, vcc_lo
	global_load_b32 v15, v[9:10], off
	global_load_b32 v18, v[13:14], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[13:14], v15, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[9:10], v18, off
	global_load_b32 v13, v[4:5], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v13, vcc_lo, s28, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s29, v14, vcc_lo
	global_load_b32 v15, v[11:12], off
	global_load_b32 v18, v[13:14], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[13:14], v15, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[11:12], v18, off
.LBB0_18:                               ; %Flow118
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_22
; %bb.19:                               ;   in Loop: Header=BB0_4 Depth=1
	s_mov_b32 s6, exec_lo
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_mbcnt_lo_u32_b32 v13, s6, 0
                                        ; implicit-def: $vgpr14
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v13
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_4 Depth=1
	s_bcnt1_i32_b32 s6, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v14, s6
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u32 v14, v17, v14, s[2:3] glc
.LBB0_21:                               ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v15, v[9:10], off
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, s0, v13
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v13, vcc_lo, s22, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v14, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[13:14], v15, off
	global_store_b32 v[11:12], v3, off
.LBB0_22:                               ; %Flow119
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b32 v13, v[4:5], off offset:4
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v11, s0, v11, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v12, s0, 0, v12, s0
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v6, v13
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_4
.LBB0_23:                               ; %Flow122
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v2, 1
	global_store_b32 v[0:1], v2, off
.LBB0_24:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3bfsPiS_S_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3bfsPiS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z3bfsPiS_S_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 972
; NumSgprs: 34
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z3lcaPiS_S_S_S_S_S_S_i ; -- Begin function _Z3lcaPiS_S_S_S_S_S_S_i
	.globl	_Z3lcaPiS_S_S_S_S_S_S_i
	.p2align	8
	.type	_Z3lcaPiS_S_S_S_S_S_S_i,@function
_Z3lcaPiS_S_S_S_S_S_S_i:                ; @_Z3lcaPiS_S_S_S_S_S_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x54
	s_mov_b32 s17, 0
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $vgpr9
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[32:33], null, s15, s2, v[0:1]
	s_load_b512 s[0:15], s[0:1], 0x0
	v_mov_b32_e32 v33, 0
	v_lshl_add_u32 v0, v32, 1, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b96 v[29:31], v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v29
	s_cbranch_execz .LBB1_4
; %bb.1:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v10, v29
	s_mov_b64 s[6:7], 0
                                        ; implicit-def: $vgpr0
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	s_mov_b32 m0, s6
	s_add_u32 s6, s6, 1
	v_movreld_b32_e32 v0, v10
	v_mov_b32_e32 v33, s6
	v_lshlrev_b64 v[11:12], 2, v[10:11]
	s_addc_u32 s7, s7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s4, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	global_load_b32 v10, v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB1_2
; %bb.3:                                ; %Flow251
	s_or_b32 exec_lo, exec_lo, s17
.LBB1_4:                                ; %Flow252
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s16
	v_mov_b32_e32 v34, 0
	s_mov_b32 s7, 0
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $vgpr29
	v_cmpx_ne_u32_e32 0, v30
	s_cbranch_execz .LBB1_8
; %bb.5:                                ; %.lr.ph106.preheader
	v_mov_b32_e32 v10, v30
	s_mov_b32 s16, 0
                                        ; implicit-def: $vgpr20
.LBB1_6:                                ; %.lr.ph106
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	s_mov_b32 m0, s16
	s_add_i32 s16, s16, 1
	v_movreld_b32_e32 v20, v10
	v_mov_b32_e32 v34, s16
	v_lshlrev_b64 v[11:12], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s4, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	global_load_b32 v10, v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_6
; %bb.7:                                ; %Flow249
	s_or_b32 exec_lo, exec_lo, s7
.LBB1_8:                                ; %Flow250
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_cmp_ne_u32_e32 vcc_lo, 9, v33
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
                                        ; implicit-def: $sgpr6
	v_cndmask_b32_e32 v19, 0, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 8, v33
	v_cndmask_b32_e32 v18, 0, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 7, v33
	v_cndmask_b32_e32 v17, 0, v7, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 6, v33
	v_cndmask_b32_e32 v16, 0, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 5, v33
	v_cndmask_b32_e32 v15, 0, v5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 4, v33
	v_cndmask_b32_e32 v14, 0, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 3, v33
	v_cndmask_b32_e32 v13, 0, v3, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 2, v33
	v_cndmask_b32_e32 v12, 0, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 1, v33
	v_cndmask_b32_e32 v11, 0, v1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v33
	v_cndmask_b32_e32 v10, 0, v0, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 9, v34
	v_cndmask_b32_e32 v9, 0, v29, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 8, v34
	v_cndmask_b32_e32 v8, 0, v28, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 7, v34
	v_cndmask_b32_e32 v7, 0, v27, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 6, v34
	v_cndmask_b32_e32 v6, 0, v26, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 5, v34
	v_cndmask_b32_e32 v5, 0, v25, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 4, v34
	v_cndmask_b32_e32 v4, 0, v24, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 3, v34
	v_cndmask_b32_e32 v3, 0, v23, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 2, v34
	v_cndmask_b32_e32 v2, 0, v22, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 1, v34
	v_min_u32_e32 v22, v33, v34
	v_cndmask_b32_e32 v1, 0, v21, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v34
	v_dual_mov_b32 v21, v34 :: v_dual_cndmask_b32 v0, 0, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v20, 1, v22
	v_mov_b32_e32 v22, v33
.LBB1_9:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v22
	s_or_b32 s6, s6, exec_lo
	v_cndmask_b32_e32 v23, v10, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v21
	v_cndmask_b32_e32 v24, v0, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v21
	v_cndmask_b32_e32 v24, v24, v2, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v13, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v21
	v_cndmask_b32_e32 v24, v24, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v14, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v21
	v_cndmask_b32_e32 v24, v24, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v15, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v21
	v_cndmask_b32_e32 v24, v24, v5, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 6, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v16, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 6, v21
	v_cndmask_b32_e32 v24, v24, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 7, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v17, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 7, v21
	v_cndmask_b32_e32 v24, v24, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 8, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 8, v21
	v_cndmask_b32_e32 v24, v24, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 9, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v19, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 9, v21
	v_cndmask_b32_e32 v24, v24, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, v23, v24
	v_mov_b32_e32 v23, s5
	s_and_saveexec_b32 s7, vcc_lo
; %bb.10:                               ;   in Loop: Header=BB1_9 Depth=1
	s_add_i32 s5, s5, 1
	v_dual_mov_b32 v23, v20 :: v_dual_add_nc_u32 v22, -1, v22
	v_cmp_eq_u32_e32 vcc_lo, s5, v20
	v_add_nc_u32_e32 v21, -1, v21
	s_and_not1_b32 s6, s6, exec_lo
	s_and_b32 s16, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s6, s16
; %bb.11:                               ; %Flow248
                                        ;   in Loop: Header=BB1_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, exec_lo, s6
	s_or_b32 s4, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_9
; %bb.12:                               ; %.critedge
	s_or_b32 exec_lo, exec_lo, s4
	v_sub_nc_u32_e32 v20, v33, v23
	v_ashrrev_i32_e32 v33, 31, v32
	v_ashrrev_i32_e32 v25, 31, v31
	v_mov_b32_e32 v24, v31
	s_mov_b32 s6, 0
	v_add_nc_u32_e32 v21, 1, v20
	v_lshlrev_b64 v[26:27], 2, v[32:33]
	s_mov_b32 s7, exec_lo
	v_lshlrev_b64 v[24:25], 2, v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 1, v21
	v_cndmask_b32_e32 v20, v10, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v21
	v_cndmask_b32_e32 v20, v20, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, v20, v13, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v21
	v_cndmask_b32_e32 v20, v20, v14, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, v20, v15, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 6, v21
	v_cndmask_b32_e32 v20, v20, v16, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 7, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, v20, v17, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 8, v21
	v_cndmask_b32_e32 v20, v20, v18, vcc_lo
	v_add_co_u32 v26, vcc_lo, s12, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s13, v27, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 9, v21
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v20, v20, v19, vcc_lo
	v_add_co_u32 v24, vcc_lo, s10, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s11, v25, vcc_lo
	global_store_b32 v[26:27], v20, off
	global_store_b32 v[24:25], v32, off
	v_cmpx_lt_i32_e32 0, v21
	s_cbranch_execz .LBB1_17
; %bb.13:                               ; %.lr.ph112
	v_add_nc_u32_e32 v24, -1, v21
	v_mov_b32_e32 v26, 1
	s_mov_b64 s[4:5], 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v25, null, v24, 1
.LBB1_14:                               ; =>This Inner Loop Header: Depth=1
	s_mov_b32 m0, s4
	s_mov_b32 s12, exec_lo
	v_movrels_b32_e32 v21, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v22, 31, v21
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, s2, v21
	v_add_co_ci_u32_e32 v28, vcc_lo, s3, v22, vcc_lo
	global_load_b32 v27, v[27:28], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	v_add_co_u32 v27, vcc_lo, s10, v27
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v28, vcc_lo, s11, v28, vcc_lo
	global_store_b32 v[27:28], v32, off
	v_cmpx_ne_u32_e64 s4, v24
	s_cbranch_execz .LBB1_16
; %bb.15:                               ;   in Loop: Header=BB1_14 Depth=1
	v_add_co_u32 v21, vcc_lo, s8, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, s9, v22, vcc_lo
	global_store_b32 v[21:22], v26, off
.LBB1_16:                               ;   in Loop: Header=BB1_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v25
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB1_14
.LBB1_17:                               ; %Flow247
	s_or_b32 exec_lo, exec_lo, s7
	v_sub_nc_u32_e32 v10, v34, v23
	s_mov_b32 s7, 0
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, 1, v10
	v_cmpx_lt_i32_e32 0, v10
	s_cbranch_execz .LBB1_22
; %bb.18:                               ; %.lr.ph114
	v_add_nc_u32_e32 v12, -1, v10
	v_mov_b32_e32 v14, 1
	s_mov_b64 s[4:5], 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v13, null, v12, 1
.LBB1_19:                               ; =>This Inner Loop Header: Depth=1
	s_mov_b32 m0, s4
	s_mov_b32 s12, exec_lo
	v_movrels_b32_e32 v10, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v16, vcc_lo, s3, v11, vcc_lo
	global_load_b32 v15, v[15:16], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	v_add_co_u32 v15, vcc_lo, s10, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v16, vcc_lo
	global_store_b32 v[15:16], v32, off
	v_cmpx_ne_u32_e64 s4, v12
	s_cbranch_execz .LBB1_21
; %bb.20:                               ;   in Loop: Header=BB1_19 Depth=1
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	global_store_b32 v[10:11], v14, off
.LBB1_21:                               ;   in Loop: Header=BB1_19 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v13
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_19
.LBB1_22:                               ; %Flow245
	s_or_b32 exec_lo, exec_lo, s6
	v_mov_b32_e32 v0, 1
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_ne_u32_e32 0, v20
	s_cbranch_execz .LBB1_24
; %bb.23:
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[20:21]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v5, v[0:1], off
	v_lshlrev_b32_e32 v0, 1, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_or_b32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s14, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v5, off
.LBB1_24:                               ; %._crit_edge115._crit_edge
	s_or_b32 exec_lo, exec_lo, s4
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	global_store_b32 v[0:1], v20, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3lcaPiS_S_S_S_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z3lcaPiS_S_S_S_S_S_S_i, .Lfunc_end1-_Z3lcaPiS_S_S_S_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1608
; NumSgprs: 20
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z4lca1PiS_S_S_S_S_S_S_ii ; -- Begin function _Z4lca1PiS_S_S_S_S_S_S_ii
	.globl	_Z4lca1PiS_S_S_S_S_S_S_ii
	.p2align	8
	.type	_Z4lca1PiS_S_S_S_S_S_S_ii,@function
_Z4lca1PiS_S_S_S_S_S_S_ii:              ; @_Z4lca1PiS_S_S_S_S_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b128 s[4:7], s[0:1], 0x38
	s_mov_b32 s13, 0
	s_mov_b32 s12, exec_lo
                                        ; implicit-def: $vgpr9
	s_load_b128 s[8:11], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[31:32], null, s15, s2, v[0:1]
	s_load_b64 s[2:3], s[0:1], 0x18
	v_mov_b32_e32 v32, 0
	v_lshl_add_u32 v0, v31, 1, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b96 v[28:30], v[0:1], off
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v0, 1, v28
	v_lshlrev_b32_e32 v2, 1, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v4, v[0:1], off offset:4
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v12, v[0:1], off offset:4
	s_waitcnt vmcnt(1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v4
	v_cndmask_b32_e64 v0, 0, s6, vcc_lo
	v_add_nc_u32_e32 v10, v0, v28
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB2_12
; %bb.1:                                ; %.lr.ph.preheader
	s_add_u32 s14, s4, 4
	s_addc_u32 s15, s5, 0
	s_mov_b64 s[2:3], 0
                                        ; implicit-def: $vgpr0
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $vgpr11
	v_cmpx_le_i32_e64 s6, v10
	s_xor_b32 s16, exec_lo, s16
	s_cbranch_execz .LBB2_4
; %bb.3:                                ; %.critedge133
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_subrev_nc_u32_e32 v13, s6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s10, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
	global_load_b32 v11, v[13:14], off
.LBB2_4:                                ; %Flow290
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_and_not1_saveexec_b32 s16, s16
	s_cbranch_execz .LBB2_10
; %bb.5:                                ;   in Loop: Header=BB2_2 Depth=1
	v_lshlrev_b32_e32 v13, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s14, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v14, vcc_lo
	global_load_b32 v11, v[13:14], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, -1, v11
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s17, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s17, exec_lo, s17
; %bb.6:                                ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v11, s6, v10
; %bb.7:                                ; %Flow288
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_and_not1_saveexec_b32 s17, s17
	s_cbranch_execz .LBB2_9
; %bb.8:                                ;   in Loop: Header=BB2_2 Depth=1
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[13:14], 2, v[10:11]
	v_add_co_u32 v13, vcc_lo, s10, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
	global_load_b32 v11, v[13:14], off
.LBB2_9:                                ; %Flow289
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
.LBB2_10:                               ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_mov_b32 m0, s2
	s_add_u32 s2, s2, 1
	v_movreld_b32_e32 v0, v10
	v_mov_b32_e32 v32, s2
	v_mov_b32_e32 v10, v11
	s_addc_u32 s3, s3, 0
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB2_2
; %bb.11:                               ; %Flow291
	s_or_b32 exec_lo, exec_lo, s13
.LBB2_12:                               ; %Flow292
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, -1, v12
	s_mov_b32 s3, 0
	s_mov_b32 s2, exec_lo
	v_mov_b32_e32 v33, 0
	v_cndmask_b32_e64 v10, 0, s6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v29
                                        ; implicit-def: $vgpr29
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB2_24
; %bb.13:                               ; %.lr.ph146.preheader
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_mov_b32 s12, 0
                                        ; implicit-def: $vgpr20
.LBB2_14:                               ; %.lr.ph146
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s13, exec_lo
                                        ; implicit-def: $vgpr11
	v_cmpx_le_i32_e64 s6, v10
	s_xor_b32 s13, exec_lo, s13
	s_cbranch_execz .LBB2_16
; %bb.15:                               ; %.critedge135
                                        ;   in Loop: Header=BB2_14 Depth=1
	v_subrev_nc_u32_e32 v11, s6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s10, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
	global_load_b32 v11, v[11:12], off
.LBB2_16:                               ; %Flow285
                                        ;   in Loop: Header=BB2_14 Depth=1
	s_and_not1_saveexec_b32 s13, s13
	s_cbranch_execz .LBB2_22
; %bb.17:                               ;   in Loop: Header=BB2_14 Depth=1
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v11, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s4, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	global_load_b32 v11, v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, -1, v11
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s14, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s14
; %bb.18:                               ;   in Loop: Header=BB2_14 Depth=1
	v_add_nc_u32_e32 v11, s6, v10
; %bb.19:                               ; %Flow283
                                        ;   in Loop: Header=BB2_14 Depth=1
	s_and_not1_saveexec_b32 s14, s14
	s_cbranch_execz .LBB2_21
; %bb.20:                               ;   in Loop: Header=BB2_14 Depth=1
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 2, v[10:11]
	v_add_co_u32 v11, vcc_lo, s10, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
	global_load_b32 v11, v[11:12], off
.LBB2_21:                               ; %Flow284
                                        ;   in Loop: Header=BB2_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB2_22:                               ;   in Loop: Header=BB2_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_mov_b32 m0, s12
	s_add_i32 s12, s12, 1
	v_movreld_b32_e32 v20, v10
	v_dual_mov_b32 v33, s12 :: v_dual_mov_b32 v10, v11
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_14
; %bb.23:                               ; %Flow286
	s_or_b32 exec_lo, exec_lo, s3
.LBB2_24:                               ; %Flow287
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_ne_u32_e32 vcc_lo, 9, v32
	s_mov_b32 s2, 0
	s_mov_b32 s3, 0
                                        ; implicit-def: $sgpr4
	v_cndmask_b32_e32 v19, 0, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 8, v32
	v_cndmask_b32_e32 v18, 0, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 7, v32
	v_cndmask_b32_e32 v17, 0, v7, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 6, v32
	v_cndmask_b32_e32 v16, 0, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 5, v32
	v_cndmask_b32_e32 v15, 0, v5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 4, v32
	v_cndmask_b32_e32 v14, 0, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 3, v32
	v_cndmask_b32_e32 v13, 0, v3, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 2, v32
	v_cndmask_b32_e32 v12, 0, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 1, v32
	v_cndmask_b32_e32 v11, 0, v1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v32
	v_cndmask_b32_e32 v10, 0, v0, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 9, v33
	v_cndmask_b32_e32 v9, 0, v29, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 8, v33
	v_cndmask_b32_e32 v8, 0, v28, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 7, v33
	v_cndmask_b32_e32 v7, 0, v27, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 6, v33
	v_cndmask_b32_e32 v6, 0, v26, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 5, v33
	v_cndmask_b32_e32 v5, 0, v25, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 4, v33
	v_cndmask_b32_e32 v4, 0, v24, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 3, v33
	v_cndmask_b32_e32 v3, 0, v23, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 2, v33
	v_cndmask_b32_e32 v2, 0, v22, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 1, v33
	v_min_u32_e32 v22, v32, v33
	v_cndmask_b32_e32 v1, 0, v21, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v33
	v_dual_mov_b32 v21, v33 :: v_dual_cndmask_b32 v0, 0, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v20, 1, v22
	v_mov_b32_e32 v22, v32
.LBB2_25:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v22
	s_or_b32 s4, s4, exec_lo
	v_cndmask_b32_e32 v23, v10, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v21
	v_cndmask_b32_e32 v24, v0, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v21
	v_cndmask_b32_e32 v24, v24, v2, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v13, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v21
	v_cndmask_b32_e32 v24, v24, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v14, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v21
	v_cndmask_b32_e32 v24, v24, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v15, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v21
	v_cndmask_b32_e32 v24, v24, v5, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 6, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v16, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 6, v21
	v_cndmask_b32_e32 v24, v24, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 7, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v17, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 7, v21
	v_cndmask_b32_e32 v24, v24, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 8, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 8, v21
	v_cndmask_b32_e32 v24, v24, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 9, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v23, v19, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 9, v21
	v_cndmask_b32_e32 v24, v24, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, v23, v24
	v_mov_b32_e32 v23, s3
	s_and_saveexec_b32 s5, vcc_lo
; %bb.26:                               ;   in Loop: Header=BB2_25 Depth=1
	s_add_i32 s3, s3, 1
	v_dual_mov_b32 v23, v20 :: v_dual_add_nc_u32 v22, -1, v22
	v_cmp_eq_u32_e32 vcc_lo, s3, v20
	v_add_nc_u32_e32 v21, -1, v21
	s_and_not1_b32 s4, s4, exec_lo
	s_and_b32 s10, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s10
; %bb.27:                               ; %Flow282
                                        ;   in Loop: Header=BB2_25 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, exec_lo, s4
	s_or_b32 s2, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_25
; %bb.28:                               ; %.critedge
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b64 s[2:3], s[0:1], 0x28
	v_ashrrev_i32_e32 v21, 31, v30
	v_mov_b32_e32 v20, v30
	v_sub_nc_u32_e32 v22, v32, v23
	s_mov_b32 s1, 0
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_nc_u32_e32 v24, 1, v22
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, s2, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
	global_store_b32 v[20:21], v31, off
	v_cmpx_lt_i32_e32 0, v24
	s_cbranch_execz .LBB2_35
; %bb.29:                               ; %.lr.ph152
	s_sub_i32 s11, s7, s6
	s_mov_b64 s[4:5], 0
.LBB2_30:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s4
	s_mov_b32 s0, exec_lo
	v_movrels_b32_e32 v21, v10
                                        ; implicit-def: $vgpr20
	v_cmpx_le_i32_e64 s6, v21
	s_xor_b32 s0, exec_lo, s0
; %bb.31:                               ;   in Loop: Header=BB2_30 Depth=1
	v_add_nc_u32_e32 v20, s11, v21
                                        ; implicit-def: $vgpr21
; %bb.32:                               ; %Flow279
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB2_34
; %bb.33:                               ;   in Loop: Header=BB2_30 Depth=1
	v_ashrrev_i32_e32 v22, 31, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 2, v[21:22]
	v_add_co_u32 v20, vcc_lo, s8, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, s9, v21, vcc_lo
	global_load_b32 v20, v[20:21], off
.LBB2_34:                               ;   in Loop: Header=BB2_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v21, 31, v20
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_ge_i32_e32 vcc_lo, s4, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	s_or_b32 s1, vcc_lo, s1
	v_add_co_u32 v20, s0, s2, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v21, s0, s3, v21, s0
	global_store_b32 v[20:21], v31, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_30
.LBB2_35:                               ; %Flow281
	s_or_b32 exec_lo, exec_lo, s10
	v_sub_nc_u32_e32 v10, v33, v23
	s_mov_b32 s1, 0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, 1, v10
	v_cmpx_lt_i32_e32 0, v13
	s_cbranch_execz .LBB2_42
; %bb.36:                               ; %.lr.ph154
	s_sub_i32 s7, s7, s6
	s_mov_b64 s[4:5], 0
.LBB2_37:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s4
	s_mov_b32 s0, exec_lo
	v_movrels_b32_e32 v11, v0
                                        ; implicit-def: $vgpr10
	v_cmpx_le_i32_e64 s6, v11
	s_xor_b32 s0, exec_lo, s0
; %bb.38:                               ;   in Loop: Header=BB2_37 Depth=1
	v_add_nc_u32_e32 v10, s7, v11
                                        ; implicit-def: $vgpr11
; %bb.39:                               ; %Flow
                                        ;   in Loop: Header=BB2_37 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB2_41
; %bb.40:                               ;   in Loop: Header=BB2_37 Depth=1
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[11:12]
	v_add_co_u32 v10, vcc_lo, s8, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	global_load_b32 v10, v[10:11], off
.LBB2_41:                               ;   in Loop: Header=BB2_37 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_ge_i32_e32 vcc_lo, s4, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_or_b32 s1, vcc_lo, s1
	v_add_co_u32 v10, s0, s2, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s0, s3, v11, s0
	global_store_b32 v[10:11], v31, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_37
.LBB2_42:                               ; %._crit_edge155
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4lca1PiS_S_S_S_S_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 34
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z4lca1PiS_S_S_S_S_S_S_ii, .Lfunc_end2-_Z4lca1PiS_S_S_S_S_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1744
; NumSgprs: 20
; NumVgprs: 34
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 34
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8auxGraphPiS_S_iS_S_  ; -- Begin function _Z8auxGraphPiS_S_iS_S_
	.globl	_Z8auxGraphPiS_S_iS_S_
	.p2align	8
	.type	_Z8auxGraphPiS_S_iS_S_,@function
_Z8auxGraphPiS_S_iS_S_:                 ; @_Z8auxGraphPiS_S_iS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x3c
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_mov_b32 s2, exec_lo
	global_load_b32 v0, v[0:1], off
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s8, s[0:1], 0x18
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v0
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, s8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_store_b32 v[1:2], v3, off
.LBB3_2:                                ; %Flow57
	s_or_saveexec_b32 s9, s2
	s_load_b128 s[0:3], s[0:1], 0x20
	s_xor_b32 exec_lo, exec_lo, s9
	s_cbranch_execz .LBB3_6
; %bb.3:
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB3_5
; %bb.4:
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s11
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u32 v1, v2, s[0:1]
.LBB3_5:                                ; %Flow56
	s_or_b32 exec_lo, exec_lo, s10
.LBB3_6:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshlrev_b32_e32 v1, 1, v0
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s0, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v1, v2
	s_cbranch_execz .LBB3_13
; %bb.7:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v4, 31, v1
	v_mov_b32_e32 v3, v1
	s_mov_b32 s1, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v5, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
                                        ; implicit-def: $sgpr4
.LBB3_8:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	global_load_b32 v5, v[5:6], off
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v5, v0
                                        ; implicit-def: $vgpr5_vgpr6
	s_and_saveexec_b32 s5, vcc_lo
; %bb.9:                                ;   in Loop: Header=BB3_8 Depth=1
	v_add_nc_u32_e32 v1, 1, v1
	v_add_co_u32 v5, s0, v3, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v6, s0, 0, v4, s0
	v_cmp_ge_i32_e32 vcc_lo, v1, v2
	s_and_not1_b32 s0, s4, exec_lo
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s0, s4
; %bb.10:                               ; %Flow54
                                        ;   in Loop: Header=BB3_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s4
	s_or_b32 s1, s0, s1
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s2, s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_8
; %bb.11:                               ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB3_13
; %bb.12:
	v_add_nc_u32_e32 v0, s8, v0
	global_store_b32 v[3:4], v0, off
.LBB3_13:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8auxGraphPiS_S_iS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z8auxGraphPiS_S_iS_S_, .Lfunc_end3-_Z8auxGraphPiS_S_iS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 620
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12markArtPointPiS_S_S_S_S_ ; -- Begin function _Z12markArtPointPiS_S_S_S_S_
	.globl	_Z12markArtPointPiS_S_S_S_S_
	.p2align	8
	.type	_Z12markArtPointPiS_S_S_S_S_,@function
_Z12markArtPointPiS_S_S_S_S_:           ; @_Z12markArtPointPiS_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_mov_b32 s18, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s12, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
	s_load_b128 s[12:15], s[0:1], 0x20
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_load_b32 v30, v[0:1], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v31, 31, v30
	v_lshlrev_b64 v[28:29], 2, v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v28
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v29, vcc_lo
	s_mov_b32 s6, exec_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v1
	s_cbranch_execz .LBB4_4
; %bb.1:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v3, 31, v0
	v_mov_b32_e32 v2, v0
	v_add_nc_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s4, 0
                                        ; implicit-def: $sgpr5
.LBB4_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v[2:3], off
	v_add_co_u32 v2, s1, v2, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s1, 0, v3, s1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v0, v1
	v_add_nc_u32_e32 v0, 1, v0
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e64 s0, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s0, vcc_lo
	s_and_b32 s1, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s1, s4
	s_and_not1_b32 s1, s5, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s5, s1, s0
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB4_2
; %bb.3:                                ; %Flow479
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s18, s5, exec_lo
.LBB4_4:                                ; %Flow480
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt lgkmcnt(0)
	s_load_b32 s19, s[14:15], 0x0
	s_load_b64 s[2:3], s[2:3], 0x50
	v_mbcnt_lo_u32_b32 v31, -1, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v31
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_10
; %bb.5:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[5:6], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB4_9
; %bb.6:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB4_7:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[10:11], v0, s[2:3]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB4_7
; %bb.8:                                ; %Flow476
	s_or_b32 exec_lo, exec_lo, s5
.LBB4_9:                                ; %Flow478
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_10:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[2:3] offset:40
	global_load_b128 v[0:3], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB4_12
; %bb.11:
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, v5
	s_add_i32 s12, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v11, vcc_lo, s12, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB4_12:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v13, s23
	v_dual_mov_b32 v11, s21 :: v_dual_mov_b32 v12, s22
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_20
; %bb.13:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s5, v3
	v_and_b32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB4_16
; %bb.14:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s12, 0
.LBB4_15:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB4_15
.LBB4_16:                               ; %Flow474
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v5, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v4, s12, 0
	global_load_b64 v[2:3], v5, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB4_18
; %bb.17:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB4_18:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB4_20
; %bb.19:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_20:                               ; %Flow475
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB4_21:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_23
; %bb.22:                               ;   in Loop: Header=BB4_21 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB4_23:                               ;   in Loop: Header=BB4_21 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB4_25
; %bb.24:                               ;   in Loop: Header=BB4_21 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB4_26
.LBB4_25:                               ;   in Loop: Header=BB4_21 Depth=1
	s_mov_b32 s1, -1
.LBB4_26:                               ; %Flow469
                                        ;   in Loop: Header=BB4_21 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_21
; %bb.27:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_31
; %bb.28:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_31
; %bb.29:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB4_30:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_30
.LBB4_31:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB4_117
; %bb.32:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v33, 0 :: v_dual_and_b32 v34, 2, v0
	v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v2, -3, v0
	v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
	s_mov_b64 s[6:7], 37
.LBB4_33:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_36 Depth 2
                                        ;     Child Loop BB4_43 Depth 2
                                        ;     Child Loop BB4_51 Depth 2
                                        ;     Child Loop BB4_59 Depth 2
                                        ;     Child Loop BB4_67 Depth 2
                                        ;     Child Loop BB4_75 Depth 2
                                        ;     Child Loop BB4_83 Depth 2
                                        ;     Child Loop BB4_91 Depth 2
                                        ;     Child Loop BB4_99 Depth 2
                                        ;     Child Loop BB4_105 Depth 2
                                        ;     Child Loop BB4_114 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[6:7], 56
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr21
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s8, s6, 56
	s_cselect_b32 s9, s7, 0
	s_cmp_gt_u32 s8, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB4_38
; %bb.34:                               ;   in Loop: Header=BB4_33 Depth=1
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB4_37
; %bb.35:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_lshl_b64 s[0:1], s[8:9], 3
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], s[4:5]
.LBB4_36:                               ; %.preheader31.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v33, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v32, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[32:33]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s0, s12
	v_or_b32_e32 v10, v4, v10
	v_or_b32_e32 v11, v5, v11
	s_cbranch_scc1 .LBB4_36
.LBB4_37:                               ; %Flow445
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s21, 0
.LBB4_38:                               ; %Flow447
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB4_40
; %bb.39:                               ;   in Loop: Header=BB4_33 Depth=1
	global_load_b64 v[10:11], v33, s[4:5]
	s_add_i32 s21, s8, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB4_40:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB4_45
; %bb.41:                               ;   in Loop: Header=BB4_33 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB4_44
; %bb.42:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB4_43:                               ; %.preheader29.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v33, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v32, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[32:33]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s21, s16
	v_or_b32_e32 v12, v4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v5, v13
	s_cbranch_scc1 .LBB4_43
.LBB4_44:                               ; %Flow440
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s20, 0
	s_branch .LBB4_46
.LBB4_45:                               ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr20
.LBB4_46:                               ; %Flow442
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB4_48
; %bb.47:                               ;   in Loop: Header=BB4_33 Depth=1
	global_load_b64 v[12:13], v33, s[0:1]
	s_add_i32 s20, s21, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB4_48:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB4_53
; %bb.49:                               ;   in Loop: Header=BB4_33 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB4_52
; %bb.50:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB4_51:                               ; %.preheader27.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v33, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v32, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[32:33]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s20, s16
	v_or_b32_e32 v14, v4, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v5, v15
	s_cbranch_scc1 .LBB4_51
.LBB4_52:                               ; %Flow435
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s21, 0
	s_branch .LBB4_54
.LBB4_53:                               ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr21
.LBB4_54:                               ; %Flow437
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB4_56
; %bb.55:                               ;   in Loop: Header=BB4_33 Depth=1
	global_load_b64 v[14:15], v33, s[0:1]
	s_add_i32 s21, s20, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB4_56:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB4_61
; %bb.57:                               ;   in Loop: Header=BB4_33 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB4_60
; %bb.58:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB4_59:                               ; %.preheader25.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v33, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v32, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[32:33]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s21, s16
	v_or_b32_e32 v16, v4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v5, v17
	s_cbranch_scc1 .LBB4_59
.LBB4_60:                               ; %Flow430
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s20, 0
	s_branch .LBB4_62
.LBB4_61:                               ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr20
.LBB4_62:                               ; %Flow432
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB4_64
; %bb.63:                               ;   in Loop: Header=BB4_33 Depth=1
	global_load_b64 v[16:17], v33, s[0:1]
	s_add_i32 s20, s21, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB4_64:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB4_69
; %bb.65:                               ;   in Loop: Header=BB4_33 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB4_68
; %bb.66:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB4_67:                               ; %.preheader23.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v33, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v32, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[32:33]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s20, s16
	v_or_b32_e32 v18, v4, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v5, v19
	s_cbranch_scc1 .LBB4_67
.LBB4_68:                               ; %Flow425
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s21, 0
	s_branch .LBB4_70
.LBB4_69:                               ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr21
.LBB4_70:                               ; %Flow427
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB4_72
; %bb.71:                               ;   in Loop: Header=BB4_33 Depth=1
	global_load_b64 v[18:19], v33, s[0:1]
	s_add_i32 s21, s20, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB4_72:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_cmp_gt_u32 s21, 7
	s_cbranch_scc1 .LBB4_77
; %bb.73:                               ;   in Loop: Header=BB4_33 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s21, 0
	s_cbranch_scc1 .LBB4_76
; %bb.74:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], 0
.LBB4_75:                               ; %.preheader21.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s0, s16
	s_addc_u32 s23, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v33, s[22:23]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v32, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[32:33]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s21, s16
	v_or_b32_e32 v20, v4, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v5, v21
	s_cbranch_scc1 .LBB4_75
.LBB4_76:                               ; %Flow420
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s20, 0
	s_branch .LBB4_78
.LBB4_77:                               ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr20
.LBB4_78:                               ; %Flow422
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB4_80
; %bb.79:                               ;   in Loop: Header=BB4_33 Depth=1
	global_load_b64 v[20:21], v33, s[0:1]
	s_add_i32 s20, s21, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB4_80:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_cmp_gt_u32 s20, 7
	s_cbranch_scc1 .LBB4_85
; %bb.81:                               ;   in Loop: Header=BB4_33 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc1 .LBB4_84
; %bb.82:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[16:17], s[0:1]
.LBB4_83:                               ; %.preheader.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v33, s[16:17]
	s_add_i32 s20, s20, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v32, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[32:33]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s20, 0
	v_or_b32_e32 v22, v4, v22
	v_or_b32_e32 v23, v5, v23
	s_cbranch_scc1 .LBB4_83
.LBB4_84:                               ; %Flow415
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, 0
	s_branch .LBB4_86
.LBB4_85:                               ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s12, -1
.LBB4_86:                               ; %Flow417
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB4_88
; %bb.87:                               ;   in Loop: Header=BB4_33 Depth=1
	global_load_b64 v[22:23], v33, s[0:1]
.LBB4_88:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB4_33 Depth=1
	v_mov_b32_e32 v32, v31
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v32
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_94
; %bb.89:                               ;   in Loop: Header=BB4_33 Depth=1
	global_load_b64 v[26:27], v33, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v33, s[2:3] offset:40
	global_load_b64 v[8:9], v33, s[2:3]
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v27
	v_and_b32_e32 v4, v4, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v24, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v24, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v33, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[26:27]
	s_cbranch_execz .LBB4_93
; %bb.90:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s13, 0
.LBB4_91:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v33, s[2:3] offset:40
	global_load_b64 v[24:25], v33, s[2:3]
	v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v26
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[24:25]
	v_and_b32_e32 v24, v9, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v24, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v33, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[26:27]
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB4_91
; %bb.92:                               ; %Flow410
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB4_93:                               ; %Flow412
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
.LBB4_94:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v33, s[2:3] offset:40
	global_load_b128 v[24:27], v33, s[2:3]
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_mov_b32 s22, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v8
	v_readfirstlane_b32 s17, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[12:13], s[16:17]
	s_mul_i32 s1, s17, 24
	s_mul_hi_u32 s20, s16, 24
	s_mul_i32 s21, s16, 24
	s_and_saveexec_b32 s23, s0
	s_cbranch_execz .LBB4_96
; %bb.95:                               ;   in Loop: Header=BB4_33 Depth=1
	v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, v33
	s_add_i32 s22, s20, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v24, s21
	v_add_co_ci_u32_e32 v9, vcc_lo, s22, v25, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB4_96:                               ;   in Loop: Header=BB4_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
	v_or_b32_e32 v4, 0, v3
	v_or_b32_e32 v5, v2, v34
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s22, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s22, s22, 28
	v_dual_cndmask_b32 v9, v4, v3 :: v_dual_cndmask_b32 v4, v5, v2
	v_lshlrev_b64 v[2:3], 6, v[32:33]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v26, s16
	v_add_co_ci_u32_e32 v27, vcc_lo, s17, v27, vcc_lo
	s_and_b32 s22, s22, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v5, v2
	v_and_or_b32 v8, 0xffffff1f, v4, s22
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v3, vcc_lo
	s_clause 0x3
	global_store_b128 v[26:27], v[8:11], off
	global_store_b128 v[26:27], v[12:15], off offset:16
	global_store_b128 v[26:27], v[16:19], off offset:32
	global_store_b128 v[26:27], v[20:23], off offset:48
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB4_104
; %bb.97:                               ;   in Loop: Header=BB4_33 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v33, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v33, s[2:3] offset:40
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s22, v2
	v_readfirstlane_b32 s23, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[22:23], s[22:23], s[12:13]
	s_mul_i32 s17, s23, 24
	s_mul_hi_u32 s23, s22, 24
	s_mul_i32 s22, s22, 24
	s_add_i32 s23, s23, s17
	v_add_co_u32 v8, vcc_lo, v24, s22
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v25, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v33, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB4_100
; %bb.98:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s22, 0
.LBB4_99:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s12 :: v_dual_mov_b32 v3, s13
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v33, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s22, vcc_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB4_99
.LBB4_100:                              ; %Flow408
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[2:3], v33, s[2:3] offset:16
	s_mov_b32 s22, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v4, s22, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB4_102
; %bb.101:                              ;   in Loop: Header=BB4_33 Depth=1
	s_bcnt1_i32_b32 s22, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v32, s22
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[32:33], off offset:8
.LBB4_102:                              ;   in Loop: Header=BB4_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB4_104
; %bb.103:                              ;   in Loop: Header=BB4_33 Depth=1
	global_load_b32 v32, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v32
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[32:33], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_104:                              ; %Flow409
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s20, s20, s1
	v_add_co_u32 v2, vcc_lo, v24, s21
	v_add_co_ci_u32_e32 v3, vcc_lo, s20, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB4_105:                              ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_107
; %bb.106:                              ;   in Loop: Header=BB4_105 Depth=2
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB4_107:                              ;   in Loop: Header=BB4_105 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB4_109
; %bb.108:                              ;   in Loop: Header=BB4_105 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB4_110
.LBB4_109:                              ;   in Loop: Header=BB4_105 Depth=2
	s_mov_b32 s1, -1
.LBB4_110:                              ; %Flow403
                                        ;   in Loop: Header=BB4_105 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_105
; %bb.111:                              ;   in Loop: Header=BB4_33 Depth=1
	global_load_b128 v[2:5], v[26:27], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_115
; %bb.112:                              ;   in Loop: Header=BB4_33 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v33, s[2:3] offset:40
	global_load_b64 v[12:13], v33, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v33, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v14, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v14, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
	v_and_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v8, v4
	v_mul_hi_u32 v14, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v10, v4
	v_mov_b32_e32 v10, v12
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo
	v_mov_b32_e32 v11, v13
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v33, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_115
; %bb.113:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_mov_b32 s0, 0
.LBB4_114:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB4_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v33, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_114
.LBB4_115:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB4_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s6, s6, s8
	s_subb_u32 s7, s7, s9
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc1 .LBB4_33
; %bb.116:                              ; %Flow448
	s_mov_b32 s0, 0
	s_branch .LBB4_118
.LBB4_117:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2_vgpr3
.LBB4_118:                              ; %Flow463
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB4_147
; %bb.119:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, v31
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_125
; %bb.120:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB4_124
; %bb.121:                              ; %.preheader3.i.i.i38.preheader
	s_mov_b32 s5, 0
.LBB4_122:                              ; %.preheader3.i.i.i38
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB4_122
; %bb.123:                              ; %Flow460
	s_or_b32 exec_lo, exec_lo, s5
.LBB4_124:                              ; %Flow462
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_125:                              ; %.loopexit4.i.i.i33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB4_127
; %bb.126:
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, v3
	s_add_i32 s12, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB4_127:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v11, s23
	v_dual_mov_b32 v9, s21 :: v_dual_mov_b32 v10, s22
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_135
; %bb.128:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
	v_mov_b32_e32 v12, s5
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s7, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s7
	v_add_co_u32 v8, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB4_131
; %bb.129:                              ; %.preheader1.i.i.i36.preheader
	s_mov_b32 s12, 0
.LBB4_130:                              ; %.preheader1.i.i.i36
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB4_130
.LBB4_131:                              ; %Flow458
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB4_133
; %bb.132:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB4_133:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB4_135
; %bb.134:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_135:                              ; %Flow459
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB4_136:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_138
; %bb.137:                              ;   in Loop: Header=BB4_136 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB4_138:                              ;   in Loop: Header=BB4_136 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB4_140
; %bb.139:                              ;   in Loop: Header=BB4_136 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB4_141
.LBB4_140:                              ;   in Loop: Header=BB4_136 Depth=1
	s_mov_b32 s1, -1
.LBB4_141:                              ; %Flow453
                                        ;   in Loop: Header=BB4_136 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_136
; %bb.142:
	global_load_b128 v[2:5], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_146
; %bb.143:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11
	v_and_b32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v4, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v6, v0
	v_mov_b32_e32 v6, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_mov_b32_e32 v7, v10
	global_store_b64 v[0:1], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v8, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_146
; %bb.144:                              ; %.preheader.i.i.i35.preheader
	s_mov_b32 s0, 0
.LBB4_145:                              ; %.preheader.i.i.i35
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7]
	v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_145
.LBB4_146:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB4_147:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v4, v31
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v4
	v_cmp_eq_u32_e64 s0, s0, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_153
; %bb.148:
	v_mov_b32_e32 v5, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[8:9], v5, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v5, s[2:3] offset:40
	global_load_b64 v[6:7], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v8
	v_and_b32_e32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v10, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v5, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[8:9]
	s_cbranch_execz .LBB4_152
; %bb.149:                              ; %.preheader3.i.i.i45.preheader
	s_mov_b32 s5, 0
.LBB4_150:                              ; %.preheader3.i.i.i45
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v5, s[2:3] offset:40
	global_load_b64 v[10:11], v5, s[2:3]
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v6, 24, v[10:11]
	v_and_b32_e32 v10, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v10, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v5, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB4_150
; %bb.151:                              ; %Flow396
	s_or_b32 exec_lo, exec_lo, s5
.LBB4_152:                              ; %Flow398
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_153:                              ; %.loopexit4.i.i.i39
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v5, s[2:3] offset:40
	global_load_b128 v[6:9], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB4_155
; %bb.154:
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, v5
	s_add_i32 s12, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v7, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[0:1], v[10:13], off offset:8
.LBB4_155:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v4, v0
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v2, 0xffffff1f, v2, 32
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v1, vcc_lo
	v_mov_b32_e32 v4, v30
	v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v13, s23
	v_dual_mov_b32 v11, s21 :: v_dual_mov_b32 v12, s22
	s_clause 0x3
	global_store_b128 v[8:9], v[2:5], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_163
; %bb.156:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
	v_mov_b32_e32 v12, s5
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s7, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s7
	v_add_co_u32 v4, vcc_lo, v6, s12
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v7, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[4:5], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB4_159
; %bb.157:                              ; %.preheader1.i.i.i43.preheader
	s_mov_b32 s12, 0
.LBB4_158:                              ; %.preheader1.i.i.i43
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB4_158
.LBB4_159:                              ; %Flow394
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB4_161
; %bb.160:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB4_161:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB4_163
; %bb.162:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_163:                              ; %Flow395
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB4_164:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_166
; %bb.165:                              ;   in Loop: Header=BB4_164 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB4_166:                              ;   in Loop: Header=BB4_164 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB4_168
; %bb.167:                              ;   in Loop: Header=BB4_164 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB4_169
.LBB4_168:                              ;   in Loop: Header=BB4_164 Depth=1
	s_mov_b32 s1, -1
.LBB4_169:                              ; %Flow389
                                        ;   in Loop: Header=BB4_164 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_164
; %bb.170:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_174
; %bb.171:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_174
; %bb.172:                              ; %.preheader.i.i.i42.preheader
	s_mov_b32 s0, 0
.LBB4_173:                              ; %.preheader.i.i.i42
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_173
.LBB4_174:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v2, v31
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_180
; %bb.175:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB4_179
; %bb.176:                              ; %.preheader3.i.i.i52.preheader
	s_mov_b32 s5, 0
.LBB4_177:                              ; %.preheader3.i.i.i52
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB4_177
; %bb.178:                              ; %Flow382
	s_or_b32 exec_lo, exec_lo, s5
.LBB4_179:                              ; %Flow384
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_180:                              ; %.loopexit4.i.i.i46
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB4_182
; %bb.181:
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, v3
	s_add_i32 s12, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB4_182:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, s19
	v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v11, s23
	v_dual_mov_b32 v9, s21 :: v_dual_mov_b32 v10, s22
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_190
; %bb.183:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
	v_mov_b32_e32 v12, s5
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s7, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s7
	v_add_co_u32 v8, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB4_186
; %bb.184:                              ; %.preheader1.i.i.i50.preheader
	s_mov_b32 s12, 0
.LBB4_185:                              ; %.preheader1.i.i.i50
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB4_185
.LBB4_186:                              ; %Flow380
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB4_188
; %bb.187:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB4_188:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB4_190
; %bb.189:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_190:                              ; %Flow381
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB4_191:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_193
; %bb.192:                              ;   in Loop: Header=BB4_191 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB4_193:                              ;   in Loop: Header=BB4_191 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB4_195
; %bb.194:                              ;   in Loop: Header=BB4_191 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB4_196
.LBB4_195:                              ;   in Loop: Header=BB4_191 Depth=1
	s_mov_b32 s1, -1
.LBB4_196:                              ; %Flow375
                                        ;   in Loop: Header=BB4_191 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_191
; %bb.197:
	global_load_b64 v[0:1], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_201
; %bb.198:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_201
; %bb.199:                              ; %.preheader.i.i.i49.preheader
	s_mov_b32 s0, 0
.LBB4_200:                              ; %.preheader.i.i.i49
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_200
.LBB4_201:                              ; %__ockl_printf_append_args.exit53
	s_or_b32 exec_lo, exec_lo, s1
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v31
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v31
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_207
; %bb.202:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[7:8], v4, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v4, s[2:3] offset:40
	global_load_b64 v[5:6], v4, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v8
	v_and_b32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v5, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v6, v3, vcc_lo
	global_load_b64 v[5:6], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[7:8]
	s_cbranch_execz .LBB4_206
; %bb.203:                              ; %.preheader3.i.i.i60.preheader
	s_mov_b32 s5, 0
.LBB4_204:                              ; %.preheader3.i.i.i60
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[2:3] offset:40
	global_load_b64 v[9:10], v4, s[2:3]
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v5, 24, v[9:10]
	v_and_b32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[3:4]
	v_mov_b32_e32 v3, v5
	global_load_b64 v[5:6], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB4_204
; %bb.205:                              ; %Flow368
	s_or_b32 exec_lo, exec_lo, s5
.LBB4_206:                              ; %Flow370
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_207:                              ; %.loopexit4.i.i.i54
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v32, 0
	v_readfirstlane_b32 s4, v2
	v_readfirstlane_b32 s5, v3
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[8:9], v32, s[2:3] offset:40
	global_load_b128 v[4:7], v32, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB4_209
; %bb.208:
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, v32
	s_add_i32 s12, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v3, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[2:3], v[8:11], off offset:8
.LBB4_209:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[31:32]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v3, v8
	s_mov_b32 s21, s20
	s_mov_b32 s22, s20
	s_mov_b32 s23, s20
	v_cndmask_b32_e64 v2, 0, 1, s18
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo
	v_dual_mov_b32 v3, v32 :: v_dual_mov_b32 v6, s20
	v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s22
	v_mov_b32_e32 v9, s23
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_217
; %bb.210:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
	v_mov_b32_e32 v10, s5
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[4:5]
	s_mul_i32 s7, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s7
	v_add_co_u32 v6, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB4_213
; %bb.211:                              ; %.preheader1.i.i.i58.preheader
	s_mov_b32 s12, 0
.LBB4_212:                              ; %.preheader1.i.i.i58
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB4_212
.LBB4_213:                              ; %Flow366
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB4_215
; %bb.214:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB4_215:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB4_217
; %bb.216:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_217:                              ; %Flow367
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB4_218:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_220
; %bb.219:                              ;   in Loop: Header=BB4_218 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB4_220:                              ;   in Loop: Header=BB4_218 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB4_222
; %bb.221:                              ;   in Loop: Header=BB4_218 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB4_223
.LBB4_222:                              ;   in Loop: Header=BB4_218 Depth=1
	s_mov_b32 s1, -1
.LBB4_223:                              ; %Flow361
                                        ;   in Loop: Header=BB4_218 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_218
; %bb.224:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_228
; %bb.225:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_228
; %bb.226:                              ; %.preheader.i.i.i57.preheader
	s_mov_b32 s0, 0
.LBB4_227:                              ; %.preheader.i.i.i57
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_227
.LBB4_228:                              ; %__ockl_printf_append_args.exit61
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_ne_u32_e32 vcc_lo, 0, v30
	s_mov_b32 s0, 0
	s_and_b32 s1, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s1, s1, -1
	s_and_saveexec_b32 s2, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s2
	s_cbranch_execz .LBB4_232
; %bb.229:
	s_xor_b32 s0, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_xor_b32 s2, s0, -1
	s_mov_b32 s0, 0
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s3
	s_cbranch_execz .LBB4_231
; %bb.230:
	v_mov_b32_e32 v0, 0
	global_load_b32 v0, v0, s[14:15]
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, 1, v0
	s_and_b32 s0, vcc_lo, exec_lo
.LBB4_231:                              ; %Flow356
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
                                        ; implicit-def: $vgpr28_vgpr29
.LBB4_232:                              ; %Flow
	s_or_saveexec_b32 s1, s1
	v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.233:
	v_add_co_u32 v0, vcc_lo, s10, v28
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v29, vcc_lo
	s_or_b32 s0, s0, exec_lo
; %bb.234:                              ; %Flow357
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_236
; %bb.235:                              ; %.sink.split
	v_mov_b32_e32 v2, 1
	global_store_b32 v[0:1], v2, off
.LBB4_236:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12markArtPointPiS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z12markArtPointPiS_S_S_S_S_, .Lfunc_end4-_Z12markArtPointPiS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9924
; NumSgprs: 26
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7findBCCPiS_S_S_S_S_  ; -- Begin function _Z7findBCCPiS_S_S_S_S_
	.globl	_Z7findBCCPiS_S_S_S_S_
	.p2align	8
	.type	_Z7findBCCPiS_S_S_S_S_,@function
_Z7findBCCPiS_S_S_S_S_:                 ; @_Z7findBCCPiS_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x3c
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	s_mov_b32 s2, exec_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v2
	s_cbranch_execz .LBB5_2
; %bb.1:                                ; %.preheader
	s_load_b64 s[0:1], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB5_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7findBCCPiS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z7findBCCPiS_S_S_S_S_, .Lfunc_end5-_Z7findBCCPiS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
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; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"vertex %d rootLCACOUnt %d bridge %d\n"
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	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
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__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
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	.end_amdgpu_metadata
