#include "includes.h"

#define GravConst 6.674e-11
#define EPS 1e-6
#define POINTS_SIZE 10

//struct Point {
//    float x, y, z;
//    float vx = 0, vy = 0, vz = 0;
//    float ax = 0, ay = 0, az = 0;
//    float m;
//};


__device__ inline float sqr(float x) { return x * x; }
__global__ void calc(float* points, float* resPoints, int dt, int size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;

int tix = threadIdx.x;
int steps = gridDim.x;

float fx,fy,fz;

float x, y, z, m, vx, vy, vz, ax, ay, az;

if (idx < size) {
x = points[idx * POINTS_SIZE + 0];
y = points[idx * POINTS_SIZE + 1];
z = points[idx * POINTS_SIZE + 2];
m = points[idx * POINTS_SIZE + 3];
vx = points[idx * POINTS_SIZE + 4];
vy = points[idx * POINTS_SIZE + 5];
vz = points[idx * POINTS_SIZE + 6];
ax = points[idx * POINTS_SIZE + 7];
ay = points[idx * POINTS_SIZE + 8];
az = points[idx * POINTS_SIZE + 9];

for (int iteration = 0; iteration < steps; iteration++) {

__shared__ float cached_points[128 * POINTS_SIZE];

if (iteration * 128 + tix < size)
for (int i = 0; i < POINTS_SIZE; i++)
cached_points[tix * POINTS_SIZE] = points[(iteration * 128 + tix) * POINTS_SIZE + i];
__syncthreads();

if (idx < size) {
fx = fy = fz = 0;
for (int i = 0; i < 128; i++) {
if (iteration * 128 + i < size && iteration * 128 + i != idx) {
float dx = cached_points[i * POINTS_SIZE] - x;
float dy = cached_points[i * POINTS_SIZE + 1] - y;
float dz = cached_points[i * POINTS_SIZE + 2] - z;
float dist = sqrt(dx * dx + dy * dy + dz * dz);
float F = (GravConst * m * cached_points[i * POINTS_SIZE + 3]) / (dist * dist + 0.001f * 0.001f);
fx += F * dx / dist;
fy += F * dy / dist;
fz += F * dz / dist;
}
__syncthreads();
}
resPoints[idx * POINTS_SIZE] = x + vx * dt + (ax * sqr(dt)) / 2;
resPoints[idx * POINTS_SIZE + 1] = y + vy * dt + (ay * sqr(dt)) / 2;
resPoints[idx * POINTS_SIZE + 2] = z + vz * dt + (az * sqr(dt)) / 2;

resPoints[idx * POINTS_SIZE + 3] = m;

resPoints[idx * POINTS_SIZE + 4] = vx + ax * dt;
resPoints[idx * POINTS_SIZE + 5] = vy + ay * dt;
resPoints[idx * POINTS_SIZE + 6] = vz + az * dt;

resPoints[idx * POINTS_SIZE + 7] = fx / m;
resPoints[idx * POINTS_SIZE + 8] = fy / m;
resPoints[idx * POINTS_SIZE + 9] = fz / m;
}
}
}







/*if (idx < size) {
float* forcesArr = forcesCalc(points, idx, size);
resPoints[idx] = points[idx] + points[idx + 4] * dt + (points[idx + 7] * sqr(dt)) / 2;
resPoints[idx + 1] = points[idx + 1] + points[idx + 5] * dt + (points[idx + 8] * sqr(dt)) / 2;
resPoints[idx + 2] = points[idx + 2] + points[idx + 6] * dt + (points[idx + 9] * sqr(dt)) / 2;

resPoints[idx + 3] = points[idx + 3];

resPoints[idx + 4] = points[idx + 4] + points[idx + 7] * dt;
resPoints[idx + 5] = points[idx + 5] + points[idx + 8] * dt;
resPoints[idx + 6] = points[idx + 6] + points[idx + 9] * dt;

resPoints[idx + 7] = forcesArr[0] / points[idx + 3];
resPoints[idx + 8] = forcesArr[1] / points[idx + 3];
resPoints[idx + 9] = forcesArr[2] / points[idx + 3];
}*/
}
	.file	"tmpxft_003a5a5b_00000000-6_calc.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z27__device_stub__Z4calcPfS_iiPfS_ii
	.type	_Z27__device_stub__Z4calcPfS_iiPfS_ii, @function
_Z27__device_stub__Z4calcPfS_iiPfS_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z4calcPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z27__device_stub__Z4calcPfS_iiPfS_ii, .-_Z27__device_stub__Z4calcPfS_iiPfS_ii
	.globl	_Z4calcPfS_ii
	.type	_Z4calcPfS_ii, @function
_Z4calcPfS_ii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z4calcPfS_iiPfS_ii
	.cfi_endproc
.LFE2034:
	.size	_Z4calcPfS_ii, .-_Z4calcPfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z4calcPfS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4calcPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

#define GravConst 6.674e-11
#define EPS 1e-6
#define POINTS_SIZE 10

//struct Point {
//    float x, y, z;
//    float vx = 0, vy = 0, vz = 0;
//    float ax = 0, ay = 0, az = 0;
//    float m;
//};


__device__ inline float sqr(float x) { return x * x; }
__global__ void calc(float* points, float* resPoints, int dt, int size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;

int tix = threadIdx.x;
int steps = gridDim.x;

float fx,fy,fz;

float x, y, z, m, vx, vy, vz, ax, ay, az;

if (idx < size) {
x = points[idx * POINTS_SIZE + 0];
y = points[idx * POINTS_SIZE + 1];
z = points[idx * POINTS_SIZE + 2];
m = points[idx * POINTS_SIZE + 3];
vx = points[idx * POINTS_SIZE + 4];
vy = points[idx * POINTS_SIZE + 5];
vz = points[idx * POINTS_SIZE + 6];
ax = points[idx * POINTS_SIZE + 7];
ay = points[idx * POINTS_SIZE + 8];
az = points[idx * POINTS_SIZE + 9];

for (int iteration = 0; iteration < steps; iteration++) {

__shared__ float cached_points[128 * POINTS_SIZE];

if (iteration * 128 + tix < size)
for (int i = 0; i < POINTS_SIZE; i++)
cached_points[tix * POINTS_SIZE] = points[(iteration * 128 + tix) * POINTS_SIZE + i];
__syncthreads();

if (idx < size) {
fx = fy = fz = 0;
for (int i = 0; i < 128; i++) {
if (iteration * 128 + i < size && iteration * 128 + i != idx) {
float dx = cached_points[i * POINTS_SIZE] - x;
float dy = cached_points[i * POINTS_SIZE + 1] - y;
float dz = cached_points[i * POINTS_SIZE + 2] - z;
float dist = sqrt(dx * dx + dy * dy + dz * dz);
float F = (GravConst * m * cached_points[i * POINTS_SIZE + 3]) / (dist * dist + 0.001f * 0.001f);
fx += F * dx / dist;
fy += F * dy / dist;
fz += F * dz / dist;
}
__syncthreads();
}
resPoints[idx * POINTS_SIZE] = x + vx * dt + (ax * sqr(dt)) / 2;
resPoints[idx * POINTS_SIZE + 1] = y + vy * dt + (ay * sqr(dt)) / 2;
resPoints[idx * POINTS_SIZE + 2] = z + vz * dt + (az * sqr(dt)) / 2;

resPoints[idx * POINTS_SIZE + 3] = m;

resPoints[idx * POINTS_SIZE + 4] = vx + ax * dt;
resPoints[idx * POINTS_SIZE + 5] = vy + ay * dt;
resPoints[idx * POINTS_SIZE + 6] = vz + az * dt;

resPoints[idx * POINTS_SIZE + 7] = fx / m;
resPoints[idx * POINTS_SIZE + 8] = fy / m;
resPoints[idx * POINTS_SIZE + 9] = fz / m;
}
}
}







/*if (idx < size) {
float* forcesArr = forcesCalc(points, idx, size);
resPoints[idx] = points[idx] + points[idx + 4] * dt + (points[idx + 7] * sqr(dt)) / 2;
resPoints[idx + 1] = points[idx + 1] + points[idx + 5] * dt + (points[idx + 8] * sqr(dt)) / 2;
resPoints[idx + 2] = points[idx + 2] + points[idx + 6] * dt + (points[idx + 9] * sqr(dt)) / 2;

resPoints[idx + 3] = points[idx + 3];

resPoints[idx + 4] = points[idx + 4] + points[idx + 7] * dt;
resPoints[idx + 5] = points[idx + 5] + points[idx + 8] * dt;
resPoints[idx + 6] = points[idx + 6] + points[idx + 9] * dt;

resPoints[idx + 7] = forcesArr[0] / points[idx + 3];
resPoints[idx + 8] = forcesArr[1] / points[idx + 3];
resPoints[idx + 9] = forcesArr[2] / points[idx + 3];
}*/
}
	.text
	.file	"calc.hip"
	.globl	_Z19__device_stub__calcPfS_ii   # -- Begin function _Z19__device_stub__calcPfS_ii
	.type	_Z19__device_stub__calcPfS_ii,@function
_Z19__device_stub__calcPfS_ii:          # @_Z19__device_stub__calcPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4calcPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__calcPfS_ii, .Lfunc_end0-_Z19__device_stub__calcPfS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4calcPfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4calcPfS_ii,@object           # @_Z4calcPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z4calcPfS_ii
	.p2align	3, 0x0
_Z4calcPfS_ii:
	.quad	_Z19__device_stub__calcPfS_ii
	.size	_Z4calcPfS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4calcPfS_ii"
	.size	.L__unnamed_1, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__calcPfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4calcPfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4calcPfS_ii           ; -- Begin function _Z4calcPfS_ii
	.globl	_Z4calcPfS_ii
	.p2align	8
	.type	_Z4calcPfS_ii,@function
_Z4calcPfS_ii:                          ; @_Z4calcPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, s15, s6, v[0:1]
	s_mov_b32 s6, exec_lo
	v_cmpx_gt_i32_e64 s5, v13
	s_cbranch_execz .LBB0_10
; %bb.1:
	s_load_b32 s6, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_10
; %bb.2:                                ; %.lr.ph
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mul_lo_u32 v1, v13, 10
	s_mov_b32 s8, 0xf4deae16
	s_mov_b32 s9, 0x3dd25868
	v_cvt_f32_i32_e32 v12, s4
	s_mov_b32 s4, 0
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[16:17], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s0, v16
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v17, vcc_lo
	v_add_co_u32 v16, vcc_lo, s2, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
	s_clause 0x2
	global_load_b128 v[1:4], v[9:10], off
	global_load_b128 v[5:8], v[9:10], off offset:16
	global_load_b64 v[18:19], v[9:10], off offset:32
	s_add_u32 s2, s0, 36
	s_addc_u32 s3, s1, 0
	s_waitcnt vmcnt(2)
	v_cvt_f64_f32_e32 v[9:10], v4
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[14:15], v[9:10], s[8:9]
	v_mul_u32_u24_e32 v10, 10, v0
	v_mul_f32_e32 v21, v12, v12
	s_waitcnt vmcnt(1)
	v_fma_f32 v9, v5, v12, v1
	v_fma_f32 v5, v8, v12, v5
	v_lshlrev_b32_e32 v20, 2, v10
	v_fma_f32 v10, v6, v12, v2
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v22, v21, v18
	v_mul_f32_e32 v11, v21, v8
	v_mul_f32_e32 v21, v21, v19
	v_fma_f32 v6, v18, v12, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v10, 0.5, v22 :: v_dual_fmac_f32 v9, 0.5, v11
	v_fma_f32 v11, v7, v12, v3
	v_fmac_f32_e32 v7, v19, v12
	v_mov_b32_e32 v19, 0
	v_fmac_f32_e32 v11, 0.5, v21
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
	v_lshl_add_u32 v8, s7, 7, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s5, v8
	s_cbranch_execz .LBB0_5
; %bb.4:                                ; %.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mul_lo_u32 v18, v8, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[21:22], 2, v[18:19]
	v_add_co_u32 v21, vcc_lo, s2, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
	global_load_b32 v8, v[21:22], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v20, v8
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v21, 0
	v_mov_b32_e32 v18, 0
	s_mov_b32 s8, 0
	s_mov_b32 s9, s4
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_6:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_cmp_ne_u32_e32 vcc_lo, s9, v13
	s_cmp_lt_i32 s9, s5
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=2
	v_mov_b32_e32 v12, s8
	ds_load_2addr_b64 v[22:25], v12 offset1:1
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v35, v24, v3 :: v_dual_sub_f32 v12, v23, v2
	v_sub_f32_e32 v34, v22, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v12, v12
	v_fmac_f32_e32 v22, v34, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v35, v35
	v_mul_f32_e32 v23, 0x4f800000, v22
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v24, v22, v23, vcc_lo
	v_cvt_f64_f32_e32 v[22:23], v25
	v_sqrt_f32_e32 v26, v24
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v27, -1, v26
	v_add_nc_u32_e32 v25, 1, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v28, -v27, v26, v24
	v_fma_f32 v29, -v25, v26, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v28
	v_cndmask_b32_e64 v26, v26, v27, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v29
	v_cndmask_b32_e64 v25, v26, v25, s0
	v_mul_f64 v[22:23], v[14:15], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v26, 0x37800000, v25
	v_cndmask_b32_e32 v25, v25, v26, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v24, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v36, v25, v24, vcc_lo
	v_fmaak_f32 v24, v36, v36, 0x358637be
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[24:25], v24
	v_div_scale_f64 v[26:27], null, v[24:25], v[24:25], v[22:23]
	v_div_scale_f64 v[32:33], vcc_lo, v[22:23], v[24:25], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[28:29], v[26:27]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0
	v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], -v[26:27], v[28:29], 1.0
	v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[32:33], v[28:29]
	v_fma_f64 v[26:27], -v[26:27], v[30:31], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[26:27], v[26:27], v[28:29], v[30:31]
	v_div_fixup_f64 v[22:23], v[26:27], v[24:25], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v22, v[22:23]
	v_mul_f32_e32 v23, v34, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v24, null, v36, v36, v23
	v_rcp_f32_e32 v27, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v24, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v32, v27
	v_mul_f32_e32 v12, v12, v22
	v_mul_f32_e32 v22, v35, v22
	v_div_scale_f32 v26, null, v36, v36, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v29, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v26, v29, 1.0
	v_fmac_f32_e32 v29, v34, v29
	v_div_scale_f32 v25, null, v36, v36, v12
	v_div_scale_f32 v30, vcc_lo, v23, v36, v23
	v_div_scale_f32 v31, s0, v12, v36, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v28, v25
	v_mul_f32_e32 v32, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v24, v32, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v25, v28, 1.0
	v_fmac_f32_e32 v32, v37, v27
	v_fmac_f32_e32 v28, v33, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, -v24, v32, v30
	v_mul_f32_e32 v33, v31, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v24, v24, v27, v32
	s_mov_b32 vcc_lo, s0
	v_fma_f32 v38, -v25, v33, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v23, v24, v36, v23
	v_dual_fmac_f32 v33, v38, v28 :: v_dual_add_f32 v8, v8, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, -v25, v33, v31
	v_div_fmas_f32 v25, v25, v28, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v12, v25, v36, v12
	v_add_f32_e32 v21, v21, v12
	v_div_scale_f32 v35, s1, v22, v36, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 vcc_lo, s1
	v_mul_f32_e32 v34, v35, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v39, -v26, v34, v35
	v_fmac_f32_e32 v34, v39, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v26, v34, v35
	v_div_fmas_f32 v26, v26, v29, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v22, v26, v36, v22
	v_add_f32_e32 v18, v18, v22
.LBB0_8:                                ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s8, s8, 40
	s_add_i32 s9, s9, 1
	s_cmpk_eq_i32 s8, 0x1400
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_6
; %bb.9:                                ;   in Loop: Header=BB0_3 Depth=1
	v_div_scale_f32 v12, null, v4, v4, v8
	v_div_scale_f32 v22, null, v4, v4, v21
	v_div_scale_f32 v23, null, v4, v4, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v24, v12
	v_rcp_f32_e32 v25, v22
	v_div_scale_f32 v27, vcc_lo, v8, v4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v26, v23
	v_div_scale_f32 v28, s0, v21, v4, v21
	v_div_scale_f32 v32, s1, v18, v4, v18
	s_add_i32 s7, s7, 1
	v_fma_f32 v29, -v12, v24, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v22, v25, 1.0
	s_addk_i32 s4, 0x80
	s_cmp_eq_u32 s7, s6
	v_fma_f32 v31, -v23, v26, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v24, v29, v24 :: v_dual_fmac_f32 v25, v30, v25
	v_dual_mul_f32 v29, v27, v24 :: v_dual_mul_f32 v30, v28, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v33, -v12, v29, v27
	v_fmac_f32_e32 v26, v31, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v34, -v22, v30, v28
	v_fmac_f32_e32 v29, v33, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v31, v32, v26 :: v_dual_fmac_f32 v30, v34, v25
	v_fma_f32 v12, -v12, v29, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v35, -v23, v31, v32
	v_fma_f32 v22, -v22, v30, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v24, v12, v24, v29
	v_dual_fmac_f32 v31, v35, v26 :: v_dual_mov_b32 v12, v4
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v22, v22, v25, v30
	v_fma_f32 v23, -v23, v31, v32
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v8, v24, v4, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v21, v22, v4, v21
	v_div_fmas_f32 v23, v23, v26, v31
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v22, v23, v4, v18
	s_clause 0x2
	global_store_b128 v[16:17], v[9:12], off
	global_store_b128 v[16:17], v[5:8], off offset:16
	global_store_b64 v[16:17], v[21:22], off offset:32
	s_cbranch_scc0 .LBB0_3
.LBB0_10:                               ; %.loopexit136
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4calcPfS_ii
		.amdhsa_group_segment_fixed_size 5120
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 40
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4calcPfS_ii, .Lfunc_end0-_Z4calcPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1492
; NumSgprs: 18
; NumVgprs: 40
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 5120 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 40
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 5120
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4calcPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4calcPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     40
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
