/*
  
Simulation of flow inside a 2D square cavity
using the lattice Boltzmann method (LBM)
  
Written by:       Abhijit Joshi (abhijit@accelereyes.com)
  
Last modified on: Sunday, March 24 @ 9:00 am

Build instructions: nvcc -arch=sm_13 gpu_lbm.cu -o lbmGPU.x

Run instructions: ./lbmGPU.x

*/

#include<iostream>

// problem parameters
const int N = 512;            // number of node points along X and Y (cavity length in lattice units)
const int TIME_STEPS = 1000;  // number of time steps for which the simulation is run

const int NDIR = 9;           // number of discrete velocity directions used in the D2Q9 model

const double DENSITY = 2.7;          // fluid density in lattice units
const double LID_VELOCITY = 0.05;    // lid velocity in lattice units
const double REYNOLDS_NUMBER = 100;  // Re = LID_VELOCITY * N / kinematicViscosity 

__global__ void initialize(double *_ex, double *_ey, double *_alpha, int *_ant, double *_rh, double *_ux, double *_uy, double *_f, double *_feq, double *_f_new)
{
    // these could be initialized directly inside the GPU kernel and moved out of the CPU part...
    _ex[0] =  0.0;   _ey[0] =  0.0;   _alpha[0] = 4.0 /  9.0;
    _ex[1] =  1.0;   _ey[1] =  0.0;   _alpha[1] = 1.0 /  9.0;
    _ex[2] =  0.0;   _ey[2] =  1.0;   _alpha[2] = 1.0 /  9.0;
    _ex[3] = -1.0;   _ey[3] =  0.0;   _alpha[3] = 1.0 /  9.0;
    _ex[4] =  0.0;   _ey[4] = -1.0;   _alpha[4] = 1.0 /  9.0;
    _ex[5] =  1.0;   _ey[5] =  1.0;   _alpha[5] = 1.0 / 36.0;
    _ex[6] = -1.0;   _ey[6] =  1.0;   _alpha[6] = 1.0 / 36.0;
    _ex[7] = -1.0;   _ey[7] = -1.0;   _alpha[7] = 1.0 / 36.0;
    _ex[8] =  1.0;   _ey[8] = -1.0;   _alpha[8] = 1.0 / 36.0;

    // these could be initialized directly inside the GPU kernel and moved out of the CPU part...
    _ant[0] = 0;      //      6        2        5
    _ant[1] = 3;      //               ^       
    _ant[2] = 4;      //               |
    _ant[3] = 1;      //               |  
    _ant[4] = 2;      //      3 <----- 0 -----> 1
    _ant[5] = 7;      //               |
    _ant[6] = 8;      //               |
    _ant[7] = 5;      //               v
    _ant[8] = 6;      //      7        4        8

    // compute the "i" and "j" location and the "dir"
    // handled by this thread

    int i = blockIdx.x * blockDim.x + threadIdx.x ;
    int j = blockIdx.y * blockDim.y + threadIdx.y ;

    // initialize density and velocity fields inside the cavity
    _rh[i+N*j] = DENSITY;
    _ux[i+N*j] = 0;
    _uy[i+N*j] = 0;

    if(j==N-1) _ux[i+N*(N-1)] = LID_VELOCITY;

    // assign initial values for distribution functions
    int ixy = i+N*j;
    for(int dir=0;dir<NDIR;dir++) {
        int index = i+j*N+dir*N*N;
        double edotu = _ex[dir]*_ux[ixy] + _ey[dir]*_uy[ixy];
        double udotu = _ux[ixy]*_ux[ixy] + _uy[ixy]*_uy[ixy];
        _feq[index] = _rh[ixy] * _alpha[dir] * (1 + 3*edotu + 4.5*edotu*edotu - 1.5*udotu);
        _f[index] = _feq[index];
        _f_new[index] = _feq[index];
    }
}

__global__ void timeIntegration(double *_ex, double *_ey, double *_alpha, int *_ant, double *_rh, double *_ux, double *_uy, double *_f, double *_feq, double *_f_new)
{
    // calculate fluid viscosity based on the Reynolds number
    double kinematicViscosity = LID_VELOCITY * (double)N / REYNOLDS_NUMBER;

    // calculate relaxation time tau
    double tau =  0.5 + 3.0 * kinematicViscosity;

    // compute the "i" and "j" location

    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int j = blockIdx.y * blockDim.y + threadIdx.y;

    {
        // collision
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                int ixy = i+N*j;
                for(int dir=0;dir<NDIR;dir++) {
                    int index = i+j*N+dir*N*N;
                    double edotu = _ex[dir]*_ux[ixy] + _ey[dir]*_uy[ixy];
                    double udotu = _ux[ixy]*_ux[ixy] + _uy[ixy]*_uy[ixy];
                    _feq[index] = _rh[ixy] * _alpha[dir] * (1 + 3*edotu + 4.5*edotu*edotu - 1.5*udotu);
                }
        }

        // streaming from interior node points
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                for(int dir=0;dir<NDIR;dir++) {

                    int index = i+j*N+dir*N*N;   // (i,j,dir)
                    int index_new = (i+_ex[dir]) + (j+_ey[dir])*N + dir*N*N;
                    int index_ant = i + j*N + _ant[dir]*N*N;

                    // post-collision distribution at (i,j) along "dir"
                    double f_plus = _f[index] - (_f[index] - _feq[index])/tau;

                    if((i+_ex[dir]==0) || (i+_ex[dir]==N-1) || (j+_ey[dir]==0) || (j+_ey[dir]==N-1)) {
                        // bounce back
                        int ixy = i+_ex[dir] + N*(j+_ey[dir]);
                        double ubdote = _ux[ixy]*_ex[dir] + _uy[ixy]*_ey[dir];
                        _f_new[index_ant] = f_plus - 6.0 * DENSITY * _alpha[dir] * ubdote;
                    }
                    else {
                        // stream to neighbor
                        _f_new[index_new] = f_plus;
                    }
                }
        }

        // push f_new into f
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                for(int dir=0;dir<NDIR;dir++) {
                    int index = i+j*N+dir*N*N;   // (i,j,dir)
                    _f[index] = _f_new[index];
                }
        }

        // update density at interior nodes
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                double rho=0;
                for(int dir=0;dir<NDIR;dir++) {
                    int index = i+j*N+dir*N*N;
                    rho+=_f_new[index];
                }
                _rh[i+N*j] = rho;
        }

        // update velocity at interior nodes
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                double velx=0;
                double vely=0;
                for(int dir=0;dir<NDIR;dir++) {
                    int index = i+j*N+dir*N*N;
                    velx+=_f_new[index]*_ex[dir];
                    vely+=_f_new[index]*_ey[dir];
                }
                _ux[i+N*j] = velx/_rh[i+N*j];
                _uy[i+N*j] = vely/_rh[i+N*j];
        }
    }

}

int main(int argc, char *argv[])
{
    // the base vectors and associated weight coefficients (GPU)
    double *_ex, *_ey, *_alpha;  // pointers to device (GPU) memory
    cudaMalloc((void **)&_ex,NDIR*sizeof(double));
    cudaMalloc((void **)&_ey,NDIR*sizeof(double));
    cudaMalloc((void **)&_alpha,NDIR*sizeof(double));

    // ant vector (GPU)
    int *_ant;  // gpu memory
    cudaMalloc((void **)&_ant,NDIR*sizeof(int));

    // allocate memory on the GPU
    double *_f, *_feq, *_f_new;
    cudaMalloc((void **)&_f,N*N*NDIR*sizeof(double));
    cudaMalloc((void **)&_feq,N*N*NDIR*sizeof(double));
    cudaMalloc((void **)&_f_new,N*N*NDIR*sizeof(double));

    double *_rh, *_ux, *_uy;
    cudaMalloc((void **)&_rh,N*N*sizeof(double));
    cudaMalloc((void **)&_ux,N*N*sizeof(double));
    cudaMalloc((void **)&_uy,N*N*sizeof(double));

    // assign a 2D distribution of CUDA "threads" within each CUDA "block"    
    int threadsAlongX=16, threadsAlongY=16;
    dim3 dimBlock(threadsAlongX, threadsAlongY, 1);

    // calculate number of blocks along X and Y in a 2D CUDA "grid"
    dim3 dimGrid( ceil(float(N)/float(dimBlock.x)), ceil(float(N)/float(dimBlock.y)), 1 );

    initialize<<<dimGrid,dimBlock>>>(_ex, _ey, _alpha, _ant, _rh, _ux, _uy, _f, _feq, _f_new);

    // time integration
    int time=0;
    while(time<TIME_STEPS) {

        time++;
       
        timeIntegration<<<dimGrid,dimBlock >>>(_ex, _ey, _alpha, _ant, _rh, _ux, _uy, _f, _feq, _f_new);

    }

/*
    double *uy = new double [N*N];
    cudaMemcpy(uy,_uy,N*N*sizeof(double),cudaMemcpyDeviceToHost);
    // centerline velocity profiles
    for(int i=1;i<N-1;i++) {
        std::cout << 0.5 + (double)(i-1) << "  " << uy[i + N*(N/2)] << std::endl;
    }
*/
    return 0;
}

	.file	"tmpxft_0028d373_00000000-6_gpu_lbm.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z10initializePdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_
	.type	_Z48__device_stub__Z10initializePdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_, @function
_Z48__device_stub__Z10initializePdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z10initializePdS_S_PiS_S_S_S_S_S_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 272
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z48__device_stub__Z10initializePdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_, .-_Z48__device_stub__Z10initializePdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_
	.globl	_Z10initializePdS_S_PiS_S_S_S_S_S_
	.type	_Z10initializePdS_S_PiS_S_S_S_S_S_, @function
_Z10initializePdS_S_PiS_S_S_S_S_S_:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z10initializePdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_
	.cfi_endproc
.LFE3661:
	.size	_Z10initializePdS_S_PiS_S_S_S_S_S_, .-_Z10initializePdS_S_PiS_S_S_S_S_S_
	.globl	_Z53__device_stub__Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_
	.type	_Z53__device_stub__Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_, @function
_Z53__device_stub__Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	96(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 272
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L8:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z53__device_stub__Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_, .-_Z53__device_stub__Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_
	.globl	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.type	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_, @function
_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_
	.cfi_endproc
.LFE3663:
	.size	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_, .-_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	$72, %esi
	subq	$112, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$72, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$72, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$36, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$18874368, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$18874368, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$18874368, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$2097152, %esi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$2097152, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$2097152, %esi
	call	cudaMalloc@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdi
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	$1, 100(%rsp)
	movq	%rdi, 92(%rsp)
	movq	%rdx, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	pushq	96(%rsp)
	.cfi_def_cfa_offset 160
	movq	96(%rsp), %r9
	movq	88(%rsp), %r8
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z48__device_stub__Z10initializePdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 128
.L14:
	movl	$1000, %ebx
.L16:
	movl	88(%rsp), %ecx
	movq	80(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	92(%rsp), %rdi
	movl	100(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	pushq	96(%rsp)
	.cfi_def_cfa_offset 160
	movq	96(%rsp), %r9
	movq	88(%rsp), %r8
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z53__device_stub__Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_PdS_S_PiS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 128
.L15:
	decl	%ebx
	jne	.L16
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$112, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_"
.LC1:
	.string	"_Z10initializePdS_S_PiS_S_S_S_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10initializePdS_S_PiS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
  
Simulation of flow inside a 2D square cavity
using the lattice Boltzmann method (LBM)
  
Written by:       Abhijit Joshi (abhijit@accelereyes.com)
  
Last modified on: Sunday, March 24 @ 9:00 am

Build instructions: nvcc -arch=sm_13 gpu_lbm.cu -o lbmGPU.x

Run instructions: ./lbmGPU.x

*/


#include <hip/hip_runtime.h>
#include<iostream>

// problem parameters
const int N = 512;            // number of node points along X and Y (cavity length in lattice units)
const int TIME_STEPS = 1000;  // number of time steps for which the simulation is run

const int NDIR = 9;           // number of discrete velocity directions used in the D2Q9 model

const double DENSITY = 2.7;          // fluid density in lattice units
const double LID_VELOCITY = 0.05;    // lid velocity in lattice units
const double REYNOLDS_NUMBER = 100;  // Re = LID_VELOCITY * N / kinematicViscosity 

__global__ void initialize(double *_ex, double *_ey, double *_alpha, int *_ant, double *_rh, double *_ux, double *_uy, double *_f, double *_feq, double *_f_new)
{
    // these could be initialized directly inside the GPU kernel and moved out of the CPU part...
    _ex[0] =  0.0;   _ey[0] =  0.0;   _alpha[0] = 4.0 /  9.0;
    _ex[1] =  1.0;   _ey[1] =  0.0;   _alpha[1] = 1.0 /  9.0;
    _ex[2] =  0.0;   _ey[2] =  1.0;   _alpha[2] = 1.0 /  9.0;
    _ex[3] = -1.0;   _ey[3] =  0.0;   _alpha[3] = 1.0 /  9.0;
    _ex[4] =  0.0;   _ey[4] = -1.0;   _alpha[4] = 1.0 /  9.0;
    _ex[5] =  1.0;   _ey[5] =  1.0;   _alpha[5] = 1.0 / 36.0;
    _ex[6] = -1.0;   _ey[6] =  1.0;   _alpha[6] = 1.0 / 36.0;
    _ex[7] = -1.0;   _ey[7] = -1.0;   _alpha[7] = 1.0 / 36.0;
    _ex[8] =  1.0;   _ey[8] = -1.0;   _alpha[8] = 1.0 / 36.0;

    // these could be initialized directly inside the GPU kernel and moved out of the CPU part...
    _ant[0] = 0;      //      6        2        5
    _ant[1] = 3;      //               ^       
    _ant[2] = 4;      //               |
    _ant[3] = 1;      //               |  
    _ant[4] = 2;      //      3 <----- 0 -----> 1
    _ant[5] = 7;      //               |
    _ant[6] = 8;      //               |
    _ant[7] = 5;      //               v
    _ant[8] = 6;      //      7        4        8

    // compute the "i" and "j" location and the "dir"
    // handled by this thread

    int i = blockIdx.x * blockDim.x + threadIdx.x ;
    int j = blockIdx.y * blockDim.y + threadIdx.y ;

    // initialize density and velocity fields inside the cavity
    _rh[i+N*j] = DENSITY;
    _ux[i+N*j] = 0;
    _uy[i+N*j] = 0;

    if(j==N-1) _ux[i+N*(N-1)] = LID_VELOCITY;

    // assign initial values for distribution functions
    int ixy = i+N*j;
    for(int dir=0;dir<NDIR;dir++) {
        int index = i+j*N+dir*N*N;
        double edotu = _ex[dir]*_ux[ixy] + _ey[dir]*_uy[ixy];
        double udotu = _ux[ixy]*_ux[ixy] + _uy[ixy]*_uy[ixy];
        _feq[index] = _rh[ixy] * _alpha[dir] * (1 + 3*edotu + 4.5*edotu*edotu - 1.5*udotu);
        _f[index] = _feq[index];
        _f_new[index] = _feq[index];
    }
}

__global__ void timeIntegration(double *_ex, double *_ey, double *_alpha, int *_ant, double *_rh, double *_ux, double *_uy, double *_f, double *_feq, double *_f_new)
{
    // calculate fluid viscosity based on the Reynolds number
    double kinematicViscosity = LID_VELOCITY * (double)N / REYNOLDS_NUMBER;

    // calculate relaxation time tau
    double tau =  0.5 + 3.0 * kinematicViscosity;

    // compute the "i" and "j" location

    int i = blockIdx.x * blockDim.x + threadIdx.x;
    int j = blockIdx.y * blockDim.y + threadIdx.y;

    {
        // collision
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                int ixy = i+N*j;
                for(int dir=0;dir<NDIR;dir++) {
                    int index = i+j*N+dir*N*N;
                    double edotu = _ex[dir]*_ux[ixy] + _ey[dir]*_uy[ixy];
                    double udotu = _ux[ixy]*_ux[ixy] + _uy[ixy]*_uy[ixy];
                    _feq[index] = _rh[ixy] * _alpha[dir] * (1 + 3*edotu + 4.5*edotu*edotu - 1.5*udotu);
                }
        }

        // streaming from interior node points
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                for(int dir=0;dir<NDIR;dir++) {

                    int index = i+j*N+dir*N*N;   // (i,j,dir)
                    int index_new = (i+_ex[dir]) + (j+_ey[dir])*N + dir*N*N;
                    int index_ant = i + j*N + _ant[dir]*N*N;

                    // post-collision distribution at (i,j) along "dir"
                    double f_plus = _f[index] - (_f[index] - _feq[index])/tau;

                    if((i+_ex[dir]==0) || (i+_ex[dir]==N-1) || (j+_ey[dir]==0) || (j+_ey[dir]==N-1)) {
                        // bounce back
                        int ixy = i+_ex[dir] + N*(j+_ey[dir]);
                        double ubdote = _ux[ixy]*_ex[dir] + _uy[ixy]*_ey[dir];
                        _f_new[index_ant] = f_plus - 6.0 * DENSITY * _alpha[dir] * ubdote;
                    }
                    else {
                        // stream to neighbor
                        _f_new[index_new] = f_plus;
                    }
                }
        }

        // push f_new into f
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                for(int dir=0;dir<NDIR;dir++) {
                    int index = i+j*N+dir*N*N;   // (i,j,dir)
                    _f[index] = _f_new[index];
                }
        }

        // update density at interior nodes
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                double rho=0;
                for(int dir=0;dir<NDIR;dir++) {
                    int index = i+j*N+dir*N*N;
                    rho+=_f_new[index];
                }
                _rh[i+N*j] = rho;
        }

        // update velocity at interior nodes
        if((i>0) && (i<N-1) && (j>0) && (j<N-1)) {
                double velx=0;
                double vely=0;
                for(int dir=0;dir<NDIR;dir++) {
                    int index = i+j*N+dir*N*N;
                    velx+=_f_new[index]*_ex[dir];
                    vely+=_f_new[index]*_ey[dir];
                }
                _ux[i+N*j] = velx/_rh[i+N*j];
                _uy[i+N*j] = vely/_rh[i+N*j];
        }
    }

}

int main(int argc, char *argv[])
{
    // the base vectors and associated weight coefficients (GPU)
    double *_ex, *_ey, *_alpha;  // pointers to device (GPU) memory
    hipMalloc((void **)&_ex,NDIR*sizeof(double));
    hipMalloc((void **)&_ey,NDIR*sizeof(double));
    hipMalloc((void **)&_alpha,NDIR*sizeof(double));

    // ant vector (GPU)
    int *_ant;  // gpu memory
    hipMalloc((void **)&_ant,NDIR*sizeof(int));

    // allocate memory on the GPU
    double *_f, *_feq, *_f_new;
    hipMalloc((void **)&_f,N*N*NDIR*sizeof(double));
    hipMalloc((void **)&_feq,N*N*NDIR*sizeof(double));
    hipMalloc((void **)&_f_new,N*N*NDIR*sizeof(double));

    double *_rh, *_ux, *_uy;
    hipMalloc((void **)&_rh,N*N*sizeof(double));
    hipMalloc((void **)&_ux,N*N*sizeof(double));
    hipMalloc((void **)&_uy,N*N*sizeof(double));

    // assign a 2D distribution of CUDA "threads" within each CUDA "block"    
    int threadsAlongX=16, threadsAlongY=16;
    dim3 dimBlock(threadsAlongX, threadsAlongY, 1);

    // calculate number of blocks along X and Y in a 2D CUDA "grid"
    dim3 dimGrid( ceil(float(N)/float(dimBlock.x)), ceil(float(N)/float(dimBlock.y)), 1 );

    initialize<<<dimGrid,dimBlock>>>(_ex, _ey, _alpha, _ant, _rh, _ux, _uy, _f, _feq, _f_new);

    // time integration
    int time=0;
    while(time<TIME_STEPS) {

        time++;
       
        timeIntegration<<<dimGrid,dimBlock >>>(_ex, _ey, _alpha, _ant, _rh, _ux, _uy, _f, _feq, _f_new);

    }

/*
    double *uy = new double [N*N];
    cudaMemcpy(uy,_uy,N*N*sizeof(double),cudaMemcpyDeviceToHost);
    // centerline velocity profiles
    for(int i=1;i<N-1;i++) {
        std::cout << 0.5 + (double)(i-1) << "  " << uy[i + N*(N/2)] << std::endl;
    }
*/
    return 0;
}

	.text
	.file	"gpu_lbm.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_ # -- Begin function _Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_
	.type	_Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_,@function
_Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_: # @_Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10initializePdS_S_PiS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_, .Lfunc_end0-_Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_ # -- Begin function _Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.type	_Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_,@function
_Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_: # @_Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_, .Lfunc_end1-_Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movabsq	$137438953504, %rbx             # imm = 0x2000000020
	movabsq	$68719476752, %r14              # imm = 0x1000000010
	leaq	72(%rsp), %rdi
	movl	$72, %esi
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movl	$72, %esi
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$72, %esi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$36, %esi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$18874368, %esi                 # imm = 0x1200000
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$18874368, %esi                 # imm = 0x1200000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$18874368, %esi                 # imm = 0x1200000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$2097152, %esi                  # imm = 0x200000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$2097152, %esi                  # imm = 0x200000
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$2097152, %esi                  # imm = 0x200000
	callq	hipMalloc
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB2_2:                                # %.preheader
	movl	$1000, %ebp                     # imm = 0x3E8
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_3 Depth=1
	movq	72(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB2_5:                                #   in Loop: Header=BB2_3 Depth=1
	decl	%ebp
	jne	.LBB2_3
# %bb.6:
	xorl	%eax, %eax
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10initializePdS_S_PiS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10initializePdS_S_PiS_S_S_S_S_S_,@object # @_Z10initializePdS_S_PiS_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z10initializePdS_S_PiS_S_S_S_S_S_
	.p2align	3, 0x0
_Z10initializePdS_S_PiS_S_S_S_S_S_:
	.quad	_Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_
	.size	_Z10initializePdS_S_PiS_S_S_S_S_S_, 8

	.type	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_,@object # @_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.globl	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.p2align	3, 0x0
_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_:
	.quad	_Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.size	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10initializePdS_S_PiS_S_S_S_S_S_"
	.size	.L__unnamed_1, 35

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_"
	.size	.L__unnamed_2, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__initializePdS_S_PiS_S_S_S_S_S_
	.addrsig_sym _Z30__device_stub__timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10initializePdS_S_PiS_S_S_S_S_S_
	.addrsig_sym _Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10initializePdS_S_PiS_S_S_S_S_S_ ; -- Begin function _Z10initializePdS_S_PiS_S_S_S_S_S_
	.globl	_Z10initializePdS_S_PiS_S_S_S_S_S_
	.p2align	8
	.type	_Z10initializePdS_S_PiS_S_S_S_S_S_,@function
_Z10initializePdS_S_PiS_S_S_S_S_S_:     ; @_Z10initializePdS_S_PiS_S_S_S_S_S_
; %bb.0:
	s_load_b512 s[16:31], s[0:1], 0x0
	s_mov_b32 s2, 0
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v10, 0x3fdc71c7
	s_mov_b32 s3, s2
	v_dual_mov_b32 v9, 0x1c71c71c :: v_dual_mov_b32 v2, 3
	v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v14, s2
	s_mov_b32 s3, 0x3ff00000
	s_mov_b32 s5, 0x3fbc71c7
	s_mov_b32 s4, 0x1c71c71c
	v_dual_mov_b32 v12, s3 :: v_dual_mov_b32 v11, s2
	s_mov_b32 s3, 0xbff00000
	v_mov_b32_e32 v13, 6
	v_dual_mov_b32 v3, 4 :: v_dual_mov_b32 v4, 1
	v_dual_mov_b32 v5, 2 :: v_dual_mov_b32 v6, 7
	s_waitcnt lgkmcnt(0)
	s_clause 0x2
	global_store_b64 v1, v[14:15], s[16:17]
	global_store_b64 v1, v[14:15], s[18:19]
	global_store_b64 v1, v[9:10], s[20:21]
	v_dual_mov_b32 v10, s5 :: v_dual_mov_b32 v9, s4
	s_mov_b32 s5, 0x3f9c71c7
	v_dual_mov_b32 v17, s3 :: v_dual_mov_b32 v16, s2
	v_dual_mov_b32 v19, s5 :: v_dual_mov_b32 v18, s4
	v_dual_mov_b32 v7, 8 :: v_dual_mov_b32 v8, 5
	s_clause 0x1a
	global_store_b64 v1, v[11:12], s[16:17] offset:8
	global_store_b64 v1, v[14:15], s[18:19] offset:8
	global_store_b64 v1, v[9:10], s[20:21] offset:8
	global_store_b64 v1, v[14:15], s[16:17] offset:16
	global_store_b64 v1, v[11:12], s[18:19] offset:16
	global_store_b64 v1, v[9:10], s[20:21] offset:16
	global_store_b64 v1, v[16:17], s[16:17] offset:24
	global_store_b64 v1, v[14:15], s[18:19] offset:24
	global_store_b64 v1, v[9:10], s[20:21] offset:24
	global_store_b64 v1, v[14:15], s[16:17] offset:32
	global_store_b64 v1, v[16:17], s[18:19] offset:32
	global_store_b64 v1, v[9:10], s[20:21] offset:32
	global_store_b64 v1, v[11:12], s[16:17] offset:40
	global_store_b64 v1, v[11:12], s[18:19] offset:40
	global_store_b64 v1, v[18:19], s[20:21] offset:40
	global_store_b64 v1, v[16:17], s[16:17] offset:48
	global_store_b64 v1, v[11:12], s[18:19] offset:48
	global_store_b64 v1, v[18:19], s[20:21] offset:48
	global_store_b64 v1, v[16:17], s[16:17] offset:56
	global_store_b64 v1, v[16:17], s[18:19] offset:56
	global_store_b64 v1, v[18:19], s[20:21] offset:56
	global_store_b64 v1, v[11:12], s[16:17] offset:64
	global_store_b64 v1, v[16:17], s[18:19] offset:64
	global_store_b64 v1, v[18:19], s[20:21] offset:64
	global_store_b128 v1, v[1:4], s[22:23]
	global_store_b128 v1, v[5:8], s[22:23] offset:16
	global_store_b32 v1, v13, s[22:23] offset:32
	s_load_b32 s2, s[0:1], 0x5c
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	v_mov_b32_e32 v13, 0x40059999
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[11:12], null, s15, s3, v[0:1]
	v_mov_b32_e32 v12, 0x9999999a
	s_mov_b32 s2, exec_lo
	v_lshl_add_u32 v2, v11, 9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[8:9], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s24, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s25, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, s26, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, s27, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, s28, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s29, v9, vcc_lo
	global_store_b64 v[4:5], v[12:13], off
	global_store_b64 v[6:7], v[14:15], off
	global_store_b64 v[8:9], v[14:15], off
	v_cmpx_eq_u32_e32 0x1ff, v11
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_ashrrev_i32_e32 v11, 31, v10
	v_mov_b32_e32 v13, 0x3fa99999
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v0, vcc_lo, s26, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s27, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, 0x1ff000, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v3, vcc_lo
	global_store_b64 v[10:11], v[12:13], off
.LBB0_2:                                ; %.preheader
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b128 s[0:3], s[0:1], 0x40
	s_mov_b64 s[4:5], 0
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s6, s16, s4
	s_addc_u32 s7, s17, s5
	global_load_b64 v[10:11], v[8:9], off
	s_add_u32 s8, s18, s4
	s_addc_u32 s9, s19, s5
	s_clause 0x1
	global_load_b64 v[12:13], v1, s[6:7]
	global_load_b64 v[14:15], v1, s[8:9]
	global_load_b64 v[16:17], v[6:7], off
	global_load_b64 v[18:19], v[4:5], off
	s_add_u32 s6, s20, s4
	s_addc_u32 s7, s21, s5
	v_ashrrev_i32_e32 v3, 31, v2
	global_load_b64 v[20:21], v1, s[6:7]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	s_cmpk_eq_i32 s4, 0x48
	s_waitcnt vmcnt(3)
	v_mul_f64 v[14:15], v[14:15], v[10:11]
	v_mul_f64 v[10:11], v[10:11], v[10:11]
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[14:15]
	v_fma_f64 v[10:11], v[16:17], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], 0x40080000, v[12:13], 1.0
	v_mul_f64 v[22:23], 0x40120000, v[12:13]
	v_fma_f64 v[12:13], v[12:13], v[22:23], v[14:15]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[14:15], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], 0xbff80000, v[10:11], v[12:13]
	v_lshlrev_b64 v[12:13], 3, v[2:3]
	v_add_nc_u32_e32 v2, 0x40000, v2
	v_mul_f64 v[10:11], v[14:15], v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, s0, v12
	v_add_co_ci_u32_e32 v15, vcc_lo, s1, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, s30, v12
	v_add_co_ci_u32_e32 v17, vcc_lo, s31, v13, vcc_lo
	v_add_co_u32 v12, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	global_store_b64 v[14:15], v[10:11], off
	global_store_b64 v[16:17], v[10:11], off
	global_load_b64 v[10:11], v[14:15], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[12:13], v[10:11], off
	s_cbranch_scc0 .LBB0_3
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10initializePdS_S_PiS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10initializePdS_S_PiS_S_S_S_S_S_, .Lfunc_end0-_Z10initializePdS_S_PiS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 988
; NumSgprs: 34
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_ ; -- Begin function _Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.globl	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
	.p2align	8
	.type	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_,@function
_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_: ; @_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x5c
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[9:10], null, s15, s3, v[0:1]
	s_mov_b32 s2, exec_lo
	v_add_nc_u32_e32 v0, -1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, -1, v9
	v_max_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x1fe, v0
	s_cbranch_execz .LBB1_16
; %bb.1:
	s_load_b512 s[4:19], s[0:1], 0x0
	v_lshl_add_u32 v6, v9, 9, v8
	v_mov_b32_e32 v7, 0
	s_load_b128 s[20:23], s[0:1], 0x40
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v10, v6
	v_lshlrev_b64 v[4:5], 3, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s14, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_add_u32 s2, s4, s0
	s_addc_u32 s3, s5, s1
	global_load_b64 v[11:12], v[0:1], off
	s_add_u32 s12, s6, s0
	s_addc_u32 s13, s7, s1
	s_clause 0x1
	global_load_b64 v[13:14], v7, s[2:3]
	global_load_b64 v[15:16], v7, s[12:13]
	global_load_b64 v[17:18], v[2:3], off
	global_load_b64 v[19:20], v[4:5], off
	s_add_u32 s2, s8, s0
	s_addc_u32 s3, s9, s1
	s_add_u32 s0, s0, 8
	global_load_b64 v[21:22], v7, s[2:3]
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x48
	s_waitcnt vmcnt(3)
	v_mul_f64 v[15:16], v[15:16], v[11:12]
	v_mul_f64 v[11:12], v[11:12], v[11:12]
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[15:16]
	v_fma_f64 v[11:12], v[17:18], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], 0x40080000, v[13:14], 1.0
	v_mul_f64 v[23:24], 0x40120000, v[13:14]
	v_fma_f64 v[13:14], v[13:14], v[23:24], v[15:16]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[15:16], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], 0xbff80000, v[11:12], v[13:14]
	v_mul_f64 v[12:13], v[15:16], v[11:12]
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 3, v[10:11]
	v_add_nc_u32_e32 v10, 0x40000, v10
	v_add_co_u32 v14, vcc_lo, s20, v14
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v15, vcc_lo, s21, v15, vcc_lo
	global_store_b64 v[14:15], v[12:13], off
	s_cbranch_scc0 .LBB1_2
; %bb.3:                                ; %.preheader
	v_cvt_f64_i32_e32 v[7:8], v8
	v_cvt_f64_i32_e32 v[9:10], v9
	v_mov_b32_e32 v20, 0
	s_mov_b32 s12, 0x5e353f7d
	s_mov_b32 s24, 0x33333334
	s_mov_b32 s13, 0xbff449ba
	s_mov_b32 s25, 0xc0303333
	s_mov_b32 s3, 0
	s_mov_b64 s[26:27], s[6:7]
	s_mov_b64 s[28:29], s[4:5]
.LBB1_4:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v11, s3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s18, v11
	v_add_co_ci_u32_e32 v14, vcc_lo, s19, v12, vcc_lo
	v_add_co_u32 v11, vcc_lo, s20, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s21, v12, vcc_lo
	global_load_b64 v[21:22], v[13:14], off
	global_load_b64 v[11:12], v[11:12], off
	s_clause 0x1
	global_load_b64 v[13:14], v20, s[28:29]
	global_load_b64 v[15:16], v20, s[26:27]
	s_waitcnt vmcnt(2)
	v_add_f64 v[11:12], v[21:22], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[17:18], null, s[12:13], s[12:13], v[11:12]
	v_rcp_f64_e32 v[23:24], v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[17:18], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	v_fma_f64 v[25:26], -v[17:18], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	v_div_scale_f64 v[25:26], vcc_lo, v[11:12], s[12:13], v[11:12]
	v_mul_f64 v[27:28], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], -v[17:18], v[27:28], v[25:26]
	s_waitcnt vmcnt(0)
	v_add_f64 v[25:26], v[15:16], v[9:10]
	v_div_fmas_f64 v[17:18], v[17:18], v[23:24], v[27:28]
	v_add_f64 v[23:24], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 s1, 0, v[25:26]
	v_cmp_neq_f64_e64 s2, 0x407ff000, v[25:26]
	v_div_fixup_f64 v[11:12], v[17:18], s[12:13], v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e32 vcc_lo, 0, v[23:24]
	v_cmp_neq_f64_e64 s0, 0x407ff000, v[23:24]
	v_fma_f64 v[18:19], 0x40800000, v[25:26], v[23:24]
                                        ; implicit-def: $vgpr17
	v_add_f64 v[11:12], v[21:22], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s2
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s1
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=1
	v_cvt_f64_i32_e32 v[13:14], s3
                                        ; implicit-def: $vgpr15_vgpr16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[18:19], v[13:14]
                                        ; implicit-def: $vgpr18_vgpr19
	v_cvt_i32_f64_e32 v17, v[13:14]
                                        ; implicit-def: $vgpr13_vgpr14
; %bb.6:                                ; %Flow
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_4 Depth=1
	v_cvt_i32_f64_e32 v17, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[17:18], 3, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, s16, v17
	v_add_co_ci_u32_e32 v22, vcc_lo, s17, v18, vcc_lo
	v_add_co_u32 v17, vcc_lo, s14, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s15, v18, vcc_lo
	global_load_b64 v[21:22], v[21:22], off
	global_load_b64 v[17:18], v[17:18], off
	global_load_b64 v[23:24], v20, s[8:9]
	s_load_b32 s1, s[10:11], 0x0
	s_waitcnt vmcnt(2)
	v_mul_f64 v[15:16], v[15:16], v[21:22]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[15:16]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[15:16], v[23:24], s[24:25]
	s_waitcnt lgkmcnt(0)
	v_lshl_add_u32 v17, s1, 18, v6
	v_fma_f64 v[11:12], v[15:16], v[13:14], v[11:12]
.LBB1_8:                                ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	s_add_i32 s3, s3, 0x40000
	s_add_u32 s28, s28, 8
	s_addc_u32 s29, s29, 0
	s_add_u32 s26, s26, 8
	v_lshlrev_b64 v[13:14], 3, v[17:18]
	s_addc_u32 s27, s27, 0
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_add_u32 s8, s8, 8
	s_addc_u32 s9, s9, 0
	v_add_co_u32 v13, vcc_lo, s22, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v14, vcc_lo
	s_cmp_lg_u32 s3, 0x240000
	global_store_b64 v[13:14], v[11:12], off
	s_cbranch_scc1 .LBB1_4
; %bb.9:                                ; %.critedge.preheader
	s_mov_b32 s0, 0
.LBB1_10:                               ; %.critedge
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v7, s0, v6
	s_add_i32 s0, s0, 0x40000
	s_cmp_lg_u32 s0, 0x240000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s22, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s23, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, s18, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v8, vcc_lo
	global_load_b64 v[9:10], v[9:10], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[9:10], off
	s_cbranch_scc1 .LBB1_10
; %bb.11:                               ; %.critedge218.preheader
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_mov_b32 s0, 0
.LBB1_12:                               ; %.critedge218
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v10, s0, v6
	s_add_i32 s0, s0, 0x40000
	s_cmp_eq_u32 s0, 0x240000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s22, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s23, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	s_cbranch_scc0 .LBB1_12
; %bb.13:                               ; %.critedge219
	v_mov_b32_e32 v10, 0
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v14, 0
	s_mov_b64 s[0:1], 0
	global_store_b64 v[4:5], v[8:9], off
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
.LBB1_14:                               ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v7, 31, v6
	s_add_u32 s2, s4, s0
	s_addc_u32 s3, s5, s1
	s_add_u32 s8, s6, s0
	s_addc_u32 s9, s7, s1
	v_lshlrev_b64 v[15:16], 3, v[6:7]
	v_add_nc_u32_e32 v6, 0x40000, v6
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x48
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, s22, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s23, v16, vcc_lo
	s_clause 0x1
	global_load_b64 v[17:18], v14, s[2:3]
	global_load_b64 v[19:20], v14, s[8:9]
	global_load_b64 v[15:16], v[15:16], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], v[15:16], v[17:18], v[12:13]
	v_fma_f64 v[10:11], v[15:16], v[19:20], v[10:11]
	s_cbranch_scc0 .LBB1_14
; %bb.15:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[6:7], null, v[8:9], v[8:9], v[12:13]
	v_div_scale_f64 v[18:19], vcc_lo, v[12:13], v[8:9], v[12:13]
	v_rcp_f64_e32 v[14:15], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_fma_f64 v[16:17], -v[6:7], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_mul_f64 v[16:17], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[16:17], v[18:19]
	v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[6:7], v[6:7], v[8:9], v[12:13]
	global_store_b64 v[2:3], v[6:7], off
	global_load_b64 v[2:3], v[4:5], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[10:11]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_div_scale_f64 v[8:9], vcc_lo, v[10:11], v[2:3], v[10:11]
	v_mul_f64 v[12:13], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[12:13], v[8:9]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[4:5], v[2:3], v[10:11]
	global_store_b64 v[0:1], v[2:3], off
.LBB1_16:                               ; %.critedge220
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_, .Lfunc_end1-_Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1664
; NumSgprs: 32
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10initializePdS_S_PiS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z10initializePdS_S_PiS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z15timeIntegrationPdS_S_PiS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
