#include "includes.h"
__global__ void ComputePositions(float *g_Data1, float *g_Data2, float *g_Data3, int *d_Ptrs, float *d_Sift, int numPts, int maxPts, int w, int h)
{
int i = __mul24(blockIdx.x, POSBLK_SIZE) + threadIdx.x;
if (i>=numPts)
return;
int p = d_Ptrs[i];
//if (p<w+1 || p>=(w*h-w-1))
//  printf("ComputePositions: read error\n");
float val[7];
val[0] = g_Data2[p];
val[1] = g_Data2[p-1];
val[2] = g_Data2[p+1];
float dx = 0.5f*(val[2] - val[1]);
float dxx = 2.0f*val[0] - val[1] - val[2];
val[3] = g_Data2[p-w];
val[4] = g_Data2[p+w];
float dy = 0.5f*(val[4] - val[3]);
float dyy = 2.0f*val[0] - val[3] - val[4];
val[5] = g_Data3[p];
val[6] = g_Data1[p];
float ds = 0.5f*(val[6] - val[5]);
float dss = 2.0f*val[0] - val[5] - val[6];
float dxy = 0.25f*
(g_Data2[p+w+1] + g_Data2[p-w-1] - g_Data2[p-w+1] - g_Data2[p+w-1]);
float dxs = 0.25f*
(g_Data3[p+1] + g_Data1[p-1] - g_Data1[p+1] - g_Data3[p-1]);
float dys = 0.25f*
(g_Data3[p+w] + g_Data1[p-w] - g_Data3[p-w] - g_Data1[p+w]);
float idxx = dyy*dss - dys*dys;
float idxy = dys*dxs - dxy*dss;
float idxs = dxy*dys - dyy*dxs;
float idyy = dxx*dss - dxs*dxs;
float idys = dxy*dxs - dxx*dys;
float idss = dxx*dyy - dxy*dxy;
float det = idxx*dxx + idxy*dxy + idxs*dxs;
float idet = 1.0f / det;
float pdx = idet*
(idxx*dx + idxy*dy + idxs*ds);
float pdy = idet*
(idxy*dx + idyy*dy + idys*ds);
float pds = idet*
(idxs*dx + idys*dy + idss*ds);
if (pdx<-0.5f || pdx>0.5f || pdy<-0.5f || pdy>0.5f || pds<-0.5f || pds>0.5f){
pdx = __fdividef(dx, dxx);
pdy = __fdividef(dy, dyy);
pds = __fdividef(ds, dss);
}
float dval = 0.5f*(dx*pdx + dy*pdy + ds*pds);
d_Sift[i+0*maxPts] = (p%w) + pdx;
d_Sift[i+1*maxPts] = (p/w) + pdy;
d_Sift[i+2*maxPts] = d_ConstantA[0] * exp2f(pds*d_ConstantB[0]);
d_Sift[i+3*maxPts] = val[0] + dval;
float tra = dxx + dyy;
det = dxx*dyy - dxy*dxy;
d_Sift[i+4*maxPts] = __fdividef(tra*tra, det);
}
	.file	"tmpxft_0028723d_00000000-6_ComputePositions.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z16ComputePositionsPfS_S_PiS_iiiiPfS_S_PiS_iiii
	.type	_Z48__device_stub__Z16ComputePositionsPfS_S_PiS_iiiiPfS_S_PiS_iiii, @function
_Z48__device_stub__Z16ComputePositionsPfS_S_PiS_iiiiPfS_S_PiS_iiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z16ComputePositionsPfS_S_PiS_iiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z48__device_stub__Z16ComputePositionsPfS_S_PiS_iiiiPfS_S_PiS_iiii, .-_Z48__device_stub__Z16ComputePositionsPfS_S_PiS_iiiiPfS_S_PiS_iiii
	.globl	_Z16ComputePositionsPfS_S_PiS_iiii
	.type	_Z16ComputePositionsPfS_S_PiS_iiii, @function
_Z16ComputePositionsPfS_S_PiS_iiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z16ComputePositionsPfS_S_PiS_iiiiPfS_S_PiS_iiii
	.cfi_endproc
.LFE2033:
	.size	_Z16ComputePositionsPfS_S_PiS_iiii, .-_Z16ComputePositionsPfS_S_PiS_iiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16ComputePositionsPfS_S_PiS_iiii"
.LC1:
	.string	"d_ConstantA"
.LC2:
	.string	"d_ConstantB"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16ComputePositionsPfS_S_PiS_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$32, %r9d
	leaq	_ZL11d_ConstantA(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$32, %r9d
	leaq	_ZL11d_ConstantB(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL11d_ConstantB
	.comm	_ZL11d_ConstantB,32,32
	.local	_ZL11d_ConstantA
	.comm	_ZL11d_ConstantA,32,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputePositions(float *g_Data1, float *g_Data2, float *g_Data3, int *d_Ptrs, float *d_Sift, int numPts, int maxPts, int w, int h)
{
int i = __mul24(blockIdx.x, POSBLK_SIZE) + threadIdx.x;
if (i>=numPts)
return;
int p = d_Ptrs[i];
//if (p<w+1 || p>=(w*h-w-1))
//  printf("ComputePositions: read error\n");
float val[7];
val[0] = g_Data2[p];
val[1] = g_Data2[p-1];
val[2] = g_Data2[p+1];
float dx = 0.5f*(val[2] - val[1]);
float dxx = 2.0f*val[0] - val[1] - val[2];
val[3] = g_Data2[p-w];
val[4] = g_Data2[p+w];
float dy = 0.5f*(val[4] - val[3]);
float dyy = 2.0f*val[0] - val[3] - val[4];
val[5] = g_Data3[p];
val[6] = g_Data1[p];
float ds = 0.5f*(val[6] - val[5]);
float dss = 2.0f*val[0] - val[5] - val[6];
float dxy = 0.25f*
(g_Data2[p+w+1] + g_Data2[p-w-1] - g_Data2[p-w+1] - g_Data2[p+w-1]);
float dxs = 0.25f*
(g_Data3[p+1] + g_Data1[p-1] - g_Data1[p+1] - g_Data3[p-1]);
float dys = 0.25f*
(g_Data3[p+w] + g_Data1[p-w] - g_Data3[p-w] - g_Data1[p+w]);
float idxx = dyy*dss - dys*dys;
float idxy = dys*dxs - dxy*dss;
float idxs = dxy*dys - dyy*dxs;
float idyy = dxx*dss - dxs*dxs;
float idys = dxy*dxs - dxx*dys;
float idss = dxx*dyy - dxy*dxy;
float det = idxx*dxx + idxy*dxy + idxs*dxs;
float idet = 1.0f / det;
float pdx = idet*
(idxx*dx + idxy*dy + idxs*ds);
float pdy = idet*
(idxy*dx + idyy*dy + idys*ds);
float pds = idet*
(idxs*dx + idys*dy + idss*ds);
if (pdx<-0.5f || pdx>0.5f || pdy<-0.5f || pdy>0.5f || pds<-0.5f || pds>0.5f){
pdx = __fdividef(dx, dxx);
pdy = __fdividef(dy, dyy);
pds = __fdividef(ds, dss);
}
float dval = 0.5f*(dx*pdx + dy*pdy + ds*pds);
d_Sift[i+0*maxPts] = (p%w) + pdx;
d_Sift[i+1*maxPts] = (p/w) + pdy;
d_Sift[i+2*maxPts] = d_ConstantA[0] * exp2f(pds*d_ConstantB[0]);
d_Sift[i+3*maxPts] = val[0] + dval;
float tra = dxx + dyy;
det = dxx*dyy - dxy*dxy;
d_Sift[i+4*maxPts] = __fdividef(tra*tra, det);
}
	.text
	.file	"ComputePositions.hip"
	.globl	_Z31__device_stub__ComputePositionsPfS_S_PiS_iiii # -- Begin function _Z31__device_stub__ComputePositionsPfS_S_PiS_iiii
	.type	_Z31__device_stub__ComputePositionsPfS_S_PiS_iiii,@function
_Z31__device_stub__ComputePositionsPfS_S_PiS_iiii: # @_Z31__device_stub__ComputePositionsPfS_S_PiS_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16ComputePositionsPfS_S_PiS_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__ComputePositionsPfS_S_PiS_iiii, .Lfunc_end0-_Z31__device_stub__ComputePositionsPfS_S_PiS_iiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16ComputePositionsPfS_S_PiS_iiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$d_ConstantA, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$32, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$d_ConstantB, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$32, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_ConstantA,@object             # @d_ConstantA
	.local	d_ConstantA
	.comm	d_ConstantA,32,16
	.type	d_ConstantB,@object             # @d_ConstantB
	.local	d_ConstantB
	.comm	d_ConstantB,32,16
	.type	_Z16ComputePositionsPfS_S_PiS_iiii,@object # @_Z16ComputePositionsPfS_S_PiS_iiii
	.section	.rodata,"a",@progbits
	.globl	_Z16ComputePositionsPfS_S_PiS_iiii
	.p2align	3, 0x0
_Z16ComputePositionsPfS_S_PiS_iiii:
	.quad	_Z31__device_stub__ComputePositionsPfS_S_PiS_iiii
	.size	_Z16ComputePositionsPfS_S_PiS_iiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16ComputePositionsPfS_S_PiS_iiii"
	.size	.L__unnamed_1, 35

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"d_ConstantA"
	.size	.L__unnamed_2, 12

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"d_ConstantB"
	.size	.L__unnamed_3, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__ComputePositionsPfS_S_PiS_iiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_ConstantA
	.addrsig_sym d_ConstantB
	.addrsig_sym _Z16ComputePositionsPfS_S_PiS_iiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16ComputePositionsPfS_S_PiS_iiii ; -- Begin function _Z16ComputePositionsPfS_S_PiS_iiii
	.globl	_Z16ComputePositionsPfS_S_PiS_iiii
	.p2align	8
	.type	_Z16ComputePositionsPfS_S_PiS_iiii,@function
_Z16ComputePositionsPfS_S_PiS_iiii:     ; @_Z16ComputePositionsPfS_S_PiS_iiii
; %bb.0:
	s_load_b128 s[16:19], s[0:1], 0x28
	s_lshl_b32 s2, s15, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s2, s2, 3
	v_add_nc_u32_e32 v5, s2, v0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s16, v5
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v6, 31, v5
	s_ashr_i32 s19, s18, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[2:3], s[18:19], 2
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v7, vcc_lo
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v3
	v_subrev_nc_u32_e32 v0, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[3:4]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[21:22], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v9, vcc_lo
	v_add_co_u32 v15, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v9, vcc_lo
	v_add_co_u32 v23, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v17, vcc_lo, s6, v21
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v22, vcc_lo
	v_add_co_u32 v19, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v20, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v25, vcc_lo, v15, s2
	v_add_co_ci_u32_e32 v26, vcc_lo, s3, v16, vcc_lo
	v_add_co_u32 v27, vcc_lo, s4, v21
	v_add_co_ci_u32_e32 v28, vcc_lo, s5, v22, vcc_lo
	v_add_co_u32 v21, vcc_lo, s8, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, s9, v22, vcc_lo
	global_load_b96 v[9:11], v[15:16], off offset:-4
	global_load_b96 v[12:14], v[23:24], off offset:-4
	s_clause 0x2
	global_load_b96 v[0:2], v[0:1], off offset:-4
	global_load_b96 v[15:17], v[17:18], off offset:-4
	global_load_b96 v[18:20], v[19:20], off offset:-4
	global_load_b32 v8, v[25:26], off
	global_load_b32 v25, v[27:28], off
	v_add_co_u32 v23, vcc_lo, v23, s2
	v_add_co_ci_u32_e32 v24, vcc_lo, s3, v24, vcc_lo
	global_load_b32 v21, v[21:22], off
	global_load_b32 v22, v[23:24], off
	s_load_b64 s[2:3], s[0:1], 0x20
	s_waitcnt vmcnt(7)
	v_add_f32_e32 v11, v11, v12
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v15, v20, v15
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v8, v25 :: v_dual_sub_f32 v11, v11, v14
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v8, v8, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v9, v11, v9 :: v_dual_sub_f32 v8, v8, v22
	v_sub_f32_e32 v12, v15, v17
	v_fma_f32 v15, v1, 2.0, -v10
	v_mul_f32_e32 v17, 0x3e800000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v14, v15, v13 :: v_dual_mul_f32 v15, 0x3e800000, v8
	v_sub_f32_e32 v12, v12, v18
	v_fma_f32 v18, v1, 2.0, -v0
	v_sub_f32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0x3e800000, v12
	v_fma_f32 v12, v1, 2.0, -v16
	v_sub_f32_e32 v8, v12, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v14, v11
	v_fma_f32 v20, v17, v15, -v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v9, v18, v2 :: v_dual_mul_f32 v18, v8, v17
	v_sub_f32_e32 v2, v13, v10
	v_mul_f32_e32 v10, 0.5, v0
	v_mul_f32_e32 v21, v11, v20
	v_sub_f32_e32 v0, v19, v16
	v_fma_f32 v18, v11, v15, -v18
	v_mul_f32_e32 v12, v15, v15
	v_mul_f32_e32 v2, 0.5, v2
	v_mul_f32_e32 v16, v17, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, v8, v14, -v12
	v_fmac_f32_e32 v21, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v17, v18
	v_div_scale_f32 v22, null, v21, v21, 1.0
	v_div_scale_f32 v25, vcc_lo, 1.0, v21, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	v_fmac_f32_e32 v23, v24, v23
	v_dual_mul_f32 v24, v9, v15 :: v_dual_mul_f32 v15, 0.5, v0
	v_mul_f32_e32 v0, v11, v11
	v_fma_f32 v16, v9, v14, -v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v13, v25, v23
	v_fma_f32 v11, v11, v17, -v24
	v_mul_f32_e32 v17, v15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v22, v13, v25
	v_fmac_f32_e32 v17, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v13, v19, v23
	v_mul_f32_e32 v19, v10, v20
	v_fma_f32 v0, v9, v8, -v0
	v_fma_f32 v20, -v22, v13, v25
	v_mul_f32_e32 v22, v15, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v19, v15, v16 :: v_dual_fmac_f32 v22, v10, v18
	v_div_fmas_f32 v12, v20, v23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, v2, v11
	v_div_fixup_f32 v13, v12, v21, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v17, v2, v18 :: v_dual_mul_f32 v12, v19, v13
	v_dual_fmac_f32 v22, v2, v0 :: v_dual_mul_f32 v11, v17, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v22, v13
	v_min3_f32 v16, v11, v12, v13
	v_max3_f32 v17, v11, v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, -0.5, v16
	v_cmp_lt_f32_e64 s0, 0.5, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_div_scale_f32 v11, null, v9, v9, v10
	v_div_scale_f32 v12, null, v8, v8, v15
	v_div_scale_f32 v13, null, v14, v14, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v16, v11
	v_rcp_f32_e32 v17, v12
	v_div_scale_f32 v19, vcc_lo, v10, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v18, v13
	v_div_scale_f32 v20, s0, v15, v8, v15
	v_div_scale_f32 v24, s1, v2, v14, v2
	v_fma_f32 v21, -v11, v16, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v12, v17, 1.0
	v_fma_f32 v23, -v13, v18, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v16, v21, v16 :: v_dual_fmac_f32 v17, v22, v17
	v_dual_mul_f32 v21, v19, v16 :: v_dual_mul_f32 v22, v20, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v25, -v11, v21, v19
	v_fmac_f32_e32 v18, v23, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, -v12, v22, v20
	v_fmac_f32_e32 v21, v25, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v23, v24, v18 :: v_dual_fmac_f32 v22, v26, v17
	v_fma_f32 v11, -v11, v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v27, -v13, v23, v24
	v_fma_f32 v12, -v12, v22, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v11, v11, v16, v21
	v_fmac_f32_e32 v23, v27, v18
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v12, v12, v17, v22
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v13, -v13, v23, v24
	v_div_fixup_f32 v11, v11, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v12, v12, v8, v15
	v_div_fmas_f32 v13, v13, v18, v23
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v13, v13, v14, v2
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s4
	s_add_i32 s0, s18, s19
	v_mul_f32_e32 v18, v15, v12
	s_xor_b32 s8, s0, s19
	s_ashr_i32 s1, s17, 31
	v_cvt_f32_u32_e32 v14, s8
	s_sub_i32 s0, 0, s8
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, d_ConstantA@rel32@lo+4
	s_addc_u32 s5, s5, d_ConstantA@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, d_ConstantB@rel32@lo+4
	s_addc_u32 s7, s7, d_ConstantB@rel32@hi+12
	v_xor_b32_e32 v19, s19, v4
	v_rcp_iflag_f32_e32 v14, v14
	s_load_b32 s6, s[6:7], 0x0
	v_fmac_f32_e32 v18, v10, v11
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v18, v2, v13 :: v_dual_add_nc_u32 v17, v3, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v14, 0x4f7ffffe, v14
	v_fmac_f32_e32 v1, 0.5, v18
	v_xor_b32_e32 v15, v17, v4
	v_cvt_u32_f32_e32 v14, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v16, s0, v14
	s_mov_b32 s0, s17
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v16, v14, v16
	v_add_nc_u32_e32 v4, v14, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_hi_u32 v14, v15, v4
	v_add3_u32 v4, s17, s17, v5
	v_add_f32_e32 v5, v9, v8
	v_add_co_u32 v8, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
	s_load_b32 s1, s[4:5], 0x0
	v_mul_lo_u32 v10, v14, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v15, v10
	v_add_nc_u32_e32 v15, 1, v14
	v_subrev_nc_u32_e32 v16, s8, v10
	v_cmp_le_u32_e32 vcc_lo, s8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v17, v14, v15 :: v_dual_add_nc_u32 v14, s17, v4
	v_cndmask_b32_e32 v2, v10, v16, vcc_lo
	v_mul_f32_e32 v16, s6, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v10, 1, v17
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	v_cndmask_b32_e32 v2, v17, v10, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v16
	v_add_nc_u32_e32 v16, s17, v14
	s_delay_alu instid0(VALU_DEP_3)
	v_xor_b32_e32 v2, v2, v19
	v_cndmask_b32_e64 v24, 1.0, 0x1f800000, vcc_lo
	v_mul_f32_e32 v20, v5, v5
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v17, 31, v16
	v_sub_nc_u32_e32 v19, v2, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v21, null, v0, v0, v20
	v_div_scale_f32 v10, s0, v20, v0, v20
	v_mul_lo_u32 v25, v19, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v22, v21
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v21, v22, 1.0
	v_fmac_f32_e32 v22, v23, v22
	v_cndmask_b32_e64 v23, 0, 0x42800000, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v18, v10, v22 :: v_dual_fmac_f32 v23, s6, v13
	v_lshlrev_b64 v[13:14], 2, v[14:15]
	v_lshlrev_b64 v[15:16], 2, v[16:17]
	v_sub_nc_u32_e32 v17, v3, v25
	v_fma_f32 v2, -v21, v18, v10
	v_exp_f32_e32 v23, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v17, v17
	v_fmac_f32_e32 v18, v2, v22
	v_add_co_u32 v2, vcc_lo, s2, v13
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v10, -v21, v18, v10
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v13, v23, v24
	v_cvt_f32_i32_e32 v14, v19
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v18, v10, v22, v18
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mul_f32 v13, s1, v13 :: v_dual_add_f32 v12, v12, v14
	v_add_f32_e32 v14, v11, v17
	v_add_co_u32 v10, vcc_lo, s2, v15
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v16, vcc_lo
	v_div_fixup_f32 v0, v18, v0, v20
	s_clause 0x4
	global_store_b32 v[6:7], v14, off
	global_store_b32 v[8:9], v12, off
	global_store_b32 v[4:5], v13, off
	global_store_b32 v[2:3], v1, off
	global_store_b32 v[10:11], v0, off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16ComputePositionsPfS_S_PiS_iiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16ComputePositionsPfS_S_PiS_iiii, .Lfunc_end0-_Z16ComputePositionsPfS_S_PiS_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1700
; NumSgprs: 22
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_ConstantA             ; @d_ConstantA
	.type	d_ConstantA,@object
	.section	.bss,"aw",@nobits
	.globl	d_ConstantA
	.p2align	4, 0x0
d_ConstantA:
	.zero	32
	.size	d_ConstantA, 32

	.protected	d_ConstantB             ; @d_ConstantB
	.type	d_ConstantB,@object
	.globl	d_ConstantB
	.p2align	4, 0x0
d_ConstantB:
	.zero	32
	.size	d_ConstantB, 32

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_ConstantA
	.addrsig_sym d_ConstantB
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16ComputePositionsPfS_S_PiS_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z16ComputePositionsPfS_S_PiS_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
