#include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>

static void HandleError( cudaError_t err, const char *file, int line ) {
    
    if (err != cudaSuccess) {
        
        printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
        exit( EXIT_FAILURE );
    
    }

}

#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))

#define HANDLE_NULL( a ) {if (a == NULL) { \
                            printf( "Host memory failed in %s at line %d\n", \
                                    __FILE__, __LINE__ ); \
                            exit( EXIT_FAILURE );}}

inline double diff_s(struct timeval start, struct timeval end)
{
   return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}

__global__ void readKernel(int *memory, int *memoryToRead)
{
   int tid = threadIdx.x + blockIdx.x*blockDim.x;
   //memory[tid]=memoryToRead[tid];
   //__shared__ int temp; 
   int temp = memoryToRead[tid];
   if(!temp)
      __syncthreads();
}
__global__ void writeKernel(int *memory)
{
   int tid = threadIdx.x + blockIdx.x*blockDim.x;
   memory[tid]=5;
   //memory[tid]++;
}
__global__ void nullKernel(int *memory)
{

}
__global__ void initCudaMallocd(int *memory, int N)
{
   int tid =threadIdx.x;
   if(tid==0){
      for(int k=0;k< N*N/(16*16) ;k++)
         memory[k]=5;
   }
}

void verify(int* memory, int N)
{
   int error = 0;
   for(int i =0; i<N*N/(16*16); i++){
      if(memory[i]!=5){
         error = 1;
         break;
      }
   }
   if(error)
      printf("error in verification\n");
   else
      printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(int* memory, int N)
{
   int tid=threadIdx.x;
   if(tid==0) {
      int error = 0;
      for(int i =0; i<N*N/(16*16); i++){
         if(memory[i]!=5){
            error = 1;
            break;
         }
      }
      if(error)
         printf("error in verification\n");
      else
         printf("verified SUCCESS\n");
   }
}

__global__ void pollute_L2_cache(int *junk)
{
   int tid=threadIdx.x+blockDim.x*blockIdx.x;
   junk[tid]= 5 & 0xDEADBEEF;
}
   int
main( int argc, char *argv[] )
{
    int *hostAllocd, *cudaMallocd, *cpuMallocd;
    int ITERATIONS = 100000;
    int numBytes = 1024;
    struct timeval  tv1, tv2;
    int opt;
    int read=0; //read benchmark? or write?
    int benchmarkType = 0;
    int pollute = 0;

      while ((opt = getopt(argc, argv, "m:b:i:r:p")) != -1) {
      switch (opt) {
         case 'm':
            numBytes = atoi(optarg);
            //assert(numBytes%16 == 0 && numBytes<=1024);
            break;
         case 'b':
            benchmarkType = atoi(optarg);
            break;
         case 'i':
            ITERATIONS = atoi(optarg);
            break;
         case 'r':
            read = atoi(optarg);
            break;
         case 'p':
            pollute = 1;
            break;
 
         default: /* '?' */
            break;
      }
   }


   cpuMallocd = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16));
   assert(cpuMallocd);
   HANDLE_ERROR( cudaHostAlloc( &hostAllocd, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
   int *junk;
   HANDLE_ERROR( cudaHostAlloc( &junk, sizeof(int)*512*64, 0 ) );
   for(int k=0;k< numBytes ;k++){
      cpuMallocd[k]=1;
      hostAllocd[k]=1;
   }

   HANDLE_ERROR( cudaMalloc( &cudaMallocd, sizeof(int)*numBytes) );
   HANDLE_ERROR( cudaMemcpy( cudaMallocd,hostAllocd, sizeof(int)*numBytes,cudaMemcpyDefault) );

   //int num_of_blocks=1;
   //int num_of_threads_per_block=numBytes;
   //if(numBytes>1024){
   //   num_of_blocks = 16;
   //   num_of_threads_per_block = numBytes/16;
   //}
   int num_of_blocks,num_of_threads_per_block;
  // if(numBytes==1)
  // {
  //    num_of_blocks=1;
  //    num_of_threads_per_block=1;
  // }
  // else
  // {
  //    assert(numBytes%2==0);
  //    num_of_blocks=2;
  //    num_of_threads_per_block=numBytes/2;
  // }
   num_of_blocks=numBytes/16;
   num_of_threads_per_block=numBytes/16;
   //HANDLE_ERROR(cudaDeviceReset());  //this causes kernel launch failure!! check with cuda-memcheck
   HANDLE_ERROR(cudaFree(0));
   switch (benchmarkType) {
      case 0: {//read/Write to hostAlloc'd data
                 if(read)
                 {

                    int *memoryToRead;
                    HANDLE_ERROR( cudaHostAlloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
                    for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
                       memoryToRead[k]=5;
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       if(pollute) {
                          pollute_L2_cache<<<512,64>>>(junk);
                          HANDLE_ERROR( cudaDeviceSynchronize());
                       }
                       readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
                       HANDLE_ERROR( cudaDeviceSynchronize());
                    }
                    gettimeofday(&tv2, NULL);
                    cudaFreeHost(memoryToRead);
                    //verify(hostAllocd,numBytes);
                 }
                 else
                 {
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       if(pollute) {
                          pollute_L2_cache<<<512,64>>>(junk);
                          HANDLE_ERROR( cudaDeviceSynchronize());
                       }

                       writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
                       HANDLE_ERROR( cudaDeviceSynchronize());
                    }
                    gettimeofday(&tv2, NULL);
                    //verify(hostAllocd,numBytes);
                 }
                 HANDLE_ERROR( cudaGetLastError());
                 double elapsedTimeSeconds = diff_s(tv1,tv2);
                 printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
                 break;
              }
   
      case 1: {//read/Write to cudaMalloc'd data
                 if(read)
                 {

                    int *memoryToRead;
                    HANDLE_ERROR( cudaMalloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16) ) );
                    initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
                    HANDLE_ERROR( cudaDeviceSynchronize());
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       if(pollute) {
                          pollute_L2_cache<<<512,64>>>(junk);
                          HANDLE_ERROR( cudaDeviceSynchronize());
                       }

                       readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
                       HANDLE_ERROR( cudaDeviceSynchronize());
                    }
                    gettimeofday(&tv2, NULL);
                    cudaFree(memoryToRead);
                    //verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
                    //HANDLE_ERROR( cudaDeviceSynchronize());
                 }
                 else
                 {
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       if(pollute) {
                          pollute_L2_cache<<<512,64>>>(junk);
                          HANDLE_ERROR( cudaDeviceSynchronize());
                       }

                       writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
                       HANDLE_ERROR( cudaDeviceSynchronize());
                    }
                    gettimeofday(&tv2, NULL);
                    //verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
                    //HANDLE_ERROR( cudaDeviceSynchronize());
                 }
                 HANDLE_ERROR( cudaGetLastError());
                 double elapsedTimeSeconds = diff_s(tv1,tv2);
                 printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
                 break;
              }

      case 2:
              {
                 gettimeofday(&tv1, NULL);
                 for(int i = 0; i < ITERATIONS; i++) {
                    nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
                    HANDLE_ERROR( cudaDeviceSynchronize());
                 }
                 gettimeofday(&tv2, NULL);
                 HANDLE_ERROR( cudaGetLastError());
                 double elapsedTimeSeconds = diff_s(tv1,tv2);
                 printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
              
              }
      case 3: {//read/Write to cpu mallocd data
                 if(read)
                 {

                    int temp;
                    int *memoryToRead = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16) );
                    assert(memoryToRead);
                    for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
                       memoryToRead[k]=5;
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       for(int j=0; j<numBytes*numBytes/(16*16); j++){
                          temp=memoryToRead[j];
                          if(!temp)
                             cpuMallocd[j]=temp;
                       }
                    }
                    gettimeofday(&tv2, NULL);
                    free(memoryToRead);
                    //verify(cpuMallocd,numBytes);
                 }
                 else
                 {
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
                          cpuMallocd[k]=5;
                    }
                    gettimeofday(&tv2, NULL);
                    verify(cpuMallocd,numBytes);
                 }
                 double elapsedTimeSeconds = diff_s(tv1,tv2);
                 printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
                 break;
              }
   

   }

   free(cpuMallocd);
   cudaFree(cudaMallocd);
   cudaFreeHost(hostAllocd);
   cudaFreeHost(junk);
   cudaDeviceReset();
   return 0;
}

	.file	"tmpxft_00298d78_00000000-6_latencyTest.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2046:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2046:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/mkdashti/bandwidthTest/master/latency-ints/latencyTest.cu"
.LC1:
	.string	"%s in %s at line %d\n"
	.text
	.type	_ZL11HandleError9cudaErrorPKci.constprop.0, @function
_ZL11HandleError9cudaErrorPKci.constprop.0:
.LFB2201:
	.cfi_startproc
	testl	%edi, %edi
	je	.L2
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%esi, 12(%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r8d
	movl	$2, %edi
	leaq	.LC0(%rip), %rcx
	movq	%rax, %rdx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2201:
	.size	_ZL11HandleError9cudaErrorPKci.constprop.0, .-_ZL11HandleError9cudaErrorPKci.constprop.0
	.section	.rodata.str1.1
.LC2:
	.string	"verified SUCCESS\n"
.LC3:
	.string	"error in verification\n"
	.text
	.globl	_Z6verifyPii
	.type	_Z6verifyPii, @function
_Z6verifyPii:
.LFB2042:
	.cfi_startproc
	endbr64
	imull	%esi, %esi
	xorl	%eax, %eax
	sarl	$8, %esi
.L9:
	cmpl	%eax, %esi
	jle	.L14
	incq	%rax
	cmpl	$5, -4(%rdi,%rax,4)
	je	.L9
	leaq	.LC3(%rip), %rsi
	jmp	.L13
.L14:
	leaq	.LC2(%rip), %rsi
.L13:
	movl	$2, %edi
	xorl	%eax, %eax
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2042:
	.size	_Z6verifyPii, .-_Z6verifyPii
	.globl	_Z32__device_stub__Z10readKernelPiS_PiS_
	.type	_Z32__device_stub__Z10readKernelPiS_PiS_, @function
_Z32__device_stub__Z10readKernelPiS_PiS_:
.LFB2068:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10readKernelPiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L15:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2068:
	.size	_Z32__device_stub__Z10readKernelPiS_PiS_, .-_Z32__device_stub__Z10readKernelPiS_PiS_
	.globl	_Z10readKernelPiS_
	.type	_Z10readKernelPiS_, @function
_Z10readKernelPiS_:
.LFB2069:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10readKernelPiS_PiS_
	.cfi_endproc
.LFE2069:
	.size	_Z10readKernelPiS_, .-_Z10readKernelPiS_
	.globl	_Z31__device_stub__Z11writeKernelPiPi
	.type	_Z31__device_stub__Z11writeKernelPiPi, @function
_Z31__device_stub__Z11writeKernelPiPi:
.LFB2070:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z11writeKernelPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L20:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2070:
	.size	_Z31__device_stub__Z11writeKernelPiPi, .-_Z31__device_stub__Z11writeKernelPiPi
	.globl	_Z11writeKernelPi
	.type	_Z11writeKernelPi, @function
_Z11writeKernelPi:
.LFB2071:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z11writeKernelPiPi
	.cfi_endproc
.LFE2071:
	.size	_Z11writeKernelPi, .-_Z11writeKernelPi
	.globl	_Z30__device_stub__Z10nullKernelPiPi
	.type	_Z30__device_stub__Z10nullKernelPiPi, @function
_Z30__device_stub__Z10nullKernelPiPi:
.LFB2072:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z10nullKernelPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L25:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2072:
	.size	_Z30__device_stub__Z10nullKernelPiPi, .-_Z30__device_stub__Z10nullKernelPiPi
	.globl	_Z10nullKernelPi
	.type	_Z10nullKernelPi, @function
_Z10nullKernelPi:
.LFB2073:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z10nullKernelPiPi
	.cfi_endproc
.LFE2073:
	.size	_Z10nullKernelPi, .-_Z10nullKernelPi
	.globl	_Z36__device_stub__Z15initCudaMallocdPiiPii
	.type	_Z36__device_stub__Z15initCudaMallocdPiiPii, @function
_Z36__device_stub__Z15initCudaMallocdPiiPii:
.LFB2074:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15initCudaMallocdPii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L30:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2074:
	.size	_Z36__device_stub__Z15initCudaMallocdPiiPii, .-_Z36__device_stub__Z15initCudaMallocdPiiPii
	.globl	_Z15initCudaMallocdPii
	.type	_Z15initCudaMallocdPii, @function
_Z15initCudaMallocdPii:
.LFB2075:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z15initCudaMallocdPiiPii
	.cfi_endproc
.LFE2075:
	.size	_Z15initCudaMallocdPii, .-_Z15initCudaMallocdPii
	.globl	_Z38__device_stub__Z17verifyCudaMallocdPiiPii
	.type	_Z38__device_stub__Z17verifyCudaMallocdPiiPii, @function
_Z38__device_stub__Z17verifyCudaMallocdPiiPii:
.LFB2076:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z17verifyCudaMallocdPii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L35:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2076:
	.size	_Z38__device_stub__Z17verifyCudaMallocdPiiPii, .-_Z38__device_stub__Z17verifyCudaMallocdPiiPii
	.globl	_Z17verifyCudaMallocdPii
	.type	_Z17verifyCudaMallocdPii, @function
_Z17verifyCudaMallocdPii:
.LFB2077:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z17verifyCudaMallocdPiiPii
	.cfi_endproc
.LFE2077:
	.size	_Z17verifyCudaMallocdPii, .-_Z17verifyCudaMallocdPii
	.globl	_Z36__device_stub__Z16pollute_L2_cachePiPi
	.type	_Z36__device_stub__Z16pollute_L2_cachePiPi, @function
_Z36__device_stub__Z16pollute_L2_cachePiPi:
.LFB2078:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z16pollute_L2_cachePi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L40:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2078:
	.size	_Z36__device_stub__Z16pollute_L2_cachePiPi, .-_Z36__device_stub__Z16pollute_L2_cachePiPi
	.globl	_Z16pollute_L2_cachePi
	.type	_Z16pollute_L2_cachePi, @function
_Z16pollute_L2_cachePi:
.LFB2079:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z16pollute_L2_cachePiPi
	.cfi_endproc
.LFE2079:
	.size	_Z16pollute_L2_cachePi, .-_Z16pollute_L2_cachePi
	.section	.rodata.str1.1
.LC4:
	.string	"read"
.LC5:
	.string	"write"
.LC6:
	.string	"m:b:i:r:p"
.LC8:
	.string	"[%s] Latency including kernel launch overhead = %f us\n"
.LC9:
	.string	"null kernel launch overhead = %f us\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	leaq	.LC6(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	$100000, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	$1024, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, (%rsp)
	movq	%rsi, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
.L46:
	movq	8(%rsp), %rsi
	movl	(%rsp), %edi
	movq	%r12, %rdx
	call	getopt@PLT
	cmpl	$-1, %eax
	je	.L130
	cmpl	$109, %eax
	je	.L47
	jg	.L48
	cmpl	$98, %eax
	je	.L49
	cmpl	$105, %eax
	jne	.L46
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	movl	%eax, %ebp
	jmp	.L46
.L48:
	cmpl	$112, %eax
	je	.L107
	cmpl	$114, %eax
	jne	.L46
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	movl	%eax, %r14d
	jmp	.L46
.L47:
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	movl	%eax, %ebx
	jmp	.L46
.L49:
	movq	optarg(%rip), %rdi
	call	atoi@PLT
	movl	%eax, %r13d
	jmp	.L46
.L107:
	movl	$1, %r15d
	jmp	.L46
.L130:
	movslq	%ebx, %r12
	movq	%r12, %rax
	imulq	%r12, %rax
	salq	$2, %rax
	shrq	$8, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rsi
	xorl	%edx, %edx
	leaq	24(%rsp), %rdi
	movq	%rax, 8(%rsp)
	call	cudaHostAlloc@PLT
	movl	$134, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%edx, %edx
	leaq	40(%rsp), %rdi
	movl	$131072, %esi
	call	cudaHostAlloc@PLT
	movl	$136, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	24(%rsp), %rdx
	xorl	%eax, %eax
.L54:
	cmpl	%eax, %ebx
	jle	.L131
	movq	8(%rsp), %rcx
	movl	$1, (%rdx,%rax,4)
	movl	$1, (%rcx,%rax,4)
	incq	%rax
	jmp	.L54
.L131:
	salq	$2, %r12
	leaq	32(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movl	$142, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdi
	movq	%r12, %rdx
	movl	$4, %ecx
	call	cudaMemcpy@PLT
	movl	$143, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movl	%ebx, %eax
	movl	$16, %ecx
	xorl	%edi, %edi
	cltd
	idivl	%ecx
	movl	%eax, %r12d
	call	cudaFree@PLT
	movl	$166, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	cmpl	$2, %r13d
	je	.L56
	jg	.L57
	testl	%r13d, %r13d
	je	.L58
	decl	%r13d
	je	.L59
	jmp	.L60
.L57:
	cmpl	$3, %r13d
	je	.L61
	jmp	.L60
.L58:
	testl	%r14d, %r14d
	je	.L62
	movq	(%rsp), %rsi
	xorl	%edx, %edx
	imull	%ebx, %ebx
	leaq	48(%rsp), %rdi
	call	cudaHostAlloc@PLT
	movl	$173, %esi
	movl	%eax, %edi
	sarl	$8, %ebx
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	48(%rsp), %rdx
	xorl	%eax, %eax
.L63:
	cmpl	%eax, %ebx
	jle	.L132
	movl	$5, (%rdx,%rax,4)
	incq	%rax
	jmp	.L63
.L132:
	leaq	72(%rsp), %rdi
	xorl	%esi, %esi
	movl	$67108865, %ebx
	call	gettimeofday@PLT
	salq	$6, %rbx
.L65:
	cmpl	%r13d, %ebp
	jle	.L133
	testl	%r15d, %r15d
	je	.L66
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rbx, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rdi, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L67
	movq	40(%rsp), %rdi
	call	_Z36__device_stub__Z16pollute_L2_cachePiPi
.L67:
	call	cudaDeviceSynchronize@PLT
	movl	$180, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
.L66:
	movabsq	$4294967297, %rax
	movl	%r12d, 88(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, 92(%rsp)
	movl	96(%rsp), %ecx
	movq	%rax, 64(%rsp)
	movq	88(%rsp), %rdx
	movl	%r12d, 60(%rsp)
	movl	68(%rsp), %esi
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L68
	movq	48(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z32__device_stub__Z10readKernelPiS_PiS_
.L68:
	call	cudaDeviceSynchronize@PLT
	movl	$183, %esi
	incl	%r13d
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	jmp	.L65
.L133:
	leaq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	movq	48(%rsp), %rdi
	call	cudaFreeHost@PLT
	jmp	.L70
.L62:
	leaq	72(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	movabsq	$4294967360, %r13
	call	gettimeofday@PLT
.L71:
	cmpl	%ebx, %ebp
	jle	.L134
	testl	%r15d, %r15d
	je	.L72
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%r13, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rdi, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L73
	movq	40(%rsp), %rdi
	call	_Z36__device_stub__Z16pollute_L2_cachePiPi
.L73:
	call	cudaDeviceSynchronize@PLT
	movl	$195, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
.L72:
	movabsq	$4294967297, %rax
	movl	%r12d, 88(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, 92(%rsp)
	movl	96(%rsp), %ecx
	movq	%rax, 64(%rsp)
	movq	88(%rsp), %rdx
	movl	%r12d, 60(%rsp)
	movl	68(%rsp), %esi
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L74
	movq	24(%rsp), %rdi
	call	_Z31__device_stub__Z11writeKernelPiPi
.L74:
	call	cudaDeviceSynchronize@PLT
	movl	$199, %esi
	incl	%ebx
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	jmp	.L71
.L134:
	leaq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
.L70:
	call	cudaGetLastError@PLT
	movl	$204, %esi
	movl	%eax, %edi
	jmp	.L129
.L59:
	testl	%r14d, %r14d
	leaq	72(%rsp), %r13
	je	.L77
	movq	(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$215, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 96(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 88(%rsp)
	movq	%rdi, 72(%rsp)
	movl	$1, 80(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L78
	movq	48(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z36__device_stub__Z15initCudaMallocdPiiPii
.L78:
	call	cudaDeviceSynchronize@PLT
	movl	$217, %esi
	xorl	%ebx, %ebx
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	%r13, %rdi
	xorl	%esi, %esi
	movabsq	$4294967360, %r13
	call	gettimeofday@PLT
.L79:
	cmpl	%ebx, %ebp
	jle	.L135
	testl	%r15d, %r15d
	je	.L80
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%r13, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rdi, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L81
	movq	40(%rsp), %rdi
	call	_Z36__device_stub__Z16pollute_L2_cachePiPi
.L81:
	call	cudaDeviceSynchronize@PLT
	movl	$222, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
.L80:
	movabsq	$4294967297, %rax
	movl	%r12d, 88(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, 92(%rsp)
	movl	96(%rsp), %ecx
	movq	%rax, 64(%rsp)
	movq	88(%rsp), %rdx
	movl	%r12d, 60(%rsp)
	movl	68(%rsp), %esi
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L82
	movq	48(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z32__device_stub__Z10readKernelPiS_PiS_
.L82:
	call	cudaDeviceSynchronize@PLT
	movl	$226, %esi
	incl	%ebx
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	jmp	.L79
.L135:
	leaq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	jmp	.L84
.L77:
	movq	%r13, %rdi
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	movabsq	$4294967360, %r13
	call	gettimeofday@PLT
.L85:
	cmpl	%ebx, %ebp
	jle	.L136
	testl	%r15d, %r15d
	je	.L86
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%r13, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rdi, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L87
	movq	40(%rsp), %rdi
	call	_Z36__device_stub__Z16pollute_L2_cachePiPi
.L87:
	call	cudaDeviceSynchronize@PLT
	movl	$239, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
.L86:
	movabsq	$4294967297, %rax
	movl	%r12d, 88(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, 92(%rsp)
	movl	96(%rsp), %ecx
	movq	%rax, 64(%rsp)
	movq	88(%rsp), %rdx
	movl	%r12d, 60(%rsp)
	movl	68(%rsp), %esi
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L88
	movq	32(%rsp), %rdi
	call	_Z31__device_stub__Z11writeKernelPiPi
.L88:
	call	cudaDeviceSynchronize@PLT
	movl	$243, %esi
	incl	%ebx
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	jmp	.L85
.L136:
	leaq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
.L84:
	call	cudaGetLastError@PLT
	movl	$249, %esi
	movl	%eax, %edi
.L129:
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	jmp	.L101
.L56:
	leaq	72(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%r15d, %r15d
	movabsq	$4294967297, %r13
	call	gettimeofday@PLT
.L91:
	cmpl	%r15d, %ebp
	jle	.L137
	movq	%r13, 92(%rsp)
	movl	96(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, 64(%rsp)
	movl	68(%rsp), %esi
	movl	%r12d, 88(%rsp)
	movq	88(%rsp), %rdx
	movl	%r12d, 60(%rsp)
	movq	60(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L92
	xorl	%edi, %edi
	call	_Z30__device_stub__Z10nullKernelPiPi
.L92:
	call	cudaDeviceSynchronize@PLT
	movl	$260, %esi
	incl	%r15d
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	jmp	.L91
.L137:
	leaq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	call	cudaGetLastError@PLT
	movl	$263, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movq	96(%rsp), %rax
	subq	80(%rsp), %rax
	leaq	.LC9(%rip), %rsi
	cvtsi2sdq	%rax, %xmm0
	movq	88(%rsp), %rax
	subq	72(%rsp), %rax
	movl	$2, %edi
	movsd	.LC7(%rip), %xmm1
	cvtsi2sdq	%rax, %xmm2
	movb	$1, %al
	divsd	%xmm1, %xmm0
	addsd	%xmm2, %xmm0
	mulsd	%xmm1, %xmm0
	cvtsi2ssl	%ebp, %xmm1
	cvtss2sd	%xmm1, %xmm1
	divsd	%xmm1, %xmm0
	call	__printf_chk@PLT
.L61:
	testl	%r14d, %r14d
	je	.L94
	imull	%ebx, %ebx
	movq	(%rsp), %rdi
	call	malloc@PLT
	movq	%rax, %r12
	sarl	$8, %ebx
	xorl	%eax, %eax
.L95:
	cmpl	%eax, %ebx
	jle	.L138
	movl	$5, (%r12,%rax,4)
	incq	%rax
	jmp	.L95
.L138:
	leaq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	xorl	%edx, %edx
.L97:
	cmpl	%edx, %ebp
	jle	.L139
	xorl	%eax, %eax
.L100:
	cmpl	%eax, %ebx
	jle	.L140
	cmpl	$0, (%r12,%rax,4)
	jne	.L98
	movq	8(%rsp), %rcx
	xorl	%esi, %esi
	movl	%esi, (%rcx,%rax,4)
.L98:
	incq	%rax
	jmp	.L100
.L140:
	incl	%edx
	jmp	.L97
.L139:
	leaq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	movq	%r12, %rdi
	call	free@PLT
	jmp	.L101
.L94:
	leaq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	movl	%ebx, %ecx
	xorl	%edx, %edx
	imull	%ebx, %ecx
	sarl	$8, %ecx
.L102:
	cmpl	%edx, %ebp
	jle	.L141
	xorl	%eax, %eax
.L104:
	cmpl	%eax, %ecx
	jle	.L142
	movq	8(%rsp), %rsi
	movl	$5, (%rsi,%rax,4)
	incq	%rax
	jmp	.L104
.L142:
	incl	%edx
	jmp	.L102
.L141:
	leaq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	movq	8(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z6verifyPii
.L101:
	movq	96(%rsp), %rax
	subq	80(%rsp), %rax
	leaq	.LC5(%rip), %rdx
	leaq	.LC8(%rip), %rsi
	cvtsi2sdq	%rax, %xmm0
	movq	88(%rsp), %rax
	subq	72(%rsp), %rax
	decl	%r14d
	movsd	.LC7(%rip), %xmm1
	cvtsi2sdq	%rax, %xmm2
	movl	$2, %edi
	leaq	.LC4(%rip), %rax
	cmove	%rax, %rdx
	movb	$1, %al
	divsd	%xmm1, %xmm0
	addsd	%xmm2, %xmm0
	mulsd	%xmm1, %xmm0
	cvtsi2ssl	%ebp, %xmm1
	cvtss2sd	%xmm1, %xmm1
	divsd	%xmm1, %xmm0
	call	__printf_chk@PLT
.L60:
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	40(%rsp), %rdi
	call	cudaFreeHost@PLT
	call	cudaDeviceReset@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L106
	call	__stack_chk_fail@PLT
.L106:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z16pollute_L2_cachePi"
.LC11:
	.string	"_Z17verifyCudaMallocdPii"
.LC12:
	.string	"_Z15initCudaMallocdPii"
.LC13:
	.string	"_Z10nullKernelPi"
.LC14:
	.string	"_Z11writeKernelPi"
.LC15:
	.string	"_Z10readKernelPiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2081:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16pollute_L2_cachePi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17verifyCudaMallocdPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15initCudaMallocdPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10nullKernelPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11writeKernelPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10readKernelPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2081:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC7:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>

static void HandleError( hipError_t err, const char *file, int line ) {
    
    if (err != hipSuccess) {
        
        printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
        exit( EXIT_FAILURE );
    
    }

}

#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))

#define HANDLE_NULL( a ) {if (a == NULL) { \
                            printf( "Host memory failed in %s at line %d\n", \
                                    __FILE__, __LINE__ ); \
                            exit( EXIT_FAILURE );}}

inline double diff_s(struct timeval start, struct timeval end)
{
   return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}

__global__ void readKernel(int *memory, int *memoryToRead)
{
   int tid = threadIdx.x + blockIdx.x*blockDim.x;
   //memory[tid]=memoryToRead[tid];
   //__shared__ int temp; 
   int temp = memoryToRead[tid];
   if(!temp)
      __syncthreads();
}
__global__ void writeKernel(int *memory)
{
   int tid = threadIdx.x + blockIdx.x*blockDim.x;
   memory[tid]=5;
   //memory[tid]++;
}
__global__ void nullKernel(int *memory)
{

}
__global__ void initCudaMallocd(int *memory, int N)
{
   int tid =threadIdx.x;
   if(tid==0){
      for(int k=0;k< N*N/(16*16) ;k++)
         memory[k]=5;
   }
}

void verify(int* memory, int N)
{
   int error = 0;
   for(int i =0; i<N*N/(16*16); i++){
      if(memory[i]!=5){
         error = 1;
         break;
      }
   }
   if(error)
      printf("error in verification\n");
   else
      printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(int* memory, int N)
{
   int tid=threadIdx.x;
   if(tid==0) {
      int error = 0;
      for(int i =0; i<N*N/(16*16); i++){
         if(memory[i]!=5){
            error = 1;
            break;
         }
      }
      if(error)
         printf("error in verification\n");
      else
         printf("verified SUCCESS\n");
   }
}

__global__ void pollute_L2_cache(int *junk)
{
   int tid=threadIdx.x+blockDim.x*blockIdx.x;
   junk[tid]= 5 & 0xDEADBEEF;
}
   int
main( int argc, char *argv[] )
{
    int *hostAllocd, *cudaMallocd, *cpuMallocd;
    int ITERATIONS = 100000;
    int numBytes = 1024;
    struct timeval  tv1, tv2;
    int opt;
    int read=0; //read benchmark? or write?
    int benchmarkType = 0;
    int pollute = 0;

      while ((opt = getopt(argc, argv, "m:b:i:r:p")) != -1) {
      switch (opt) {
         case 'm':
            numBytes = atoi(optarg);
            //assert(numBytes%16 == 0 && numBytes<=1024);
            break;
         case 'b':
            benchmarkType = atoi(optarg);
            break;
         case 'i':
            ITERATIONS = atoi(optarg);
            break;
         case 'r':
            read = atoi(optarg);
            break;
         case 'p':
            pollute = 1;
            break;
 
         default: /* '?' */
            break;
      }
   }


   cpuMallocd = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16));
   assert(cpuMallocd);
   HANDLE_ERROR( hipHostAlloc( &hostAllocd, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
   int *junk;
   HANDLE_ERROR( hipHostAlloc( &junk, sizeof(int)*512*64, 0 ) );
   for(int k=0;k< numBytes ;k++){
      cpuMallocd[k]=1;
      hostAllocd[k]=1;
   }

   HANDLE_ERROR( hipMalloc( &cudaMallocd, sizeof(int)*numBytes) );
   HANDLE_ERROR( hipMemcpy( cudaMallocd,hostAllocd, sizeof(int)*numBytes,hipMemcpyDefault) );

   //int num_of_blocks=1;
   //int num_of_threads_per_block=numBytes;
   //if(numBytes>1024){
   //   num_of_blocks = 16;
   //   num_of_threads_per_block = numBytes/16;
   //}
   int num_of_blocks,num_of_threads_per_block;
  // if(numBytes==1)
  // {
  //    num_of_blocks=1;
  //    num_of_threads_per_block=1;
  // }
  // else
  // {
  //    assert(numBytes%2==0);
  //    num_of_blocks=2;
  //    num_of_threads_per_block=numBytes/2;
  // }
   num_of_blocks=numBytes/16;
   num_of_threads_per_block=numBytes/16;
   //HANDLE_ERROR(cudaDeviceReset());  //this causes kernel launch failure!! check with cuda-memcheck
   HANDLE_ERROR(hipFree(0));
   switch (benchmarkType) {
      case 0: {//read/Write to hostAlloc'd data
                 if(read)
                 {

                    int *memoryToRead;
                    HANDLE_ERROR( hipHostAlloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
                    for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
                       memoryToRead[k]=5;
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       if(pollute) {
                          pollute_L2_cache<<<512,64>>>(junk);
                          HANDLE_ERROR( hipDeviceSynchronize());
                       }
                       readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
                       HANDLE_ERROR( hipDeviceSynchronize());
                    }
                    gettimeofday(&tv2, NULL);
                    hipHostFree(memoryToRead);
                    //verify(hostAllocd,numBytes);
                 }
                 else
                 {
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       if(pollute) {
                          pollute_L2_cache<<<512,64>>>(junk);
                          HANDLE_ERROR( hipDeviceSynchronize());
                       }

                       writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
                       HANDLE_ERROR( hipDeviceSynchronize());
                    }
                    gettimeofday(&tv2, NULL);
                    //verify(hostAllocd,numBytes);
                 }
                 HANDLE_ERROR( hipGetLastError());
                 double elapsedTimeSeconds = diff_s(tv1,tv2);
                 printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
                 break;
              }
   
      case 1: {//read/Write to cudaMalloc'd data
                 if(read)
                 {

                    int *memoryToRead;
                    HANDLE_ERROR( hipMalloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16) ) );
                    initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
                    HANDLE_ERROR( hipDeviceSynchronize());
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       if(pollute) {
                          pollute_L2_cache<<<512,64>>>(junk);
                          HANDLE_ERROR( hipDeviceSynchronize());
                       }

                       readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
                       HANDLE_ERROR( hipDeviceSynchronize());
                    }
                    gettimeofday(&tv2, NULL);
                    hipFree(memoryToRead);
                    //verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
                    //HANDLE_ERROR( cudaDeviceSynchronize());
                 }
                 else
                 {
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       if(pollute) {
                          pollute_L2_cache<<<512,64>>>(junk);
                          HANDLE_ERROR( hipDeviceSynchronize());
                       }

                       writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
                       HANDLE_ERROR( hipDeviceSynchronize());
                    }
                    gettimeofday(&tv2, NULL);
                    //verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
                    //HANDLE_ERROR( cudaDeviceSynchronize());
                 }
                 HANDLE_ERROR( hipGetLastError());
                 double elapsedTimeSeconds = diff_s(tv1,tv2);
                 printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
                 break;
              }

      case 2:
              {
                 gettimeofday(&tv1, NULL);
                 for(int i = 0; i < ITERATIONS; i++) {
                    nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
                    HANDLE_ERROR( hipDeviceSynchronize());
                 }
                 gettimeofday(&tv2, NULL);
                 HANDLE_ERROR( hipGetLastError());
                 double elapsedTimeSeconds = diff_s(tv1,tv2);
                 printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
              
              }
      case 3: {//read/Write to cpu mallocd data
                 if(read)
                 {

                    int temp;
                    int *memoryToRead = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16) );
                    assert(memoryToRead);
                    for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
                       memoryToRead[k]=5;
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       for(int j=0; j<numBytes*numBytes/(16*16); j++){
                          temp=memoryToRead[j];
                          if(!temp)
                             cpuMallocd[j]=temp;
                       }
                    }
                    gettimeofday(&tv2, NULL);
                    free(memoryToRead);
                    //verify(cpuMallocd,numBytes);
                 }
                 else
                 {
                    gettimeofday(&tv1, NULL);
                    for(int i = 0; i < ITERATIONS; i++) {
                       for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
                          cpuMallocd[k]=5;
                    }
                    gettimeofday(&tv2, NULL);
                    verify(cpuMallocd,numBytes);
                 }
                 double elapsedTimeSeconds = diff_s(tv1,tv2);
                 printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
                 break;
              }
   

   }

   free(cpuMallocd);
   hipFree(cudaMallocd);
   hipHostFree(hostAllocd);
   hipHostFree(junk);
   hipDeviceReset();
   return 0;
}

	.text
	.file	"latencyTest.hip"
	.globl	_Z25__device_stub__readKernelPiS_ # -- Begin function _Z25__device_stub__readKernelPiS_
	.type	_Z25__device_stub__readKernelPiS_,@function
_Z25__device_stub__readKernelPiS_:      # @_Z25__device_stub__readKernelPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10readKernelPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__readKernelPiS_, .Lfunc_end0-_Z25__device_stub__readKernelPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__writeKernelPi # -- Begin function _Z26__device_stub__writeKernelPi
	.type	_Z26__device_stub__writeKernelPi,@function
_Z26__device_stub__writeKernelPi:       # @_Z26__device_stub__writeKernelPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11writeKernelPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z26__device_stub__writeKernelPi, .Lfunc_end1-_Z26__device_stub__writeKernelPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__nullKernelPi # -- Begin function _Z25__device_stub__nullKernelPi
	.type	_Z25__device_stub__nullKernelPi,@function
_Z25__device_stub__nullKernelPi:        # @_Z25__device_stub__nullKernelPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10nullKernelPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__nullKernelPi, .Lfunc_end2-_Z25__device_stub__nullKernelPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__initCudaMallocdPii # -- Begin function _Z30__device_stub__initCudaMallocdPii
	.type	_Z30__device_stub__initCudaMallocdPii,@function
_Z30__device_stub__initCudaMallocdPii:  # @_Z30__device_stub__initCudaMallocdPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15initCudaMallocdPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z30__device_stub__initCudaMallocdPii, .Lfunc_end3-_Z30__device_stub__initCudaMallocdPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z6verifyPii                    # -- Begin function _Z6verifyPii
	.type	_Z6verifyPii,@function
_Z6verifyPii:                           # @_Z6verifyPii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
	movq	%rdi, %rax
	imull	%esi, %esi
	movl	$.Lstr, %edi
	cmpl	$256, %esi                      # imm = 0x100
	jb	puts@PLT                        # TAILCALL
# %bb.1:                                # %.lr.ph.preheader
	shrl	$8, %esi
	xorl	%ecx, %ecx
	jmp	.LBB4_3
.LBB4_2:                                #   in Loop: Header=BB4_3 Depth=1
	incq	%rcx
	cmpq	%rcx, %rsi
	je	puts@PLT                        # TAILCALL
.LBB4_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	cmpl	$5, (%rax,%rcx,4)
	je	.LBB4_2
# %bb.4:
	movl	$.Lstr.1, %edi
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end4:
	.size	_Z6verifyPii, .Lfunc_end4-_Z6verifyPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__verifyCudaMallocdPii # -- Begin function _Z32__device_stub__verifyCudaMallocdPii
	.type	_Z32__device_stub__verifyCudaMallocdPii,@function
_Z32__device_stub__verifyCudaMallocdPii: # @_Z32__device_stub__verifyCudaMallocdPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17verifyCudaMallocdPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z32__device_stub__verifyCudaMallocdPii, .Lfunc_end5-_Z32__device_stub__verifyCudaMallocdPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__pollute_L2_cachePi # -- Begin function _Z31__device_stub__pollute_L2_cachePi
	.type	_Z31__device_stub__pollute_L2_cachePi,@function
_Z31__device_stub__pollute_L2_cachePi:  # @_Z31__device_stub__pollute_L2_cachePi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16pollute_L2_cachePi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z31__device_stub__pollute_L2_cachePi, .Lfunc_end6-_Z31__device_stub__pollute_L2_cachePi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI7_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movl	%edi, %r12d
	movl	$100000, %ebx                   # imm = 0x186A0
	movl	$1024, %r15d                    # imm = 0x400
	xorl	%r13d, %r13d
	movb	$1, %al
	movl	%eax, 16(%rsp)                  # 4-byte Spill
	xorl	%ebp, %ebp
.LBB7_1:                                # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %edx
	movl	%r12d, %edi
	movq	%r14, %rsi
	callq	getopt
                                        # kill: def $eax killed $eax def $rax
	leal	-105(%rax), %ecx
	cmpl	$9, %ecx
	ja	.LBB7_2
# %bb.96:                               #   in Loop: Header=BB7_1 Depth=1
	jmpq	*.LJTI7_0(,%rcx,8)
.LBB7_5:                                #   in Loop: Header=BB7_1 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	movl	%eax, %ebx
	jmp	.LBB7_1
.LBB7_2:                                #   in Loop: Header=BB7_1 Depth=1
	cmpl	$-1, %eax
	je	.LBB7_8
# %bb.3:                                #   in Loop: Header=BB7_1 Depth=1
	cmpl	$98, %eax
	jne	.LBB7_1
# %bb.4:                                #   in Loop: Header=BB7_1 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	movl	%eax, %r13d
	jmp	.LBB7_1
.LBB7_7:                                #   in Loop: Header=BB7_1 Depth=1
	movl	$0, 16(%rsp)                    # 4-byte Folded Spill
	jmp	.LBB7_1
.LBB7_6:                                #   in Loop: Header=BB7_1 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	movl	%eax, %ebp
	jmp	.LBB7_1
.LBB7_97:                               #   in Loop: Header=BB7_1 Depth=1
	movq	optarg(%rip), %rdi
	callq	atoi
	movl	%eax, %r15d
	jmp	.LBB7_1
.LBB7_8:
	movl	%ebp, 20(%rsp)                  # 4-byte Spill
	movl	%ebx, 12(%rsp)                  # 4-byte Spill
	movslq	%r15d, %rbx
	leaq	(,%rbx,4), %r12
	movq	%r12, %rbp
	imulq	%rbx, %rbp
	shrq	$8, %rbp
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, %r14
	leaq	72(%rsp), %rdi
	movq	%rbp, %rsi
	xorl	%edx, %edx
	callq	hipHostAlloc
	movl	%eax, %edi
	movl	$136, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	64(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	xorl	%edx, %edx
	callq	hipHostAlloc
	movl	%eax, %edi
	movl	$138, %esi
	callq	_ZL11HandleError10hipError_tPKci
	testl	%ebx, %ebx
	jle	.LBB7_11
# %bb.9:                                # %.lr.ph
	movq	72(%rsp), %rax
	movl	%r15d, %ecx
	xorl	%edx, %edx
	movl	$1, %esi
.LBB7_10:                               # =>This Inner Loop Header: Depth=1
	movl	%esi, (%r14,%rdx,4)
	movl	%esi, (%rax,%rdx,4)
	incq	%rdx
	cmpq	%rdx, %rcx
	jne	.LBB7_10
.LBB7_11:                               # %._crit_edge
	leaq	80(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	%eax, %edi
	movl	$144, %esi
	callq	_ZL11HandleError10hipError_tPKci
	movq	(%rbx), %rdi
	movq	72(%rsp), %rsi
	movq	%r12, %rdx
	movl	$4, %ecx
	callq	hipMemcpy
	movl	%eax, %edi
	movl	$145, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leal	15(%r15), %ebx
	testl	%r15d, %r15d
	cmovnsl	%r15d, %ebx
	xorl	%edi, %edi
	callq	hipFree
	movl	%eax, %edi
	movl	$168, %esi
	callq	_ZL11HandleError10hipError_tPKci
	cmpl	$3, %r13d
	ja	.LBB7_95
# %bb.12:                               # %._crit_edge
	sarl	$4, %ebx
	movl	%r13d, %eax
	jmpq	*.LJTI7_1(,%rax,8)
.LBB7_13:
	cmpl	$0, 20(%rsp)                    # 4-byte Folded Reload
	je	.LBB7_27
# %bb.14:
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	xorl	%edx, %edx
	callq	hipHostAlloc
	movl	%eax, %edi
	movl	$175, %esi
	callq	_ZL11HandleError10hipError_tPKci
	imull	%r15d, %r15d
	cmpl	$256, %r15d                     # imm = 0x100
	jb	.LBB7_17
# %bb.15:                               # %.lr.ph287
	shrl	$8, %r15d
	movq	24(%rsp), %rax
	xorl	%ecx, %ecx
.LBB7_16:                               # =>This Inner Loop Header: Depth=1
	movl	$5, (%rax,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %r15
	jne	.LBB7_16
.LBB7_17:                               # %._crit_edge288
	leaq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	12(%rsp), %ebp                  # 4-byte Reload
	testl	%ebp, %ebp
	jle	.LBB7_26
# %bb.18:                               # %.lr.ph291
	movabsq	$4294967296, %r15               # imm = 0x100000000
	movl	%ebx, %r12d
	btsq	$32, %r12
	leaq	64(%r15), %r13
	addq	$512, %r15                      # imm = 0x200
	movl	%ebp, %ebx
.LBB7_19:                               # =>This Inner Loop Header: Depth=1
	testb	$1, 16(%rsp)                    # 1-byte Folded Reload
	jne	.LBB7_23
# %bb.20:                               #   in Loop: Header=BB7_19 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_22
# %bb.21:                               #   in Loop: Header=BB7_19 Depth=1
	movq	64(%rsp), %rdi
	callq	_Z31__device_stub__pollute_L2_cachePi
.LBB7_22:                               #   in Loop: Header=BB7_19 Depth=1
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$182, %esi
	callq	_ZL11HandleError10hipError_tPKci
.LBB7_23:                               #   in Loop: Header=BB7_19 Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_25
# %bb.24:                               #   in Loop: Header=BB7_19 Depth=1
	movq	72(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z25__device_stub__readKernelPiS_
.LBB7_25:                               #   in Loop: Header=BB7_19 Depth=1
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$185, %esi
	callq	_ZL11HandleError10hipError_tPKci
	decl	%ebx
	jne	.LBB7_19
.LBB7_26:                               # %._crit_edge292
	leaq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	24(%rsp), %rdi
	callq	hipHostFree
	jmp	.LBB7_37
.LBB7_63:
	leaq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	cmpl	$0, 12(%rsp)                    # 4-byte Folded Reload
	jle	.LBB7_68
# %bb.64:                               # %.lr.ph261
	movl	%ebx, %r12d
	btsq	$32, %r12
	movl	12(%rsp), %ebx                  # 4-byte Reload
.LBB7_65:                               # =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_67
# %bb.66:                               #   in Loop: Header=BB7_65 Depth=1
	xorl	%edi, %edi
	callq	_Z25__device_stub__nullKernelPi
.LBB7_67:                               #   in Loop: Header=BB7_65 Depth=1
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$262, %esi                      # imm = 0x106
	callq	_ZL11HandleError10hipError_tPKci
	decl	%ebx
	jne	.LBB7_65
.LBB7_68:                               # %._crit_edge262
	leaq	48(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	callq	hipGetLastError
	movl	%eax, %edi
	movl	$265, %esi                      # imm = 0x109
	callq	_ZL11HandleError10hipError_tPKci
	movq	8(%rbx), %rax
	subq	40(%rsp), %rax
	movq	(%rbx), %rcx
	cvtsi2sd	%rax, %xmm1
	movsd	.LCPI7_0(%rip), %xmm2           # xmm2 = mem[0],zero
	subq	32(%rsp), %rcx
	cvtsi2sd	%rcx, %xmm0
	divsd	%xmm2, %xmm1
	cvtsi2ssl	12(%rsp), %xmm3         # 4-byte Folded Reload
	addsd	%xmm1, %xmm0
	mulsd	%xmm2, %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm3, %xmm1
	divsd	%xmm1, %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
.LBB7_69:
	cmpl	$0, 20(%rsp)                    # 4-byte Folded Reload
	je	.LBB7_82
# %bb.70:
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, %r12
	imull	%r15d, %r15d
	movl	%r15d, %ebx
	shrl	$8, %ebx
	cmpl	$256, %r15d                     # imm = 0x100
	jb	.LBB7_73
# %bb.71:                               # %.lr.ph265.preheader
	cmpl	$1, %ebx
	movl	%ebx, %eax
	adcl	$0, %eax
	xorl	%ecx, %ecx
.LBB7_72:                               # %.lr.ph265
                                        # =>This Inner Loop Header: Depth=1
	movl	$5, (%r12,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB7_72
.LBB7_73:                               # %._crit_edge266
	xorl	%r13d, %r13d
	leaq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	12(%rsp), %ebp                  # 4-byte Reload
	testl	%ebp, %ebp
	jle	.LBB7_81
# %bb.74:                               # %.preheader257.lr.ph
	cmpl	$1, %ebx
	adcl	$0, %ebx
.LBB7_75:                               # %.preheader257
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_77 Depth 2
	cmpl	$256, %r15d                     # imm = 0x100
	jb	.LBB7_80
# %bb.76:                               # %.lr.ph268.preheader
                                        #   in Loop: Header=BB7_75 Depth=1
	xorl	%eax, %eax
.LBB7_77:                               # %.lr.ph268
                                        #   Parent Loop BB7_75 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	$0, (%r12,%rax,4)
	jne	.LBB7_79
# %bb.78:                               #   in Loop: Header=BB7_77 Depth=2
	movl	$0, (%r14,%rax,4)
.LBB7_79:                               #   in Loop: Header=BB7_77 Depth=2
	incq	%rax
	cmpq	%rax, %rbx
	jne	.LBB7_77
.LBB7_80:                               # %._crit_edge269
                                        #   in Loop: Header=BB7_75 Depth=1
	incl	%r13d
	cmpl	%ebp, %r13d
	jne	.LBB7_75
.LBB7_81:                               # %._crit_edge271
	leaq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	%r12, %rdi
	callq	free
	jmp	.LBB7_94
.LBB7_39:
	cmpl	$0, 20(%rsp)                    # 4-byte Folded Reload
	je	.LBB7_52
# %bb.40:
	movabsq	$4294967296, %r13               # imm = 0x100000000
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	%eax, %edi
	movl	$217, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	1(%r13), %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_42
# %bb.41:
	movq	24(%rsp), %rdi
	movl	%r15d, %esi
	callq	_Z30__device_stub__initCudaMallocdPii
.LBB7_42:
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$219, %esi
	callq	_ZL11HandleError10hipError_tPKci
	leaq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	12(%rsp), %ebp                  # 4-byte Reload
	testl	%ebp, %ebp
	jle	.LBB7_51
# %bb.43:                               # %.lr.ph279
	movl	%ebx, %r15d
	orq	%r13, %r15
	leaq	64(%r13), %r12
	addq	$512, %r13                      # imm = 0x200
	movl	%ebp, %ebx
.LBB7_44:                               # =>This Inner Loop Header: Depth=1
	testb	$1, 16(%rsp)                    # 1-byte Folded Reload
	jne	.LBB7_48
# %bb.45:                               #   in Loop: Header=BB7_44 Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_47
# %bb.46:                               #   in Loop: Header=BB7_44 Depth=1
	movq	64(%rsp), %rdi
	callq	_Z31__device_stub__pollute_L2_cachePi
.LBB7_47:                               #   in Loop: Header=BB7_44 Depth=1
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$224, %esi
	callq	_ZL11HandleError10hipError_tPKci
.LBB7_48:                               #   in Loop: Header=BB7_44 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_50
# %bb.49:                               #   in Loop: Header=BB7_44 Depth=1
	movq	80(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z25__device_stub__readKernelPiS_
.LBB7_50:                               #   in Loop: Header=BB7_44 Depth=1
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$228, %esi
	callq	_ZL11HandleError10hipError_tPKci
	decl	%ebx
	jne	.LBB7_44
.LBB7_51:                               # %._crit_edge280
	leaq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	24(%rsp), %rdi
	callq	hipFree
	jmp	.LBB7_62
.LBB7_82:
	xorl	%ebx, %ebx
	leaq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	imull	%r15d, %r15d
	movl	12(%rsp), %ebp                  # 4-byte Reload
	testl	%ebp, %ebp
	jle	.LBB7_88
# %bb.83:                               # %.preheader.lr.ph
	movl	%r15d, %eax
	shrl	$8, %eax
	cmpl	$1, %eax
	adcl	$0, %eax
.LBB7_84:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_86 Depth 2
	cmpl	$256, %r15d                     # imm = 0x100
	jb	.LBB7_87
# %bb.85:                               # %.lr.ph273.preheader
                                        #   in Loop: Header=BB7_84 Depth=1
	xorl	%ecx, %ecx
.LBB7_86:                               # %.lr.ph273
                                        #   Parent Loop BB7_84 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$5, (%r14,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB7_86
.LBB7_87:                               # %._crit_edge274
                                        #   in Loop: Header=BB7_84 Depth=1
	incl	%ebx
	cmpl	%ebp, %ebx
	jne	.LBB7_84
.LBB7_88:                               # %._crit_edge276
	leaq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	$.Lstr, %edi
	cmpl	$256, %r15d                     # imm = 0x100
	jb	.LBB7_93
# %bb.89:                               # %.lr.ph.preheader.i
	shrl	$8, %r15d
	xorl	%eax, %eax
.LBB7_91:                               # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	cmpl	$5, (%r14,%rax,4)
	jne	.LBB7_92
# %bb.90:                               #   in Loop: Header=BB7_91 Depth=1
	incq	%rax
	cmpq	%rax, %r15
	jne	.LBB7_91
	jmp	.LBB7_93
.LBB7_27:
	leaq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	12(%rsp), %ebp                  # 4-byte Reload
	testl	%ebp, %ebp
	jle	.LBB7_36
# %bb.28:                               # %.lr.ph295
	movabsq	$4294967296, %r15               # imm = 0x100000000
	movl	%ebx, %r12d
	btsq	$32, %r12
	leaq	64(%r15), %r13
	addq	$512, %r15                      # imm = 0x200
	movl	%ebp, %ebx
.LBB7_29:                               # =>This Inner Loop Header: Depth=1
	testb	$1, 16(%rsp)                    # 1-byte Folded Reload
	jne	.LBB7_33
# %bb.30:                               #   in Loop: Header=BB7_29 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_32
# %bb.31:                               #   in Loop: Header=BB7_29 Depth=1
	movq	64(%rsp), %rdi
	callq	_Z31__device_stub__pollute_L2_cachePi
.LBB7_32:                               #   in Loop: Header=BB7_29 Depth=1
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$197, %esi
	callq	_ZL11HandleError10hipError_tPKci
.LBB7_33:                               #   in Loop: Header=BB7_29 Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_35
# %bb.34:                               #   in Loop: Header=BB7_29 Depth=1
	movq	72(%rsp), %rdi
	callq	_Z26__device_stub__writeKernelPi
.LBB7_35:                               #   in Loop: Header=BB7_29 Depth=1
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$201, %esi
	callq	_ZL11HandleError10hipError_tPKci
	decl	%ebx
	jne	.LBB7_29
.LBB7_36:                               # %._crit_edge296
	leaq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
.LBB7_37:
	callq	hipGetLastError
	movl	%eax, %edi
	movl	$206, %esi
	jmp	.LBB7_38
.LBB7_52:
	leaq	32(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	12(%rsp), %ebp                  # 4-byte Reload
	testl	%ebp, %ebp
	jle	.LBB7_61
# %bb.53:                               # %.lr.ph283
	movabsq	$4294967296, %r15               # imm = 0x100000000
	movl	%ebx, %r12d
	btsq	$32, %r12
	leaq	64(%r15), %r13
	addq	$512, %r15                      # imm = 0x200
	movl	%ebp, %ebx
.LBB7_54:                               # =>This Inner Loop Header: Depth=1
	testb	$1, 16(%rsp)                    # 1-byte Folded Reload
	jne	.LBB7_58
# %bb.55:                               #   in Loop: Header=BB7_54 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_57
# %bb.56:                               #   in Loop: Header=BB7_54 Depth=1
	movq	64(%rsp), %rdi
	callq	_Z31__device_stub__pollute_L2_cachePi
.LBB7_57:                               #   in Loop: Header=BB7_54 Depth=1
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$241, %esi
	callq	_ZL11HandleError10hipError_tPKci
.LBB7_58:                               #   in Loop: Header=BB7_54 Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_60
# %bb.59:                               #   in Loop: Header=BB7_54 Depth=1
	movq	80(%rsp), %rdi
	callq	_Z26__device_stub__writeKernelPi
.LBB7_60:                               #   in Loop: Header=BB7_54 Depth=1
	callq	hipDeviceSynchronize
	movl	%eax, %edi
	movl	$245, %esi
	callq	_ZL11HandleError10hipError_tPKci
	decl	%ebx
	jne	.LBB7_54
.LBB7_61:                               # %._crit_edge284
	leaq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
.LBB7_62:
	callq	hipGetLastError
	movl	%eax, %edi
	movl	$251, %esi
.LBB7_38:                               # %.sink.split
	callq	_ZL11HandleError10hipError_tPKci
	jmp	.LBB7_94
.LBB7_92:
	movl	$.Lstr.1, %edi
.LBB7_93:                               # %_Z6verifyPii.exit
	callq	puts@PLT
.LBB7_94:
	movq	48(%rsp), %rax
	movq	56(%rsp), %rcx
	subq	40(%rsp), %rcx
	subq	32(%rsp), %rax
	xorps	%xmm1, %xmm1
	cvtsi2sd	%rcx, %xmm1
	movsd	.LCPI7_0(%rip), %xmm2           # xmm2 = mem[0],zero
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	cmpl	$1, 20(%rsp)                    # 4-byte Folded Reload
	movl	$.L.str.5, %eax
	movl	$.L.str.6, %esi
	cmoveq	%rax, %rsi
	divsd	%xmm2, %xmm1
	xorps	%xmm3, %xmm3
	cvtsi2ss	%ebp, %xmm3
	addsd	%xmm1, %xmm0
	mulsd	%xmm2, %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	%xmm3, %xmm1
	divsd	%xmm1, %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
.LBB7_95:
	movq	%r14, %rdi
	callq	free
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipHostFree
	movq	64(%rsp), %rdi
	callq	hipHostFree
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	main, .Lfunc_end7-main
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI7_0:
	.quad	.LBB7_5
	.quad	.LBB7_1
	.quad	.LBB7_1
	.quad	.LBB7_1
	.quad	.LBB7_97
	.quad	.LBB7_1
	.quad	.LBB7_1
	.quad	.LBB7_7
	.quad	.LBB7_1
	.quad	.LBB7_6
.LJTI7_1:
	.quad	.LBB7_13
	.quad	.LBB7_39
	.quad	.LBB7_63
	.quad	.LBB7_69
                                        # -- End function
	.text
	.type	_ZL11HandleError10hipError_tPKci,@function # -- Begin function _ZL11HandleError10hipError_tPKci
_ZL11HandleError10hipError_tPKci:       # @_ZL11HandleError10hipError_tPKci
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB8_2
# %bb.1:
	retq
.LBB8_2:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%esi, %ebx
	callq	hipGetErrorString
	movl	$.L.str.8, %edi
	movl	$.L.str.3, %edx
	movq	%rax, %rsi
	movl	%ebx, %ecx
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end8:
	.size	_ZL11HandleError10hipError_tPKci, .Lfunc_end8-_ZL11HandleError10hipError_tPKci
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10readKernelPiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11writeKernelPi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10nullKernelPi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15initCudaMallocdPii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17verifyCudaMallocdPii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16pollute_L2_cachePi, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10readKernelPiS_,@object      # @_Z10readKernelPiS_
	.section	.rodata,"a",@progbits
	.globl	_Z10readKernelPiS_
	.p2align	3, 0x0
_Z10readKernelPiS_:
	.quad	_Z25__device_stub__readKernelPiS_
	.size	_Z10readKernelPiS_, 8

	.type	_Z11writeKernelPi,@object       # @_Z11writeKernelPi
	.globl	_Z11writeKernelPi
	.p2align	3, 0x0
_Z11writeKernelPi:
	.quad	_Z26__device_stub__writeKernelPi
	.size	_Z11writeKernelPi, 8

	.type	_Z10nullKernelPi,@object        # @_Z10nullKernelPi
	.globl	_Z10nullKernelPi
	.p2align	3, 0x0
_Z10nullKernelPi:
	.quad	_Z25__device_stub__nullKernelPi
	.size	_Z10nullKernelPi, 8

	.type	_Z15initCudaMallocdPii,@object  # @_Z15initCudaMallocdPii
	.globl	_Z15initCudaMallocdPii
	.p2align	3, 0x0
_Z15initCudaMallocdPii:
	.quad	_Z30__device_stub__initCudaMallocdPii
	.size	_Z15initCudaMallocdPii, 8

	.type	_Z17verifyCudaMallocdPii,@object # @_Z17verifyCudaMallocdPii
	.globl	_Z17verifyCudaMallocdPii
	.p2align	3, 0x0
_Z17verifyCudaMallocdPii:
	.quad	_Z32__device_stub__verifyCudaMallocdPii
	.size	_Z17verifyCudaMallocdPii, 8

	.type	_Z16pollute_L2_cachePi,@object  # @_Z16pollute_L2_cachePi
	.globl	_Z16pollute_L2_cachePi
	.p2align	3, 0x0
_Z16pollute_L2_cachePi:
	.quad	_Z31__device_stub__pollute_L2_cachePi
	.size	_Z16pollute_L2_cachePi, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"m:b:i:r:p"
	.size	.L.str.2, 10

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/mkdashti/bandwidthTest/master/latency-ints/latencyTest.hip"
	.size	.L.str.3, 121

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"[%s] Latency including kernel launch overhead = %f us\n"
	.size	.L.str.4, 55

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"read"
	.size	.L.str.5, 5

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"write"
	.size	.L.str.6, 6

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"null kernel launch overhead = %f us\n"
	.size	.L.str.7, 37

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"%s in %s at line %d\n"
	.size	.L.str.8, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10readKernelPiS_"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11writeKernelPi"
	.size	.L__unnamed_2, 18

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10nullKernelPi"
	.size	.L__unnamed_3, 17

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z15initCudaMallocdPii"
	.size	.L__unnamed_4, 23

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z17verifyCudaMallocdPii"
	.size	.L__unnamed_5, 25

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z16pollute_L2_cachePi"
	.size	.L__unnamed_6, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"verified SUCCESS"
	.size	.Lstr, 17

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"error in verification"
	.size	.Lstr.1, 22

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__readKernelPiS_
	.addrsig_sym _Z26__device_stub__writeKernelPi
	.addrsig_sym _Z25__device_stub__nullKernelPi
	.addrsig_sym _Z30__device_stub__initCudaMallocdPii
	.addrsig_sym _Z32__device_stub__verifyCudaMallocdPii
	.addrsig_sym _Z31__device_stub__pollute_L2_cachePi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10readKernelPiS_
	.addrsig_sym _Z11writeKernelPi
	.addrsig_sym _Z10nullKernelPi
	.addrsig_sym _Z15initCudaMallocdPii
	.addrsig_sym _Z17verifyCudaMallocdPii
	.addrsig_sym _Z16pollute_L2_cachePi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10readKernelPiS_      ; -- Begin function _Z10readKernelPiS_
	.globl	_Z10readKernelPiS_
	.p2align	8
	.type	_Z10readKernelPiS_,@function
_Z10readKernelPiS_:                     ; @_Z10readKernelPiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s0, exec_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_barrier
	buffer_gl0_inv
.LBB0_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10readKernelPiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10readKernelPiS_, .Lfunc_end0-_Z10readKernelPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 116
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11writeKernelPi       ; -- Begin function _Z11writeKernelPi
	.globl	_Z11writeKernelPi
	.p2align	8
	.type	_Z11writeKernelPi,@function
_Z11writeKernelPi:                      ; @_Z11writeKernelPi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x14
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 5
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11writeKernelPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11writeKernelPi, .Lfunc_end1-_Z11writeKernelPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 100
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10nullKernelPi        ; -- Begin function _Z10nullKernelPi
	.globl	_Z10nullKernelPi
	.p2align	8
	.type	_Z10nullKernelPi,@function
_Z10nullKernelPi:                       ; @_Z10nullKernelPi
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10nullKernelPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10nullKernelPi, .Lfunc_end2-_Z10nullKernelPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15initCudaMallocdPii  ; -- Begin function _Z15initCudaMallocdPii
	.globl	_Z15initCudaMallocdPii
	.p2align	8
	.type	_Z15initCudaMallocdPii,@function
_Z15initCudaMallocdPii:                 ; @_Z15initCudaMallocdPii
; %bb.0:
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_4
; %bb.1:                                ; %.preheader
	s_load_b32 s2, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lt_u32 s2, 0x100
	s_cbranch_scc1 .LBB3_4
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x0
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 5
	s_lshr_b32 s2, s2, 8
.LBB3_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s2, s2, -1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s2, 0
	s_cbranch_scc1 .LBB3_3
.LBB3_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15initCudaMallocdPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 12
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 3
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z15initCudaMallocdPii, .Lfunc_end3-_Z15initCudaMallocdPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 108
; NumSgprs: 3
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 3
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2align	2                               ; -- Begin function __ockl_printf_append_string_n
	.type	__ockl_printf_append_string_n,@function
__ockl_printf_append_string_n:          ; @__ockl_printf_append_string_n
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
	v_mbcnt_lo_u32_b32 v2, -1, 0
	s_mov_b32 s9, 0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ne_u64_e32 0, v[6:7]
	s_xor_b32 s8, exec_lo, s0
	s_cbranch_execz .LBB4_87
; %bb.1:
	v_dual_mov_b32 v33, 0 :: v_dual_and_b32 v0, -3, v0
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
	s_mov_b32 s10, 0
.LBB4_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_5 Depth 2
                                        ;     Child Loop BB4_13 Depth 2
                                        ;     Child Loop BB4_21 Depth 2
                                        ;     Child Loop BB4_29 Depth 2
                                        ;     Child Loop BB4_37 Depth 2
                                        ;     Child Loop BB4_45 Depth 2
                                        ;     Child Loop BB4_53 Depth 2
                                        ;     Child Loop BB4_61 Depth 2
                                        ;     Child Loop BB4_69 Depth 2
                                        ;     Child Loop BB4_75 Depth 2
                                        ;     Child Loop BB4_84 Depth 2
	v_cmp_gt_u64_e32 vcc_lo, 56, v[4:5]
                                        ; implicit-def: $sgpr4
	s_mov_b32 s0, exec_lo
	v_dual_cndmask_b32 v1, 0, v5 :: v_dual_cndmask_b32 v0, 56, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 8, v0
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB4_8
; %bb.3:                                ;   in Loop: Header=BB4_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB4_7
; %bb.4:                                ; %.preheader31.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_lshlrev_b64 v[8:9], 3, v[0:1]
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v17, v7
	v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v16, v6
	s_mov_b64 s[4:5], 0
	s_mov_b32 s7, 0
.LBB4_5:                                ; %.preheader31
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v3, v[16:17]
	v_mov_b32_e32 v19, s9
	v_add_co_u32 v16, vcc_lo, v16, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v18, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[18:19], s4, v[18:19]
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e64 s0, s4, v8
	v_or_b32_e32 v15, v19, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_or_b32_e32 v14, v18, v14
	s_or_b32 s7, s0, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB4_5
; %bb.6:                                ; %Flow163
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
.LBB4_7:                                ; %Flow165
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s4, 0
.LBB4_8:                                ; %Flow167
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_saveexec_b32 s0, s1
	v_mov_b32_e32 v9, v7
	v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v8, v6
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_10
; %bb.9:                                ;   in Loop: Header=BB4_2 Depth=1
	s_clause 0x2
	flat_load_u8 v3, v[6:7]
	flat_load_u8 v8, v[6:7] offset:1
	flat_load_u8 v9, v[6:7] offset:2
	s_waitcnt vmcnt(3)
	s_clause 0x2
	flat_load_u8 v14, v[6:7] offset:3
	flat_load_u8 v15, v[6:7] offset:5
	flat_load_u8 v16, v[6:7] offset:4
	v_mov_b32_e32 v17, v33
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v8, 8, v8
	s_clause 0x1
	flat_load_u8 v18, v[6:7] offset:7
	flat_load_d16_hi_u8 v17, v[6:7] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v9
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v14, 24, v14
	v_or_b32_e32 v3, v8, v3
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v8, 8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v3, v3, v9, v14
	s_waitcnt vmcnt(2)
	v_or3_b32 v8, 0, v16, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or3_b32 v14, v3, 0, 0
	v_add_nc_u32_e32 v3, -8, v0
	v_or3_b32 v14, v14, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v18
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v15, v8, v17, v9
	v_add_co_u32 v8, vcc_lo, v6, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
.LBB4_10:                               ; %.loopexit32
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v3
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB4_16
; %bb.11:                               ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v3
	s_cbranch_execz .LBB4_15
; %bb.12:                               ; %.preheader29.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s11, 0
	s_mov_b64 s[4:5], 0
.LBB4_13:                               ; %.preheader29
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v18, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v3
	flat_load_u8 v18, v[18:19]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v19, s9 :: v_dual_and_b32 v18, 0xffff, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], s0, v[18:19]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s11, vcc_lo, s11
	v_or_b32_e32 v17, v19, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v18, v16
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB4_13
; %bb.14:                               ; %Flow158
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB4_15:                               ; %Flow160
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr3
.LBB4_16:                               ; %Flow162
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v20, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_18
; %bb.17:                               ;   in Loop: Header=BB4_2 Depth=1
	s_clause 0x5
	flat_load_u8 v16, v[8:9]
	flat_load_u8 v17, v[8:9] offset:1
	flat_load_u8 v18, v[8:9] offset:2
	flat_load_u8 v19, v[8:9] offset:3
	flat_load_u8 v20, v[8:9] offset:5
	flat_load_u8 v21, v[8:9] offset:4
	v_mov_b32_e32 v22, v33
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v16, 0xffff, v16
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v17, 8, v17
	s_clause 0x1
	flat_load_u8 v23, v[8:9] offset:7
	flat_load_d16_hi_u8 v22, v[8:9] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v18, 16, v18
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v19, 24, v19
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v16, v17, v16
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v17, 8, v20
	v_add_nc_u32_e32 v20, -8, v3
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_or3_b32 v16, v16, v18, v19
	s_waitcnt vmcnt(2)
	v_or3_b32 v17, 0, v21, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v16, v16, 0, 0
	v_or3_b32 v16, v16, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v18, 24, v23
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v17, v17, v22, v18
.LBB4_18:                               ; %.loopexit30
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v20
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB4_24
; %bb.19:                               ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v20
	s_cbranch_execz .LBB4_23
; %bb.20:                               ; %.preheader27.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s11, 0
	s_mov_b64 s[4:5], 0
.LBB4_21:                               ; %.preheader27
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v21, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v22, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v20
	flat_load_u8 v3, v[21:22]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v22, s9 :: v_dual_and_b32 v21, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[21:22], s0, v[21:22]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s11, vcc_lo, s11
	v_or_b32_e32 v19, v22, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v21, v18
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB4_21
; %bb.22:                               ; %Flow153
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB4_23:                               ; %Flow155
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr20
.LBB4_24:                               ; %Flow157
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v3, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_26
; %bb.25:                               ;   in Loop: Header=BB4_2 Depth=1
	s_clause 0x5
	flat_load_u8 v3, v[8:9]
	flat_load_u8 v18, v[8:9] offset:1
	flat_load_u8 v19, v[8:9] offset:2
	flat_load_u8 v21, v[8:9] offset:3
	flat_load_u8 v22, v[8:9] offset:5
	flat_load_u8 v23, v[8:9] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v24, v33 :: v_dual_and_b32 v3, 0xffff, v3
	s_clause 0x1
	flat_load_u8 v25, v[8:9] offset:7
	flat_load_d16_hi_u8 v24, v[8:9] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v18, 8, v18
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v19, 16, v19
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v21, 24, v21
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v3, v18, v3
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v18, 8, v22
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v3, v3, v19, v21
	s_waitcnt vmcnt(2)
	v_or3_b32 v18, 0, v23, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_or3_b32 v21, v3, 0, 0
	v_add_nc_u32_e32 v3, -8, v20
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v19, 24, v25
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_or3_b32 v19, v18, v24, v19
	v_or3_b32 v18, v21, 0, 0
.LBB4_26:                               ; %.loopexit28
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v3
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB4_32
; %bb.27:                               ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v3
	s_cbranch_execz .LBB4_31
; %bb.28:                               ; %.preheader25.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s11, 0
	s_mov_b64 s[4:5], 0
.LBB4_29:                               ; %.preheader25
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v22, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v3
	flat_load_u8 v22, v[22:23]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v23, s9 :: v_dual_and_b32 v22, 0xffff, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], s0, v[22:23]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s11, vcc_lo, s11
	v_or_b32_e32 v21, v23, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v22, v20
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB4_29
; %bb.30:                               ; %Flow148
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB4_31:                               ; %Flow150
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr3
.LBB4_32:                               ; %Flow152
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v24, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_34
; %bb.33:                               ;   in Loop: Header=BB4_2 Depth=1
	s_clause 0x5
	flat_load_u8 v20, v[8:9]
	flat_load_u8 v21, v[8:9] offset:1
	flat_load_u8 v22, v[8:9] offset:2
	flat_load_u8 v23, v[8:9] offset:3
	flat_load_u8 v24, v[8:9] offset:5
	flat_load_u8 v25, v[8:9] offset:4
	v_mov_b32_e32 v26, v33
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v20, 0xffff, v20
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v21, 8, v21
	s_clause 0x1
	flat_load_u8 v27, v[8:9] offset:7
	flat_load_d16_hi_u8 v26, v[8:9] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v22, 16, v22
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v23, 24, v23
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v20, v21, v20
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v21, 8, v24
	v_add_nc_u32_e32 v24, -8, v3
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_or3_b32 v20, v20, v22, v23
	s_waitcnt vmcnt(2)
	v_or3_b32 v21, 0, v25, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v20, v20, 0, 0
	v_or3_b32 v20, v20, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v22, 24, v27
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v21, v21, v26, v22
.LBB4_34:                               ; %.loopexit26
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v24
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB4_40
; %bb.35:                               ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB4_39
; %bb.36:                               ; %.preheader23.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s11, 0
	s_mov_b64 s[4:5], 0
.LBB4_37:                               ; %.preheader23
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v25, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v26, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v24
	flat_load_u8 v3, v[25:26]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v26, s9 :: v_dual_and_b32 v25, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[25:26], s0, v[25:26]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s11, vcc_lo, s11
	v_or_b32_e32 v23, v26, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v25, v22
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB4_37
; %bb.38:                               ; %Flow143
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB4_39:                               ; %Flow145
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr24
.LBB4_40:                               ; %Flow147
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v3, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_42
; %bb.41:                               ;   in Loop: Header=BB4_2 Depth=1
	s_clause 0x5
	flat_load_u8 v3, v[8:9]
	flat_load_u8 v22, v[8:9] offset:1
	flat_load_u8 v23, v[8:9] offset:2
	flat_load_u8 v25, v[8:9] offset:3
	flat_load_u8 v26, v[8:9] offset:5
	flat_load_u8 v27, v[8:9] offset:4
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_dual_mov_b32 v28, v33 :: v_dual_and_b32 v3, 0xffff, v3
	s_clause 0x1
	flat_load_u8 v29, v[8:9] offset:7
	flat_load_d16_hi_u8 v28, v[8:9] offset:6
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v22, 8, v22
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v23, 16, v23
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v25, 24, v25
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v3, v22, v3
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v22, 8, v26
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or3_b32 v3, v3, v23, v25
	s_waitcnt vmcnt(2)
	v_or3_b32 v22, 0, v27, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_or3_b32 v25, v3, 0, 0
	v_add_nc_u32_e32 v3, -8, v24
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v23, 24, v29
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_or3_b32 v23, v22, v28, v23
	v_or3_b32 v22, v25, 0, 0
.LBB4_42:                               ; %.loopexit24
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v3
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB4_48
; %bb.43:                               ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_ne_u32_e32 0, v3
	s_cbranch_execz .LBB4_47
; %bb.44:                               ; %.preheader21.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s11, 0
	s_mov_b64 s[4:5], 0
.LBB4_45:                               ; %.preheader21
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v26, vcc_lo, v8, s4
	v_add_co_ci_u32_e32 v27, vcc_lo, s5, v9, vcc_lo
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	v_cmp_eq_u32_e32 vcc_lo, s4, v3
	flat_load_u8 v26, v[26:27]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v27, s9 :: v_dual_and_b32 v26, 0xffff, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[26:27], s0, v[26:27]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s11, vcc_lo, s11
	v_or_b32_e32 v25, v27, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v24, v26, v24
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB4_45
; %bb.46:                               ; %Flow138
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB4_47:                               ; %Flow140
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mov_b32 s1, 0
                                        ; implicit-def: $vgpr3
.LBB4_48:                               ; %Flow142
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_saveexec_b32 s0, s6
	v_mov_b32_e32 v28, s1
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB4_50
; %bb.49:                               ;   in Loop: Header=BB4_2 Depth=1
	s_clause 0x5
	flat_load_u8 v24, v[8:9]
	flat_load_u8 v25, v[8:9] offset:1
	flat_load_u8 v26, v[8:9] offset:2
	flat_load_u8 v27, v[8:9] offset:3
	flat_load_u8 v28, v[8:9] offset:5
	flat_load_u8 v29, v[8:9] offset:4
	v_mov_b32_e32 v30, v33
	s_waitcnt vmcnt(5) lgkmcnt(0)
	v_and_b32_e32 v24, 0xffff, v24
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v25, 8, v25
	s_clause 0x1
	flat_load_u8 v31, v[8:9] offset:7
	flat_load_d16_hi_u8 v30, v[8:9] offset:6
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v26, 16, v26
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v27, 24, v27
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_or_b32_e32 v24, v25, v24
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v25, 8, v28
	v_add_nc_u32_e32 v28, -8, v3
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_or3_b32 v24, v24, v26, v27
	s_waitcnt vmcnt(2)
	v_or3_b32 v25, 0, v29, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v24, v24, 0, 0
	v_or3_b32 v24, v24, 0, 0
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_lshlrev_b32_e32 v26, 24, v31
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v25, v25, v30, v26
.LBB4_50:                               ; %.loopexit22
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 8, v28
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB4_56
; %bb.51:                               ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_ne_u32_e32 0, v28
	s_cbranch_execz .LBB4_55
; %bb.52:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_mov_b64 s[0:1], 0
	s_mov_b32 s6, 0
.LBB4_53:                               ; %.preheader
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	flat_load_u8 v3, v[8:9]
	v_mov_b32_e32 v30, s9
	v_add_nc_u32_e32 v28, -1, v28
	v_add_co_u32 v8, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v28
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_and_b32_e32 v29, 0xffff, v3
	v_lshlrev_b64 v[29:30], s0, v[29:30]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v27, v30, v27
	v_or_b32_e32 v26, v29, v26
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB4_53
; %bb.54:                               ; %Flow133
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB4_55:                               ; %Flow135
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr8_vgpr9
.LBB4_56:                               ; %Flow137
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB4_58
; %bb.57:                               ;   in Loop: Header=BB4_2 Depth=1
	s_clause 0x5
	flat_load_u8 v3, v[8:9]
	flat_load_u8 v26, v[8:9] offset:1
	flat_load_u8 v27, v[8:9] offset:2
	flat_load_u8 v28, v[8:9] offset:3
	flat_load_u8 v29, v[8:9] offset:5
	flat_load_u8 v30, v[8:9] offset:4
	v_mov_b32_e32 v31, v33
	s_clause 0x1
	flat_load_u8 v32, v[8:9] offset:7
	flat_load_d16_hi_u8 v31, v[8:9] offset:6
	s_waitcnt vmcnt(7) lgkmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_waitcnt vmcnt(6)
	v_lshlrev_b32_e32 v8, 8, v26
	s_waitcnt vmcnt(5)
	v_lshlrev_b32_e32 v9, 16, v27
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v26, 8, v29
	v_or_b32_e32 v3, v8, v3
	v_lshlrev_b32_e32 v8, 24, v28
	s_delay_alu instid0(VALU_DEP_1)
	v_or3_b32 v3, v3, v9, v8
	s_waitcnt vmcnt(2)
	v_or3_b32 v8, 0, v30, v26
	s_waitcnt vmcnt(1)
	v_lshlrev_b32_e32 v9, 24, v32
	v_or3_b32 v3, v3, 0, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v27, v8, v31, v9
	v_or3_b32 v26, v3, 0, 0
.LBB4_58:                               ; %.loopexit
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v32, v2
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v32
	v_cmp_eq_u32_e64 s0, s0, v32
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_64
; %bb.59:                               ;   in Loop: Header=BB4_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[30:31], v33, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[8:9], v33, s[2:3] offset:40
	global_load_b64 v[28:29], v33, s[2:3]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v9, v31
	v_and_b32_e32 v8, v8, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v9, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v28, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v29, v3, vcc_lo
	global_load_b64 v[28:29], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v33, v[28:31], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[30:31]
	s_cbranch_execz .LBB4_63
; %bb.60:                               ; %.preheader3.i.i19.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_mov_b32 s5, 0
.LBB4_61:                               ; %.preheader3.i.i19
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[28:29], v33, s[2:3] offset:40
	global_load_b64 v[34:35], v33, s[2:3]
	v_dual_mov_b32 v31, v9 :: v_dual_mov_b32 v30, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v28, v30
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[8:9], null, v3, 24, v[34:35]
	v_and_b32_e32 v34, v29, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v9
	v_mad_u64_u32 v[28:29], null, v34, 24, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v9, v28
	global_load_b64 v[28:29], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v33, v[28:31], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[30:31]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB4_61
; %bb.62:                               ; %Flow130
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB4_63:                               ; %Flow132
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_64:                               ; %.loopexit4.i.i14
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[34:35], v33, s[2:3] offset:40
	global_load_b128 v[28:31], v33, s[2:3]
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v34
	v_readfirstlane_b32 s7, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s11, s6, 24
	s_mul_i32 s12, s6, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB4_66
; %bb.65:                               ;   in Loop: Header=BB4_2 Depth=1
	s_add_i32 s15, s11, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v34, vcc_lo, v28, s12
	v_add_co_ci_u32_e32 v35, vcc_lo, s15, v29, vcc_lo
	v_dual_mov_b32 v8, s13 :: v_dual_mov_b32 v9, v33
	global_store_b128 v[34:35], v[8:11], off offset:8
.LBB4_66:                               ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_cmp_lt_u64_e32 vcc_lo, 56, v[4:5]
	v_or_b32_e32 v3, 2, v12
	v_lshl_add_u32 v8, v0, 2, 28
	s_lshl_b64 s[6:7], s[6:7], 12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v12, vcc_lo
	v_and_b32_e32 v12, 0x1e0, v8
	v_lshlrev_b64 v[8:9], 6, v[32:33]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v30, vcc_lo, v30, s6
	v_add_co_ci_u32_e32 v31, vcc_lo, s7, v31, vcc_lo
	v_and_or_b32 v12, 0xffffff1f, v3, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v30, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, v31, v9, vcc_lo
	s_clause 0x3
	global_store_b128 v[8:9], v[12:15], off
	global_store_b128 v[8:9], v[16:19], off offset:16
	global_store_b128 v[8:9], v[20:23], off offset:32
	global_store_b128 v[8:9], v[24:27], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_74
; %bb.67:                               ;   in Loop: Header=BB4_2 Depth=1
	s_clause 0x1
	global_load_b64 v[20:21], v33, s[2:3] offset:32 glc
	global_load_b64 v[12:13], v33, s[2:3] offset:40
	v_dual_mov_b32 v18, s4 :: v_dual_mov_b32 v19, s5
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v12
	v_readfirstlane_b32 s15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[4:5]
	s_mul_i32 s7, s15, 24
	s_mul_hi_u32 s13, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s13, s13, s7
	v_add_co_u32 v16, vcc_lo, v28, s14
	v_add_co_ci_u32_e32 v17, vcc_lo, s13, v29, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[16:17], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v33, v[18:21], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[20:21]
	s_cbranch_execz .LBB4_70
; %bb.68:                               ; %.preheader1.i.i17.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_mov_b32 s13, 0
.LBB4_69:                               ; %.preheader1.i.i17
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5
	s_sleep 1
	global_store_b64 v[16:17], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v33, v[12:15], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB4_69
.LBB4_70:                               ; %Flow128
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	global_load_b64 v[12:13], v33, s[2:3] offset:16
	s_mov_b32 s13, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v3, s13, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB4_72
; %bb.71:                               ;   in Loop: Header=BB4_2 Depth=1
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v32, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[12:13], v[32:33], off offset:8
.LBB4_72:                               ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[14:15], v[12:13], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	s_cbranch_vccnz .LBB4_74
; %bb.73:                               ;   in Loop: Header=BB4_2 Depth=1
	global_load_b32 v32, v[12:13], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v32
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[14:15], v[32:33], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_74:                               ; %Flow129
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s11, s11, s1
	v_add_co_u32 v3, vcc_lo, v28, s12
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
.LBB4_75:                               ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_77
; %bb.76:                               ;   in Loop: Header=BB4_75 Depth=2
	global_load_b32 v3, v[12:13], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB4_77:                               ;   in Loop: Header=BB4_75 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v3
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB4_79
; %bb.78:                               ;   in Loop: Header=BB4_75 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB4_80
.LBB4_79:                               ;   in Loop: Header=BB4_75 Depth=2
	s_mov_b32 s1, -1
.LBB4_80:                               ; %Flow123
                                        ;   in Loop: Header=BB4_75 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_75
; %bb.81:                               ;   in Loop: Header=BB4_2 Depth=1
	global_load_b128 v[12:15], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_85
; %bb.82:                               ;   in Loop: Header=BB4_2 Depth=1
	s_clause 0x2
	global_load_b64 v[8:9], v33, s[2:3] offset:40
	global_load_b64 v[18:19], v33, s[2:3] offset:24 glc
	global_load_b64 v[16:17], v33, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v3, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_dual_cndmask_b32 v15, v15, v20 :: v_dual_cndmask_b32 v14, v14, v3
	v_and_b32_e32 v3, v15, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v14, v8
	v_mul_hi_u32 v9, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, vcc_lo, v16, v8
	v_mov_b32_e32 v16, v18
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, v17, v3, vcc_lo
	v_mov_b32_e32 v17, v19
	global_store_b64 v[8:9], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v33, v[14:17], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[18:19]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_85
; %bb.83:                               ; %.preheader.i.i16.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_mov_b32 s0, 0
.LBB4_84:                               ; %.preheader.i.i16
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[8:9], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v33, v[14:17], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[16:17]
	v_dual_mov_b32 v16, v18 :: v_dual_mov_b32 v17, v19
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_84
.LBB4_85:                               ; %__ockl_hostcall_preview.exit20
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_sub_co_u32 v4, vcc_lo, v4, v0
	v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v1, vcc_lo
	v_add_co_u32 v6, s0, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s0, v7, v1, s0
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB4_2
; %bb.86:                               ; %Flow168
	s_or_b32 exec_lo, exec_lo, s10
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr1
.LBB4_87:                               ; %Flow185
	s_and_not1_saveexec_b32 s1, s8
	s_cbranch_execz .LBB4_116
; %bb.88:
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v2
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB4_94
; %bb.89:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB4_93
; %bb.90:                               ; %.preheader3.i.i.preheader
	s_mov_b32 s6, 0
.LBB4_91:                               ; %.preheader3.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB4_91
; %bb.92:                               ; %Flow181
	s_or_b32 exec_lo, exec_lo, s6
.LBB4_93:                               ; %Flow183
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB4_94:                               ; %.loopexit4.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s11, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s8, s7, 24
	s_mul_hi_u32 s9, s6, 24
	s_mul_i32 s10, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB4_96
; %bb.95:
	s_add_i32 s13, s9, s8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v5, vcc_lo
	v_dual_mov_b32 v8, s11 :: v_dual_mov_b32 v9, v3
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB4_96:
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v9, s15
	v_dual_mov_b32 v7, s13 :: v_dual_mov_b32 v8, s14
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_104
; %bb.97:
	v_mov_b32_e32 v8, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	v_dual_mov_b32 v9, s4 :: v_dual_mov_b32 v10, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v6, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB4_100
; %bb.98:                               ; %.preheader1.i.i.preheader
	s_mov_b32 s11, 0
.LBB4_99:                               ; %.preheader1.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB4_99
.LBB4_100:                              ; %Flow179
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s11, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s11, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB4_102
; %bb.101:
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB4_102:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB4_104
; %bb.103:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB4_104:                              ; %Flow180
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s9, s9, s8
	v_add_co_u32 v0, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB4_105:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_107
; %bb.106:                              ;   in Loop: Header=BB4_105 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB4_107:                              ;   in Loop: Header=BB4_105 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB4_109
; %bb.108:                              ;   in Loop: Header=BB4_105 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB4_110
.LBB4_109:                              ;   in Loop: Header=BB4_105 Depth=1
	s_mov_b32 s6, -1
.LBB4_110:                              ; %Flow174
                                        ;   in Loop: Header=BB4_105 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB4_105
; %bb.111:
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB4_115
; %bb.112:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB4_115
; %bb.113:                              ; %.preheader.i.i.preheader
	s_mov_b32 s0, 0
.LBB4_114:                              ; %.preheader.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_114
.LBB4_115:                              ; %Flow172
	s_or_b32 exec_lo, exec_lo, s6
.LBB4_116:                              ; %Flow186
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end4:
	.size	__ockl_printf_append_string_n, .Lfunc_end4-__ockl_printf_append_string_n
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 5644
; NumSgprs: 34
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z17verifyCudaMallocdPii ; -- Begin function _Z17verifyCudaMallocdPii
	.globl	_Z17verifyCudaMallocdPii
	.p2align	8
	.type	_Z17verifyCudaMallocdPii,@function
_Z17verifyCudaMallocdPii:               ; @_Z17verifyCudaMallocdPii
; %bb.0:
	s_mov_b64 s[16:17], s[0:1]
	s_mov_b32 s32, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB5_64
; %bb.1:                                ; %.preheader19
	s_load_b32 s2, s[16:17], 0x8
	s_mov_b32 s18, -1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lt_u32 s2, 0x100
	s_cbranch_scc1 .LBB5_35
; %bb.2:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[16:17], 0x0
	s_lshr_b32 s2, s2, 8
.LBB5_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_load_b32 s3, s[0:1], 0x0
	s_mov_b32 s4, -1
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s3, 5
	s_mov_b32 s3, -1
	s_cbranch_scc0 .LBB5_5
; %bb.4:                                ;   in Loop: Header=BB5_3 Depth=1
	s_add_i32 s2, s2, -1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s2, 0
	s_mov_b32 s3, 0
	s_cselect_b32 s4, -1, 0
.LBB5_5:                                ; %Flow77
                                        ;   in Loop: Header=BB5_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB5_3
; %bb.6:                                ; %loop.exit.guard
	s_and_b32 vcc_lo, exec_lo, s3
	s_mov_b32 s18, -1
	s_cbranch_vccz .LBB5_35
; %bb.7:
	s_load_b64 s[2:3], s[16:17], 0x60
	v_mbcnt_lo_u32_b32 v4, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v4
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	v_cmp_eq_u32_e64 s0, s0, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB5_13
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[5:6], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB5_12
; %bb.9:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB5_10:                               ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[10:11], v0, s[2:3]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB5_10
; %bb.11:                               ; %Flow74
	s_or_b32 exec_lo, exec_lo, s5
.LBB5_12:                               ; %Flow76
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB5_13:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[2:3] offset:40
	global_load_b128 v[0:3], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB5_15
; %bb.14:
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, v5
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v11, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB5_15:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
	v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB5_23
; %bb.16:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s5, v3
	v_and_b32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB5_19
; %bb.17:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s10, 0
.LBB5_18:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB5_18
.LBB5_19:                               ; %Flow72
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v5, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v4, s10, 0
	global_load_b64 v[2:3], v5, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB5_21
; %bb.20:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB5_21:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB5_23
; %bb.22:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB5_23:                               ; %Flow73
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB5_24:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB5_26
; %bb.25:                               ;   in Loop: Header=BB5_24 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB5_26:                               ;   in Loop: Header=BB5_24 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB5_28
; %bb.27:                               ;   in Loop: Header=BB5_24 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB5_29
.LBB5_28:                               ;   in Loop: Header=BB5_24 Depth=1
	s_mov_b32 s1, -1
.LBB5_29:                               ; %Flow67
                                        ;   in Loop: Header=BB5_24 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB5_24
; %bb.30:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB5_34
; %bb.31:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB5_34
; %bb.32:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB5_33:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB5_33
.LBB5_34:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str@rel32@lo+4
	s_addc_u32 s1, s1, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	s_cmp_lg_u64 s[0:1], 0
	s_mov_b32 s18, 0
	s_cselect_b32 s4, 23, 0
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s4
	s_add_u32 s8, s16, 16
	s_addc_u32 s9, s17, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
.LBB5_35:                               ; %Flow92
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB5_64
; %bb.36:                               ; %.critedge
	s_load_b64 s[2:3], s[16:17], 0x60
	v_mbcnt_lo_u32_b32 v4, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v4
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	v_cmp_eq_u32_e64 s0, s0, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB5_42
; %bb.37:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[5:6], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB5_41
; %bb.38:                               ; %.preheader3.i.i.i16.preheader
	s_mov_b32 s5, 0
.LBB5_39:                               ; %.preheader3.i.i.i16
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[10:11], v0, s[2:3]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB5_39
; %bb.40:                               ; %Flow89
	s_or_b32 exec_lo, exec_lo, s5
.LBB5_41:                               ; %Flow91
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB5_42:                               ; %.loopexit4.i.i.i11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[2:3] offset:40
	global_load_b128 v[0:3], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB5_44
; %bb.43:
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, v5
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v11, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB5_44:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
	v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB5_52
; %bb.45:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s5, v3
	v_and_b32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB5_48
; %bb.46:                               ; %.preheader1.i.i.i14.preheader
	s_mov_b32 s10, 0
.LBB5_47:                               ; %.preheader1.i.i.i14
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB5_47
.LBB5_48:                               ; %Flow87
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v5, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v4, s10, 0
	global_load_b64 v[2:3], v5, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB5_50
; %bb.49:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB5_50:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB5_52
; %bb.51:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB5_52:                               ; %Flow88
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB5_53:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB5_55
; %bb.54:                               ;   in Loop: Header=BB5_53 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB5_55:                               ;   in Loop: Header=BB5_53 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB5_57
; %bb.56:                               ;   in Loop: Header=BB5_53 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB5_58
.LBB5_57:                               ;   in Loop: Header=BB5_53 Depth=1
	s_mov_b32 s1, -1
.LBB5_58:                               ; %Flow82
                                        ;   in Loop: Header=BB5_53 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB5_53
; %bb.59:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB5_63
; %bb.60:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB5_63
; %bb.61:                               ; %.preheader.i.i.i13.preheader
	s_mov_b32 s0, 0
.LBB5_62:                               ; %.preheader.i.i.i13
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB5_62
.LBB5_63:                               ; %__ockl_printf_begin.exit17
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, .str.1@rel32@lo+4
	s_addc_u32 s1, s1, .str.1@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
	s_cmp_lg_u64 s[0:1], 0
	v_mov_b32_e32 v5, 0
	s_cselect_b32 s4, 18, 0
	s_add_u32 s8, s16, 16
	v_mov_b32_e32 v4, s4
	s_addc_u32 s9, s17, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[2:3]
.LBB5_64:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17verifyCudaMallocdPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z17verifyCudaMallocdPii, .Lfunc_end5-_Z17verifyCudaMallocdPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3120
; NumSgprs: 35
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16pollute_L2_cachePi  ; -- Begin function _Z16pollute_L2_cachePi
	.globl	_Z16pollute_L2_cachePi
	.p2align	8
	.type	_Z16pollute_L2_cachePi,@function
_Z16pollute_L2_cachePi:                 ; @_Z16pollute_L2_cachePi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x14
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 5
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16pollute_L2_cachePi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z16pollute_L2_cachePi, .Lfunc_end6-_Z16pollute_L2_cachePi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 100
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"error in verification\n"
	.size	.str, 23

	.type	.str.1,@object                  ; @.str.1
.str.1:
	.asciz	"verified SUCCESS\n"
	.size	.str.1, 18

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10readKernelPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10readKernelPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11writeKernelPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11writeKernelPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10nullKernelPi
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z10nullKernelPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 12
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15initCudaMallocdPii
    .private_segment_fixed_size: 0
    .sgpr_count:     3
    .sgpr_spill_count: 0
    .symbol:         _Z15initCudaMallocdPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         96
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17verifyCudaMallocdPii
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         _Z17verifyCudaMallocdPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     36
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16pollute_L2_cachePi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16pollute_L2_cachePi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
