#include <iostream>
#include <math.h>

// TODO: find proper alignment (__align__(x))
struct node {
    int value;
    int children[8];
    int next;
};

// function to add the elements of a static array and a more dynamic tree structure
__global__
void add(int n, float* a, node* nodes, float* b) {
    printf("hello world from the device!\n"); 
    int index = threadIdx.x;
    int stride = blockDim.x;
    int childID = 0;
    //int childID = nodes[0].children[0];
    for (int i = index; i < n; i += stride)
        b[i] += a[i] + nodes[childID].value;
}

int main(void) {
    // 1 + 8 + 8*8 + 8*8*8
    int N = 585;
    //int N = 1<<20;

    // create buffers
    float *a, *b;

    // initialize a and b arrays on the host
    for (int i = 0; i < N; i++) {
        a[i] = 1.0f;
        b[i] = 2.0f;
    }

    // create node buffer
    node nodes[N];
    // initialize "tree" structure
    // calculate the required depth for our structure first
    int depth = 1;
    int x = N;
    while (x >= 8) {
        x -= x % 8;
        x /= 8;
        depth++;
    }

    int rootnodelength = 1;
    for (int d = 0; d < depth; d++) {
        rootnodelength *= 8;
    }
    // pad rootnodelength with unused fields
    rootnodelength += N % rootnodelength;
    rootnodelength += 1;

    for (int i = 0; i < N; i++) {
        // replace depth with current depth
        nodes[i].value = (100 * depth) + i;
        // logarithm of x base b = log(x)/log(b)
        // TODO: create some sort of magical function to get the current depth for i
        // using a log base 8 function and more sik math skills
        // then populate nodes and their indeces in accordance with the current depth

        // for testing purposes **ONLY**
        for (int j = 0; j < 8; j++) {
            // set all children to node number 1 (yeah I know pretty lame)
            nodes[i].children[j] = 1;
        }
        // also set next temporarily
        nodes[i].next = 2;
    }

    printf("aaaaaaaaaaaaaaaa\n");
    // create space in memory for a copy of nodes to be used by the device
    node *nodes_d;
    cudaMallocManaged(&a, N * sizeof(float));
    cudaMallocManaged(&b, N * sizeof(float));
    cudaMallocManaged((void**) &nodes_d, sizeof(node) * sizeof(nodes));

    // copy nodes buffer to nodes_d (memory space we allocated for the device)
    cudaMemcpy(nodes_d, nodes, sizeof(node) * sizeof(node), cudaMemcpyHostToDevice);
    // suffering
    printf("AAAAAAAAAAAA\n");
    add<<<1, 256>>>(N, a, nodes, b);

    // wait for gpu (blocks thread till end is signaled)
    cudaDeviceSynchronize();
    // even more suffering
    printf("aaaaaabbbbbbbbbbbbbbbb");

    /*
    float max_error = 0.0f;
    for (int i = 0; i < N; i++)
        max_error = fmax(max_error, fabs(b[i]));
    std::cout << "max error: " << max_error << std::endl;
    */

    float median = 0.0f;
    for (int i = 0; i < N; i++) {
        median = fmax(median, fabs(b[i]));
    }
    std::cout << "median : " << median << "\n";

    // free memory
    cudaFree(a);
    cudaFree(b);
    cudaFree(nodes);

    return 0;
}

	.file	"tmpxft_002f6cbf_00000000-6_add.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z3addiPfP4nodeS_iPfP4nodeS_
	.type	_Z31__device_stub__Z3addiPfP4nodeS_iPfP4nodeS_, @function
_Z31__device_stub__Z3addiPfP4nodeS_iPfP4nodeS_:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3addiPfP4nodeS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z31__device_stub__Z3addiPfP4nodeS_iPfP4nodeS_, .-_Z31__device_stub__Z3addiPfP4nodeS_iPfP4nodeS_
	.globl	_Z3addiPfP4nodeS_
	.type	_Z3addiPfP4nodeS_, @function
_Z3addiPfP4nodeS_:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z3addiPfP4nodeS_iPfP4nodeS_
	.cfi_endproc
.LFE3661:
	.size	_Z3addiPfP4nodeS_, .-_Z3addiPfP4nodeS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"aaaaaaaaaaaaaaaa\n"
.LC4:
	.string	"AAAAAAAAAAAA\n"
.LC5:
	.string	"aaaaaabbbbbbbbbbbbbbbb"
.LC7:
	.string	"median : "
.LC8:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset 13, -24
	.cfi_offset 12, -32
	.cfi_offset 3, -40
	movq	-88(%rbp), %rcx
	movq	-80(%rbp), %rdx
	movq	%fs:40, %rax
	movq	%rax, -40(%rbp)
	xorl	%eax, %eax
	movss	.LC1(%rip), %xmm1
	movss	.LC2(%rip), %xmm0
.L9:
	movss	%xmm1, (%rcx,%rax)
	movss	%xmm0, (%rdx,%rax)
	addq	$4, %rax
	cmpq	$2340, %rax
	jne	.L9
	leaq	-20480(%rsp), %rax
.L10:
	cmpq	%rax, %rsp
	je	.L11
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L10
.L11:
	subq	$2928, %rsp
	orq	$0, 2920(%rsp)
	movl	$400, %edx
	movq	%rsp, %rbx
	movq	%rbx, %rax
.L13:
	movl	%edx, (%rax)
	incl	%edx
	addq	$40, %rax
	movl	$1, -36(%rax)
	movl	$1, -32(%rax)
	movl	$1, -28(%rax)
	movl	$1, -24(%rax)
	movl	$1, -20(%rax)
	movl	$1, -16(%rax)
	movl	$1, -12(%rax)
	movl	$1, -8(%rax)
	movl	$2, -4(%rax)
	cmpl	$985, %edx
	jne	.L13
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	-88(%rbp), %rdi
	movl	$1, %edx
	movl	$2340, %esi
	call	cudaMallocManaged@PLT
	leaq	-80(%rbp), %rdi
	movl	$1, %edx
	movl	$2340, %esi
	call	cudaMallocManaged@PLT
	leaq	-72(%rbp), %rdi
	movl	$1, %edx
	movl	$936000, %esi
	call	cudaMallocManaged@PLT
	movq	-72(%rbp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1600, %edx
	call	cudaMemcpy@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, -52(%rbp)
	movl	$1, -44(%rbp)
	movq	%rdi, -64(%rbp)
	movl	$1, -56(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	-80(%rbp), %rcx
	movq	-88(%rbp), %rsi
	movq	%rbx, %rdx
	movl	$585, %edi
	call	_Z31__device_stub__Z3addiPfP4nodeS_iPfP4nodeS_
.L14:
	call	cudaDeviceSynchronize@PLT
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r12d, %r12d
	leaq	.LC5(%rip), %rsi
	call	__printf_chk@PLT
	movq	-80(%rbp), %r13
	xorps	%xmm1, %xmm1
.L15:
	movss	0(%r13,%r12,4), %xmm0
	andps	.LC6(%rip), %xmm0
	incq	%r12
	call	fmaxf@PLT
	movaps	%xmm0, %xmm1
	cmpq	$585, %r12
	jne	.L15
	leaq	.LC7(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	movss	%xmm0, -100(%rbp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	-100(%rbp), %xmm1
	movq	%rax, %rdi
	cvtss2sd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	-88(%rbp), %rdi
	call	cudaFree@PLT
	movq	-80(%rbp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	cudaFree@PLT
	movq	-40(%rbp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	leaq	-24(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z3addiPfP4nodeS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3addiPfP4nodeS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.align 4
.LC2:
	.long	1073741824
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC6:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>

// TODO: find proper alignment (__align__(x))
struct node {
    int value;
    int children[8];
    int next;
};

// function to add the elements of a static array and a more dynamic tree structure
__global__
void add(int n, float* a, node* nodes, float* b) {
    printf("hello world from the device!\n"); 
    int index = threadIdx.x;
    int stride = blockDim.x;
    int childID = 0;
    //int childID = nodes[0].children[0];
    for (int i = index; i < n; i += stride)
        b[i] += a[i] + nodes[childID].value;
}

int main(void) {
    // 1 + 8 + 8*8 + 8*8*8
    int N = 585;
    //int N = 1<<20;

    // create buffers
    float *a, *b;

    // initialize a and b arrays on the host
    for (int i = 0; i < N; i++) {
        a[i] = 1.0f;
        b[i] = 2.0f;
    }

    // create node buffer
    node nodes[N];
    // initialize "tree" structure
    // calculate the required depth for our structure first
    int depth = 1;
    int x = N;
    while (x >= 8) {
        x -= x % 8;
        x /= 8;
        depth++;
    }

    int rootnodelength = 1;
    for (int d = 0; d < depth; d++) {
        rootnodelength *= 8;
    }
    // pad rootnodelength with unused fields
    rootnodelength += N % rootnodelength;
    rootnodelength += 1;

    for (int i = 0; i < N; i++) {
        // replace depth with current depth
        nodes[i].value = (100 * depth) + i;
        // logarithm of x base b = log(x)/log(b)
        // TODO: create some sort of magical function to get the current depth for i
        // using a log base 8 function and more sik math skills
        // then populate nodes and their indeces in accordance with the current depth

        // for testing purposes **ONLY**
        for (int j = 0; j < 8; j++) {
            // set all children to node number 1 (yeah I know pretty lame)
            nodes[i].children[j] = 1;
        }
        // also set next temporarily
        nodes[i].next = 2;
    }

    printf("aaaaaaaaaaaaaaaa\n");
    // create space in memory for a copy of nodes to be used by the device
    node *nodes_d;
    hipMallocManaged(&a, N * sizeof(float));
    hipMallocManaged(&b, N * sizeof(float));
    hipMallocManaged((void**) &nodes_d, sizeof(node) * sizeof(nodes));

    // copy nodes buffer to nodes_d (memory space we allocated for the device)
    hipMemcpy(nodes_d, nodes, sizeof(node) * sizeof(node), hipMemcpyHostToDevice);
    // suffering
    printf("AAAAAAAAAAAA\n");
    add<<<1, 256>>>(N, a, nodes, b);

    // wait for gpu (blocks thread till end is signaled)
    hipDeviceSynchronize();
    // even more suffering
    printf("aaaaaabbbbbbbbbbbbbbbb");

    /*
    float max_error = 0.0f;
    for (int i = 0; i < N; i++)
        max_error = fmax(max_error, fabs(b[i]));
    std::cout << "max error: " << max_error << std::endl;
    */

    float median = 0.0f;
    for (int i = 0; i < N; i++) {
        median = fmax(median, fabs(b[i]));
    }
    std::cout << "median : " << median << "\n";

    // free memory
    hipFree(a);
    hipFree(b);
    hipFree(nodes);

    return 0;
}

	.text
	.file	"add.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z18__device_stub__addiPfP4nodeS_ # -- Begin function _Z18__device_stub__addiPfP4nodeS_
	.type	_Z18__device_stub__addiPfP4nodeS_,@function
_Z18__device_stub__addiPfP4nodeS_:      # @_Z18__device_stub__addiPfP4nodeS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3addiPfP4nodeS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__addiPfP4nodeS_, .Lfunc_end0-_Z18__device_stub__addiPfP4nodeS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3addiPfP4nodeS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3addiPfP4nodeS_,@object       # @_Z3addiPfP4nodeS_
	.section	.rodata,"a",@progbits
	.globl	_Z3addiPfP4nodeS_
	.p2align	3, 0x0
_Z3addiPfP4nodeS_:
	.quad	_Z18__device_stub__addiPfP4nodeS_
	.size	_Z3addiPfP4nodeS_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z3addiPfP4nodeS_"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__addiPfP4nodeS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3addiPfP4nodeS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3addiPfP4nodeS_       ; -- Begin function _Z3addiPfP4nodeS_
	.globl	_Z3addiPfP4nodeS_
	.p2align	8
	.type	_Z3addiPfP4nodeS_,@function
_Z3addiPfP4nodeS_:                      ; @_Z3addiPfP4nodeS_
; %bb.0:
	s_load_b64 s[4:5], s[0:1], 0x70
	v_mbcnt_lo_u32_b32 v3, -1, 0
	s_add_u32 s8, s0, 32
	s_addc_u32 s9, s1, 0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v8, v3
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v8
	v_cmp_eq_u32_e64 s2, s2, v8
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_6
; %bb.1:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[11:12], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v4, s[4:5] offset:40
	global_load_b64 v[5:6], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v11
	v_and_b32_e32 v2, v2, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v7, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[9:10], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[1:2], v[11:12]
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s7, 0
.LBB0_3:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	v_dual_mov_b32 v12, v2 :: v_dual_mov_b32 v11, v1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v5, v11
	v_and_b32_e32 v7, v6, v12
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v5, 24, v[9:10]
	v_mad_u64_u32 v[5:6], null, v7, 24, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v5
	global_load_b64 v[9:10], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[1:2], v4, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[11:12]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_3
; %bb.4:                                ; %Flow287
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_5:                                ; %Flow289
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_6:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v9, 0
	v_readfirstlane_b32 s6, v1
	v_readfirstlane_b32 s7, v2
	s_mov_b32 s14, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[10:11], v9, s[4:5] offset:40
	global_load_b128 v[4:7], v9, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v10
	v_readfirstlane_b32 s11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s2
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, v9
	s_add_i32 s14, s12, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v4, s13
	v_add_co_ci_u32_e32 v2, vcc_lo, s14, v5, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[1:2], v[10:13], off offset:8
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[1:2], 6, v[8:9]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v6, v1
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_add_co_ci_u32_e32 v2, vcc_lo, v7, v2, vcc_lo
	v_dual_mov_b32 v8, 33 :: v_dual_mov_b32 v11, v9
	v_mov_b32_e32 v10, v9
	v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v15, s19
	v_dual_mov_b32 v13, s17 :: v_dual_mov_b32 v14, s18
	s_clause 0x3
	global_store_b128 v[1:2], v[8:11], off
	global_store_b128 v[1:2], v[12:15], off offset:16
	global_store_b128 v[1:2], v[12:15], off offset:32
	global_store_b128 v[1:2], v[12:15], off offset:48
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_16
; %bb.9:
	v_mov_b32_e32 v12, 0
	s_mov_b32 s11, exec_lo
	s_clause 0x1
	global_load_b64 v[15:16], v12, s[4:5] offset:32 glc
	global_load_b64 v[6:7], v12, s[4:5] offset:40
	v_dual_mov_b32 v13, s6 :: v_dual_mov_b32 v14, s7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v7, s7, v7
	v_and_b32_e32 v6, s6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v7, 24
	v_mul_hi_u32 v8, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v8, v7
	v_add_co_u32 v10, vcc_lo, v4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, v5, v7, vcc_lo
	global_store_b64 v[10:11], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v12, v[13:16], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[8:9], v[15:16]
	s_cbranch_execz .LBB0_12
; %bb.10:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s14, 0
.LBB0_11:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
	s_sleep 1
	global_store_b64 v[10:11], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v12, v[6:9], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_11
.LBB0_12:                               ; %Flow285
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v9, 0
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v8, s14, 0
	global_load_b64 v[6:7], v9, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v8
	s_cbranch_execz .LBB0_14
; %bb.13:
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[6:7], v[8:9], off offset:8
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[6:7], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB0_16
; %bb.15:
	global_load_b32 v6, v[6:7], off offset:24
	v_mov_b32_e32 v7, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v6
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[6:7], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:                               ; %Flow286
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s3
	v_add_co_u32 v4, vcc_lo, v4, s13
	v_add_co_ci_u32_e32 v5, vcc_lo, s12, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_17:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	global_load_b32 v6, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB0_19:                               ;   in Loop: Header=BB0_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v6
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_17 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_22
.LBB0_21:                               ;   in Loop: Header=BB0_17 Depth=1
	s_mov_b32 s3, -1
.LBB0_22:                               ; %Flow280
                                        ;   in Loop: Header=BB0_17 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_17
; %bb.23:
	global_load_b64 v[1:2], v[1:2], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_27
; %bb.24:
	v_mov_b32_e32 v10, 0
	s_clause 0x2
	global_load_b64 v[6:7], v10, s[4:5] offset:40
	global_load_b64 v[11:12], v10, s[4:5] offset:24 glc
	global_load_b64 v[8:9], v10, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v14 :: v_dual_cndmask_b32 v4, v4, v13
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, v4, v6
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v6, 24
	v_mul_lo_u32 v6, v6, 24
	v_add_nc_u32_e32 v7, v13, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v12
	global_store_b64 v[8:9], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v10, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_27
; %bb.25:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s2, 0
.LBB0_26:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[6:7]
	v_dual_mov_b32 v6, v11 :: v_dual_mov_b32 v7, v12
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_26
.LBB0_27:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_mov_b32 s2, -1
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_113
; %bb.28:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v9, v2 :: v_dual_and_b32 v8, -3, v1
	v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v6, 2
	v_mov_b32_e32 v7, 1
	s_mov_b64 s[10:11], 30
.LBB0_29:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_32 Depth 2
                                        ;     Child Loop BB0_39 Depth 2
                                        ;     Child Loop BB0_47 Depth 2
                                        ;     Child Loop BB0_55 Depth 2
                                        ;     Child Loop BB0_63 Depth 2
                                        ;     Child Loop BB0_71 Depth 2
                                        ;     Child Loop BB0_79 Depth 2
                                        ;     Child Loop BB0_87 Depth 2
                                        ;     Child Loop BB0_95 Depth 2
                                        ;     Child Loop BB0_101 Depth 2
                                        ;     Child Loop BB0_110 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s2, s[10:11], 56
                                        ; implicit-def: $sgpr19
	s_and_b32 s2, s2, exec_lo
	s_cselect_b32 s12, s10, 56
	s_cselect_b32 s13, s11, 0
	s_cmp_gt_u32 s12, 7
	s_mov_b32 s2, -1
	s_cbranch_scc1 .LBB0_34
; %bb.30:                               ;   in Loop: Header=BB0_29 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc1 .LBB0_33
; %bb.31:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_lshl_b64 s[2:3], s[12:13], 3
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[6:7]
.LBB0_32:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v29, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[28:29]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s2, s14
	v_or_b32_e32 v10, v4, v10
	v_or_b32_e32 v11, v5, v11
	s_cbranch_scc1 .LBB0_32
.LBB0_33:                               ; %Flow255
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s2, 0
	s_mov_b32 s19, 0
.LBB0_34:                               ; %Flow257
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_mov_b64 s[2:3], s[6:7]
	s_cbranch_vccnz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[10:11], v29, s[6:7]
	s_add_i32 s19, s12, -8
	s_add_u32 s2, s6, 8
	s_addc_u32 s3, s7, 0
.LBB0_36:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_41
; %bb.37:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_40
; %bb.38:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_39:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v29, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[28:29]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v12, v4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v5, v13
	s_cbranch_scc1 .LBB0_39
.LBB0_40:                               ; %Flow250
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_42
.LBB0_41:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr18
.LBB0_42:                               ; %Flow252
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_44
; %bb.43:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[12:13], v29, s[2:3]
	s_add_i32 s18, s19, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_44:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_49
; %bb.45:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_48
; %bb.46:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_47:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v29, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[28:29]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v14, v4, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v5, v15
	s_cbranch_scc1 .LBB0_47
.LBB0_48:                               ; %Flow245
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_50
.LBB0_49:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr19
.LBB0_50:                               ; %Flow247
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_52
; %bb.51:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[14:15], v29, s[2:3]
	s_add_i32 s19, s18, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_52:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_57
; %bb.53:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_56
; %bb.54:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_55:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v29, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[28:29]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v16, v4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v5, v17
	s_cbranch_scc1 .LBB0_55
.LBB0_56:                               ; %Flow240
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_58
.LBB0_57:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr18
.LBB0_58:                               ; %Flow242
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_60
; %bb.59:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[16:17], v29, s[2:3]
	s_add_i32 s18, s19, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_60:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_65
; %bb.61:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_64
; %bb.62:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_63:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v29, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[28:29]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v18, v4, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v5, v19
	s_cbranch_scc1 .LBB0_63
.LBB0_64:                               ; %Flow235
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_66
.LBB0_65:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr19
.LBB0_66:                               ; %Flow237
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_68
; %bb.67:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[18:19], v29, s[2:3]
	s_add_i32 s19, s18, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_68:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_73
; %bb.69:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_72
; %bb.70:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_71:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s2, s16
	s_addc_u32 s21, s3, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v4, v29, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[28:29]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v20, v4, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v5, v21
	s_cbranch_scc1 .LBB0_71
.LBB0_72:                               ; %Flow230
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_74
.LBB0_73:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr18
.LBB0_74:                               ; %Flow232
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_76
; %bb.75:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[20:21], v29, s[2:3]
	s_add_i32 s18, s19, -8
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
.LBB0_76:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_81
; %bb.77:                               ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_80
; %bb.78:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[2:3]
.LBB0_79:                               ; %.preheader.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v29, s[16:17]
	s_add_i32 s18, s18, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v28, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s14, v[28:29]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s18, 0
	v_or_b32_e32 v22, v4, v22
	v_or_b32_e32 v23, v5, v23
	s_cbranch_scc1 .LBB0_79
.LBB0_80:                               ; %Flow225
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, 0
	s_branch .LBB0_82
.LBB0_81:                               ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s14, -1
.LBB0_82:                               ; %Flow227
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_84
; %bb.83:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[22:23], v29, s[2:3]
.LBB0_84:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	v_mov_b32_e32 v28, v3
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v28
	v_cmp_eq_u32_e64 s2, s2, v28
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_90
; %bb.85:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b64 v[26:27], v29, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v29, s[4:5] offset:40
	global_load_b64 v[24:25], v29, s[4:5]
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v27
	v_and_b32_e32 v4, v4, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v30, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v30, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v24, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v25, v5, vcc_lo
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v29, v[24:27], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[26:27]
	s_cbranch_execz .LBB0_89
; %bb.86:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s15, 0
.LBB0_87:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[24:25], v29, s[4:5] offset:40
	global_load_b64 v[30:31], v29, s[4:5]
	v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v24, v24, v26
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v24, 24, v[30:31]
	v_and_b32_e32 v30, v25, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[24:25], null, v30, 24, v[5:6]
	v_mov_b32_e32 v5, v24
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v29, v[24:27], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[26:27]
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_87
; %bb.88:                               ; %Flow220
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
.LBB0_89:                               ; %Flow222
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_90:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	global_load_b64 v[30:31], v29, s[4:5] offset:40
	global_load_b128 v[24:27], v29, s[4:5]
	v_readfirstlane_b32 s14, v4
	v_readfirstlane_b32 s15, v5
	s_mov_b32 s20, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v30
	v_readfirstlane_b32 s17, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[14:15], s[16:17]
	s_mul_i32 s3, s17, 24
	s_mul_hi_u32 s18, s16, 24
	s_mul_i32 s19, s16, 24
	s_and_saveexec_b32 s21, s2
	s_cbranch_execz .LBB0_92
; %bb.91:                               ;   in Loop: Header=BB0_29 Depth=1
	v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v5, v29
	s_add_i32 s20, s18, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v30, vcc_lo, v24, s19
	v_add_co_ci_u32_e32 v31, vcc_lo, s20, v25, vcc_lo
	global_store_b128 v[30:31], v[4:7], off offset:8
.LBB0_92:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	v_cmp_gt_u64_e64 vcc_lo, s[10:11], 56
	v_or_b32_e32 v4, 2, v8
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s20, s12, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s20, s20, 28
	v_cndmask_b32_e32 v8, v4, v8, vcc_lo
	v_lshlrev_b64 v[4:5], 6, v[28:29]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v26, vcc_lo, v26, s16
	v_add_co_ci_u32_e32 v27, vcc_lo, s17, v27, vcc_lo
	s_and_b32 s20, s20, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v26, v4
	v_and_or_b32 v8, 0xffffff1f, v8, s20
	v_add_co_ci_u32_e32 v5, vcc_lo, v27, v5, vcc_lo
	s_clause 0x3
	global_store_b128 v[4:5], v[8:11], off
	global_store_b128 v[4:5], v[12:15], off offset:16
	global_store_b128 v[4:5], v[16:19], off offset:32
	global_store_b128 v[4:5], v[20:23], off offset:48
	s_and_saveexec_b32 s16, s2
	s_cbranch_execz .LBB0_100
; %bb.93:                               ;   in Loop: Header=BB0_29 Depth=1
	s_clause 0x1
	global_load_b64 v[16:17], v29, s[4:5] offset:32 glc
	global_load_b64 v[8:9], v29, s[4:5] offset:40
	v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v8
	v_readfirstlane_b32 s21, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[20:21], s[14:15]
	s_mul_i32 s17, s21, 24
	s_mul_hi_u32 s21, s20, 24
	s_mul_i32 s20, s20, 24
	s_add_i32 s21, s21, s17
	v_add_co_u32 v12, vcc_lo, v24, s20
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v25, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[12:13], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v29, v[14:17], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[10:11], v[16:17]
	s_cbranch_execz .LBB0_96
; %bb.94:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s20, 0
.LBB0_95:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, s15
	s_sleep 1
	global_store_b64 v[12:13], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v29, v[8:11], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_95
.LBB0_96:                               ; %Flow218
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[8:9], v29, s[4:5] offset:16
	s_mov_b32 s20, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v10, s20, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v10
	s_cbranch_execz .LBB0_98
; %bb.97:                               ;   in Loop: Header=BB0_29 Depth=1
	s_bcnt1_i32_b32 s20, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v28, s20
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[28:29], off offset:8
.LBB0_98:                               ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB0_100
; %bb.99:                               ;   in Loop: Header=BB0_29 Depth=1
	global_load_b32 v28, v[8:9], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v28
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[28:29], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_100:                              ; %Flow219
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s18, s18, s3
	v_add_co_u32 v8, vcc_lo, v24, s19
	v_add_co_ci_u32_e32 v9, vcc_lo, s18, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v8, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB0_101:                              ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v10, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_103
; %bb.102:                              ;   in Loop: Header=BB0_101 Depth=2
	global_load_b32 v10, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v10, 1, v10
.LBB0_103:                              ;   in Loop: Header=BB0_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v10
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_105
; %bb.104:                              ;   in Loop: Header=BB0_101 Depth=2
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_106
.LBB0_105:                              ;   in Loop: Header=BB0_101 Depth=2
	s_mov_b32 s3, -1
.LBB0_106:                              ; %Flow213
                                        ;   in Loop: Header=BB0_101 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_101
; %bb.107:                              ;   in Loop: Header=BB0_29 Depth=1
	global_load_b128 v[8:11], v[4:5], off
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_111
; %bb.108:                              ;   in Loop: Header=BB0_29 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v29, s[4:5] offset:40
	global_load_b64 v[14:15], v29, s[4:5] offset:24 glc
	global_load_b64 v[12:13], v29, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v16, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v16, s14
	v_add_co_ci_u32_e32 v11, vcc_lo, s15, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	v_dual_cndmask_b32 v11, v11, v17 :: v_dual_cndmask_b32 v10, v10, v16
	v_and_b32_e32 v5, v11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v10, v4
	v_mul_hi_u32 v16, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v12, v4
	v_mov_b32_e32 v12, v14
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v16, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v13, v5, vcc_lo
	v_mov_b32_e32 v13, v15
	global_store_b64 v[4:5], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v29, v[10:13], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[14:15]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_111
; %bb.109:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_mov_b32 s2, 0
.LBB0_110:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v29, v[10:13], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[12:13]
	v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_110
.LBB0_111:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_sub_u32 s10, s10, s12
	s_subb_u32 s11, s11, s13
	s_add_u32 s6, s6, s12
	s_addc_u32 s7, s7, s13
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_29
; %bb.112:                              ; %Flow258
	s_mov_b32 s2, 0
.LBB0_113:                              ; %Flow274
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_142
; %bb.114:
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v3
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_120
; %bb.115:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[7:8], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v5, 24
	v_mul_lo_u32 v6, v6, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v11, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[9:10], v[7:8]
	s_cbranch_execz .LBB0_119
; %bb.116:                              ; %.preheader3.i.i.i18.preheader
	s_mov_b32 s7, 0
.LBB0_117:                              ; %.preheader3.i.i.i18
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[11:12], v4, s[4:5]
	v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v8, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v5, v7
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[11:12]
	v_mov_b32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v6, 24, v[5:6]
	global_load_b64 v[5:6], v[9:10], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[7:8]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_117
; %bb.118:                              ; %Flow271
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_119:                              ; %Flow273
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_120:                              ; %.loopexit4.i.i.i13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v4, 0
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_mov_b32 s14, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v4, s[4:5] offset:40
	global_load_b128 v[5:8], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v11
	v_readfirstlane_b32 s11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[6:7], s[10:11]
	s_mul_i32 s3, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s2
	s_cbranch_execz .LBB0_122
; %bb.121:
	v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, v4
	s_add_i32 s14, s12, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v5, s13
	v_add_co_ci_u32_e32 v14, vcc_lo, s14, v6, vcc_lo
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_122:
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[9:10], 6, v[3:4]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v8, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v3, v9
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_and_or_b32 v1, 0xffffff1d, v1, 34
	v_add_co_ci_u32_e32 v12, vcc_lo, v7, v10, vcc_lo
	v_mov_b32_e32 v3, v4
	v_dual_mov_b32 v7, s16 :: v_dual_mov_b32 v10, s19
	v_dual_mov_b32 v8, s17 :: v_dual_mov_b32 v9, s18
	s_clause 0x3
	global_store_b128 v[11:12], v[1:4], off
	global_store_b128 v[11:12], v[7:10], off offset:16
	global_store_b128 v[11:12], v[7:10], off offset:32
	global_store_b128 v[11:12], v[7:10], off offset:48
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB0_130
; %bb.123:
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, s6
	v_mov_b32_e32 v11, s7
	s_clause 0x1
	global_load_b64 v[12:13], v9, s[4:5] offset:32 glc
	global_load_b64 v[1:2], v9, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v1
	v_readfirstlane_b32 s15, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[6:7]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v7, vcc_lo, v5, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v6, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[7:8], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v9, v[10:13], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB0_126
; %bb.124:                              ; %.preheader1.i.i.i16.preheader
	s_mov_b32 s14, 0
.LBB0_125:                              ; %.preheader1.i.i.i16
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v1, s6 :: v_dual_mov_b32 v2, s7
	s_sleep 1
	global_store_b64 v[7:8], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[1:2], v9, v[1:4], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[3:4]
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_125
.LBB0_126:                              ; %Flow269
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v4, 0
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v3, s14, 0
	global_load_b64 v[1:2], v4, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB0_128
; %bb.127:
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[1:2], v[3:4], off offset:8
.LBB0_128:
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[3:4], v[1:2], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	s_cbranch_vccnz .LBB0_130
; %bb.129:
	global_load_b32 v1, v[1:2], off offset:24
	v_mov_b32_e32 v2, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[3:4], v[1:2], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_130:                              ; %Flow270
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s3
	v_add_co_u32 v1, vcc_lo, v5, s13
	v_add_co_ci_u32_e32 v2, vcc_lo, s12, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_131:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_133
; %bb.132:                              ;   in Loop: Header=BB0_131 Depth=1
	global_load_b32 v3, v[1:2], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v3, 1, v3
.LBB0_133:                              ;   in Loop: Header=BB0_131 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v3
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB0_135
; %bb.134:                              ;   in Loop: Header=BB0_131 Depth=1
	s_mov_b32 s3, 0
	s_sleep 1
	s_branch .LBB0_136
.LBB0_135:                              ;   in Loop: Header=BB0_131 Depth=1
	s_mov_b32 s3, -1
.LBB0_136:                              ; %Flow264
                                        ;   in Loop: Header=BB0_131 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_131
; %bb.137:
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_141
; %bb.138:
	v_mov_b32_e32 v7, 0
	s_clause 0x2
	global_load_b64 v[3:4], v7, s[4:5] offset:40
	global_load_b64 v[8:9], v7, s[4:5] offset:24 glc
	global_load_b64 v[5:6], v7, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v10, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v10, s6
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[1:2]
	v_dual_cndmask_b32 v2, v2, v11 :: v_dual_cndmask_b32 v1, v1, v10
	v_and_b32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v1, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v5, v3
	v_mov_b32_e32 v3, v8
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v4, vcc_lo
	v_mov_b32_e32 v4, v9
	global_store_b64 v[5:6], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[3:4], v7, v[1:4], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[3:4], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_141
; %bb.139:                              ; %.preheader.i.i.i15.preheader
	s_mov_b32 s2, 0
.LBB0_140:                              ; %.preheader.i.i.i15
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[5:6], v[3:4], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v7, v[1:4], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[3:4]
	v_dual_mov_b32 v3, v8 :: v_dual_mov_b32 v4, v9
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_140
.LBB0_141:                              ; %Flow262
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_142:                              ; %__ockl_printf_append_string_n.exit
	s_load_b32 s10, s[0:1], 0x0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s10, v0
	s_cbranch_execz .LBB0_145
; %bb.143:                              ; %.lr.ph
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v1, 0
	s_load_b32 s0, s[8:9], 0xc
	v_lshlrev_b32_e32 v3, 2, v0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v2, v1, s[6:7]
	s_mov_b32 s6, 0
	s_and_b32 s1, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s7, s1, 2
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v2, v2
.LBB0_144:                              ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v4, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v1, vcc_lo
	v_add_nc_u32_e32 v0, s1, v0
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[6:7], off
	v_add_co_u32 v3, vcc_lo, v3, s7
	v_cmp_le_i32_e64 s0, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 s6, s0, s6
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v5, v4
	global_store_b32 v[6:7], v4, off
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_144
.LBB0_145:                              ; %Flow209
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3addiPfP4nodeS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3addiPfP4nodeS_, .Lfunc_end0-_Z3addiPfP4nodeS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5508
; NumSgprs: 24
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"hello world from the device!\n"
	.size	.str, 30

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         112
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3addiPfP4nodeS_
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z3addiPfP4nodeS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
