#include <stdio.h>
#include <cuda.h>

#define N 100

__global__ void matrixAddKernel(int * a, int * b, int * c, int  n){
  int col = threadIdx.x + blockDim.x * blockIdx.x; 
  int row = threadIdx.y + blockDim.y * blockIdx.y;
  int index = row * N + col;
  if(col < N && row < N)
  {
    c[index] = a[index]+b[index];
  }
  //int index = threadIdx.y*n + threadIdx.x;
  //c[index] = a[index] + b[index]; 

}

void matrixAdd(int *a, int *b, int *c, int n)
{
  int index;
  for(int col=0; col<n; col++)
  {
    for(int row=0; row<n; row++)
    {
      index = row * n + col;
      c[index] = a[index] + b[index];
    }
  }
}
int main(){

  dim3 grid(1, 1, 1);
  dim3 block(N, N, 1);
  int *a_h;
  int *b_h;
  int *c_h;
  int *d_h;
  int *a_d;
  int *b_d;
  int *c_d;
  
  int size;
  cudaEvent_t start;
  cudaEvent_t stop;
  float elapsedTime; 
  printf("Number of threads: %i (%ix%i)\n", block.x*block.y, block.x, block.y);
  printf("Number of blocks: %i (%ix%i)\n", grid.x*grid.y, grid.x, grid.y); 

  size = N * N * sizeof(int);
  a_h = (int*) malloc(size);
  b_h = (int*) malloc(size);
  c_h = (int*) malloc(size);
  d_h = (int*) malloc(size);
  for(int i=0; i<N; i++)
  {
    for(int j=0; j<N; j++)
    {
      a_h[i * N + j] = i;
      b_h[i * N + j] = i;
    }
  }

  cudaMalloc((void**)&a_d, size);
  cudaMalloc((void**)&b_d, size);
  cudaMalloc((void**)&c_d, size);

  cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
  cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
  cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);

  cudaEventCreate(&start);
  cudaEventCreate(&stop);
  cudaEventRecord(start, 0);

  matrixAddKernel<<<grid, block>>>(a_d, b_d, c_d, N);

  cudaEventRecord(stop, 0);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&elapsedTime, start, stop);
  printf("Time to calculate results on GPU: %f ms.\n",elapsedTime);
  cudaMemcpy(c_h, c_d, size ,cudaMemcpyDeviceToHost);
  cudaEventRecord(start, 0);

  matrixAdd(a_h, b_h, d_h, N);
  cudaEventRecord(stop, 0);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&elapsedTime, start, stop );
  printf("Time to calculate results on CPU: %f ms.\n",elapsedTime); 
  
  for(int i=0; i<N*N; i++)
  {
    if (c_h[i] != d_h[i]) printf("Error: CPU and GPU results do not match\n");
    break;
  }




  return 0;
}

	.file	"tmpxft_0026fbd3_00000000-6_matAdd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9matrixAddPiS_S_i
	.type	_Z9matrixAddPiS_S_i, @function
_Z9matrixAddPiS_S_i:
.LFB2027:
	.cfi_startproc
	endbr64
	movslq	%ecx, %r8
	movq	%rdi, %r9
	xorl	%edi, %edi
	salq	$2, %r8
.L3:
	cmpl	%edi, %ecx
	jle	.L8
	leaq	0(,%rdi,4), %rax
	xorl	%r10d, %r10d
.L4:
	movl	(%rsi,%rax), %r11d
	incl	%r10d
	addl	(%r9,%rax), %r11d
	movl	%r11d, (%rdx,%rax)
	addq	%r8, %rax
	cmpl	%r10d, %ecx
	jne	.L4
	incq	%rdi
	jmp	.L3
.L8:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z9matrixAddPiS_S_i, .-_Z9matrixAddPiS_S_i
	.globl	_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
	.type	_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15matrixAddKernelPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L9:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
	.globl	_Z15matrixAddKernelPiS_S_i
	.type	_Z15matrixAddKernelPiS_S_i, @function
_Z15matrixAddKernelPiS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z15matrixAddKernelPiS_S_i, .-_Z15matrixAddKernelPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Number of threads: %i (%ix%i)\n"
.LC1:
	.string	"Number of blocks: %i (%ix%i)\n"
.LC2:
	.string	"Time to calculate results on GPU: %f ms.\n"
.LC3:
	.string	"Time to calculate results on CPU: %f ms.\n"
.LC4:
	.string	"Error: CPU and GPU results do not match\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$100, %r8d
	movl	$100, %ecx
	movl	$10000, %edx
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movl	$1, 56(%rsp)
	movl	$1, 68(%rsp)
	call	__printf_chk@PLT
	movl	$1, %r8d
	xorl	%eax, %eax
	movl	$1, %ecx
	movl	$1, %edx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$40000, %edi
	call	malloc@PLT
	movl	$40000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$40000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$40000, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	%rax, %r13
	xorl	%eax, %eax
.L15:
	imulq	$400, %rax, %rdx
	movl	%eax, %esi
	movl	$100, %ecx
.L16:
	movl	%esi, 0(%rbp,%rdx)
	movl	%esi, (%r12,%rdx)
	addq	$4, %rdx
	decl	%ecx
	jne	.L16
	incq	%rax
	cmpq	$100, %rax
	jne	.L15
	leaq	8(%rsp), %rdi
	movl	$40000, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$40000, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$40000, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$40000, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$40000, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$40000, %edx
	call	cudaMemcpy@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	68(%rsp), %ecx
	movl	56(%rsp), %esi
	xorl	%r9d, %r9d
	movabsq	$429496729700, %rdx
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$100, %ecx
	movq	8(%rsp), %rdi
	call	_Z40__device_stub__Z15matrixAddKernelPiS_S_iPiS_S_i
.L18:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	leaq	4(%rsp), %r14
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	%r14, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$40000, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$100, %ecx
	movq	%r13, %rdx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	call	_Z9matrixAddPiS_S_i
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	%r14, %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	4(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	0(%r13), %eax
	cmpl	%eax, (%rbx)
	je	.L19
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L19:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z15matrixAddKernelPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15matrixAddKernelPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>

#define N 100

__global__ void matrixAddKernel(int * a, int * b, int * c, int  n){
  int col = threadIdx.x + blockDim.x * blockIdx.x; 
  int row = threadIdx.y + blockDim.y * blockIdx.y;
  int index = row * N + col;
  if(col < N && row < N)
  {
    c[index] = a[index]+b[index];
  }
  //int index = threadIdx.y*n + threadIdx.x;
  //c[index] = a[index] + b[index]; 

}

void matrixAdd(int *a, int *b, int *c, int n)
{
  int index;
  for(int col=0; col<n; col++)
  {
    for(int row=0; row<n; row++)
    {
      index = row * n + col;
      c[index] = a[index] + b[index];
    }
  }
}
int main(){

  dim3 grid(1, 1, 1);
  dim3 block(N, N, 1);
  int *a_h;
  int *b_h;
  int *c_h;
  int *d_h;
  int *a_d;
  int *b_d;
  int *c_d;
  
  int size;
  hipEvent_t start;
  hipEvent_t stop;
  float elapsedTime; 
  printf("Number of threads: %i (%ix%i)\n", block.x*block.y, block.x, block.y);
  printf("Number of blocks: %i (%ix%i)\n", grid.x*grid.y, grid.x, grid.y); 

  size = N * N * sizeof(int);
  a_h = (int*) malloc(size);
  b_h = (int*) malloc(size);
  c_h = (int*) malloc(size);
  d_h = (int*) malloc(size);
  for(int i=0; i<N; i++)
  {
    for(int j=0; j<N; j++)
    {
      a_h[i * N + j] = i;
      b_h[i * N + j] = i;
    }
  }

  hipMalloc((void**)&a_d, size);
  hipMalloc((void**)&b_d, size);
  hipMalloc((void**)&c_d, size);

  hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
  hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
  hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);

  hipEventCreate(&start);
  hipEventCreate(&stop);
  hipEventRecord(start, 0);

  matrixAddKernel<<<grid, block>>>(a_d, b_d, c_d, N);

  hipEventRecord(stop, 0);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&elapsedTime, start, stop);
  printf("Time to calculate results on GPU: %f ms.\n",elapsedTime);
  hipMemcpy(c_h, c_d, size ,hipMemcpyDeviceToHost);
  hipEventRecord(start, 0);

  matrixAdd(a_h, b_h, d_h, N);
  hipEventRecord(stop, 0);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&elapsedTime, start, stop );
  printf("Time to calculate results on CPU: %f ms.\n",elapsedTime); 
  
  for(int i=0; i<N*N; i++)
  {
    if (c_h[i] != d_h[i]) printf("Error: CPU and GPU results do not match\n");
    break;
  }




  return 0;
}

	.text
	.file	"matAdd.hip"
	.globl	_Z30__device_stub__matrixAddKernelPiS_S_i # -- Begin function _Z30__device_stub__matrixAddKernelPiS_S_i
	.type	_Z30__device_stub__matrixAddKernelPiS_S_i,@function
_Z30__device_stub__matrixAddKernelPiS_S_i: # @_Z30__device_stub__matrixAddKernelPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15matrixAddKernelPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__matrixAddKernelPiS_S_i, .Lfunc_end0-_Z30__device_stub__matrixAddKernelPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z9matrixAddPiS_S_i             # -- Begin function _Z9matrixAddPiS_S_i
	.type	_Z9matrixAddPiS_S_i,@function
_Z9matrixAddPiS_S_i:                    # @_Z9matrixAddPiS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB1_5
# %bb.1:                                # %.preheader.lr.ph
	movl	%ecx, %eax
	leaq	(,%rax,4), %rcx
	xorl	%r8d, %r8d
.LBB1_2:                                # %.lr.ph.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_3 Depth 2
	movq	%rax, %r9
	xorl	%r10d, %r10d
.LBB1_3:                                # %.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rsi,%r10), %r11d
	addl	(%rdi,%r10), %r11d
	movl	%r11d, (%rdx,%r10)
	addq	%rcx, %r10
	decq	%r9
	jne	.LBB1_3
# %bb.4:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r8
	addq	$4, %rdx
	addq	$4, %rsi
	addq	$4, %rdi
	cmpq	%rax, %r8
	jne	.LBB1_2
.LBB1_5:                                # %._crit_edge18
	retq
.Lfunc_end1:
	.size	_Z9matrixAddPiS_S_i, .Lfunc_end1-_Z9matrixAddPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%r14d, %r14d
	movl	$.L.str, %edi
	movl	$10000, %esi                    # imm = 0x2710
	movl	$100, %edx
	movl	$100, %ecx
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movl	$1, %esi
	movl	$1, %edx
	movl	$1, %ecx
	xorl	%eax, %eax
	callq	printf
	movl	$40000, %edi                    # imm = 0x9C40
	callq	malloc
	movq	%rax, %r15
	movl	$40000, %edi                    # imm = 0x9C40
	callq	malloc
	movq	%rax, %r12
	movl	$40000, %edi                    # imm = 0x9C40
	callq	malloc
	movq	%rax, %rbx
	movl	$40000, %edi                    # imm = 0x9C40
	callq	malloc
	movl	$400, %edi                      # imm = 0x190
	movq	%r15, %rcx
	movq	%r12, %rdx
.LBB2_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	xorl	%esi, %esi
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r14d, (%rcx,%rsi,4)
	movl	%r14d, (%rdx,%rsi,4)
	incq	%rsi
	cmpq	$100, %rsi
	jne	.LBB2_2
# %bb.3:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%r14
	addq	%rdi, %rdx
	addq	%rdi, %rcx
	cmpq	$100, %r14
	jne	.LBB2_1
# %bb.4:
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	leaq	48(%rsp), %r13
	movl	$40000, %esi                    # imm = 0x9C40
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	40(%rsp), %rbp
	movl	$40000, %esi                    # imm = 0x9C40
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %r14
	movl	$40000, %esi                    # imm = 0x9C40
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$40000, %edx                    # imm = 0x9C40
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$40000, %edx                    # imm = 0x9C40
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	movl	$40000, %edx                    # imm = 0x9C40
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r14), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movabsq	$429496729700, %rdx             # imm = 0x6400000064
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	$100, %ecx
	callq	_Z30__device_stub__matrixAddKernelPiS_S_i
.LBB2_6:
	movq	(%rsp), %rdi
	xorl	%r13d, %r13d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	20(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movq	24(%rsp), %rsi
	movl	$40000, %edx                    # imm = 0x9C40
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	32(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rax
.LBB2_7:                                # %.lr.ph.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_8 Depth 2
	xorl	%ecx, %ecx
.LBB2_8:                                # %.lr.ph.i
                                        #   Parent Loop BB2_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r12,%rcx), %edx
	addl	(%r15,%rcx), %edx
	movl	%edx, (%rax,%rcx)
	addq	$400, %rcx                      # imm = 0x190
	cmpq	$40000, %rcx                    # imm = 0x9C40
	jne	.LBB2_8
# %bb.9:                                # %._crit_edge.i
                                        #   in Loop: Header=BB2_7 Depth=1
	incq	%r13
	addq	$4, %rax
	addq	$4, %r12
	addq	$4, %r15
	cmpq	$100, %r13
	jne	.LBB2_7
# %bb.10:                               # %_Z9matrixAddPiS_S_i.exit
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	20(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movl	(%rbx), %eax
	cmpl	(%rbp), %eax
	je	.LBB2_12
# %bb.11:
	movl	$.Lstr, %edi
	callq	puts@PLT
.LBB2_12:
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15matrixAddKernelPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15matrixAddKernelPiS_S_i,@object # @_Z15matrixAddKernelPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z15matrixAddKernelPiS_S_i
	.p2align	3, 0x0
_Z15matrixAddKernelPiS_S_i:
	.quad	_Z30__device_stub__matrixAddKernelPiS_S_i
	.size	_Z15matrixAddKernelPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Number of threads: %i (%ix%i)\n"
	.size	.L.str, 31

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Number of blocks: %i (%ix%i)\n"
	.size	.L.str.1, 30

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Time to calculate results on GPU: %f ms.\n"
	.size	.L.str.2, 42

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Time to calculate results on CPU: %f ms.\n"
	.size	.L.str.3, 42

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15matrixAddKernelPiS_S_i"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Error: CPU and GPU results do not match"
	.size	.Lstr, 40

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__matrixAddKernelPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15matrixAddKernelPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15matrixAddKernelPiS_S_i ; -- Begin function _Z15matrixAddKernelPiS_S_i
	.globl	_Z15matrixAddKernelPiS_S_i
	.p2align	8
	.type	_Z15matrixAddKernelPiS_S_i,@function
_Z15matrixAddKernelPiS_S_i:             ; @_Z15matrixAddKernelPiS_S_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x2c
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 0x64, v2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, 0x64, v1, v[0:1]
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15matrixAddKernelPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15matrixAddKernelPiS_S_i, .Lfunc_end0-_Z15matrixAddKernelPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 216
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15matrixAddKernelPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15matrixAddKernelPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
