#include "includes.h"
__global__ void backward_kernel(const float *dz, const float *z, const float *var, const float *weight, const float *bias, const float *edz, const float *eydz, float *dx, float *dweight, float *dbias, float eps, int N, int C, int S) {
int plane = blockIdx.x;
float _edz = edz[plane];
float _eydz = eydz[plane];

float gamma = weight != 0 ? abs(weight[plane]) + eps : 1.f;
float beta = bias != 0 ? bias[plane] : 0.f;

if (dx != 0) {
float _var = var[plane];
float invStd = 0;
if (_var != 0.f || eps != 0.f) {
invStd = 1 / sqrt(_var + eps);
}

float mul = gamma * invStd;

for (int batch = 0; batch < N; ++batch) {
for (int n = threadIdx.x; n < S; n += blockDim.x) {
float _dz = dz[(batch * C + plane) * S + n];
float _y = (z[(batch * C + plane) * S + n] - beta) / gamma;
dx[(batch * C + plane) * S + n] = (_dz - _edz - _y * _eydz) * mul;
}
}
}

if (dweight != 0 || dbias != 0) {
float norm = N * S;

if (dweight != 0) {
if (threadIdx.x == 0) {
if (weight[plane] > 0)
dweight[plane] += _eydz * norm;
else if (weight[plane] < 0)
dweight[plane] -= _eydz * norm;
}
}

if (dbias != 0) {
if (threadIdx.x == 0) {
dbias[plane] += _edz * norm;
}
}
}
}
	.file	"tmpxft_0031dad2_00000000-6_backward_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z66__device_stub__Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiiiPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.type	_Z66__device_stub__Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiiiPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii, @function
_Z66__device_stub__Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiiiPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	304(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	120(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 40(%rsp)
	movq	312(%rsp), %rax
	movq	%rdx, 72(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 32(%rsp)
	movq	320(%rsp), %rax
	movq	%rcx, 64(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 24(%rsp)
	movq	328(%rsp), %rax
	movq	%r8, 56(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	112(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 320
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L2:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z66__device_stub__Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiiiPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii, .-_Z66__device_stub__Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiiiPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.globl	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.type	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii, @function
_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z66__device_stub__Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiiiPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.cfi_endproc
.LFE2033:
	.size	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii, .-_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void backward_kernel(const float *dz, const float *z, const float *var, const float *weight, const float *bias, const float *edz, const float *eydz, float *dx, float *dweight, float *dbias, float eps, int N, int C, int S) {
int plane = blockIdx.x;
float _edz = edz[plane];
float _eydz = eydz[plane];

float gamma = weight != 0 ? abs(weight[plane]) + eps : 1.f;
float beta = bias != 0 ? bias[plane] : 0.f;

if (dx != 0) {
float _var = var[plane];
float invStd = 0;
if (_var != 0.f || eps != 0.f) {
invStd = 1 / sqrt(_var + eps);
}

float mul = gamma * invStd;

for (int batch = 0; batch < N; ++batch) {
for (int n = threadIdx.x; n < S; n += blockDim.x) {
float _dz = dz[(batch * C + plane) * S + n];
float _y = (z[(batch * C + plane) * S + n] - beta) / gamma;
dx[(batch * C + plane) * S + n] = (_dz - _edz - _y * _eydz) * mul;
}
}
}

if (dweight != 0 || dbias != 0) {
float norm = N * S;

if (dweight != 0) {
if (threadIdx.x == 0) {
if (weight[plane] > 0)
dweight[plane] += _eydz * norm;
else if (weight[plane] < 0)
dweight[plane] -= _eydz * norm;
}
}

if (dbias != 0) {
if (threadIdx.x == 0) {
dbias[plane] += _edz * norm;
}
}
}
}
	.text
	.file	"backward_kernel.hip"
	.globl	_Z30__device_stub__backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii # -- Begin function _Z30__device_stub__backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.type	_Z30__device_stub__backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii,@function
_Z30__device_stub__backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii: # @_Z30__device_stub__backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	movq	%r9, 80(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii, .Lfunc_end0-_Z30__device_stub__backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii,@object # @_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.section	.rodata,"a",@progbits
	.globl	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.p2align	3, 0x0
_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii:
	.quad	_Z30__device_stub__backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.size	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii"
	.size	.L__unnamed_1, 53

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii ; -- Begin function _Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.globl	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
	.p2align	8
	.type	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii,@function
_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii: ; @_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
; %bb.0:
	s_mov_b32 s26, s15
	s_clause 0x1
	s_load_b512 s[4:19], s[0:1], 0x0
	s_load_b128 s[20:23], s[0:1], 0x50
	s_ashr_i32 s27, s26, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[24:25], s[26:27], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s14, s24
	s_addc_u32 s3, s15, s25
	s_add_u32 s14, s16, s24
	s_addc_u32 s15, s17, s25
	s_cmp_eq_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_2
; %bb.1:
	s_add_u32 s16, s10, s24
	s_addc_u32 s17, s11, s25
	s_load_b32 s16, s[16:17], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v1, |s16|, s20
	s_branch .LBB0_3
.LBB0_2:
	v_mov_b32_e32 v1, 1.0
.LBB0_3:
	s_cmp_eq_u64 s[12:13], 0
	s_cbranch_scc1 .LBB0_5
; %bb.4:
	s_add_u32 s12, s12, s24
	s_addc_u32 s13, s13, s25
	s_load_b32 s16, s[12:13], 0x0
	s_branch .LBB0_6
.LBB0_5:
	s_mov_b32 s16, 0
.LBB0_6:
	s_load_b32 s12, s[2:3], 0x0
	s_load_b32 s13, s[14:15], 0x0
	s_cmp_eq_u64 s[18:19], 0
	s_cbranch_scc1 .LBB0_15
; %bb.7:
	s_add_u32 s2, s8, s24
	s_addc_u32 s3, s9, s25
	v_mov_b32_e32 v2, 0
	s_load_b32 s2, s[2:3], 0x0
	v_cmp_eq_f32_e64 s3, s20, 0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f32_e64 s8, s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s3, s8
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_9
; %bb.8:
	v_add_f32_e64 v2, s2, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x4f800000, v2
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, -1, v3
	v_add_nc_u32_e32 v5, 1, v3
	v_fma_f32 v6, -v4, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v3, v2
	v_cmp_ge_f32_e64 s2, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, v4, s2
	v_cmp_lt_f32_e64 s2, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v5, s2
	v_mul_f32_e32 v4, 0x37800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v3, null, v2, v2, 1.0
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, 1.0, v2, 1.0
	v_mul_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v6, v5
	v_fmac_f32_e32 v6, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v6, v5
	v_div_fmas_f32 v3, v3, v4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v2, v3, v2, 1.0
.LBB0_9:
	s_cmp_lt_i32 s21, 1
	s_cbranch_scc1 .LBB0_15
; %bb.10:                               ; %.lr.ph103
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, v1, v2
	v_cmp_gt_i32_e64 s2, s23, v0
	s_add_u32 s8, s0, 0x60
	s_addc_u32 s9, s1, 0
	s_mul_i32 s14, s26, s23
	s_mul_i32 s15, s23, s22
	s_mov_b32 s17, 0
.LBB0_11:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_13 Depth 2
	s_and_saveexec_b32 s20, s2
	s_cbranch_execz .LBB0_14
; %bb.12:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_load_b32 s3, s[8:9], 0xc
	v_mov_b32_e32 v3, v0
	s_mov_b32 s26, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s22, s3, 0xffff
.LBB0_13:                               ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s14, v3
	v_add_nc_u32_e32 v3, s22, v3
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v6, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v8, v[6:7], off
	v_add_co_u32 v6, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v4, s3, s18, v4
	v_add_co_ci_u32_e64 v5, s3, s19, v5, s3
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(1)
	v_subrev_f32_e32 v7, s16, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_scale_f32 v8, null, v1, v1, v7
	v_div_scale_f32 v11, vcc_lo, v7, v1, v7
	s_waitcnt vmcnt(0)
	v_subrev_f32_e32 v6, s12, v6
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v9
	v_mul_f32_e32 v10, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v8, v10, v11
	v_fmac_f32_e32 v10, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v10, v11
	v_div_fmas_f32 v8, v8, v9, v10
	v_cmp_le_i32_e32 vcc_lo, s23, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v7, v8, v1, v7
	s_or_b32 s26, vcc_lo, s26
	v_fma_f32 v6, -s13, v7, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v6, v2, v6
	global_store_b32 v[4:5], v6, off
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB0_13
.LBB0_14:                               ; %Flow150
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_add_i32 s17, s17, 1
	s_add_i32 s14, s14, s15
	s_cmp_eq_u32 s17, s21
	s_cbranch_scc0 .LBB0_11
.LBB0_15:                               ; %.loopexit
	s_load_b128 s[4:7], s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_or_b64 s[8:9], s[4:5], s[6:7]
	s_cmp_lg_u64 s[4:5], 0
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u64 s[6:7], 0
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u64 s[8:9], 0
	s_cbranch_scc1 .LBB0_24
; %bb.16:
	s_mul_i32 s3, s23, s21
	v_cmp_eq_u32_e64 s0, 0, v0
	v_cvt_f32_i32_e32 v0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s0
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_22
; %bb.17:
	v_mov_b32_e32 v1, 0
	s_add_u32 s8, s10, s24
	s_addc_u32 s9, s11, s25
	s_mov_b32 s3, -1
	global_load_b32 v1, v1, s[8:9]
	s_waitcnt vmcnt(0)
	v_cmp_nlt_f32_e32 vcc_lo, 0, v1
	s_cbranch_vccz .LBB0_20
; %bb.18:
	v_cmp_ngt_f32_e32 vcc_lo, 0, v1
	s_mov_b32 s3, 0
	s_cbranch_vccnz .LBB0_20
; %bb.19:
	v_mov_b32_e32 v1, 0
	s_add_u32 s8, s4, s24
	s_addc_u32 s9, s5, s25
	global_load_b32 v2, v1, s[8:9]
	s_waitcnt vmcnt(0)
	v_fma_f32 v2, -s13, v0, v2
	global_store_b32 v1, v2, s[8:9]
.LBB0_20:                               ; %Flow146
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_22
; %bb.21:
	v_mov_b32_e32 v1, 0
	s_add_u32 s4, s4, s24
	s_addc_u32 s5, s5, s25
	global_load_b32 v2, v1, s[4:5]
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v2, s13, v0
	global_store_b32 v1, v2, s[4:5]
.LBB0_22:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_mov_b32_e32 v1, 0
	s_add_u32 s0, s6, s24
	s_addc_u32 s1, s7, s25
	global_load_b32 v2, v1, s[0:1]
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v2, s12, v0
	global_store_b32 v1, v2, s[0:1]
.LBB0_24:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii, .Lfunc_end0-_Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1068
; NumSgprs: 30
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z15backward_kernelPKfS0_S0_S0_S0_S0_S0_PfS1_S1_fiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
