#include <stdio.h>
__global__ void compute_transport_props_gpu_kernel(double *vx, double *vy, double *vz, double *u, int nelt, int nxyz,int nnel,int irpu, int irpv, int irpw, int iret, int irg, int toteq,int if3d,double *vtrans, int irho, double *phig, int lx1, int ly1, int lz1, int *lglel, double *xm1, double *ym1, double *zm1, double *t,int ldimt, int npscal, double *pr, double p0th, double *sii, double *siii, double *vdiff, int ifield,char *cb, int icv, int icp, double *csound, int imu,int ilam, double cpgref, double cvgref, double gmaref, double rgasref, int *gllel, double *res2, int iknd, int inus, int lxy,int nlel ){

	int id = blockIdx.x*blockDim.x+threadIdx.x;
	if(id<nnel){

		int e = id/nxyz;
		int ieg= lglel[e];
		int k =  (id / (lx1*ly1))%lz1;
		int j =  (id/lx1)%ly1;
		int newi = id % lx1;

		// nekasgn
		double x = xm1[e*nxyz+k*lxy+j*lx1+newi];
		double y = ym1[e*nxyz+k*lxy+j*lx1+newi];
		double z = zm1[e*nxyz+k*lxy+j*lx1+newi];
		double r = x*x+y*y;
		double theta=0.0;
		if (r>0.0){ r = sqrtf(r);}
		if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
		double ux= vx[e*nxyz+k*lxy+j*lx1+newi];
		double uy= vy[e*nxyz+k*lxy+j*lx1+newi];
		double uz= vz[e*nxyz+k*lxy+j*lx1+newi];
		double temp = t [ e*nxyz+k*lxy+j*lx1+newi ];
		int ips;
		double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
		for (ips=0;ips<npscal;ips++){
			ps[ips]=t[(ips+1)*nlel+e*nxyz+k*lxy+j*lx1+newi ]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
		}
		double pa = pr [e*nxyz+k*lxy+j*lx1+newi];
		double p0= p0th;
		double si2 =  sii[e*nxyz+k*lxy+j*lx1+newi];
		double si3 =  siii[e*nxyz+k*lxy+j*lx1+newi];
		double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];
		double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];
		char cbu1 = cb[0];
		char cbu2 = cb[1];
		char cbu3 = cb[2];

		//cmtasgn
		int eqnum;
		double varsic[10];
		int e_offset = toteq*nxyz;
		for (eqnum=0;eqnum<toteq;eqnum++){
			varsic[eqnum] = u[e*e_offset+eqnum*nxyz+k*lxy+j*lx1+newi];

		}
		double phi = phig[e*nxyz+k*lxy+j*lx1+newi];
		double rho = vtrans[(irho-1)*nlel +e*nxyz+k*lxy+j*lx1+newi];
		double pres = pr[e*nxyz+k*lxy+j*lx1+newi];
		double cv=0.0,cp=0.0;
		if(rho!=0){
			cv=vtrans[(icv-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]/rho;
			cp=vtrans[(icp-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]/rho;
		}
		double asnd = csound [e*nxyz+k*lxy+j*lx1+newi];
		double mu = vdiff[(imu-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];
		udiff = vdiff[(imu-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
		double lambda = vdiff[(ilam-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];

		// uservp
		int uservpe = gllel[ieg];
		mu=rho*res2[(uservpe-1)*nxyz+k*lxy+j*lx1+newi] ;//! finite c_E;
		double nu_s=0.75*mu/rho;

		mu=0.5*mu ;
		lambda=0.0;
		udiff=0.0;  // uservp makes these to zero. vdiff get zeros. Check with Dr. Tania. adeesha
		utrans=0.0;	

		vdiff[(imu-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]=mu; // vidff [  + id] is same as this. check later . adeesha
		vdiff[(ilam-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]=lambda;
		vdiff[(iknd-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]=iknd;
		vdiff[(inus-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]=nu_s;



	}

}


extern "C" void compute_transport_props_gpu_wrapper_(int *glbblockSize1,double *d_vx, double *d_vy, double *d_vz, double *d_u,int *nelt,int *irpu, int *irpv, int *irpw, int* iret,  int *irg, int *toteq, int *if3d, double *d_vtrans, int *irho, double *d_phig, int *lx1, int *ly1, int *lz1, int *d_lglel, double *d_xm1, double *d_ym1, double *d_zm1, double *d_t,int *ldimt, int *npscal, double *d_pr, double *p0th, double *d_sii, double *d_siii, double *d_vdiff, int *ifield,char *d_cb, int *icv, int *icp, double *d_csound, int *imu,int *ilam, double *cpgref, double *cvgref, double *gmaref, double *rgasref,  int *d_gllel, double *d_res2, int *iknd, int *inus,int *lelt){

	cudaError_t code1 = cudaPeekAtLastError();

	printf("CUDA: Start compute_transport_props_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));

	printf("CUDA: Start compute_transport_props_gpu_wrapper values nelt =%d,irpu=%d,irpv=%d,irpw=%d,iret=%d,irg=%d,toteq=%d,if3d=%d,irho=%d,lx1=%d,ly1=%d,lz1=%d,ldimt=%d,npscal=%d,p0th=%lf,ifield=%d,icv=%d,icp=%d,imu=%d,ilam=%d,cpgref=%lf,cvgref=%lf,gmaref=%lf,rgasref=%lf,iknd=%d,inus=%d,lelt=%d ,\n", nelt[0],irpu[0],irpv[0],irpw[0],iret[0],irg[0],toteq[0],if3d[0],irho[0],lx1[0],ly1[0],lz1[0],ldimt[0],npscal[0],p0th[0],ifield[0],icv[0],icp[0],imu[0],ilam[0],cpgref[0],cvgref[0],gmaref[0],rgasref[0],iknd[0],inus[0],lelt[0]);


	int blockSize = glbblockSize1[0], gridSize;
	int lxy = lx1[0]*ly1[0];
	int nxyz= lxy*lz1[0];
	int nnel=nxyz*nelt[0];
	int nlel= nxyz*lelt[0];
	gridSize = (int)ceil((float)nnel/blockSize);
	compute_transport_props_gpu_kernel<<<gridSize, blockSize>>>(d_vx, d_vy, d_vz, d_u, nelt[0], nxyz,nnel,  irpu[0], irpv[0], irpw[0], iret[0],irg[0],toteq[0],if3d[0],d_vtrans, irho[0],d_phig ,lx1[0], ly1[0],lz1[0], d_lglel, d_xm1, d_ym1,d_zm1, d_t,ldimt[0], npscal[0], d_pr,p0th[0], d_sii,d_siii,d_vdiff, ifield[0],d_cb, icv[0], icp[0],d_csound,imu[0],ilam[0],  cpgref[0], cvgref[0], gmaref[0], rgasref[0], d_gllel, d_res2, iknd[0], inus[0], lxy,nlel);

	cudaError_t code2 = cudaPeekAtLastError();
	printf("CUDA: End compute_transport_props_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code2));



}


__global__ void imqqtu_gpu_kernel(double *flux, int nf, int lf, int iuj, int ium, int iup,int totthreads){

	int id = blockIdx.x*blockDim.x+threadIdx.x;
	if(id<totthreads){
		flux[(iuj-1)+id] =flux[(ium-1)+id] + flux[(iup-1)+id] ; //add3
		flux[(iuj-1)+id] =flux[(iuj-1)+id] * -0.5; //cmult
		flux[(iuj-1)+id] =  flux[(iuj-1)+id] + flux[(ium-1)+id] ;// add 2
		//above 3 can be simplified iuj= (ium-ium) /2 check with Dr.Tania adeesha


	}

}

extern "C" void imqqtu_gpu_wrapper_(int *glbblockSize2,double *d_flux,int *iuj,int *ium,int *iup,int *lx1, int *ly1, int *lz1, int *ldim, int *nelt, int *lelt, int *toteq){
	 cudaDeviceSynchronize();

	cudaError_t code1 = cudaPeekAtLastError();

	printf("CUDA: Start imqqtu_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));

	printf("CUDA: Start imqqtu_gpu_wrapper values iuj =%d ,ium=%d,iup=%d,lx1=%d,ly1=%d,lz1=%d,ldim=%d,nelt=%d,lelt=%d,toteq=%d\n",iuj[0],ium[0],iup[0],lx1[0],ly1[0],lz1[0],ldim[0],nelt[0],lelt[0],toteq[0]);

	int nf= lx1[0]*lz1[0]*2*ldim[0]*nelt[0];
	int lf= lx1[0]*lz1[0]*2*ldim[0]*lelt[0];
	int totthreads = nf*toteq[0];


	int blockSize = glbblockSize2[0], gridSize;
	gridSize = (int)ceil((float)totthreads/blockSize);
	imqqtu_gpu_kernel<<<gridSize, blockSize>>>(d_flux,nf,lf,iuj[0],ium[0],iup[0],totthreads);

	cudaError_t code2 = cudaPeekAtLastError();

	printf("CUDA: End imqqtu_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code2));



}

__global__ void imqqtu_dirichlet_gpu_kernel(double *flux, int ntot, int ifield, int ltot, int ilam, int irho, int icv, int icp, int imu, double molmass, int iwp, int iwm, int iuj, int iux,int iuy,int iuz, int iph, int ithm, int iu1, int iu2, int iu3, int iu4, int iu5, int icvf,int toteq,int lx1,int ly1,int lz1,int lxy, int lxz,int nxyz, int lxz2ldim, int lxz2ldimlelt, int a2ldim, char *cbc, int *lglel, double *xm1,double *ym1, double *zm1, double *vx, double *vy, double *vz, double *t, double *pr, double *sii, double *siii, double *vdiff, double *vtrans, char *cb, double *u, double *phig, double *pres, double *csound,int npscal,double p0th,int e_offset,int nlel,int nqq){

	int id = blockIdx.x*blockDim.x+threadIdx.x;
	if(id<ntot){
		int i1 = id % lx1;
		int i2 = (id/lx1)%lz1;
		int iface= ((id/lxz)%a2ldim);
		int e = id/lxz2ldim;


		char cb1 = cbc[e*18+iface];
		char cb2 = cbc[e*18+iface+1];
		char cb3 = cbc[e*18+iface+2];
		if(cb1!='E' &&  cb1!='P'){
			if(cb1 =='W'|| cb1=='I'){
				int ieg=lglel[e];

				if(iface==0){
					int iy=0;
					int iz=i2;
					int ix=i1;		
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;

					int l=lx1*iz+ix; // this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha

					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}

				if(iface==3){
					int ix=0;
					int iz=i2;
					int iy=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=ly1*iz+iy;
					// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha


					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}
				if(iface==4){
					int iz=0;
					int iy=i2;
					int ix=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=lx1*iy+ix;// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha


					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-10)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}

				if(iface==1){
					int ix=lx1-1;
					int iz=i2;
					int iy=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=lx1*iz+iy;// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha

					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}

				if(iface==2){
					int iy=ly1-1;
					int iz=i2;
					int ix=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=lx1*iz+ix;// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha


					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}



				if(iface==5){
					int iz=lz1-1;
					int iy=i2;
					int ix=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=lx1*iy+ix;;// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha

					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}
				//			__syncthreads();// double  check  whether this is needed.  adeesha
				int iy=0;
				int iz=i2;
				int ix=i1;
				for(int ivar=0;ivar<toteq;ivar++){
					flux[(iuj-1)+ivar*lxz2ldimlelt+id] = flux[(iwm-1)+ivar*lxz2ldimlelt+id]-flux[(iwp-1)+ivar*lxz2ldimlelt+id];
				}


			}

		}
	}
}


extern "C" void imqqtu_dirichlet_gpu_wrapper_(int *glbblockSize2,double *d_flux, int *ifield,  int *ilam, int *irho, int *icv, int *icp, int *imu, double *molmass, int *iwp, int *iwm, int *iuj, int *iux,int *iuy,int *iuz, int *iph, int *ithm, int *iu1, int *iu2, int *iu3, int *iu4, int *iu5, int *icvf,int *toteq,int *lx1,int *ly1,int *lz1, char *d_cbc, int *d_lglel, double *d_xm1,double *d_ym1, double *d_zm1, double *d_vx, double *d_vy, double *d_vz, double *d_t, double *d_pr, double *d_sii, double *d_siii, double *d_vdiff, double *d_vtrans, char *d_cb, double *d_u, double *d_phig, double *d_pres, double *d_csound, int *ldim, int *lelt, int *nelt,int *npscal, double *p0th,int *nqq  ){

	cudaError_t code1 = cudaPeekAtLastError();

	printf("CUDA: Start imqqtu_dirichlet_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));

	printf("CUDA: Start imqqtu_dirichlet_gpu_wrapper values ifield=%d,ilam=%d,irho=%d,icv=%d,icp=%d,imu=%d,molmass=%lf,iwp=%d,iwm=%d,iuj=%d,iux=%d,iuy=%d,iuz=%d,iph=%d,ithm=%d,iu1=%d,iu2=%d,iu3=%d,iu4=%d,iu5=%d,icvf=%d,toteq=%d,lx1=%d,ly1=%d,lz1=%d,ldim=%d,lelt=%d,nelt=%d,npscal=%d,p0th=%lf,nqq=%d,\n",ifield[0],ilam[0],irho[0],icv[0],icp[0],imu[0],molmass[0],iwp[0],iwm[0],iuj[0],iux[0],iuy[0],iuz[0],iph[0],ithm[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],icvf[0],toteq[0],lx1[0],ly1[0],lz1[0],ldim[0],lelt[0],nelt[0],npscal[0],p0th[0],nqq[0]);

	int lxz2ldim = lx1[0]*lz1[0]*2*ldim[0];
	int nxyz = lx1[0]*ly1[0]*lz1[0];
	int lxy = lx1[0]*ly1[0];
	int lxz = lx1[0]*lz1[0];
	int ntot = nelt[0]*lxz2ldim;
	int lxz2ldimlelt = lxz2ldim*lelt[0];
	int ltot= lxz2ldim*lelt[0];
	int e_offset=toteq[0]*nxyz;
	int  nlel= nxyz*lelt[0];

	int a2ldim= 2*ldim[0];
	int blockSize = glbblockSize2[0], gridSize;
	gridSize = (int)ceil((float)ntot/blockSize);


	imqqtu_dirichlet_gpu_kernel<<<gridSize, blockSize>>>(d_flux, ntot, ifield[0], ltot,ilam[0],irho[0],icv[0],icp[0],imu[0],molmass[0],iwp[0],iwm[0],iuj[0],iux[0],iuy[0],iuz[0],iph[0],ithm[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],icvf[0],toteq[0],lx1[0],ly1[0],lz1[0],lxy,lxz,nxyz,lxz2ldim,lxz2ldimlelt,a2ldim,d_cbc, d_lglel,d_xm1,d_ym1, d_zm1, d_vx,d_vy,d_vz,d_t,d_pr,d_sii,d_siii,d_vdiff,d_vtrans, d_cb,d_u, d_phig,d_pres,d_csound,npscal[0],p0th[0],e_offset,nlel,nqq[0] );

	cudaError_t code2 = cudaPeekAtLastError();

	printf("CUDA: End imqqtu_dirichlet_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code2));


}


	.file	"tmpxft_0023bd1c_00000000-6_diffusive_cmt_cuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z121__device_stub__Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiiiPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.type	_Z121__device_stub__Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiiiPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii, @function
_Z121__device_stub__Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiiiPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$680, %rsp
	.cfi_def_cfa_offset 688
	movq	752(%rsp), %rax
	movq	%rdi, 200(%rsp)
	leaq	224(%rsp), %rdi
	movq	%rsi, 192(%rsp)
	leaq	236(%rsp), %rsi
	movq	%rax, 160(%rsp)
	movq	768(%rsp), %rax
	movq	%rdx, 184(%rsp)
	leaq	208(%rsp), %rdx
	movq	%rax, 152(%rsp)
	movq	800(%rsp), %rax
	movq	%rcx, 176(%rsp)
	leaq	216(%rsp), %rcx
	movq	%rax, 144(%rsp)
	movq	808(%rsp), %rax
	movl	%r8d, 172(%rsp)
	movq	%rax, 136(%rsp)
	movq	816(%rsp), %rax
	movl	%r9d, 168(%rsp)
	movq	%rax, 128(%rsp)
	movq	824(%rsp), %rax
	movsd	%xmm0, 96(%rsp)
	movq	%rax, 120(%rsp)
	movq	832(%rsp), %rax
	movsd	%xmm1, 48(%rsp)
	movq	%rax, 112(%rsp)
	movq	856(%rsp), %rax
	movsd	%xmm2, 40(%rsp)
	movq	%rax, 104(%rsp)
	movq	864(%rsp), %rax
	movsd	%xmm3, 32(%rsp)
	movq	%rax, 88(%rsp)
	movq	872(%rsp), %rax
	movsd	%xmm4, 24(%rsp)
	movq	%rax, 80(%rsp)
	movq	880(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	896(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	920(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	944(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	952(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 664(%rsp)
	xorl	%eax, %eax
	leaq	200(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	184(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	172(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	688(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	696(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	704(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	712(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	720(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	728(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	736(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	744(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	760(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	776(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	784(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	792(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 432(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 440(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 448(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 456(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 464(%rsp)
	leaq	840(%rsp), %rax
	movq	%rax, 472(%rsp)
	leaq	848(%rsp), %rax
	movq	%rax, 480(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 488(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 496(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 504(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 512(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 520(%rsp)
	leaq	888(%rsp), %rax
	movq	%rax, 528(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 536(%rsp)
	leaq	904(%rsp), %rax
	movq	%rax, 544(%rsp)
	leaq	912(%rsp), %rax
	movq	%rax, 552(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 560(%rsp)
	leaq	928(%rsp), %rax
	movq	%rax, 568(%rsp)
	leaq	936(%rsp), %rax
	movq	%rax, 576(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 584(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 592(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 600(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 608(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 616(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 624(%rsp)
	leaq	960(%rsp), %rax
	movq	%rax, 632(%rsp)
	leaq	968(%rsp), %rax
	movq	%rax, 640(%rsp)
	leaq	976(%rsp), %rax
	movq	%rax, 648(%rsp)
	leaq	984(%rsp), %rax
	movq	%rax, 656(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 224(%rsp)
	movl	$1, 232(%rsp)
	movq	%rax, 236(%rsp)
	movl	$1, 244(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	216(%rsp)
	.cfi_def_cfa_offset 696
	leaq	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii(%rip), %rdi
	pushq	216(%rsp)
	.cfi_def_cfa_offset 704
	movq	252(%rsp), %rcx
	movl	260(%rsp), %r8d
	movq	240(%rsp), %rsi
	movl	248(%rsp), %edx
	leaq	288(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 696
	popq	%rdx
	.cfi_def_cfa_offset 688
.L2:
	movq	664(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$680, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z121__device_stub__Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiiiPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii, .-_Z121__device_stub__Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiiiPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.globl	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.type	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii, @function
_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z121__device_stub__Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiiiPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.cfi_endproc
.LFE2055:
	.size	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii, .-_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA: Start compute_transport_props_gpu_wrapper cuda status: %s\n"
.LC1:
	.ascii	"CUDA: Start compute_transport_p"
	.string	"rops_gpu_wrapper values nelt =%d,irpu=%d,irpv=%d,irpw=%d,iret=%d,irg=%d,toteq=%d,if3d=%d,irho=%d,lx1=%d,ly1=%d,lz1=%d,ldimt=%d,npscal=%d,p0th=%lf,ifield=%d,icv=%d,icp=%d,imu=%d,ilam=%d,cpgref=%lf,cvgref=%lf,gmaref=%lf,rgasref=%lf,iknd=%d,inus=%d,lelt=%d ,\n"
.LC2:
	.string	"CUDA: End compute_transport_props_gpu_wrapper cuda status: %s\n"
	.text
	.globl	compute_transport_props_gpu_wrapper_
	.type	compute_transport_props_gpu_wrapper_, @function
compute_transport_props_gpu_wrapper_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	subq	$392, %rsp
	.cfi_def_cfa_offset 448
	movq	448(%rsp), %rax
	movq	%rcx, 200(%rsp)
	movq	%r8, 208(%rsp)
	movq	%rax, 24(%rsp)
	movq	456(%rsp), %rax
	movq	%r9, 8(%rsp)
	movq	%rax, 32(%rsp)
	movq	464(%rsp), %rax
	movq	%rsi, 184(%rsp)
	movq	%rax, 40(%rsp)
	movq	472(%rsp), %rax
	movq	%rdx, 192(%rsp)
	movq	%rax, 48(%rsp)
	movq	480(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	488(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	496(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	504(%rsp), %rax
	movq	528(%rsp), %r12
	movq	536(%rsp), %rbp
	movq	%rax, 216(%rsp)
	movq	512(%rsp), %rax
	movq	544(%rsp), %r14
	movq	%rax, 80(%rsp)
	movq	520(%rsp), %rax
	movq	%rax, 224(%rsp)
	movq	552(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	560(%rsp), %rax
	movq	%rax, 240(%rsp)
	movq	568(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	576(%rsp), %rax
	movq	%rax, 256(%rsp)
	movq	584(%rsp), %rax
	movq	%rax, 264(%rsp)
	movq	592(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	600(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	608(%rsp), %rax
	movq	%rax, 272(%rsp)
	movq	616(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	624(%rsp), %rax
	movq	%rax, 280(%rsp)
	movq	632(%rsp), %rax
	movq	%rax, 288(%rsp)
	movq	640(%rsp), %rax
	movq	%rax, 296(%rsp)
	movq	648(%rsp), %rax
	movq	760(%rsp), %r11
	movq	768(%rsp), %r13
	movq	%rax, 112(%rsp)
	movq	656(%rsp), %rax
	movq	%r11, 16(%rsp)
	movq	696(%rsp), %r15
	movq	%rax, 304(%rsp)
	movq	664(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	672(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	680(%rsp), %rax
	movq	%rax, 312(%rsp)
	movq	688(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	704(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	712(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	720(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	728(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	736(%rsp), %rax
	movq	%rax, 320(%rsp)
	movq	744(%rsp), %rax
	movq	%rax, 328(%rsp)
	movq	752(%rsp), %rax
	movq	%rax, 176(%rsp)
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	0(%r13), %eax
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	pushq	%rax
	.cfi_def_cfa_offset 456
	movq	24(%rsp), %r11
	movl	(%r11), %eax
	movq	%r11, 352(%rsp)
	pushq	%rax
	.cfi_def_cfa_offset 464
	movq	192(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 472
	movl	(%r15), %eax
	pushq	%rax
	.cfi_def_cfa_offset 480
	movq	168(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 488
	movq	168(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 496
	movq	168(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 504
	movq	168(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 512
	movq	160(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 520
	movq	160(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 528
	movl	(%r14), %eax
	pushq	%rax
	.cfi_def_cfa_offset 536
	movl	0(%rbp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 544
	movl	(%r12), %eax
	pushq	%rax
	.cfi_def_cfa_offset 552
	movq	184(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 560
	movq	184(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 568
	movq	184(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 576
	movq	184(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 584
	movq	184(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 592
	movq	312(%rsp), %rax
	movsd	(%rax), %xmm4
	movq	304(%rsp), %rax
	movsd	(%rax), %xmm3
	movq	296(%rsp), %rax
	movsd	(%rax), %xmm2
	movq	288(%rsp), %rax
	movsd	(%rax), %xmm1
	movq	248(%rsp), %rax
	movsd	(%rax), %xmm0
	movq	184(%rsp), %rax
	movl	(%rax), %r9d
	movq	176(%rsp), %rax
	movl	(%rax), %r8d
	movq	168(%rsp), %rax
	movl	(%rax), %ecx
	movq	152(%rsp), %rax
	movl	(%rax), %edx
	movb	$5, %al
	call	__printf_chk@PLT
	movl	(%rbx), %eax
	movl	(%r12), %ebx
	imull	0(%rbp), %ebx
	movl	(%r14), %r10d
	movq	152(%rsp), %rdx
	cvtsi2ssl	%eax, %xmm1
	movl	0(%r13), %r13d
	imull	%ebx, %r10d
	movl	%r10d, %ecx
	imull	(%rdx), %ecx
	movl	%r10d, 484(%rsp)
	movl	%ecx, 160(%rsp)
	addq	$144, %rsp
	.cfi_def_cfa_offset 448
	cvtsi2ssl	16(%rsp), %xmm0
	movl	%eax, 336(%rsp)
	divss	%xmm1, %xmm0
	call	ceilf@PLT
	movl	336(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttss2sil	%xmm0, %edx
	movl	%eax, 372(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 376(%rsp)
	movl	380(%rsp), %ecx
	movq	%rax, 364(%rsp)
	movl	368(%rsp), %esi
	movl	%edx, 360(%rsp)
	movq	372(%rsp), %rdx
	movq	360(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movl	340(%rsp), %r10d
	movq	344(%rsp), %r11
	testl	%eax, %eax
	jne	.L9
	imull	%r10d, %r13d
	movl	%r10d, %r9d
	pushq	%r13
	.cfi_def_cfa_offset 456
	pushq	%rbx
	.cfi_def_cfa_offset 464
	movl	(%r11), %eax
	pushq	%rax
	.cfi_def_cfa_offset 472
	movq	200(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 480
	pushq	360(%rsp)
	.cfi_def_cfa_offset 488
	pushq	360(%rsp)
	.cfi_def_cfa_offset 496
	movl	(%r15), %eax
	pushq	%rax
	.cfi_def_cfa_offset 504
	movq	192(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 512
	pushq	376(%rsp)
	.cfi_def_cfa_offset 520
	movq	200(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 528
	movq	200(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 536
	pushq	392(%rsp)
	.cfi_def_cfa_offset 544
	movq	208(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 552
	pushq	400(%rsp)
	.cfi_def_cfa_offset 560
	pushq	400(%rsp)
	.cfi_def_cfa_offset 568
	pushq	400(%rsp)
	.cfi_def_cfa_offset 576
	pushq	400(%rsp)
	.cfi_def_cfa_offset 584
	movq	232(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 592
	movq	232(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 600
	pushq	416(%rsp)
	.cfi_def_cfa_offset 608
	pushq	416(%rsp)
	.cfi_def_cfa_offset 616
	pushq	416(%rsp)
	.cfi_def_cfa_offset 624
	pushq	416(%rsp)
	.cfi_def_cfa_offset 632
	pushq	416(%rsp)
	.cfi_def_cfa_offset 640
	movl	(%r14), %eax
	pushq	%rax
	.cfi_def_cfa_offset 648
	movl	0(%rbp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 656
	movl	(%r12), %eax
	pushq	%rax
	.cfi_def_cfa_offset 664
	pushq	440(%rsp)
	.cfi_def_cfa_offset 672
	movq	304(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 680
	pushq	448(%rsp)
	.cfi_def_cfa_offset 688
	movq	312(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 696
	movq	312(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 704
	movq	312(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 712
	movq	312(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 720
	movq	312(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 728
	movq	312(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 736
	movq	312(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 744
	movl	312(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 752
	movq	472(%rsp), %rax
	movsd	(%rax), %xmm4
	movq	464(%rsp), %rax
	movq	512(%rsp), %rcx
	movq	504(%rsp), %rdx
	movsd	(%rax), %xmm3
	movq	456(%rsp), %rax
	movq	496(%rsp), %rsi
	movq	488(%rsp), %rdi
	movsd	(%rax), %xmm2
	movq	448(%rsp), %rax
	movsd	(%rax), %xmm1
	movq	408(%rsp), %rax
	movsd	(%rax), %xmm0
	movq	312(%rsp), %rax
	movl	(%rax), %r8d
	call	_Z121__device_stub__Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiiiPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	addq	$304, %rsp
	.cfi_def_cfa_offset 448
.L9:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	addq	$392, %rsp
	.cfi_def_cfa_offset 56
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%rax, %rdx
	popq	%rbp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2027:
	.size	compute_transport_props_gpu_wrapper_, .-compute_transport_props_gpu_wrapper_
	.globl	_Z43__device_stub__Z17imqqtu_gpu_kernelPdiiiiiiPdiiiiii
	.type	_Z43__device_stub__Z17imqqtu_gpu_kernelPdiiiiiiPdiiiiii, @function
_Z43__device_stub__Z17imqqtu_gpu_kernelPdiiiiiiPdiiiiii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z17imqqtu_gpu_kernelPdiiiiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L11:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z43__device_stub__Z17imqqtu_gpu_kernelPdiiiiiiPdiiiiii, .-_Z43__device_stub__Z17imqqtu_gpu_kernelPdiiiiiiPdiiiiii
	.globl	_Z17imqqtu_gpu_kernelPdiiiiii
	.type	_Z17imqqtu_gpu_kernelPdiiiiii, @function
_Z17imqqtu_gpu_kernelPdiiiiii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z17imqqtu_gpu_kernelPdiiiiiiPdiiiiii
	.cfi_endproc
.LFE2057:
	.size	_Z17imqqtu_gpu_kernelPdiiiiii, .-_Z17imqqtu_gpu_kernelPdiiiiii
	.section	.rodata.str1.1
.LC3:
	.string	"CUDA: Start imqqtu_gpu_wrapper cuda status: %s\n"
.LC4:
	.string	"CUDA: Start imqqtu_gpu_wrapper values iuj =%d ,ium=%d,iup=%d,lx1=%d,ly1=%d,lz1=%d,ldim=%d,nelt=%d,lelt=%d,toteq=%d\n"
.LC5:
	.string	"CUDA: End imqqtu_gpu_wrapper cuda status: %s\n"
	.text
	.globl	imqqtu_gpu_wrapper_
	.type	imqqtu_gpu_wrapper_, @function
imqqtu_gpu_wrapper_:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rcx, 8(%rsp)
	movq	144(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	168(%rsp), %r15
	movq	%rcx, 40(%rsp)
	movq	184(%rsp), %r13
	movq	%rsi, 32(%rsp)
	movq	152(%rsp), %rbp
	movq	%rdx, (%rsp)
	movq	160(%rsp), %rbx
	movq	%rdi, 24(%rsp)
	movq	176(%rsp), %r14
	call	cudaDeviceSynchronize@PLT
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	0(%r13), %eax
	movl	$2, %edi
	leaq	.LC4(%rip), %rsi
	pushq	%rax
	.cfi_def_cfa_offset 152
	movl	(%r14), %eax
	pushq	%rax
	.cfi_def_cfa_offset 160
	movl	(%r15), %eax
	pushq	%rax
	.cfi_def_cfa_offset 168
	movl	(%rbx), %eax
	pushq	%rax
	.cfi_def_cfa_offset 176
	movl	0(%rbp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 184
	movq	80(%rsp), %rcx
	movl	(%rcx), %eax
	pushq	%rax
	.cfi_def_cfa_offset 192
	movq	64(%rsp), %rax
	movl	(%r12), %r9d
	movl	(%rax), %r8d
	movq	56(%rsp), %rax
	movl	(%rax), %ecx
	movq	48(%rsp), %rax
	movl	(%rax), %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	(%r12), %edx
	imull	0(%rbp), %edx
	imull	(%rbx), %edx
	movl	0(%r13), %eax
	movl	(%r14), %r14d
	movl	%edx, %r12d
	imull	(%r15), %r12d
	movl	%edx, 88(%rsp)
	addl	%r12d, %r12d
	imull	%r12d, %eax
	movl	%eax, %r13d
	movq	72(%rsp), %rax
	addq	$48, %rsp
	.cfi_def_cfa_offset 144
	cvtsi2ssl	%r13d, %xmm0
	movl	(%rax), %r15d
	cvtsi2ssl	%r15d, %xmm1
	divss	%xmm1, %xmm0
	call	ceilf@PLT
	movl	%r15d, 68(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	cvttss2sil	%xmm0, %edx
	movq	%rax, 72(%rsp)
	movl	76(%rsp), %ecx
	movq	%rax, 60(%rsp)
	movl	64(%rsp), %esi
	movl	%edx, 56(%rsp)
	movq	68(%rsp), %rdx
	movq	56(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movl	40(%rsp), %r10d
	testl	%eax, %eax
	jne	.L17
	pushq	%rax
	.cfi_def_cfa_offset 152
	imull	%r14d, %r10d
	movl	%r12d, %esi
	pushq	%r13
	.cfi_def_cfa_offset 160
	movq	32(%rsp), %rax
	movq	48(%rsp), %rdi
	movl	(%rax), %r9d
	movq	24(%rsp), %rax
	leal	(%r10,%r10), %edx
	movl	(%rax), %r8d
	movq	16(%rsp), %rax
	movl	(%rax), %ecx
	call	_Z43__device_stub__Z17imqqtu_gpu_kernelPdiiiiiiPdiiiiii
	popq	%rdx
	.cfi_def_cfa_offset 152
	popq	%rcx
	.cfi_def_cfa_offset 144
.L17:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	movl	$2, %edi
	leaq	.LC5(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%rax, %rdx
	popq	%rbp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2028:
	.size	imqqtu_gpu_wrapper_, .-imqqtu_gpu_wrapper_
	.globl	_Z124__device_stub__Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiiiPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.type	_Z124__device_stub__Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiiiPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii, @function
_Z124__device_stub__Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiiiPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$760, %rsp
	.cfi_def_cfa_offset 768
	movq	984(%rsp), %rax
	movq	%rdi, 200(%rsp)
	leaq	232(%rsp), %rdi
	movl	%esi, 196(%rsp)
	leaq	244(%rsp), %rsi
	movq	%rax, 160(%rsp)
	movq	992(%rsp), %rax
	movl	%edx, 192(%rsp)
	leaq	216(%rsp), %rdx
	movq	%rax, 152(%rsp)
	movq	1000(%rsp), %rax
	movl	%ecx, 188(%rsp)
	leaq	224(%rsp), %rcx
	movq	%rax, 144(%rsp)
	movq	1008(%rsp), %rax
	movl	%r8d, 184(%rsp)
	movq	%rax, 136(%rsp)
	movq	1016(%rsp), %rax
	movl	%r9d, 180(%rsp)
	movq	%rax, 128(%rsp)
	movq	1024(%rsp), %rax
	movsd	%xmm0, 168(%rsp)
	movq	%rax, 120(%rsp)
	movq	1032(%rsp), %rax
	movsd	%xmm1, 8(%rsp)
	movq	%rax, 112(%rsp)
	movq	1040(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	1048(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	1056(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	1064(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	1072(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	1080(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	1088(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	1096(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	1104(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	1112(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	1120(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	1128(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 744(%rsp)
	xorl	%eax, %eax
	leaq	200(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	196(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	188(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	184(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	180(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	768(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	776(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	784(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	792(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	800(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	808(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	816(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	824(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	832(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	840(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	848(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	856(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	864(%rsp), %rax
	movq	%rax, 432(%rsp)
	leaq	872(%rsp), %rax
	movq	%rax, 440(%rsp)
	leaq	880(%rsp), %rax
	movq	%rax, 448(%rsp)
	leaq	888(%rsp), %rax
	movq	%rax, 456(%rsp)
	leaq	896(%rsp), %rax
	movq	%rax, 464(%rsp)
	leaq	904(%rsp), %rax
	movq	%rax, 472(%rsp)
	leaq	912(%rsp), %rax
	movq	%rax, 480(%rsp)
	leaq	920(%rsp), %rax
	movq	%rax, 488(%rsp)
	leaq	928(%rsp), %rax
	movq	%rax, 496(%rsp)
	leaq	936(%rsp), %rax
	movq	%rax, 504(%rsp)
	leaq	944(%rsp), %rax
	movq	%rax, 512(%rsp)
	leaq	952(%rsp), %rax
	movq	%rax, 520(%rsp)
	leaq	960(%rsp), %rax
	movq	%rax, 528(%rsp)
	leaq	968(%rsp), %rax
	movq	%rax, 536(%rsp)
	leaq	976(%rsp), %rax
	movq	%rax, 544(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 552(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 560(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 568(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 576(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 584(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 592(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 600(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 608(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 616(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 624(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 632(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 640(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 648(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 656(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 664(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 672(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 680(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 688(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 696(%rsp)
	leaq	1136(%rsp), %rax
	movq	%rax, 704(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 712(%rsp)
	leaq	1144(%rsp), %rax
	movq	%rax, 720(%rsp)
	leaq	1152(%rsp), %rax
	movq	%rax, 728(%rsp)
	leaq	1160(%rsp), %rax
	movq	%rax, 736(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 232(%rsp)
	movl	$1, 240(%rsp)
	movq	%rax, 244(%rsp)
	movl	$1, 252(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	224(%rsp)
	.cfi_def_cfa_offset 776
	leaq	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii(%rip), %rdi
	pushq	224(%rsp)
	.cfi_def_cfa_offset 784
	movq	260(%rsp), %rcx
	movl	268(%rsp), %r8d
	movq	248(%rsp), %rsi
	movl	256(%rsp), %edx
	leaq	296(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 776
	popq	%rdx
	.cfi_def_cfa_offset 768
.L19:
	movq	744(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$760, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z124__device_stub__Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiiiPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii, .-_Z124__device_stub__Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiiiPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.globl	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.type	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii, @function
_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z124__device_stub__Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiiiPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.cfi_endproc
.LFE2059:
	.size	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii, .-_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.section	.rodata.str1.1
.LC6:
	.string	"CUDA: Start imqqtu_dirichlet_gpu_wrapper cuda status: %s\n"
.LC7:
	.ascii	"CUDA: Start imqqtu_dirichlet_gpu"
	.string	"_wrapper values ifield=%d,ilam=%d,irho=%d,icv=%d,icp=%d,imu=%d,molmass=%lf,iwp=%d,iwm=%d,iuj=%d,iux=%d,iuy=%d,iuz=%d,iph=%d,ithm=%d,iu1=%d,iu2=%d,iu3=%d,iu4=%d,iu5=%d,icvf=%d,toteq=%d,lx1=%d,ly1=%d,lz1=%d,ldim=%d,lelt=%d,nelt=%d,npscal=%d,p0th=%lf,nqq=%d,\n"
.LC8:
	.string	"CUDA: End imqqtu_dirichlet_gpu_wrapper cuda status: %s\n"
	.text
	.globl	imqqtu_dirichlet_gpu_wrapper_
	.type	imqqtu_dirichlet_gpu_wrapper_, @function
imqqtu_dirichlet_gpu_wrapper_:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$440, %rsp
	.cfi_def_cfa_offset 496
	movq	496(%rsp), %rax
	movq	%rcx, 40(%rsp)
	movq	%r8, 48(%rsp)
	movq	%rax, 64(%rsp)
	movq	504(%rsp), %rax
	movq	%r9, 56(%rsp)
	movq	%rax, 72(%rsp)
	movq	512(%rsp), %rax
	movq	%rsi, 232(%rsp)
	movq	%rax, 80(%rsp)
	movq	520(%rsp), %rax
	movq	%rdx, 32(%rsp)
	movq	%rax, 88(%rsp)
	movq	528(%rsp), %rax
	movq	%rdi, 224(%rsp)
	movq	%rax, 96(%rsp)
	movq	536(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	544(%rsp), %rax
	movq	632(%rsp), %r13
	movq	%rax, 112(%rsp)
	movq	552(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	560(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	568(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	576(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	584(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	592(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	600(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	608(%rsp), %rax
	movq	%rax, 176(%rsp)
	movq	616(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	624(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	640(%rsp), %rax
	movq	%rax, (%rsp)
	movq	648(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	656(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	664(%rsp), %rax
	movq	%rax, 240(%rsp)
	movq	672(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	680(%rsp), %rax
	movq	%rax, 256(%rsp)
	movq	688(%rsp), %rax
	movq	%rax, 264(%rsp)
	movq	696(%rsp), %rax
	movq	%rax, 272(%rsp)
	movq	704(%rsp), %rax
	movq	%rax, 280(%rsp)
	movq	712(%rsp), %rax
	movq	%rax, 288(%rsp)
	movq	720(%rsp), %rax
	movq	%rax, 296(%rsp)
	movq	728(%rsp), %rax
	movq	%rax, 304(%rsp)
	movq	736(%rsp), %rax
	movq	%rax, 312(%rsp)
	movq	744(%rsp), %rax
	movq	%rax, 320(%rsp)
	movq	752(%rsp), %rax
	movq	%rax, 328(%rsp)
	movq	760(%rsp), %rax
	movq	%rax, 336(%rsp)
	movq	768(%rsp), %rax
	movq	%rax, 344(%rsp)
	movq	776(%rsp), %rax
	movq	%rax, 352(%rsp)
	movq	784(%rsp), %rax
	movq	%rax, 360(%rsp)
	movq	792(%rsp), %rax
	movq	%rax, 368(%rsp)
	movq	800(%rsp), %rax
	movq	%rax, 376(%rsp)
	movq	808(%rsp), %rax
	movq	816(%rsp), %rbp
	movq	832(%rsp), %r15
	movq	%rax, 384(%rsp)
	movq	840(%rsp), %rax
	movq	824(%rsp), %r14
	movq	%rax, 200(%rsp)
	movq	848(%rsp), %rax
	movq	%rax, 208(%rsp)
	movq	856(%rsp), %rax
	movq	%rax, 216(%rsp)
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	pushq	%rax
	.cfi_def_cfa_offset 504
	movq	224(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 512
	movq	216(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 520
	movl	(%r15), %eax
	pushq	%rax
	.cfi_def_cfa_offset 528
	movl	(%r14), %eax
	pushq	%rax
	.cfi_def_cfa_offset 536
	movl	0(%rbp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 544
	movq	64(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 552
	movq	64(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 560
	movq	64(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 568
	movl	0(%r13), %eax
	pushq	%rax
	.cfi_def_cfa_offset 576
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 584
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 592
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 600
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 608
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 616
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 624
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 632
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 640
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 648
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 656
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 664
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 672
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 680
	movq	272(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 688
	movq	264(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 696
	movq	264(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 704
	movq	416(%rsp), %rax
	movsd	(%rax), %xmm1
	movq	288(%rsp), %rax
	movsd	(%rax), %xmm0
	movq	264(%rsp), %rax
	movl	(%rax), %r9d
	movq	256(%rsp), %rax
	movl	(%rax), %r8d
	movq	248(%rsp), %rax
	movl	(%rax), %ecx
	movq	240(%rsp), %rax
	movl	(%rax), %edx
	movb	$2, %al
	call	__printf_chk@PLT
	movq	208(%rsp), %rax
	movl	(%r14), %r14d
	movl	(%rax), %r11d
	movq	224(%rsp), %rax
	movl	(%rax), %ebx
	movl	%r11d, %r10d
	movl	0(%rbp), %eax
	movl	%r11d, 604(%rsp)
	imull	%ebx, %r10d
	movl	%eax, %ebp
	movl	%eax, 232(%rsp)
	movq	216(%rsp), %rax
	movl	(%rax), %r12d
	movl	(%r15), %eax
	imull	%r10d, %ebp
	movl	%r10d, 600(%rsp)
	movl	0(%r13), %r15d
	addl	%ebp, %ebp
	imull	%ebp, %eax
	movl	%eax, 236(%rsp)
	movq	432(%rsp), %rax
	addq	$208, %rsp
	.cfi_def_cfa_offset 496
	cvtsi2ssl	28(%rsp), %xmm0
	movl	(%rax), %eax
	cvtsi2ssl	%eax, %xmm1
	movl	%eax, 224(%rsp)
	divss	%xmm1, %xmm0
	call	ceilf@PLT
	movl	224(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttss2sil	%xmm0, %edx
	movl	%eax, 420(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 424(%rsp)
	movl	428(%rsp), %ecx
	movq	%rax, 412(%rsp)
	movl	416(%rsp), %esi
	movl	%edx, 408(%rsp)
	movq	420(%rsp), %rdx
	movq	408(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movl	392(%rsp), %r10d
	movl	396(%rsp), %r11d
	testl	%eax, %eax
	jne	.L25
	imull	%r11d, %r12d
	movq	216(%rsp), %rax
	movl	%r14d, %ecx
	imull	%ebp, %ecx
	movl	(%rax), %eax
	imull	%r12d, %ebx
	pushq	%rax
	.cfi_def_cfa_offset 504
	imull	%ebx, %r14d
	imull	%ebx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 512
	pushq	%r15
	.cfi_def_cfa_offset 520
	movq	224(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 528
	pushq	416(%rsp)
	.cfi_def_cfa_offset 536
	pushq	416(%rsp)
	.cfi_def_cfa_offset 544
	pushq	416(%rsp)
	.cfi_def_cfa_offset 552
	pushq	416(%rsp)
	.cfi_def_cfa_offset 560
	pushq	416(%rsp)
	.cfi_def_cfa_offset 568
	pushq	416(%rsp)
	.cfi_def_cfa_offset 576
	pushq	416(%rsp)
	.cfi_def_cfa_offset 584
	pushq	416(%rsp)
	.cfi_def_cfa_offset 592
	pushq	416(%rsp)
	.cfi_def_cfa_offset 600
	pushq	416(%rsp)
	.cfi_def_cfa_offset 608
	pushq	416(%rsp)
	.cfi_def_cfa_offset 616
	pushq	416(%rsp)
	.cfi_def_cfa_offset 624
	pushq	416(%rsp)
	.cfi_def_cfa_offset 632
	pushq	416(%rsp)
	.cfi_def_cfa_offset 640
	pushq	416(%rsp)
	.cfi_def_cfa_offset 648
	pushq	416(%rsp)
	.cfi_def_cfa_offset 656
	pushq	416(%rsp)
	.cfi_def_cfa_offset 664
	pushq	416(%rsp)
	.cfi_def_cfa_offset 672
	pushq	416(%rsp)
	.cfi_def_cfa_offset 680
	movl	208(%rsp), %eax
	addl	%eax, %eax
	pushq	%rax
	.cfi_def_cfa_offset 688
	pushq	%rcx
	.cfi_def_cfa_offset 696
	pushq	%rbp
	.cfi_def_cfa_offset 704
	pushq	%rbx
	.cfi_def_cfa_offset 712
	pushq	%r10
	.cfi_def_cfa_offset 720
	pushq	%r12
	.cfi_def_cfa_offset 728
	movq	248(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 736
	movq	248(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 744
	movq	248(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 752
	movl	0(%r13), %eax
	pushq	%rax
	.cfi_def_cfa_offset 760
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 768
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 776
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 784
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 792
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 800
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 808
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 816
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 824
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 832
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 840
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 848
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 856
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 864
	movq	456(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 872
	movq	448(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 880
	movq	448(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 888
	movq	448(%rsp), %rax
	movl	(%rax), %eax
	pushq	%rax
	.cfi_def_cfa_offset 896
	movq	608(%rsp), %rax
	movl	428(%rsp), %esi
	movq	632(%rsp), %rdi
	movsd	(%rax), %xmm1
	movq	480(%rsp), %rax
	movsd	(%rax), %xmm0
	movq	448(%rsp), %rax
	movl	(%rax), %r9d
	movq	440(%rsp), %rax
	movl	(%rax), %r8d
	movq	432(%rsp), %rax
	movl	(%rax), %edx
	call	_Z124__device_stub__Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiiiPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	addq	$400, %rsp
	.cfi_def_cfa_offset 496
.L25:
	call	cudaPeekAtLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	addq	$440, %rsp
	.cfi_def_cfa_offset 56
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%rax, %rdx
	popq	%rbp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2029:
	.size	imqqtu_dirichlet_gpu_wrapper_, .-imqqtu_dirichlet_gpu_wrapper_
	.section	.rodata.str1.1
.LC9:
	.string	"_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii"
.LC10:
	.string	"_Z17imqqtu_gpu_kernelPdiiiiii"
.LC11:
	.string	"_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17imqqtu_gpu_kernelPdiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void compute_transport_props_gpu_kernel(double *vx, double *vy, double *vz, double *u, int nelt, int nxyz,int nnel,int irpu, int irpv, int irpw, int iret, int irg, int toteq,int if3d,double *vtrans, int irho, double *phig, int lx1, int ly1, int lz1, int *lglel, double *xm1, double *ym1, double *zm1, double *t,int ldimt, int npscal, double *pr, double p0th, double *sii, double *siii, double *vdiff, int ifield,char *cb, int icv, int icp, double *csound, int imu,int ilam, double cpgref, double cvgref, double gmaref, double rgasref, int *gllel, double *res2, int iknd, int inus, int lxy,int nlel ){

	int id = blockIdx.x*blockDim.x+threadIdx.x;
	if(id<nnel){

		int e = id/nxyz;
		int ieg= lglel[e];
		int k =  (id / (lx1*ly1))%lz1;
		int j =  (id/lx1)%ly1;
		int newi = id % lx1;

		// nekasgn
		double x = xm1[e*nxyz+k*lxy+j*lx1+newi];
		double y = ym1[e*nxyz+k*lxy+j*lx1+newi];
		double z = zm1[e*nxyz+k*lxy+j*lx1+newi];
		double r = x*x+y*y;
		double theta=0.0;
		if (r>0.0){ r = sqrtf(r);}
		if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
		double ux= vx[e*nxyz+k*lxy+j*lx1+newi];
		double uy= vy[e*nxyz+k*lxy+j*lx1+newi];
		double uz= vz[e*nxyz+k*lxy+j*lx1+newi];
		double temp = t [ e*nxyz+k*lxy+j*lx1+newi ];
		int ips;
		double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
		for (ips=0;ips<npscal;ips++){
			ps[ips]=t[(ips+1)*nlel+e*nxyz+k*lxy+j*lx1+newi ]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
		}
		double pa = pr [e*nxyz+k*lxy+j*lx1+newi];
		double p0= p0th;
		double si2 =  sii[e*nxyz+k*lxy+j*lx1+newi];
		double si3 =  siii[e*nxyz+k*lxy+j*lx1+newi];
		double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];
		double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];
		char cbu1 = cb[0];
		char cbu2 = cb[1];
		char cbu3 = cb[2];

		//cmtasgn
		int eqnum;
		double varsic[10];
		int e_offset = toteq*nxyz;
		for (eqnum=0;eqnum<toteq;eqnum++){
			varsic[eqnum] = u[e*e_offset+eqnum*nxyz+k*lxy+j*lx1+newi];

		}
		double phi = phig[e*nxyz+k*lxy+j*lx1+newi];
		double rho = vtrans[(irho-1)*nlel +e*nxyz+k*lxy+j*lx1+newi];
		double pres = pr[e*nxyz+k*lxy+j*lx1+newi];
		double cv=0.0,cp=0.0;
		if(rho!=0){
			cv=vtrans[(icv-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]/rho;
			cp=vtrans[(icp-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]/rho;
		}
		double asnd = csound [e*nxyz+k*lxy+j*lx1+newi];
		double mu = vdiff[(imu-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];
		udiff = vdiff[(imu-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
		double lambda = vdiff[(ilam-1)*nlel+e*nxyz+k*lxy+j*lx1+newi];

		// uservp
		int uservpe = gllel[ieg];
		mu=rho*res2[(uservpe-1)*nxyz+k*lxy+j*lx1+newi] ;//! finite c_E;
		double nu_s=0.75*mu/rho;

		mu=0.5*mu ;
		lambda=0.0;
		udiff=0.0;  // uservp makes these to zero. vdiff get zeros. Check with Dr. Tania. adeesha
		utrans=0.0;	

		vdiff[(imu-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]=mu; // vidff [  + id] is same as this. check later . adeesha
		vdiff[(ilam-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]=lambda;
		vdiff[(iknd-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]=iknd;
		vdiff[(inus-1)*nlel +e*nxyz+k*lxy+j*lx1+newi]=nu_s;



	}

}


extern "C" void compute_transport_props_gpu_wrapper_(int *glbblockSize1,double *d_vx, double *d_vy, double *d_vz, double *d_u,int *nelt,int *irpu, int *irpv, int *irpw, int* iret,  int *irg, int *toteq, int *if3d, double *d_vtrans, int *irho, double *d_phig, int *lx1, int *ly1, int *lz1, int *d_lglel, double *d_xm1, double *d_ym1, double *d_zm1, double *d_t,int *ldimt, int *npscal, double *d_pr, double *p0th, double *d_sii, double *d_siii, double *d_vdiff, int *ifield,char *d_cb, int *icv, int *icp, double *d_csound, int *imu,int *ilam, double *cpgref, double *cvgref, double *gmaref, double *rgasref,  int *d_gllel, double *d_res2, int *iknd, int *inus,int *lelt){

	hipError_t code1 = hipPeekAtLastError();

	printf("CUDA: Start compute_transport_props_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));

	printf("CUDA: Start compute_transport_props_gpu_wrapper values nelt =%d,irpu=%d,irpv=%d,irpw=%d,iret=%d,irg=%d,toteq=%d,if3d=%d,irho=%d,lx1=%d,ly1=%d,lz1=%d,ldimt=%d,npscal=%d,p0th=%lf,ifield=%d,icv=%d,icp=%d,imu=%d,ilam=%d,cpgref=%lf,cvgref=%lf,gmaref=%lf,rgasref=%lf,iknd=%d,inus=%d,lelt=%d ,\n", nelt[0],irpu[0],irpv[0],irpw[0],iret[0],irg[0],toteq[0],if3d[0],irho[0],lx1[0],ly1[0],lz1[0],ldimt[0],npscal[0],p0th[0],ifield[0],icv[0],icp[0],imu[0],ilam[0],cpgref[0],cvgref[0],gmaref[0],rgasref[0],iknd[0],inus[0],lelt[0]);


	int blockSize = glbblockSize1[0], gridSize;
	int lxy = lx1[0]*ly1[0];
	int nxyz= lxy*lz1[0];
	int nnel=nxyz*nelt[0];
	int nlel= nxyz*lelt[0];
	gridSize = (int)ceil((float)nnel/blockSize);
	compute_transport_props_gpu_kernel<<<gridSize, blockSize>>>(d_vx, d_vy, d_vz, d_u, nelt[0], nxyz,nnel,  irpu[0], irpv[0], irpw[0], iret[0],irg[0],toteq[0],if3d[0],d_vtrans, irho[0],d_phig ,lx1[0], ly1[0],lz1[0], d_lglel, d_xm1, d_ym1,d_zm1, d_t,ldimt[0], npscal[0], d_pr,p0th[0], d_sii,d_siii,d_vdiff, ifield[0],d_cb, icv[0], icp[0],d_csound,imu[0],ilam[0],  cpgref[0], cvgref[0], gmaref[0], rgasref[0], d_gllel, d_res2, iknd[0], inus[0], lxy,nlel);

	hipError_t code2 = hipPeekAtLastError();
	printf("CUDA: End compute_transport_props_gpu_wrapper cuda status: %s\n",hipGetErrorString(code2));



}


__global__ void imqqtu_gpu_kernel(double *flux, int nf, int lf, int iuj, int ium, int iup,int totthreads){

	int id = blockIdx.x*blockDim.x+threadIdx.x;
	if(id<totthreads){
		flux[(iuj-1)+id] =flux[(ium-1)+id] + flux[(iup-1)+id] ; //add3
		flux[(iuj-1)+id] =flux[(iuj-1)+id] * -0.5; //cmult
		flux[(iuj-1)+id] =  flux[(iuj-1)+id] + flux[(ium-1)+id] ;// add 2
		//above 3 can be simplified iuj= (ium-ium) /2 check with Dr.Tania adeesha


	}

}

extern "C" void imqqtu_gpu_wrapper_(int *glbblockSize2,double *d_flux,int *iuj,int *ium,int *iup,int *lx1, int *ly1, int *lz1, int *ldim, int *nelt, int *lelt, int *toteq){
	 hipDeviceSynchronize();

	hipError_t code1 = hipPeekAtLastError();

	printf("CUDA: Start imqqtu_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));

	printf("CUDA: Start imqqtu_gpu_wrapper values iuj =%d ,ium=%d,iup=%d,lx1=%d,ly1=%d,lz1=%d,ldim=%d,nelt=%d,lelt=%d,toteq=%d\n",iuj[0],ium[0],iup[0],lx1[0],ly1[0],lz1[0],ldim[0],nelt[0],lelt[0],toteq[0]);

	int nf= lx1[0]*lz1[0]*2*ldim[0]*nelt[0];
	int lf= lx1[0]*lz1[0]*2*ldim[0]*lelt[0];
	int totthreads = nf*toteq[0];


	int blockSize = glbblockSize2[0], gridSize;
	gridSize = (int)ceil((float)totthreads/blockSize);
	imqqtu_gpu_kernel<<<gridSize, blockSize>>>(d_flux,nf,lf,iuj[0],ium[0],iup[0],totthreads);

	hipError_t code2 = hipPeekAtLastError();

	printf("CUDA: End imqqtu_gpu_wrapper cuda status: %s\n",hipGetErrorString(code2));



}

__global__ void imqqtu_dirichlet_gpu_kernel(double *flux, int ntot, int ifield, int ltot, int ilam, int irho, int icv, int icp, int imu, double molmass, int iwp, int iwm, int iuj, int iux,int iuy,int iuz, int iph, int ithm, int iu1, int iu2, int iu3, int iu4, int iu5, int icvf,int toteq,int lx1,int ly1,int lz1,int lxy, int lxz,int nxyz, int lxz2ldim, int lxz2ldimlelt, int a2ldim, char *cbc, int *lglel, double *xm1,double *ym1, double *zm1, double *vx, double *vy, double *vz, double *t, double *pr, double *sii, double *siii, double *vdiff, double *vtrans, char *cb, double *u, double *phig, double *pres, double *csound,int npscal,double p0th,int e_offset,int nlel,int nqq){

	int id = blockIdx.x*blockDim.x+threadIdx.x;
	if(id<ntot){
		int i1 = id % lx1;
		int i2 = (id/lx1)%lz1;
		int iface= ((id/lxz)%a2ldim);
		int e = id/lxz2ldim;


		char cb1 = cbc[e*18+iface];
		char cb2 = cbc[e*18+iface+1];
		char cb3 = cbc[e*18+iface+2];
		if(cb1!='E' &&  cb1!='P'){
			if(cb1 =='W'|| cb1=='I'){
				int ieg=lglel[e];

				if(iface==0){
					int iy=0;
					int iz=i2;
					int ix=i1;		
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;

					int l=lx1*iz+ix; // this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha

					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}

				if(iface==3){
					int ix=0;
					int iz=i2;
					int iy=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=ly1*iz+iy;
					// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha


					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}
				if(iface==4){
					int iz=0;
					int iy=i2;
					int ix=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=lx1*iy+ix;// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha


					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-10)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}

				if(iface==1){
					int ix=lx1-1;
					int iz=i2;
					int iy=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=lx1*iz+iy;// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha

					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}

				if(iface==2){
					int iy=ly1-1;
					int iz=i2;
					int ix=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=lx1*iz+ix;// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha


					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}



				if(iface==5){
					int iz=lz1-1;
					int iy=i2;
					int ix=i1;
					//nekasgn
					double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
					double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
					double r = x*x+y*y;
					double theta=0.0;
					if (r>0.0){ r = sqrtf(r);}
					if ( x != 0.0 || y!= 0.0){theta = atan2(y,x);   }
					double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
					double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
					double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
					double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
					int ips;
					double ps[10]; // ps is size of ldimt which is 3. Not sure npscal is also 3. Need to check with Dr.Tania
					for (ips=0;ips<npscal;ips++){
						ps[ips]=t[(ips+1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]; // 5 th dimension of t is idlmt which is 3. Not sure how the  nekasgn access ips+1. Need to check with Dr.Tania
					}
					double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
					double p0= p0th;
					double si2 =  sii[e*nxyz+iz*lxy+iy*lx1+ix];
					double si3 =  siii[e*nxyz+iz*lxy+iy*lx1+ix];
					double udiff =  vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					double utrans =  vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					char cbu1 = cb[0];
					char cbu2 = cb[1];
					char cbu3 = cb[2];

					//cmtasgn
					int eqnum;
					double varsic[10];
					for (eqnum=0;eqnum<toteq;eqnum++){
						varsic[eqnum] = u[e*e_offset+eqnum*nxyz+iz*lxy+iy*lx1+ix];

					}
					double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
					double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
					double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
					double cv=0.0,cp=0.0;
					if(rho!=0){
						cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
						cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
					}
					double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
					double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
					double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
					// userbc
					double molarmass = molmass;
					int l=lx1*iy+ix;;// this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha

					if(fabs(vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix]) > 0.0000000001){
						flux[(iwp-1)+(iux-1)*lxz2ldimlelt+id] = ux;
						flux[(iwp-1)+(iuy-1)*lxz2ldimlelt+id] = uy;
						flux[(iwp-1)+(iuz-1)*lxz2ldimlelt+id] = uz;
						flux[(iwp-1)+(iph-1)*lxz2ldimlelt+id] = phi;
						flux[(iwp-1)+(ithm-1)*lxz2ldimlelt+id] = temp;
						flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id] = flux[(iwm-1)+(iu1-1)*lxz2ldimlelt+id];// can remove later and just muliitply with followings. adeesha.
						flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*ux;
						flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id+l] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uy;
						flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id] = flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*uz;

						if(cb1=='W'){

							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id] = phi*flux[(iwm-1)+(icvf-1)*lxz2ldimlelt+id]*temp+0.5/flux[(iwp-1)+(iu1-1)*lxz2ldimlelt+id]*( (flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu2-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu3-1)*lxz2ldimlelt+id])+(flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]*flux[(iwp-1)+(iu4-1)*lxz2ldimlelt+id]));
						}
						else if(cb1=='I'){
							flux[(iwp-1)+(iu5-1)*lxz2ldimlelt+id]=flux[(iwm-1)+(iu5-1)*lxz2ldimlelt+id];
						}

					}
					else{
						for(int m=0;m<nqq;m++){
							flux[(iwp-1)+m*lxz2ldimlelt+id]= flux[(iwm-1)+m*lxz2ldimlelt+id];
						}

					}



				}
				//			__syncthreads();// double  check  whether this is needed.  adeesha
				int iy=0;
				int iz=i2;
				int ix=i1;
				for(int ivar=0;ivar<toteq;ivar++){
					flux[(iuj-1)+ivar*lxz2ldimlelt+id] = flux[(iwm-1)+ivar*lxz2ldimlelt+id]-flux[(iwp-1)+ivar*lxz2ldimlelt+id];
				}


			}

		}
	}
}


extern "C" void imqqtu_dirichlet_gpu_wrapper_(int *glbblockSize2,double *d_flux, int *ifield,  int *ilam, int *irho, int *icv, int *icp, int *imu, double *molmass, int *iwp, int *iwm, int *iuj, int *iux,int *iuy,int *iuz, int *iph, int *ithm, int *iu1, int *iu2, int *iu3, int *iu4, int *iu5, int *icvf,int *toteq,int *lx1,int *ly1,int *lz1, char *d_cbc, int *d_lglel, double *d_xm1,double *d_ym1, double *d_zm1, double *d_vx, double *d_vy, double *d_vz, double *d_t, double *d_pr, double *d_sii, double *d_siii, double *d_vdiff, double *d_vtrans, char *d_cb, double *d_u, double *d_phig, double *d_pres, double *d_csound, int *ldim, int *lelt, int *nelt,int *npscal, double *p0th,int *nqq  ){

	hipError_t code1 = hipPeekAtLastError();

	printf("CUDA: Start imqqtu_dirichlet_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));

	printf("CUDA: Start imqqtu_dirichlet_gpu_wrapper values ifield=%d,ilam=%d,irho=%d,icv=%d,icp=%d,imu=%d,molmass=%lf,iwp=%d,iwm=%d,iuj=%d,iux=%d,iuy=%d,iuz=%d,iph=%d,ithm=%d,iu1=%d,iu2=%d,iu3=%d,iu4=%d,iu5=%d,icvf=%d,toteq=%d,lx1=%d,ly1=%d,lz1=%d,ldim=%d,lelt=%d,nelt=%d,npscal=%d,p0th=%lf,nqq=%d,\n",ifield[0],ilam[0],irho[0],icv[0],icp[0],imu[0],molmass[0],iwp[0],iwm[0],iuj[0],iux[0],iuy[0],iuz[0],iph[0],ithm[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],icvf[0],toteq[0],lx1[0],ly1[0],lz1[0],ldim[0],lelt[0],nelt[0],npscal[0],p0th[0],nqq[0]);

	int lxz2ldim = lx1[0]*lz1[0]*2*ldim[0];
	int nxyz = lx1[0]*ly1[0]*lz1[0];
	int lxy = lx1[0]*ly1[0];
	int lxz = lx1[0]*lz1[0];
	int ntot = nelt[0]*lxz2ldim;
	int lxz2ldimlelt = lxz2ldim*lelt[0];
	int ltot= lxz2ldim*lelt[0];
	int e_offset=toteq[0]*nxyz;
	int  nlel= nxyz*lelt[0];

	int a2ldim= 2*ldim[0];
	int blockSize = glbblockSize2[0], gridSize;
	gridSize = (int)ceil((float)ntot/blockSize);


	imqqtu_dirichlet_gpu_kernel<<<gridSize, blockSize>>>(d_flux, ntot, ifield[0], ltot,ilam[0],irho[0],icv[0],icp[0],imu[0],molmass[0],iwp[0],iwm[0],iuj[0],iux[0],iuy[0],iuz[0],iph[0],ithm[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],icvf[0],toteq[0],lx1[0],ly1[0],lz1[0],lxy,lxz,nxyz,lxz2ldim,lxz2ldimlelt,a2ldim,d_cbc, d_lglel,d_xm1,d_ym1, d_zm1, d_vx,d_vy,d_vz,d_t,d_pr,d_sii,d_siii,d_vdiff,d_vtrans, d_cb,d_u, d_phig,d_pres,d_csound,npscal[0],p0th[0],e_offset,nlel,nqq[0] );

	hipError_t code2 = hipPeekAtLastError();

	printf("CUDA: End imqqtu_dirichlet_gpu_wrapper cuda status: %s\n",hipGetErrorString(code2));


}


	.text
	.file	"diffusive_cmt_cuda.hip"
	.globl	_Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii # -- Begin function _Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.type	_Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii,@function
_Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii: # @_Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$528, %rsp                      # imm = 0x210
	.cfi_def_cfa_offset 576
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	80(%rsp), %r11
	movq	%rsi, (%r11)
	leaq	72(%rsp), %r14
	movq	%rdx, (%r14)
	leaq	64(%rsp), %r15
	movq	%rcx, (%r15)
	leaq	4(%rsp), %r12
	movl	%r8d, (%r12)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	56(%rsp), %rdi
	movsd	%xmm0, (%rdi)
	leaq	48(%rsp), %rax
	movsd	%xmm1, (%rax)
	leaq	40(%rsp), %rcx
	movsd	%xmm2, (%rcx)
	leaq	32(%rsp), %rdx
	movsd	%xmm3, (%rdx)
	leaq	24(%rsp), %rsi
	movsd	%xmm4, (%rsi)
	leaq	128(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%r11, 8(%rbx)
	movq	%r14, 16(%rbx)
	movq	%r15, 24(%rbx)
	movq	%r12, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	576(%rsp), %r8
	movq	%r8, 48(%rbx)
	leaq	584(%rsp), %r8
	movq	%r8, 56(%rbx)
	leaq	592(%rsp), %r8
	movq	%r8, 64(%rbx)
	leaq	600(%rsp), %r8
	movq	%r8, 72(%rbx)
	leaq	608(%rsp), %r8
	movq	%r8, 80(%rbx)
	leaq	616(%rsp), %r8
	movq	%r8, 88(%rbx)
	leaq	624(%rsp), %r8
	movq	%r8, 96(%rbx)
	leaq	632(%rsp), %r8
	movq	%r8, 104(%rbx)
	leaq	640(%rsp), %r8
	movq	%r8, 112(%rbx)
	leaq	648(%rsp), %r8
	movq	%r8, 120(%rbx)
	leaq	656(%rsp), %r8
	movq	%r8, 128(%rbx)
	leaq	664(%rsp), %r8
	movq	%r8, 136(%rbx)
	leaq	672(%rsp), %r8
	movq	%r8, 144(%rbx)
	leaq	680(%rsp), %r8
	movq	%r8, 152(%rbx)
	leaq	688(%rsp), %r8
	movq	%r8, 160(%rbx)
	leaq	696(%rsp), %r8
	movq	%r8, 168(%rbx)
	leaq	704(%rsp), %r8
	movq	%r8, 176(%rbx)
	leaq	712(%rsp), %r8
	movq	%r8, 184(%rbx)
	leaq	720(%rsp), %r8
	movq	%r8, 192(%rbx)
	leaq	728(%rsp), %r8
	movq	%r8, 200(%rbx)
	leaq	736(%rsp), %r8
	movq	%r8, 208(%rbx)
	leaq	744(%rsp), %r8
	movq	%r8, 216(%rbx)
	movq	%rdi, 224(%rbx)
	leaq	752(%rsp), %rdi
	movq	%rdi, 232(%rbx)
	leaq	760(%rsp), %rdi
	movq	%rdi, 240(%rbx)
	leaq	768(%rsp), %rdi
	movq	%rdi, 248(%rbx)
	leaq	776(%rsp), %rdi
	movq	%rdi, 256(%rbx)
	leaq	784(%rsp), %rdi
	movq	%rdi, 264(%rbx)
	leaq	792(%rsp), %rdi
	movq	%rdi, 272(%rbx)
	leaq	800(%rsp), %rdi
	movq	%rdi, 280(%rbx)
	leaq	808(%rsp), %rdi
	movq	%rdi, 288(%rbx)
	leaq	816(%rsp), %rdi
	movq	%rdi, 296(%rbx)
	leaq	824(%rsp), %rdi
	movq	%rdi, 304(%rbx)
	movq	%rax, 312(%rbx)
	movq	%rcx, 320(%rbx)
	movq	%rdx, 328(%rbx)
	movq	%rsi, 336(%rbx)
	leaq	832(%rsp), %rax
	movq	%rax, 344(%rbx)
	leaq	840(%rsp), %rax
	movq	%rax, 352(%rbx)
	leaq	848(%rsp), %rax
	movq	%rax, 360(%rbx)
	leaq	856(%rsp), %rax
	movq	%rax, 368(%rbx)
	leaq	864(%rsp), %rax
	movq	%rax, 376(%rbx)
	leaq	872(%rsp), %rax
	movq	%rax, 384(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$544, %rsp                      # imm = 0x220
	.cfi_adjust_cfa_offset -544
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii, .Lfunc_end0-_Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.cfi_endproc
                                        # -- End function
	.globl	compute_transport_props_gpu_wrapper_ # -- Begin function compute_transport_props_gpu_wrapper_
	.type	compute_transport_props_gpu_wrapper_,@function
compute_transport_props_gpu_wrapper_:   # @compute_transport_props_gpu_wrapper_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$456, %rsp                      # imm = 0x1C8
	.cfi_def_cfa_offset 512
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 112(%rsp)                  # 8-byte Spill
	movq	%r8, 248(%rsp)                  # 8-byte Spill
	movq	%rcx, 240(%rsp)                 # 8-byte Spill
	movq	%rdx, 232(%rsp)                 # 8-byte Spill
	movq	%rsi, 224(%rsp)                 # 8-byte Spill
	movq	%rdi, 448(%rsp)                 # 8-byte Spill
	movq	824(%rsp), %rax
	movq	%rax, 168(%rsp)                 # 8-byte Spill
	movq	816(%rsp), %rax
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	movq	808(%rsp), %rax
	movq	%rax, 256(%rsp)                 # 8-byte Spill
	movq	800(%rsp), %rax
	movq	%rax, 264(%rsp)                 # 8-byte Spill
	movq	792(%rsp), %rax
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movq	784(%rsp), %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	776(%rsp), %rax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	768(%rsp), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	760(%rsp), %rax
	movq	%rax, 152(%rsp)                 # 8-byte Spill
	movq	752(%rsp), %rax
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movq	744(%rsp), %rax
	movq	%rax, 272(%rsp)                 # 8-byte Spill
	movq	736(%rsp), %rax
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	movq	728(%rsp), %rax
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movq	720(%rsp), %rax
	movq	%rax, 280(%rsp)                 # 8-byte Spill
	movq	712(%rsp), %rax
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movq	704(%rsp), %rax
	movq	%rax, 288(%rsp)                 # 8-byte Spill
	movq	696(%rsp), %rax
	movq	%rax, 296(%rsp)                 # 8-byte Spill
	movq	688(%rsp), %rax
	movq	%rax, 304(%rsp)                 # 8-byte Spill
	movq	680(%rsp), %rax
	movq	%rax, 128(%rsp)                 # 8-byte Spill
	movq	672(%rsp), %rax
	movq	%rax, 312(%rsp)                 # 8-byte Spill
	movq	664(%rsp), %rax
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movq	656(%rsp), %rax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	648(%rsp), %rax
	movq	%rax, 320(%rsp)                 # 8-byte Spill
	movq	640(%rsp), %rax
	movq	%rax, 328(%rsp)                 # 8-byte Spill
	movq	632(%rsp), %rax
	movq	%rax, 336(%rsp)                 # 8-byte Spill
	movq	624(%rsp), %rax
	movq	%rax, 344(%rsp)                 # 8-byte Spill
	movq	616(%rsp), %rax
	movq	%rax, 352(%rsp)                 # 8-byte Spill
	movq	608(%rsp), %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	600(%rsp), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	592(%rsp), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	584(%rsp), %rax
	movq	%rax, 360(%rsp)                 # 8-byte Spill
	movq	576(%rsp), %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	568(%rsp), %rax
	movq	%rax, 368(%rsp)                 # 8-byte Spill
	movq	560(%rsp), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	552(%rsp), %r15
	movq	544(%rsp), %rbx
	movq	536(%rsp), %r14
	movq	528(%rsp), %r13
	movq	520(%rsp), %r12
	movq	512(%rsp), %rbp
	movq	832(%rsp), %rax
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	callq	hipPeekAtLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movq	112(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %esi
	movq	%rbp, 176(%rsp)                 # 8-byte Spill
	movl	(%rbp), %edx
	movq	%r12, 184(%rsp)                 # 8-byte Spill
	movl	(%r12), %ecx
	movq	%r13, 192(%rsp)                 # 8-byte Spill
	movl	(%r13), %r8d
	movq	%r14, 200(%rsp)                 # 8-byte Spill
	movl	(%r14), %r9d
	movq	%rbx, 208(%rsp)                 # 8-byte Spill
	movl	(%rbx), %ebx
	movq	%r15, 216(%rsp)                 # 8-byte Spill
	movl	(%r15), %eax
	movq	%rax, 440(%rsp)                 # 8-byte Spill
	movq	32(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 432(%rsp)                 # 8-byte Spill
	movq	40(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 424(%rsp)                 # 8-byte Spill
	movq	8(%rsp), %rax                   # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 416(%rsp)                 # 8-byte Spill
	movq	16(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 408(%rsp)                 # 8-byte Spill
	movq	24(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 400(%rsp)                 # 8-byte Spill
	movq	64(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 392(%rsp)                 # 8-byte Spill
	movq	80(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 384(%rsp)                 # 8-byte Spill
	movq	128(%rsp), %rax                 # 8-byte Reload
	movsd	(%rax), %xmm0                   # xmm0 = mem[0],zero
	movq	96(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 376(%rsp)                 # 8-byte Spill
	movq	48(%rsp), %rax                  # 8-byte Reload
	movsd	(%rax), %xmm1                   # xmm1 = mem[0],zero
	movq	56(%rsp), %rax                  # 8-byte Reload
	movsd	(%rax), %xmm2                   # xmm2 = mem[0],zero
	movq	72(%rsp), %rax                  # 8-byte Reload
	movsd	(%rax), %xmm3                   # xmm3 = mem[0],zero
	movq	88(%rsp), %rax                  # 8-byte Reload
	movsd	(%rax), %xmm4                   # xmm4 = mem[0],zero
	movq	104(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r15d
	movq	136(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r12d
	movq	144(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r13d
	movq	152(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %ebp
	movq	160(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r14d
	movq	168(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r10d
	movq	120(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r11d
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$.L.str.1, %edi
	movb	$5, %al
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	movq	144(%rsp), %r14                 # 8-byte Reload
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	440(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	456(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	472(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	488(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	504(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	520(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	536(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	552(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	568(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	printf
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	movq	448(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %ebx
	movq	16(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r12d
	movq	8(%rsp), %rax                   # 8-byte Reload
	imull	(%rax), %r12d
	movq	24(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %ebp
	imull	%r12d, %ebp
	movl	(%r14), %r13d
	imull	%ebp, %r13d
	movq	120(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r15d
	cvtsi2ss	%r13d, %xmm0
	cvtsi2ss	%ebx, %xmm1
	divss	%xmm1, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %edi
	btsq	$32, %rdi
	btsq	$32, %rbx
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	128(%rsp), %rax                 # 8-byte Reload
	movsd	(%rax), %xmm0                   # xmm0 = mem[0],zero
	movq	48(%rsp), %rax                  # 8-byte Reload
	movsd	(%rax), %xmm1                   # xmm1 = mem[0],zero
	movq	56(%rsp), %rax                  # 8-byte Reload
	movsd	(%rax), %xmm2                   # xmm2 = mem[0],zero
	movq	72(%rsp), %rax                  # 8-byte Reload
	movsd	(%rax), %xmm3                   # xmm3 = mem[0],zero
	movq	88(%rsp), %rax                  # 8-byte Reload
	movsd	(%rax), %xmm4                   # xmm4 = mem[0],zero
	imull	%ebp, %r15d
	movl	(%r14), %r8d
	movq	176(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	movq	184(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	movq	192(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movq	200(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	208(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	216(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	32(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	40(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	8(%rsp), %rax                   # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	16(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	24(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	64(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	80(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movq	96(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movq	104(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movq	136(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	144(%rsp), %rcx                 # 8-byte Reload
	movl	(%rcx), %r10d
	movq	152(%rsp), %rcx                 # 8-byte Reload
	movl	(%rcx), %r11d
	movq	160(%rsp), %rcx                 # 8-byte Reload
	movl	(%rcx), %r14d
	movq	168(%rsp), %rcx                 # 8-byte Reload
	movl	(%rcx), %ebx
	movq	224(%rsp), %rdi                 # 8-byte Reload
	movq	232(%rsp), %rsi                 # 8-byte Reload
	movq	240(%rsp), %rdx                 # 8-byte Reload
	movq	248(%rsp), %rcx                 # 8-byte Reload
	movl	%ebp, %r9d
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	288(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	304(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	336(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	368(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	192(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	392(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	408(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	424(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	440(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	216(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	208(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	472(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	488(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	504(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	520(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	536(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	216(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	216(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	216(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	576(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	264(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	600(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	272(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	296(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	312(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	336(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	360(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	392(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	408(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	callq	_Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	addq	$304, %rsp                      # imm = 0x130
	.cfi_adjust_cfa_offset -304
.LBB1_2:
	callq	hipPeekAtLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.2, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	addq	$456, %rsp                      # imm = 0x1C8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.Lfunc_end1:
	.size	compute_transport_props_gpu_wrapper_, .Lfunc_end1-compute_transport_props_gpu_wrapper_
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__imqqtu_gpu_kernelPdiiiiii # -- Begin function _Z32__device_stub__imqqtu_gpu_kernelPdiiiiii
	.type	_Z32__device_stub__imqqtu_gpu_kernelPdiiiiii,@function
_Z32__device_stub__imqqtu_gpu_kernelPdiiiiii: # @_Z32__device_stub__imqqtu_gpu_kernelPdiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17imqqtu_gpu_kernelPdiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__imqqtu_gpu_kernelPdiiiiii, .Lfunc_end2-_Z32__device_stub__imqqtu_gpu_kernelPdiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	imqqtu_gpu_wrapper_             # -- Begin function imqqtu_gpu_wrapper_
	.type	imqqtu_gpu_wrapper_,@function
imqqtu_gpu_wrapper_:                    # @imqqtu_gpu_wrapper_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 56(%rsp)                   # 8-byte Spill
	movq	%r8, %r15
	movq	%rcx, %rbp
	movq	%rdx, %r14
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	movq	168(%rsp), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	160(%rsp), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	152(%rsp), %rbx
	movq	144(%rsp), %r12
	movq	136(%rsp), %r13
	movq	128(%rsp), %rax
	movq	%rax, (%rsp)                    # 8-byte Spill
	callq	hipDeviceSynchronize
	callq	hipPeekAtLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.3, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movq	%r14, 24(%rsp)                  # 8-byte Spill
	movl	(%r14), %esi
	movq	%rbp, 32(%rsp)                  # 8-byte Spill
	movl	(%rbp), %edx
	movq	%r15, 48(%rsp)                  # 8-byte Spill
	movl	(%r15), %ecx
	movq	56(%rsp), %r14                  # 8-byte Reload
	movl	(%r14), %r8d
	movq	(%rsp), %rax                    # 8-byte Reload
	movl	(%rax), %r9d
	movl	(%r13), %eax
	movq	%rax, (%rsp)                    # 8-byte Spill
	movl	(%r12), %r11d
	movl	(%rbx), %r10d
	movq	8(%rsp), %rax                   # 8-byte Reload
	movl	(%rax), %r15d
	movq	16(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %ebp
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	printf
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
	movl	(%r14), %ebp
	imull	(%r13), %ebp
	imull	(%r12), %ebp
	addl	%ebp, %ebp
	movl	(%rbx), %r14d
	imull	%ebp, %r14d
	movq	8(%rsp), %rax                   # 8-byte Reload
	movl	(%rax), %r15d
	movq	16(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %ebx
	imull	%r14d, %ebx
	movq	64(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r13d
	cvtsi2ss	%ebx, %xmm0
	cvtsi2ss	%r13d, %xmm1
	divss	%xmm1, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %edi
	btsq	$32, %rdi
	btsq	$32, %r13
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	imull	%r15d, %ebp
	movq	24(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %ecx
	movq	32(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r8d
	movq	48(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r9d
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	%r14d, %esi
	movl	%ebp, %edx
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	callq	_Z32__device_stub__imqqtu_gpu_kernelPdiiiiii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB3_2:
	callq	hipPeekAtLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.Lfunc_end3:
	.size	imqqtu_gpu_wrapper_, .Lfunc_end3-imqqtu_gpu_wrapper_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii # -- Begin function _Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.type	_Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii,@function
_Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii: # @_Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$560, %rsp                      # imm = 0x230
	.cfi_def_cfa_offset 608
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	48(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	40(%rsp), %rax
	movsd	%xmm1, (%rax)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	608(%rsp), %rcx
	movq	%rcx, 48(%rbx)
	leaq	616(%rsp), %rcx
	movq	%rcx, 56(%rbx)
	leaq	624(%rsp), %rcx
	movq	%rcx, 64(%rbx)
	movq	%r9, 72(%rbx)
	leaq	632(%rsp), %rcx
	movq	%rcx, 80(%rbx)
	leaq	640(%rsp), %rcx
	movq	%rcx, 88(%rbx)
	leaq	648(%rsp), %rcx
	movq	%rcx, 96(%rbx)
	leaq	656(%rsp), %rcx
	movq	%rcx, 104(%rbx)
	leaq	664(%rsp), %rcx
	movq	%rcx, 112(%rbx)
	leaq	672(%rsp), %rcx
	movq	%rcx, 120(%rbx)
	leaq	680(%rsp), %rcx
	movq	%rcx, 128(%rbx)
	leaq	688(%rsp), %rcx
	movq	%rcx, 136(%rbx)
	leaq	696(%rsp), %rcx
	movq	%rcx, 144(%rbx)
	leaq	704(%rsp), %rcx
	movq	%rcx, 152(%rbx)
	leaq	712(%rsp), %rcx
	movq	%rcx, 160(%rbx)
	leaq	720(%rsp), %rcx
	movq	%rcx, 168(%rbx)
	leaq	728(%rsp), %rcx
	movq	%rcx, 176(%rbx)
	leaq	736(%rsp), %rcx
	movq	%rcx, 184(%rbx)
	leaq	744(%rsp), %rcx
	movq	%rcx, 192(%rbx)
	leaq	752(%rsp), %rcx
	movq	%rcx, 200(%rbx)
	leaq	760(%rsp), %rcx
	movq	%rcx, 208(%rbx)
	leaq	768(%rsp), %rcx
	movq	%rcx, 216(%rbx)
	leaq	776(%rsp), %rcx
	movq	%rcx, 224(%rbx)
	leaq	784(%rsp), %rcx
	movq	%rcx, 232(%rbx)
	leaq	792(%rsp), %rcx
	movq	%rcx, 240(%rbx)
	leaq	800(%rsp), %rcx
	movq	%rcx, 248(%rbx)
	leaq	808(%rsp), %rcx
	movq	%rcx, 256(%rbx)
	leaq	816(%rsp), %rcx
	movq	%rcx, 264(%rbx)
	leaq	824(%rsp), %rcx
	movq	%rcx, 272(%rbx)
	leaq	832(%rsp), %rcx
	movq	%rcx, 280(%rbx)
	leaq	840(%rsp), %rcx
	movq	%rcx, 288(%rbx)
	leaq	848(%rsp), %rcx
	movq	%rcx, 296(%rbx)
	leaq	856(%rsp), %rcx
	movq	%rcx, 304(%rbx)
	leaq	864(%rsp), %rcx
	movq	%rcx, 312(%rbx)
	leaq	872(%rsp), %rcx
	movq	%rcx, 320(%rbx)
	leaq	880(%rsp), %rcx
	movq	%rcx, 328(%rbx)
	leaq	888(%rsp), %rcx
	movq	%rcx, 336(%rbx)
	leaq	896(%rsp), %rcx
	movq	%rcx, 344(%rbx)
	leaq	904(%rsp), %rcx
	movq	%rcx, 352(%rbx)
	leaq	912(%rsp), %rcx
	movq	%rcx, 360(%rbx)
	leaq	920(%rsp), %rcx
	movq	%rcx, 368(%rbx)
	leaq	928(%rsp), %rcx
	movq	%rcx, 376(%rbx)
	leaq	936(%rsp), %rcx
	movq	%rcx, 384(%rbx)
	leaq	944(%rsp), %rcx
	movq	%rcx, 392(%rbx)
	leaq	952(%rsp), %rcx
	movq	%rcx, 400(%rbx)
	leaq	960(%rsp), %rcx
	movq	%rcx, 408(%rbx)
	leaq	968(%rsp), %rcx
	movq	%rcx, 416(%rbx)
	leaq	976(%rsp), %rcx
	movq	%rcx, 424(%rbx)
	movq	%rax, 432(%rbx)
	leaq	984(%rsp), %rax
	movq	%rax, 440(%rbx)
	leaq	992(%rsp), %rax
	movq	%rax, 448(%rbx)
	leaq	1000(%rsp), %rax
	movq	%rax, 456(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$576, %rsp                      # imm = 0x240
	.cfi_adjust_cfa_offset -576
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii, .Lfunc_end4-_Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.cfi_endproc
                                        # -- End function
	.globl	imqqtu_dirichlet_gpu_wrapper_   # -- Begin function imqqtu_dirichlet_gpu_wrapper_
	.type	imqqtu_dirichlet_gpu_wrapper_,@function
imqqtu_dirichlet_gpu_wrapper_:          # @imqqtu_dirichlet_gpu_wrapper_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$552, %rsp                      # imm = 0x228
	.cfi_def_cfa_offset 608
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 176(%rsp)                  # 8-byte Spill
	movq	%r8, 168(%rsp)                  # 8-byte Spill
	movq	%rcx, 160(%rsp)                 # 8-byte Spill
	movq	%rdx, 152(%rsp)                 # 8-byte Spill
	movq	%rsi, 272(%rsp)                 # 8-byte Spill
	movq	%rdi, 192(%rsp)                 # 8-byte Spill
	movq	968(%rsp), %rax
	movq	%rax, 216(%rsp)                 # 8-byte Spill
	movq	960(%rsp), %rax
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	movq	952(%rsp), %rax
	movq	%rax, 208(%rsp)                 # 8-byte Spill
	movq	920(%rsp), %rax
	movq	%rax, 280(%rsp)                 # 8-byte Spill
	movq	912(%rsp), %rax
	movq	%rax, 288(%rsp)                 # 8-byte Spill
	movq	904(%rsp), %rax
	movq	%rax, 296(%rsp)                 # 8-byte Spill
	movq	896(%rsp), %rax
	movq	%rax, 304(%rsp)                 # 8-byte Spill
	movq	888(%rsp), %rax
	movq	%rax, 312(%rsp)                 # 8-byte Spill
	movq	880(%rsp), %rax
	movq	%rax, 320(%rsp)                 # 8-byte Spill
	movq	872(%rsp), %rax
	movq	%rax, 328(%rsp)                 # 8-byte Spill
	movq	864(%rsp), %rax
	movq	%rax, 336(%rsp)                 # 8-byte Spill
	movq	856(%rsp), %rax
	movq	%rax, 344(%rsp)                 # 8-byte Spill
	movq	848(%rsp), %rax
	movq	%rax, 352(%rsp)                 # 8-byte Spill
	movq	840(%rsp), %rax
	movq	%rax, 360(%rsp)                 # 8-byte Spill
	movq	832(%rsp), %rax
	movq	%rax, 368(%rsp)                 # 8-byte Spill
	movq	824(%rsp), %rax
	movq	%rax, 376(%rsp)                 # 8-byte Spill
	movq	816(%rsp), %rax
	movq	%rax, 384(%rsp)                 # 8-byte Spill
	movq	808(%rsp), %rax
	movq	%rax, 392(%rsp)                 # 8-byte Spill
	movq	800(%rsp), %rax
	movq	%rax, 400(%rsp)                 # 8-byte Spill
	movq	792(%rsp), %rax
	movq	%rax, 408(%rsp)                 # 8-byte Spill
	movq	784(%rsp), %rax
	movq	%rax, 416(%rsp)                 # 8-byte Spill
	movq	776(%rsp), %rax
	movq	%rax, 424(%rsp)                 # 8-byte Spill
	movq	768(%rsp), %rax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	760(%rsp), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	752(%rsp), %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	744(%rsp), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	736(%rsp), %rax
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movq	728(%rsp), %rax
	movq	%rax, 128(%rsp)                 # 8-byte Spill
	movq	720(%rsp), %rax
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	movq	712(%rsp), %rax
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	movq	704(%rsp), %rax
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movq	696(%rsp), %rax
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movq	688(%rsp), %rax
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movq	680(%rsp), %rax
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movq	672(%rsp), %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	664(%rsp), %rax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	656(%rsp), %rax
	movq	%rax, 200(%rsp)                 # 8-byte Spill
	movq	648(%rsp), %rbx
	movq	640(%rsp), %r13
	movq	632(%rsp), %r14
	movq	624(%rsp), %r12
	movq	616(%rsp), %rbp
	movq	608(%rsp), %r15
	movq	944(%rsp), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	936(%rsp), %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	928(%rsp), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	callq	hipPeekAtLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.6, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movq	152(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %esi
	movq	160(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %edx
	movq	168(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %ecx
	movq	176(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r8d
	movq	%r15, 232(%rsp)                 # 8-byte Spill
	movl	(%r15), %r9d
	movq	%rbp, 240(%rsp)                 # 8-byte Spill
	movl	(%rbp), %eax
	movq	%rax, 184(%rsp)                 # 8-byte Spill
	movq	%r12, 224(%rsp)                 # 8-byte Spill
	movsd	(%r12), %xmm0                   # xmm0 = mem[0],zero
	movq	%r14, 248(%rsp)                 # 8-byte Spill
	movl	(%r14), %eax
	movq	%rax, 544(%rsp)                 # 8-byte Spill
	movq	%r13, 256(%rsp)                 # 8-byte Spill
	movl	(%r13), %eax
	movq	%rax, 536(%rsp)                 # 8-byte Spill
	movq	%rbx, 264(%rsp)                 # 8-byte Spill
	movl	(%rbx), %eax
	movq	%rax, 528(%rsp)                 # 8-byte Spill
	movq	200(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 520(%rsp)                 # 8-byte Spill
	movq	64(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 512(%rsp)                 # 8-byte Spill
	movq	72(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 504(%rsp)                 # 8-byte Spill
	movq	80(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 496(%rsp)                 # 8-byte Spill
	movq	88(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 488(%rsp)                 # 8-byte Spill
	movq	96(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 480(%rsp)                 # 8-byte Spill
	movq	136(%rsp), %rax                 # 8-byte Reload
	movsd	(%rax), %xmm1                   # xmm1 = mem[0],zero
	movq	104(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 472(%rsp)                 # 8-byte Spill
	movq	112(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 464(%rsp)                 # 8-byte Spill
	movq	120(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 456(%rsp)                 # 8-byte Spill
	movq	128(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 448(%rsp)                 # 8-byte Spill
	movq	144(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 440(%rsp)                 # 8-byte Spill
	movq	32(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 432(%rsp)                 # 8-byte Spill
	movq	40(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r12d
	movq	48(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r13d
	movq	56(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %ebp
	movq	8(%rsp), %rax                   # 8-byte Reload
	movl	(%rax), %r10d
	movq	24(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r14d
	movq	16(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r11d
	movq	208(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %ebx
	movq	216(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r15d
	movl	$.L.str.7, %edi
	movb	$2, %al
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	496(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	512(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	528(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	544(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	560(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	576(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	592(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	608(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	624(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	640(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	656(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	672(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	688(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	704(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	720(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	368(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	printf
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	movq	40(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %ebx
	movq	56(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r13d
	movq	%r13, 184(%rsp)                 # 8-byte Spill
                                        # kill: def $r13d killed $r13d killed $r13 def $r13
	imull	%ebx, %r13d
	movq	8(%rsp), %rax                   # 8-byte Reload
	movl	(%rax), %eax
	movl	%r13d, %r12d
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	imull	%eax, %r12d
	addl	%r12d, %r12d
	movq	48(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r15d
	movq	16(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %r14d
	imull	%r12d, %r14d
	movq	24(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	32(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	192(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %ebp
	cvtsi2ss	%r14d, %xmm0
	cvtsi2ss	%ebp, %xmm1
	divss	%xmm1, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %edi
	btsq	$32, %rdi
	btsq	$32, %rbp
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	imull	%ebx, %r15d
	movq	%r15, %rcx
	movq	%r15, 192(%rsp)                 # 8-byte Spill
	movq	224(%rsp), %rax                 # 8-byte Reload
	movsd	(%rax), %xmm0                   # xmm0 = mem[0],zero
	movq	136(%rsp), %rax                 # 8-byte Reload
	movsd	(%rax), %xmm1                   # xmm1 = mem[0],zero
	movq	8(%rsp), %rax                   # 8-byte Reload
	addl	%eax, %eax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	184(%rsp), %r15                 # 8-byte Reload
	imull	%ecx, %r15d
	movl	%r15d, %ebx
	movq	24(%rsp), %rbp                  # 8-byte Reload
	imull	%ebp, %ebx
	movq	16(%rsp), %r10                  # 8-byte Reload
	imull	%r15d, %r10d
	imull	%r12d, %ebp
	movq	152(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %edx
	movq	160(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r8d
	movq	168(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %r9d
	movq	176(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	232(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	240(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 176(%rsp)                 # 8-byte Spill
	movq	248(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 168(%rsp)                 # 8-byte Spill
	movq	256(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	movq	264(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 152(%rsp)                 # 8-byte Spill
	movq	200(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	movq	64(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movq	72(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	80(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movq	88(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 88(%rsp)                  # 8-byte Spill
	movq	96(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	movq	104(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movq	112(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	movq	120(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	movq	128(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 128(%rsp)                 # 8-byte Spill
	movq	144(%rsp), %rax                 # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movq	32(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	40(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	48(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	56(%rsp), %rax                  # 8-byte Reload
	movl	(%rax), %eax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	208(%rsp), %rcx                 # 8-byte Reload
	movl	(%rcx), %eax
	movq	216(%rsp), %rcx                 # 8-byte Reload
	movl	(%rcx), %r11d
	movq	272(%rsp), %rdi                 # 8-byte Reload
	movl	%r14d, %esi
	movl	%ebp, %ecx
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	312(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	328(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	344(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	360(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	376(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	392(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	408(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	424(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	440(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	456(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	472(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	488(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	504(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	520(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	536(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	552(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	568(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	584(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	600(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	192(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	416(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	288(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	288(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	288(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	288(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	408(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	480(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	504(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	520(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	536(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	552(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	400(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	416(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	addq	$400, %rsp                      # imm = 0x190
	.cfi_adjust_cfa_offset -400
.LBB5_2:
	callq	hipPeekAtLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.8, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	addq	$552, %rsp                      # imm = 0x228
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.Lfunc_end5:
	.size	imqqtu_dirichlet_gpu_wrapper_, .Lfunc_end5-imqqtu_dirichlet_gpu_wrapper_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17imqqtu_gpu_kernelPdiiiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii,@object # @_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.section	.rodata,"a",@progbits
	.globl	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.p2align	3, 0x0
_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii:
	.quad	_Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.size	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA: Start compute_transport_props_gpu_wrapper cuda status: %s\n"
	.size	.L.str, 65

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"CUDA: Start compute_transport_props_gpu_wrapper values nelt =%d,irpu=%d,irpv=%d,irpw=%d,iret=%d,irg=%d,toteq=%d,if3d=%d,irho=%d,lx1=%d,ly1=%d,lz1=%d,ldimt=%d,npscal=%d,p0th=%lf,ifield=%d,icv=%d,icp=%d,imu=%d,ilam=%d,cpgref=%lf,cvgref=%lf,gmaref=%lf,rgasref=%lf,iknd=%d,inus=%d,lelt=%d ,\n"
	.size	.L.str.1, 288

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"CUDA: End compute_transport_props_gpu_wrapper cuda status: %s\n"
	.size	.L.str.2, 63

	.type	_Z17imqqtu_gpu_kernelPdiiiiii,@object # @_Z17imqqtu_gpu_kernelPdiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z17imqqtu_gpu_kernelPdiiiiii
	.p2align	3, 0x0
_Z17imqqtu_gpu_kernelPdiiiiii:
	.quad	_Z32__device_stub__imqqtu_gpu_kernelPdiiiiii
	.size	_Z17imqqtu_gpu_kernelPdiiiiii, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"CUDA: Start imqqtu_gpu_wrapper cuda status: %s\n"
	.size	.L.str.3, 48

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"CUDA: Start imqqtu_gpu_wrapper values iuj =%d ,ium=%d,iup=%d,lx1=%d,ly1=%d,lz1=%d,ldim=%d,nelt=%d,lelt=%d,toteq=%d\n"
	.size	.L.str.4, 116

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"CUDA: End imqqtu_gpu_wrapper cuda status: %s\n"
	.size	.L.str.5, 46

	.type	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii,@object # @_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.section	.rodata,"a",@progbits
	.globl	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.p2align	3, 0x0
_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii:
	.quad	_Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.size	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii, 8

	.type	.L.str.6,@object                # @.str.6
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.6:
	.asciz	"CUDA: Start imqqtu_dirichlet_gpu_wrapper cuda status: %s\n"
	.size	.L.str.6, 58

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"CUDA: Start imqqtu_dirichlet_gpu_wrapper values ifield=%d,ilam=%d,irho=%d,icv=%d,icp=%d,imu=%d,molmass=%lf,iwp=%d,iwm=%d,iuj=%d,iux=%d,iuy=%d,iuz=%d,iph=%d,ithm=%d,iu1=%d,iu2=%d,iu3=%d,iu4=%d,iu5=%d,icvf=%d,toteq=%d,lx1=%d,ly1=%d,lz1=%d,ldim=%d,lelt=%d,nelt=%d,npscal=%d,p0th=%lf,nqq=%d,\n"
	.size	.L.str.7, 289

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"CUDA: End imqqtu_dirichlet_gpu_wrapper cuda status: %s\n"
	.size	.L.str.8, 56

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii"
	.size	.L__unnamed_1, 108

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17imqqtu_gpu_kernelPdiiiiii"
	.size	.L__unnamed_2, 30

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii"
	.size	.L__unnamed_3, 111

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z49__device_stub__compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.addrsig_sym _Z32__device_stub__imqqtu_gpu_kernelPdiiiiii
	.addrsig_sym _Z42__device_stub__imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.addrsig_sym _Z17imqqtu_gpu_kernelPdiiiiii
	.addrsig_sym _Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii ; -- Begin function _Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.globl	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
	.p2align	8
	.type	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii,@function
_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii: ; @_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x13c
	s_load_b64 s[16:17], s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s17, v1
	s_cbranch_execz .LBB0_2
; %bb.1:                                ; %.preheader.preheader
	s_ashr_i32 s2, s16, 31
	v_ashrrev_i32_e32 v5, 31, v1
	s_add_i32 s3, s16, s2
	s_load_b128 s[12:15], s[0:1], 0x60
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v0, s3
	v_add_nc_u32_e32 v3, v1, v5
	s_sub_i32 s4, 0, s3
	v_rcp_iflag_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v3, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s17, s13, 31
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s4, v0
	s_load_b256 s[4:11], s[0:1], 0x110
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_hi_u32 v0, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v0, s3
	v_add_nc_u32_e32 v3, 1, v0
	v_sub_nc_u32_e32 v2, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v4, s3, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_xor_b32_e32 v4, s2, v5
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s3, v2
	s_load_b64 s[2:3], s[0:1], 0x70
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v4
	v_sub_nc_u32_e32 v2, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_mul_lo_u32 v16, v2, s16
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_mul_i32 s2, s13, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	global_load_b32 v3, v[3:4], off
	s_add_i32 s2, s2, s3
	s_xor_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s2
	s_sub_i32 s15, 0, s2
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_ashr_i32 s4, s12, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s12, s4
	global_load_b32 v7, v[3:4], off
	s_xor_b32 s5, s5, s4
	v_mul_lo_u32 v4, s15, v0
	v_cvt_f32_u32_e32 v3, s5
	s_sub_i32 s15, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v3, v3
	v_mul_hi_u32 v4, v0, v4
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v0, v0, v4
	v_xor_b32_e32 v4, s4, v5
	v_xor_b32_e32 v5, s3, v5
	s_add_i32 s4, s13, s17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_hi_u32 v0, v6, v0
	s_xor_b32 s4, s4, s17
	v_cvt_f32_u32_e32 v11, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v8, s15, v3
	s_ashr_i32 s15, s14, 31
	s_add_i32 s14, s14, s15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v12, 1, v0
	s_xor_b32 s3, s14, s15
	v_rcp_iflag_f32_e32 v11, v11
	v_cvt_f32_u32_e32 v10, s3
	v_mul_hi_u32 v8, v3, v8
	s_sub_i32 s13, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v10, v10
	v_add_nc_u32_e32 v3, v3, v8
	v_mul_lo_u32 v8, v0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v6, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v10, 0x4f7ffffe, v10
	v_sub_nc_u32_e32 v8, v6, v8
	v_mul_lo_u32 v9, v3, s5
	v_cmp_le_u32_e32 vcc_lo, s2, v8
	v_cndmask_b32_e32 v0, v0, v12, vcc_lo
	v_add_nc_u32_e32 v12, 1, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v9
	v_subrev_nc_u32_e32 v9, s2, v8
	v_subrev_nc_u32_e32 v13, s5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v8, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v6
	v_add_nc_u32_e32 v9, 1, v0
	v_cmp_le_u32_e64 s2, s2, v8
	v_dual_cndmask_b32 v6, v6, v13 :: v_dual_cndmask_b32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, v0, v9, s2
	v_cmp_le_u32_e32 vcc_lo, s5, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v8, 1, v3
	v_cvt_u32_f32_e32 v9, v10
	v_mul_f32_e32 v10, 0x4f7ffffe, v11
	v_xor_b32_e32 v0, v0, v5
	s_sub_i32 s2, 0, s4
	v_cndmask_b32_e32 v3, v3, v8, vcc_lo
	v_mul_lo_u32 v6, s13, v9
	v_cvt_u32_f32_e32 v8, v10
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v3, v4
	v_mul_lo_u32 v5, s2, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v10, 31, v0
	v_mul_hi_u32 v6, v9, v6
	v_sub_nc_u32_e32 v11, v3, v4
	s_load_b32 s2, s[0:1], 0x50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v0, v10
	v_ashrrev_i32_e32 v3, 31, v11
	v_mul_hi_u32 v4, v8, v5
	v_add_nc_u32_e32 v5, v9, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v0, v0, v10
	v_add_nc_u32_e32 v6, v11, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v5, v0, v5
	v_add_nc_u32_e32 v4, v8, v4
	v_xor_b32_e32 v6, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v4, v6, v4
	v_mul_lo_u32 v5, v5, s3
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, s4
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v5, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	v_sub_nc_u32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_subrev_nc_u32_e32 v5, s4, v4
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v6, s3, v0
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v5, s4, v4
	v_cndmask_b32_e32 v0, v0, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v0, v0, v10
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v10
	v_xor_b32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, s10
	v_sub_nc_u32_e32 v5, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, v5, s12, v[0:1]
	v_mul_lo_u32 v0, v11, s12
	v_mad_u64_u32 v[4:5], null, s2, s11, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, v1, v0
	s_load_b64 s[2:3], s[0:1], 0x48
	v_add3_u32 v0, v4, v16, v17
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, -1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v2, s16
	v_add3_u32 v4, v3, v17, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[4:5], v[4:5], off
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0xe8
	s_load_b64 s[0:1], s[0:1], 0xc0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s2, -1
	s_waitcnt vmcnt(0)
	v_mul_f64 v[4:5], v[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[6:7], 0x3fe80000, v[4:5]
	v_div_scale_f64 v[8:9], null, v[0:1], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_div_scale_f64 v[12:13], vcc_lo, v[6:7], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[14:15], v[12:13], v[10:11]
	v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
	v_mad_u64_u32 v[10:11], null, s2, s11, v[3:4]
	s_add_i32 s2, s3, -1
	v_mad_u64_u32 v[11:12], null, s2, s11, v[3:4]
	v_mul_f64 v[4:5], v[4:5], 0.5
	s_add_i32 s2, s8, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v10, v10, v16, v17
	v_add3_u32 v2, v11, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v11, 31, v10
	v_div_fixup_f64 v[0:1], v[8:9], v[0:1], v[6:7]
	v_lshlrev_b64 v[9:10], 3, v[10:11]
	v_mov_b32_e32 v11, 0
	v_mad_u64_u32 v[12:13], null, s2, s11, v[3:4]
	v_cvt_f64_i32_e32 v[13:14], s8
	s_add_i32 s2, s9, -1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s0, v9
	v_mad_u64_u32 v[6:7], null, s2, s11, v[3:4]
	v_add3_u32 v7, v12, v16, v17
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
	v_mov_b32_e32 v12, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add3_u32 v6, v6, v16, v17
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_lshlrev_b64 v[15:16], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v15, vcc_lo, s0, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s1, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	s_clause 0x3
	global_store_b64 v[9:10], v[4:5], off
	global_store_b64 v[2:3], v[11:12], off
	global_store_b64 v[15:16], v[13:14], off
	global_store_b64 v[6:7], v[0:1], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 560
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii, .Lfunc_end0-_Z34compute_transport_props_gpu_kernelPdS_S_S_iiiiiiiiiiS_iS_iiiPiS_S_S_S_iiS_dS_S_S_iPciiS_iiddddS0_S_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1584
; NumSgprs: 20
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17imqqtu_gpu_kernelPdiiiiii ; -- Begin function _Z17imqqtu_gpu_kernelPdiiiiii
	.globl	_Z17imqqtu_gpu_kernelPdiiiiii
	.p2align	8
	.type	_Z17imqqtu_gpu_kernelPdiiiiii,@function
_Z17imqqtu_gpu_kernelPdiiiiii:          ; @_Z17imqqtu_gpu_kernelPdiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s7, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_add_nc_u32_e32 v6, -1, v1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v0, s5, v6
	v_add_nc_u32_e32 v2, s6, v6
	v_add_nc_u32_e32 v6, s4, v6
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v6
	s_clause 0x1
	global_load_b64 v[4:5], v[0:1], off
	global_load_b64 v[2:3], v[2:3], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[4:5], v[2:3], -0.5
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[2:3], -0.5, v[0:1]
	global_store_b64 v[6:7], v[0:1], off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17imqqtu_gpu_kernelPdiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17imqqtu_gpu_kernelPdiiiiii, .Lfunc_end1-_Z17imqqtu_gpu_kernelPdiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 272
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii ; -- Begin function _Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.globl	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
	.p2align	8
	.type	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii,@function
_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii: ; @_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x154
	s_load_b32 s3, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB2_152
; %bb.1:                                ; %NodeBlock
	s_load_b256 s[20:27], s[0:1], 0x70
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s23, 31
	s_ashr_i32 s6, s25, 31
	s_add_i32 s3, s23, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v0, s4, v3
	s_ashr_i32 s4, s27, 31
	s_add_i32 s5, s27, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_xor_b32 s4, s5, s4
	s_add_i32 s5, s25, s6
	v_cvt_f32_u32_e32 v5, s4
	v_mul_hi_u32 v4, v3, v0
	s_xor_b32 s5, s5, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v7, s5
	v_rcp_iflag_f32_e32 v5, v5
	v_add_nc_u32_e32 v0, v1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_xor_b32_e32 v0, v0, v2
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_mul_lo_u32 v4, v3, s3
	v_add_nc_u32_e32 v6, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v4
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	v_subrev_nc_u32_e32 v8, s3, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_rcp_iflag_f32_e32 v6, v7
	v_cndmask_b32_e32 v4, v4, v8, vcc_lo
	v_xor_b32_e32 v8, s2, v2
	s_sub_i32 s2, 0, s4
	v_add_nc_u32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s3, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v6
	v_mul_lo_u32 v6, s2, v5
	s_sub_i32 s2, 0, s5
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v4, v4
	v_xor_b32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v6, v5, v6
	v_mul_lo_u32 v7, s2, v4
	s_load_b64 s[2:3], s[0:1], 0x90
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, v3, v8
	v_add_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v7, v4, v7
	v_ashrrev_i32_e32 v8, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v4, v7
	v_mul_hi_u32 v4, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v7, 1, v4
	v_add_nc_u32_e32 v3, v3, v8
	v_mul_lo_u32 v6, v4, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v8
	v_mul_hi_u32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v5, s4
	v_sub_nc_u32_e32 v3, v3, v5
	v_sub_nc_u32_e32 v5, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v6, s4, v3
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	v_subrev_nc_u32_e32 v9, s5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v5
	v_subrev_nc_u32_e32 v6, s4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v5, v5, v9
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	v_xor_b32_e32 v9, s6, v2
	v_add_nc_u32_e32 v7, 1, v4
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v3, v8
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v8
	v_xor_b32_e32 v4, v4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, v4, v9
	v_mad_u64_u32 v[4:5], null, v17, 18, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_mov_b32 s2, 0
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_mov_b32 s3, exec_lo
	global_load_u8 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i16_e32 0x4f, v4
	s_xor_b32 s3, exec_lo, s3
; %bb.2:                                ; %LeafBlock2715
	v_cmp_ne_u16_e32 vcc_lo, 0x50, v4
	s_and_b32 s2, vcc_lo, exec_lo
; %bb.3:                                ; %Flow2845
	s_and_not1_saveexec_b32 s3, s3
; %bb.4:                                ; %LeafBlock
	v_cmp_ne_u16_e32 vcc_lo, 0x45, v4
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s4
; %bb.5:                                ; %Flow2846
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_152
; %bb.6:                                ; %NodeBlock2721
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_i16_e32 0x56, v4
	s_xor_b32 s3, exec_lo, s3
; %bb.7:                                ; %LeafBlock2719
	v_cmp_eq_u16_e32 vcc_lo, 0x57, v4
	s_and_b32 s2, vcc_lo, exec_lo
; %bb.8:                                ; %Flow2842
	s_and_not1_saveexec_b32 s3, s3
; %bb.9:                                ; %LeafBlock2717
	v_cmp_eq_u16_e32 vcc_lo, 0x49, v4
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s4
; %bb.10:                               ; %Flow2843
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_152
; %bb.11:                               ; %NodeBlock2735
	s_load_b512 s[4:19], s[0:1], 0x30
	s_mov_b32 s45, 0
	s_mov_b32 s44, 0
	s_mov_b32 s33, 0
	s_mov_b32 s27, exec_lo
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr19
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s19, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s19, s2
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v5, s3
	s_sub_i32 s23, 0, s3
	v_rcp_iflag_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v5, v5
	v_mul_lo_u32 v6, s23, v5
	s_ashr_i32 s23, s21, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s25, s21, s23
	s_xor_b32 s25, s25, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v7, s25
	v_mul_hi_u32 v6, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v7, v7
	v_add_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v0, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	v_mul_lo_u32 v6, v5, s3
	v_sub_nc_u32_e32 v0, v0, v6
	v_add_nc_u32_e32 v6, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	v_dual_cndmask_b32 v5, v5, v6 :: v_dual_cndmask_b32 v0, v0, v8
	v_xor_b32_e32 v8, s2, v2
	s_sub_i32 s2, 0, s25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, 1, v5
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v5, v6, vcc_lo
	v_cvt_u32_f32_e32 v5, v7
	v_xor_b32_e32 v0, v0, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v6, s2, v5
	s_clause 0x5
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b32 s23, s[0:1], 0x14
	s_load_b256 s[36:43], s[0:1], 0xb8
	s_load_b64 s[34:35], s[0:1], 0xf0
	s_load_b64 s[28:29], s[0:1], 0x110
	s_load_b64 s[30:31], s[0:1], 0x13c
	v_cmp_ne_u16_e64 s1, 0x57, v4
	v_sub_nc_u32_e32 v0, v0, v8
	v_cmp_eq_u16_e64 s0, 0x49, v4
	v_mul_hi_u32 v6, v5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v0
	v_add_nc_u32_e32 v8, v0, v7
	v_mul_lo_u32 v0, v0, s19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, v5, v6
	v_xor_b32_e32 v6, v8, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v1, v0
	v_mul_hi_u32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v5, s25
	v_sub_nc_u32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s25, v5
	v_cmp_le_u32_e32 vcc_lo, s25, v5
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s25, v5
	v_cmp_le_u32_e32 vcc_lo, s25, v5
	s_mov_b32 s25, 0
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v7
	v_sub_nc_u32_e32 v16, v5, v7
	v_cmpx_lt_i32_e32 2, v3
	s_xor_b32 s27, exec_lo, s27
	s_cbranch_execz .LBB2_71
; %bb.12:                               ; %NodeBlock2733
	s_mov_b32 s46, 0
	s_mov_b32 s44, exec_lo
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $sgpr48
                                        ; implicit-def: $sgpr49
	v_cmpx_lt_i32_e32 3, v3
	s_xor_b32 s44, exec_lo, s44
	s_cbranch_execz .LBB2_20
; %bb.13:                               ; %NodeBlock2731
	s_mov_b32 s47, exec_lo
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $sgpr48
	v_cmpx_lt_i32_e32 4, v3
	s_xor_b32 s47, exec_lo, s47
	s_cbranch_execz .LBB2_17
; %bb.14:                               ; %LeafBlock2729
	s_mov_b32 s49, exec_lo
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $sgpr48
	v_cmpx_eq_u32_e32 5, v3
	s_cbranch_execz .LBB2_16
; %bb.15:                               ; %..preheader2465.preheader_crit_edge
	s_waitcnt lgkmcnt(0)
	s_add_i32 s48, s23, -1
	s_mov_b32 s33, exec_lo
	v_mul_lo_u32 v18, v17, s24
	s_mul_i32 s48, s48, s30
.LBB2_16:                               ; %Flow2807
	s_or_b32 exec_lo, exec_lo, s49
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s33, s33, exec_lo
.LBB2_17:                               ; %Flow2806
	s_or_saveexec_b32 s47, s47
                                        ; implicit-def: $sgpr49
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 exec_lo, exec_lo, s47
	s_cbranch_execz .LBB2_19
; %bb.18:                               ; %..preheader2474.preheader_crit_edge
	s_waitcnt lgkmcnt(0)
	s_add_i32 s49, s23, -1
	s_mov_b32 s46, exec_lo
	v_mul_lo_u32 v18, v17, s24
	s_mul_i32 s49, s49, s30
.LBB2_19:                               ; %Flow2808
	s_or_b32 exec_lo, exec_lo, s47
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s33, s33, exec_lo
	s_and_b32 s46, s46, exec_lo
.LBB2_20:                               ; %Flow2805
	s_or_saveexec_b32 s47, s44
	v_dual_mov_b32 v20, s48 :: v_dual_mov_b32 v19, s49
                                        ; implicit-def: $sgpr44
	s_xor_b32 exec_lo, exec_lo, s47
	s_cbranch_execz .LBB2_40
; %bb.21:                               ; %..preheader2477.preheader_crit_edge
	v_mul_lo_u32 v18, v17, s24
	v_mul_lo_u32 v4, v16, s22
	v_mul_lo_u32 v5, v0, s19
	s_waitcnt lgkmcnt(0)
	s_add_i32 s44, s23, -1
	s_mov_b32 s48, 0xd9d7bdbb
	s_mul_i32 s44, s44, s30
	s_mov_b32 s49, 0x3ddb7cdf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v4, v4, v5, v18
	v_add_nc_u32_e32 v5, s44, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s34, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s35, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f64_e64 s45, |v[5:6]|, s[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s48, s45
	s_xor_b32 s45, exec_lo, s48
	s_cbranch_execz .LBB2_25
; %bb.22:                               ; %.preheader2475
	s_cmp_lt_i32 s31, 1
                                        ; implicit-def: $vgpr4
	s_cbranch_scc1 .LBB2_25
; %bb.23:                               ; %.lr.ph2483
	v_add_nc_u32_e32 v5, -1, v1
	s_mov_b32 s48, s31
.LBB2_24:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s5, v5
	v_add_nc_u32_e32 v8, s4, v5
	v_add_nc_u32_e32 v5, s26, v5
	s_add_i32 s48, s48, -1
                                        ; implicit-def: $vgpr4
	s_cmp_eq_u32 s48, 0
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[6:7], off
	s_cbranch_scc0 .LBB2_24
.LBB2_25:                               ; %Flow2781
	s_and_not1_saveexec_b32 s45, s45
	s_cbranch_execz .LBB2_35
; %bb.26:
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s49, s14, -1
	s_add_i32 s50, s7, -1
	s_mul_i32 s49, s49, s26
	s_mul_i32 s50, s50, s26
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_ashr_i32 s48, s4, 31
	s_add_i32 s51, s4, s49
	s_ashr_i32 s52, s50, 31
	s_add_u32 s50, s50, s4
	s_addc_u32 s52, s52, s48
	v_add_co_u32 v6, vcc_lo, s28, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s29, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s40, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s41, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s38, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, s39, v5, vcc_lo
	v_add_co_u32 v12, vcc_lo, s36, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, s37, v5, vcc_lo
	v_add_co_u32 v14, vcc_lo, s42, v4
	v_add_co_ci_u32_e32 v15, vcc_lo, s43, v5, vcc_lo
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[19:20], v[10:11], off
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[4:5], v[6:7], off
	global_load_b64 v[6:7], v[14:15], off
	v_add_co_u32 v10, vcc_lo, s50, v1
	s_add_i32 s53, s8, -1
	v_add_co_ci_u32_e32 v11, vcc_lo, s52, v2, vcc_lo
	s_mul_i32 s53, s53, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_ashr_i32 s50, s53, 31
	s_add_u32 s52, s53, s4
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_addc_u32 s50, s50, s48
	s_add_i32 s53, s9, -1
	v_add_co_u32 v14, vcc_lo, s52, v1
	s_mul_i32 s53, s53, s26
	v_add_co_ci_u32_e32 v15, vcc_lo, s50, v2, vcc_lo
	s_ashr_i32 s50, s53, 31
	v_add_co_u32 v10, vcc_lo, s2, v10
	s_add_u32 s52, s53, s4
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	s_addc_u32 s50, s50, s48
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v21, vcc_lo, s52, v1
	s_add_i32 s53, s10, -1
	v_add_co_ci_u32_e32 v22, vcc_lo, s50, v2, vcc_lo
	s_mul_i32 s53, s53, s26
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_ashr_i32 s50, s53, 31
	s_add_u32 s52, s53, s4
	s_addc_u32 s50, s50, s48
	s_add_i32 s53, s11, -1
	v_lshlrev_b64 v[21:22], 3, v[21:22]
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_mul_i32 s53, s53, s26
	v_add_co_u32 v23, vcc_lo, s52, v1
	v_add_co_ci_u32_e32 v24, vcc_lo, s50, v2, vcc_lo
	s_ashr_i32 s50, s53, 31
	s_add_u32 s52, s53, s4
	s_addc_u32 s53, s50, s48
	s_add_i32 s54, s12, -1
	v_add_co_u32 v21, vcc_lo, s2, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
	s_mul_i32 s54, s54, s26
	v_add_co_u32 v25, vcc_lo, s52, v1
	s_ashr_i32 s50, s5, 31
	s_ashr_i32 s52, s54, 31
	v_add_co_ci_u32_e32 v26, vcc_lo, s53, v2, vcc_lo
	s_add_u32 s53, s54, s5
	s_addc_u32 s55, s52, s50
	v_add_co_u32 v27, vcc_lo, s53, v1
	v_lshlrev_b64 v[23:24], 3, v[23:24]
	v_add_co_ci_u32_e32 v28, vcc_lo, s55, v2, vcc_lo
	v_lshlrev_b64 v[25:26], 3, v[25:26]
	s_add_u32 s53, s54, s4
	s_addc_u32 s52, s52, s48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v23, vcc_lo, s2, v23
	v_lshlrev_b64 v[27:28], 3, v[27:28]
	v_add_co_ci_u32_e32 v24, vcc_lo, s3, v24, vcc_lo
	v_add_co_u32 v25, vcc_lo, s2, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, s3, v26, vcc_lo
	v_add_co_u32 v27, vcc_lo, s2, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s3, v28, vcc_lo
	s_add_i32 s54, s13, -1
                                        ; implicit-def: $sgpr55
	s_waitcnt vmcnt(4)
	global_store_b64 v[10:11], v[12:13], off offset:-8
	s_waitcnt vmcnt(3)
	global_store_b64 v[14:15], v[19:20], off offset:-8
	s_waitcnt vmcnt(2)
	global_store_b64 v[21:22], v[8:9], off offset:-8
	s_waitcnt vmcnt(1)
	global_store_b64 v[23:24], v[4:5], off offset:-8
	s_waitcnt vmcnt(0)
	global_store_b64 v[25:26], v[6:7], off offset:-8
	global_load_b64 v[14:15], v[27:28], off offset:-8
	s_mul_i32 s54, s54, s26
	v_add_co_u32 v10, vcc_lo, s53, v1
	v_add_co_ci_u32_e32 v11, vcc_lo, s52, v2, vcc_lo
	s_ashr_i32 s52, s54, 31
	s_add_u32 s53, s54, s4
	s_addc_u32 s52, s52, s48
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[21:22], v[12:13], v[14:15]
	v_add_co_u32 v12, vcc_lo, s53, v1
	v_add_co_ci_u32_e32 v13, vcc_lo, s52, v2, vcc_lo
	s_mov_b32 s53, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[23:24], 3, v[12:13]
	v_add_co_u32 v12, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v23
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v24, vcc_lo
	s_clause 0x1
	global_store_b64 v[12:13], v[14:15], off offset:-8
	global_store_b64 v[10:11], v[21:22], off offset:-8
	global_load_b64 v[14:15], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[14:15], v[19:20], v[14:15]
	v_mul_lo_u32 v19, v16, s20
	v_add3_u32 v20, s51, -1, v1
	s_add_i32 s51, s15, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s51, s51, s26
	s_ashr_i32 s52, s51, 31
	s_add_u32 s51, s51, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v19, v0, v20, v19
	s_addc_u32 s52, s52, s48
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 3, v[19:20]
	v_add_co_u32 v19, vcc_lo, s2, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v20, vcc_lo, s3, v20, vcc_lo
	global_store_b64 v[19:20], v[14:15], off
	global_load_b64 v[14:15], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[8:9], v[14:15]
	v_add_co_u32 v14, vcc_lo, s51, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s52, v2, vcc_lo
	s_mov_b32 s51, s4
	s_mov_b32 s52, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	global_store_b64 v[14:15], v[8:9], off offset:-8
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s54, s1
	s_xor_b32 s54, exec_lo, s54
	s_cbranch_execz .LBB2_30
; %bb.27:
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr55
	s_and_saveexec_b32 s56, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s56, exec_lo, s56
	s_cbranch_execz .LBB2_29
; %bb.28:
	s_add_i32 s55, s16, -1
	s_mov_b32 s52, exec_lo
	s_mul_i32 s55, s55, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_ashr_i32 s57, s55, 31
	s_add_u32 s58, s55, s53
	s_addc_u32 s57, s57, s50
	v_add_co_u32 v4, vcc_lo, s58, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s57, v2, vcc_lo
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b64 v[14:15], v[4:5], off offset:-8
.LBB2_29:                               ; %Flow2777
	s_or_b32 exec_lo, exec_lo, s56
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s52, s52, exec_lo
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr6_vgpr7
.LBB2_30:                               ; %Flow2776
	s_or_saveexec_b32 s54, s54
	v_mov_b32_e32 v19, s55
	s_xor_b32 exec_lo, exec_lo, s54
	s_cbranch_execz .LBB2_32
; %bb.31:
	global_load_b64 v[12:13], v[12:13], off offset:-8
	s_add_i32 s55, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s55, s55, s26
	s_ashr_i32 s56, s55, 31
	s_add_u32 s53, s55, s53
	s_addc_u32 s50, s56, s50
	s_ashr_i32 s55, s49, 31
	s_add_u32 s49, s49, s51
	s_addc_u32 s55, s55, s48
	s_waitcnt vmcnt(1)
	v_add_co_u32 v14, vcc_lo, s49, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s55, v2, vcc_lo
	s_add_i32 s49, s16, -1
	s_or_b32 s52, s52, exec_lo
	s_mul_i32 s49, s49, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_clause 0x1
	global_load_b64 v[10:11], v[10:11], off offset:-8
	global_load_b64 v[14:15], v[14:15], off offset:-8
	v_add_co_u32 v23, vcc_lo, s53, v1
	v_add_co_ci_u32_e32 v24, vcc_lo, s50, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 3, v[23:24]
	v_add_co_u32 v23, vcc_lo, s2, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v24, vcc_lo, s3, v24, vcc_lo
	global_load_b64 v[23:24], v[23:24], off offset:-8
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[19:20], null, v[12:13], v[12:13], 0.5
	v_div_scale_f64 v[27:28], vcc_lo, 0.5, v[12:13], 0.5
	s_waitcnt vmcnt(1)
	v_mul_f64 v[14:15], v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[21:22], v[19:20]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[4:5], v[4:5], v[23:24]
	v_fma_f64 v[10:11], v[10:11], v[10:11], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[19:20], v[21:22], 1.0
	v_fma_f64 v[8:9], v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_fma_f64 v[25:26], -v[19:20], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_mul_f64 v[25:26], v[27:28], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[19:20], v[25:26], v[27:28]
	v_div_fmas_f64 v[19:20], v[19:20], v[21:22], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[12:13], v[19:20], v[12:13], 0.5
	v_mov_b32_e32 v19, s49
	v_mul_f64 v[8:9], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[14:15], v[6:7], v[4:5], v[8:9]
.LBB2_32:                               ; %Flow2778
	s_or_b32 exec_lo, exec_lo, s54
	s_and_saveexec_b32 s49, s52
	s_cbranch_execz .LBB2_34
; %bb.33:                               ; %.loopexit2476.sink.split
	v_ashrrev_i32_e32 v4, 31, v19
	v_add_co_u32 v5, vcc_lo, v19, s51
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s48, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v6, v2, vcc_lo
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[14:15], off offset:-8
.LBB2_34:                               ; %Flow2779
	s_or_b32 exec_lo, exec_lo, s49
.LBB2_35:                               ; %.loopexit2476
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s45
	s_mov_b32 s48, -1
	s_mov_b32 s49, s46
	s_mov_b32 s50, s33
	s_mov_b32 s45, exec_lo
	v_cmpx_lt_i32_e32 3, v3
	s_cbranch_execz .LBB2_39
; %bb.36:                               ; %NodeBlock2745
	s_mov_b32 s49, s33
	s_mov_b32 s50, exec_lo
	v_cmpx_lt_i32_e32 4, v3
; %bb.37:                               ; %LeafBlock2743
	v_cmp_eq_u32_e32 vcc_lo, 5, v3
	s_and_not1_b32 s48, s33, exec_lo
	s_and_b32 s49, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s49, s48, s49
	s_xor_b32 s48, exec_lo, -1
; %bb.38:                               ; %Flow2811
	s_or_b32 exec_lo, exec_lo, s50
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s50, s33, exec_lo
	s_and_b32 s49, s49, exec_lo
	s_and_b32 s51, s48, exec_lo
	s_or_b32 s50, s50, s49
	s_and_not1_b32 s49, s46, exec_lo
	s_xor_b32 s48, exec_lo, -1
	s_or_b32 s49, s49, s51
.LBB2_39:                               ; %Flow2810
	s_or_b32 exec_lo, exec_lo, s45
	v_dual_mov_b32 v20, s44 :: v_dual_mov_b32 v19, s44
	s_and_not1_b32 s33, s33, exec_lo
	s_and_b32 s45, s50, exec_lo
	s_and_not1_b32 s46, s46, exec_lo
	s_and_b32 s49, s49, exec_lo
	s_or_b32 s33, s33, s45
	s_and_b32 s45, s48, exec_lo
	s_or_b32 s46, s46, s49
.LBB2_40:                               ; %Flow2809
	s_or_b32 exec_lo, exec_lo, s47
	s_mov_b32 s48, 0
	s_mov_b32 s49, 0
	s_and_saveexec_b32 s47, s46
	s_cbranch_execz .LBB2_64
; %bb.41:                               ; %.preheader2474.preheader
	v_mad_u64_u32 v[8:9], null, v16, s19, v[0:1]
	s_mov_b32 s48, 0xd9d7bdbb
	s_mov_b32 s49, 0x3ddb7cdf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v8, v18
	v_add_nc_u32_e32 v5, v4, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s34, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s35, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f64_e64 s46, |v[5:6]|, s[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s48, s46
	s_xor_b32 s46, exec_lo, s48
	s_cbranch_execz .LBB2_45
; %bb.42:                               ; %.preheader2472
	s_cmp_lt_i32 s31, 1
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr8_vgpr9
	s_cbranch_scc1 .LBB2_45
; %bb.43:                               ; %.lr.ph2485
	v_add_nc_u32_e32 v5, -1, v1
	s_mov_b32 s48, s31
.LBB2_44:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s5, v5
	v_add_nc_u32_e32 v8, s4, v5
	v_add_nc_u32_e32 v5, s26, v5
	s_add_i32 s48, s48, -1
                                        ; implicit-def: $vgpr4
	s_cmp_eq_u32 s48, 0
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v9, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
                                        ; implicit-def: $vgpr8_vgpr9
	s_waitcnt vmcnt(0)
	global_store_b64 v[10:11], v[6:7], off
	s_cbranch_scc0 .LBB2_44
.LBB2_45:                               ; %Flow2773
	s_and_not1_saveexec_b32 s46, s46
	s_cbranch_execz .LBB2_55
; %bb.46:
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s49, s14, -1
	s_add_i32 s50, s7, -1
	s_mul_i32 s49, s49, s26
	s_mul_i32 s50, s50, s26
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_ashr_i32 s48, s4, 31
	s_add_i32 s51, s4, s49
	s_ashr_i32 s52, s50, 31
	s_add_u32 s50, s50, s4
	s_addc_u32 s52, s52, s48
	v_add_co_u32 v6, vcc_lo, s28, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s29, v5, vcc_lo
	v_add_co_u32 v9, vcc_lo, s40, v4
	v_add_co_ci_u32_e32 v10, vcc_lo, s41, v5, vcc_lo
	v_add_co_u32 v11, vcc_lo, s38, v4
	v_add_co_ci_u32_e32 v12, vcc_lo, s39, v5, vcc_lo
	v_add_co_u32 v13, vcc_lo, s36, v4
	v_add_co_ci_u32_e32 v14, vcc_lo, s37, v5, vcc_lo
	v_add_co_u32 v20, vcc_lo, s42, v4
	v_add_co_ci_u32_e32 v21, vcc_lo, s43, v5, vcc_lo
	global_load_b64 v[13:14], v[13:14], off
	global_load_b64 v[22:23], v[11:12], off
	global_load_b64 v[24:25], v[9:10], off
	global_load_b64 v[4:5], v[6:7], off
	global_load_b64 v[6:7], v[20:21], off
	v_add_co_u32 v9, vcc_lo, s50, v1
	s_add_i32 s53, s8, -1
	v_add_co_ci_u32_e32 v10, vcc_lo, s52, v2, vcc_lo
	s_mul_i32 s53, s53, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_ashr_i32 s50, s53, 31
	s_add_u32 s52, s53, s4
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	s_addc_u32 s50, s50, s48
	s_add_i32 s53, s9, -1
	v_add_co_u32 v11, vcc_lo, s52, v1
	s_mul_i32 s53, s53, s26
	v_add_co_ci_u32_e32 v12, vcc_lo, s50, v2, vcc_lo
	s_ashr_i32 s50, s53, 31
	v_add_co_u32 v9, vcc_lo, s2, v9
	s_add_u32 s52, s53, s4
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	s_addc_u32 s50, s50, s48
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	v_add_co_u32 v20, vcc_lo, s52, v1
	s_add_i32 s53, s10, -1
	v_add_co_ci_u32_e32 v21, vcc_lo, s50, v2, vcc_lo
	s_mul_i32 s53, s53, s26
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s2, v11
	s_ashr_i32 s50, s53, 31
	s_add_u32 s52, s53, s4
	s_addc_u32 s50, s50, s48
	s_add_i32 s53, s11, -1
	v_lshlrev_b64 v[20:21], 3, v[20:21]
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	s_mul_i32 s53, s53, s26
	v_add_co_u32 v26, vcc_lo, s52, v1
	v_add_co_ci_u32_e32 v27, vcc_lo, s50, v2, vcc_lo
	s_ashr_i32 s50, s53, 31
	s_add_u32 s52, s53, s4
	s_addc_u32 s53, s50, s48
	s_add_i32 s54, s12, -1
	v_add_co_u32 v20, vcc_lo, s2, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
	s_mul_i32 s54, s54, s26
	v_add_co_u32 v28, vcc_lo, s52, v1
	s_ashr_i32 s50, s5, 31
	s_ashr_i32 s52, s54, 31
	v_add_co_ci_u32_e32 v29, vcc_lo, s53, v2, vcc_lo
	s_add_u32 s53, s54, s5
	s_addc_u32 s55, s52, s50
	v_add_co_u32 v30, vcc_lo, s53, v1
	v_lshlrev_b64 v[26:27], 3, v[26:27]
	v_add_co_ci_u32_e32 v31, vcc_lo, s55, v2, vcc_lo
	v_lshlrev_b64 v[28:29], 3, v[28:29]
	s_add_u32 s53, s54, s4
	s_addc_u32 s52, s52, s48
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v26, vcc_lo, s2, v26
	v_lshlrev_b64 v[30:31], 3, v[30:31]
	v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
	v_add_co_u32 v28, vcc_lo, s2, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
	v_add_co_u32 v30, vcc_lo, s2, v30
	v_add_co_ci_u32_e32 v31, vcc_lo, s3, v31, vcc_lo
	s_add_i32 s54, s13, -1
                                        ; implicit-def: $sgpr55
	s_waitcnt vmcnt(4)
	global_store_b64 v[9:10], v[13:14], off offset:-8
	s_waitcnt vmcnt(3)
	global_store_b64 v[11:12], v[22:23], off offset:-8
	s_waitcnt vmcnt(2)
	global_store_b64 v[20:21], v[24:25], off offset:-8
	s_waitcnt vmcnt(1)
	global_store_b64 v[26:27], v[4:5], off offset:-8
	s_waitcnt vmcnt(0)
	global_store_b64 v[28:29], v[6:7], off offset:-8
	global_load_b64 v[20:21], v[30:31], off offset:-8
	s_mul_i32 s54, s54, s26
	v_add_co_u32 v9, vcc_lo, s53, v1
	v_add_co_ci_u32_e32 v10, vcc_lo, s52, v2, vcc_lo
	s_ashr_i32 s52, s54, 31
	s_add_u32 s53, s4, s54
	s_addc_u32 s52, s48, s52
	v_add_co_u32 v11, vcc_lo, s53, v1
	v_add_co_ci_u32_e32 v12, vcc_lo, s52, v2, vcc_lo
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	s_add_i32 s51, s51, -1
	s_mov_b32 s53, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[26:27], 3, v[11:12]
	v_add3_u32 v8, s51, v1, v8
	s_add_i32 s51, s15, -1
	v_add_co_u32 v12, vcc_lo, s2, v9
	s_mul_i32 s51, s51, s26
	v_ashrrev_i32_e32 v9, 31, v8
	s_ashr_i32 s52, s51, 31
	s_add_u32 s51, s51, s4
	s_addc_u32 s52, s52, s48
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[14:15], v[13:14], v[20:21]
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v10, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v26
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v27, vcc_lo
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	s_clause 0x1
	global_store_b64 v[12:13], v[20:21], off offset:-8
	global_store_b64 v[10:11], v[14:15], off offset:-80
	global_load_b64 v[14:15], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[14:15], v[22:23], v[14:15]
	global_store_b64 v[8:9], v[14:15], off
	global_load_b64 v[8:9], v[12:13], off offset:-8
	v_add_co_u32 v14, vcc_lo, s51, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s52, v2, vcc_lo
	s_mov_b32 s51, s4
	s_mov_b32 s52, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[24:25], v[8:9]
	global_store_b64 v[14:15], v[8:9], off offset:-8
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s54, s1
	s_xor_b32 s54, exec_lo, s54
	s_cbranch_execz .LBB2_50
; %bb.47:
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr55
	s_and_saveexec_b32 s56, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s56, exec_lo, s56
	s_cbranch_execz .LBB2_49
; %bb.48:
	s_add_i32 s55, s16, -1
	s_mov_b32 s52, exec_lo
	s_mul_i32 s55, s55, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_ashr_i32 s57, s55, 31
	s_add_u32 s58, s55, s53
	s_addc_u32 s57, s57, s50
	v_add_co_u32 v4, vcc_lo, s58, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s57, v2, vcc_lo
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b64 v[14:15], v[4:5], off offset:-8
.LBB2_49:                               ; %Flow2769
	s_or_b32 exec_lo, exec_lo, s56
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s52, s52, exec_lo
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr6_vgpr7
.LBB2_50:                               ; %Flow2768
	s_or_saveexec_b32 s54, s54
	v_mov_b32_e32 v20, s55
	s_xor_b32 exec_lo, exec_lo, s54
	s_cbranch_execz .LBB2_52
; %bb.51:
	global_load_b64 v[12:13], v[12:13], off offset:-8
	s_add_i32 s55, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s55, s55, s26
	s_ashr_i32 s56, s55, 31
	s_add_u32 s53, s55, s53
	s_addc_u32 s50, s56, s50
	s_ashr_i32 s55, s49, 31
	s_add_u32 s49, s49, s51
	s_addc_u32 s55, s55, s48
	s_waitcnt vmcnt(1)
	v_add_co_u32 v14, vcc_lo, s49, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s55, v2, vcc_lo
	s_add_i32 s49, s16, -1
	s_or_b32 s52, s52, exec_lo
	s_mul_i32 s49, s49, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_clause 0x1
	global_load_b64 v[10:11], v[10:11], off offset:-8
	global_load_b64 v[14:15], v[14:15], off offset:-8
	v_add_co_u32 v24, vcc_lo, s53, v1
	v_add_co_ci_u32_e32 v25, vcc_lo, s50, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[24:25], 3, v[24:25]
	v_add_co_u32 v24, vcc_lo, s2, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
	global_load_b64 v[24:25], v[24:25], off offset:-8
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[20:21], null, v[12:13], v[12:13], 0.5
	v_div_scale_f64 v[28:29], vcc_lo, 0.5, v[12:13], 0.5
	s_waitcnt vmcnt(1)
	v_mul_f64 v[14:15], v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[22:23], v[20:21]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[4:5], v[4:5], v[24:25]
	v_fma_f64 v[10:11], v[10:11], v[10:11], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[20:21], v[22:23], 1.0
	v_fma_f64 v[8:9], v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	v_fma_f64 v[26:27], -v[20:21], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	v_mul_f64 v[26:27], v[28:29], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], -v[20:21], v[26:27], v[28:29]
	v_div_fmas_f64 v[20:21], v[20:21], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[12:13], v[20:21], v[12:13], 0.5
	v_mov_b32_e32 v20, s49
	v_mul_f64 v[8:9], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[14:15], v[6:7], v[4:5], v[8:9]
.LBB2_52:                               ; %Flow2770
	s_or_b32 exec_lo, exec_lo, s54
	s_and_saveexec_b32 s49, s52
	s_cbranch_execz .LBB2_54
; %bb.53:                               ; %.loopexit2473.sink.split
	v_ashrrev_i32_e32 v4, 31, v20
	v_add_co_u32 v5, vcc_lo, v20, s51
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s48, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v6, v2, vcc_lo
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[14:15], off offset:-8
.LBB2_54:                               ; %Flow2771
	s_or_b32 exec_lo, exec_lo, s49
.LBB2_55:                               ; %.loopexit2473
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s46
	s_mov_b32 s46, 0
	s_mov_b32 s49, 0
	s_mov_b32 s50, s33
	s_mov_b32 s48, exec_lo
                                        ; implicit-def: $vgpr20
	v_cmpx_lt_i32_e32 1, v3
	s_xor_b32 s48, exec_lo, s48
	s_cbranch_execz .LBB2_61
; %bb.56:                               ; %NodeBlock2755
	s_mov_b32 s49, s33
	s_mov_b32 s50, exec_lo
	v_cmpx_lt_i32_e32 4, v3
	s_xor_b32 s50, exec_lo, s50
; %bb.57:                               ; %LeafBlock2753
	v_cmp_eq_u32_e32 vcc_lo, 5, v3
	s_and_not1_b32 s49, s33, exec_lo
	s_and_b32 s51, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s49, s49, s51
; %bb.58:                               ; %Flow2814
	s_or_saveexec_b32 s50, s50
	s_mov_b32 s51, 0
	s_xor_b32 exec_lo, exec_lo, s50
; %bb.59:                               ; %LeafBlock2751
	v_cmp_eq_u32_e32 vcc_lo, 2, v3
	s_and_b32 s51, vcc_lo, exec_lo
; %bb.60:                               ; %Flow2815
	s_or_b32 exec_lo, exec_lo, s50
	v_mov_b32_e32 v20, v19
	s_and_not1_b32 s50, s33, exec_lo
	s_and_b32 s49, s49, exec_lo
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s50, s50, s49
	s_and_b32 s49, s51, exec_lo
.LBB2_61:                               ; %Flow2813
	s_and_not1_saveexec_b32 s48, s48
; %bb.62:                               ; %LeafBlock2749
	v_cmp_eq_u32_e32 vcc_lo, 1, v3
                                        ; implicit-def: $vgpr20
	s_and_b32 s46, vcc_lo, exec_lo
; %bb.63:                               ; %Flow2816
	s_or_b32 exec_lo, exec_lo, s48
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s33, s33, exec_lo
	s_and_b32 s48, s50, exec_lo
	s_and_b32 s49, s49, exec_lo
	s_or_b32 s33, s33, s48
	s_and_b32 s48, s46, exec_lo
.LBB2_64:                               ; %Flow2812
	s_or_b32 exec_lo, exec_lo, s47
	s_and_saveexec_b32 s46, s45
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s45, exec_lo, s46
	s_cbranch_execz .LBB2_70
; %bb.65:                               ; %NodeBlock2741
	s_mov_b32 s46, s49
	s_mov_b32 s47, exec_lo
	v_cmpx_lt_i32_e32 1, v3
	s_xor_b32 s47, exec_lo, s47
; %bb.66:                               ; %LeafBlock2739
	v_cmp_eq_u32_e32 vcc_lo, 2, v3
	s_and_not1_b32 s46, s49, exec_lo
	s_and_b32 s50, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s46, s46, s50
; %bb.67:                               ; %Flow2818
	s_or_saveexec_b32 s47, s47
	s_mov_b32 s50, s48
	s_xor_b32 exec_lo, exec_lo, s47
; %bb.68:                               ; %LeafBlock2737
	v_cmp_eq_u32_e32 vcc_lo, 1, v3
	s_and_not1_b32 s50, s48, exec_lo
	s_and_b32 s51, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s50, s50, s51
; %bb.69:                               ; %Flow2819
	s_or_b32 exec_lo, exec_lo, s47
	v_dual_mov_b32 v20, s44 :: v_dual_mov_b32 v19, s44
	s_and_not1_b32 s44, s49, exec_lo
	s_and_b32 s46, s46, exec_lo
	s_and_not1_b32 s47, s48, exec_lo
	s_and_b32 s48, s50, exec_lo
	s_or_b32 s49, s44, s46
	s_or_b32 s48, s47, s48
.LBB2_70:                               ; %Flow2817
	s_or_b32 exec_lo, exec_lo, s45
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s33, s33, exec_lo
	s_and_b32 s44, s49, exec_lo
	s_and_b32 s45, s48, exec_lo
.LBB2_71:                               ; %Flow2804
	s_and_not1_saveexec_b32 s27, s27
	s_cbranch_execz .LBB2_79
; %bb.72:                               ; %NodeBlock2727
	s_mov_b32 s49, -1
	s_mov_b32 s48, s45
	s_mov_b32 s50, s44
	s_mov_b32 s46, exec_lo
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $sgpr25
                                        ; implicit-def: $sgpr47
	v_cmpx_lt_i32_e32 0, v3
	s_cbranch_execz .LBB2_78
; %bb.73:                               ; %NodeBlock2725
	s_mov_b32 s48, s44
	s_mov_b32 s47, exec_lo
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $sgpr25
	v_cmpx_lt_i32_e32 1, v3
	s_xor_b32 s47, exec_lo, s47
	s_cbranch_execz .LBB2_75
; %bb.74:                               ; %..preheader2468.preheader_crit_edge
	s_waitcnt lgkmcnt(0)
	s_add_i32 s25, s23, -1
	v_mul_lo_u32 v18, v17, s24
	s_mul_i32 s25, s25, s30
	s_or_b32 s48, s44, exec_lo
.LBB2_75:                               ; %Flow2822
	s_or_saveexec_b32 s49, s47
	s_mov_b32 s50, s45
                                        ; implicit-def: $sgpr47
	s_xor_b32 exec_lo, exec_lo, s49
	s_cbranch_execz .LBB2_77
; %bb.76:                               ; %..preheader2471.preheader_crit_edge
	v_mul_lo_u32 v18, v17, s24
	s_waitcnt lgkmcnt(0)
	s_add_i32 s47, s23, -1
	s_or_b32 s50, s45, exec_lo
	s_mul_i32 s47, s47, s30
.LBB2_77:                               ; %Flow2823
	s_or_b32 exec_lo, exec_lo, s49
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s51, s44, exec_lo
	s_and_b32 s48, s48, exec_lo
	s_and_not1_b32 s52, s45, exec_lo
	s_and_b32 s53, s50, exec_lo
	s_xor_b32 s49, exec_lo, -1
	s_or_b32 s50, s51, s48
	s_or_b32 s48, s52, s53
.LBB2_78:                               ; %Flow2821
	s_or_b32 exec_lo, exec_lo, s46
	v_dual_mov_b32 v20, s25 :: v_dual_mov_b32 v19, s47
	s_and_not1_b32 s44, s44, exec_lo
	s_and_b32 s46, s50, exec_lo
	s_and_not1_b32 s45, s45, exec_lo
	s_and_b32 s47, s48, exec_lo
	s_and_b32 s25, s49, exec_lo
	s_or_b32 s44, s44, s46
	s_or_b32 s45, s45, s47
.LBB2_79:                               ; %Flow2820
	s_or_b32 exec_lo, exec_lo, s27
	s_and_saveexec_b32 s27, s45
	s_cbranch_execz .LBB2_99
; %bb.80:                               ; %.preheader2471.preheader
	v_mul_lo_u32 v4, v0, s19
	v_mul_lo_u32 v5, v16, s22
	s_mov_b32 s46, 0xd9d7bdbb
	s_mov_b32 s47, 0x3ddb7cdf
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v4, s19, -1, v4
	v_add3_u32 v4, v4, v5, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v4, v19
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s34, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s35, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f64_e64 s45, |v[5:6]|, s[46:47]
	s_and_saveexec_b32 s46, s45
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s45, exec_lo, s46
	s_cbranch_execz .LBB2_84
; %bb.81:                               ; %.preheader2469
	s_cmp_lt_i32 s31, 1
                                        ; implicit-def: $vgpr4
	s_cbranch_scc1 .LBB2_84
; %bb.82:                               ; %.lr.ph2487
	v_add_nc_u32_e32 v5, -1, v1
	s_mov_b32 s46, s31
.LBB2_83:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s5, v5
	v_add_nc_u32_e32 v8, s4, v5
	v_add_nc_u32_e32 v5, s26, v5
	s_add_i32 s46, s46, -1
                                        ; implicit-def: $vgpr4
	s_cmp_eq_u32 s46, 0
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[6:7], off
	s_cbranch_scc0 .LBB2_83
.LBB2_84:                               ; %Flow2799
	s_and_not1_saveexec_b32 s45, s45
	s_cbranch_execz .LBB2_94
; %bb.85:
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s47, s14, -1
	s_add_i32 s48, s7, -1
	s_mul_i32 s47, s47, s26
	s_mul_i32 s48, s48, s26
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_ashr_i32 s46, s4, 31
	s_add_i32 s49, s4, s47
	s_ashr_i32 s50, s48, 31
	s_add_u32 s48, s48, s4
	s_addc_u32 s50, s50, s46
	v_add_co_u32 v6, vcc_lo, s28, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s29, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s40, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s41, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s38, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, s39, v5, vcc_lo
	v_add_co_u32 v12, vcc_lo, s36, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, s37, v5, vcc_lo
	v_add_co_u32 v14, vcc_lo, s42, v4
	v_add_co_ci_u32_e32 v15, vcc_lo, s43, v5, vcc_lo
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[20:21], v[10:11], off
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[4:5], v[6:7], off
	global_load_b64 v[6:7], v[14:15], off
	v_add_co_u32 v10, vcc_lo, s48, v1
	s_add_i32 s51, s8, -1
	v_add_co_ci_u32_e32 v11, vcc_lo, s50, v2, vcc_lo
	s_mul_i32 s51, s51, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_ashr_i32 s48, s51, 31
	s_add_u32 s50, s51, s4
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_addc_u32 s48, s48, s46
	s_add_i32 s51, s9, -1
	v_add_co_u32 v14, vcc_lo, s50, v1
	s_mul_i32 s51, s51, s26
	v_add_co_ci_u32_e32 v15, vcc_lo, s48, v2, vcc_lo
	s_ashr_i32 s48, s51, 31
	v_add_co_u32 v10, vcc_lo, s2, v10
	s_add_u32 s50, s51, s4
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	s_addc_u32 s48, s48, s46
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v22, vcc_lo, s50, v1
	s_add_i32 s51, s10, -1
	v_add_co_ci_u32_e32 v23, vcc_lo, s48, v2, vcc_lo
	s_mul_i32 s51, s51, s26
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_ashr_i32 s48, s51, 31
	s_add_u32 s50, s51, s4
	s_addc_u32 s48, s48, s46
	s_add_i32 s51, s11, -1
	v_lshlrev_b64 v[22:23], 3, v[22:23]
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_mul_i32 s51, s51, s26
	v_add_co_u32 v24, vcc_lo, s50, v1
	v_add_co_ci_u32_e32 v25, vcc_lo, s48, v2, vcc_lo
	s_ashr_i32 s48, s51, 31
	s_add_u32 s50, s51, s4
	s_addc_u32 s51, s48, s46
	s_add_i32 s52, s12, -1
	v_add_co_u32 v22, vcc_lo, s2, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s3, v23, vcc_lo
	s_mul_i32 s52, s52, s26
	v_add_co_u32 v26, vcc_lo, s50, v1
	s_ashr_i32 s48, s5, 31
	s_ashr_i32 s50, s52, 31
	v_add_co_ci_u32_e32 v27, vcc_lo, s51, v2, vcc_lo
	s_add_u32 s51, s52, s5
	s_addc_u32 s53, s50, s48
	v_add_co_u32 v28, vcc_lo, s51, v1
	v_lshlrev_b64 v[24:25], 3, v[24:25]
	v_add_co_ci_u32_e32 v29, vcc_lo, s53, v2, vcc_lo
	v_lshlrev_b64 v[26:27], 3, v[26:27]
	s_add_u32 s51, s52, s4
	s_addc_u32 s50, s50, s46
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v24, vcc_lo, s2, v24
	v_lshlrev_b64 v[28:29], 3, v[28:29]
	v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
	v_add_co_u32 v26, vcc_lo, s2, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
	v_add_co_u32 v28, vcc_lo, s2, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
	s_add_i32 s52, s13, -1
                                        ; implicit-def: $sgpr53
	s_waitcnt vmcnt(4)
	global_store_b64 v[10:11], v[12:13], off offset:-8
	s_waitcnt vmcnt(3)
	global_store_b64 v[14:15], v[20:21], off offset:-8
	s_waitcnt vmcnt(2)
	global_store_b64 v[22:23], v[8:9], off offset:-8
	s_waitcnt vmcnt(1)
	global_store_b64 v[24:25], v[4:5], off offset:-8
	s_waitcnt vmcnt(0)
	global_store_b64 v[26:27], v[6:7], off offset:-8
	global_load_b64 v[14:15], v[28:29], off offset:-8
	s_mul_i32 s52, s52, s26
	v_add_co_u32 v10, vcc_lo, s51, v1
	v_add_co_ci_u32_e32 v11, vcc_lo, s50, v2, vcc_lo
	s_ashr_i32 s50, s52, 31
	s_add_u32 s51, s52, s4
	s_addc_u32 s50, s50, s46
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[22:23], v[12:13], v[14:15]
	v_add_co_u32 v12, vcc_lo, s51, v1
	v_add_co_ci_u32_e32 v13, vcc_lo, s50, v2, vcc_lo
	s_mov_b32 s51, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[24:25], 3, v[12:13]
	v_add_co_u32 v12, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v24
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v25, vcc_lo
	s_clause 0x1
	global_store_b64 v[12:13], v[14:15], off offset:-8
	global_store_b64 v[10:11], v[22:23], off offset:-8
	global_load_b64 v[14:15], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[14:15], v[20:21], v[14:15]
	v_mul_lo_u32 v20, v16, s19
	v_add3_u32 v21, s49, -1, v1
	s_add_i32 s49, s15, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s49, s49, s26
	s_ashr_i32 s50, s49, 31
	s_add_u32 s49, s49, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v20, v0, v21, v20
	s_addc_u32 s50, s50, s46
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 3, v[20:21]
	v_add_co_u32 v20, vcc_lo, s2, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
	global_store_b64 v[20:21], v[14:15], off
	global_load_b64 v[14:15], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[8:9], v[14:15]
	v_add_co_u32 v14, vcc_lo, s49, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s50, v2, vcc_lo
	s_mov_b32 s49, s4
	s_mov_b32 s50, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	global_store_b64 v[14:15], v[8:9], off offset:-8
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s52, s1
	s_xor_b32 s52, exec_lo, s52
	s_cbranch_execz .LBB2_89
; %bb.86:
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr53
	s_and_saveexec_b32 s54, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s54, exec_lo, s54
	s_cbranch_execz .LBB2_88
; %bb.87:
	s_add_i32 s53, s16, -1
	s_mov_b32 s50, exec_lo
	s_mul_i32 s53, s53, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_ashr_i32 s55, s53, 31
	s_add_u32 s56, s53, s51
	s_addc_u32 s55, s55, s48
	v_add_co_u32 v4, vcc_lo, s56, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s55, v2, vcc_lo
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b64 v[14:15], v[4:5], off offset:-8
.LBB2_88:                               ; %Flow2795
	s_or_b32 exec_lo, exec_lo, s54
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s50, s50, exec_lo
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr6_vgpr7
.LBB2_89:                               ; %Flow2794
	s_or_saveexec_b32 s52, s52
	v_mov_b32_e32 v20, s53
	s_xor_b32 exec_lo, exec_lo, s52
	s_cbranch_execz .LBB2_91
; %bb.90:
	global_load_b64 v[12:13], v[12:13], off offset:-8
	s_add_i32 s53, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s53, s53, s26
	s_ashr_i32 s54, s53, 31
	s_add_u32 s51, s53, s51
	s_addc_u32 s48, s54, s48
	s_ashr_i32 s53, s47, 31
	s_add_u32 s47, s47, s49
	s_addc_u32 s53, s53, s46
	s_waitcnt vmcnt(1)
	v_add_co_u32 v14, vcc_lo, s47, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s53, v2, vcc_lo
	s_add_i32 s47, s16, -1
	s_or_b32 s50, s50, exec_lo
	s_mul_i32 s47, s47, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_clause 0x1
	global_load_b64 v[10:11], v[10:11], off offset:-8
	global_load_b64 v[14:15], v[14:15], off offset:-8
	v_add_co_u32 v24, vcc_lo, s51, v1
	v_add_co_ci_u32_e32 v25, vcc_lo, s48, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[24:25], 3, v[24:25]
	v_add_co_u32 v24, vcc_lo, s2, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
	global_load_b64 v[24:25], v[24:25], off offset:-8
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[20:21], null, v[12:13], v[12:13], 0.5
	v_div_scale_f64 v[28:29], vcc_lo, 0.5, v[12:13], 0.5
	s_waitcnt vmcnt(1)
	v_mul_f64 v[14:15], v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[22:23], v[20:21]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[4:5], v[4:5], v[24:25]
	v_fma_f64 v[10:11], v[10:11], v[10:11], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[20:21], v[22:23], 1.0
	v_fma_f64 v[8:9], v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	v_fma_f64 v[26:27], -v[20:21], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	v_mul_f64 v[26:27], v[28:29], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], -v[20:21], v[26:27], v[28:29]
	v_div_fmas_f64 v[20:21], v[20:21], v[22:23], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[12:13], v[20:21], v[12:13], 0.5
	v_mov_b32_e32 v20, s47
	v_mul_f64 v[8:9], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[14:15], v[6:7], v[4:5], v[8:9]
.LBB2_91:                               ; %Flow2796
	s_or_b32 exec_lo, exec_lo, s52
	s_and_saveexec_b32 s47, s50
	s_cbranch_execz .LBB2_93
; %bb.92:                               ; %.loopexit2470.sink.split
	v_ashrrev_i32_e32 v4, 31, v20
	v_add_co_u32 v5, vcc_lo, v20, s49
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s46, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v6, v2, vcc_lo
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[14:15], off offset:-8
.LBB2_93:                               ; %Flow2797
	s_or_b32 exec_lo, exec_lo, s47
.LBB2_94:                               ; %.loopexit2470
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s45
	s_mov_b32 s45, s33
	s_mov_b32 s46, exec_lo
	v_cmpx_lt_i32_e32 4, v3
	s_xor_b32 s46, exec_lo, s46
; %bb.95:                               ; %LeafBlock2761
	v_cmp_eq_u32_e32 vcc_lo, 5, v3
	s_and_not1_b32 s45, s33, exec_lo
	s_and_b32 s47, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s45, s45, s47
; %bb.96:                               ; %Flow2825
	s_or_saveexec_b32 s47, s46
	s_mov_b32 s46, s44
	s_xor_b32 exec_lo, exec_lo, s47
; %bb.97:                               ; %LeafBlock2759
	v_cmp_eq_u32_e32 vcc_lo, 2, v3
	s_and_not1_b32 s46, s44, exec_lo
	s_and_b32 s48, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s46, s46, s48
; %bb.98:                               ; %Flow2826
	s_or_b32 exec_lo, exec_lo, s47
	v_mov_b32_e32 v20, v19
	s_and_not1_b32 s33, s33, exec_lo
	s_and_b32 s45, s45, exec_lo
	s_and_not1_b32 s44, s44, exec_lo
	s_and_b32 s46, s46, exec_lo
	s_or_b32 s33, s33, s45
	s_or_b32 s44, s44, s46
.LBB2_99:                               ; %Flow2824
	s_or_b32 exec_lo, exec_lo, s27
	s_and_saveexec_b32 s27, s44
	s_cbranch_execz .LBB2_115
; %bb.100:                              ; %.preheader2468.preheader
	s_add_i32 s20, s20, -1
	v_mul_lo_u32 v6, v16, s22
	v_mad_u64_u32 v[4:5], null, s20, s19, v[0:1]
	s_mov_b32 s44, 0xd9d7bdbb
	s_mov_b32 s45, 0x3ddb7cdf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v4, v4, v6, v18
	v_add_nc_u32_e32 v5, v4, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s34, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s35, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f64_e64 s20, |v[5:6]|, s[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s44, s20
	s_xor_b32 s20, exec_lo, s44
	s_cbranch_execz .LBB2_104
; %bb.101:                              ; %.preheader2466
	s_cmp_lt_i32 s31, 1
                                        ; implicit-def: $vgpr4
	s_cbranch_scc1 .LBB2_104
; %bb.102:                              ; %.lr.ph2489
	v_add_nc_u32_e32 v5, -1, v1
	s_mov_b32 s44, s31
.LBB2_103:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s5, v5
	v_add_nc_u32_e32 v8, s4, v5
	v_add_nc_u32_e32 v5, s26, v5
	s_add_i32 s44, s44, -1
                                        ; implicit-def: $vgpr4
	s_cmp_eq_u32 s44, 0
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[6:7], off
	s_cbranch_scc0 .LBB2_103
.LBB2_104:                              ; %Flow2791
	s_and_not1_saveexec_b32 s20, s20
	s_cbranch_execz .LBB2_114
; %bb.105:
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s45, s14, -1
	s_add_i32 s46, s7, -1
	s_mul_i32 s45, s45, s26
	s_mul_i32 s46, s46, s26
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_ashr_i32 s44, s4, 31
	s_add_i32 s47, s4, s45
	s_ashr_i32 s48, s46, 31
	s_add_u32 s46, s46, s4
	s_addc_u32 s48, s48, s44
	v_add_co_u32 v6, vcc_lo, s28, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s29, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s40, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s41, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s38, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, s39, v5, vcc_lo
	v_add_co_u32 v12, vcc_lo, s36, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, s37, v5, vcc_lo
	v_add_co_u32 v14, vcc_lo, s42, v4
	v_add_co_ci_u32_e32 v15, vcc_lo, s43, v5, vcc_lo
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[21:22], v[10:11], off
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[4:5], v[6:7], off
	global_load_b64 v[6:7], v[14:15], off
	v_add_co_u32 v10, vcc_lo, s46, v1
	s_add_i32 s49, s8, -1
	v_add_co_ci_u32_e32 v11, vcc_lo, s48, v2, vcc_lo
	s_mul_i32 s49, s49, s26
	v_mul_lo_u32 v19, v16, s19
	s_ashr_i32 s46, s49, 31
	s_add_u32 s48, s49, s4
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_addc_u32 s46, s46, s44
	s_add_i32 s49, s9, -1
	v_add_co_u32 v14, vcc_lo, s48, v1
	s_mul_i32 s49, s49, s26
	v_add_co_ci_u32_e32 v15, vcc_lo, s46, v2, vcc_lo
	s_ashr_i32 s46, s49, 31
	v_add_co_u32 v10, vcc_lo, s2, v10
	s_add_u32 s48, s49, s4
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	s_addc_u32 s46, s46, s44
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v23, vcc_lo, s48, v1
	s_add_i32 s49, s10, -1
	v_add_co_ci_u32_e32 v24, vcc_lo, s46, v2, vcc_lo
	s_mul_i32 s49, s49, s26
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_ashr_i32 s46, s49, 31
	s_add_u32 s48, s49, s4
	s_addc_u32 s46, s46, s44
	s_add_i32 s49, s11, -1
	v_lshlrev_b64 v[23:24], 3, v[23:24]
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_mul_i32 s49, s49, s26
	v_add_co_u32 v25, vcc_lo, s48, v1
	v_add_co_ci_u32_e32 v26, vcc_lo, s46, v2, vcc_lo
	s_ashr_i32 s46, s49, 31
	s_add_u32 s48, s49, s4
	s_addc_u32 s49, s46, s44
	s_add_i32 s50, s12, -1
	v_add_co_u32 v23, vcc_lo, s2, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s3, v24, vcc_lo
	s_mul_i32 s50, s50, s26
	v_add_co_u32 v27, vcc_lo, s48, v1
	s_ashr_i32 s46, s5, 31
	s_ashr_i32 s48, s50, 31
	v_add_co_ci_u32_e32 v28, vcc_lo, s49, v2, vcc_lo
	s_add_u32 s49, s50, s5
	s_addc_u32 s51, s48, s46
	v_add_co_u32 v29, vcc_lo, s49, v1
	v_lshlrev_b64 v[25:26], 3, v[25:26]
	v_add_co_ci_u32_e32 v30, vcc_lo, s51, v2, vcc_lo
	v_lshlrev_b64 v[27:28], 3, v[27:28]
	s_add_u32 s49, s50, s4
	s_addc_u32 s48, s48, s44
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v25, vcc_lo, s2, v25
	v_lshlrev_b64 v[29:30], 3, v[29:30]
	v_add_co_ci_u32_e32 v26, vcc_lo, s3, v26, vcc_lo
	v_add_co_u32 v27, vcc_lo, s2, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s3, v28, vcc_lo
	v_add_co_u32 v29, vcc_lo, s2, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s3, v30, vcc_lo
	s_add_i32 s50, s13, -1
                                        ; implicit-def: $sgpr51
	s_waitcnt vmcnt(4)
	global_store_b64 v[10:11], v[12:13], off offset:-8
	s_waitcnt vmcnt(3)
	global_store_b64 v[14:15], v[21:22], off offset:-8
	s_waitcnt vmcnt(2)
	global_store_b64 v[23:24], v[8:9], off offset:-8
	s_waitcnt vmcnt(1)
	global_store_b64 v[25:26], v[4:5], off offset:-8
	s_waitcnt vmcnt(0)
	global_store_b64 v[27:28], v[6:7], off offset:-8
	global_load_b64 v[14:15], v[29:30], off offset:-8
	s_mul_i32 s50, s50, s26
	v_add_co_u32 v10, vcc_lo, s49, v1
	v_add_co_ci_u32_e32 v11, vcc_lo, s48, v2, vcc_lo
	s_ashr_i32 s48, s50, 31
	s_add_u32 s49, s50, s4
	s_addc_u32 s48, s48, s44
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[23:24], v[12:13], v[14:15]
	v_add_co_u32 v12, vcc_lo, s49, v1
	v_add_co_ci_u32_e32 v13, vcc_lo, s48, v2, vcc_lo
	s_mov_b32 s49, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[25:26], 3, v[12:13]
	v_add_co_u32 v12, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v25
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v26, vcc_lo
	s_clause 0x1
	global_store_b64 v[12:13], v[14:15], off offset:-8
	global_store_b64 v[10:11], v[23:24], off offset:-8
	global_load_b64 v[14:15], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[14:15], v[21:22], v[14:15]
	v_add3_u32 v21, s47, -1, v1
	s_add_i32 s47, s15, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s47, s47, s26
	v_add3_u32 v21, v0, v21, v19
	s_ashr_i32 s48, s47, 31
	s_add_u32 s47, s47, s4
	s_addc_u32 s48, s48, s44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v22, 31, v21
	v_lshlrev_b64 v[21:22], 3, v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, s2, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
	global_store_b64 v[21:22], v[14:15], off
	global_load_b64 v[14:15], v[12:13], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[8:9], v[14:15]
	v_add_co_u32 v14, vcc_lo, s47, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s48, v2, vcc_lo
	s_mov_b32 s47, s4
	s_mov_b32 s48, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	global_store_b64 v[14:15], v[8:9], off offset:-8
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s50, s1
	s_xor_b32 s50, exec_lo, s50
	s_cbranch_execz .LBB2_109
; %bb.106:
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr51
	s_and_saveexec_b32 s52, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s52, exec_lo, s52
	s_cbranch_execz .LBB2_108
; %bb.107:
	s_add_i32 s51, s16, -1
	s_mov_b32 s48, exec_lo
	s_mul_i32 s51, s51, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_ashr_i32 s53, s51, 31
	s_add_u32 s54, s51, s49
	s_addc_u32 s53, s53, s46
	v_add_co_u32 v4, vcc_lo, s54, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s53, v2, vcc_lo
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b64 v[14:15], v[4:5], off offset:-8
.LBB2_108:                              ; %Flow2787
	s_or_b32 exec_lo, exec_lo, s52
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s48, s48, exec_lo
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr6_vgpr7
.LBB2_109:                              ; %Flow2786
	s_or_saveexec_b32 s50, s50
	v_mov_b32_e32 v19, s51
	s_xor_b32 exec_lo, exec_lo, s50
	s_cbranch_execz .LBB2_111
; %bb.110:
	global_load_b64 v[12:13], v[12:13], off offset:-8
	s_add_i32 s51, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s51, s51, s26
	s_ashr_i32 s52, s51, 31
	s_add_u32 s49, s51, s49
	s_addc_u32 s46, s52, s46
	s_ashr_i32 s51, s45, 31
	s_add_u32 s45, s45, s47
	s_addc_u32 s51, s51, s44
	s_waitcnt vmcnt(1)
	v_add_co_u32 v14, vcc_lo, s45, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s51, v2, vcc_lo
	s_add_i32 s45, s16, -1
	s_or_b32 s48, s48, exec_lo
	s_mul_i32 s45, s45, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_mov_b32_e32 v19, s45
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_clause 0x1
	global_load_b64 v[10:11], v[10:11], off offset:-8
	global_load_b64 v[14:15], v[14:15], off offset:-8
	v_add_co_u32 v25, vcc_lo, s49, v1
	v_add_co_ci_u32_e32 v26, vcc_lo, s46, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[25:26], 3, v[25:26]
	v_add_co_u32 v25, vcc_lo, s2, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v26, vcc_lo, s3, v26, vcc_lo
	global_load_b64 v[25:26], v[25:26], off offset:-8
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[21:22], null, v[12:13], v[12:13], 0.5
	v_div_scale_f64 v[29:30], vcc_lo, 0.5, v[12:13], 0.5
	s_waitcnt vmcnt(1)
	v_mul_f64 v[14:15], v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[23:24], v[21:22]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[4:5], v[4:5], v[25:26]
	v_fma_f64 v[10:11], v[10:11], v[10:11], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[27:28], -v[21:22], v[23:24], 1.0
	v_fma_f64 v[8:9], v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_fma_f64 v[27:28], -v[21:22], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	v_mul_f64 v[27:28], v[29:30], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], -v[21:22], v[27:28], v[29:30]
	v_div_fmas_f64 v[21:22], v[21:22], v[23:24], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[12:13], v[21:22], v[12:13], 0.5
	v_mul_f64 v[8:9], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[14:15], v[6:7], v[4:5], v[8:9]
.LBB2_111:                              ; %Flow2788
	s_or_b32 exec_lo, exec_lo, s50
	s_and_saveexec_b32 s45, s48
	s_cbranch_execz .LBB2_113
; %bb.112:                              ; %.loopexit2467.sink.split
	v_ashrrev_i32_e32 v4, 31, v19
	v_add_co_u32 v5, vcc_lo, v19, s47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s44, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v6, v2, vcc_lo
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[14:15], off offset:-8
.LBB2_113:                              ; %Flow2789
	s_or_b32 exec_lo, exec_lo, s45
.LBB2_114:                              ; %.loopexit2467
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
	v_cmp_eq_u32_e32 vcc_lo, 5, v3
	s_and_not1_b32 s20, s33, exec_lo
	s_and_b32 s33, vcc_lo, exec_lo
	s_or_b32 s33, s20, s33
.LBB2_115:                              ; %Flow2827
	s_or_b32 exec_lo, exec_lo, s27
	s_mov_b32 s20, 0
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr19
	s_and_saveexec_b32 s27, s33
	s_cbranch_execz .LBB2_129
; %bb.116:                              ; %.preheader2465.preheader
	s_add_i32 s20, s21, -1
	v_mul_lo_u32 v10, v16, s19
	v_mad_u64_u32 v[4:5], null, s20, s22, v[0:1]
	s_mov_b32 s20, 0xd9d7bdbb
	s_mov_b32 s21, 0x3ddb7cdf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v4, v4, v10, v18
	v_add_nc_u32_e32 v5, v4, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s34, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s35, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f64_e64 s20, |v[5:6]|, s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s21, s20
	s_xor_b32 s20, exec_lo, s21
	s_cbranch_execz .LBB2_120
; %bb.117:                              ; %.preheader
	s_cmp_lt_i32 s31, 1
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr10
	s_cbranch_scc1 .LBB2_120
; %bb.118:                              ; %.lr.ph2491
	v_add_nc_u32_e32 v5, -1, v1
	s_mov_b32 s21, s31
                                        ; implicit-def: $vgpr10
.LBB2_119:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s5, v5
	v_add_nc_u32_e32 v8, s4, v5
	v_add_nc_u32_e32 v5, s26, v5
	s_add_i32 s21, s21, -1
                                        ; implicit-def: $vgpr4
	s_cmp_eq_u32 s21, 0
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[6:7], off
	s_cbranch_scc0 .LBB2_119
.LBB2_120:                              ; %Flow2829
	s_or_saveexec_b32 s20, s20
	s_mov_b32 s21, 0
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr19
	s_xor_b32 exec_lo, exec_lo, s20
	s_cbranch_execz .LBB2_128
; %bb.121:
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s33, s7, -1
	s_add_i32 s21, s4, -1
	s_mul_i32 s44, s33, s26
	s_ashr_i32 s33, s4, 31
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_ashr_i32 s45, s44, 31
	s_add_u32 s44, s44, s4
	s_addc_u32 s45, s45, s33
	s_add_i32 s46, s8, -1
                                        ; implicit-def: $sgpr50
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s46, s46, s26
	v_add_co_u32 v6, vcc_lo, s28, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s29, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s40, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s41, v5, vcc_lo
	v_add_co_u32 v11, vcc_lo, s38, v4
	v_add_co_ci_u32_e32 v12, vcc_lo, s39, v5, vcc_lo
	v_add_co_u32 v13, vcc_lo, s36, v4
	v_add_co_ci_u32_e32 v14, vcc_lo, s37, v5, vcc_lo
	v_add_co_u32 v18, vcc_lo, s42, v4
	v_add_co_ci_u32_e32 v19, vcc_lo, s43, v5, vcc_lo
	global_load_b64 v[13:14], v[13:14], off
	global_load_b64 v[20:21], v[11:12], off
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[4:5], v[6:7], off
	global_load_b64 v[6:7], v[18:19], off
	v_add_co_u32 v11, vcc_lo, s44, v1
	v_add_co_ci_u32_e32 v12, vcc_lo, s45, v2, vcc_lo
	s_ashr_i32 s44, s46, 31
	s_add_u32 s45, s46, s4
	s_addc_u32 s44, s44, s33
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_add_i32 s46, s9, -1
	v_add_co_u32 v18, vcc_lo, s45, v1
	s_mul_i32 s46, s46, s26
	v_add_co_ci_u32_e32 v19, vcc_lo, s44, v2, vcc_lo
	s_ashr_i32 s44, s46, 31
	v_add_co_u32 v11, vcc_lo, s2, v11
	s_add_u32 s45, s46, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	s_addc_u32 s44, s44, s33
	v_lshlrev_b64 v[18:19], 3, v[18:19]
	v_add_co_u32 v22, vcc_lo, s45, v1
	s_add_i32 s46, s10, -1
	v_add_co_ci_u32_e32 v23, vcc_lo, s44, v2, vcc_lo
	s_mul_i32 s46, s46, s26
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, s2, v18
	s_ashr_i32 s44, s46, 31
	s_add_u32 s45, s46, s4
	s_addc_u32 s44, s44, s33
	s_add_i32 s46, s11, -1
	v_lshlrev_b64 v[22:23], 3, v[22:23]
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
	s_mul_i32 s46, s46, s26
	v_add_co_u32 v24, vcc_lo, s45, v1
	v_add_co_ci_u32_e32 v25, vcc_lo, s44, v2, vcc_lo
	s_ashr_i32 s44, s46, 31
	s_add_u32 s45, s46, s4
	s_addc_u32 s46, s44, s33
	s_add_i32 s47, s12, -1
	v_add_co_u32 v22, vcc_lo, s2, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s3, v23, vcc_lo
	s_mul_i32 s47, s47, s26
	v_add_co_u32 v26, vcc_lo, s45, v1
	s_ashr_i32 s44, s5, 31
	s_ashr_i32 s45, s47, 31
	v_add_co_ci_u32_e32 v27, vcc_lo, s46, v2, vcc_lo
	s_add_u32 s46, s47, s5
	s_addc_u32 s48, s45, s44
	v_add_co_u32 v28, vcc_lo, s46, v1
	v_lshlrev_b64 v[24:25], 3, v[24:25]
	v_add_co_ci_u32_e32 v29, vcc_lo, s48, v2, vcc_lo
	v_lshlrev_b64 v[26:27], 3, v[26:27]
	s_add_u32 s46, s47, s4
	s_addc_u32 s45, s45, s33
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v24, vcc_lo, s2, v24
	v_lshlrev_b64 v[28:29], 3, v[28:29]
	v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
	v_add_co_u32 v26, vcc_lo, s2, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s3, v27, vcc_lo
	v_add_co_u32 v28, vcc_lo, s2, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
	s_add_i32 s47, s13, -1
	s_mov_b32 s48, s5
	s_mul_i32 s47, s47, s26
	s_waitcnt vmcnt(4)
	global_store_b64 v[11:12], v[13:14], off offset:-8
	s_waitcnt vmcnt(3)
	global_store_b64 v[18:19], v[20:21], off offset:-8
	s_waitcnt vmcnt(2)
	global_store_b64 v[22:23], v[8:9], off offset:-8
	s_waitcnt vmcnt(1)
	global_store_b64 v[24:25], v[4:5], off offset:-8
	s_waitcnt vmcnt(0)
	global_store_b64 v[26:27], v[6:7], off offset:-8
	global_load_b64 v[18:19], v[28:29], off offset:-8
	v_add_co_u32 v11, vcc_lo, s46, v1
	v_add_co_ci_u32_e32 v12, vcc_lo, s45, v2, vcc_lo
	s_ashr_i32 s45, s47, 31
	s_add_u32 s46, s47, s4
	s_addc_u32 s45, s45, s33
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[22:23], v[13:14], v[18:19]
	v_add_co_u32 v13, vcc_lo, s46, v1
	v_add_co_ci_u32_e32 v14, vcc_lo, s45, v2, vcc_lo
	s_add_i32 s45, s14, -1
	s_add_i32 s46, s15, -1
	s_mul_i32 s45, s45, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[24:25], 3, v[13:14]
	v_add_co_u32 v14, vcc_lo, s2, v11
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v12, vcc_lo
	v_add3_u32 v11, s45, s21, v1
	v_add_co_u32 v12, vcc_lo, s2, v24
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v10, v0, v11, v10
	s_mul_i32 s46, s46, s26
	s_clause 0x1
	global_store_b64 v[14:15], v[18:19], off offset:-8
	global_store_b64 v[12:13], v[22:23], off offset:-8
	global_load_b64 v[18:19], v[14:15], off offset:-8
	v_ashrrev_i32_e32 v11, 31, v10
	s_ashr_i32 s47, s46, 31
	s_add_u32 s46, s46, s4
	s_addc_u32 s47, s47, s33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v10, vcc_lo, s2, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[18:19], v[20:21], v[18:19]
	global_store_b64 v[10:11], v[18:19], off
	global_load_b64 v[10:11], v[14:15], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[10:11], v[8:9], v[10:11]
	v_add_co_u32 v8, vcc_lo, s46, v1
	v_add_co_ci_u32_e32 v9, vcc_lo, s47, v2, vcc_lo
	s_mov_b32 s47, s4
	s_mov_b32 s46, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_u32 v8, vcc_lo, s2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_store_b64 v[8:9], v[10:11], off offset:-8
                                        ; implicit-def: $vgpr8_vgpr9
	s_and_saveexec_b32 s49, s1
	s_xor_b32 s49, exec_lo, s49
	s_cbranch_execz .LBB2_125
; %bb.122:
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $sgpr50
	s_and_saveexec_b32 s51, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s51, exec_lo, s51
	s_cbranch_execz .LBB2_124
; %bb.123:
	s_add_i32 s50, s16, -1
	s_mov_b32 s46, exec_lo
	s_mul_i32 s50, s50, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s52, s50, 31
	s_add_u32 s53, s50, s48
	s_addc_u32 s52, s52, s44
	v_add_co_u32 v4, vcc_lo, s53, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s52, v2, vcc_lo
	s_add_i32 s50, s50, s21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b64 v[8:9], v[4:5], off offset:-8
.LBB2_124:                              ; %Flow2832
	s_or_b32 exec_lo, exec_lo, s51
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s46, s46, exec_lo
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr6_vgpr7
.LBB2_125:                              ; %Flow2831
	s_or_saveexec_b32 s49, s49
	v_mov_b32_e32 v19, s50
	s_xor_b32 exec_lo, exec_lo, s49
	s_cbranch_execz .LBB2_127
; %bb.126:
	global_load_b64 v[8:9], v[14:15], off offset:-8
	s_add_i32 s50, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s50, s50, s26
	s_ashr_i32 s51, s50, 31
	s_add_u32 s48, s50, s48
	s_addc_u32 s44, s51, s44
	s_ashr_i32 s50, s45, 31
	s_add_u32 s45, s45, s47
	s_addc_u32 s33, s50, s33
	v_add_co_u32 v14, vcc_lo, s45, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s33, v2, vcc_lo
	s_add_i32 s33, s16, -1
	s_or_b32 s46, s46, exec_lo
	s_mul_i32 s33, s33, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	s_add_i32 s21, s33, s21
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_clause 0x1
	global_load_b64 v[12:13], v[12:13], off offset:-8
	global_load_b64 v[14:15], v[14:15], off offset:-8
	v_add_co_u32 v22, vcc_lo, s48, v1
	v_add_co_ci_u32_e32 v23, vcc_lo, s44, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[22:23], 3, v[22:23]
	v_add_co_u32 v22, vcc_lo, s2, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v23, vcc_lo, s3, v23, vcc_lo
	global_load_b64 v[22:23], v[22:23], off offset:-8
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[18:19], null, v[8:9], v[8:9], 0.5
	v_div_scale_f64 v[26:27], vcc_lo, 0.5, v[8:9], 0.5
	s_waitcnt vmcnt(1)
	v_mul_f64 v[14:15], v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[20:21], v[18:19]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[4:5], v[4:5], v[22:23]
	v_fma_f64 v[12:13], v[12:13], v[12:13], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[18:19], v[20:21], 1.0
	v_fma_f64 v[10:11], v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	v_fma_f64 v[24:25], -v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	v_mul_f64 v[24:25], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[18:19], v[24:25], v[26:27]
	v_div_fmas_f64 v[18:19], v[18:19], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[8:9], v[18:19], v[8:9], 0.5
	v_mov_b32_e32 v19, s21
	v_mul_f64 v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[4:5], v[8:9]
.LBB2_127:                              ; %Flow2833
	s_or_b32 exec_lo, exec_lo, s49
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s21, s46, exec_lo
.LBB2_128:                              ; %Flow2830
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s20, s21, exec_lo
.LBB2_129:                              ; %Flow2828
	s_or_b32 exec_lo, exec_lo, s27
	s_and_saveexec_b32 s21, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s21, exec_lo, s21
	s_cbranch_execz .LBB2_147
; %bb.130:                              ; %LeafBlock2723
	s_mov_b32 s27, s20
	s_mov_b32 s25, exec_lo
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr19
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB2_146
; %bb.131:                              ; %.preheader2480.preheader
	v_mul_lo_u32 v3, v17, s24
	v_mul_lo_u32 v4, v16, s22
	s_waitcnt lgkmcnt(0)
	s_add_i32 s23, s23, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v4, v0, v3
	v_mad_u64_u32 v[4:5], null, s23, s30, v[3:4]
	s_mov_b32 s22, 0xd9d7bdbb
	s_mov_b32 s23, 0x3ddb7cdf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s34, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s35, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f64_e64 s22, |v[4:5]|, s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s23, s22
	s_xor_b32 s22, exec_lo, s23
	s_cbranch_execz .LBB2_135
; %bb.132:                              ; %.preheader2478
	s_cmp_lt_i32 s31, 1
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr1_vgpr2
	s_cbranch_scc1 .LBB2_135
; %bb.133:                              ; %.lr.ph
	v_add_nc_u32_e32 v4, -1, v1
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr0
.LBB2_134:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s5, v4
	s_add_i32 s31, s31, -1
	s_cmp_eq_u32 s31, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b64 v[5:6], v[2:3], off
	v_add_nc_u32_e32 v2, s4, v4
	v_add_nc_u32_e32 v4, s26, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v3, vcc_lo
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr1_vgpr2
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[5:6], off
	s_cbranch_scc0 .LBB2_134
.LBB2_135:                              ; %Flow2836
	s_or_saveexec_b32 s22, s22
	s_mov_b32 s23, s20
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr19
	s_xor_b32 exec_lo, exec_lo, s22
	s_cbranch_execz .LBB2_145
; %bb.136:
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_i32 s23, s7, -1
	s_add_i32 s7, s4, -1
	s_mul_i32 s24, s23, s26
	s_ashr_i32 s23, s4, 31
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_ashr_i32 s27, s24, 31
	s_add_u32 s24, s24, s4
	s_addc_u32 s27, s27, s23
	s_add_i32 s8, s8, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s8, s8, s26
	v_add_co_u32 v5, vcc_lo, s28, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s29, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, s40, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s41, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, s38, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s39, v4, vcc_lo
	v_add_co_u32 v11, vcc_lo, s36, v3
	v_add_co_ci_u32_e32 v12, vcc_lo, s37, v4, vcc_lo
	v_add_co_u32 v13, vcc_lo, s42, v3
	v_add_co_ci_u32_e32 v14, vcc_lo, s43, v4, vcc_lo
	global_load_b64 v[11:12], v[11:12], off
	global_load_b64 v[17:18], v[9:10], off
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[3:4], v[5:6], off
	global_load_b64 v[5:6], v[13:14], off
	v_add_co_u32 v9, vcc_lo, s24, v1
	v_add_co_ci_u32_e32 v10, vcc_lo, s27, v2, vcc_lo
	s_ashr_i32 s24, s8, 31
	s_add_u32 s8, s8, s4
	s_addc_u32 s24, s24, s23
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	s_add_i32 s9, s9, -1
	v_add_co_u32 v13, vcc_lo, s8, v1
	s_mul_i32 s9, s9, s26
	v_add_co_ci_u32_e32 v14, vcc_lo, s24, v2, vcc_lo
	s_ashr_i32 s8, s9, 31
	v_add_co_u32 v9, vcc_lo, s2, v9
	s_add_u32 s9, s9, s4
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	s_addc_u32 s8, s8, s23
	v_lshlrev_b64 v[13:14], 3, v[13:14]
	v_add_co_u32 v19, vcc_lo, s9, v1
	s_add_i32 s10, s10, -1
	v_add_co_ci_u32_e32 v20, vcc_lo, s8, v2, vcc_lo
	s_mul_i32 s10, s10, s26
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, s2, v13
	s_ashr_i32 s8, s10, 31
	s_add_u32 s9, s10, s4
	s_addc_u32 s8, s8, s23
	s_add_i32 s10, s11, -1
	v_lshlrev_b64 v[19:20], 3, v[19:20]
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
	s_mul_i32 s10, s10, s26
	v_add_co_u32 v21, vcc_lo, s9, v1
	v_add_co_ci_u32_e32 v22, vcc_lo, s8, v2, vcc_lo
	s_ashr_i32 s8, s10, 31
	s_add_u32 s9, s10, s4
	s_addc_u32 s10, s8, s23
	s_add_i32 s11, s12, -1
	v_add_co_u32 v19, vcc_lo, s2, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s3, v20, vcc_lo
	s_mul_i32 s11, s11, s26
	v_add_co_u32 v23, vcc_lo, s9, v1
	s_ashr_i32 s8, s5, 31
	s_ashr_i32 s9, s11, 31
	v_add_co_ci_u32_e32 v24, vcc_lo, s10, v2, vcc_lo
	s_add_u32 s10, s11, s5
	s_addc_u32 s12, s9, s8
	v_add_co_u32 v25, vcc_lo, s10, v1
	v_lshlrev_b64 v[21:22], 3, v[21:22]
	v_add_co_ci_u32_e32 v26, vcc_lo, s12, v2, vcc_lo
	v_lshlrev_b64 v[23:24], 3, v[23:24]
	s_add_u32 s10, s11, s4
	s_addc_u32 s9, s9, s23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v21, vcc_lo, s2, v21
	v_lshlrev_b64 v[25:26], 3, v[25:26]
	v_add_co_ci_u32_e32 v22, vcc_lo, s3, v22, vcc_lo
	v_add_co_u32 v23, vcc_lo, s2, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s3, v24, vcc_lo
	v_add_co_u32 v25, vcc_lo, s2, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, s3, v26, vcc_lo
	s_add_i32 s11, s13, -1
	s_mov_b32 s12, s5
	s_mul_i32 s11, s11, s26
                                        ; implicit-def: $sgpr13
	s_waitcnt vmcnt(4)
	global_store_b64 v[9:10], v[11:12], off offset:-8
	s_waitcnt vmcnt(3)
	global_store_b64 v[13:14], v[17:18], off offset:-8
	s_waitcnt vmcnt(2)
	global_store_b64 v[19:20], v[7:8], off offset:-8
	s_waitcnt vmcnt(1)
	global_store_b64 v[21:22], v[3:4], off offset:-8
	s_waitcnt vmcnt(0)
	global_store_b64 v[23:24], v[5:6], off offset:-8
	global_load_b64 v[19:20], v[25:26], off offset:-8
	v_add_co_u32 v9, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v2, vcc_lo
	s_ashr_i32 s9, s11, 31
	s_add_u32 s10, s11, s4
	s_addc_u32 s9, s9, s23
	v_add_co_u32 v14, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v2, vcc_lo
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	s_add_i32 s9, s14, -1
	s_add_i32 s10, s15, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[21:22], 3, v[14:15]
	s_mul_i32 s9, s9, s26
	s_mul_i32 s10, s10, s26
	v_add_co_u32 v14, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v10, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v21
	v_mul_lo_u32 v9, v16, s19
	v_add3_u32 v16, s9, s7, v1
	s_ashr_i32 s11, s10, 31
	s_add_u32 s10, s10, s4
	s_addc_u32 s11, s11, s23
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v16, v0, v16, v9
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[11:12], v[19:20]
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v22, vcc_lo
	s_clause 0x1
	global_store_b64 v[14:15], v[19:20], off offset:-8
	global_store_b64 v[10:11], v[12:13], off offset:-8
	global_load_b64 v[12:13], v[14:15], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[17:18], v[12:13]
	v_ashrrev_i32_e32 v17, 31, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[16:17]
	v_add_co_u32 v16, vcc_lo, s2, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
	global_store_b64 v[16:17], v[12:13], off
	global_load_b64 v[12:13], v[14:15], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[7:8], v[12:13]
	v_add_co_u32 v7, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v2, vcc_lo
	s_mov_b32 s11, s4
	s_mov_b32 s10, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_add_co_u32 v7, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_store_b64 v[7:8], v[12:13], off offset:-8
                                        ; implicit-def: $vgpr8_vgpr9
	s_and_saveexec_b32 s14, s1
	s_xor_b32 s1, exec_lo, s14
	s_cbranch_execz .LBB2_140
; %bb.137:
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $sgpr13
	s_and_saveexec_b32 s14, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s14
	s_cbranch_execz .LBB2_139
; %bb.138:
	s_add_i32 s13, s16, -1
	s_mov_b32 s10, exec_lo
	s_mul_i32 s13, s13, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_ashr_i32 s14, s13, 31
	s_add_u32 s15, s13, s12
	s_addc_u32 s14, s14, s8
	v_add_co_u32 v3, vcc_lo, s15, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s14, v2, vcc_lo
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b64 v[8:9], v[2:3], off offset:-8
.LBB2_139:                              ; %Flow2839
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s10, s10, exec_lo
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr5_vgpr6
                                        ; implicit-def: $vgpr1_vgpr2
.LBB2_140:                              ; %Flow2838
	s_or_saveexec_b32 s0, s1
	v_mov_b32_e32 v0, s13
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB2_142
; %bb.141:
	global_load_b64 v[7:8], v[14:15], off offset:-8
	s_add_i32 s1, s17, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s26
	s_ashr_i32 s13, s1, 31
	s_add_u32 s1, s1, s12
	s_addc_u32 s8, s13, s8
	s_ashr_i32 s12, s9, 31
	s_add_u32 s9, s9, s11
	s_addc_u32 s11, s12, s23
	v_add_co_u32 v14, vcc_lo, s9, v1
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v2, vcc_lo
	s_or_b32 s10, s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v14, vcc_lo, s2, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	s_clause 0x1
	global_load_b64 v[9:10], v[10:11], off offset:-8
	global_load_b64 v[14:15], v[14:15], off offset:-8
	v_add_co_u32 v20, vcc_lo, s1, v1
	v_add_co_ci_u32_e32 v21, vcc_lo, s8, v2, vcc_lo
	s_add_i32 s1, s16, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s26
	v_lshlrev_b64 v[20:21], 3, v[20:21]
	v_mov_b32_e32 v0, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, s2, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
	global_load_b64 v[20:21], v[20:21], off offset:-8
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[16:17], null, v[7:8], v[7:8], 0.5
	v_div_scale_f64 v[24:25], vcc_lo, 0.5, v[7:8], 0.5
	s_waitcnt vmcnt(1)
	v_mul_f64 v[14:15], v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[2:3], v[3:4], v[20:21]
	v_fma_f64 v[9:10], v[9:10], v[9:10], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[22:23], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[9:10], v[12:13], v[12:13], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
	v_fma_f64 v[22:23], -v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
	v_mul_f64 v[22:23], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[16:17], v[22:23], v[24:25]
	v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[7:8], v[16:17], v[7:8], 0.5
	v_mul_f64 v[7:8], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[8:9], v[5:6], v[2:3], v[7:8]
.LBB2_142:                              ; %Flow2840
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, s20
                                        ; implicit-def: $vgpr19
	s_and_saveexec_b32 s1, s10
; %bb.143:                              ; %.loopexit2479.sink.split
	v_add_nc_u32_e32 v19, s7, v0
	s_or_b32 s0, s20, exec_lo
; %bb.144:                              ; %Flow2841
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s20, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s23, s1, s0
.LBB2_145:                              ; %Flow2837
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s20, exec_lo
	s_and_b32 s1, s23, exec_lo
	s_or_b32 s27, s0, s1
.LBB2_146:                              ; %Flow2835
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s20, exec_lo
	s_and_b32 s1, s27, exec_lo
	s_or_b32 s20, s0, s1
.LBB2_147:                              ; %Flow2834
	s_or_b32 exec_lo, exec_lo, s21
	s_and_saveexec_b32 s0, s20
	s_cbranch_execz .LBB2_149
; %bb.148:                              ; %.loopexit2464.sink.split
	v_add_nc_u32_e32 v2, v19, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[8:9], off
.LBB2_149:                              ; %.loopexit2464
	s_or_b32 exec_lo, exec_lo, s0
	s_cmp_lt_i32 s18, 1
	s_cbranch_scc1 .LBB2_152
; %bb.150:                              ; %.lr.ph2493
	v_add_nc_u32_e32 v0, -1, v1
.LBB2_151:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s5, v0
	v_add_nc_u32_e32 v3, s4, v0
	s_add_i32 s18, s18, -1
	s_cmp_lg_u32 s18, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[1:2], v[1:2], off
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], -v[3:4]
	v_add_nc_u32_e32 v3, s6, v0
	v_add_nc_u32_e32 v0, s26, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_store_b64 v[3:4], v[1:2], off
	s_cbranch_scc1 .LBB2_151
.LBB2_152:                              ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 584
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 59
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii, .Lfunc_end2-_Z27imqqtu_dirichlet_gpu_kernelPdiiiiiiiidiiiiiiiiiiiiiiiiiiiiiiiiPcPiS_S_S_S_S_S_S_S_S_S_S_S_S0_S_S_S_S_idiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 12404
; NumSgprs: 61
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 61
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
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	.end_amdgpu_metadata
