extern "C" { 
    
__global__ void gamma_transform_2(float3* d_idata, float3* d_odata, int width, int height, float gamma)  
    {  
      int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
      int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
      int idx = yIndex * width + xIndex;
     if (xIndex < width && yIndex < height){
        float3 rgb = d_idata[idx];
        d_odata[idx].x = powf(rgb.x, gamma);
        d_odata[idx].y = powf(rgb.y, gamma);
        d_odata[idx].z = powf(rgb.z, gamma);
     }
           
    }

}
	.file	"tmpxft_00244af5_00000000-6_06-gamma-transform.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif
	.type	_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif, @function
_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	gamma_transform_2(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif, .-_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif
	.globl	gamma_transform_2
	.type	gamma_transform_2, @function
gamma_transform_2:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif
	.cfi_endproc
.LFE2033:
	.size	gamma_transform_2, .-gamma_transform_2
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"gamma_transform_2"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	gamma_transform_2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C" { 
    
__global__ void gamma_transform_2(float3* d_idata, float3* d_odata, int width, int height, float gamma)  
    {  
      int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
      int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
      int idx = yIndex * width + xIndex;
     if (xIndex < width && yIndex < height){
        float3 rgb = d_idata[idx];
        d_odata[idx].x = powf(rgb.x, gamma);
        d_odata[idx].y = powf(rgb.y, gamma);
        d_odata[idx].z = powf(rgb.z, gamma);
     }
           
    }

}
	.text
	.file	"06-gamma-transform.hip"
	.globl	__device_stub__gamma_transform_2 # -- Begin function __device_stub__gamma_transform_2
	.type	__device_stub__gamma_transform_2,@function
__device_stub__gamma_transform_2:       # @__device_stub__gamma_transform_2
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$gamma_transform_2, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__gamma_transform_2, .Lfunc_end0-__device_stub__gamma_transform_2
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$gamma_transform_2, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	gamma_transform_2,@object       # @gamma_transform_2
	.section	.rodata,"a",@progbits
	.globl	gamma_transform_2
	.p2align	3, 0x0
gamma_transform_2:
	.quad	__device_stub__gamma_transform_2
	.size	gamma_transform_2, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"gamma_transform_2"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__gamma_transform_2
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym gamma_transform_2
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	gamma_transform_2       ; -- Begin function gamma_transform_2
	.globl	gamma_transform_2
	.p2align	8
	.type	gamma_transform_2,@function
gamma_transform_2:                      ; @gamma_transform_2
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	s_mov_b32 s13, 0x3e76c4e1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[0:1], null, v2, 12, s[0:1]
	global_load_b96 v[5:7], v[0:1], off
	v_mad_i64_i32 v[0:1], null, v2, 12, s[2:3]
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v5
	v_cndmask_b32_e64 v2, 1.0, s6, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_trunc_f32_e32 v8, v2
	v_cndmask_b32_e64 v3, 1.0, s6, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v7
	v_mul_f32_e32 v9, 0.5, v2
	v_cmp_gt_f32_e64 s5, 0, v2
	v_cmp_eq_f32_e64 s2, v8, v2
	v_cmp_neq_f32_e64 s12, v3, |v3|
	v_cndmask_b32_e64 v4, 1.0, s6, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	v_trunc_f32_e32 v8, v9
	v_cmp_gt_f32_e64 s6, 0, v3
	v_cmp_neq_f32_e64 s7, v2, |v2|
	v_trunc_f32_e32 v12, v4
	v_cndmask_b32_e32 v5, 1.0, v5, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v3
	v_mul_f32_e32 v13, 0.5, v4
	v_cmp_neq_f32_e64 s10, v8, v9
	v_cmp_eq_f32_e64 s4, v12, v4
	v_trunc_f32_e32 v10, v3
	v_cndmask_b32_e32 v6, 1.0, v6, vcc_lo
	v_frexp_mant_f32_e64 v14, |v5|
	v_cmp_neq_f32_e32 vcc_lo, 0, v4
	v_trunc_f32_e32 v12, v13
	v_cmp_lt_f32_e64 s11, |v5|, 1.0
	v_cmp_lt_f32_e64 s18, |v6|, 1.0
	v_cmp_gt_f32_e64 s9, 0x3f2aaaab, v14
	v_cndmask_b32_e32 v7, 1.0, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v5
	v_cmp_eq_f32_e64 s0, 0, v6
	v_frexp_mant_f32_e64 v16, |v6|
	v_cndmask_b32_e64 v20, 0, 1, s9
	v_mul_f32_e32 v11, 0.5, v3
	s_xor_b32 s5, s5, vcc_lo
	s_xor_b32 s7, s7, s11
	v_cndmask_b32_e64 v8, 0x7f800000, 0, s5
	s_xor_b32 s5, s12, s18
	v_cmp_gt_f32_e64 s11, 0x3f2aaaab, v16
	v_cndmask_b32_e64 v23, |v3|, 0, s5
	s_xor_b32 s5, s6, s0
	v_cmp_neq_f32_e64 s6, v12, v13
	v_ldexp_f32 v13, v14, v20
	v_cmp_neq_f32_e64 s17, v4, |v4|
	v_cmp_gt_f32_e64 s8, 0, v4
	v_frexp_exp_i32_f32_e32 v15, v5
	v_cmp_eq_f32_e64 s3, v10, v3
	v_add_f32_e32 v26, -1.0, v13
	v_frexp_mant_f32_e64 v18, |v7|
	v_cmp_lt_f32_e64 s19, |v7|, 1.0
	v_cmp_eq_f32_e64 s1, 0, v7
	v_trunc_f32_e32 v10, v11
	v_cndmask_b32_e64 v22, 0, 1, s11
	v_cmp_gt_f32_e64 s12, 0x3f2aaaab, v18
	v_cndmask_b32_e64 v9, 0x7f800000, 0, s5
	s_xor_b32 s5, s17, s19
	v_cndmask_b32_e64 v21, |v2|, 0, s7
	v_cndmask_b32_e64 v12, |v4|, 0, s5
	s_xor_b32 s5, s8, s1
	v_cmp_neq_f32_e64 s7, v10, v11
	v_cndmask_b32_e64 v24, 0, 1, s12
	v_cndmask_b32_e64 v10, 0x7f800000, 0, s5
	v_subrev_co_ci_u32_e64 v14, s5, 0, v15, s9
	v_ldexp_f32 v15, v16, v22
	s_delay_alu instid0(VALU_DEP_4)
	v_ldexp_f32 v16, v18, v24
	v_add_f32_e32 v18, 1.0, v13
	v_frexp_exp_i32_f32_e32 v17, v6
	v_frexp_exp_i32_f32_e32 v19, v7
	v_add_f32_e32 v20, 1.0, v15
	v_add_f32_e32 v22, 1.0, v16
	v_rcp_f32_e32 v24, v18
	v_dual_add_f32 v28, -1.0, v15 :: v_dual_add_f32 v29, -1.0, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v25, v20
	v_rcp_f32_e32 v27, v22
	v_add_f32_e32 v31, -1.0, v18
	v_add_f32_e32 v33, -1.0, v20
	v_subrev_co_ci_u32_e64 v17, s8, 0, v17, s11
	v_subrev_co_ci_u32_e64 v19, s8, 0, v19, s12
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
	v_mul_f32_e32 v30, v26, v24
	v_cvt_f32_i32_e32 v14, v14
	v_mul_f32_e32 v32, v28, v25
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v34, v29, v27
	v_add_f32_e32 v36, -1.0, v22
	v_mul_f32_e32 v35, v18, v30
	v_cvt_f32_i32_e32 v17, v17
	v_mul_f32_e32 v37, v20, v32
	v_dual_sub_f32 v13, v13, v31 :: v_dual_sub_f32 v16, v16, v36
	v_sub_f32_e32 v15, v15, v33
	v_fma_f32 v18, v30, v18, -v35
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v20, v32, v20, -v37
	v_mul_f32_e32 v31, v22, v34
	v_cvt_f32_i32_e32 v19, v19
	v_cmp_eq_f32_e64 s8, |v5|, 1.0
	v_dual_fmac_f32 v18, v30, v13 :: v_dual_mul_f32 v13, 0x3f317218, v14
	v_fmac_f32_e32 v20, v32, v15
	v_fma_f32 v22, v34, v22, -v31
	v_mul_f32_e32 v15, 0x3f317218, v17
	v_mul_f32_e32 v33, 0x3f317218, v19
	v_fma_f32 v38, 0x3f317218, v14, -v13
	v_add_f32_e32 v36, v37, v20
	v_fmac_f32_e32 v22, v34, v16
	v_add_f32_e32 v16, v35, v18
	s_and_b32 s5, s2, s10
	v_fmac_f32_e32 v38, 0xb102e308, v14
	v_cndmask_b32_e64 v11, 1.0, v5, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_add_f32 v39, v31, v22 :: v_dual_sub_f32 v40, v26, v16
	v_sub_f32_e32 v41, v28, v36
	v_sub_f32_e32 v35, v16, v35
	s_and_b32 s7, s3, s7
	v_sub_f32_e32 v42, v29, v39
	v_dual_sub_f32 v26, v26, v40 :: v_dual_sub_f32 v31, v39, v31
	v_sub_f32_e32 v28, v28, v41
	v_dual_sub_f32 v37, v36, v37 :: v_dual_sub_f32 v18, v35, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v29, v29, v42 :: v_dual_sub_f32 v16, v26, v16
	v_sub_f32_e32 v26, v28, v36
	v_sub_f32_e32 v22, v31, v22
	s_and_b32 s6, s4, s6
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v28, v29, v39
	v_add_f32_e32 v16, v18, v16
	v_fma_f32 v18, 0x3f317218, v17, -v15
	v_cmp_class_f32_e64 s14, v5, 0x204
	v_cmp_class_f32_e64 s15, v6, 0x204
	v_add_f32_e32 v22, v22, v28
	v_sub_f32_e32 v20, v37, v20
	v_fmac_f32_e32 v18, 0xb102e308, v17
	v_cmp_class_f32_e64 s16, v7, 0x204
	s_or_b32 vcc_lo, vcc_lo, s14
	v_add_f32_e32 v17, v42, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v22, v15, v18
	v_dual_mul_f32 v17, v27, v17 :: v_dual_add_f32 v20, v20, v26
	v_fma_f32 v26, 0x3f317218, v19, -v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, v22, v15
	v_dual_add_f32 v27, v34, v17 :: v_dual_add_f32 v14, v41, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v26, 0xb102e308, v19 :: v_dual_add_f32 v19, v13, v38
	v_mul_f32_e32 v14, v25, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v25, v33, v26 :: v_dual_add_f32 v16, v40, v16
	v_dual_sub_f32 v13, v19, v13 :: v_dual_mul_f32 v16, v24, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v24, v32, v14
	v_add_f32_e32 v20, v30, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v31, v24, v24
	v_dual_sub_f32 v15, v18, v15 :: v_dual_sub_f32 v28, v20, v30
	v_mul_f32_e32 v29, v20, v20
	v_sub_f32_e32 v30, v24, v32
	v_dual_sub_f32 v32, v27, v34 :: v_dual_sub_f32 v13, v38, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v16, v16, v28
	v_fma_f32 v34, v20, v20, -v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v14, v14, v30
	v_mul_f32_e32 v28, v27, v27
	v_add_f32_e32 v30, v16, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v35, v27, v27, -v28
	v_fmac_f32_e32 v34, v20, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v30, v29, v34
	v_fmaak_f32 v41, s13, v30, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmaak_f32 v41, v30, v41, 0x3ecccdef
	v_sub_f32_e32 v17, v17, v32
	v_fma_f32 v32, v24, v24, -v31
	v_add_f32_e32 v37, v17, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v27, v37
	v_add_f32_e32 v40, v28, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v45, s13, v40, 0x3e91f4c4
	v_fmaak_f32 v45, v40, v45, 0x3ecccdef
	v_sub_f32_e32 v28, v40, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v49, v40, v45 :: v_dual_sub_f32 v28, v35, v28
	v_dual_mul_f32 v46, v27, v40 :: v_dual_sub_f32 v29, v30, v29
	v_dual_mul_f32 v42, v20, v30 :: v_dual_mul_f32 v47, v30, v41
	v_fma_f32 v35, v40, v27, -v46
	v_add_f32_e32 v36, v14, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v29, v34, v29
	v_fma_f32 v34, v30, v20, -v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v35, v40, v17
	v_fmac_f32_e32 v32, v24, v36
	v_ldexp_f32 v36, v20, 1
	v_ldexp_f32 v17, v17, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v39, v31, v32
	v_fmaak_f32 v43, s13, v39, 0x3e91f4c4
	v_sub_f32_e32 v31, v39, v31
	v_mul_f32_e32 v44, v24, v39
	v_ldexp_f32 v37, v24, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v43, v39, v43, 0x3ecccdef
	v_sub_f32_e32 v31, v32, v31
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v32, v39, v24, -v44
	v_fmac_f32_e32 v34, v30, v16
	v_fma_f32 v30, v30, v41, -v47
	v_mul_f32_e32 v48, v39, v43
	v_ldexp_f32 v16, v16, 1
	v_fmac_f32_e32 v32, v39, v14
	v_ldexp_f32 v14, v14, 1
	v_fmac_f32_e32 v30, v29, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v32, v31, v24
	v_fma_f32 v24, v40, v45, -v49
	v_fmac_f32_e32 v24, v28, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v41, v49, v24
	v_add_f32_e32 v50, 0x3f2aaaaa, v41
	v_sub_f32_e32 v49, v41, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v24, v24, v49 :: v_dual_add_f32 v49, 0xbf2aaaaa, v50
	v_dual_fmac_f32 v35, v28, v27 :: v_dual_add_f32 v28, v47, v30
	v_dual_add_f32 v24, 0x31739010, v24 :: v_dual_sub_f32 v41, v41, v49
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v45, v28, v47 :: v_dual_fmac_f32 v34, v29, v20
	v_fma_f32 v20, v39, v43, -v48
	v_add_f32_e32 v24, v24, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v20, v31, v43 :: v_dual_add_f32 v31, v44, v32
	v_add_f32_e32 v43, 0x3f2aaaaa, v28
	v_add_f32_e32 v39, v48, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v47, 0x3f2aaaaa, v39 :: v_dual_sub_f32 v48, v39, v48
	v_sub_f32_e32 v20, v20, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v48, 0xbf2aaaaa, v47
	v_dual_sub_f32 v39, v39, v48 :: v_dual_sub_f32 v30, v30, v45
	v_add_f32_e32 v45, 0xbf2aaaaa, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v30, 0x31739010, v30
	v_sub_f32_e32 v28, v28, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v28, v30, v28
	v_dual_add_f32 v40, v46, v35 :: v_dual_add_f32 v41, v43, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v43, v43, v41
	v_dual_add_f32 v29, v42, v34 :: v_dual_add_f32 v28, v28, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v45, v29, v41
	v_sub_f32_e32 v30, v29, v42
	v_sub_f32_e32 v42, v40, v46
	v_fma_f32 v43, v29, v41, -v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v30, v34, v30 :: v_dual_fmac_f32 v43, v29, v28
	v_dual_fmac_f32 v43, v30, v41 :: v_dual_add_f32 v20, 0x31739010, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v20, v20, v39 :: v_dual_sub_f32 v39, v31, v44
	v_add_f32_e32 v44, v47, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v28, v32, v39
	v_sub_f32_e32 v46, v47, v44
	v_mul_f32_e32 v47, v31, v44
	v_add_f32_e32 v34, v50, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v20, v20, v46
	v_fma_f32 v46, v31, v44, -v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v48, v50, v34
	v_dual_mul_f32 v49, v40, v34 :: v_dual_fmac_f32 v46, v31, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v24, v24, v48
	v_fma_f32 v48, v40, v34, -v49
	v_sub_f32_e32 v20, v35, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v46, v28, v44
	v_fmac_f32_e32 v48, v40, v24
	v_ldexp_f32 v24, v27, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v27, v47, v46
	v_fmac_f32_e32 v48, v20, v34
	v_add_f32_e32 v20, v45, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v31, v27, v47
	v_sub_f32_e32 v29, v20, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v30, v36, v20 :: v_dual_sub_f32 v31, v46, v31
	v_dual_sub_f32 v29, v43, v29 :: v_dual_sub_f32 v36, v30, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v14, v31
	v_add_f32_e32 v16, v16, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v20, v20, v36
	v_add_f32_e32 v16, v16, v20
	v_sub_f32_e32 v20, v25, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v20, v26, v20
	v_add_f32_e32 v28, v49, v48
	v_add_f32_e32 v32, v37, v27
	v_sub_f32_e32 v34, v28, v49
	v_add_f32_e32 v35, v24, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v37, v32, v37
	v_sub_f32_e32 v34, v48, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v24, v35, v24
	v_sub_f32_e32 v27, v27, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v17, v17, v34 :: v_dual_sub_f32 v24, v28, v24
	v_dual_add_f32 v14, v14, v27 :: v_dual_add_f32 v17, v17, v24
	v_add_f32_e32 v24, v30, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v26, v35, v17 :: v_dual_sub_f32 v27, v24, v30
	v_dual_add_f32 v28, v19, v24 :: v_dual_sub_f32 v31, v26, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v16, v27
	v_sub_f32_e32 v27, v28, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v17, v31
	v_sub_f32_e32 v33, v28, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v24, v24, v27 :: v_dual_add_f32 v27, v13, v16
	v_sub_f32_e32 v19, v19, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v33, v27, v13
	v_dual_add_f32 v19, v24, v19 :: v_dual_sub_f32 v24, v27, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v16, v33 :: v_dual_add_f32 v19, v27, v19
	v_sub_f32_e32 v13, v13, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v16, v13
	v_add_f32_e32 v18, v32, v14
	v_dual_sub_f32 v29, v18, v32 :: v_dual_add_f32 v32, v25, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v31, v32, v25
	v_sub_f32_e32 v35, v32, v31
	v_dual_sub_f32 v26, v26, v31 :: v_dual_add_f32 v31, v20, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v25, v35
	v_sub_f32_e32 v35, v31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v25, v26, v25 :: v_dual_sub_f32 v26, v31, v35
	v_dual_sub_f32 v17, v17, v35 :: v_dual_add_f32 v24, v31, v25
	v_add_f32_e32 v25, v28, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v20, v20, v26
	v_sub_f32_e32 v26, v25, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v17, v17, v20 :: v_dual_sub_f32 v16, v19, v26
	v_cndmask_b32_e64 v19, v21, |v5|, s8
	v_cmp_eq_f32_e64 s8, |v6|, 1.0
	v_dual_add_f32 v13, v13, v16 :: v_dual_add_f32 v30, v22, v18
	v_sub_f32_e32 v14, v14, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, v23, |v6|, s8
	v_cmp_eq_f32_e64 s8, |v7|, 1.0
	v_cndmask_b32_e64 v16, 1.0, v6, s7
	v_sub_f32_e32 v29, v30, v22
	v_cndmask_b32_e64 v12, v12, |v7|, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v34, v30, v29
	v_dual_sub_f32 v18, v18, v29 :: v_dual_add_f32 v29, v15, v14
	v_sub_f32_e32 v22, v22, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v34, v29, v15
	v_add_f32_e32 v18, v18, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v22, v29, v34
	v_sub_f32_e32 v14, v14, v34
	v_add_f32_e32 v18, v29, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v15, v15, v22 :: v_dual_add_f32 v22, v32, v24
	v_add_f32_e32 v27, v30, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v14, v15
	v_dual_sub_f32 v15, v22, v32 :: v_dual_sub_f32 v28, v27, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v24, v15 :: v_dual_sub_f32 v18, v18, v28
	v_add_f32_e32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v17, v25, v13 :: v_dual_add_f32 v14, v14, v18
	v_add_f32_e32 v21, v22, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v23, v17, v25 :: v_dual_add_f32 v18, v27, v14
	v_mul_f32_e32 v24, v2, v17
	v_sub_f32_e32 v22, v21, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v13, v13, v23
	v_dual_sub_f32 v25, v18, v27 :: v_dual_mul_f32 v26, v3, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v17, v2, v17, -v24
	v_mul_f32_e32 v27, v4, v21
	v_dual_sub_f32 v15, v15, v22 :: v_dual_sub_f32 v14, v14, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v18, v3, v18, -v26
	v_fmac_f32_e32 v17, v2, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v21, v4, v21, -v27
	v_cmp_class_f32_e64 s8, v24, 0x204
	v_cndmask_b32_e64 v13, 1.0, v7, s6
	v_fmac_f32_e32 v18, v3, v14
	v_add_f32_e32 v14, v24, v17
	v_fmac_f32_e32 v21, v4, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, v26, v18
	v_sub_f32_e32 v23, v14, v24
	v_cndmask_b32_e64 v14, v14, v24, s8
	v_cmp_class_f32_e64 s8, v26, 0x204
	v_add_f32_e32 v22, v27, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v24, v15, v26 :: v_dual_sub_f32 v17, v17, v23
	v_cndmask_b32_e64 v15, v15, v26, s8
	v_cmp_class_f32_e64 s8, v27, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v18, v24
	v_cndmask_b32_e64 v25, v22, v27, s8
	v_cmp_eq_f32_e64 s8, 0x42b17218, v14
	v_sub_f32_e32 v22, v22, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v26, 0, 0x37000000, s8
	v_cmp_eq_f32_e64 s8, 0x42b17218, v15
	v_sub_f32_e32 v21, v21, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v30, v14, v26
	v_cndmask_b32_e64 v28, 0, 0x37000000, s8
	v_cmp_eq_f32_e64 s8, 0x42b17218, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v31, 0x3fb8aa3b, v30
	v_sub_f32_e32 v27, v15, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v29, 0, 0x37000000, s8
	v_cmp_neq_f32_e64 s8, 0x7f800000, |v14|
	v_fma_f32 v32, 0x3fb8aa3b, v30, -v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v24, 0x3fb8aa3b, v27 :: v_dual_sub_f32 v23, v25, v29
	v_rndne_f32_e32 v33, v31
	v_cndmask_b32_e64 v14, 0, v17, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v32, 0x32a5705f, v30
	v_fma_f32 v34, 0x3fb8aa3b, v27, -v24
	v_mul_f32_e32 v22, 0x3fb8aa3b, v23
	v_rndne_f32_e32 v35, v24
	v_sub_f32_e32 v31, v31, v33
	v_cmp_neq_f32_e64 s8, 0x7f800000, |v15|
	v_fmac_f32_e32 v34, 0x32a5705f, v27
	v_fma_f32 v36, 0x3fb8aa3b, v23, -v22
	v_rndne_f32_e32 v37, v22
	v_dual_sub_f32 v24, v24, v35 :: v_dual_add_f32 v17, v31, v32
	v_cndmask_b32_e64 v15, 0, v18, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v36, 0x32a5705f, v23
	v_sub_f32_e32 v22, v22, v37
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v24, v24, v34
	v_exp_f32_e32 v17, v17
	v_cmp_neq_f32_e64 s8, 0x7f800000, |v25|
	v_cvt_i32_f32_e32 v25, v35
	v_add_f32_e32 v22, v22, v36
	v_exp_f32_e32 v18, v24
	v_cvt_i32_f32_e32 v24, v33
	v_cndmask_b32_e64 v21, 0, v21, s8
	v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v30
	v_exp_f32_e32 v22, v22
	v_add_f32_e32 v14, v26, v14
	v_ldexp_f32 v17, v17, v24
	v_cvt_i32_f32_e32 v26, v37
	v_add_f32_e32 v15, v28, v15
	v_add_f32_e32 v21, v29, v21
	v_ldexp_f32 v18, v18, v25
	v_cndmask_b32_e64 v17, 0, v17, s8
	v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v27
	v_cndmask_b32_e64 v24, 0, v6, s7
	v_ldexp_f32 v22, v22, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, 0, v18, s8
	v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v23
	v_bfi_b32 v9, 0x7fffffff, v9, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v22, 0, v22, s8
	v_cmp_nlt_f32_e64 s8, 0x42b17218, v30
	v_cndmask_b32_e64 v17, 0x7f800000, v17, s8
	v_cmp_nlt_f32_e64 s8, 0x42b17218, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, v17, v14, v17
	v_cndmask_b32_e64 v18, 0x7f800000, v18, s8
	v_cmp_nlt_f32_e64 s8, 0x42b17218, v23
	v_cndmask_b32_e64 v23, 0, v5, s5
	v_cmp_eq_f32_e64 s5, 0x7f800000, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v15, v18, v15, v18
	v_cndmask_b32_e64 v22, 0x7f800000, v22, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v8, 0x7fffffff, v8, v23
	v_cndmask_b32_e64 v14, v14, v17, s5
	v_cmp_eq_f32_e64 s5, 0x7f800000, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v21, v22, v21, v22
	v_bfi_b32 v11, 0x7fffffff, v14, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v18, s5
	v_cmp_eq_f32_e64 s5, 0x7f800000, v22
	v_cndmask_b32_e64 v18, 0, v7, s6
	v_bfi_b32 v14, 0x7fffffff, v15, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v21, v22, s5
	v_cndmask_b32_e64 v15, 0x7fc00000, v11, s2
	v_cmp_gt_f32_e64 s2, 0, v5
	v_bfi_b32 v10, 0x7fffffff, v10, v18
	v_cndmask_b32_e64 v16, 0x7fc00000, v14, s3
	v_bfi_b32 v13, 0x7fffffff, v17, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v11, v15, s2
	v_cmp_gt_f32_e64 s2, 0, v6
	v_cndmask_b32_e64 v17, 0x7fc00000, v13, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v14, v16, s2
	v_cmp_gt_f32_e64 s2, 0, v7
	v_cndmask_b32_e64 v13, v13, v17, s2
	v_cmp_class_f32_e64 s2, v2, 0x204
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v11, v19, s2
	v_cmp_class_f32_e64 s2, v3, 0x204
	v_cndmask_b32_e32 v8, v11, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v20, s2
	v_cmp_class_f32_e64 s2, v4, 0x204
	s_or_b32 vcc_lo, s0, s15
	v_cndmask_b32_e32 v9, v14, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v13, v12, s2
	s_or_b32 vcc_lo, s1, s16
	v_cndmask_b32_e32 v10, v12, v10, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v5, v2
	v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v6, v3
	v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v7, v4
	v_cndmask_b32_e32 v4, 0x7fc00000, v10, vcc_lo
	global_store_b96 v[0:1], v[2:4], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel gamma_transform_2
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 51
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	gamma_transform_2, .Lfunc_end0-gamma_transform_2
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3500
; NumSgprs: 22
; NumVgprs: 51
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 51
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           gamma_transform_2
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         gamma_transform_2.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     51
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
