#include <stdio.h>
#include <stdlib.h>

__global__ void update_h(int nx, int ny, int nz, int nyz, int idx0, float *hx, float *hy, float *hz, float *ex, float *ey, float *ez) {
	int tx = threadIdx.x;
	int idx = blockDim.x*blockIdx.x + tx + idx0;
	int i = idx/(nyz);
	int j = (idx - i*nyz)/nz;
	int k = idx%nz;

	if( j>0 && k>0 ) hx[idx] -= 0.5*( ez[idx] - ez[idx-nz] - ey[idx] + ey[idx-1] );
	if( i>0 && k>0 ) hy[idx] -= 0.5*( ex[idx] - ex[idx-1] - ez[idx] + ez[idx-nyz] );
	if( i>0 && j>0 ) hz[idx] -= 0.5*( ey[idx] - ey[idx-nyz] - ex[idx] + ex[idx-nz] );
}

__global__ void update_e(int nx, int ny, int nz, int nyz, int idx0, float *hx, float *hy, float *hz, float *ex, float *ey, float *ez, float *cex, float *cey, float *cez) {
	int tx = threadIdx.x;
	int idx = blockDim.x*blockIdx.x + tx + idx0;
	int i = idx/(nyz);
	int j = (idx - i*nyz)/nz;
	int k = idx%nz;

	if( j<ny-1 && k<nz-1 ) ex[idx] += cex[idx]*( hz[idx+nz] - hz[idx] - hy[idx+1] + hy[idx] );
	if( i<nx-1 && k<nz-1 ) ey[idx] += cey[idx]*( hx[idx+1] - hx[idx] - hz[idx+nyz] + hz[idx] );
	if( i<nx-1 && j<ny-1 ) ez[idx] += cez[idx]*( hy[idx+nyz] - hy[idx] - hx[idx+nz] + hx[idx] );
}

__global__ void update_src(int nx, int ny, int nz, int nyz, float tn, float *f) {
	int idx = threadIdx.x;
	int ijk = (nx/2)*nyz + (ny/2)*nz + idx;

	if( idx < nz ) f[ijk] += sin(0.1*tn);
}
  
__global__ void init_zero(int n, int idx0, float *f) {
	int tx = threadIdx.x;
	int idx = blockDim.x*blockIdx.x + tx + idx0;
	if( idx < n ) f[idx] = 0;
}


int main() {
	int i, n, nx, ny, nz, tn, tmax;
	nx = 320;
	ny = 480;
	nz = 480;
	n = nx*ny*nz;
	tmax = 100000;

	printf("Simple FDTD simulation\n", nx, ny, nz);
	printf("Array size : %dx%dx%d\n", nx, ny, nz);
	printf("Total used memory : %1.2f GB\n", n*4*9./(1024*1024*1024));
	printf("Iteration : %d step\n", tmax);

	// memory allocate
	float *f, *cf;
	f = (float *) calloc (n, sizeof(float));
	cf = (float *) calloc (n, sizeof(float));
	for( i=0; i<n; i++ ) cf[i] = 0.5;

	float *hx_gpu, *hy_gpu, *hz_gpu;
	float *ex_gpu, *ey_gpu, *ez_gpu;
	float *cex_gpu, *cey_gpu, *cez_gpu;
	cudaMalloc ( (void**) &hx_gpu, n*sizeof(float) );
	cudaMalloc ( (void**) &hy_gpu, n*sizeof(float) );
	cudaMalloc ( (void**) &hz_gpu, n*sizeof(float) );
	cudaMalloc ( (void**) &ex_gpu, n*sizeof(float) );
	cudaMalloc ( (void**) &ey_gpu, n*sizeof(float) );
	cudaMalloc ( (void**) &ez_gpu, n*sizeof(float) );
	cudaMalloc ( (void**) &cex_gpu, n*sizeof(float) );
	cudaMalloc ( (void**) &cey_gpu, n*sizeof(float) );
	cudaMalloc ( (void**) &cez_gpu, n*sizeof(float) );

	cudaMemcpy ( cex_gpu, cf, n*sizeof(float), cudaMemcpyHostToDevice );
	cudaMemcpy ( cey_gpu, cf, n*sizeof(float), cudaMemcpyHostToDevice );
	cudaMemcpy ( cez_gpu, cf, n*sizeof(float), cudaMemcpyHostToDevice );

	int ng = 6;			// number of grid
	int tpb = 256;		// threads per block
	int bpg = n/tpb/ng;	// blocks per grid
	for( i=0; i<ng; i++) {
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, hx_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, hy_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, hz_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, ex_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, ey_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, ez_gpu);
	}

	// main loop
	for( tn=0; tn<tmax; tn++ ) {
		for( i=0; i<ng; i++) update_h <<<dim3(bpg),dim3(tpb)>>> (nx, ny, nz, ny*nz, i*bpg*tpb, hx_gpu, hy_gpu, hz_gpu, ex_gpu, ey_gpu, ez_gpu); 

		for( i=0; i<ng; i++) update_e <<<dim3(bpg),dim3(tpb)>>> (nx, ny, nz, ny*nz, i*bpg*tpb, hx_gpu, hy_gpu, hz_gpu, ex_gpu, ey_gpu, ez_gpu, cex_gpu, cey_gpu, cez_gpu); 

		update_src <<<dim3(1),dim3(512)>>> (nx, ny, nz, ny*nz, tn, ez_gpu);
	}
	cudaMemcpy( f, ez_gpu, n*sizeof(float), cudaMemcpyDeviceToHost );
	printf("Complete.\n");

	return 0;
}

	.file	"tmpxft_0039dfa1_00000000-6_012-row_major.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z8update_hiiiiiPfS_S_S_S_S_iiiiiPfS_S_S_S_S_
	.type	_Z42__device_stub__Z8update_hiiiiiPfS_S_S_S_S_iiiiiPfS_S_S_S_S_, @function
_Z42__device_stub__Z8update_hiiiiiPfS_S_S_S_S_iiiiiPfS_S_S_S_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 40(%rsp)
	movq	264(%rsp), %rax
	movl	%edx, 68(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 32(%rsp)
	movq	272(%rsp), %rax
	movl	%ecx, 64(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 24(%rsp)
	movq	280(%rsp), %rax
	movl	%r8d, 60(%rsp)
	movq	%rax, 16(%rsp)
	movq	288(%rsp), %rax
	movq	%r9, 48(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movl	$1, 104(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z8update_hiiiiiPfS_S_S_S_S_(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z42__device_stub__Z8update_hiiiiiPfS_S_S_S_S_iiiiiPfS_S_S_S_S_, .-_Z42__device_stub__Z8update_hiiiiiPfS_S_S_S_S_iiiiiPfS_S_S_S_S_
	.globl	_Z8update_hiiiiiPfS_S_S_S_S_
	.type	_Z8update_hiiiiiPfS_S_S_S_S_, @function
_Z8update_hiiiiiPfS_S_S_S_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z8update_hiiiiiPfS_S_S_S_S_iiiiiPfS_S_S_S_S_
	.cfi_endproc
.LFE2053:
	.size	_Z8update_hiiiiiPfS_S_S_S_S_, .-_Z8update_hiiiiiPfS_S_S_S_S_
	.globl	_Z48__device_stub__Z8update_eiiiiiPfS_S_S_S_S_S_S_S_iiiiiPfS_S_S_S_S_S_S_S_
	.type	_Z48__device_stub__Z8update_eiiiiiPfS_S_S_S_S_S_S_S_iiiiiPfS_S_S_S_S_S_S_S_, @function
_Z48__device_stub__Z8update_eiiiiiPfS_S_S_S_S_S_S_S_iiiiiPfS_S_S_S_S_S_S_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	304(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	120(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	312(%rsp), %rax
	movl	%edx, 84(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	320(%rsp), %rax
	movl	%ecx, 80(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	328(%rsp), %rax
	movl	%r8d, 76(%rsp)
	movq	%rax, 32(%rsp)
	movq	336(%rsp), %rax
	movq	%r9, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	344(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	352(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	360(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	76(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 264(%rsp)
	movq	%rsp, %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	112(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 320
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L8:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z48__device_stub__Z8update_eiiiiiPfS_S_S_S_S_S_S_S_iiiiiPfS_S_S_S_S_S_S_S_, .-_Z48__device_stub__Z8update_eiiiiiPfS_S_S_S_S_S_S_S_iiiiiPfS_S_S_S_S_S_S_S_
	.globl	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
	.type	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_, @function
_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z8update_eiiiiiPfS_S_S_S_S_S_S_S_iiiiiPfS_S_S_S_S_S_S_S_
	.cfi_endproc
.LFE2055:
	.size	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_, .-_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
	.globl	_Z35__device_stub__Z10update_srciiiifPfiiiifPf
	.type	_Z35__device_stub__Z10update_srciiiifPfiiiifPf, @function
_Z35__device_stub__Z10update_srciiiifPfiiiifPf:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z10update_srciiiifPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L13:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z35__device_stub__Z10update_srciiiifPfiiiifPf, .-_Z35__device_stub__Z10update_srciiiifPfiiiifPf
	.globl	_Z10update_srciiiifPf
	.type	_Z10update_srciiiifPf, @function
_Z10update_srciiiifPf:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z10update_srciiiifPfiiiifPf
	.cfi_endproc
.LFE2057:
	.size	_Z10update_srciiiifPf, .-_Z10update_srciiiifPf
	.globl	_Z30__device_stub__Z9init_zeroiiPfiiPf
	.type	_Z30__device_stub__Z9init_zeroiiPfiiPf, @function
_Z30__device_stub__Z9init_zeroiiPfiiPf:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 8(%rsp)
	leaq	44(%rsp), %rsi
	movq	%rdx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z9init_zeroiiPf(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L18:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z30__device_stub__Z9init_zeroiiPfiiPf, .-_Z30__device_stub__Z9init_zeroiiPfiiPf
	.globl	_Z9init_zeroiiPf
	.type	_Z9init_zeroiiPf, @function
_Z9init_zeroiiPf:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z9init_zeroiiPfiiPf
	.cfi_endproc
.LFE2059:
	.size	_Z9init_zeroiiPf, .-_Z9init_zeroiiPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Simple FDTD simulation\n"
.LC1:
	.string	"Array size : %dx%dx%d\n"
.LC3:
	.string	"Total used memory : %1.2f GB\n"
.LC4:
	.string	"Iteration : %d step\n"
.LC6:
	.string	"Complete.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$480, %r8d
	movl	$480, %ecx
	movl	$320, %edx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$480, %r8d
	xorl	%eax, %eax
	movl	$480, %ecx
	movl	$320, %edx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	.LC2(%rip), %xmm0
	leaq	.LC3(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$100000, %edx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$4, %esi
	movl	$73728000, %edi
	call	calloc@PLT
	movl	$4, %esi
	movl	$73728000, %edi
	movq	%rax, 8(%rsp)
	call	calloc@PLT
	movss	.LC5(%rip), %xmm0
	movq	%rax, %rbx
	xorl	%eax, %eax
.L24:
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$73728000, %rax
	jne	.L24
	leaq	24(%rsp), %rdi
	movl	$294912000, %esi
	movl	$33554807, %ebp
	xorl	%r12d, %r12d
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$294912000, %esi
	salq	$7, %rbp
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$294912000, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$294912000, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$294912000, %esi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$294912000, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$294912000, %esi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movl	$294912000, %esi
	call	cudaMalloc@PLT
	leaq	88(%rsp), %rdi
	movl	$294912000, %esi
	call	cudaMalloc@PLT
	movq	72(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$294912000, %edx
	call	cudaMemcpy@PLT
	movq	80(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$294912000, %edx
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$294912000, %edx
	movl	$16777217, %ebx
	call	cudaMemcpy@PLT
	salq	$8, %rbx
.L31:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%rbp, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	24(%rsp), %rdx
	movl	%r12d, %esi
	movl	$73728000, %edi
	call	_Z30__device_stub__Z9init_zeroiiPfiiPf
.L25:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%rbp, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	32(%rsp), %rdx
	movl	%r12d, %esi
	movl	$73728000, %edi
	call	_Z30__device_stub__Z9init_zeroiiPfiiPf
.L26:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%rbp, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	40(%rsp), %rdx
	movl	%r12d, %esi
	movl	$73728000, %edi
	call	_Z30__device_stub__Z9init_zeroiiPfiiPf
.L27:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%rbp, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	48(%rsp), %rdx
	movl	%r12d, %esi
	movl	$73728000, %edi
	call	_Z30__device_stub__Z9init_zeroiiPfiiPf
.L28:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%rbp, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	56(%rsp), %rdx
	movl	%r12d, %esi
	movl	$73728000, %edi
	call	_Z30__device_stub__Z9init_zeroiiPfiiPf
.L29:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%rbp, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	64(%rsp), %rdx
	movl	%r12d, %esi
	movl	$73728000, %edi
	call	_Z30__device_stub__Z9init_zeroiiPfiiPf
.L30:
	addl	$12288000, %r12d
	cmpl	$73728000, %r12d
	jne	.L31
	movabsq	$4294967552, %r12
	xorl	%ebp, %ebp
	movabsq	$4295015296, %r13
	movabsq	$4294967808, %r14
	movabsq	$4294967297, %r15
.L32:
	xorl	%ebx, %ebx
.L34:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%r13, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	%rax
	.cfi_def_cfa_offset 200
	movl	%ebx, %r8d
	movl	$230400, %ecx
	movl	$480, %edx
	pushq	72(%rsp)
	.cfi_def_cfa_offset 208
	movl	$480, %esi
	movl	$320, %edi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	72(%rsp), %r9
	call	_Z42__device_stub__Z8update_hiiiiiPfS_S_S_S_S_iiiiiPfS_S_S_S_S_
	addq	$48, %rsp
	.cfi_def_cfa_offset 192
.L33:
	addl	$12288000, %ebx
	cmpl	$73728000, %ebx
	jne	.L34
	xorl	%ebx, %ebx
.L36:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%r13, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	88(%rsp)
	.cfi_def_cfa_offset 200
	movl	%ebx, %r8d
	movl	$230400, %ecx
	movl	$480, %edx
	pushq	88(%rsp)
	.cfi_def_cfa_offset 208
	movl	$480, %esi
	movl	$320, %edi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 216
	pushq	88(%rsp)
	.cfi_def_cfa_offset 224
	pushq	88(%rsp)
	.cfi_def_cfa_offset 232
	pushq	88(%rsp)
	.cfi_def_cfa_offset 240
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	88(%rsp), %r9
	call	_Z48__device_stub__Z8update_eiiiiiPfS_S_S_S_S_S_S_S_iiiiiPfS_S_S_S_S_S_S_S_
	addq	$64, %rsp
	.cfi_def_cfa_offset 192
.L35:
	addl	$12288000, %ebx
	cmpl	$73728000, %ebx
	jne	.L36
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r14, %rdx
	movl	$1, %ecx
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, 108(%rsp)
	movl	$1, 116(%rsp)
	movq	%r15, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	cvtsi2ssl	%ebp, %xmm0
	movq	64(%rsp), %r8
	movl	$230400, %ecx
	movl	$480, %edx
	movl	$480, %esi
	movl	$320, %edi
	call	_Z35__device_stub__Z10update_srciiiifPfiiiifPf
.L37:
	incl	%ebp
	cmpl	$100000, %ebp
	jne	.L32
	movq	64(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$294912000, %edx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC6(%rip), %rsi
	call	__printf_chk@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L39
	call	__stack_chk_fail@PLT
.L39:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z9init_zeroiiPf"
.LC8:
	.string	"_Z10update_srciiiifPf"
.LC9:
	.string	"_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_"
.LC10:
	.string	"_Z8update_hiiiiiPfS_S_S_S_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9init_zeroiiPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10update_srciiiifPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8update_hiiiiiPfS_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1073989248
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC5:
	.long	1056964608
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

__global__ void update_h(int nx, int ny, int nz, int nyz, int idx0, float *hx, float *hy, float *hz, float *ex, float *ey, float *ez) {
	int tx = threadIdx.x;
	int idx = blockDim.x*blockIdx.x + tx + idx0;
	int i = idx/(nyz);
	int j = (idx - i*nyz)/nz;
	int k = idx%nz;

	if( j>0 && k>0 ) hx[idx] -= 0.5*( ez[idx] - ez[idx-nz] - ey[idx] + ey[idx-1] );
	if( i>0 && k>0 ) hy[idx] -= 0.5*( ex[idx] - ex[idx-1] - ez[idx] + ez[idx-nyz] );
	if( i>0 && j>0 ) hz[idx] -= 0.5*( ey[idx] - ey[idx-nyz] - ex[idx] + ex[idx-nz] );
}

__global__ void update_e(int nx, int ny, int nz, int nyz, int idx0, float *hx, float *hy, float *hz, float *ex, float *ey, float *ez, float *cex, float *cey, float *cez) {
	int tx = threadIdx.x;
	int idx = blockDim.x*blockIdx.x + tx + idx0;
	int i = idx/(nyz);
	int j = (idx - i*nyz)/nz;
	int k = idx%nz;

	if( j<ny-1 && k<nz-1 ) ex[idx] += cex[idx]*( hz[idx+nz] - hz[idx] - hy[idx+1] + hy[idx] );
	if( i<nx-1 && k<nz-1 ) ey[idx] += cey[idx]*( hx[idx+1] - hx[idx] - hz[idx+nyz] + hz[idx] );
	if( i<nx-1 && j<ny-1 ) ez[idx] += cez[idx]*( hy[idx+nyz] - hy[idx] - hx[idx+nz] + hx[idx] );
}

__global__ void update_src(int nx, int ny, int nz, int nyz, float tn, float *f) {
	int idx = threadIdx.x;
	int ijk = (nx/2)*nyz + (ny/2)*nz + idx;

	if( idx < nz ) f[ijk] += sin(0.1*tn);
}
  
__global__ void init_zero(int n, int idx0, float *f) {
	int tx = threadIdx.x;
	int idx = blockDim.x*blockIdx.x + tx + idx0;
	if( idx < n ) f[idx] = 0;
}


int main() {
	int i, n, nx, ny, nz, tn, tmax;
	nx = 320;
	ny = 480;
	nz = 480;
	n = nx*ny*nz;
	tmax = 100000;

	printf("Simple FDTD simulation\n", nx, ny, nz);
	printf("Array size : %dx%dx%d\n", nx, ny, nz);
	printf("Total used memory : %1.2f GB\n", n*4*9./(1024*1024*1024));
	printf("Iteration : %d step\n", tmax);

	// memory allocate
	float *f, *cf;
	f = (float *) calloc (n, sizeof(float));
	cf = (float *) calloc (n, sizeof(float));
	for( i=0; i<n; i++ ) cf[i] = 0.5;

	float *hx_gpu, *hy_gpu, *hz_gpu;
	float *ex_gpu, *ey_gpu, *ez_gpu;
	float *cex_gpu, *cey_gpu, *cez_gpu;
	hipMalloc ( (void**) &hx_gpu, n*sizeof(float) );
	hipMalloc ( (void**) &hy_gpu, n*sizeof(float) );
	hipMalloc ( (void**) &hz_gpu, n*sizeof(float) );
	hipMalloc ( (void**) &ex_gpu, n*sizeof(float) );
	hipMalloc ( (void**) &ey_gpu, n*sizeof(float) );
	hipMalloc ( (void**) &ez_gpu, n*sizeof(float) );
	hipMalloc ( (void**) &cex_gpu, n*sizeof(float) );
	hipMalloc ( (void**) &cey_gpu, n*sizeof(float) );
	hipMalloc ( (void**) &cez_gpu, n*sizeof(float) );

	hipMemcpy ( cex_gpu, cf, n*sizeof(float), hipMemcpyHostToDevice );
	hipMemcpy ( cey_gpu, cf, n*sizeof(float), hipMemcpyHostToDevice );
	hipMemcpy ( cez_gpu, cf, n*sizeof(float), hipMemcpyHostToDevice );

	int ng = 6;			// number of grid
	int tpb = 256;		// threads per block
	int bpg = n/tpb/ng;	// blocks per grid
	for( i=0; i<ng; i++) {
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, hx_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, hy_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, hz_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, ex_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, ey_gpu);
		init_zero <<<dim3(bpg),dim3(tpb)>>> (n, i*bpg*tpb, ez_gpu);
	}

	// main loop
	for( tn=0; tn<tmax; tn++ ) {
		for( i=0; i<ng; i++) update_h <<<dim3(bpg),dim3(tpb)>>> (nx, ny, nz, ny*nz, i*bpg*tpb, hx_gpu, hy_gpu, hz_gpu, ex_gpu, ey_gpu, ez_gpu); 

		for( i=0; i<ng; i++) update_e <<<dim3(bpg),dim3(tpb)>>> (nx, ny, nz, ny*nz, i*bpg*tpb, hx_gpu, hy_gpu, hz_gpu, ex_gpu, ey_gpu, ez_gpu, cex_gpu, cey_gpu, cez_gpu); 

		update_src <<<dim3(1),dim3(512)>>> (nx, ny, nz, ny*nz, tn, ez_gpu);
	}
	hipMemcpy( f, ez_gpu, n*sizeof(float), hipMemcpyDeviceToHost );
	printf("Complete.\n");

	return 0;
}

	.text
	.file	"012-row_major.hip"
	.globl	_Z23__device_stub__update_hiiiiiPfS_S_S_S_S_ # -- Begin function _Z23__device_stub__update_hiiiiiPfS_S_S_S_S_
	.type	_Z23__device_stub__update_hiiiiiPfS_S_S_S_S_,@function
_Z23__device_stub__update_hiiiiiPfS_S_S_S_S_: # @_Z23__device_stub__update_hiiiiiPfS_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8update_hiiiiiPfS_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__update_hiiiiiPfS_S_S_S_S_, .Lfunc_end0-_Z23__device_stub__update_hiiiiiPfS_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_ # -- Begin function _Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_
	.type	_Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_,@function
_Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_: # @_Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_, .Lfunc_end1-_Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__update_srciiiifPf # -- Begin function _Z25__device_stub__update_srciiiifPf
	.type	_Z25__device_stub__update_srciiiifPf,@function
_Z25__device_stub__update_srciiiifPf:   # @_Z25__device_stub__update_srciiiifPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	40(%rsp), %r9
	movq	%r8, (%r9)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r9, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10update_srciiiifPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__update_srciiiifPf, .Lfunc_end2-_Z25__device_stub__update_srciiiifPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__init_zeroiiPf # -- Begin function _Z24__device_stub__init_zeroiiPf
	.type	_Z24__device_stub__init_zeroiiPf,@function
_Z24__device_stub__init_zeroiiPf:       # @_Z24__device_stub__init_zeroiiPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	movq	%rsp, %rcx
	movl	%esi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9init_zeroiiPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z24__device_stub__init_zeroiiPf, .Lfunc_end3-_Z24__device_stub__init_zeroiiPf
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI4_0:
	.quad	0x4003c68000000000              # double 2.471923828125
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
	movl	$.L.str.1, %edi
	movl	$320, %esi                      # imm = 0x140
	movl	$480, %edx                      # imm = 0x1E0
	movl	$480, %ecx                      # imm = 0x1E0
	xorl	%eax, %eax
	callq	printf
	movsd	.LCPI4_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.3, %edi
	movl	$100000, %esi                   # imm = 0x186A0
	xorl	%eax, %eax
	callq	printf
	movl	$73728000, %edi                 # imm = 0x4650000
	movl	$4, %esi
	callq	calloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movl	$73728000, %edi                 # imm = 0x4650000
	movl	$4, %esi
	callq	calloc
	movq	%rax, %r15
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	movl	$1056964608, (%r15,%rbx,4)      # imm = 0x3F000000
	incq	%rbx
	cmpq	$73728000, %rbx                 # imm = 0x4650000
	jne	.LBB4_1
# %bb.2:
	movabsq	$4294967552, %r14               # imm = 0x100000100
	leaq	48(%rsp), %rdi
	movl	$294912000, %esi                # imm = 0x11940000
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$294912000, %esi                # imm = 0x11940000
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$294912000, %esi                # imm = 0x11940000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$294912000, %esi                # imm = 0x11940000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$294912000, %esi                # imm = 0x11940000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$294912000, %esi                # imm = 0x11940000
	callq	hipMalloc
	leaq	80(%rsp), %r12
	movl	$294912000, %esi                # imm = 0x11940000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	72(%rsp), %r13
	movl	$294912000, %esi                # imm = 0x11940000
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	64(%rsp), %rbp
	movl	$294912000, %esi                # imm = 0x11940000
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$294912000, %edx                # imm = 0x11940000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$294912000, %edx                # imm = 0x11940000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$294912000, %edx                # imm = 0x11940000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
	leaq	47744(%r14), %r15
.LBB4_3:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_5
# %bb.4:                                #   in Loop: Header=BB4_3 Depth=1
	movq	48(%rsp), %rdx
	movl	$73728000, %edi                 # imm = 0x4650000
	movl	%r12d, %esi
	callq	_Z24__device_stub__init_zeroiiPf
.LBB4_5:                                #   in Loop: Header=BB4_3 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_7
# %bb.6:                                #   in Loop: Header=BB4_3 Depth=1
	movq	40(%rsp), %rdx
	movl	$73728000, %edi                 # imm = 0x4650000
	movl	%r12d, %esi
	callq	_Z24__device_stub__init_zeroiiPf
.LBB4_7:                                #   in Loop: Header=BB4_3 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_9
# %bb.8:                                #   in Loop: Header=BB4_3 Depth=1
	movq	32(%rsp), %rdx
	movl	$73728000, %edi                 # imm = 0x4650000
	movl	%r12d, %esi
	callq	_Z24__device_stub__init_zeroiiPf
.LBB4_9:                                #   in Loop: Header=BB4_3 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_11
# %bb.10:                               #   in Loop: Header=BB4_3 Depth=1
	movq	24(%rsp), %rdx
	movl	$73728000, %edi                 # imm = 0x4650000
	movl	%r12d, %esi
	callq	_Z24__device_stub__init_zeroiiPf
.LBB4_11:                               #   in Loop: Header=BB4_3 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_13
# %bb.12:                               #   in Loop: Header=BB4_3 Depth=1
	movq	16(%rsp), %rdx
	movl	$73728000, %edi                 # imm = 0x4650000
	movl	%r12d, %esi
	callq	_Z24__device_stub__init_zeroiiPf
.LBB4_13:                               #   in Loop: Header=BB4_3 Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_15
# %bb.14:                               #   in Loop: Header=BB4_3 Depth=1
	movq	8(%rsp), %rdx
	movl	$73728000, %edi                 # imm = 0x4650000
	movl	%r12d, %esi
	callq	_Z24__device_stub__init_zeroiiPf
.LBB4_15:                               #   in Loop: Header=BB4_3 Depth=1
	addl	$12288000, %r12d                # imm = 0xBB8000
	cmpl	$73728000, %r12d                # imm = 0x4650000
	jne	.LBB4_3
# %bb.16:                               # %.preheader206.preheader
	xorl	%ebx, %ebx
	leaq	-255(%r14), %r12
	leaq	256(%r14), %r13
.LBB4_17:                               # %.preheader206
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_18 Depth 2
                                        #     Child Loop BB4_22 Depth 2
	xorl	%ebp, %ebp
.LBB4_18:                               #   Parent Loop BB4_17 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_20
# %bb.19:                               #   in Loop: Header=BB4_18 Depth=2
	movq	48(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$320, %edi                      # imm = 0x140
	movl	$480, %esi                      # imm = 0x1E0
	movl	$480, %edx                      # imm = 0x1E0
	movl	$230400, %ecx                   # imm = 0x38400
	movl	%ebp, %r8d
	pushq	16(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z23__device_stub__update_hiiiiiPfS_S_S_S_S_
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB4_20:                               #   in Loop: Header=BB4_18 Depth=2
	addl	$12288000, %ebp                 # imm = 0xBB8000
	cmpl	$73728000, %ebp                 # imm = 0x4650000
	jne	.LBB4_18
# %bb.21:                               # %.preheader.preheader
                                        #   in Loop: Header=BB4_17 Depth=1
	xorl	%ebp, %ebp
.LBB4_22:                               # %.preheader
                                        #   Parent Loop BB4_17 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_24
# %bb.23:                               #   in Loop: Header=BB4_22 Depth=2
	movq	48(%rsp), %r9
	movl	$320, %edi                      # imm = 0x140
	movl	$480, %esi                      # imm = 0x1E0
	movl	$480, %edx                      # imm = 0x1E0
	movl	$230400, %ecx                   # imm = 0x38400
	movl	%ebp, %r8d
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB4_24:                               #   in Loop: Header=BB4_22 Depth=2
	addl	$12288000, %ebp                 # imm = 0xBB8000
	cmpl	$73728000, %ebp                 # imm = 0x4650000
	jne	.LBB4_22
# %bb.25:                               #   in Loop: Header=BB4_17 Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_27
# %bb.26:                               #   in Loop: Header=BB4_17 Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebx, %xmm0
	movq	8(%rsp), %r8
	movl	$320, %edi                      # imm = 0x140
	movl	$480, %esi                      # imm = 0x1E0
	movl	$480, %edx                      # imm = 0x1E0
	movl	$230400, %ecx                   # imm = 0x38400
	callq	_Z25__device_stub__update_srciiiifPf
.LBB4_27:                               #   in Loop: Header=BB4_17 Depth=1
	incl	%ebx
	cmpl	$100000, %ebx                   # imm = 0x186A0
	jne	.LBB4_17
# %bb.28:
	movq	8(%rsp), %rsi
	movl	$294912000, %edx                # imm = 0x11940000
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8update_hiiiiiPfS_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10update_srciiiifPf, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9init_zeroiiPf, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8update_hiiiiiPfS_S_S_S_S_,@object # @_Z8update_hiiiiiPfS_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z8update_hiiiiiPfS_S_S_S_S_
	.p2align	3, 0x0
_Z8update_hiiiiiPfS_S_S_S_S_:
	.quad	_Z23__device_stub__update_hiiiiiPfS_S_S_S_S_
	.size	_Z8update_hiiiiiPfS_S_S_S_S_, 8

	.type	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_,@object # @_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
	.globl	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
	.p2align	3, 0x0
_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_:
	.quad	_Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_
	.size	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_, 8

	.type	_Z10update_srciiiifPf,@object   # @_Z10update_srciiiifPf
	.globl	_Z10update_srciiiifPf
	.p2align	3, 0x0
_Z10update_srciiiifPf:
	.quad	_Z25__device_stub__update_srciiiifPf
	.size	_Z10update_srciiiifPf, 8

	.type	_Z9init_zeroiiPf,@object        # @_Z9init_zeroiiPf
	.globl	_Z9init_zeroiiPf
	.p2align	3, 0x0
_Z9init_zeroiiPf:
	.quad	_Z24__device_stub__init_zeroiiPf
	.size	_Z9init_zeroiiPf, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Array size : %dx%dx%d\n"
	.size	.L.str.1, 23

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Total used memory : %1.2f GB\n"
	.size	.L.str.2, 30

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Iteration : %d step\n"
	.size	.L.str.3, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8update_hiiiiiPfS_S_S_S_S_"
	.size	.L__unnamed_1, 29

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_"
	.size	.L__unnamed_2, 35

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10update_srciiiifPf"
	.size	.L__unnamed_3, 22

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z9init_zeroiiPf"
	.size	.L__unnamed_4, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Simple FDTD simulation"
	.size	.Lstr, 23

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Complete."
	.size	.Lstr.1, 10

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__update_hiiiiiPfS_S_S_S_S_
	.addrsig_sym _Z23__device_stub__update_eiiiiiPfS_S_S_S_S_S_S_S_
	.addrsig_sym _Z25__device_stub__update_srciiiifPf
	.addrsig_sym _Z24__device_stub__init_zeroiiPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8update_hiiiiiPfS_S_S_S_S_
	.addrsig_sym _Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
	.addrsig_sym _Z10update_srciiiifPf
	.addrsig_sym _Z9init_zeroiiPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8update_hiiiiiPfS_S_S_S_S_ ; -- Begin function _Z8update_hiiiiiPfS_S_S_S_S_
	.globl	_Z8update_hiiiiiPfS_S_S_S_S_
	.p2align	8
	.type	_Z8update_hiiiiiPfS_S_S_S_S_,@function
_Z8update_hiiiiiPfS_S_S_S_S_:           ; @_Z8update_hiiiiiPfS_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x8
	s_load_b32 s4, s[0:1], 0x54
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s17, 31
	s_and_b32 s4, s4, 0xffff
	s_add_i32 s3, s17, s2
	s_mul_i32 s15, s15, s4
	s_xor_b32 s3, s3, s2
	v_add3_u32 v0, s15, s18, v0
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v2, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, s4, v2
	v_add_nc_u32_e32 v4, v0, v1
	s_ashr_i32 s4, s16, 31
	v_xor_b32_e32 v7, s2, v1
	s_add_i32 s5, s16, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v4, v4, v1
	s_xor_b32 s5, s5, s4
	v_mul_hi_u32 v3, v2, v3
	s_sub_i32 s2, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_hi_u32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v2, s3
	v_add_nc_u32_e32 v5, 1, v2
	v_sub_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v3, v3, v6
	v_cvt_f32_u32_e32 v6, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, 1, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v3, v6
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v7
	v_sub_nc_u32_e32 v5, v2, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v3
	v_mul_lo_u32 v3, v5, s17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v6, s2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v0, v3
	v_ashrrev_i32_e32 v7, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v2, v6
	v_add_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v6
	v_xor_b32_e32 v3, v3, v7
	v_xor_b32_e32 v7, s4, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v6, v4, v2
	v_mul_hi_u32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, s5
	v_mul_lo_u32 v8, v2, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v6
	v_sub_nc_u32_e32 v3, v3, v8
	v_add_nc_u32_e32 v6, 1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v8, s5, v4
	v_subrev_nc_u32_e32 v9, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_cmp_le_u32_e64 s2, s5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v9 :: v_dual_cndmask_b32 v2, v2, v6
	v_cndmask_b32_e64 v4, v4, v8, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_add_nc_u32_e32 v6, 1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s5, v4
	v_cndmask_b32_e32 v2, v2, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v4
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x38
	s_load_b256 s[4:11], s[0:1], 0x18
	v_xor_b32_e32 v2, v2, v7
	v_cndmask_b32_e32 v3, v4, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v2, v7
	v_xor_b32_e32 v3, v3, v1
	v_subrev_nc_u32_e32 v2, s16, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e32 vcc_lo, 0, v4
	v_sub_nc_u32_e32 v3, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_i32_e64 s0, 0, v3
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s14, v6
	v_add_co_ci_u32_e64 v11, s1, s15, v7, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, s14, v8
	v_add_co_ci_u32_e64 v9, s1, s15, v9, s1
	v_add_co_u32 v12, s1, s12, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s1, s13, v7, s1
	s_clause 0x1
	global_load_b32 v4, v[10:11], off
	global_load_b32 v10, v[8:9], off
	global_load_b64 v[8:9], v[12:13], off offset:-4
	v_add_co_u32 v6, s1, s4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s1, s5, v7, s1
	global_load_b32 v11, v[6:7], off
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v4, v4, v10
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v4, v4, v9
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[10:11], v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v8
	v_cvt_f64_f32_e32 v[8:9], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], -0.5, v[10:11]
	v_cvt_f32_f64_e32 v4, v[8:9]
	global_store_b32 v[6:7], v4, off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s2
	v_subrev_nc_u32_e32 v4, s17, v0
	v_cmp_lt_i32_e64 s1, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	s_and_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, s10, v6
	v_add_co_ci_u32_e64 v11, s0, s11, v7, s0
	v_add_co_u32 v12, s0, s14, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s0, s15, v7, s0
	global_load_b64 v[10:11], v[10:11], off offset:-4
	v_add_co_u32 v8, s0, s14, v8
	v_add_co_ci_u32_e64 v9, s0, s15, v9, s0
	s_clause 0x1
	global_load_b32 v12, v[12:13], off
	global_load_b32 v8, v[8:9], off
	v_add_co_u32 v6, s0, s6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
	global_load_b32 v13, v[6:7], off
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v9, v11, v10
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v9, v9, v12
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v9, v8
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[10:11], v13
	v_cvt_f64_f32_e32 v[8:9], v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], -0.5, v[10:11]
	v_cvt_f32_f64_e32 v8, v[8:9]
	global_store_b32 v[6:7], v8, off
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_b32 s0, s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	s_clause 0x1
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v3, v6, v7
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v4
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[4:5], v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[2:3], v2
	v_fma_f64 v[2:3], v[2:3], -0.5, v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v2, v[2:3]
	global_store_b32 v[0:1], v2, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8update_hiiiiiPfS_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8update_hiiiiiPfS_S_S_S_S_, .Lfunc_end0-_Z8update_hiiiiiPfS_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1212
; NumSgprs: 22
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_ ; -- Begin function _Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
	.globl	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
	.p2align	8
	.type	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_,@function
_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_:     ; @_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
; %bb.0:
	s_clause 0x2
	s_load_b128 s[20:23], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x10
	s_load_b32 s5, s[0:1], 0x6c
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s23, 31
	s_and_b32 s5, s5, 0xffff
	s_add_i32 s4, s23, s3
	s_mul_i32 s15, s15, s5
	s_xor_b32 s4, s4, s3
	v_add3_u32 v0, s15, s2, v0
	v_cvt_f32_u32_e32 v1, s4
	s_sub_i32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v2, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, s5, v2
	v_add_nc_u32_e32 v4, v0, v1
	s_ashr_i32 s5, s22, 31
	v_xor_b32_e32 v7, s3, v1
	s_add_i32 s2, s22, s5
	s_add_i32 s3, s22, -1
	v_xor_b32_e32 v4, v4, v1
	s_xor_b32 s6, s2, s5
	v_mul_hi_u32 v3, v2, v3
	s_sub_i32 s2, 0, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_hi_u32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v2, s4
	v_add_nc_u32_e32 v5, 1, v2
	v_sub_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s4, v3
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v3, v3, v6
	v_cvt_f32_u32_e32 v6, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, 1, v2
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v3, v6
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v7
	v_sub_nc_u32_e32 v5, v2, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v3
	v_mul_lo_u32 v3, v5, s23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v6, s2, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v0, v3
	v_ashrrev_i32_e32 v7, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v2, v6
	v_add_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v6
	v_xor_b32_e32 v3, v3, v7
	v_xor_b32_e32 v7, s5, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v6, v4, v2
	v_mul_hi_u32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, s6
	v_mul_lo_u32 v8, v2, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v6
	v_sub_nc_u32_e32 v3, v3, v8
	v_add_nc_u32_e32 v6, 1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v8, s6, v4
	v_subrev_nc_u32_e32 v9, s6, v3
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	v_cmp_le_u32_e64 s2, s6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v9 :: v_dual_cndmask_b32 v2, v2, v6
	v_cndmask_b32_e64 v4, v4, v8, s2
	s_add_i32 s2, s21, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s6, v3
	v_add_nc_u32_e32 v6, 1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s6, v4
	v_cndmask_b32_e32 v2, v2, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s6, v4
	s_load_b512 s[4:19], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v2, v7
	v_cndmask_b32_e32 v3, v4, v8, vcc_lo
	v_sub_nc_u32_e32 v4, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v3, v1
	v_add_nc_u32_e32 v2, s22, v0
	v_cmp_gt_i32_e32 vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v1
	v_cmp_gt_i32_e64 s2, s3, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	s_and_b32 s3, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s21, s3
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_lshlrev_b64 v[8:9], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s3, s8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s3, s9, v7, s3
	v_add_co_u32 v10, s3, s8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s9, v9, s3
	v_add_co_u32 v12, s3, s6, v8
	v_add_co_ci_u32_e64 v13, s3, s7, v9, s3
	s_clause 0x1
	global_load_b32 v4, v[6:7], off
	global_load_b32 v14, v[10:11], off
	global_load_b64 v[6:7], v[12:13], off
	v_add_co_u32 v10, s3, s16, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s17, v9, s3
	v_add_co_u32 v8, s3, s10, v8
	v_add_co_ci_u32_e64 v9, s3, s11, v9, s3
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v[8:9], off
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v4, v4, v14
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v7
	v_add_f32_e32 v4, v4, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v11, v10, v4
	global_store_b32 v[8:9], v11, off
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s21
	v_add_nc_u32_e32 v4, s23, v0
	s_add_i32 s3, s20, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s3, v5
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, s3, s2
	s_waitcnt lgkmcnt(0)
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s2, s4, v6
	v_add_co_ci_u32_e64 v11, s2, s5, v7, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s2, s8, v8
	v_add_co_ci_u32_e64 v9, s2, s9, v9, s2
	global_load_b64 v[10:11], v[10:11], off
	v_add_co_u32 v12, s2, s8, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s2, s9, v7, s2
	v_add_co_u32 v14, s2, s18, v6
	s_clause 0x1
	global_load_b32 v8, v[8:9], off
	global_load_b32 v9, v[12:13], off
	v_add_co_ci_u32_e64 v15, s2, s19, v7, s2
	v_add_co_u32 v6, s2, s12, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s2, s13, v7, s2
	global_load_b32 v12, v[14:15], off
	global_load_b32 v13, v[6:7], off
	s_waitcnt vmcnt(4)
	v_sub_f32_e32 v10, v11, v10
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v10, v8
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v8, v8, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v13, v12, v8
	global_store_b32 v[6:7], v13, off
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s10
	s_and_b32 s2, s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_6
; %bb.5:
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_load_b64 s[0:1], s[0:1], 0x58
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v8, v[4:5], off
	global_load_b32 v9, v[6:7], off
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s0, v0
	s_clause 0x1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	global_load_b32 v4, v[6:7], off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(4)
	v_sub_f32_e32 v6, v8, v9
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v6, v2
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v2, v2, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v5, v4, v2
	global_store_b32 v[0:1], v5, off
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_, .Lfunc_end1-_Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1248
; NumSgprs: 26
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10update_srciiiifPf   ; -- Begin function _Z10update_srciiiifPf
	.globl	_Z10update_srciiiifPf
	.p2align	8
	.type	_Z10update_srciiiifPf,@function
_Z10update_srciiiifPf:                  ; @_Z10update_srciiiifPf
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s6, v0
	s_cbranch_execz .LBB2_7
; %bb.1:
	s_load_b32 s2, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[1:2], s2
	s_mov_b32 s2, 0x9999999a
	s_mov_b32 s3, 0x3fb99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[1:2], v[1:2], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s2, 0x41d00000, |v[1:2]|
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB2_3
; %bb.2:
	v_ldexp_f64 v[3:4], |v[1:2]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[1:2]|
	v_trig_preop_f64 v[5:6], |v[1:2]|, 0
	v_and_b32_e32 v7, 0x7fffffff, v2
	v_trig_preop_f64 v[17:18], |v[1:2]|, 2
	s_mov_b32 s8, 0
	s_mov_b32 s10, 0x33145c07
	s_mov_b32 s11, 0x3c91a626
	v_dual_cndmask_b32 v4, v7, v4 :: v_dual_cndmask_b32 v3, v1, v3
	v_trig_preop_f64 v[7:8], |v[1:2]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[9:10], v[5:6], v[3:4]
	v_mul_f64 v[23:24], v[17:18], v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[11:12], v[7:8], v[3:4]
	v_fma_f64 v[5:6], v[5:6], v[3:4], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[7:8], v[7:8], v[3:4], -v[11:12]
	v_fma_f64 v[3:4], v[17:18], v[3:4], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[11:12], v[5:6]
	v_add_f64 v[15:16], v[13:14], -v[11:12]
	v_add_f64 v[21:22], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[13:14], -v[15:16]
	v_add_f64 v[5:6], v[5:6], -v[15:16]
	v_ldexp_f64 v[15:16], v[21:22], -2
	v_add_f64 v[9:10], v[21:22], -v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[11:12], -v[19:20]
	v_add_f64 v[19:20], v[23:24], v[7:8]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[15:16]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[9:10], v[13:14], -v[9:10]
	v_add_f64 v[5:6], v[5:6], v[11:12]
	v_fract_f64_e32 v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[19:20], v[5:6]
	v_dual_cndmask_b32 v12, 0, v12 :: v_dual_cndmask_b32 v11, 0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[11:12], v[11:12], 2
	v_add_f64 v[15:16], v[9:10], v[13:14]
	v_add_f64 v[25:26], v[13:14], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[15:16], v[11:12]
	v_add_f64 v[31:32], v[13:14], -v[25:26]
	v_add_f64 v[5:6], v[5:6], -v[25:26]
	v_add_f64 v[9:10], v[15:16], -v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[21:22]
	v_add_f64 v[21:22], v[19:20], -v[23:24]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s9, 0x40100000, 0
	v_add_f64 v[29:30], v[19:20], -v[21:22]
	v_add_f64 v[11:12], v[11:12], s[8:9]
	v_add_f64 v[7:8], v[7:8], -v[21:22]
	v_add_f64 v[19:20], v[19:20], -v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[23:24], -v[29:30]
	v_add_f64 v[27:28], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], v[19:20]
	v_add_f64 v[7:8], v[7:8], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v27, v[27:28]
	v_add_f64 v[5:6], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[25:26], v27
	v_add_f64 v[7:8], v[13:14], -v[9:10]
	v_add_f64 v[3:4], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[25:26]
	v_add_f64 v[3:4], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[15:16], v[11:12]
	v_add_f64 v[5:6], v[17:18], -v[11:12]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[17:18]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[5:6], v[15:16], -v[5:6]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s9, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v7, s2, 0, v27, vcc_lo
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x3ff921fb
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_add_f64 v[5:6], v[17:18], -s[8:9]
	v_add_f64 v[8:9], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[10:11], v[8:9], s[2:3]
	v_add_f64 v[5:6], v[8:9], -v[5:6]
	v_fma_f64 v[12:13], v[8:9], s[2:3], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], -v[5:6]
	v_fma_f64 v[5:6], v[8:9], s[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[3:4], s[2:3], v[5:6]
	v_add_f64 v[3:4], v[10:11], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[3:4], -v[10:11]
	v_add_f64 v[5:6], v[5:6], -v[8:9]
	s_branch .LBB2_4
.LBB2_3:
	s_mov_b32 s8, -1
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr5_vgpr6
.LBB2_4:                                ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB2_6
; %bb.5:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s9, 0xbc91a626
	v_mul_f64 v[3:4], |v[1:2]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s8, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[7:8], v[3:4]
	v_fma_f64 v[3:4], v[7:8], s[2:3], |v[1:2]|
	v_mul_f64 v[5:6], v[7:8], s[8:9]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[7:8], s[8:9], v[3:4]
	v_add_f64 v[9:10], v[3:4], v[5:6]
	s_mov_b32 s9, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[3:4], v[3:4], -v[9:10]
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_fma_f64 v[5:6], v[7:8], s[8:9], v[5:6]
	v_add_f64 v[3:4], v[9:10], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], -v[5:6]
	v_fma_f64 v[5:6], v[7:8], s[2:3], v[3:4]
	v_cvt_i32_f64_e32 v7, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[11:12], v[5:6]
	v_add_f64 v[9:10], v[3:4], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[9:10]
.LBB2_6:                                ; %_ZL3sind.exit
	s_lshr_b32 s2, s4, 31
	s_lshr_b32 s3, s5, 31
	s_add_i32 s2, s4, s2
	s_add_i32 s3, s5, s3
	s_ashr_i32 s2, s2, 1
	s_ashr_i32 s3, s3, 1
	s_load_b64 s[0:1], s[0:1], 0x18
	s_mul_i32 s2, s2, s7
	s_mul_i32 s3, s3, s6
	v_mul_f64 v[8:9], v[3:4], v[3:4]
	v_add3_u32 v10, s2, s3, v0
	s_mov_b32 s2, 0xf9a43bb8
	s_mov_b32 s3, 0x3de5e0b2
	s_mov_b32 s4, 0x796cde01
	s_mov_b32 s5, 0x3ec71de3
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[5:6], 0.5
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s1, 0xbe5ae600
	global_load_b32 v0, v[10:11], off
	v_fma_f64 v[12:13], v[8:9], s[2:3], s[0:1]
	s_mov_b32 s0, 0x9037ab78
	s_mov_b32 s2, 0x46cc5e42
	s_mov_b32 s1, 0x3e21eeb6
	s_mov_b32 s3, 0xbda907db
	v_mul_f64 v[14:15], v[8:9], 0.5
	v_fma_f64 v[16:17], v[8:9], s[2:3], s[0:1]
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s2, 0x19e83e5c
	s_mov_b32 s1, 0xbe927e4f
	s_mov_b32 s3, 0xbf2a01a0
	v_mul_f64 v[22:23], v[3:4], -v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
	v_add_f64 v[18:19], -v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[8:9], v[16:17], s[0:1]
	s_mov_b32 s0, 0x19f4ec90
	s_mov_b32 s1, 0x3efa01a0
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[2:3]
	s_mov_b32 s2, 0x11110bb3
	s_mov_b32 s3, 0x3f811111
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], -v[18:19], 1.0
	v_fma_f64 v[16:17], v[8:9], v[16:17], s[0:1]
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[2:3]
	v_add_f64 v[14:15], v[20:21], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[16:17], v[8:9], v[16:17], s[0:1]
	s_mov_b32 s1, 0x3fa55555
	s_mov_b32 s0, 0x55555555
	v_mul_f64 v[20:21], v[8:9], v[8:9]
	v_fma_f64 v[12:13], v[22:23], v[12:13], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[3:4], -v[5:6], v[14:15]
	v_fma_f64 v[16:17], v[8:9], v[16:17], s[0:1]
	s_mov_b32 s1, 0xbfc55555
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[8:9], v[12:13], -v[5:6]
	v_fma_f64 v[8:9], v[20:21], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[5:6], v[22:23], s[0:1], v[5:6]
	v_cmp_class_f64_e64 s0, v[1:2], 0x1f8
	v_add_f64 v[8:9], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], -v[5:6]
	v_and_b32_e32 v5, 1, v7
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	v_lshlrev_b32_e32 v5, 30, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v5, v2
	v_and_b32_e32 v2, 0x80000000, v2
	v_dual_cndmask_b32 v4, v9, v4 :: v_dual_cndmask_b32 v3, v8, v3
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[0:1], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v2
	v_cndmask_b32_e64 v2, 0, v3, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, 0x7ff80000, v4, s0
	v_add_f64 v[0:1], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_store_b32 v[10:11], v0, off
.LBB2_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10update_srciiiifPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 12
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10update_srciiiifPf, .Lfunc_end2-_Z10update_srciiiifPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1668
; NumSgprs: 14
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 14
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9init_zeroiiPf        ; -- Begin function _Z9init_zeroiiPf
	.globl	_Z9init_zeroiiPf
	.p2align	8
	.type	_Z9init_zeroiiPf,@function
_Z9init_zeroiiPf:                       ; @_Z9init_zeroiiPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s4
	v_add3_u32 v0, s15, s3, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x8
	v_ashrrev_i32_e32 v1, 31, v0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9init_zeroiiPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z9init_zeroiiPf, .Lfunc_end3-_Z9init_zeroiiPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 132
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8update_hiiiiiPfS_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z8update_hiiiiiPfS_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8update_eiiiiiPfS_S_S_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z8update_eiiiiiPfS_S_S_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10update_srciiiifPf
    .private_segment_fixed_size: 0
    .sgpr_count:     14
    .sgpr_spill_count: 0
    .symbol:         _Z10update_srciiiifPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9init_zeroiiPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9init_zeroiiPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
