/*
* This code is courtesy of, and copyright 2015,
* Tomas Oppelstrup, Livermore National Lab. Please
* do not redistribute without his approval.
*/
#define NTHREADS_RADIX 128
#define NBLOCKS_RADIX   56

__global__ static void
boxsum_stage1(int nc,int count[]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = gridDim.x;
  const int pid = bid*nt + tid, np = nb*nt;
  int i;
  for(i = pid; i<nc; i+=np)
    count[i] = 0;
}

__global__ static void
boxsum_stage2(int n,int v[],int listid[],int count[]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = gridDim.x;
  const int pid = bid*nt + tid, np = nb*nt;
  int i,vi,x;
  volatile __shared__ struct { int vi[NTHREADS_RADIX],x[NTHREADS_RADIX]; } shm;

  if(0) {
    for(i = pid; i<n; i+=np) {
      // Compute index within box.
      vi = v[i];
      x = atomicAdd(&count[vi],1);
      listid[i] = x;
    }
  } else {
    for(i = pid; i<n+tid; i+=np) {
      // Compute index within box.
      if(n-(i-tid) < nt) {
	if(i < n) {
	  vi = v[i];
	  x = atomicAdd(&count[vi],1);
	  listid[i] = x;
	}
      } else {
	shm.vi[tid] = v[i];
	__syncthreads();
	// Requirement is that gcd(11,nt) = 1
	shm.x[(19*tid)%nt] = atomicAdd(&count[shm.vi[(19*tid)%nt]],1);
	__syncthreads();
	listid[i] = shm.x[tid];
      }
    }

    /*
    int i0,i1;
    {
      int q = n/np;
      int r = n%np;
      if(pid >= r) { i0 = q*pid + r; i1 = i0 + q; }
      else { i0 = q*pid + pid; i1 = i0 + q + 1; }
    }
    for(i = i0; i<i1; i++) {
      vi = v[i];
      x = atomicAdd(&count[vi],1);
      listid[i] = x;
    }
    */
  }
}

__global__ static void
boxsum_stage3(int nboxes,int count[],int psum[]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = gridDim.x;
  const int pid = bid*nt + tid, np = nb*nt;
  int i,x;
  volatile __shared__ struct { int x[NTHREADS_RADIX]; } shm;
  for(i = pid; i<nboxes+tid; i+=np) {
    __syncthreads();
    x = 0;
    if(i < nboxes) x = count[i];
    shm.x[tid] = x;
    __syncthreads();
    if(tid < 64) shm.x[tid] += shm.x[tid+64];
    __syncthreads();
    if(tid < 32) {
      shm.x[tid] += shm.x[tid+32];
      shm.x[tid] += shm.x[tid+16];
      shm.x[tid] += shm.x[tid+ 8];
      shm.x[tid] += shm.x[tid+ 4];
      shm.x[tid] += shm.x[tid+ 2];
      shm.x[tid] += shm.x[tid+ 1];
    }
    if(tid == 0) psum[i/nt] = shm.x[0];
  }
}

__global__ static void
boxsum_stage4(int n,int psum[]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x;
  int i,j,x,s;
  volatile __shared__ int xshare[NTHREADS_RADIX];

  s = 0;
  if(bid == 0)
    for(i = tid; i<n+tid; i+=nt) {
      __syncthreads();
      x = 0;
      if(i < n) x = psum[i];
      xshare[tid] = x;
      __syncthreads();
      // Make cumulative summation of columns in type!
      j = 1;
      while(j < nt) {
	if(tid >= j) x += xshare[tid-j];
	__syncthreads();
	xshare[tid] = x;
	j = j*2;
	__syncthreads();
      }
      if(i < n) psum[i] = xshare[tid] + s;
      s = s + xshare[nt-1];
    }
}

__global__ static void
boxsum_stage5(int nboxes,int count[],int psum[])  {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = NBLOCKS_RADIX;
  const int pid = bid*nt + tid, np = nb*nt;

  int i,x,x1;
  volatile __shared__ struct {
    int psum,x[2][NTHREADS_RADIX],y[2][NTHREADS_RADIX];
  } shm;

  shm.x[0][tid] = 0;
  shm.y[0][tid] = 0;
  for(i = pid; i<nboxes+tid; i+=np) {
    __syncthreads();
    if(tid == 0) shm.psum = psum[i/nt];
    x = 0;
    if(i < nboxes) x = count[i];
    x1 = x;
    shm.x[1][tid] = x; __syncthreads();
    x += shm.x[1][tid- 1]; shm.y[1][tid] = x; __syncthreads();
    x += shm.y[1][tid- 2]; shm.x[1][tid] = x; __syncthreads();
    x += shm.x[1][tid- 4]; shm.y[1][tid] = x; __syncthreads();
    x += shm.y[1][tid- 8]; shm.x[1][tid] = x; __syncthreads();
    x += shm.x[1][tid-16]; shm.y[1][tid] = x; __syncthreads();
    x += shm.y[1][tid-32]; shm.x[1][tid] = x; __syncthreads();
    x += shm.x[1][tid-64]; shm.y[1][tid] = x; __syncthreads();
    x += shm.psum - shm.y[1][nt-1];
    //if(i == nboxes-1) { x=0; x1=0; }
    if(i < nboxes) count[i] = x-x1;
  }
}

__global__ static void
boxsum_stage6(int n,int v[],int listid[],int count[])  {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = NBLOCKS_RADIX;
  const int pid = bid*nt + tid, np = nb*nt;
  int i,lid,bno,idx;
  for(i = pid; i<n; i+=np) {
    lid = listid[i];
    bno = v[i];
    idx = 0;
    if(bno > 0) idx = count[bno];
    listid[i] = lid + idx;
  }
}

__global__ static void
boxsum_stage7(int n,int listid[],int bin[],float xx[][4], float vv[][4],
	      int bout[],float xxout[][4], float vvout[][4]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = NBLOCKS_RADIX;
  const int pid = bid*nt + tid, np = nb*nt;
  int i,j,xend;
  float x,v;
  volatile __shared__ struct { int idx[NTHREADS_RADIX]; } shm;
  for(i = pid; i<n+tid; i+=np) {
    j = 0;
    if(i < n) j = listid[i];
    xend = min(nt,n-(i-tid));
    __syncthreads();
    shm.idx[tid] = j;
    __syncthreads();

    if(i < n) bout[j] = bin[i];
    for(j = tid; j<4*xend; j+=nt) {
      x = xx[i-tid][j];
      v = vv[i-tid][j];
      xxout[shm.idx[j/4]][j%4] = x;
      vvout[shm.idx[j/4]][j%4] = v;
    }
  }
}

void rsort_card(int n,int nc,
		int *xin_g,float (*data1in_g)[4],float (*data2in_g)[4],
		int *xout_g,float (*data1out_g)[4],float (*data2out_g)[4],
		int *count_g) {
  static int n_init = 0, nc_init = 0;
  static int *psum_g,*listid_g;
  int ns = (nc+NTHREADS_RADIX-1)/NTHREADS_RADIX;

  if(n <= 0 || nc <= 0) {
    if(n_init > 0) {
      cudaFree(listid_g);
      cudaFree(psum_g);
    }
    n_init = 0;
    nc_init = 0;
  } else if(n > n_init || nc > nc_init) {
    if(n_init > 0) {
      cudaFree(listid_g);
      cudaFree(psum_g);
    }
    cudaMalloc((void **) &psum_g,sizeof(int) * ns);
    cudaMalloc((void **) &listid_g,sizeof(int) * n);
    n_init = n;
    nc_init = nc;
  }

  if(n > 0 && nc > 0) {
    /*
    int *listid = (int *) malloc(sizeof(int) * n);
    int *count = (int *) malloc(sizeof(int) * nc);
    int *count2 = (int *) malloc(sizeof(int) * nc);
    int *psum = (int *) malloc(sizeof(int) * ns);
    int *psum2 = (int *) malloc(sizeof(int) * ns);
    int i,s;
    */
    boxsum_stage1<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g);
    /*
    cudaThreadSynchronize();
    s = 0;
    for(i = 0; i<nc; i++)
      s += abs(count[i]);
    if(s != 0)
      printf("count not zeroed, s=%d\n",s);
    */

    boxsum_stage2<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
    /*
    cudaThreadSynchronize();

    cudaMemcpy(listid,listid_g,sizeof(int) * n,cudaMemcpyDeviceToHost);
    cudaMemcpy(count,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
    s = 0;
    for(i = 0; i<nc; i++)
      s += count[i];
    if(s != n)
      printf("Error in count, s=%d, n=%d\n",s,n);
    */
    boxsum_stage3<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
    /*
    cudaThreadSynchronize();

    cudaMemcpy(psum,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);

    for(i = 0; i<ns; i++) {
      int j;
      s = 0;
      for(j = 0; j<NTHREADS_RADIX; j++)
	if(i*NTHREADS_RADIX+j < nc) s += count[i*NTHREADS_RADIX+j];
      if(s != psum[i])
	printf("psum error, i=%d ns=%d s=%d psum=%d\n",i,ns,s,psum[i]);
    }
    */
    boxsum_stage4<<<1,NTHREADS_RADIX>>>(ns,psum_g);
    /*
    cudaThreadSynchronize();

    cudaMemcpy(psum2,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);

    s = 0;
    for(i = 0; i<ns; i++) {
      s += psum[i];
      if(s != psum2[i])
	printf("cumsum error in psum: s=%d psum2=%d i=%d ns=%d\n",
	       s,psum2[i],i,ns);
    }
    */
    boxsum_stage5<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
    /*
    cudaThreadSynchronize();

    cudaMemcpy(count2,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);

    s = 0;
    for(i = 0; i<nc; i++) {
      s += count[i];
      if(s != count2[i])
	printf("cumsum error in count: s=%d count2=%d i=%d nc=%d\n",
	       s,count2[i],i,nc);
    }
    */
    boxsum_stage6<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
    boxsum_stage7<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,listid_g,xin_g,
						    data1in_g,data2in_g,xout_g,
						    data1out_g,data2out_g);
  }
}

	.file	"tmpxft_0031d186_00000000-6_boxsortinc.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_, @function
_ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_:
.LFB2045:
	.cfi_startproc
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2045:
	.size	_ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_, .-_ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_
	.type	_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, @function
_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_:
.LFB2046:
	.cfi_startproc
	endbr64
	jmp	_ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_
	.cfi_endproc
.LFE2046:
	.size	_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, .-_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
	.type	_ZL34__device_stub__Z13boxsum_stage1iPiiPi, @function
_ZL34__device_stub__Z13boxsum_stage1iPiiPi:
.LFB2033:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL13boxsum_stage1iPi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_ZL34__device_stub__Z13boxsum_stage1iPiiPi, .-_ZL34__device_stub__Z13boxsum_stage1iPiiPi
	.type	_ZL13boxsum_stage1iPi, @function
_ZL13boxsum_stage1iPi:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_ZL34__device_stub__Z13boxsum_stage1iPiiPi
	.cfi_endproc
.LFE2034:
	.size	_ZL13boxsum_stage1iPi, .-_ZL13boxsum_stage1iPi
	.type	_ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_, @function
_ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_:
.LFB2035:
	.cfi_startproc
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZL13boxsum_stage2iPiS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_, .-_ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_
	.type	_ZL13boxsum_stage2iPiS_S_, @function
_ZL13boxsum_stage2iPiS_S_:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_
	.cfi_endproc
.LFE2036:
	.size	_ZL13boxsum_stage2iPiS_S_, .-_ZL13boxsum_stage2iPiS_S_
	.type	_ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_, @function
_ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_:
.LFB2037:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL13boxsum_stage3iPiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L18:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_, .-_ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_
	.type	_ZL13boxsum_stage3iPiS_, @function
_ZL13boxsum_stage3iPiS_:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_
	.cfi_endproc
.LFE2038:
	.size	_ZL13boxsum_stage3iPiS_, .-_ZL13boxsum_stage3iPiS_
	.type	_ZL34__device_stub__Z13boxsum_stage4iPiiPi, @function
_ZL34__device_stub__Z13boxsum_stage4iPiiPi:
.LFB2039:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL13boxsum_stage4iPi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L23:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_ZL34__device_stub__Z13boxsum_stage4iPiiPi, .-_ZL34__device_stub__Z13boxsum_stage4iPiiPi
	.type	_ZL13boxsum_stage4iPi, @function
_ZL13boxsum_stage4iPi:
.LFB2040:
	.cfi_startproc
	endbr64
	jmp	_ZL34__device_stub__Z13boxsum_stage4iPiiPi
	.cfi_endproc
.LFE2040:
	.size	_ZL13boxsum_stage4iPi, .-_ZL13boxsum_stage4iPi
	.type	_ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_, @function
_ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_:
.LFB2041:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL13boxsum_stage5iPiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L28:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_, .-_ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_
	.type	_ZL13boxsum_stage5iPiS_, @function
_ZL13boxsum_stage5iPiS_:
.LFB2042:
	.cfi_startproc
	endbr64
	jmp	_ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_
	.cfi_endproc
.LFE2042:
	.size	_ZL13boxsum_stage5iPiS_, .-_ZL13boxsum_stage5iPiS_
	.type	_ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_, @function
_ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_:
.LFB2043:
	.cfi_startproc
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZL13boxsum_stage6iPiS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L33:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	_ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_, .-_ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_
	.type	_ZL13boxsum_stage6iPiS_S_, @function
_ZL13boxsum_stage6iPiS_S_:
.LFB2044:
	.cfi_startproc
	endbr64
	jmp	_ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_
	.cfi_endproc
.LFE2044:
	.size	_ZL13boxsum_stage6iPiS_S_, .-_ZL13boxsum_stage6iPiS_S_
	.globl	_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
	.type	_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_, @function
_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r8, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	144(%rsp), %rax
	movq	%rdx, 8(%rsp)
	movq	%rcx, 24(%rsp)
	movl	$128, %ecx
	movq	128(%rsp), %r14
	movq	%rax, (%rsp)
	leal	127(%rsi), %eax
	movq	136(%rsp), %r15
	cltd
	idivl	%ecx
	movl	%eax, 20(%rsp)
	movl	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip), %eax
	testl	%edi, %edi
	jle	.L56
	testl	%esi, %esi
	jg	.L39
.L56:
	testl	%eax, %eax
	jle	.L41
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
	call	cudaFree@PLT
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
	call	cudaFree@PLT
.L41:
	xorl	%eax, %eax
	movl	%eax, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip)
	movl	%eax, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
	testl	%ebx, %ebx
	jle	.L38
	testl	%ebp, %ebp
	jle	.L38
	jmp	.L42
.L39:
	cmpl	%eax, %edi
	jg	.L45
	cmpl	%esi, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
	jl	.L46
	jmp	.L42
.L45:
	testl	%eax, %eax
	jle	.L47
.L46:
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
	call	cudaFree@PLT
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
	call	cudaFree@PLT
.L47:
	movslq	20(%rsp), %rsi
	leaq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	%ebx, %rsi
	leaq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	%ebx, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip)
	movl	%ebp, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
.L42:
	movl	$33554433, %edx
	movl	$536870919, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	movq	(%rsp), %rsi
	movl	%ebp, %edi
	call	_ZL34__device_stub__Z13boxsum_stage1iPiiPi
.L54:
	movl	$33554433, %edx
	movl	$536870919, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	movq	(%rsp), %rcx
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdx
	movl	%ebx, %edi
	movq	8(%rsp), %rsi
	call	_ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_
.L48:
	movl	$33554433, %edx
	movl	$536870919, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdx
	movq	(%rsp), %rsi
	movl	%ebp, %edi
	call	_ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_
.L49:
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$7, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 60(%rsp)
	movq	%rdx, 52(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rsi
	movl	20(%rsp), %edi
	call	_ZL34__device_stub__Z13boxsum_stage4iPiiPi
.L50:
	movl	$33554433, %edx
	movl	$536870919, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdx
	movq	(%rsp), %rsi
	movl	%ebp, %edi
	call	_ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_
.L51:
	movl	$33554433, %edx
	movl	$536870919, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	movq	(%rsp), %rcx
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdx
	movl	%ebx, %edi
	movq	8(%rsp), %rsi
	call	_ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_
.L52:
	movl	$33554433, %edx
	movl	$536870919, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 52(%rsp)
	movl	$1, 60(%rsp)
	movq	%rdi, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	%r15, 136(%rsp)
	movq	%r13, %r9
	movq	%r12, %r8
	movl	%ebx, %edi
	movq	%r14, 128(%rsp)
	movq	24(%rsp), %rcx
	movq	8(%rsp), %rdx
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rsi
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_
.L38:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_, .-_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_"
.LC1:
	.string	"_Z13boxsum_stage6iPiS_S_"
.LC2:
	.string	"_Z13boxsum_stage5iPiS_"
.LC3:
	.string	"_Z13boxsum_stage4iPi"
.LC4:
	.string	"_Z13boxsum_stage3iPiS_"
.LC5:
	.string	"_Z13boxsum_stage2iPiS_S_"
.LC6:
	.string	"_Z13boxsum_stage1iPi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2048:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL13boxsum_stage6iPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL13boxsum_stage5iPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL13boxsum_stage4iPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL13boxsum_stage3iPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL13boxsum_stage2iPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL13boxsum_stage1iPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2048:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g
	.comm	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g,8,8
	.local	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g
	.comm	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g,8,8
	.local	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init
	.comm	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init,4,4
	.local	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init
	.comm	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init,4,4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*
* This code is courtesy of, and copyright 2015,
* Tomas Oppelstrup, Livermore National Lab. Please
* do not redistribute without his approval.
*/
#define NTHREADS_RADIX 128
#define NBLOCKS_RADIX   56

__global__ static void
boxsum_stage1(int nc,int count[]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = gridDim.x;
  const int pid = bid*nt + tid, np = nb*nt;
  int i;
  for(i = pid; i<nc; i+=np)
    count[i] = 0;
}

__global__ static void
boxsum_stage2(int n,int v[],int listid[],int count[]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = gridDim.x;
  const int pid = bid*nt + tid, np = nb*nt;
  int i,vi,x;
  volatile __shared__ struct { int vi[NTHREADS_RADIX],x[NTHREADS_RADIX]; } shm;

  if(0) {
    for(i = pid; i<n; i+=np) {
      // Compute index within box.
      vi = v[i];
      x = atomicAdd(&count[vi],1);
      listid[i] = x;
    }
  } else {
    for(i = pid; i<n+tid; i+=np) {
      // Compute index within box.
      if(n-(i-tid) < nt) {
	if(i < n) {
	  vi = v[i];
	  x = atomicAdd(&count[vi],1);
	  listid[i] = x;
	}
      } else {
	shm.vi[tid] = v[i];
	__syncthreads();
	// Requirement is that gcd(11,nt) = 1
	shm.x[(19*tid)%nt] = atomicAdd(&count[shm.vi[(19*tid)%nt]],1);
	__syncthreads();
	listid[i] = shm.x[tid];
      }
    }

    /*
    int i0,i1;
    {
      int q = n/np;
      int r = n%np;
      if(pid >= r) { i0 = q*pid + r; i1 = i0 + q; }
      else { i0 = q*pid + pid; i1 = i0 + q + 1; }
    }
    for(i = i0; i<i1; i++) {
      vi = v[i];
      x = atomicAdd(&count[vi],1);
      listid[i] = x;
    }
    */
  }
}

__global__ static void
boxsum_stage3(int nboxes,int count[],int psum[]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = gridDim.x;
  const int pid = bid*nt + tid, np = nb*nt;
  int i,x;
  volatile __shared__ struct { int x[NTHREADS_RADIX]; } shm;
  for(i = pid; i<nboxes+tid; i+=np) {
    __syncthreads();
    x = 0;
    if(i < nboxes) x = count[i];
    shm.x[tid] = x;
    __syncthreads();
    if(tid < 64) shm.x[tid] += shm.x[tid+64];
    __syncthreads();
    if(tid < 32) {
      shm.x[tid] += shm.x[tid+32];
      shm.x[tid] += shm.x[tid+16];
      shm.x[tid] += shm.x[tid+ 8];
      shm.x[tid] += shm.x[tid+ 4];
      shm.x[tid] += shm.x[tid+ 2];
      shm.x[tid] += shm.x[tid+ 1];
    }
    if(tid == 0) psum[i/nt] = shm.x[0];
  }
}

__global__ static void
boxsum_stage4(int n,int psum[]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x;
  int i,j,x,s;
  volatile __shared__ int xshare[NTHREADS_RADIX];

  s = 0;
  if(bid == 0)
    for(i = tid; i<n+tid; i+=nt) {
      __syncthreads();
      x = 0;
      if(i < n) x = psum[i];
      xshare[tid] = x;
      __syncthreads();
      // Make cumulative summation of columns in type!
      j = 1;
      while(j < nt) {
	if(tid >= j) x += xshare[tid-j];
	__syncthreads();
	xshare[tid] = x;
	j = j*2;
	__syncthreads();
      }
      if(i < n) psum[i] = xshare[tid] + s;
      s = s + xshare[nt-1];
    }
}

__global__ static void
boxsum_stage5(int nboxes,int count[],int psum[])  {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = NBLOCKS_RADIX;
  const int pid = bid*nt + tid, np = nb*nt;

  int i,x,x1;
  volatile __shared__ struct {
    int psum,x[2][NTHREADS_RADIX],y[2][NTHREADS_RADIX];
  } shm;

  shm.x[0][tid] = 0;
  shm.y[0][tid] = 0;
  for(i = pid; i<nboxes+tid; i+=np) {
    __syncthreads();
    if(tid == 0) shm.psum = psum[i/nt];
    x = 0;
    if(i < nboxes) x = count[i];
    x1 = x;
    shm.x[1][tid] = x; __syncthreads();
    x += shm.x[1][tid- 1]; shm.y[1][tid] = x; __syncthreads();
    x += shm.y[1][tid- 2]; shm.x[1][tid] = x; __syncthreads();
    x += shm.x[1][tid- 4]; shm.y[1][tid] = x; __syncthreads();
    x += shm.y[1][tid- 8]; shm.x[1][tid] = x; __syncthreads();
    x += shm.x[1][tid-16]; shm.y[1][tid] = x; __syncthreads();
    x += shm.y[1][tid-32]; shm.x[1][tid] = x; __syncthreads();
    x += shm.x[1][tid-64]; shm.y[1][tid] = x; __syncthreads();
    x += shm.psum - shm.y[1][nt-1];
    //if(i == nboxes-1) { x=0; x1=0; }
    if(i < nboxes) count[i] = x-x1;
  }
}

__global__ static void
boxsum_stage6(int n,int v[],int listid[],int count[])  {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = NBLOCKS_RADIX;
  const int pid = bid*nt + tid, np = nb*nt;
  int i,lid,bno,idx;
  for(i = pid; i<n; i+=np) {
    lid = listid[i];
    bno = v[i];
    idx = 0;
    if(bno > 0) idx = count[bno];
    listid[i] = lid + idx;
  }
}

__global__ static void
boxsum_stage7(int n,int listid[],int bin[],float xx[][4], float vv[][4],
	      int bout[],float xxout[][4], float vvout[][4]) {
  const int tid = threadIdx.x, nt = NTHREADS_RADIX;
  const int bid = blockIdx.x,  nb = NBLOCKS_RADIX;
  const int pid = bid*nt + tid, np = nb*nt;
  int i,j,xend;
  float x,v;
  volatile __shared__ struct { int idx[NTHREADS_RADIX]; } shm;
  for(i = pid; i<n+tid; i+=np) {
    j = 0;
    if(i < n) j = listid[i];
    xend = min(nt,n-(i-tid));
    __syncthreads();
    shm.idx[tid] = j;
    __syncthreads();

    if(i < n) bout[j] = bin[i];
    for(j = tid; j<4*xend; j+=nt) {
      x = xx[i-tid][j];
      v = vv[i-tid][j];
      xxout[shm.idx[j/4]][j%4] = x;
      vvout[shm.idx[j/4]][j%4] = v;
    }
  }
}

void rsort_card(int n,int nc,
		int *xin_g,float (*data1in_g)[4],float (*data2in_g)[4],
		int *xout_g,float (*data1out_g)[4],float (*data2out_g)[4],
		int *count_g) {
  static int n_init = 0, nc_init = 0;
  static int *psum_g,*listid_g;
  int ns = (nc+NTHREADS_RADIX-1)/NTHREADS_RADIX;

  if(n <= 0 || nc <= 0) {
    if(n_init > 0) {
      hipFree(listid_g);
      hipFree(psum_g);
    }
    n_init = 0;
    nc_init = 0;
  } else if(n > n_init || nc > nc_init) {
    if(n_init > 0) {
      hipFree(listid_g);
      hipFree(psum_g);
    }
    hipMalloc((void **) &psum_g,sizeof(int) * ns);
    hipMalloc((void **) &listid_g,sizeof(int) * n);
    n_init = n;
    nc_init = nc;
  }

  if(n > 0 && nc > 0) {
    /*
    int *listid = (int *) malloc(sizeof(int) * n);
    int *count = (int *) malloc(sizeof(int) * nc);
    int *count2 = (int *) malloc(sizeof(int) * nc);
    int *psum = (int *) malloc(sizeof(int) * ns);
    int *psum2 = (int *) malloc(sizeof(int) * ns);
    int i,s;
    */
    boxsum_stage1<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g);
    /*
    cudaThreadSynchronize();
    s = 0;
    for(i = 0; i<nc; i++)
      s += abs(count[i]);
    if(s != 0)
      printf("count not zeroed, s=%d\n",s);
    */

    boxsum_stage2<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
    /*
    cudaThreadSynchronize();

    cudaMemcpy(listid,listid_g,sizeof(int) * n,cudaMemcpyDeviceToHost);
    cudaMemcpy(count,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
    s = 0;
    for(i = 0; i<nc; i++)
      s += count[i];
    if(s != n)
      printf("Error in count, s=%d, n=%d\n",s,n);
    */
    boxsum_stage3<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
    /*
    cudaThreadSynchronize();

    cudaMemcpy(psum,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);

    for(i = 0; i<ns; i++) {
      int j;
      s = 0;
      for(j = 0; j<NTHREADS_RADIX; j++)
	if(i*NTHREADS_RADIX+j < nc) s += count[i*NTHREADS_RADIX+j];
      if(s != psum[i])
	printf("psum error, i=%d ns=%d s=%d psum=%d\n",i,ns,s,psum[i]);
    }
    */
    boxsum_stage4<<<1,NTHREADS_RADIX>>>(ns,psum_g);
    /*
    cudaThreadSynchronize();

    cudaMemcpy(psum2,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);

    s = 0;
    for(i = 0; i<ns; i++) {
      s += psum[i];
      if(s != psum2[i])
	printf("cumsum error in psum: s=%d psum2=%d i=%d ns=%d\n",
	       s,psum2[i],i,ns);
    }
    */
    boxsum_stage5<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
    /*
    cudaThreadSynchronize();

    cudaMemcpy(count2,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);

    s = 0;
    for(i = 0; i<nc; i++) {
      s += count[i];
      if(s != count2[i])
	printf("cumsum error in count: s=%d count2=%d i=%d nc=%d\n",
	       s,count2[i],i,nc);
    }
    */
    boxsum_stage6<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
    boxsum_stage7<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,listid_g,xin_g,
						    data1in_g,data2in_g,xout_g,
						    data1out_g,data2out_g);
  }
}

	.text
	.file	"boxsortinc.hip"
	.globl	_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_ # -- Begin function _Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
	.type	_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_,@function
_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_:   # @_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %r12
	movq	%r8, 32(%rsp)                   # 8-byte Spill
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	movq	%rdx, 8(%rsp)                   # 8-byte Spill
	movl	%esi, %ebx
	movl	%edi, %ebp
	leal	127(%rbx), %eax
	leal	254(%rbx), %r14d
	testl	%eax, %eax
	cmovnsl	%eax, %r14d
	movq	112(%rsp), %r13
	sarl	$7, %r14d
	movl	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip), %eax
	testl	%edi, %edi
	jle	.LBB0_2
# %bb.1:
	testl	%ebx, %ebx
	jle	.LBB0_2
# %bb.5:
	cmpl	%ebp, %eax
	jl	.LBB0_7
# %bb.6:
	cmpl	%ebx, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
	jge	.LBB0_11
.LBB0_7:
	testl	%eax, %eax
	jle	.LBB0_9
# %bb.8:
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
	callq	hipFree
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
	callq	hipFree
.LBB0_9:
	movslq	%r14d, %rsi
	shlq	$2, %rsi
	movl	$_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g, %edi
	callq	hipMalloc
	movl	%ebp, %esi
	shlq	$2, %rsi
	movl	$_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g, %edi
	callq	hipMalloc
	movl	%ebp, %r15d
	movl	%ebx, %eax
	jmp	.LBB0_10
.LBB0_2:
	xorl	%r15d, %r15d
	testl	%eax, %eax
	jle	.LBB0_3
# %bb.4:
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
	callq	hipFree
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
	callq	hipFree
.LBB0_3:
	xorl	%eax, %eax
.LBB0_10:                               # %.sink.split
	movl	%r15d, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip)
	movl	%eax, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
.LBB0_11:
	testl	%ebp, %ebp
	jle	.LBB0_26
# %bb.12:
	testl	%ebx, %ebx
	jle	.LBB0_26
# %bb.13:
	movq	%r12, 16(%rsp)                  # 8-byte Spill
	movabsq	$4294967424, %r15               # imm = 0x100000080
	leaq	-72(%r15), %r12
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_15
# %bb.14:
	movl	%ebx, %edi
	movq	%r13, %rsi
	callq	_ZL28__device_stub__boxsum_stage1iPi
.LBB0_15:
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_17
# %bb.16:
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdx
	movl	%ebp, %edi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	%r13, %rcx
	callq	_ZL28__device_stub__boxsum_stage2iPiS_S_
.LBB0_17:
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_19
# %bb.18:
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdx
	movl	%ebx, %edi
	movq	%r13, %rsi
	callq	_ZL28__device_stub__boxsum_stage3iPiS_
.LBB0_19:
	leaq	-127(%r15), %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_21
# %bb.20:
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rsi
	movl	%r14d, %edi
	callq	_ZL28__device_stub__boxsum_stage4iPi
.LBB0_21:
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_23
# %bb.22:
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdx
	movl	%ebx, %edi
	movq	%r13, %rsi
	callq	_ZL28__device_stub__boxsum_stage5iPiS_
.LBB0_23:
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_25
# %bb.24:
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdx
	movl	%ebp, %edi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	%r13, %rcx
	callq	_ZL28__device_stub__boxsum_stage6iPiS_S_
.LBB0_25:
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	16(%rsp), %r9                   # 8-byte Reload
	je	.LBB0_27
.LBB0_26:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_27:
	.cfi_def_cfa_offset 96
	movq	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rsi
	movl	%ebp, %edi
	movq	8(%rsp), %rdx                   # 8-byte Reload
	movq	24(%rsp), %rcx                  # 8-byte Reload
	movq	32(%rsp), %r8                   # 8-byte Reload
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_ # TAILCALL
.Lfunc_end0:
	.size	_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_, .Lfunc_end0-_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
	.cfi_endproc
                                        # -- End function
	.type	_ZL28__device_stub__boxsum_stage1iPi,@function # -- Begin function _ZL28__device_stub__boxsum_stage1iPi
_ZL28__device_stub__boxsum_stage1iPi:   # @_ZL28__device_stub__boxsum_stage1iPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL13boxsum_stage1iPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZL28__device_stub__boxsum_stage1iPi, .Lfunc_end1-_ZL28__device_stub__boxsum_stage1iPi
	.cfi_endproc
                                        # -- End function
	.type	_ZL28__device_stub__boxsum_stage2iPiS_S_,@function # -- Begin function _ZL28__device_stub__boxsum_stage2iPiS_S_
_ZL28__device_stub__boxsum_stage2iPiS_S_: # @_ZL28__device_stub__boxsum_stage2iPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL13boxsum_stage2iPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_ZL28__device_stub__boxsum_stage2iPiS_S_, .Lfunc_end2-_ZL28__device_stub__boxsum_stage2iPiS_S_
	.cfi_endproc
                                        # -- End function
	.type	_ZL28__device_stub__boxsum_stage3iPiS_,@function # -- Begin function _ZL28__device_stub__boxsum_stage3iPiS_
_ZL28__device_stub__boxsum_stage3iPiS_: # @_ZL28__device_stub__boxsum_stage3iPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL13boxsum_stage3iPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZL28__device_stub__boxsum_stage3iPiS_, .Lfunc_end3-_ZL28__device_stub__boxsum_stage3iPiS_
	.cfi_endproc
                                        # -- End function
	.type	_ZL28__device_stub__boxsum_stage4iPi,@function # -- Begin function _ZL28__device_stub__boxsum_stage4iPi
_ZL28__device_stub__boxsum_stage4iPi:   # @_ZL28__device_stub__boxsum_stage4iPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL13boxsum_stage4iPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_ZL28__device_stub__boxsum_stage4iPi, .Lfunc_end4-_ZL28__device_stub__boxsum_stage4iPi
	.cfi_endproc
                                        # -- End function
	.type	_ZL28__device_stub__boxsum_stage5iPiS_,@function # -- Begin function _ZL28__device_stub__boxsum_stage5iPiS_
_ZL28__device_stub__boxsum_stage5iPiS_: # @_ZL28__device_stub__boxsum_stage5iPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL13boxsum_stage5iPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZL28__device_stub__boxsum_stage5iPiS_, .Lfunc_end5-_ZL28__device_stub__boxsum_stage5iPiS_
	.cfi_endproc
                                        # -- End function
	.type	_ZL28__device_stub__boxsum_stage6iPiS_S_,@function # -- Begin function _ZL28__device_stub__boxsum_stage6iPiS_S_
_ZL28__device_stub__boxsum_stage6iPiS_S_: # @_ZL28__device_stub__boxsum_stage6iPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL13boxsum_stage6iPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_ZL28__device_stub__boxsum_stage6iPiS_S_, .Lfunc_end6-_ZL28__device_stub__boxsum_stage6iPiS_S_
	.cfi_endproc
                                        # -- End function
	.type	_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_,@function # -- Begin function _ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_: # @_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, .Lfunc_end7-_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL13boxsum_stage1iPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL13boxsum_stage2iPiS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL13boxsum_stage3iPiS_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL13boxsum_stage4iPi, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL13boxsum_stage5iPiS_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL13boxsum_stage6iPiS_S_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init,@object # @_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init
	.local	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init
	.comm	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init,4,4
	.type	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init,@object # @_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init
	.local	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init
	.comm	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init,4,4
	.type	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g,@object # @_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g
	.local	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g
	.comm	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g,8,8
	.type	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g,@object # @_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g
	.local	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g
	.comm	_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g,8,8
	.type	_ZL13boxsum_stage1iPi,@object   # @_ZL13boxsum_stage1iPi
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL13boxsum_stage1iPi:
	.quad	_ZL28__device_stub__boxsum_stage1iPi
	.size	_ZL13boxsum_stage1iPi, 8

	.type	_ZL13boxsum_stage2iPiS_S_,@object # @_ZL13boxsum_stage2iPiS_S_
	.p2align	3, 0x0
_ZL13boxsum_stage2iPiS_S_:
	.quad	_ZL28__device_stub__boxsum_stage2iPiS_S_
	.size	_ZL13boxsum_stage2iPiS_S_, 8

	.type	_ZL13boxsum_stage3iPiS_,@object # @_ZL13boxsum_stage3iPiS_
	.p2align	3, 0x0
_ZL13boxsum_stage3iPiS_:
	.quad	_ZL28__device_stub__boxsum_stage3iPiS_
	.size	_ZL13boxsum_stage3iPiS_, 8

	.type	_ZL13boxsum_stage4iPi,@object   # @_ZL13boxsum_stage4iPi
	.p2align	3, 0x0
_ZL13boxsum_stage4iPi:
	.quad	_ZL28__device_stub__boxsum_stage4iPi
	.size	_ZL13boxsum_stage4iPi, 8

	.type	_ZL13boxsum_stage5iPiS_,@object # @_ZL13boxsum_stage5iPiS_
	.p2align	3, 0x0
_ZL13boxsum_stage5iPiS_:
	.quad	_ZL28__device_stub__boxsum_stage5iPiS_
	.size	_ZL13boxsum_stage5iPiS_, 8

	.type	_ZL13boxsum_stage6iPiS_S_,@object # @_ZL13boxsum_stage6iPiS_S_
	.p2align	3, 0x0
_ZL13boxsum_stage6iPiS_S_:
	.quad	_ZL28__device_stub__boxsum_stage6iPiS_S_
	.size	_ZL13boxsum_stage6iPiS_S_, 8

	.type	_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_,@object # @_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
	.p2align	3, 0x0
_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_:
	.quad	_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
	.size	_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZL13boxsum_stage1iPi"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZL13boxsum_stage2iPiS_S_"
	.size	.L__unnamed_2, 26

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZL13boxsum_stage3iPiS_"
	.size	.L__unnamed_3, 24

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZL13boxsum_stage4iPi"
	.size	.L__unnamed_4, 22

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_ZL13boxsum_stage5iPiS_"
	.size	.L__unnamed_5, 24

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_ZL13boxsum_stage6iPiS_S_"
	.size	.L__unnamed_6, 26

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_"
	.size	.L__unnamed_7, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZL28__device_stub__boxsum_stage1iPi
	.addrsig_sym _ZL28__device_stub__boxsum_stage2iPiS_S_
	.addrsig_sym _ZL28__device_stub__boxsum_stage3iPiS_
	.addrsig_sym _ZL28__device_stub__boxsum_stage4iPi
	.addrsig_sym _ZL28__device_stub__boxsum_stage5iPiS_
	.addrsig_sym _ZL28__device_stub__boxsum_stage6iPiS_S_
	.addrsig_sym _ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g
	.addrsig_sym _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g
	.addrsig_sym _ZL13boxsum_stage1iPi
	.addrsig_sym _ZL13boxsum_stage2iPiS_S_
	.addrsig_sym _ZL13boxsum_stage3iPiS_
	.addrsig_sym _ZL13boxsum_stage4iPi
	.addrsig_sym _ZL13boxsum_stage5iPiS_
	.addrsig_sym _ZL13boxsum_stage6iPiS_S_
	.addrsig_sym _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL13boxsum_stage1iPi,"axG",@progbits,_ZL13boxsum_stage1iPi,comdat
	.globl	_ZL13boxsum_stage1iPi           ; -- Begin function _ZL13boxsum_stage1iPi
	.p2align	8
	.type	_ZL13boxsum_stage1iPi,@function
_ZL13boxsum_stage1iPi:                  ; @_ZL13boxsum_stage1iPi
; %bb.0:
	s_load_b32 s6, s[0:1], 0x0
	s_lshl_b32 s2, s15, 7
	s_mov_b32 s3, exec_lo
	v_add_nc_u32_e32 v2, s2, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s6, v2
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x8
	s_ashr_i32 s4, s2, 31
	v_add_co_u32 v0, s2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v1, null, s4, 0, s2
	v_mov_b32_e32 v3, 0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s2, s3, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s1, 0
	s_lshl_b64 s[4:5], s[2:3], 2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v2, s2, v2
	global_store_b32 v[0:1], v3, off
	v_add_co_u32 v0, s0, v0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	v_cmp_le_i32_e32 vcc_lo, s6, v2
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL13boxsum_stage1iPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL13boxsum_stage1iPi,"axG",@progbits,_ZL13boxsum_stage1iPi,comdat
.Lfunc_end0:
	.size	_ZL13boxsum_stage1iPi, .Lfunc_end0-_ZL13boxsum_stage1iPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 192
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL13boxsum_stage2iPiS_S_,"axG",@progbits,_ZL13boxsum_stage2iPiS_S_,comdat
	.globl	_ZL13boxsum_stage2iPiS_S_       ; -- Begin function _ZL13boxsum_stage2iPiS_S_
	.p2align	8
	.type	_ZL13boxsum_stage2iPiS_S_,@function
_ZL13boxsum_stage2iPiS_S_:              ; @_ZL13boxsum_stage2iPiS_S_
; %bb.0:
	s_load_b32 s10, s[0:1], 0x0
	s_lshl_b32 s12, s15, 7
	s_waitcnt lgkmcnt(0)
	s_cmp_le_i32 s10, s12
	s_cbranch_scc1 .LBB1_13
; %bb.1:                                ; %.lr.ph
	v_mul_u32_u24_e32 v1, 19, v0
	v_lshlrev_b32_e32 v2, 2, v0
	s_clause 0x2
	s_load_b32 s13, s[0:1], 0x20
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x18
	v_dual_mov_b32 v15, 1 :: v_dual_add_nc_u32 v14, s10, v0
	v_add_nc_u32_e32 v0, s12, v0
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_and_b32_e32 v1, 0x7f, v1
	v_add_nc_u32_e32 v8, 0x200, v2
	s_mov_b64 s[8:9], src_shared_base
	s_mov_b32 s11, 0
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_lshlrev_b32_e32 v4, 2, v1
	v_ashrrev_i32_e32 v1, 31, v0
	v_cndmask_b32_e64 v3, 0, s9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, -1, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_or_b32_e32 v6, 0x200, v4
	v_lshlrev_b64 v[10:11], 2, v[0:1]
	v_cmp_ne_u32_e64 s0, -1, v4
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cndmask_b32_e64 v9, 0, s9, vcc_lo
	v_cmp_ne_u32_e64 s1, -1, v6
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s8, s13, 7
	v_add_co_u32 v10, vcc_lo, s4, v10
	v_cndmask_b32_e64 v4, 0, v4, s0
	v_cndmask_b32_e64 v5, 0, s9, s0
	v_cndmask_b32_e64 v6, 0, v6, s1
	v_cndmask_b32_e64 v7, 0, s9, s1
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	s_ashr_i32 s9, s8, 31
	s_sub_i32 s1, s10, s12
	s_lshl_b64 s[4:5], s[8:9], 2
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_cmpk_gt_i32 s1, 0x7f
	s_cbranch_scc0 .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	global_load_b32 v12, v[10:11], off
	s_mov_b32 s12, 0
	s_mov_b32 s0, -1
	s_waitcnt vmcnt(0)
	flat_store_b32 v[2:3], v12 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v12, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s2, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	global_atomic_add_u32 v12, v[12:13], v15, off glc
	s_waitcnt vmcnt(0)
	flat_store_b32 v[6:7], v12 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v16, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	s_branch .LBB1_5
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr16
.LBB1_5:                                ; %Flow
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_9
; %bb.6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s12, exec_lo
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr12_vgpr13
	v_cmpx_gt_i32_e64 s10, v0
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_2 Depth=1
	global_load_b32 v12, v[10:11], off
	s_or_b32 s0, s0, exec_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s2, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u32 v16, v[12:13], v15, off glc
	v_ashrrev_i32_e32 v13, 31, v0
	v_mov_b32_e32 v12, v0
.LBB1_8:                                ; %Flow51
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_branch .LBB1_10
.LBB1_9:                                ;   in Loop: Header=BB1_2 Depth=1
	v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
.LBB1_10:                               ; %Flow50
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB1_12
; %bb.11:                               ; %.sink.split
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v12, vcc_lo, s6, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	global_store_b32 v[12:13], v16, off
.LBB1_12:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_add_co_u32 v0, vcc_lo, v0, s8
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v10, s0, v10, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v0, v14
	v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
	s_sub_i32 s1, s1, s8
	s_or_b32 s11, vcc_lo, s11
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_2
.LBB1_13:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL13boxsum_stage2iPiS_S_
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL13boxsum_stage2iPiS_S_,"axG",@progbits,_ZL13boxsum_stage2iPiS_S_,comdat
.Lfunc_end1:
	.size	_ZL13boxsum_stage2iPiS_S_, .Lfunc_end1-_ZL13boxsum_stage2iPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 628
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL13boxsum_stage3iPiS_,"axG",@progbits,_ZL13boxsum_stage3iPiS_,comdat
	.globl	_ZL13boxsum_stage3iPiS_         ; -- Begin function _ZL13boxsum_stage3iPiS_
	.p2align	8
	.type	_ZL13boxsum_stage3iPiS_,@function
_ZL13boxsum_stage3iPiS_:                ; @_ZL13boxsum_stage3iPiS_
; %bb.0:
	s_load_b32 s10, s[0:1], 0x0
	s_lshl_b32 s2, s15, 7
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s2, s10
	s_cbranch_scc1 .LBB2_11
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b32_e32 v2, 2, v0
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x8
	v_add_nc_u32_e32 v1, s2, v0
	s_mov_b64 s[2:3], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, s3 :: v_dual_add_nc_u32 v22, s10, v0
	v_cmp_ne_u32_e64 s1, -1, v2
	v_add_nc_u32_e32 v8, 0x80, v2
	v_add_nc_u32_e32 v6, 0x100, v2
	v_add_nc_u32_e32 v12, 32, v2
	v_add_nc_u32_e32 v10, 64, v2
	v_cndmask_b32_e64 v4, 0, v2, s1
	v_cndmask_b32_e64 v5, 0, s3, s1
	v_cmp_ne_u32_e64 s1, -1, v8
	v_cmp_ne_u32_e64 s2, -1, v6
	v_add_nc_u32_e32 v14, 16, v2
	v_add_nc_u32_e32 v16, 8, v2
	v_add_nc_u32_e32 v18, 4, v2
	v_cndmask_b32_e64 v8, 0, v8, s1
	v_cndmask_b32_e64 v9, 0, s3, s1
	v_cmp_ne_u32_e64 s1, -1, v12
	v_ashrrev_i32_e32 v2, 31, v1
	v_cndmask_b32_e64 v6, 0, v6, s2
	v_cndmask_b32_e64 v7, 0, s3, s2
	v_cmp_ne_u32_e64 s2, -1, v10
	v_cndmask_b32_e64 v12, 0, v12, s1
	v_cndmask_b32_e64 v13, 0, s3, s1
	v_cmp_ne_u32_e64 s1, -1, v14
	v_lshlrev_b64 v[20:21], 2, v[1:2]
	v_cndmask_b32_e64 v10, 0, v10, s2
	v_cndmask_b32_e64 v11, 0, s3, s2
	v_cmp_ne_u32_e64 s2, -1, v16
	v_cndmask_b32_e64 v14, 0, v14, s1
	v_cndmask_b32_e64 v15, 0, s3, s1
	v_cmp_ne_u32_e64 s1, -1, v18
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s8, s8, 7
	v_cndmask_b32_e64 v16, 0, v16, s2
	v_cndmask_b32_e64 v17, 0, s3, s2
	v_add_co_u32 v20, s2, s4, v20
	v_cmp_gt_u32_e32 vcc_lo, 64, v0
	v_cmp_gt_u32_e64 s0, 32, v0
	v_cndmask_b32_e64 v18, 0, v18, s1
	v_cndmask_b32_e64 v19, 0, s3, s1
	v_cmp_eq_u32_e64 s1, 0, v0
	v_add_co_ci_u32_e64 v21, s2, s5, v21, s2
	v_mov_b32_e32 v2, 0
	s_ashr_i32 s9, s8, 31
	s_mov_b32 s11, 0
	s_lshl_b64 s[4:5], s[8:9], 2
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	global_load_b32 v0, v[20:21], off
.LBB2_4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	flat_store_b32 v[4:5], v0 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_2 Depth=1
	flat_load_b32 v0, v[6:7] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v23, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v23, v0
	flat_store_b32 v[4:5], v0 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_6:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB2_8
; %bb.7:                                ;   in Loop: Header=BB2_2 Depth=1
	flat_load_b32 v0, v[8:9] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v23, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v23, v0
	flat_store_b32 v[4:5], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[10:11] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v23, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v23, v0
	flat_store_b32 v[4:5], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[12:13] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v23, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v23, v0
	flat_store_b32 v[4:5], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[14:15] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v23, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v23, v0
	flat_store_b32 v[4:5], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[16:17] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v23, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v23, v0
	flat_store_b32 v[4:5], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v0, v[18:19] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v23, v[4:5] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v0, v23, v0
	flat_store_b32 v[4:5], v0 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_8:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB2_10
; %bb.9:                                ;   in Loop: Header=BB2_2 Depth=1
	flat_load_b32 v0, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v23, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v23, 25, v23
	v_add_nc_u32_e32 v23, v1, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v23, 7, v23
	v_ashrrev_i32_e32 v24, 31, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	v_add_co_u32 v23, s2, s6, v23
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v24, s2, s7, v24, s2
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[23:24], v0, off
.LBB2_10:                               ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v1, s8, v1
	v_add_co_u32 v20, s3, v20, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v21, s3, s5, v21, s3
	v_cmp_ge_i32_e64 s2, v1, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s11, s2, s11
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB2_2
.LBB2_11:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL13boxsum_stage3iPiS_
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL13boxsum_stage3iPiS_,"axG",@progbits,_ZL13boxsum_stage3iPiS_,comdat
.Lfunc_end2:
	.size	_ZL13boxsum_stage3iPiS_, .Lfunc_end2-_ZL13boxsum_stage3iPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 924
; NumSgprs: 18
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL13boxsum_stage4iPi,"axG",@progbits,_ZL13boxsum_stage4iPi,comdat
	.globl	_ZL13boxsum_stage4iPi           ; -- Begin function _ZL13boxsum_stage4iPi
	.p2align	8
	.type	_ZL13boxsum_stage4iPi,@function
_ZL13boxsum_stage4iPi:                  ; @_ZL13boxsum_stage4iPi
; %bb.0:
	s_cmp_lg_u32 s15, 0
	s_cbranch_scc1 .LBB3_12
; %bb.1:                                ; %.preheader
	s_load_b32 s4, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB3_12
; %bb.2:                                ; %.lr.ph
	s_load_b64 s[2:3], s[0:1], 0x8
	s_mov_b64 s[0:1], src_shared_base
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v4, s1 :: v_dual_lshlrev_b32 v1, 2, v0
	v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, s4, v0
	v_mov_b32_e32 v3, 0x1fc
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_mov_b32_e32 v5, v0
	s_mov_b32 s5, 0
	v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v1, 0, v1
	v_cndmask_b32_e64 v2, 0, s1, vcc_lo
.LBB3_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_6 Depth 2
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s4, v5
	v_mov_b32_e32 v9, 0
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB3_5
; %bb.4:                                ;   in Loop: Header=BB3_3 Depth=1
	v_lshlrev_b64 v[9:10], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v9, s0, s2, v9
	v_add_co_ci_u32_e64 v10, s0, s3, v10, s0
	global_load_b32 v9, v[9:10], off
.LBB3_5:                                ;   in Loop: Header=BB3_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s6, 1
	s_waitcnt vmcnt(0)
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_6:                                ;   Parent Loop BB3_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s7, exec_lo
	v_cmpx_le_u32_e64 s6, v0
	s_cbranch_execz .LBB3_8
; %bb.7:                                ;   in Loop: Header=BB3_6 Depth=2
	v_subrev_nc_u32_e32 v10, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v10, 2, v10
	v_cmp_ne_u32_e64 s0, -1, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, 0, v10, s0
	v_cndmask_b32_e64 v11, 0, s1, s0
	flat_load_b32 v10, v[10:11] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v9, v10, v9
.LBB3_8:                                ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s7
	s_lshl_b32 s0, s6, 1
	s_cmp_lt_u32 s6, 64
	s_mov_b32 s6, s0
	s_barrier
	buffer_gl0_inv
	flat_store_b32 v[1:2], v9 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB3_6
; %bb.9:                                ;   in Loop: Header=BB3_3 Depth=1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB3_11
; %bb.10:                               ;   in Loop: Header=BB3_3 Depth=1
	flat_load_b32 v11, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_lshlrev_b64 v[9:10], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v8
	global_store_b32 v[9:10], v11, off
.LBB3_11:                               ;   in Loop: Header=BB3_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	flat_load_b32 v9, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 0x80, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v5, v7
	s_or_b32 s5, vcc_lo, s5
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v8, v9, v8
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB3_3
.LBB3_12:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL13boxsum_stage4iPi
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL13boxsum_stage4iPi,"axG",@progbits,_ZL13boxsum_stage4iPi,comdat
.Lfunc_end3:
	.size	_ZL13boxsum_stage4iPi, .Lfunc_end3-_ZL13boxsum_stage4iPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 468
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL13boxsum_stage5iPiS_,"axG",@progbits,_ZL13boxsum_stage5iPiS_,comdat
	.globl	_ZL13boxsum_stage5iPiS_         ; -- Begin function _ZL13boxsum_stage5iPiS_
	.p2align	8
	.type	_ZL13boxsum_stage5iPiS_,@function
_ZL13boxsum_stage5iPiS_:                ; @_ZL13boxsum_stage5iPiS_
; %bb.0:
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 2, v0
	s_load_b32 s3, s[0:1], 0x0
	s_mov_b64 s[8:9], src_shared_base
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, 4, v4
	v_cmp_ne_u32_e32 vcc_lo, -1, v2
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_add_nc_u32 v3, 0x404, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s2, -1, v3
	v_cndmask_b32_e64 v5, 0, v3, s2
	v_cndmask_b32_e64 v3, 0, s9, vcc_lo
	v_cndmask_b32_e64 v6, 0, s9, s2
	s_lshl_b32 s2, s15, 7
	flat_store_b32 v[2:3], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_store_b32 v[5:6], v1 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s2, s3
	s_cbranch_scc1 .LBB4_9
; %bb.1:                                ; %.lr.ph
	v_add_nc_u32_e32 v2, 0x204, v4
	s_load_b128 s[4:7], s[0:1], 0x8
	v_add_nc_u32_e32 v27, s3, v0
	v_add_nc_u32_e32 v3, s2, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_cmp_ne_u32_e64 s0, -1, v2
	v_add_nc_u32_e32 v0, 0x604, v4
	v_add_nc_u32_e32 v7, 0x200, v4
	v_add_nc_u32_e32 v11, 0x5fc, v4
	v_add_nc_u32_e32 v15, 0x5e4, v4
	v_cndmask_b32_e64 v5, 0, v2, s0
	v_mov_b32_e32 v2, s9
	v_cndmask_b32_e64 v6, 0, s9, s0
	v_cmp_ne_u32_e64 s0, -1, v0
	v_cmp_ne_u32_e64 s1, -1, v7
	v_add_nc_u32_e32 v19, 0x584, v4
	v_add_nc_u32_e32 v21, 0x104, v4
	v_mov_b32_e32 v25, 0x800
	v_cndmask_b32_e64 v9, 0, v0, s0
	v_add_nc_u32_e32 v0, 0x1f4, v4
	v_cndmask_b32_e64 v10, 0, s9, s0
	v_cndmask_b32_e64 v7, 0, v7, s1
	v_cndmask_b32_e64 v8, 0, s9, s1
	v_cmp_ne_u32_e64 s1, -1, v11
	v_cmp_ne_u32_e64 s0, -1, v0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, 0, v11, s1
	v_cndmask_b32_e64 v13, 0, v0, s0
	v_add_nc_u32_e32 v0, 0x1c4, v4
	v_ashrrev_i32_e32 v4, 31, v3
	v_cndmask_b32_e64 v14, 0, s9, s0
	v_cndmask_b32_e64 v12, 0, s9, s1
	v_cmp_ne_u32_e64 s1, -1, v15
	v_cmp_ne_u32_e64 s0, -1, v0
	v_lshlrev_b64 v[23:24], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, 0, v15, s1
	v_cndmask_b32_e64 v17, 0, v0, s0
	v_cndmask_b32_e64 v18, 0, s9, s0
	v_cmp_ne_u32_e64 s0, -1, v21
	v_cndmask_b32_e64 v16, 0, s9, s1
	v_cmp_ne_u32_e64 s1, -1, v19
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v21, 0, v21, s0
	v_cndmask_b32_e64 v22, 0, s9, s0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v23, s0, s4, v23
	v_cndmask_b32_e64 v19, 0, v19, s1
	v_cndmask_b32_e64 v20, 0, s9, s1
	v_add_co_ci_u32_e64 v24, s0, s5, v24, s0
.LBB4_2:                                ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB4_4
; %bb.3:                                ;   in Loop: Header=BB4_2 Depth=1
	v_ashrrev_i32_e32 v0, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 25, v0
	v_add_nc_u32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 7, v0
	v_ashrrev_i32_e32 v29, 31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	v_add_co_u32 v28, s0, s6, v28
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v29, s0, s7, v29, s0
	global_load_b32 v0, v[28:29], off
	s_waitcnt vmcnt(0)
	flat_store_b32 v[1:2], v0 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_4:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_gt_i32_e64 s0, s3, v3
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_6
; %bb.5:                                ;   in Loop: Header=BB4_2 Depth=1
	global_load_b32 v0, v[23:24], off
.LBB4_6:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	flat_store_b32 v[5:6], v0 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v4, v[7:8] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v4, v0
	flat_store_b32 v[9:10], v4 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v26, v[11:12] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v26, v4
	flat_store_b32 v[5:6], v4 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v26, v[13:14] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v26, v4
	flat_store_b32 v[9:10], v4 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v26, v[15:16] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v26, v4
	flat_store_b32 v[5:6], v4 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v26, v[17:18] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v26, v4
	flat_store_b32 v[9:10], v4 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v26, v[19:20] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v26, v4
	flat_store_b32 v[5:6], v4 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v26, v[21:22] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v4, v26, v4
	v_mov_b32_e32 v26, v2
	flat_store_b32 v[9:10], v4 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	flat_load_b32 v28, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v26, v[25:26] glc dlc
	s_waitcnt vmcnt(0)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_8
; %bb.7:                                ;   in Loop: Header=BB4_2 Depth=1
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v4, v4, v28
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v0, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v4, v0
	global_store_b32 v[23:24], v0, off
.LBB4_8:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v3, 0x1c00, v3
	v_add_co_u32 v23, s1, 0x7000, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v24, s1, 0, v24, s1
	v_cmp_ge_i32_e64 s0, v3, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB4_2
.LBB4_9:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL13boxsum_stage5iPiS_
		.amdhsa_group_segment_fixed_size 2052
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL13boxsum_stage5iPiS_,"axG",@progbits,_ZL13boxsum_stage5iPiS_,comdat
.Lfunc_end4:
	.size	_ZL13boxsum_stage5iPiS_, .Lfunc_end4-_ZL13boxsum_stage5iPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1120
; NumSgprs: 18
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2052 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL13boxsum_stage6iPiS_S_,"axG",@progbits,_ZL13boxsum_stage6iPiS_S_,comdat
	.globl	_ZL13boxsum_stage6iPiS_S_       ; -- Begin function _ZL13boxsum_stage6iPiS_S_
	.p2align	8
	.type	_ZL13boxsum_stage6iPiS_S_,@function
_ZL13boxsum_stage6iPiS_S_:              ; @_ZL13boxsum_stage6iPiS_S_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x0
	s_lshl_b32 s2, s15, 7
	s_mov_b32 s3, exec_lo
	v_add_nc_u32_e32 v6, s2, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v6
	s_cbranch_execz .LBB5_5
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[8:11], s[0:1], 0x8
	s_ashr_i32 s3, s2, 31
	v_add_co_u32 v0, s2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, null, s3, 0, s2
	s_load_b64 s[2:3], s[0:1], 0x18
	s_mov_b32 s1, 0
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
.LBB5_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v0, v[4:5], off
	global_load_b32 v7, v[2:3], off
	v_mov_b32_e32 v8, 0
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(1)
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB5_4
; %bb.3:                                ;   in Loop: Header=BB5_2 Depth=1
	v_lshlrev_b64 v[8:9], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_b32 v8, v[8:9], off
.LBB5_4:                                ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v8, v7
	v_add_nc_u32_e32 v6, 0x1c00, v6
	v_add_co_u32 v4, s0, 0x7000, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
	global_store_b32 v[2:3], v0, off
	v_add_co_u32 v2, vcc_lo, 0x7000, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s4, v6
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB5_2
.LBB5_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL13boxsum_stage6iPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL13boxsum_stage6iPiS_S_,"axG",@progbits,_ZL13boxsum_stage6iPiS_S_,comdat
.Lfunc_end5:
	.size	_ZL13boxsum_stage6iPiS_S_, .Lfunc_end5-_ZL13boxsum_stage6iPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_,"axG",@progbits,_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_,comdat
	.globl	_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_ ; -- Begin function _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
	.p2align	8
	.type	_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_,@function
_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_: ; @_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
; %bb.0:
	s_load_b32 s16, s[0:1], 0x0
	s_lshl_b32 s2, s15, 7
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s2, s16
	s_cbranch_scc1 .LBB6_10
; %bb.1:                                ; %.lr.ph52
	v_add_nc_u32_e32 v1, s2, v0
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b128 s[12:15], s[0:1], 0x28
	s_load_b64 s[2:3], s[0:1], 0x38
	v_lshlrev_b32_e32 v3, 2, v0
	v_mul_hi_u32_u24_e32 v6, 12, v0
	s_mov_b64 s[0:1], src_shared_base
	v_ashrrev_i32_e32 v2, 31, v1
	v_and_b32_e32 v9, 3, v0
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_add_nc_u32_e32 v13, s16, v0
	v_and_b32_e32 v14, 0x3fc, v0
	v_lshlrev_b64 v[4:5], 4, v[1:2]
	v_mul_u32_u24_e32 v2, 12, v0
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_lshlrev_b32_e32 v15, 2, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_u32 v2, s0, v4, v2
	v_sub_co_ci_u32_e64 v8, s0, v5, v6, s0
	v_cndmask_b32_e64 v4, 0, s1, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	s_mov_b32 s8, 0
.LBB6_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB6_8 Depth 2
	v_cmp_gt_i32_e32 vcc_lo, s16, v1
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v9, 0
	s_and_saveexec_b32 s9, vcc_lo
	s_cbranch_execz .LBB6_4
; %bb.3:                                ;   in Loop: Header=BB6_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[1:2]
	v_add_co_u32 v9, s0, s4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, s5, v10, s0
	global_load_b32 v9, v[9:10], off
.LBB6_4:                                ;   in Loop: Header=BB6_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	flat_store_b32 v[3:4], v9 dlc
	s_waitcnt_vscnt null, 0x0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB6_6
; %bb.5:                                ;   in Loop: Header=BB6_2 Depth=1
	v_lshlrev_b64 v[10:11], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v2, v[10:11], off
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, vcc_lo, s12, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s13, v10, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[9:10], v2, off
.LBB6_6:                                ;   in Loop: Header=BB6_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_sub_nc_u32_e32 v2, v0, v1
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s16, v2
	v_min_i32_e32 v2, 0x80, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 2, v2
	v_cmpx_lt_i32_e64 v0, v2
	s_cbranch_execz .LBB6_9
; %bb.7:                                ; %.lr.ph
                                        ;   in Loop: Header=BB6_2 Depth=1
	v_mov_b32_e32 v10, v8
	v_dual_mov_b32 v12, v6 :: v_dual_mov_b32 v17, v0
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v9, v7
	v_mov_b32_e32 v11, v5
	s_mov_b32 s10, 0
.LBB6_8:                                ;   Parent Loop BB6_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v16
	global_load_b32 v22, v[11:12], off
	global_load_b32 v23, v[9:10], off
	v_add_nc_u32_e32 v17, 0x80, v17
	v_cndmask_b32_e64 v19, 0, s1, vcc_lo
	v_cndmask_b32_e32 v18, 0, v16, vcc_lo
	v_add_nc_u32_e32 v16, 0x80, v16
	flat_load_b32 v20, v[18:19] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 4, v[20:21]
	v_add_co_u32 v20, vcc_lo, s14, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v21, vcc_lo
	v_add_co_u32 v20, vcc_lo, v20, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v11, vcc_lo, 0x200, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	global_store_b32 v[20:21], v22, off
	flat_load_b32 v18, v[18:19] glc dlc
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, 0x200, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 4, v[18:19]
	v_add_co_u32 v18, vcc_lo, s2, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v17, v2
	v_add_co_u32 v18, s0, v18, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, s0, 0, v19, s0
	s_or_b32 s10, vcc_lo, s10
	global_store_b32 v[18:19], v23, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB6_8
.LBB6_9:                                ; %Flow87
                                        ;   in Loop: Header=BB6_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v1, 0x1c00, v1
	v_add_co_u32 v5, vcc_lo, 0x1c000, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v1, v13
	v_add_co_u32 v7, s0, 0x1c000, v7
	v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
	s_or_b32 s8, vcc_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB6_2
.LBB6_10:                               ; %._crit_edge53
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 64
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_,"axG",@progbits,_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_,comdat
.Lfunc_end6:
	.size	_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, .Lfunc_end6-_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 776
; NumSgprs: 19
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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  - 2
...

	.end_amdgpu_metadata
