/* blockDim=[16, 16, 1]
 * 
 * i refers to x coordinate of the j or y pixel
 * j refers to y coordinate of the j or y pixel
 * k refers to x coordinate of the i or x pixel
 * l refers to y coordinate of the i or x pixel
 * */

__global__ void calc_partial_sums7(float const * const A, float *partialSum16x16, float *ZpartialSum16x16, float patchSigma, float filtSigmaSquared, int m, int n) {
  
  __shared__ float Z[256], my_w[256];
  float differences_of_areaG[49];
  
  int i=blockDim.x*blockIdx.x+threadIdx.x+3;
  int j=blockDim.y*blockIdx.y+threadIdx.y+3;
  int k=(blockIdx.z)%(m+6)+3;
  int l=(blockIdx.z)/(m+6)+3;
  int tid=threadIdx.y*16+threadIdx.x;
  
  for (int u=-3; u<=3; u++) {
    for (int v=-3; v<=3; v++) {
      differences_of_areaG[7*(u+3)+v+3]=(A[(l+u)*(m+6)+k+v]-A[(j+u)*(m+6)+i+v])*expf(-(u*u+v*v)/(2*patchSigma)); // The first A is the same for the whole block.
    }
  }
  Z[tid]=expf(-powf(normf(49, differences_of_areaG),2)/(2*filtSigmaSquared));
  my_w[tid]=Z[tid]*A[i+j*(m+6)];
  // Reduction algorithm
  __syncthreads();
  if (tid<128) {Z[tid]+=Z[tid+128]; my_w[tid]+=my_w[tid+128]; } __syncthreads();
  if (tid< 64) {Z[tid]+=Z[tid+ 64]; my_w[tid]+=my_w[tid+ 64]; } __syncthreads();
  if (tid< 32) {Z[tid]+=Z[tid+ 32]; my_w[tid]+=my_w[tid+ 32]; } __syncthreads();
  if (tid< 16) {Z[tid]+=Z[tid+ 16]; my_w[tid]+=my_w[tid+ 16]; } __syncthreads();
  if (tid<  8) {Z[tid]+=Z[tid+  8]; my_w[tid]+=my_w[tid+  8]; } __syncthreads();
  if (tid<  4) {Z[tid]+=Z[tid+  4]; my_w[tid]+=my_w[tid+  4]; } __syncthreads();
  if (tid<  2) {Z[tid]+=Z[tid+  2]; my_w[tid]+=my_w[tid+  2]; } __syncthreads();
  if (tid<  1) {
    // Pass the value to global variable
    ZpartialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=Z[0]+Z[1];
     partialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=my_w[0]+my_w[1];
  }
}

/* blockDim=[16, 16, 1]
 * 
 * i refers to x coordinate of the j or y pixel
 * j refers to y coordinate of the j or y pixel
 * k refers to x coordinate of the i or x pixel
 * l refers to y coordinate of the i or x pixel
 * */

__global__ void calc_partial_sums5(float const * const A, float *partialSum16x16, float *ZpartialSum16x16, float patchSigma, float filtSigmaSquared, int m, int n) {
  
  __shared__ float Z[256], my_w[256];
  float differences_of_areaG[25];
  
  int i=blockDim.x*blockIdx.x+threadIdx.x+2;
  int j=blockDim.y*blockIdx.y+threadIdx.y+2;
  int k=(blockIdx.z)%(m+4)+2;
  int l=(blockIdx.z)/(m+4)+2;
  int tid=threadIdx.y*16+threadIdx.x;
  
  for (int u=-2; u<=2; u++) {
    for (int v=-2; v<=2; v++) {
      differences_of_areaG[7*(u+2)+v+2]=(A[(l+u)*(m+4)+k+v]-A[(j+u)*(m+4)+i+v])*expf(-(u*u+v*v)/(2*patchSigma)); // The first A is the same for the whole block.
    }
  }
  Z[tid]=expf(-powf(normf(25, differences_of_areaG),2)/(2*filtSigmaSquared));
  my_w[tid]=Z[tid]*A[i+j*(m+4)];
  // Reduction algorithm
  __syncthreads();
  if (tid<128) {Z[tid]+=Z[tid+128]; my_w[tid]+=my_w[tid+128]; } __syncthreads();
  if (tid< 64) {Z[tid]+=Z[tid+ 64]; my_w[tid]+=my_w[tid+ 64]; } __syncthreads();
  if (tid< 32) {Z[tid]+=Z[tid+ 32]; my_w[tid]+=my_w[tid+ 32]; } __syncthreads();
  if (tid< 16) {Z[tid]+=Z[tid+ 16]; my_w[tid]+=my_w[tid+ 16]; } __syncthreads();
  if (tid<  8) {Z[tid]+=Z[tid+  8]; my_w[tid]+=my_w[tid+  8]; } __syncthreads();
  if (tid<  4) {Z[tid]+=Z[tid+  4]; my_w[tid]+=my_w[tid+  4]; } __syncthreads();
  if (tid<  2) {Z[tid]+=Z[tid+  2]; my_w[tid]+=my_w[tid+  2]; } __syncthreads();
  if (tid<  1) {
    // Pass the value to global variable
    ZpartialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=Z[0]+Z[1];
     partialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=my_w[0]+my_w[1];
  }
}

__global__ void calc_partial_sums3(float const * const A, float *partialSum16x16, float *ZpartialSum16x16, float patchSigma, float filtSigmaSquared, int m, int n) {
  
  __shared__ float Z[256], my_w[256];
  float differences_of_areaG[9];
  
  int i=blockDim.x*blockIdx.x+threadIdx.x+1;
  int j=blockDim.y*blockIdx.y+threadIdx.y+1;
  int k=(blockIdx.z)%(m+2)+1;
  int l=(blockIdx.z)/(m+2)+1;
  int tid=threadIdx.y*16+threadIdx.x;
  
  for (int u=-1; u<=1; u++) {
    for (int v=-1; v<=1; v++) {
      differences_of_areaG[7*(u+1)+v+1]=(A[(l+u)*(m+2)+k+v]-A[(j+u)*(m+2)+i+v])*expf(-(u*u+v*v)/(2*patchSigma)); // The first A is the same for the whole block.
    }
  }
  Z[tid]=expf(-powf(normf(9, differences_of_areaG),2)/(2*filtSigmaSquared));
  my_w[tid]=Z[tid]*A[i+j*(m+2)];
  // Reduction algorithm
  __syncthreads();
  if (tid<128) {Z[tid]+=Z[tid+128]; my_w[tid]+=my_w[tid+128]; } __syncthreads();
  if (tid< 64) {Z[tid]+=Z[tid+ 64]; my_w[tid]+=my_w[tid+ 64]; } __syncthreads();
  if (tid< 32) {Z[tid]+=Z[tid+ 32]; my_w[tid]+=my_w[tid+ 32]; } __syncthreads();
  if (tid< 16) {Z[tid]+=Z[tid+ 16]; my_w[tid]+=my_w[tid+ 16]; } __syncthreads();
  if (tid<  8) {Z[tid]+=Z[tid+  8]; my_w[tid]+=my_w[tid+  8]; } __syncthreads();
  if (tid<  4) {Z[tid]+=Z[tid+  4]; my_w[tid]+=my_w[tid+  4]; } __syncthreads();
  if (tid<  2) {Z[tid]+=Z[tid+  2]; my_w[tid]+=my_w[tid+  2]; } __syncthreads();
  if (tid<  1) {
    // Pass the value to global variable
    ZpartialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=Z[0]+Z[1];
     partialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=my_w[0]+my_w[1];
  }
}

	.file	"tmpxft_00397376_00000000-6_nlm_step1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z18calc_partial_sums7PKfPfS1_ffiiPKfPfS1_ffii
	.type	_Z48__device_stub__Z18calc_partial_sums7PKfPfS1_ffiiPKfPfS1_ffii, @function
_Z48__device_stub__Z18calc_partial_sums7PKfPfS1_ffiiPKfPfS1_ffii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18calc_partial_sums7PKfPfS1_ffii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z48__device_stub__Z18calc_partial_sums7PKfPfS1_ffiiPKfPfS1_ffii, .-_Z48__device_stub__Z18calc_partial_sums7PKfPfS1_ffiiPKfPfS1_ffii
	.globl	_Z18calc_partial_sums7PKfPfS1_ffii
	.type	_Z18calc_partial_sums7PKfPfS1_ffii, @function
_Z18calc_partial_sums7PKfPfS1_ffii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z18calc_partial_sums7PKfPfS1_ffiiPKfPfS1_ffii
	.cfi_endproc
.LFE2033:
	.size	_Z18calc_partial_sums7PKfPfS1_ffii, .-_Z18calc_partial_sums7PKfPfS1_ffii
	.globl	_Z48__device_stub__Z18calc_partial_sums5PKfPfS1_ffiiPKfPfS1_ffii
	.type	_Z48__device_stub__Z18calc_partial_sums5PKfPfS1_ffiiPKfPfS1_ffii, @function
_Z48__device_stub__Z18calc_partial_sums5PKfPfS1_ffiiPKfPfS1_ffii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18calc_partial_sums5PKfPfS1_ffii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z48__device_stub__Z18calc_partial_sums5PKfPfS1_ffiiPKfPfS1_ffii, .-_Z48__device_stub__Z18calc_partial_sums5PKfPfS1_ffiiPKfPfS1_ffii
	.globl	_Z18calc_partial_sums5PKfPfS1_ffii
	.type	_Z18calc_partial_sums5PKfPfS1_ffii, @function
_Z18calc_partial_sums5PKfPfS1_ffii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z18calc_partial_sums5PKfPfS1_ffiiPKfPfS1_ffii
	.cfi_endproc
.LFE2035:
	.size	_Z18calc_partial_sums5PKfPfS1_ffii, .-_Z18calc_partial_sums5PKfPfS1_ffii
	.globl	_Z48__device_stub__Z18calc_partial_sums3PKfPfS1_ffiiPKfPfS1_ffii
	.type	_Z48__device_stub__Z18calc_partial_sums3PKfPfS1_ffiiPKfPfS1_ffii, @function
_Z48__device_stub__Z18calc_partial_sums3PKfPfS1_ffiiPKfPfS1_ffii:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z18calc_partial_sums3PKfPfS1_ffii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L13:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z48__device_stub__Z18calc_partial_sums3PKfPfS1_ffiiPKfPfS1_ffii, .-_Z48__device_stub__Z18calc_partial_sums3PKfPfS1_ffiiPKfPfS1_ffii
	.globl	_Z18calc_partial_sums3PKfPfS1_ffii
	.type	_Z18calc_partial_sums3PKfPfS1_ffii, @function
_Z18calc_partial_sums3PKfPfS1_ffii:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z18calc_partial_sums3PKfPfS1_ffiiPKfPfS1_ffii
	.cfi_endproc
.LFE2037:
	.size	_Z18calc_partial_sums3PKfPfS1_ffii, .-_Z18calc_partial_sums3PKfPfS1_ffii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z18calc_partial_sums3PKfPfS1_ffii"
.LC1:
	.string	"_Z18calc_partial_sums5PKfPfS1_ffii"
.LC2:
	.string	"_Z18calc_partial_sums7PKfPfS1_ffii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18calc_partial_sums3PKfPfS1_ffii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18calc_partial_sums5PKfPfS1_ffii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18calc_partial_sums7PKfPfS1_ffii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/* blockDim=[16, 16, 1]
 * 
 * i refers to x coordinate of the j or y pixel
 * j refers to y coordinate of the j or y pixel
 * k refers to x coordinate of the i or x pixel
 * l refers to y coordinate of the i or x pixel
 * */

__global__ void calc_partial_sums7(float const * const A, float *partialSum16x16, float *ZpartialSum16x16, float patchSigma, float filtSigmaSquared, int m, int n) {
  
  __shared__ float Z[256], my_w[256];
  float differences_of_areaG[49];
  
  int i=blockDim.x*blockIdx.x+threadIdx.x+3;
  int j=blockDim.y*blockIdx.y+threadIdx.y+3;
  int k=(blockIdx.z)%(m+6)+3;
  int l=(blockIdx.z)/(m+6)+3;
  int tid=threadIdx.y*16+threadIdx.x;
  
  for (int u=-3; u<=3; u++) {
    for (int v=-3; v<=3; v++) {
      differences_of_areaG[7*(u+3)+v+3]=(A[(l+u)*(m+6)+k+v]-A[(j+u)*(m+6)+i+v])*expf(-(u*u+v*v)/(2*patchSigma)); // The first A is the same for the whole block.
    }
  }
  Z[tid]=expf(-powf(normf(49, differences_of_areaG),2)/(2*filtSigmaSquared));
  my_w[tid]=Z[tid]*A[i+j*(m+6)];
  // Reduction algorithm
  __syncthreads();
  if (tid<128) {Z[tid]+=Z[tid+128]; my_w[tid]+=my_w[tid+128]; } __syncthreads();
  if (tid< 64) {Z[tid]+=Z[tid+ 64]; my_w[tid]+=my_w[tid+ 64]; } __syncthreads();
  if (tid< 32) {Z[tid]+=Z[tid+ 32]; my_w[tid]+=my_w[tid+ 32]; } __syncthreads();
  if (tid< 16) {Z[tid]+=Z[tid+ 16]; my_w[tid]+=my_w[tid+ 16]; } __syncthreads();
  if (tid<  8) {Z[tid]+=Z[tid+  8]; my_w[tid]+=my_w[tid+  8]; } __syncthreads();
  if (tid<  4) {Z[tid]+=Z[tid+  4]; my_w[tid]+=my_w[tid+  4]; } __syncthreads();
  if (tid<  2) {Z[tid]+=Z[tid+  2]; my_w[tid]+=my_w[tid+  2]; } __syncthreads();
  if (tid<  1) {
    // Pass the value to global variable
    ZpartialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=Z[0]+Z[1];
     partialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=my_w[0]+my_w[1];
  }
}

/* blockDim=[16, 16, 1]
 * 
 * i refers to x coordinate of the j or y pixel
 * j refers to y coordinate of the j or y pixel
 * k refers to x coordinate of the i or x pixel
 * l refers to y coordinate of the i or x pixel
 * */

__global__ void calc_partial_sums5(float const * const A, float *partialSum16x16, float *ZpartialSum16x16, float patchSigma, float filtSigmaSquared, int m, int n) {
  
  __shared__ float Z[256], my_w[256];
  float differences_of_areaG[25];
  
  int i=blockDim.x*blockIdx.x+threadIdx.x+2;
  int j=blockDim.y*blockIdx.y+threadIdx.y+2;
  int k=(blockIdx.z)%(m+4)+2;
  int l=(blockIdx.z)/(m+4)+2;
  int tid=threadIdx.y*16+threadIdx.x;
  
  for (int u=-2; u<=2; u++) {
    for (int v=-2; v<=2; v++) {
      differences_of_areaG[7*(u+2)+v+2]=(A[(l+u)*(m+4)+k+v]-A[(j+u)*(m+4)+i+v])*expf(-(u*u+v*v)/(2*patchSigma)); // The first A is the same for the whole block.
    }
  }
  Z[tid]=expf(-powf(normf(25, differences_of_areaG),2)/(2*filtSigmaSquared));
  my_w[tid]=Z[tid]*A[i+j*(m+4)];
  // Reduction algorithm
  __syncthreads();
  if (tid<128) {Z[tid]+=Z[tid+128]; my_w[tid]+=my_w[tid+128]; } __syncthreads();
  if (tid< 64) {Z[tid]+=Z[tid+ 64]; my_w[tid]+=my_w[tid+ 64]; } __syncthreads();
  if (tid< 32) {Z[tid]+=Z[tid+ 32]; my_w[tid]+=my_w[tid+ 32]; } __syncthreads();
  if (tid< 16) {Z[tid]+=Z[tid+ 16]; my_w[tid]+=my_w[tid+ 16]; } __syncthreads();
  if (tid<  8) {Z[tid]+=Z[tid+  8]; my_w[tid]+=my_w[tid+  8]; } __syncthreads();
  if (tid<  4) {Z[tid]+=Z[tid+  4]; my_w[tid]+=my_w[tid+  4]; } __syncthreads();
  if (tid<  2) {Z[tid]+=Z[tid+  2]; my_w[tid]+=my_w[tid+  2]; } __syncthreads();
  if (tid<  1) {
    // Pass the value to global variable
    ZpartialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=Z[0]+Z[1];
     partialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=my_w[0]+my_w[1];
  }
}

__global__ void calc_partial_sums3(float const * const A, float *partialSum16x16, float *ZpartialSum16x16, float patchSigma, float filtSigmaSquared, int m, int n) {
  
  __shared__ float Z[256], my_w[256];
  float differences_of_areaG[9];
  
  int i=blockDim.x*blockIdx.x+threadIdx.x+1;
  int j=blockDim.y*blockIdx.y+threadIdx.y+1;
  int k=(blockIdx.z)%(m+2)+1;
  int l=(blockIdx.z)/(m+2)+1;
  int tid=threadIdx.y*16+threadIdx.x;
  
  for (int u=-1; u<=1; u++) {
    for (int v=-1; v<=1; v++) {
      differences_of_areaG[7*(u+1)+v+1]=(A[(l+u)*(m+2)+k+v]-A[(j+u)*(m+2)+i+v])*expf(-(u*u+v*v)/(2*patchSigma)); // The first A is the same for the whole block.
    }
  }
  Z[tid]=expf(-powf(normf(9, differences_of_areaG),2)/(2*filtSigmaSquared));
  my_w[tid]=Z[tid]*A[i+j*(m+2)];
  // Reduction algorithm
  __syncthreads();
  if (tid<128) {Z[tid]+=Z[tid+128]; my_w[tid]+=my_w[tid+128]; } __syncthreads();
  if (tid< 64) {Z[tid]+=Z[tid+ 64]; my_w[tid]+=my_w[tid+ 64]; } __syncthreads();
  if (tid< 32) {Z[tid]+=Z[tid+ 32]; my_w[tid]+=my_w[tid+ 32]; } __syncthreads();
  if (tid< 16) {Z[tid]+=Z[tid+ 16]; my_w[tid]+=my_w[tid+ 16]; } __syncthreads();
  if (tid<  8) {Z[tid]+=Z[tid+  8]; my_w[tid]+=my_w[tid+  8]; } __syncthreads();
  if (tid<  4) {Z[tid]+=Z[tid+  4]; my_w[tid]+=my_w[tid+  4]; } __syncthreads();
  if (tid<  2) {Z[tid]+=Z[tid+  2]; my_w[tid]+=my_w[tid+  2]; } __syncthreads();
  if (tid<  1) {
    // Pass the value to global variable
    ZpartialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=Z[0]+Z[1];
     partialSum16x16[gridDim.x*gridDim.y*blockIdx.z+gridDim.x*blockIdx.y+blockIdx.x]=my_w[0]+my_w[1];
  }
}

	.text
	.file	"nlm_step1.hip"
	.globl	_Z33__device_stub__calc_partial_sums7PKfPfS1_ffii # -- Begin function _Z33__device_stub__calc_partial_sums7PKfPfS1_ffii
	.type	_Z33__device_stub__calc_partial_sums7PKfPfS1_ffii,@function
_Z33__device_stub__calc_partial_sums7PKfPfS1_ffii: # @_Z33__device_stub__calc_partial_sums7PKfPfS1_ffii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	16(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	12(%rsp), %r10
	movl	%ecx, (%r10)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r9, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%rcx, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18calc_partial_sums7PKfPfS1_ffii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__calc_partial_sums7PKfPfS1_ffii, .Lfunc_end0-_Z33__device_stub__calc_partial_sums7PKfPfS1_ffii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__calc_partial_sums5PKfPfS1_ffii # -- Begin function _Z33__device_stub__calc_partial_sums5PKfPfS1_ffii
	.type	_Z33__device_stub__calc_partial_sums5PKfPfS1_ffii,@function
_Z33__device_stub__calc_partial_sums5PKfPfS1_ffii: # @_Z33__device_stub__calc_partial_sums5PKfPfS1_ffii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	16(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	12(%rsp), %r10
	movl	%ecx, (%r10)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r9, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%rcx, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18calc_partial_sums5PKfPfS1_ffii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z33__device_stub__calc_partial_sums5PKfPfS1_ffii, .Lfunc_end1-_Z33__device_stub__calc_partial_sums5PKfPfS1_ffii
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__calc_partial_sums3PKfPfS1_ffii # -- Begin function _Z33__device_stub__calc_partial_sums3PKfPfS1_ffii
	.type	_Z33__device_stub__calc_partial_sums3PKfPfS1_ffii,@function
_Z33__device_stub__calc_partial_sums3PKfPfS1_ffii: # @_Z33__device_stub__calc_partial_sums3PKfPfS1_ffii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	16(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	12(%rsp), %r10
	movl	%ecx, (%r10)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r9, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%rcx, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18calc_partial_sums3PKfPfS1_ffii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z33__device_stub__calc_partial_sums3PKfPfS1_ffii, .Lfunc_end2-_Z33__device_stub__calc_partial_sums3PKfPfS1_ffii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18calc_partial_sums7PKfPfS1_ffii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18calc_partial_sums5PKfPfS1_ffii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18calc_partial_sums3PKfPfS1_ffii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18calc_partial_sums7PKfPfS1_ffii,@object # @_Z18calc_partial_sums7PKfPfS1_ffii
	.section	.rodata,"a",@progbits
	.globl	_Z18calc_partial_sums7PKfPfS1_ffii
	.p2align	3, 0x0
_Z18calc_partial_sums7PKfPfS1_ffii:
	.quad	_Z33__device_stub__calc_partial_sums7PKfPfS1_ffii
	.size	_Z18calc_partial_sums7PKfPfS1_ffii, 8

	.type	_Z18calc_partial_sums5PKfPfS1_ffii,@object # @_Z18calc_partial_sums5PKfPfS1_ffii
	.globl	_Z18calc_partial_sums5PKfPfS1_ffii
	.p2align	3, 0x0
_Z18calc_partial_sums5PKfPfS1_ffii:
	.quad	_Z33__device_stub__calc_partial_sums5PKfPfS1_ffii
	.size	_Z18calc_partial_sums5PKfPfS1_ffii, 8

	.type	_Z18calc_partial_sums3PKfPfS1_ffii,@object # @_Z18calc_partial_sums3PKfPfS1_ffii
	.globl	_Z18calc_partial_sums3PKfPfS1_ffii
	.p2align	3, 0x0
_Z18calc_partial_sums3PKfPfS1_ffii:
	.quad	_Z33__device_stub__calc_partial_sums3PKfPfS1_ffii
	.size	_Z18calc_partial_sums3PKfPfS1_ffii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18calc_partial_sums7PKfPfS1_ffii"
	.size	.L__unnamed_1, 35

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z18calc_partial_sums5PKfPfS1_ffii"
	.size	.L__unnamed_2, 35

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z18calc_partial_sums3PKfPfS1_ffii"
	.size	.L__unnamed_3, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__calc_partial_sums7PKfPfS1_ffii
	.addrsig_sym _Z33__device_stub__calc_partial_sums5PKfPfS1_ffii
	.addrsig_sym _Z33__device_stub__calc_partial_sums3PKfPfS1_ffii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18calc_partial_sums7PKfPfS1_ffii
	.addrsig_sym _Z18calc_partial_sums5PKfPfS1_ffii
	.addrsig_sym _Z18calc_partial_sums3PKfPfS1_ffii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18calc_partial_sums7PKfPfS1_ffii ; -- Begin function _Z18calc_partial_sums7PKfPfS1_ffii
	.globl	_Z18calc_partial_sums7PKfPfS1_ffii
	.p2align	8
	.type	_Z18calc_partial_sums7PKfPfS1_ffii,@function
_Z18calc_partial_sums7PKfPfS1_ffii:     ; @_Z18calc_partial_sums7PKfPfS1_ffii
; %bb.0:
	s_clause 0x1
	s_load_b32 s18, s[0:1], 0x34
	s_load_b128 s[8:11], s[0:1], 0x18
	v_bfe_u32 v3, v0, 10, 10
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b64 s[16:17], s[0:1], 0x28
	v_and_b32_e32 v4, 0x3ff, v0
	v_mov_b32_e32 v6, 16
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s11, s18, 16
	s_add_i32 s12, s10, 6
	s_mul_i32 s19, s14, s11
	s_and_b32 s0, s18, 0xffff
	v_add_nc_u32_e32 v1, s19, v3
	s_mul_i32 s18, s13, s0
	v_add_f32_e64 v5, s8, s8
	s_mov_b32 s8, -3
	s_mov_b32 s0, s15
	v_mul_lo_u32 v1, v1, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v4, v1, s18
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v7, v6
	s_lshl_b64 s[10:11], s[0:1], 2
	s_mul_i32 s1, s8, s8
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_add_u32 s10, s4, s10
	s_addc_u32 s11, s5, s11
	s_mov_b32 s20, -3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v8, v[1:2], off
	s_mul_i32 s21, s20, s20
	s_add_i32 s20, s20, 1
	s_add_i32 s21, s1, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s21, 0, s21
	v_cvt_f32_i32_e32 v9, s21
	s_load_b32 s21, s[10:11], 0x0
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s20, 4
	v_div_scale_f32 v10, null, v5, v5, v9
	v_div_scale_f32 v13, vcc_lo, v9, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v10, v11, 1.0
	v_fmac_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v13, v11
	v_fma_f32 v14, -v10, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v11
	v_fma_f32 v10, -v10, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v10, v10, v11, v12
	v_div_fixup_f32 v9, v10, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fb8aa3b, v9
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	v_fma_f32 v11, 0x3fb8aa3b, v9, -v10
	v_rndne_f32_e32 v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v11, 0x32a5705f, v9 :: v_dual_sub_f32 v10, v10, v12
	v_add_f32_e32 v10, v10, v11
	v_cvt_i32_f32_e32 v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v10, v11
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v9, 0x7f800000, v10, vcc_lo
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v8, s21, v8
	v_mul_f32_e32 v8, v9, v8
	scratch_store_b32 v7, v8, off
	v_add_nc_u32_e32 v7, 4, v7
	s_cbranch_scc0 .LBB0_2
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v6, 28, v6
	v_add_nc_u32_e32 v0, s12, v0
	s_add_i32 s8, s8, 1
	s_add_i32 s0, s0, s12
	s_cmp_lg_u32 s8, 4
	s_cbranch_scc1 .LBB0_1
; %bb.4:                                ; %.lr.ph.i.preheader
	v_mov_b32_e32 v0, 0
	s_mov_b32 s0, 0
.LBB0_5:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s1, s0, 16
	s_add_i32 s0, s0, 4
	scratch_load_b32 v1, off, s1
	s_cmpk_lg_i32 s0, 0xc4
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, v1, v1
	s_cbranch_scc1 .LBB0_5
; %bb.6:                                ; %_ZL5normfiPKf.exit
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v2, -1, v1
	v_add_nc_u32_e32 v5, 1, v1
	v_fma_f32 v6, -v2, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v1, v0
	v_cmp_ge_f32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v2, s0
	v_cmp_lt_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, v5, s0
	s_mov_b32 s0, 0x3e76c4e1
	v_mul_f32_e32 v2, 0x37800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	v_cndmask_b32_e32 v2, v1, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v0, |v2|
	v_cmp_eq_f32_e64 s1, 0, v2
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, v1
	v_add_f32_e32 v1, 1.0, v0
	v_add_f32_e32 v6, -1.0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v1
	v_add_f32_e32 v8, -1.0, v1
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v0, v0, v8 :: v_dual_mul_f32 v7, v6, v5
	v_mul_f32_e32 v9, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, v7, v1, -v9
	v_fmac_f32_e32 v1, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v9, v1
	v_dual_sub_f32 v9, v0, v9 :: v_dual_sub_f32 v8, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v9, v1 :: v_dual_sub_f32 v6, v6, v8
	v_sub_f32_e32 v0, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v0
	v_add_f32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v5, v0
	v_add_f32_e32 v5, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v5, v7
	v_mul_f32_e32 v6, v5, v5
	v_sub_f32_e32 v7, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v0, v5, v5, -v6
	v_add_f32_e32 v1, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v5, v1
	v_add_f32_e32 v8, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v1, s0, v8, 0x3e91f4c4 :: v_dual_sub_f32 v6, v8, v6
	v_fmaak_f32 v1, v8, v1, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v6, v0, v6
	v_add3_u32 v0, v3, s19, 3
	v_mul_f32_e32 v9, v8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, s12
	v_fma_f32 v10, v8, v1, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v10, v6, v1 :: v_dual_add_nc_u32 v1, s18, v4
	v_add_f32_e32 v11, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v0, v1, v0, 3
	v_add_f32_e32 v13, 0x3f2aaaaa, v11
	v_dual_sub_f32 v9, v11, v9 :: v_dual_mul_f32 v12, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_sub_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, v8, v5, -v12
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v14, v8, v7
	v_add_f32_e32 v8, 0x31739010, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, s4, v0
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, v6, v5
	v_add_f32_e32 v10, 0xbf2aaaaa, v13
	v_ldexp_f32 v5, v5, 1
	v_ldexp_f32 v7, v7, 1
	v_sub_f32_e32 v9, v11, v10
	global_load_b32 v10, v[0:1], off
	v_add_f32_e32 v6, v8, v9
	v_add_f32_e32 v9, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v13, v6
	v_sub_f32_e32 v11, v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, v9, v8
	v_dual_sub_f32 v0, v13, v8 :: v_dual_sub_f32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v6, v0
	v_fma_f32 v6, v9, v8, -v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v9, v0
	v_frexp_exp_i32_f32_e32 v0, v2
	v_fmac_f32_e32 v6, v11, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
	v_add_f32_e32 v8, v1, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v0, v0
	v_sub_f32_e32 v1, v8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3f317218, v0
	v_sub_f32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, 0x3f317218, v0, -v11
	v_dual_add_f32 v9, v5, v8 :: v_dual_fmamk_f32 v0, v0, 0xb102e308, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v5, v9, v5
	v_add_f32_e32 v1, v7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v8, v5
	v_add_f32_e32 v1, v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v11, v0 :: v_dual_add_f32 v6, v9, v1
	v_sub_f32_e32 v11, v5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v5, v6 :: v_dual_sub_f32 v0, v0, v11
	v_sub_f32_e32 v8, v7, v5
	v_sub_f32_e32 v9, v6, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v8
	v_dual_sub_f32 v12, v7, v8 :: v_dual_sub_f32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v5, v12 :: v_dual_add_f32 v8, v0, v1
	v_dual_add_f32 v5, v6, v5 :: v_dual_sub_f32 v6, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v8, v5
	v_sub_f32_e32 v8, v8, v6
	v_sub_f32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v7, v5 :: v_dual_sub_f32 v0, v0, v8
	v_sub_f32_e32 v6, v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v1, v0
	v_sub_f32_e32 v1, v5, v6
	v_cndmask_b32_e64 v5, 2.0, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v1
	v_add_f32_e32 v1, v9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v1, v9
	v_dual_sub_f32 v0, v0, v6 :: v_dual_mul_f32 v7, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v1, v5, v1, -v7
	v_cmp_class_f32_e64 vcc_lo, v7, 0x204
	v_fmac_f32_e32 v1, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v7, v1
	v_cndmask_b32_e32 v6, v0, v7, vcc_lo
	v_sub_f32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
	v_sub_f32_e32 v0, v1, v0
	v_trunc_f32_e32 v1, v5
	v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v6, v8
	v_dual_cndmask_b32 v0, 0, v0 :: v_dual_mul_f32 v11, 0x3fb8aa3b, v9
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	v_cmp_nlt_f32_e64 s0, 0x42b17218, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v0, v8, v0
	v_fma_f32 v12, 0x3fb8aa3b, v9, -v11
	v_rndne_f32_e32 v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, 0x32a5705f, v9
	v_sub_f32_e32 v11, v11, v13
	v_cvt_i32_f32_e32 v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v11, v12
	v_exp_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, 0.5, v5 :: v_dual_cndmask_b32 v6, 0, v7
	v_trunc_f32_e32 v7, v11
	v_cmp_eq_f32_e32 vcc_lo, v1, v5
	v_cndmask_b32_e64 v5, 0x7f800000, 0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v1, 0x7f800000, v6, s0
	v_cmp_neq_f32_e64 s0, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v0, v1, v0, v1
	s_and_b32 vcc_lo, vcc_lo, s0
	v_cmp_class_f32_e64 s0, v2, 0x204
	v_cndmask_b32_e32 v6, 1.0, v2, vcc_lo
	v_cndmask_b32_e32 v7, 0, v2, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v1
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfi_b32 v1, 0x7fffffff, v5, v7
	s_or_b32 vcc_lo, s1, s0
	s_mov_b32 s0, exec_lo
	v_bfi_b32 v0, 0x7fffffff, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v2, v2
	v_add_f32_e64 v1, s9, s9
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v1, v1, -v0
	v_div_scale_f32 v7, vcc_lo, -v0, v1, -v0
	v_rcp_f32_e32 v5, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v2, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_mul_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v2, v6, v7
	v_fmac_f32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v6, v7
	v_div_fmas_f32 v2, v2, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v2, v1, -v0
	v_mul_f32_e32 v0, 0x3fb8aa3b, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, 0x3fb8aa3b, v1, -v0
	v_rndne_f32_e32 v5, v0
	v_fmac_f32_e32 v2, 0x32a5705f, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v5
	v_add_f32_e32 v0, v0, v2
	v_cvt_i32_f32_e32 v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v0, v2
	v_cndmask_b32_e32 v2, 0, v0, vcc_lo
	v_lshl_add_u32 v0, v3, 4, v4
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v1, 2, v0
	v_cndmask_b32_e32 v3, 0x7f800000, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, 0x400, v1
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, v3, v10
	ds_store_2addr_stride64_b32 v1, v3, v4 offset1:4
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB0_8
; %bb.7:
	ds_load_2addr_stride64_b32 v[3:4], v1 offset1:2
	ds_load_b32 v5, v1 offset:1536
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v4, v3 :: v_dual_add_f32 v4, v5, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB0_10
; %bb.9:
	ds_load_2addr_stride64_b32 v[3:4], v1 offset0:1 offset1:5
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_add_nc_u32_e32 v3, 0x80, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_add_nc_u32_e32 v3, 64, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_add_nc_u32_e32 v3, 32, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB0_18
; %bb.17:
	v_add_nc_u32_e32 v3, 16, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB0_18:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB0_20
; %bb.19:
	v_add_nc_u32_e32 v3, 8, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB0_20:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_mov_b32_e32 v4, 0
	s_mul_i32 s0, s17, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s16
	ds_load_2addr_stride64_b64 v[0:3], v4 offset1:2
	s_add_i32 s0, s0, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s2, s2, s0
	s_addc_u32 s3, s3, s1
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v0, v0, v1 :: v_dual_add_f32 v1, v2, v3
	s_clause 0x1
	global_store_b32 v4, v0, s[2:3]
	global_store_b32 v4, v1, s[0:1]
.LBB0_22:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18calc_partial_sums7PKfPfS1_ffii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 224
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18calc_partial_sums7PKfPfS1_ffii, .Lfunc_end0-_Z18calc_partial_sums7PKfPfS1_ffii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2808
; NumSgprs: 24
; NumVgprs: 15
; ScratchSize: 224
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z18calc_partial_sums5PKfPfS1_ffii ; -- Begin function _Z18calc_partial_sums5PKfPfS1_ffii
	.globl	_Z18calc_partial_sums5PKfPfS1_ffii
	.p2align	8
	.type	_Z18calc_partial_sums5PKfPfS1_ffii,@function
_Z18calc_partial_sums5PKfPfS1_ffii:     ; @_Z18calc_partial_sums5PKfPfS1_ffii
; %bb.0:
	s_clause 0x1
	s_load_b32 s18, s[0:1], 0x34
	s_load_b128 s[8:11], s[0:1], 0x18
	v_bfe_u32 v3, v0, 10, 10
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b64 s[16:17], s[0:1], 0x28
	v_and_b32_e32 v4, 0x3ff, v0
	v_mov_b32_e32 v6, 16
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s11, s18, 16
	s_add_i32 s12, s10, 4
	s_mul_i32 s19, s14, s11
	s_and_b32 s0, s18, 0xffff
	v_add_nc_u32_e32 v1, s19, v3
	s_mul_i32 s18, s13, s0
	v_add_f32_e64 v5, s8, s8
	s_mov_b32 s8, -2
	s_mov_b32 s0, s15
	v_mul_lo_u32 v1, v1, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v4, v1, s18
.LBB1_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_2 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v7, v6
	s_lshl_b64 s[10:11], s[0:1], 2
	s_mul_i32 s1, s8, s8
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_add_u32 s10, s4, s10
	s_addc_u32 s11, s5, s11
	s_mov_b32 s20, -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.LBB1_2:                                ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v8, v[1:2], off
	s_mul_i32 s21, s20, s20
	s_add_i32 s20, s20, 1
	s_add_i32 s21, s1, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s21, 0, s21
	v_cvt_f32_i32_e32 v9, s21
	s_load_b32 s21, s[10:11], 0x0
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s20, 3
	v_div_scale_f32 v10, null, v5, v5, v9
	v_div_scale_f32 v13, vcc_lo, v9, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v10, v11, 1.0
	v_fmac_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v13, v11
	v_fma_f32 v14, -v10, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v11
	v_fma_f32 v10, -v10, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v10, v10, v11, v12
	v_div_fixup_f32 v9, v10, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fb8aa3b, v9
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	v_fma_f32 v11, 0x3fb8aa3b, v9, -v10
	v_rndne_f32_e32 v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v11, 0x32a5705f, v9 :: v_dual_sub_f32 v10, v10, v12
	v_add_f32_e32 v10, v10, v11
	v_cvt_i32_f32_e32 v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v10, v11
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v9, 0x7f800000, v10, vcc_lo
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v8, s21, v8
	v_mul_f32_e32 v8, v9, v8
	scratch_store_b32 v7, v8, off
	v_add_nc_u32_e32 v7, 4, v7
	s_cbranch_scc0 .LBB1_2
; %bb.3:                                ;   in Loop: Header=BB1_1 Depth=1
	v_add_nc_u32_e32 v6, 28, v6
	v_add_nc_u32_e32 v0, s12, v0
	s_add_i32 s8, s8, 1
	s_add_i32 s0, s0, s12
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB1_1
; %bb.4:                                ; %.lr.ph.i.preheader
	v_mov_b32_e32 v0, 0
	s_mov_b32 s0, 0
.LBB1_5:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s1, s0, 16
	s_add_i32 s0, s0, 4
	scratch_load_b32 v1, off, s1
	s_cmpk_lg_i32 s0, 0x64
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, v1, v1
	s_cbranch_scc1 .LBB1_5
; %bb.6:                                ; %_ZL5normfiPKf.exit
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v2, -1, v1
	v_add_nc_u32_e32 v5, 1, v1
	v_fma_f32 v6, -v2, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v1, v0
	v_cmp_ge_f32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v2, s0
	v_cmp_lt_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, v5, s0
	s_mov_b32 s0, 0x3e76c4e1
	v_mul_f32_e32 v2, 0x37800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	v_cndmask_b32_e32 v2, v1, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v0, |v2|
	v_cmp_eq_f32_e64 s1, 0, v2
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, v1
	v_add_f32_e32 v1, 1.0, v0
	v_add_f32_e32 v6, -1.0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v1
	v_add_f32_e32 v8, -1.0, v1
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v0, v0, v8 :: v_dual_mul_f32 v7, v6, v5
	v_mul_f32_e32 v9, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, v7, v1, -v9
	v_fmac_f32_e32 v1, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v9, v1
	v_dual_sub_f32 v9, v0, v9 :: v_dual_sub_f32 v8, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v9, v1 :: v_dual_sub_f32 v6, v6, v8
	v_sub_f32_e32 v0, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v0
	v_add_f32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v5, v0
	v_add_f32_e32 v5, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v5, v7
	v_mul_f32_e32 v6, v5, v5
	v_sub_f32_e32 v7, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v0, v5, v5, -v6
	v_add_f32_e32 v1, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v5, v1
	v_add_f32_e32 v8, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v1, s0, v8, 0x3e91f4c4 :: v_dual_sub_f32 v6, v8, v6
	v_fmaak_f32 v1, v8, v1, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v6, v0, v6
	v_add3_u32 v0, v3, s19, 2
	v_mul_f32_e32 v9, v8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, s12
	v_fma_f32 v10, v8, v1, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v10, v6, v1 :: v_dual_add_nc_u32 v1, s18, v4
	v_add_f32_e32 v11, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v0, v1, v0, 2
	v_add_f32_e32 v13, 0x3f2aaaaa, v11
	v_dual_sub_f32 v9, v11, v9 :: v_dual_mul_f32 v12, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_sub_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, v8, v5, -v12
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v14, v8, v7
	v_add_f32_e32 v8, 0x31739010, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, s4, v0
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, v6, v5
	v_add_f32_e32 v10, 0xbf2aaaaa, v13
	v_ldexp_f32 v5, v5, 1
	v_ldexp_f32 v7, v7, 1
	v_sub_f32_e32 v9, v11, v10
	global_load_b32 v10, v[0:1], off
	v_add_f32_e32 v6, v8, v9
	v_add_f32_e32 v9, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v13, v6
	v_sub_f32_e32 v11, v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, v9, v8
	v_dual_sub_f32 v0, v13, v8 :: v_dual_sub_f32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v6, v0
	v_fma_f32 v6, v9, v8, -v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, v9, v0
	v_frexp_exp_i32_f32_e32 v0, v2
	v_fmac_f32_e32 v6, v11, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
	v_add_f32_e32 v8, v1, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v0, v0
	v_sub_f32_e32 v1, v8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3f317218, v0
	v_sub_f32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, 0x3f317218, v0, -v11
	v_dual_add_f32 v9, v5, v8 :: v_dual_fmamk_f32 v0, v0, 0xb102e308, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v5, v9, v5
	v_add_f32_e32 v1, v7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v8, v5
	v_add_f32_e32 v1, v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v11, v0 :: v_dual_add_f32 v6, v9, v1
	v_sub_f32_e32 v11, v5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v5, v6 :: v_dual_sub_f32 v0, v0, v11
	v_sub_f32_e32 v8, v7, v5
	v_sub_f32_e32 v9, v6, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v8
	v_dual_sub_f32 v12, v7, v8 :: v_dual_sub_f32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v5, v12 :: v_dual_add_f32 v8, v0, v1
	v_dual_add_f32 v5, v6, v5 :: v_dual_sub_f32 v6, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v8, v5
	v_sub_f32_e32 v8, v8, v6
	v_sub_f32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v7, v5 :: v_dual_sub_f32 v0, v0, v8
	v_sub_f32_e32 v6, v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v1, v0
	v_sub_f32_e32 v1, v5, v6
	v_cndmask_b32_e64 v5, 2.0, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v1
	v_add_f32_e32 v1, v9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v1, v9
	v_dual_sub_f32 v0, v0, v6 :: v_dual_mul_f32 v7, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v1, v5, v1, -v7
	v_cmp_class_f32_e64 vcc_lo, v7, 0x204
	v_fmac_f32_e32 v1, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v7, v1
	v_cndmask_b32_e32 v6, v0, v7, vcc_lo
	v_sub_f32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
	v_sub_f32_e32 v0, v1, v0
	v_trunc_f32_e32 v1, v5
	v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v6, v8
	v_dual_cndmask_b32 v0, 0, v0 :: v_dual_mul_f32 v11, 0x3fb8aa3b, v9
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	v_cmp_nlt_f32_e64 s0, 0x42b17218, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v0, v8, v0
	v_fma_f32 v12, 0x3fb8aa3b, v9, -v11
	v_rndne_f32_e32 v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, 0x32a5705f, v9
	v_sub_f32_e32 v11, v11, v13
	v_cvt_i32_f32_e32 v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v11, v12
	v_exp_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, 0.5, v5 :: v_dual_cndmask_b32 v6, 0, v7
	v_trunc_f32_e32 v7, v11
	v_cmp_eq_f32_e32 vcc_lo, v1, v5
	v_cndmask_b32_e64 v5, 0x7f800000, 0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v1, 0x7f800000, v6, s0
	v_cmp_neq_f32_e64 s0, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v0, v1, v0, v1
	s_and_b32 vcc_lo, vcc_lo, s0
	v_cmp_class_f32_e64 s0, v2, 0x204
	v_cndmask_b32_e32 v6, 1.0, v2, vcc_lo
	v_cndmask_b32_e32 v7, 0, v2, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v1
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfi_b32 v1, 0x7fffffff, v5, v7
	s_or_b32 vcc_lo, s1, s0
	s_mov_b32 s0, exec_lo
	v_bfi_b32 v0, 0x7fffffff, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v2, v2
	v_add_f32_e64 v1, s9, s9
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v1, v1, -v0
	v_div_scale_f32 v7, vcc_lo, -v0, v1, -v0
	v_rcp_f32_e32 v5, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v2, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_mul_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v2, v6, v7
	v_fmac_f32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v6, v7
	v_div_fmas_f32 v2, v2, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v2, v1, -v0
	v_mul_f32_e32 v0, 0x3fb8aa3b, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, 0x3fb8aa3b, v1, -v0
	v_rndne_f32_e32 v5, v0
	v_fmac_f32_e32 v2, 0x32a5705f, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v5
	v_add_f32_e32 v0, v0, v2
	v_cvt_i32_f32_e32 v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v0, v2
	v_cndmask_b32_e32 v2, 0, v0, vcc_lo
	v_lshl_add_u32 v0, v3, 4, v4
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v1, 2, v0
	v_cndmask_b32_e32 v3, 0x7f800000, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, 0x400, v1
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, v3, v10
	ds_store_2addr_stride64_b32 v1, v3, v4 offset1:4
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB1_8
; %bb.7:
	ds_load_2addr_stride64_b32 v[3:4], v1 offset1:2
	ds_load_b32 v5, v1 offset:1536
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v4, v3 :: v_dual_add_f32 v4, v5, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB1_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB1_10
; %bb.9:
	ds_load_2addr_stride64_b32 v[3:4], v1 offset0:1 offset1:5
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB1_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB1_12
; %bb.11:
	v_add_nc_u32_e32 v3, 0x80, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB1_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB1_14
; %bb.13:
	v_add_nc_u32_e32 v3, 64, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB1_14:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB1_16
; %bb.15:
	v_add_nc_u32_e32 v3, 32, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB1_16:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB1_18
; %bb.17:
	v_add_nc_u32_e32 v3, 16, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB1_18:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB1_20
; %bb.19:
	v_add_nc_u32_e32 v3, 8, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB1_20:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_22
; %bb.21:
	v_mov_b32_e32 v4, 0
	s_mul_i32 s0, s17, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s16
	ds_load_2addr_stride64_b64 v[0:3], v4 offset1:2
	s_add_i32 s0, s0, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s2, s2, s0
	s_addc_u32 s3, s3, s1
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v0, v0, v1 :: v_dual_add_f32 v1, v2, v3
	s_clause 0x1
	global_store_b32 v4, v0, s[2:3]
	global_store_b32 v4, v1, s[0:1]
.LBB1_22:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18calc_partial_sums5PKfPfS1_ffii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 128
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z18calc_partial_sums5PKfPfS1_ffii, .Lfunc_end1-_Z18calc_partial_sums5PKfPfS1_ffii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2808
; NumSgprs: 24
; NumVgprs: 15
; ScratchSize: 128
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z18calc_partial_sums3PKfPfS1_ffii ; -- Begin function _Z18calc_partial_sums3PKfPfS1_ffii
	.globl	_Z18calc_partial_sums3PKfPfS1_ffii
	.p2align	8
	.type	_Z18calc_partial_sums3PKfPfS1_ffii,@function
_Z18calc_partial_sums3PKfPfS1_ffii:     ; @_Z18calc_partial_sums3PKfPfS1_ffii
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x34
	s_load_b128 s[8:11], s[0:1], 0x18
	v_bfe_u32 v3, v0, 10, 10
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b64 s[16:17], s[0:1], 0x28
	v_dual_mov_b32 v7, 16 :: v_dual_and_b32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s11, s12, 16
	s_add_i32 s10, s10, 2
	s_mul_i32 s11, s14, s11
	s_and_b32 s0, s12, 0xffff
	v_add_nc_u32_e32 v5, s11, v3
	s_mul_i32 s11, s13, s0
	v_add_f32_e64 v6, s8, s8
	s_mov_b32 s8, -1
	s_mov_b32 s0, s15
	v_mul_lo_u32 v1, v5, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v4, v1, s11
.LBB2_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_2 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v8, v7
	s_lshl_b64 s[18:19], s[0:1], 2
	s_mul_i32 s1, s8, s8
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_add_u32 s18, s4, s18
	s_addc_u32 s19, s5, s19
	s_mov_b32 s12, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.LBB2_2:                                ;   Parent Loop BB2_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v9, v[1:2], off
	s_mul_i32 s20, s12, s12
	s_add_i32 s12, s12, 1
	s_add_i32 s20, s1, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s20, 0, s20
	v_cvt_f32_i32_e32 v10, s20
	s_load_b32 s20, s[18:19], 0x0
	s_add_u32 s18, s18, 4
	s_addc_u32 s19, s19, 0
	s_cmp_eq_u32 s12, 2
	v_div_scale_f32 v11, null, v6, v6, v10
	v_div_scale_f32 v14, vcc_lo, v10, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v11, v12, 1.0
	v_fmac_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v14, v12
	v_fma_f32 v15, -v11, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v15, v12
	v_fma_f32 v11, -v11, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v11, v11, v12, v13
	v_div_fixup_f32 v10, v11, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3fb8aa3b, v10
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
	v_fma_f32 v12, 0x3fb8aa3b, v10, -v11
	v_rndne_f32_e32 v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, 0x32a5705f, v10 :: v_dual_sub_f32 v11, v11, v13
	v_add_f32_e32 v11, v11, v12
	v_cvt_i32_f32_e32 v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v11, v11, v12
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, 0x7f800000, v11, vcc_lo
	v_add_co_u32 v1, vcc_lo, v1, 4
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v9, s20, v9
	v_mul_f32_e32 v9, v10, v9
	scratch_store_b32 v8, v9, off
	v_add_nc_u32_e32 v8, 4, v8
	s_cbranch_scc0 .LBB2_2
; %bb.3:                                ;   in Loop: Header=BB2_1 Depth=1
	v_add_nc_u32_e32 v7, 28, v7
	v_add_nc_u32_e32 v0, s10, v0
	s_add_i32 s8, s8, 1
	s_add_i32 s0, s0, s10
	s_cmp_lg_u32 s8, 2
	s_cbranch_scc1 .LBB2_1
; %bb.4:                                ; %.lr.ph.i.preheader
	v_mov_b32_e32 v0, 0
	s_mov_b32 s0, 0
.LBB2_5:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s1, s0, 16
	s_add_i32 s0, s0, 4
	scratch_load_b32 v1, off, s1
	s_cmp_lg_u32 s0, 36
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v0, v1, v1
	s_cbranch_scc1 .LBB2_5
; %bb.6:                                ; %_ZL5normfiPKf.exit
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v2, -1, v1
	v_add_nc_u32_e32 v6, 1, v1
	v_fma_f32 v7, -v2, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v6, v1, v0
	v_cmp_ge_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v2, s0
	v_cmp_lt_f32_e64 s0, 0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v1, v6, s0
	s_mov_b32 s0, 0x3e76c4e1
	v_mul_f32_e32 v2, 0x37800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	v_cndmask_b32_e32 v2, v1, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e64 v0, |v2|
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	v_ldexp_f32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, 1.0, v0
	v_add_f32_e32 v7, -1.0, v0
	v_add_f32_e32 v9, -1.0, v1
	v_rcp_f32_e32 v6, v1
	v_cmp_eq_f32_e64 s1, 0, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, v7, v6
	v_sub_f32_e32 v0, v0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v1, v8
	v_fma_f32 v1, v8, v1, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, v8, v0
	v_add_f32_e32 v0, v10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v7, v0
	v_dual_sub_f32 v7, v7, v9 :: v_dual_sub_f32 v10, v0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v0, v7, v0 :: v_dual_sub_f32 v1, v10, v1
	v_add_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v9, v0
	v_mul_f32_e32 v0, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v8, v0
	v_sub_f32_e32 v1, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v7, v6, v6 :: v_dual_sub_f32 v8, v0, v1
	v_fma_f32 v0, v6, v6, -v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v8, v8
	v_fmac_f32_e32 v0, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v7, v0
	v_fmaak_f32 v1, s0, v9, 0x3e91f4c4
	v_sub_f32_e32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v1, v9, v1, 0x3ecccdef
	v_dual_sub_f32 v7, v0, v7 :: v_dual_mul_f32 v10, v9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v9, v1, -v10
	v_fmac_f32_e32 v11, v7, v1
	v_mad_u64_u32 v[0:1], null, s10, v5, s[10:11]
	v_add_nc_u32_e32 v1, s11, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v10, v11
	v_add3_u32 v0, v1, v0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v5, v10
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v11, v10
	v_mul_f32_e32 v12, v6, v9
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v14, v9, v6, -v12
	v_add_f32_e32 v13, 0x3f2aaaaa, v5
	v_add_co_u32 v0, s0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v14, v9, v8 :: v_dual_add_f32 v11, 0xbf2aaaaa, v13
	v_add_f32_e32 v9, 0x31739010, v10
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	v_dual_fmac_f32 v14, v7, v6 :: v_dual_sub_f32 v5, v5, v11
	v_ldexp_f32 v6, v6, 1
	global_load_b32 v10, v[0:1], off
	v_ldexp_f32 v8, v8, 1
	v_add_f32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v13, v5
	v_dual_add_f32 v9, v12, v14 :: v_dual_sub_f32 v0, v13, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v1, v9, v7
	v_sub_f32_e32 v11, v9, v12
	v_add_f32_e32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v5, v9, v7, -v1
	v_sub_f32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v5, v9, v0
	v_frexp_exp_i32_f32_e32 v0, v2
	v_fmac_f32_e32 v5, v11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
	v_add_f32_e32 v7, v1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v0, v0
	v_add_f32_e32 v9, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v7, v1 :: v_dual_sub_f32 v6, v9, v6
	v_dual_sub_f32 v1, v5, v1 :: v_dual_sub_f32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v8, v1
	v_add_f32_e32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, 0x3f317218, v0 :: v_dual_add_f32 v6, v9, v1
	v_fma_f32 v5, 0x3f317218, v0, -v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v6, v9 :: v_dual_fmamk_f32 v0, v0, 0xb102e308, v5
	v_sub_f32_e32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v11, v0
	v_add_f32_e32 v7, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v5, v11 :: v_dual_sub_f32 v8, v7, v5
	v_sub_f32_e32 v0, v0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v7, v8
	v_sub_f32_e32 v6, v6, v8
	v_dual_add_f32 v8, v0, v1 :: v_dual_sub_f32 v5, v5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v6, v5 :: v_dual_sub_f32 v6, v8, v0
	v_add_f32_e32 v5, v8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v8, v6
	v_sub_f32_e32 v1, v1, v6
	v_dual_add_f32 v9, v7, v5 :: v_dual_sub_f32 v0, v0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v9, v7
	v_add_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v5, v6
	v_cndmask_b32_e64 v5, 2.0, 1.0, vcc_lo
	v_add_f32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v9, v0
	v_sub_f32_e32 v6, v1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v7, v5, v1 :: v_dual_sub_f32 v0, v0, v6
	v_fma_f32 v1, v5, v1, -v7
	v_cmp_class_f32_e64 vcc_lo, v7, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, v5, v0
	v_add_f32_e32 v0, v7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v0, v7, vcc_lo
	v_sub_f32_e32 v0, v0, v7
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v0, v1, v0
	v_trunc_f32_e32 v1, v5
	v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
	v_sub_f32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v0, 0, v0 :: v_dual_mul_f32 v11, 0x3fb8aa3b, v9
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	v_cmp_nlt_f32_e64 s0, 0x42b17218, v9
	v_add_f32_e32 v0, v8, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3fb8aa3b, v9, -v11
	v_rndne_f32_e32 v13, v11
	v_fmac_f32_e32 v12, 0x32a5705f, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v11, v13
	v_cvt_i32_f32_e32 v7, v13
	v_add_f32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v11, v7
	v_dual_mul_f32 v11, 0.5, v5 :: v_dual_cndmask_b32 v6, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v7, v11
	v_cmp_eq_f32_e32 vcc_lo, v1, v5
	v_cndmask_b32_e64 v5, 0x7f800000, 0, s1
	v_cndmask_b32_e64 v1, 0x7f800000, v6, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_neq_f32_e64 s0, v7, v11
	v_fma_f32 v0, v1, v0, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 vcc_lo, vcc_lo, s0
	v_cmp_class_f32_e64 s0, v2, 0x204
	v_cndmask_b32_e32 v6, 1.0, v2, vcc_lo
	v_cndmask_b32_e32 v7, 0, v2, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v1
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfi_b32 v1, 0x7fffffff, v5, v7
	s_or_b32 vcc_lo, s1, s0
	s_mov_b32 s0, exec_lo
	v_bfi_b32 v0, 0x7fffffff, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v2, v2
	v_add_f32_e64 v1, s9, s9
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v1, v1, -v0
	v_div_scale_f32 v7, vcc_lo, -v0, v1, -v0
	v_rcp_f32_e32 v5, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v2, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_mul_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v2, v6, v7
	v_fmac_f32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v6, v7
	v_div_fmas_f32 v2, v2, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v2, v1, -v0
	v_mul_f32_e32 v0, 0x3fb8aa3b, v1
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, 0x3fb8aa3b, v1, -v0
	v_rndne_f32_e32 v5, v0
	v_fmac_f32_e32 v2, 0x32a5705f, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v5
	v_add_f32_e32 v0, v0, v2
	v_cvt_i32_f32_e32 v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v0, v2
	v_cndmask_b32_e32 v2, 0, v0, vcc_lo
	v_lshl_add_u32 v0, v3, 4, v4
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v1, 2, v0
	v_cndmask_b32_e32 v3, 0x7f800000, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, 0x400, v1
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, v3, v10
	ds_store_2addr_stride64_b32 v1, v3, v4 offset1:4
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v0
	s_cbranch_execz .LBB2_8
; %bb.7:
	ds_load_2addr_stride64_b32 v[3:4], v1 offset1:2
	ds_load_b32 v5, v1 offset:1536
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v4, v3 :: v_dual_add_f32 v4, v5, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB2_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB2_10
; %bb.9:
	ds_load_2addr_stride64_b32 v[3:4], v1 offset0:1 offset1:5
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB2_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB2_12
; %bb.11:
	v_add_nc_u32_e32 v3, 0x80, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB2_12:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB2_14
; %bb.13:
	v_add_nc_u32_e32 v3, 64, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB2_14:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB2_16
; %bb.15:
	v_add_nc_u32_e32 v3, 32, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB2_16:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB2_18
; %bb.17:
	v_add_nc_u32_e32 v3, 16, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB2_18:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB2_20
; %bb.19:
	v_add_nc_u32_e32 v3, 8, v1
	ds_load_2addr_stride64_b32 v[3:4], v3 offset1:4
	ds_load_b32 v5, v1
	ds_load_b32 v6, v2
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	ds_store_b32 v1, v3
	ds_store_b32 v2, v4
.LBB2_20:
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_22
; %bb.21:
	v_mov_b32_e32 v4, 0
	s_mul_i32 s0, s17, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_mul_i32 s0, s0, s16
	ds_load_2addr_stride64_b64 v[0:3], v4 offset1:2
	s_add_i32 s0, s0, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s2, s2, s0
	s_addc_u32 s3, s3, s1
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v0, v0, v1 :: v_dual_add_f32 v1, v2, v3
	s_clause 0x1
	global_store_b32 v4, v0, s[2:3]
	global_store_b32 v4, v1, s[0:1]
.LBB2_22:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18calc_partial_sums3PKfPfS1_ffii
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 64
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z18calc_partial_sums3PKfPfS1_ffii, .Lfunc_end2-_Z18calc_partial_sums3PKfPfS1_ffii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2792
; NumSgprs: 23
; NumVgprs: 16
; ScratchSize: 64
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18calc_partial_sums7PKfPfS1_ffii
    .private_segment_fixed_size: 224
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z18calc_partial_sums7PKfPfS1_ffii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
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        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18calc_partial_sums5PKfPfS1_ffii
    .private_segment_fixed_size: 128
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z18calc_partial_sums5PKfPfS1_ffii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18calc_partial_sums3PKfPfS1_ffii
    .private_segment_fixed_size: 64
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z18calc_partial_sums3PKfPfS1_ffii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
