#include "stdio.h"
#include "stdlib.h"
#include "string.h"
#include "math.h"
#include "time.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#define DX 1
#define DY 1
#define DT 1
#define ERRMAX 1E-5
#define NX 201
#define NY 201
#define NTMAX 50000
#define NTHREAD 512
#define NBLOCK 256
#define Q 9
#define RE 1000.
#define RHO0 1.
#define U0 0.1
#define OUTPUTFILENAME "output.dat"

struct attribute{
	double f[Q];
	double fnew[Q];
	double g[Q];
	double u[2];
	double u0[2];
	double rho;
	double vor;
};

__constant__ double dev_CS2[1], dev_NU[1], dev_TAO[1], dev_w[Q];
__constant__ int dev_e[Q * 2];
const double w[Q] = { 4. / 9, 1. / 9, 1. / 9, 1. / 9, 1. / 9, 1. / 36,\
	1. / 36, 1. / 36, 1. / 36 };
int C = DX / DT;
int e[Q * 2] = { 0, 0, C, 0, 0, C, -C, 0, 0, -C, C, C, -C, C, -C, -C, C, -C };
double *CS2, *NU, *TAO;
attribute *domain;

cudaError_t LBM();
int Ord2(int x, int y, int nx);
double Cfeq(double u[2], double rho, int k);
void Init();
void OutWatch(int t, double err, double rhoav);
void Outp();
__device__ int d_Ord2(int x, int y, int nx);
__device__ void d_Ord2r(int id, int *x, int *y, int nx);
__device__ double d_Cfeq(double u[2], double rho, int k);
__global__ void Collision(attribute *domain);
__global__ void PreStreaming(attribute *domain);
__global__ void Streaming(attribute *domain);
__global__ void Physics(attribute *domain);
__global__ void MovingBoundary(attribute *domain);
__global__ void StaticBoundary(attribute *domain);
__global__ void Error(attribute *domain, double *err);
__global__ void Watch(attribute *domain, double *rhoav);
__global__ void Cvor(attribute *domain);

int main()
{
	Init();
	cudaError_t cudaStatus = LBM();
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "Cuda LBM Failed!");
		return 1;
	}
	Outp();

	free(CS2);
	free(NU);
	free(TAO);
	free(domain);

	return 0;
}

cudaError_t LBM(){
	attribute *dev_domain;
	cudaError_t cudaStatus;
	clock_t start, finish;
	double *err = (double*)malloc(sizeof(double));
	double *rhoav = (double*)malloc(sizeof(double));
	double *dev_err, *dev_rhoav;

	// Choose which GPU to run on, change this on a multi-GPU system.
	cudaStatus = cudaSetDevice(0);
	if (cudaStatus != cudaSuccess) goto Error;

	cudaStatus = cudaMalloc((void**)&dev_err, sizeof(double));
	if (cudaStatus != cudaSuccess) goto Error;
	cudaStatus = cudaMalloc((void**)&dev_rhoav, sizeof(double));
	if (cudaStatus != cudaSuccess) goto Error;
	cudaStatus = cudaMalloc((void**)&dev_domain, NX * NY * sizeof(attribute));
	if (cudaStatus != cudaSuccess) goto Error;
	cudaStatus = cudaMemcpy(dev_domain, domain, NX * NY * sizeof(attribute),\
		cudaMemcpyHostToDevice);
	if (cudaStatus != cudaSuccess) goto Error;

	cudaStatus = cudaMemcpyToSymbol(dev_w, w, Q * sizeof(double));
	if (cudaStatus != cudaSuccess) goto Error;
	cudaStatus = cudaMemcpyToSymbol(dev_e, e, Q * 2 * sizeof(int));
	if (cudaStatus != cudaSuccess) goto Error;
	cudaStatus = cudaMemcpyToSymbol(dev_CS2, CS2, sizeof(double));
	if (cudaStatus != cudaSuccess) goto Error;
	cudaStatus = cudaMemcpyToSymbol(dev_NU, NU, sizeof(double));
	if (cudaStatus != cudaSuccess) goto Error;
	cudaStatus = cudaMemcpyToSymbol(dev_TAO, TAO, sizeof(double));
	if (cudaStatus != cudaSuccess) goto Error;

	start = clock();
	for (int t = 0;; t++){
		Collision <<<NBLOCK, NTHREAD >>>(dev_domain);
		PreStreaming <<<NBLOCK, NTHREAD >>>(dev_domain);
		Streaming <<<NBLOCK, NTHREAD >>>(dev_domain);
		Physics <<<NBLOCK, NTHREAD >>>(dev_domain);
		MovingBoundary <<<NBLOCK, NTHREAD >>>(dev_domain);
		StaticBoundary <<<NBLOCK, NTHREAD >>>(dev_domain);
		Error <<<1, NTHREAD >>>(dev_domain, dev_err);

		cudaStatus = cudaMemcpy(err, dev_err, sizeof(double),\
			cudaMemcpyDeviceToHost);
		if (cudaStatus != cudaSuccess) goto Error;
		
		if (t % 100 == 0){
			Watch <<<1, NTHREAD >>>(dev_domain, dev_rhoav);
			cudaStatus = cudaMemcpy(rhoav, dev_rhoav, sizeof(double),\
				cudaMemcpyDeviceToHost);
			if (cudaStatus != cudaSuccess) goto Error;
			OutWatch(t, *err, *rhoav);
		}
		
		if ((*err < ERRMAX) || (t > NTMAX)) break;
	}
	Cvor <<<NBLOCK, NTHREAD >>>(dev_domain);
	finish = clock();
	printf("Time Take : %7.2lfs\n", (double)(finish - start) / CLOCKS_PER_SEC);

	cudaStatus = cudaMemcpy(domain, dev_domain, NX * NY * sizeof(attribute),\
		cudaMemcpyDeviceToHost);
	if (cudaStatus != cudaSuccess) goto Error;

Error:
	free(err);
	free(rhoav);
	cudaFree(dev_err);
	cudaFree(dev_rhoav);
	cudaFree(dev_domain);

	return cudaStatus;
}

int Ord2(int x, int y, int nx){
	return y * nx + x;
}

double Cfeq(double u[2], double rho, int k){
	double v1 = e[k * 2] * u[0] + e[k * 2 + 1] * u[1];
	double v2 = u[0] * u[0] + u[1] * u[1];
	return (rho * w[k] * (1.0 + v1 / (*CS2) + v1 * v1 / (2. * (*CS2)\
		* (*CS2)) - v2 / (2. * (*CS2))));
}

void Init(){
	CS2 = (double*)malloc(sizeof(double));
	NU = (double*)malloc(sizeof(double));
	TAO = (double*)malloc(sizeof(double));
	*CS2 = C * C / 3.;
	*NU = U0 * (NX - 1) * DX / RE;
	*TAO = *NU / DT / *CS2 + 0.5;
	domain = (attribute*)malloc(NX * NY * sizeof(attribute));
	memset(domain, 0, NX * NY * sizeof(attribute));
	for (int i = 0; i < NX; i++)
		for (int j = 0; j < NY; j++){
			domain[Ord2(i, j, NX)].rho = RHO0;
			domain[Ord2(i, j, NX)].u[0] = (j == NY - 1) ? U0 : 0.;
			domain[Ord2(i, j, NX)].u[1] = 0.;
			for (int k = 0; k < Q; k++)
				domain[Ord2(i, j, NX)].f[k] = Cfeq(domain[Ord2(i, j, NX)].u, \
				domain[Ord2(i, j, NX)].rho, k);
		}
	return;
}

void OutWatch(int t, double err, double rhoav){
	printf("Time Step %d, ", t);
	printf("Error = %lf, ", err);
	printf("Average Density = %lf\n", rhoav);
}

void Outp(){
	FILE *fp = fopen(OUTPUTFILENAME, "w");
	fprintf(fp, "Title=\"LBM Lid Driven Cavity\"\n");
	fprintf(fp, "VARIABLES=\"X\",\"Y\",\"U\",\"V\",\"P\",\"OMG\"\n");
	fprintf(fp, "ZONE T=\"BOX\",I=%d,J=%d,F=POINT\n", NX, NY);
	for (int j = 0; j < NY; j++)
		for (int i = 0; i < NX; i++){
			fprintf(fp, "%lf ", (double)i / (NX - 1) / DX);
			fprintf(fp, "%lf ", (double)j / (NY - 1) / DY);
			fprintf(fp, "%lf ", domain[Ord2(i, j, NX)].u[0]);
			fprintf(fp, "%lf ", domain[Ord2(i, j, NX)].u[1]);
			fprintf(fp, "%lf ", domain[Ord2(i, j, NX)].rho * (*CS2));
			fprintf(fp, "%lf\n", domain[Ord2(i, j, NX)].vor);
		}
	fclose(fp);
	return;
}

__device__ int d_Ord2(int x, int y, int nx){
	return y * nx + x;
}

__device__ void d_Ord2r(int id, int *x, int *y, int nx){
	*y = id / nx;
	*x = id % nx;
	return;
}

__device__ double d_Cfeq(double u[2], double rho, int k){
	double v1 = dev_e[k * 2] * u[0] + dev_e[k * 2 + 1] * u[1];
	double v2 = u[0] * u[0] + u[1] * u[1];
	return (rho * dev_w[k] * (1.0 + v1 / (*dev_CS2) + v1 * v1 / (2.\
		* (*dev_CS2) * (*dev_CS2)) - v2 / (2. * (*dev_CS2))));
}

__global__ void Collision(attribute *domain){
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		for (int k = 0; k < Q; k++){
			double feq = d_Cfeq(domain[tid].u, domain[tid].rho, k);
			domain[tid].fnew[k] = domain[tid].f[k] - (domain[tid].f[k]\
				- feq) / (*dev_TAO);
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void PreStreaming(attribute *domain){
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		for (int k = 0; k < Q; k++)
			domain[tid].g[k] = domain[tid].fnew[k];
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void Streaming(attribute *domain){
	int x, y;
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		for (int k = 0; k < Q; k++){
			int xn = (x + dev_e[k * 2] + NX) % NX;
			int yn = (y + dev_e[k * 2 + 1] + NY) % NY;
			domain[d_Ord2(xn, yn, NX)].fnew[k] = domain[tid].g[k];
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void Physics(attribute *domain){
	int x, y;
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		if ((x > 0) && (y > 0) && (x < NX - 1) && (y < NY - 1)){
			domain[tid].u0[0] = domain[tid].u[0];
			domain[tid].u0[1] = domain[tid].u[1];
			domain[tid].rho = 0.;
			domain[tid].u[0] = 0.;
			domain[tid].u[1] = 0.;
			for (int k = 0; k < Q; k++){
				domain[tid].f[k] = domain[tid].fnew[k];
				domain[tid].rho += domain[tid].f[k];
				domain[tid].u[0] += dev_e[k * 2] * domain[tid].f[k];
				domain[tid].u[1] += dev_e[k * 2 + 1] * domain[tid].f[k];
			}
			domain[tid].u[0] /= domain[tid].rho;
			domain[tid].u[1] /= domain[tid].rho;
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void MovingBoundary(attribute *domain){
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX){
		domain[d_Ord2(tid, NY - 1, NX)].rho = domain[d_Ord2(tid, NY - 2, NX)].rho;
		domain[d_Ord2(tid, NY - 1, NX)].u[0] = U0;
		for (int k = 0; k < Q; k++){
			domain[d_Ord2(tid, NY - 1, NX)].f[k] = d_Cfeq(domain[d_Ord2(tid, \
				NY - 1, NX)].u, domain[d_Ord2(tid, NY - 1, NX)].rho, k)\
				+ domain[d_Ord2(tid, NY - 2, NX)].f[k] - d_Cfeq(domain[d_Ord2(tid, \
				NY - 2, NX)].u, domain[d_Ord2(tid, NY - 2, NX)].rho, k);
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void StaticBoundary(attribute *domain){
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	int tid0 = tid;
	while (tid < NX){
		domain[d_Ord2(tid, 0, NX)].rho = domain[d_Ord2(tid, 1, NX)].rho;
		for (int k = 0; k < Q; k++){
			domain[d_Ord2(tid, 0, NX)].f[k] = d_Cfeq(domain[d_Ord2(tid, \
				0, NX)].u, domain[d_Ord2(tid, 0, NX)].rho, k)\
				+ domain[d_Ord2(tid, 1, NX)].f[k] - d_Cfeq(domain[d_Ord2(tid, \
				1, NX)].u, domain[d_Ord2(tid, 1, NX)].rho, k);
		}
		tid += blockDim.x * gridDim.x;
	}
	tid = tid0;
	while (tid < NY - 1){
		if (tid > 0){
			domain[d_Ord2(0, tid, NX)].rho = domain[d_Ord2(1, tid, NX)].rho;
			domain[d_Ord2(NX - 1, tid, NX)].rho = domain[d_Ord2(NX - 2,\
				tid, NX)].rho;
			for (int k = 0; k < Q; k++){
				domain[d_Ord2(0, tid, NX)].f[k] = d_Cfeq(domain[d_Ord2(0,\
					tid, NX)].u, domain[d_Ord2(0, tid, NX)].rho, k)\
					+ domain[d_Ord2(1, tid, NX)].f[k] - d_Cfeq(domain[d_Ord2(1,\
					tid, NX)].u, domain[d_Ord2(1, tid, NX)].rho, k);
				domain[d_Ord2(NX - 1, tid, NX)].f[k] = d_Cfeq(domain[d_Ord2(NX - 1,\
					tid, NX)].u, domain[d_Ord2(NX - 1, tid, NX)].rho, k)\
					+ domain[d_Ord2(NX - 2, tid, NX)].f[k] - d_Cfeq(domain[d_Ord2(NX - 2,\
					tid, NX)].u, domain[d_Ord2(NX - 2, tid, NX)].rho, k);
			}
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}	

__global__ void Error(attribute *domain, double *err){
	__shared__ double cache[NTHREAD][2];
	int x, y;
	int tid = threadIdx.x;
	cache[threadIdx.x][0] = 0.;
	cache[threadIdx.x][1] = 0.;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		if ((x > 0) && (y > 0) && (x < NX - 1) && (y < NY - 1)){
			cache[threadIdx.x][0] += (domain[tid].u[0] - domain[tid].u0[0])\
				* (domain[tid].u[0] - domain[tid].u0[0]) + (domain[tid].u[1]\
				- domain[tid].u0[1]) * (domain[tid].u[1] - domain[tid].u0[1]);
			cache[threadIdx.x][1] += domain[tid].u[0] * domain[tid].u[0]\
				+ domain[tid].u[1] * domain[tid].u[1];
		}
		tid += blockDim.x;
	}
	__syncthreads();
	int i = blockDim.x / 2;
	while (i > 0){
		if (threadIdx.x < i){
			cache[threadIdx.x][0] += cache[threadIdx.x + i][0];
			cache[threadIdx.x][1] += cache[threadIdx.x + i][1];
		}
		__syncthreads();
		i /= 2;
	}
	if (threadIdx.x == 0)
		*err = sqrt(cache[threadIdx.x][0] / (cache[threadIdx.x][1] + 1.E-10));
	return;
}

__global__ void Watch(attribute *domain, double *rhoav){
	__shared__ int cachen[NTHREAD];
	__shared__ double cache[NTHREAD];
	int x, y;
	int tid = threadIdx.x;
	cachen[threadIdx.x] = 0;
	cache[threadIdx.x] = 0.;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		if ((x > 0) && (y > 0) && (x < NX - 1) && (y < NY - 1)){
			cachen[threadIdx.x]++;
			cache[threadIdx.x] += domain[tid].rho;
		}
		tid += blockDim.x;
	}
	__syncthreads();
	int i = blockDim.x / 2;
	while (i > 0){
		if (threadIdx.x < i){
			cache[threadIdx.x] += cache[threadIdx.x + i];
			cachen[threadIdx.x] += cachen[threadIdx.x + i];
		}
		__syncthreads();
		i /= 2;
	}
	if (threadIdx.x == 0)
		*rhoav = cache[threadIdx.x] / ((double)cachen[threadIdx.x] + 1.E-10);
	return;
}

__global__ void Cvor(attribute *domain){
	int x, y;
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		if ((x > 0) && (y > 0) && (x < NX - 1) && (y < NY - 1)){
			domain[tid].vor = (domain[d_Ord2(x + 1, y, NX)].u[1]\
				- domain[d_Ord2(x - 1, y, NX)].u[1]) / (2 * DX);
			domain[tid].vor -= (domain[d_Ord2(x, y + 1, NX)].u[0]\
				- domain[d_Ord2(x, y - 1, NX)].u[0]) / (2 * DY);
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

	.file	"tmpxft_0031da69_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2039:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4Ord2iii
	.type	_Z4Ord2iii, @function
_Z4Ord2iii:
.LFB2029:
	.cfi_startproc
	endbr64
	imull	%edx, %esi
	leal	(%rsi,%rdi), %eax
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z4Ord2iii, .-_Z4Ord2iii
	.globl	_Z4CfeqPddi
	.type	_Z4CfeqPddi, @function
_Z4CfeqPddi:
.LFB2030:
	.cfi_startproc
	endbr64
	leal	(%rsi,%rsi), %eax
	leaq	e(%rip), %rcx
	movaps	%xmm0, %xmm5
	movslq	%esi, %rsi
	leal	1(%rax), %edx
	cltq
	movsd	(%rdi), %xmm2
	movsd	8(%rdi), %xmm3
	movslq	%edx, %rdx
	cvtsi2sdl	(%rcx,%rax,4), %xmm0
	movq	CS2(%rip), %rax
	cvtsi2sdl	(%rcx,%rdx,4), %xmm1
	movsd	(%rax), %xmm4
	leaq	_ZL1w(%rip), %rax
	mulsd	(%rax,%rsi,8), %xmm5
	mulsd	%xmm2, %xmm0
	movaps	%xmm4, %xmm6
	movaps	%xmm4, %xmm7
	mulsd	%xmm3, %xmm1
	addsd	%xmm4, %xmm6
	mulsd	%xmm3, %xmm3
	mulsd	%xmm2, %xmm2
	mulsd	%xmm6, %xmm7
	addsd	%xmm0, %xmm1
	addsd	%xmm3, %xmm2
	movaps	%xmm1, %xmm0
	mulsd	%xmm1, %xmm0
	divsd	%xmm4, %xmm1
	divsd	%xmm7, %xmm0
	addsd	.LC0(%rip), %xmm1
	divsd	%xmm6, %xmm2
	addsd	%xmm1, %xmm0
	subsd	%xmm2, %xmm0
	mulsd	%xmm5, %xmm0
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z4CfeqPddi, .-_Z4CfeqPddi
	.globl	_Z4Initv
	.type	_Z4Initv, @function
_Z4Initv:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$8, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	pushq	%rdx
	.cfi_def_cfa_offset 32
	call	malloc@PLT
	movl	$8, %edi
	movq	%rax, %rbp
	movq	%rax, CS2(%rip)
	call	malloc@PLT
	movl	$8, %edi
	movq	%rax, %rbx
	movq	%rax, NU(%rip)
	call	malloc@PLT
	movl	C(%rip), %edx
	movl	$10665864, %edi
	movsd	.LC4(%rip), %xmm0
	movq	%rax, TAO(%rip)
	imull	%edx, %edx
	movsd	%xmm0, (%rbx)
	xorl	%ebx, %ebx
	cvtsi2sdl	%edx, %xmm1
	divsd	.LC3(%rip), %xmm1
	divsd	%xmm1, %xmm0
	movsd	%xmm1, 0(%rbp)
	addsd	.LC5(%rip), %xmm0
	movsd	%xmm0, (%rax)
	call	malloc@PLT
	movl	$2666466, %ecx
	movsd	.LC0(%rip), %xmm8
	movq	%rax, %r8
	movq	%rax, domain(%rip)
	xorl	%eax, %eax
	movq	%r8, %rdi
	rep stosl
.L5:
	movq	%r8, %r9
	xorl	%r11d, %r11d
.L8:
	movsd	%xmm8, 248(%r9)
	xorps	%xmm0, %xmm0
	cmpl	$200, %r11d
	jne	.L6
	movsd	.LC1(%rip), %xmm0
.L6:
	movq	$0x000000000, 224(%r9)
	xorl	%r10d, %r10d
	leaq	216(%r9), %rdi
	movsd	%xmm0, 216(%r9)
.L7:
	movl	%r10d, %esi
	movaps	%xmm8, %xmm0
	call	_Z4CfeqPddi
	movsd	%xmm0, (%r9,%r10,8)
	incq	%r10
	cmpq	$9, %r10
	jne	.L7
	incl	%r11d
	addq	$53064, %r9
	cmpl	$201, %r11d
	jne	.L8
	incl	%ebx
	addq	$264, %r8
	cmpl	$201, %ebx
	jne	.L5
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z4Initv, .-_Z4Initv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC6:
	.string	"Time Step %d, "
.LC7:
	.string	"Error = %lf, "
.LC8:
	.string	"Average Density = %lf\n"
	.text
	.globl	_Z8OutWatchidd
	.type	_Z8OutWatchidd, @function
_Z8OutWatchidd:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%edi, %edx
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movq	%xmm1, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	movsd	%xmm0, 8(%rsp)
	call	__printf_chk@PLT
	movsd	8(%rsp), %xmm0
	leaq	.LC7(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %xmm0
	movb	$1, %al
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2032:
	.size	_Z8OutWatchidd, .-_Z8OutWatchidd
	.section	.rodata.str1.1
.LC9:
	.string	"w"
.LC10:
	.string	"output.dat"
.LC11:
	.string	"Title=\"LBM Lid Driven Cavity\"\n"
.LC12:
	.string	"VARIABLES=\"X\",\"Y\",\"U\",\"V\",\"P\",\"OMG\"\n"
.LC13:
	.string	"ZONE T=\"BOX\",I=%d,J=%d,F=POINT\n"
.LC15:
	.string	"%lf "
.LC16:
	.string	"%lf\n"
	.text
	.globl	_Z4Outpv
	.type	_Z4Outpv, @function
_Z4Outpv:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC9(%rip), %rsi
	leaq	.LC10(%rip), %rdi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	fopen@PLT
	leaq	.LC11(%rip), %rdx
	movl	$2, %esi
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movq	8(%rsp), %rdi
	leaq	.LC12(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movq	8(%rsp), %rdi
	xorl	%eax, %eax
	movl	$201, %r8d
	movl	$201, %ecx
	leaq	.LC13(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
.L18:
	imulq	$53064, %rbx, %r14
	movl	%ebx, %r15d
	xorl	%r12d, %r12d
.L19:
	leaq	.LC15(%rip), %r13
	movq	8(%rsp), %rdi
	movl	$2, %esi
	movb	$1, %al
	movq	%r13, %rdx
	cvtsi2sdl	%r12d, %xmm0
	divsd	.LC14(%rip), %xmm0
	call	__fprintf_chk@PLT
	movq	8(%rsp), %rdi
	movq	%r13, %rdx
	movb	$1, %al
	imulq	$264, %r12, %rbp
	movl	$2, %esi
	incq	%r12
	cvtsi2sdl	%r15d, %xmm0
	divsd	.LC14(%rip), %xmm0
	call	__fprintf_chk@PLT
	movq	domain(%rip), %rax
	movq	8(%rsp), %rdi
	movq	%r13, %rdx
	addq	%r14, %rbp
	movl	$2, %esi
	movsd	216(%rax,%rbp), %xmm0
	movb	$1, %al
	call	__fprintf_chk@PLT
	movq	domain(%rip), %rax
	movq	8(%rsp), %rdi
	movq	%r13, %rdx
	movl	$2, %esi
	movsd	224(%rax,%rbp), %xmm0
	movb	$1, %al
	call	__fprintf_chk@PLT
	movq	domain(%rip), %rax
	movq	8(%rsp), %rdi
	movq	%r13, %rdx
	movl	$2, %esi
	movsd	248(%rax,%rbp), %xmm0
	movq	CS2(%rip), %rax
	mulsd	(%rax), %xmm0
	movb	$1, %al
	call	__fprintf_chk@PLT
	movq	8(%rsp), %rdi
	movl	$2, %esi
	movq	domain(%rip), %rax
	leaq	.LC16(%rip), %rdx
	movsd	256(%rax,%rbp), %xmm0
	movb	$1, %al
	call	__fprintf_chk@PLT
	cmpq	$201, %r12
	jne	.L19
	incq	%rbx
	cmpq	$201, %rbx
	jne	.L18
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE2033:
	.size	_Z4Outpv, .-_Z4Outpv
	.globl	_Z6d_Ord2iii
	.type	_Z6d_Ord2iii, @function
_Z6d_Ord2iii:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2034:
	.size	_Z6d_Ord2iii, .-_Z6d_Ord2iii
	.globl	_Z7d_Ord2riPiS_i
	.type	_Z7d_Ord2riPiS_i, @function
_Z7d_Ord2riPiS_i:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2035:
	.size	_Z7d_Ord2riPiS_i, .-_Z7d_Ord2riPiS_i
	.globl	_Z6d_CfeqPddi
	.type	_Z6d_CfeqPddi, @function
_Z6d_CfeqPddi:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2036:
	.size	_Z6d_CfeqPddi, .-_Z6d_CfeqPddi
	.globl	_Z37__device_stub__Z9CollisionP9attributeP9attribute
	.type	_Z37__device_stub__Z9CollisionP9attributeP9attribute, @function
_Z37__device_stub__Z9CollisionP9attributeP9attribute:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z9CollisionP9attribute(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L29:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z37__device_stub__Z9CollisionP9attributeP9attribute, .-_Z37__device_stub__Z9CollisionP9attributeP9attribute
	.globl	_Z9CollisionP9attribute
	.type	_Z9CollisionP9attribute, @function
_Z9CollisionP9attribute:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z9CollisionP9attributeP9attribute
	.cfi_endproc
.LFE2062:
	.size	_Z9CollisionP9attribute, .-_Z9CollisionP9attribute
	.globl	_Z41__device_stub__Z12PreStreamingP9attributeP9attribute
	.type	_Z41__device_stub__Z12PreStreamingP9attributeP9attribute, @function
_Z41__device_stub__Z12PreStreamingP9attributeP9attribute:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z12PreStreamingP9attribute(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L34:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z41__device_stub__Z12PreStreamingP9attributeP9attribute, .-_Z41__device_stub__Z12PreStreamingP9attributeP9attribute
	.globl	_Z12PreStreamingP9attribute
	.type	_Z12PreStreamingP9attribute, @function
_Z12PreStreamingP9attribute:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z12PreStreamingP9attributeP9attribute
	.cfi_endproc
.LFE2064:
	.size	_Z12PreStreamingP9attribute, .-_Z12PreStreamingP9attribute
	.globl	_Z37__device_stub__Z9StreamingP9attributeP9attribute
	.type	_Z37__device_stub__Z9StreamingP9attributeP9attribute, @function
_Z37__device_stub__Z9StreamingP9attributeP9attribute:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z9StreamingP9attribute(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L39:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z37__device_stub__Z9StreamingP9attributeP9attribute, .-_Z37__device_stub__Z9StreamingP9attributeP9attribute
	.globl	_Z9StreamingP9attribute
	.type	_Z9StreamingP9attribute, @function
_Z9StreamingP9attribute:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z9StreamingP9attributeP9attribute
	.cfi_endproc
.LFE2066:
	.size	_Z9StreamingP9attribute, .-_Z9StreamingP9attribute
	.globl	_Z35__device_stub__Z7PhysicsP9attributeP9attribute
	.type	_Z35__device_stub__Z7PhysicsP9attributeP9attribute, @function
_Z35__device_stub__Z7PhysicsP9attributeP9attribute:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z7PhysicsP9attribute(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L44:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z35__device_stub__Z7PhysicsP9attributeP9attribute, .-_Z35__device_stub__Z7PhysicsP9attributeP9attribute
	.globl	_Z7PhysicsP9attribute
	.type	_Z7PhysicsP9attribute, @function
_Z7PhysicsP9attribute:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z7PhysicsP9attributeP9attribute
	.cfi_endproc
.LFE2068:
	.size	_Z7PhysicsP9attribute, .-_Z7PhysicsP9attribute
	.globl	_Z43__device_stub__Z14MovingBoundaryP9attributeP9attribute
	.type	_Z43__device_stub__Z14MovingBoundaryP9attributeP9attribute, @function
_Z43__device_stub__Z14MovingBoundaryP9attributeP9attribute:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z14MovingBoundaryP9attribute(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L49:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z43__device_stub__Z14MovingBoundaryP9attributeP9attribute, .-_Z43__device_stub__Z14MovingBoundaryP9attributeP9attribute
	.globl	_Z14MovingBoundaryP9attribute
	.type	_Z14MovingBoundaryP9attribute, @function
_Z14MovingBoundaryP9attribute:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z14MovingBoundaryP9attributeP9attribute
	.cfi_endproc
.LFE2070:
	.size	_Z14MovingBoundaryP9attribute, .-_Z14MovingBoundaryP9attribute
	.globl	_Z43__device_stub__Z14StaticBoundaryP9attributeP9attribute
	.type	_Z43__device_stub__Z14StaticBoundaryP9attributeP9attribute, @function
_Z43__device_stub__Z14StaticBoundaryP9attributeP9attribute:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z14StaticBoundaryP9attribute(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L54:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z43__device_stub__Z14StaticBoundaryP9attributeP9attribute, .-_Z43__device_stub__Z14StaticBoundaryP9attributeP9attribute
	.globl	_Z14StaticBoundaryP9attribute
	.type	_Z14StaticBoundaryP9attribute, @function
_Z14StaticBoundaryP9attribute:
.LFB2072:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z14StaticBoundaryP9attributeP9attribute
	.cfi_endproc
.LFE2072:
	.size	_Z14StaticBoundaryP9attribute, .-_Z14StaticBoundaryP9attribute
	.globl	_Z35__device_stub__Z5ErrorP9attributePdP9attributePd
	.type	_Z35__device_stub__Z5ErrorP9attributePdP9attributePd, @function
_Z35__device_stub__Z5ErrorP9attributePdP9attributePd:
.LFB2073:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5ErrorP9attributePd(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L59:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_Z35__device_stub__Z5ErrorP9attributePdP9attributePd, .-_Z35__device_stub__Z5ErrorP9attributePdP9attributePd
	.globl	_Z5ErrorP9attributePd
	.type	_Z5ErrorP9attributePd, @function
_Z5ErrorP9attributePd:
.LFB2074:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z5ErrorP9attributePdP9attributePd
	.cfi_endproc
.LFE2074:
	.size	_Z5ErrorP9attributePd, .-_Z5ErrorP9attributePd
	.globl	_Z35__device_stub__Z5WatchP9attributePdP9attributePd
	.type	_Z35__device_stub__Z5WatchP9attributePdP9attributePd, @function
_Z35__device_stub__Z5WatchP9attributePdP9attributePd:
.LFB2075:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5WatchP9attributePd(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L64:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_Z35__device_stub__Z5WatchP9attributePdP9attributePd, .-_Z35__device_stub__Z5WatchP9attributePdP9attributePd
	.globl	_Z5WatchP9attributePd
	.type	_Z5WatchP9attributePd, @function
_Z5WatchP9attributePd:
.LFB2076:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z5WatchP9attributePdP9attributePd
	.cfi_endproc
.LFE2076:
	.size	_Z5WatchP9attributePd, .-_Z5WatchP9attributePd
	.globl	_Z32__device_stub__Z4CvorP9attributeP9attribute
	.type	_Z32__device_stub__Z4CvorP9attributeP9attribute, @function
_Z32__device_stub__Z4CvorP9attributeP9attribute:
.LFB2077:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z4CvorP9attribute(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L69:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L71
	call	__stack_chk_fail@PLT
.L71:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2077:
	.size	_Z32__device_stub__Z4CvorP9attributeP9attribute, .-_Z32__device_stub__Z4CvorP9attributeP9attribute
	.globl	_Z4CvorP9attribute
	.type	_Z4CvorP9attribute, @function
_Z4CvorP9attribute:
.LFB2078:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z4CvorP9attributeP9attribute
	.cfi_endproc
.LFE2078:
	.size	_Z4CvorP9attribute, .-_Z4CvorP9attribute
	.section	.rodata.str1.1
.LC19:
	.string	"Time Take : %7.2lfs\n"
	.text
	.globl	_Z3LBMv
	.type	_Z3LBMv, @function
_Z3LBMv:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$8, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$8, %edi
	movq	%rax, %r12
	call	malloc@PLT
	xorl	%edi, %edi
	movq	%rax, (%rsp)
	call	cudaSetDevice@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	leaq	32(%rsp), %rdi
	movl	$8, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	leaq	40(%rsp), %rdi
	movl	$8, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	leaq	24(%rsp), %rdi
	movl	$10665864, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	movq	24(%rsp), %rdi
	movl	$10665864, %edx
	movl	$1, %ecx
	movq	domain(%rip), %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	movl	$72, %edx
	movl	$1, %r8d
	xorl	%ecx, %ecx
	leaq	_ZL1w(%rip), %rsi
	leaq	_ZL5dev_w(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	movl	$72, %edx
	movl	$1, %r8d
	xorl	%ecx, %ecx
	leaq	e(%rip), %rsi
	leaq	_ZL5dev_e(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	movq	CS2(%rip), %rsi
	movl	$8, %edx
	movl	$1, %r8d
	xorl	%ecx, %ecx
	leaq	_ZL7dev_CS2(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	movq	NU(%rip), %rsi
	movl	$8, %edx
	movl	$1, %r8d
	xorl	%ecx, %ecx
	leaq	_ZL6dev_NU(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	movq	TAO(%rip), %rsi
	movl	$8, %edx
	movl	$1, %r8d
	xorl	%ecx, %ecx
	leaq	_ZL7dev_TAO(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	call	clock@PLT
	movl	$8388609, %ebx
	movl	$16777217, %ebp
	xorl	%r13d, %r13d
	salq	$9, %rbx
	movq	%rax, %r15
	salq	$8, %rbp
	movabsq	$4294967297, %r14
.L86:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rbp, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L76
	movq	24(%rsp), %rdi
	call	_Z37__device_stub__Z9CollisionP9attributeP9attribute
.L76:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rbp, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L77
	movq	24(%rsp), %rdi
	call	_Z41__device_stub__Z12PreStreamingP9attributeP9attribute
.L77:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rbp, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L78
	movq	24(%rsp), %rdi
	call	_Z37__device_stub__Z9StreamingP9attributeP9attribute
.L78:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rbp, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L79
	movq	24(%rsp), %rdi
	call	_Z35__device_stub__Z7PhysicsP9attributeP9attribute
.L79:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rbp, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L80
	movq	24(%rsp), %rdi
	call	_Z43__device_stub__Z14MovingBoundaryP9attributeP9attribute
.L80:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rbp, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L81
	movq	24(%rsp), %rdi
	call	_Z43__device_stub__Z14StaticBoundaryP9attributeP9attribute
.L81:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%r14, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L82
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z35__device_stub__Z5ErrorP9attributePdP9attributePd
.L82:
	movq	32(%rsp), %rsi
	movl	$8, %edx
	movl	$2, %ecx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	movl	%r13d, %eax
	movl	$100, %ecx
	cltd
	idivl	%ecx
	testl	%edx, %edx
	jne	.L83
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%r14, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L84
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z35__device_stub__Z5WatchP9attributePdP9attributePd
.L84:
	movq	40(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$8, %edx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	jne	.L75
	movq	(%rsp), %rax
	movsd	(%r12), %xmm0
	movl	%r13d, %edi
	movsd	(%rax), %xmm1
	call	_Z8OutWatchidd
.L83:
	movsd	.LC17(%rip), %xmm2
	comisd	(%r12), %xmm2
	ja	.L85
	cmpl	$50001, %r13d
	je	.L85
	incl	%r13d
	jmp	.L86
.L85:
	movl	$8388609, %edx
	movl	$16777217, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	salq	$8, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L87
	movq	24(%rsp), %rdi
	call	_Z32__device_stub__Z4CvorP9attributeP9attribute
.L87:
	call	clock@PLT
	leaq	.LC19(%rip), %rsi
	movl	$2, %edi
	subq	%r15, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC18(%rip), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rsi
	movl	$10665864, %edx
	movq	domain(%rip), %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movl	%eax, %edx
.L75:
	movq	%r12, %rdi
	movl	%edx, 12(%rsp)
	call	free@PLT
	movq	(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movl	12(%rsp), %edx
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L88
	call	__stack_chk_fail@PLT
.L88:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	movl	%edx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z3LBMv, .-_Z3LBMv
	.section	.rodata.str1.1
.LC20:
	.string	"Cuda LBM Failed!"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rcx
	.cfi_def_cfa_offset 16
	call	_Z4Initv
	call	_Z3LBMv
	testl	%eax, %eax
	je	.L94
	movq	stderr(%rip), %rdi
	leaq	.LC20(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %eax
	jmp	.L93
.L94:
	call	_Z4Outpv
	movq	CS2(%rip), %rdi
	call	free@PLT
	movq	NU(%rip), %rdi
	call	free@PLT
	movq	TAO(%rip), %rdi
	call	free@PLT
	movq	domain(%rip), %rdi
	call	free@PLT
	xorl	%eax, %eax
.L93:
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC21:
	.string	"_Z4CvorP9attribute"
.LC22:
	.string	"_Z5WatchP9attributePd"
.LC23:
	.string	"_Z5ErrorP9attributePd"
.LC24:
	.string	"_Z14StaticBoundaryP9attribute"
.LC25:
	.string	"_Z14MovingBoundaryP9attribute"
.LC26:
	.string	"_Z7PhysicsP9attribute"
.LC27:
	.string	"_Z9StreamingP9attribute"
.LC28:
	.string	"_Z12PreStreamingP9attribute"
.LC29:
	.string	"_Z9CollisionP9attribute"
.LC30:
	.string	"dev_CS2"
.LC31:
	.string	"dev_NU"
.LC32:
	.string	"dev_TAO"
.LC33:
	.string	"dev_w"
.LC34:
	.string	"dev_e"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2080:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z4CvorP9attribute(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z5WatchP9attributePd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z5ErrorP9attributePd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14StaticBoundaryP9attribute(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14MovingBoundaryP9attribute(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7PhysicsP9attribute(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC27(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9StreamingP9attribute(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC28(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12PreStreamingP9attribute(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC29(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z9CollisionP9attribute(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC30(%rip), %rdx
	movl	$8, %r9d
	leaq	_ZL7dev_CS2(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC31(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dev_NU(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC32(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL7dev_TAO(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC33(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL5dev_w(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC34(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL5dev_e(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2080:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text.startup
	.type	_GLOBAL__sub_I_C, @function
_GLOBAL__sub_I_C:
.LFB2200:
	.cfi_startproc
	endbr64
	movl	C(%rip), %eax
	movl	%eax, %edx
	movl	%eax, 8+e(%rip)
	negl	%edx
	movl	%eax, 20+e(%rip)
	movl	%edx, 24+e(%rip)
	movl	%edx, 36+e(%rip)
	movl	%eax, 40+e(%rip)
	movl	%eax, 44+e(%rip)
	movl	%edx, 48+e(%rip)
	movl	%eax, 52+e(%rip)
	movl	%edx, 56+e(%rip)
	movl	%edx, 60+e(%rip)
	movl	%eax, 64+e(%rip)
	movl	%edx, 68+e(%rip)
	ret
	.cfi_endproc
.LFE2200:
	.size	_GLOBAL__sub_I_C, .-_GLOBAL__sub_I_C
	.section	.init_array
	.align 8
	.quad	_GLOBAL__sub_I_C
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	domain
	.bss
	.align 8
	.type	domain, @object
	.size	domain, 8
domain:
	.zero	8
	.globl	TAO
	.align 8
	.type	TAO, @object
	.size	TAO, 8
TAO:
	.zero	8
	.globl	NU
	.align 8
	.type	NU, @object
	.size	NU, 8
NU:
	.zero	8
	.globl	CS2
	.align 8
	.type	CS2, @object
	.size	CS2, 8
CS2:
	.zero	8
	.globl	e
	.align 32
	.type	e, @object
	.size	e, 72
e:
	.zero	72
	.globl	C
	.data
	.align 4
	.type	C, @object
	.size	C, 4
C:
	.long	1
	.section	.rodata
	.align 32
	.type	_ZL1w, @object
	.size	_ZL1w, 72
_ZL1w:
	.long	477218588
	.long	1071411655
	.long	477218588
	.long	1069314503
	.long	477218588
	.long	1069314503
	.long	477218588
	.long	1069314503
	.long	477218588
	.long	1069314503
	.long	477218588
	.long	1067217351
	.long	477218588
	.long	1067217351
	.long	477218588
	.long	1067217351
	.long	477218588
	.long	1067217351
	.local	_ZL5dev_e
	.comm	_ZL5dev_e,72,32
	.local	_ZL5dev_w
	.comm	_ZL5dev_w,72,32
	.local	_ZL7dev_TAO
	.comm	_ZL7dev_TAO,8,8
	.local	_ZL6dev_NU
	.comm	_ZL6dev_NU,8,8
	.local	_ZL7dev_CS2
	.comm	_ZL7dev_CS2,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1072693248
	.align 8
.LC1:
	.long	-1717986918
	.long	1069128089
	.align 8
.LC3:
	.long	0
	.long	1074266112
	.align 8
.LC4:
	.long	1202590843
	.long	1066695393
	.align 8
.LC5:
	.long	0
	.long	1071644672
	.align 8
.LC14:
	.long	0
	.long	1080623104
	.align 8
.LC17:
	.long	-1998362383
	.long	1055193269
	.align 8
.LC18:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "stdio.h"
#include "stdlib.h"
#include "string.h"
#include "math.h"
#include "time.h"
#include "hip/hip_runtime.h"


#define DX 1
#define DY 1
#define DT 1
#define ERRMAX 1E-5
#define NX 201
#define NY 201
#define NTMAX 50000
#define NTHREAD 512
#define NBLOCK 256
#define Q 9
#define RE 1000.
#define RHO0 1.
#define U0 0.1
#define OUTPUTFILENAME "output.dat"

struct attribute{
	double f[Q];
	double fnew[Q];
	double g[Q];
	double u[2];
	double u0[2];
	double rho;
	double vor;
};

__constant__ double dev_CS2[1], dev_NU[1], dev_TAO[1], dev_w[Q];
__constant__ int dev_e[Q * 2];
const double w[Q] = { 4. / 9, 1. / 9, 1. / 9, 1. / 9, 1. / 9, 1. / 36,\
	1. / 36, 1. / 36, 1. / 36 };
int C = DX / DT;
int e[Q * 2] = { 0, 0, C, 0, 0, C, -C, 0, 0, -C, C, C, -C, C, -C, -C, C, -C };
double *CS2, *NU, *TAO;
attribute *domain;

hipError_t LBM();
int Ord2(int x, int y, int nx);
double Cfeq(double u[2], double rho, int k);
void Init();
void OutWatch(int t, double err, double rhoav);
void Outp();
__device__ int d_Ord2(int x, int y, int nx);
__device__ void d_Ord2r(int id, int *x, int *y, int nx);
__device__ double d_Cfeq(double u[2], double rho, int k);
__global__ void Collision(attribute *domain);
__global__ void PreStreaming(attribute *domain);
__global__ void Streaming(attribute *domain);
__global__ void Physics(attribute *domain);
__global__ void MovingBoundary(attribute *domain);
__global__ void StaticBoundary(attribute *domain);
__global__ void Error(attribute *domain, double *err);
__global__ void Watch(attribute *domain, double *rhoav);
__global__ void Cvor(attribute *domain);

int main()
{
	Init();
	hipError_t cudaStatus = LBM();
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "Cuda LBM Failed!");
		return 1;
	}
	Outp();

	free(CS2);
	free(NU);
	free(TAO);
	free(domain);

	return 0;
}

hipError_t LBM(){
	attribute *dev_domain;
	hipError_t cudaStatus;
	clock_t start, finish;
	double *err = (double*)malloc(sizeof(double));
	double *rhoav = (double*)malloc(sizeof(double));
	double *dev_err, *dev_rhoav;

	// Choose which GPU to run on, change this on a multi-GPU system.
	cudaStatus = hipSetDevice(0);
	if (cudaStatus != hipSuccess) goto Error;

	cudaStatus = hipMalloc((void**)&dev_err, sizeof(double));
	if (cudaStatus != hipSuccess) goto Error;
	cudaStatus = hipMalloc((void**)&dev_rhoav, sizeof(double));
	if (cudaStatus != hipSuccess) goto Error;
	cudaStatus = hipMalloc((void**)&dev_domain, NX * NY * sizeof(attribute));
	if (cudaStatus != hipSuccess) goto Error;
	cudaStatus = hipMemcpy(dev_domain, domain, NX * NY * sizeof(attribute),\
		hipMemcpyHostToDevice);
	if (cudaStatus != hipSuccess) goto Error;

	cudaStatus = hipMemcpyToSymbol(HIP_SYMBOL(dev_w), w, Q * sizeof(double));
	if (cudaStatus != hipSuccess) goto Error;
	cudaStatus = hipMemcpyToSymbol(HIP_SYMBOL(dev_e), e, Q * 2 * sizeof(int));
	if (cudaStatus != hipSuccess) goto Error;
	cudaStatus = hipMemcpyToSymbol(HIP_SYMBOL(dev_CS2), CS2, sizeof(double));
	if (cudaStatus != hipSuccess) goto Error;
	cudaStatus = hipMemcpyToSymbol(HIP_SYMBOL(dev_NU), NU, sizeof(double));
	if (cudaStatus != hipSuccess) goto Error;
	cudaStatus = hipMemcpyToSymbol(HIP_SYMBOL(dev_TAO), TAO, sizeof(double));
	if (cudaStatus != hipSuccess) goto Error;

	start = clock();
	for (int t = 0;; t++){
		Collision <<<NBLOCK, NTHREAD >>>(dev_domain);
		PreStreaming <<<NBLOCK, NTHREAD >>>(dev_domain);
		Streaming <<<NBLOCK, NTHREAD >>>(dev_domain);
		Physics <<<NBLOCK, NTHREAD >>>(dev_domain);
		MovingBoundary <<<NBLOCK, NTHREAD >>>(dev_domain);
		StaticBoundary <<<NBLOCK, NTHREAD >>>(dev_domain);
		Error <<<1, NTHREAD >>>(dev_domain, dev_err);

		cudaStatus = hipMemcpy(err, dev_err, sizeof(double),\
			hipMemcpyDeviceToHost);
		if (cudaStatus != hipSuccess) goto Error;
		
		if (t % 100 == 0){
			Watch <<<1, NTHREAD >>>(dev_domain, dev_rhoav);
			cudaStatus = hipMemcpy(rhoav, dev_rhoav, sizeof(double),\
				hipMemcpyDeviceToHost);
			if (cudaStatus != hipSuccess) goto Error;
			OutWatch(t, *err, *rhoav);
		}
		
		if ((*err < ERRMAX) || (t > NTMAX)) break;
	}
	Cvor <<<NBLOCK, NTHREAD >>>(dev_domain);
	finish = clock();
	printf("Time Take : %7.2lfs\n", (double)(finish - start) / CLOCKS_PER_SEC);

	cudaStatus = hipMemcpy(domain, dev_domain, NX * NY * sizeof(attribute),\
		hipMemcpyDeviceToHost);
	if (cudaStatus != hipSuccess) goto Error;

Error:
	free(err);
	free(rhoav);
	hipFree(dev_err);
	hipFree(dev_rhoav);
	hipFree(dev_domain);

	return cudaStatus;
}

int Ord2(int x, int y, int nx){
	return y * nx + x;
}

double Cfeq(double u[2], double rho, int k){
	double v1 = e[k * 2] * u[0] + e[k * 2 + 1] * u[1];
	double v2 = u[0] * u[0] + u[1] * u[1];
	return (rho * w[k] * (1.0 + v1 / (*CS2) + v1 * v1 / (2. * (*CS2)\
		* (*CS2)) - v2 / (2. * (*CS2))));
}

void Init(){
	CS2 = (double*)malloc(sizeof(double));
	NU = (double*)malloc(sizeof(double));
	TAO = (double*)malloc(sizeof(double));
	*CS2 = C * C / 3.;
	*NU = U0 * (NX - 1) * DX / RE;
	*TAO = *NU / DT / *CS2 + 0.5;
	domain = (attribute*)malloc(NX * NY * sizeof(attribute));
	memset(domain, 0, NX * NY * sizeof(attribute));
	for (int i = 0; i < NX; i++)
		for (int j = 0; j < NY; j++){
			domain[Ord2(i, j, NX)].rho = RHO0;
			domain[Ord2(i, j, NX)].u[0] = (j == NY - 1) ? U0 : 0.;
			domain[Ord2(i, j, NX)].u[1] = 0.;
			for (int k = 0; k < Q; k++)
				domain[Ord2(i, j, NX)].f[k] = Cfeq(domain[Ord2(i, j, NX)].u, \
				domain[Ord2(i, j, NX)].rho, k);
		}
	return;
}

void OutWatch(int t, double err, double rhoav){
	printf("Time Step %d, ", t);
	printf("Error = %lf, ", err);
	printf("Average Density = %lf\n", rhoav);
}

void Outp(){
	FILE *fp = fopen(OUTPUTFILENAME, "w");
	fprintf(fp, "Title=\"LBM Lid Driven Cavity\"\n");
	fprintf(fp, "VARIABLES=\"X\",\"Y\",\"U\",\"V\",\"P\",\"OMG\"\n");
	fprintf(fp, "ZONE T=\"BOX\",I=%d,J=%d,F=POINT\n", NX, NY);
	for (int j = 0; j < NY; j++)
		for (int i = 0; i < NX; i++){
			fprintf(fp, "%lf ", (double)i / (NX - 1) / DX);
			fprintf(fp, "%lf ", (double)j / (NY - 1) / DY);
			fprintf(fp, "%lf ", domain[Ord2(i, j, NX)].u[0]);
			fprintf(fp, "%lf ", domain[Ord2(i, j, NX)].u[1]);
			fprintf(fp, "%lf ", domain[Ord2(i, j, NX)].rho * (*CS2));
			fprintf(fp, "%lf\n", domain[Ord2(i, j, NX)].vor);
		}
	fclose(fp);
	return;
}

__device__ int d_Ord2(int x, int y, int nx){
	return y * nx + x;
}

__device__ void d_Ord2r(int id, int *x, int *y, int nx){
	*y = id / nx;
	*x = id % nx;
	return;
}

__device__ double d_Cfeq(double u[2], double rho, int k){
	double v1 = dev_e[k * 2] * u[0] + dev_e[k * 2 + 1] * u[1];
	double v2 = u[0] * u[0] + u[1] * u[1];
	return (rho * dev_w[k] * (1.0 + v1 / (*dev_CS2) + v1 * v1 / (2.\
		* (*dev_CS2) * (*dev_CS2)) - v2 / (2. * (*dev_CS2))));
}

__global__ void Collision(attribute *domain){
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		for (int k = 0; k < Q; k++){
			double feq = d_Cfeq(domain[tid].u, domain[tid].rho, k);
			domain[tid].fnew[k] = domain[tid].f[k] - (domain[tid].f[k]\
				- feq) / (*dev_TAO);
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void PreStreaming(attribute *domain){
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		for (int k = 0; k < Q; k++)
			domain[tid].g[k] = domain[tid].fnew[k];
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void Streaming(attribute *domain){
	int x, y;
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		for (int k = 0; k < Q; k++){
			int xn = (x + dev_e[k * 2] + NX) % NX;
			int yn = (y + dev_e[k * 2 + 1] + NY) % NY;
			domain[d_Ord2(xn, yn, NX)].fnew[k] = domain[tid].g[k];
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void Physics(attribute *domain){
	int x, y;
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		if ((x > 0) && (y > 0) && (x < NX - 1) && (y < NY - 1)){
			domain[tid].u0[0] = domain[tid].u[0];
			domain[tid].u0[1] = domain[tid].u[1];
			domain[tid].rho = 0.;
			domain[tid].u[0] = 0.;
			domain[tid].u[1] = 0.;
			for (int k = 0; k < Q; k++){
				domain[tid].f[k] = domain[tid].fnew[k];
				domain[tid].rho += domain[tid].f[k];
				domain[tid].u[0] += dev_e[k * 2] * domain[tid].f[k];
				domain[tid].u[1] += dev_e[k * 2 + 1] * domain[tid].f[k];
			}
			domain[tid].u[0] /= domain[tid].rho;
			domain[tid].u[1] /= domain[tid].rho;
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void MovingBoundary(attribute *domain){
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX){
		domain[d_Ord2(tid, NY - 1, NX)].rho = domain[d_Ord2(tid, NY - 2, NX)].rho;
		domain[d_Ord2(tid, NY - 1, NX)].u[0] = U0;
		for (int k = 0; k < Q; k++){
			domain[d_Ord2(tid, NY - 1, NX)].f[k] = d_Cfeq(domain[d_Ord2(tid, \
				NY - 1, NX)].u, domain[d_Ord2(tid, NY - 1, NX)].rho, k)\
				+ domain[d_Ord2(tid, NY - 2, NX)].f[k] - d_Cfeq(domain[d_Ord2(tid, \
				NY - 2, NX)].u, domain[d_Ord2(tid, NY - 2, NX)].rho, k);
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

__global__ void StaticBoundary(attribute *domain){
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	int tid0 = tid;
	while (tid < NX){
		domain[d_Ord2(tid, 0, NX)].rho = domain[d_Ord2(tid, 1, NX)].rho;
		for (int k = 0; k < Q; k++){
			domain[d_Ord2(tid, 0, NX)].f[k] = d_Cfeq(domain[d_Ord2(tid, \
				0, NX)].u, domain[d_Ord2(tid, 0, NX)].rho, k)\
				+ domain[d_Ord2(tid, 1, NX)].f[k] - d_Cfeq(domain[d_Ord2(tid, \
				1, NX)].u, domain[d_Ord2(tid, 1, NX)].rho, k);
		}
		tid += blockDim.x * gridDim.x;
	}
	tid = tid0;
	while (tid < NY - 1){
		if (tid > 0){
			domain[d_Ord2(0, tid, NX)].rho = domain[d_Ord2(1, tid, NX)].rho;
			domain[d_Ord2(NX - 1, tid, NX)].rho = domain[d_Ord2(NX - 2,\
				tid, NX)].rho;
			for (int k = 0; k < Q; k++){
				domain[d_Ord2(0, tid, NX)].f[k] = d_Cfeq(domain[d_Ord2(0,\
					tid, NX)].u, domain[d_Ord2(0, tid, NX)].rho, k)\
					+ domain[d_Ord2(1, tid, NX)].f[k] - d_Cfeq(domain[d_Ord2(1,\
					tid, NX)].u, domain[d_Ord2(1, tid, NX)].rho, k);
				domain[d_Ord2(NX - 1, tid, NX)].f[k] = d_Cfeq(domain[d_Ord2(NX - 1,\
					tid, NX)].u, domain[d_Ord2(NX - 1, tid, NX)].rho, k)\
					+ domain[d_Ord2(NX - 2, tid, NX)].f[k] - d_Cfeq(domain[d_Ord2(NX - 2,\
					tid, NX)].u, domain[d_Ord2(NX - 2, tid, NX)].rho, k);
			}
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}	

__global__ void Error(attribute *domain, double *err){
	__shared__ double cache[NTHREAD][2];
	int x, y;
	int tid = threadIdx.x;
	cache[threadIdx.x][0] = 0.;
	cache[threadIdx.x][1] = 0.;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		if ((x > 0) && (y > 0) && (x < NX - 1) && (y < NY - 1)){
			cache[threadIdx.x][0] += (domain[tid].u[0] - domain[tid].u0[0])\
				* (domain[tid].u[0] - domain[tid].u0[0]) + (domain[tid].u[1]\
				- domain[tid].u0[1]) * (domain[tid].u[1] - domain[tid].u0[1]);
			cache[threadIdx.x][1] += domain[tid].u[0] * domain[tid].u[0]\
				+ domain[tid].u[1] * domain[tid].u[1];
		}
		tid += blockDim.x;
	}
	__syncthreads();
	int i = blockDim.x / 2;
	while (i > 0){
		if (threadIdx.x < i){
			cache[threadIdx.x][0] += cache[threadIdx.x + i][0];
			cache[threadIdx.x][1] += cache[threadIdx.x + i][1];
		}
		__syncthreads();
		i /= 2;
	}
	if (threadIdx.x == 0)
		*err = sqrt(cache[threadIdx.x][0] / (cache[threadIdx.x][1] + 1.E-10));
	return;
}

__global__ void Watch(attribute *domain, double *rhoav){
	__shared__ int cachen[NTHREAD];
	__shared__ double cache[NTHREAD];
	int x, y;
	int tid = threadIdx.x;
	cachen[threadIdx.x] = 0;
	cache[threadIdx.x] = 0.;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		if ((x > 0) && (y > 0) && (x < NX - 1) && (y < NY - 1)){
			cachen[threadIdx.x]++;
			cache[threadIdx.x] += domain[tid].rho;
		}
		tid += blockDim.x;
	}
	__syncthreads();
	int i = blockDim.x / 2;
	while (i > 0){
		if (threadIdx.x < i){
			cache[threadIdx.x] += cache[threadIdx.x + i];
			cachen[threadIdx.x] += cachen[threadIdx.x + i];
		}
		__syncthreads();
		i /= 2;
	}
	if (threadIdx.x == 0)
		*rhoav = cache[threadIdx.x] / ((double)cachen[threadIdx.x] + 1.E-10);
	return;
}

__global__ void Cvor(attribute *domain){
	int x, y;
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	while (tid < NX * NY){
		d_Ord2r(tid, &x, &y, NX);
		if ((x > 0) && (y > 0) && (x < NX - 1) && (y < NY - 1)){
			domain[tid].vor = (domain[d_Ord2(x + 1, y, NX)].u[1]\
				- domain[d_Ord2(x - 1, y, NX)].u[1]) / (2 * DX);
			domain[tid].vor -= (domain[d_Ord2(x, y + 1, NX)].u[0]\
				- domain[d_Ord2(x, y - 1, NX)].u[0]) / (2 * DY);
		}
		tid += blockDim.x * gridDim.x;
	}
	return;
}

	.text
	.file	"kernel.hip"
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	_Z4Initv
	callq	_Z3LBMv
	testl	%eax, %eax
	jne	.LBB0_1
# %bb.2:
	callq	_Z4Outpv
	movq	CS2(%rip), %rdi
	callq	free
	movq	NU(%rip), %rdi
	callq	free
	movq	TAO(%rip), %rdi
	callq	free
	movq	domain(%rip), %rdi
	callq	free
	xorl	%eax, %eax
.LBB0_3:
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.LBB0_1:
	.cfi_def_cfa_offset 16
	movq	stderr(%rip), %rcx
	movl	$.L.str, %edi
	movl	$16, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movl	$1, %eax
	jmp	.LBB0_3
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z4Initv
.LCPI1_0:
	.quad	0x4008000000000000              # double 3
.LCPI1_1:
	.quad	0x3f947ae147ae147b              # double 0.02
.LCPI1_2:
	.quad	0x3fe0000000000000              # double 0.5
.LCPI1_3:
	.quad	0x3fb999999999999a              # double 0.10000000000000001
	.text
	.globl	_Z4Initv
	.type	_Z4Initv,@function
_Z4Initv:                               # @_Z4Initv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$8, %edi
	callq	malloc
	movq	%rax, %rbx
	movq	%rax, CS2(%rip)
	movl	$8, %edi
	callq	malloc
	movq	%rax, %r14
	movq	%rax, NU(%rip)
	movl	$8, %edi
	callq	malloc
	movq	%rax, TAO(%rip)
	movl	C(%rip), %ecx
	imull	%ecx, %ecx
	cvtsi2sd	%ecx, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	movsd	%xmm0, (%rbx)
	movabsq	$4581421828931458171, %rcx      # imm = 0x3F947AE147AE147B
	movq	%rcx, (%r14)
	movsd	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero
	divsd	%xmm0, %xmm1
	addsd	.LCPI1_2(%rip), %xmm1
	movsd	%xmm1, (%rax)
	movl	$1, %edi
	movl	$10665864, %esi                 # imm = 0xA2BF88
	callq	calloc@PLT
	movq	%rax, %rbx
	movq	%rax, domain(%rip)
	xorl	%eax, %eax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	%rbx, %rbp
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
                                        #       Child Loop BB1_5 Depth 3
	movq	%rbp, 16(%rsp)                  # 8-byte Spill
	xorl	%r13d, %r13d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_5 Depth 3
	imulq	$201, %r13, %rax
	addq	8(%rsp), %rax                   # 8-byte Folded Reload
	movq	%rax, %rcx
	shlq	$8, %rcx
	leaq	(%rcx,%rax,8), %rax
	movabsq	$4607182418800017408, %rcx      # imm = 0x3FF0000000000000
	movq	%rcx, 248(%rbx,%rax)
	movsd	.LCPI1_3(%rip), %xmm0           # xmm0 = mem[0],zero
	cmpq	$200, %r13
	je	.LBB1_4
# %bb.3:                                #   in Loop: Header=BB1_2 Depth=2
	xorps	%xmm0, %xmm0
.LBB1_4:                                #   in Loop: Header=BB1_2 Depth=2
	leaq	(%rbx,%rax), %r12
	addq	$248, %r12
	leaq	(%rbx,%rax), %r14
	addq	$216, %r14
	movsd	%xmm0, 216(%rbx,%rax)
	movq	$0, 224(%rbx,%rax)
	xorl	%r15d, %r15d
.LBB1_5:                                #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movsd	(%r12), %xmm0                   # xmm0 = mem[0],zero
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_Z4CfeqPddi
	movsd	%xmm0, (%rbp,%r15,8)
	incq	%r15
	cmpq	$9, %r15
	jne	.LBB1_5
# %bb.6:                                #   in Loop: Header=BB1_2 Depth=2
	incq	%r13
	addq	$53064, %rbp                    # imm = 0xCF48
	cmpq	$201, %r13
	jne	.LBB1_2
# %bb.7:                                #   in Loop: Header=BB1_1 Depth=1
	movq	8(%rsp), %rcx                   # 8-byte Reload
	incq	%rcx
	movq	16(%rsp), %rbp                  # 8-byte Reload
	addq	$264, %rbp                      # imm = 0x108
	movq	%rcx, %rax
	movq	%rcx, 8(%rsp)                   # 8-byte Spill
	cmpq	$201, %rcx
	jne	.LBB1_1
# %bb.8:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z4Initv, .Lfunc_end1-_Z4Initv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z3LBMv
.LCPI2_0:
	.quad	0x3ee4f8b588e368f1              # double 1.0000000000000001E-5
.LCPI2_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z3LBMv
	.type	_Z3LBMv,@function
_Z3LBMv:                                # @_Z3LBMv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$8, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$8, %edi
	callq	malloc
	movq	%rax, %r14
	xorl	%edi, %edi
	callq	hipSetDevice
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.1:
	leaq	16(%rsp), %rdi
	movl	$8, %esi
	callq	hipMalloc
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.2:
	leaq	8(%rsp), %rdi
	movl	$8, %esi
	callq	hipMalloc
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.3:
	movq	%rsp, %rdi
	movl	$10665864, %esi                 # imm = 0xA2BF88
	callq	hipMalloc
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.4:
	movq	(%rsp), %rdi
	movq	domain(%rip), %rsi
	movl	$10665864, %edx                 # imm = 0xA2BF88
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.5:
	movl	$dev_w, %edi
	movl	$_ZL1w, %esi
	movl	$72, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.6:
	movl	$dev_e, %edi
	movl	$e, %esi
	movl	$72, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.7:
	movq	CS2(%rip), %rsi
	movl	$dev_CS2, %edi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.8:
	movq	NU(%rip), %rsi
	movl	$dev_NU, %edi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.9:
	movq	TAO(%rip), %rsi
	xorl	%r12d, %r12d
	movl	$dev_TAO, %edi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	%eax, %r15d
	testl	%eax, %eax
	jne	.LBB2_37
# %bb.10:
	movabsq	$4294967808, %r13               # imm = 0x100000200
	callq	clock
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	leaq	-256(%r13), %rbp
	leaq	-511(%r13), %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
.LBB2_11:                               # =>This Inner Loop Header: Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_13
# %bb.12:                               #   in Loop: Header=BB2_11 Depth=1
	movq	(%rsp), %rdi
	callq	_Z24__device_stub__CollisionP9attribute
.LBB2_13:                               #   in Loop: Header=BB2_11 Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_15
# %bb.14:                               #   in Loop: Header=BB2_11 Depth=1
	movq	(%rsp), %rdi
	callq	_Z27__device_stub__PreStreamingP9attribute
.LBB2_15:                               #   in Loop: Header=BB2_11 Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_17
# %bb.16:                               #   in Loop: Header=BB2_11 Depth=1
	movq	(%rsp), %rdi
	callq	_Z24__device_stub__StreamingP9attribute
.LBB2_17:                               #   in Loop: Header=BB2_11 Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_19
# %bb.18:                               #   in Loop: Header=BB2_11 Depth=1
	movq	(%rsp), %rdi
	callq	_Z22__device_stub__PhysicsP9attribute
.LBB2_19:                               #   in Loop: Header=BB2_11 Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_21
# %bb.20:                               #   in Loop: Header=BB2_11 Depth=1
	movq	(%rsp), %rdi
	callq	_Z29__device_stub__MovingBoundaryP9attribute
.LBB2_21:                               #   in Loop: Header=BB2_11 Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_23
# %bb.22:                               #   in Loop: Header=BB2_11 Depth=1
	movq	(%rsp), %rdi
	callq	_Z29__device_stub__StaticBoundaryP9attribute
.LBB2_23:                               #   in Loop: Header=BB2_11 Depth=1
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_25
# %bb.24:                               #   in Loop: Header=BB2_11 Depth=1
	movq	(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	_Z20__device_stub__ErrorP9attributePd
.LBB2_25:                               #   in Loop: Header=BB2_11 Depth=1
	movq	16(%rsp), %rsi
	movl	$8, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_36
# %bb.26:                               #   in Loop: Header=BB2_11 Depth=1
	movl	%r12d, %eax
	imulq	$1374389535, %rax, %rax         # imm = 0x51EB851F
	shrq	$37, %rax
	imull	$100, %eax, %eax
	cmpl	%r12d, %eax
	jne	.LBB2_31
# %bb.27:                               #   in Loop: Header=BB2_11 Depth=1
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_29
# %bb.28:                               #   in Loop: Header=BB2_11 Depth=1
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z20__device_stub__WatchP9attributePd
.LBB2_29:                               #   in Loop: Header=BB2_11 Depth=1
	movq	8(%rsp), %rsi
	movl	$8, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_36
# %bb.30:                               #   in Loop: Header=BB2_11 Depth=1
	movsd	(%rbx), %xmm0                   # xmm0 = mem[0],zero
	movsd	(%r14), %xmm1                   # xmm1 = mem[0],zero
	movl	%r12d, %edi
	callq	_Z8OutWatchidd
.LBB2_31:                               #   in Loop: Header=BB2_11 Depth=1
	movsd	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero
	ucomisd	(%rbx), %xmm0
	ja	.LBB2_33
# %bb.32:                               #   in Loop: Header=BB2_11 Depth=1
	leal	1(%r12), %eax
	cmpl	$50001, %r12d                   # imm = 0xC351
	movl	%eax, %r12d
	jb	.LBB2_11
.LBB2_33:
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_35
# %bb.34:
	movq	(%rsp), %rdi
	callq	_Z19__device_stub__CvorP9attribute
.LBB2_35:
	callq	clock
	subq	32(%rsp), %rax                  # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI2_1(%rip), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	domain(%rip), %rdi
	movq	(%rsp), %rsi
	movl	$10665864, %edx                 # imm = 0xA2BF88
	movl	$2, %ecx
	callq	hipMemcpy
.LBB2_36:                               # %.thread
	movl	%eax, %r15d
.LBB2_37:                               # %.thread
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movl	%r15d, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z3LBMv, .Lfunc_end2-_Z3LBMv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z4Outpv
.LCPI3_0:
	.quad	0x4069000000000000              # double 200
	.text
	.globl	_Z4Outpv
	.type	_Z4Outpv,@function
_Z4Outpv:                               # @_Z4Outpv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	$.L.str.7, %edi
	movl	$30, %esi
	movl	$1, %edx
	movq	%rax, %rcx
	callq	fwrite@PLT
	movl	$.L.str.8, %edi
	movl	$36, %esi
	movl	$1, %edx
	movq	%rbx, %rcx
	callq	fwrite@PLT
	xorl	%r14d, %r14d
	movl	$.L.str.9, %esi
	movq	%rbx, %rdi
	movl	$201, %edx
	movl	$201, %ecx
	xorl	%eax, %eax
	callq	fprintf
	movsd	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero
	xorl	%r15d, %r15d
.LBB3_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r15d, %xmm0
	divsd	%xmm1, %xmm0
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r13d, %xmm0
	divsd	%xmm1, %xmm0
	movl	$.L.str.10, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	movl	$.L.str.10, %esi
	movq	%rbx, %rdi
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	fprintf
	movq	domain(%rip), %rax
	movsd	216(%rax,%r12), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.10, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	movq	domain(%rip), %rax
	movsd	224(%rax,%r12), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.10, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	movq	domain(%rip), %rax
	movsd	248(%rax,%r12), %xmm0           # xmm0 = mem[0],zero
	movq	CS2(%rip), %rax
	mulsd	(%rax), %xmm0
	movl	$.L.str.10, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	movq	domain(%rip), %rax
	movsd	256(%rax,%r12), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.11, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	movsd	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero
	incq	%r13
	addq	$264, %r12                      # imm = 0x108
	cmpq	$201, %r13
	jne	.LBB3_2
# %bb.3:                                #   in Loop: Header=BB3_1 Depth=1
	incq	%r15
	addq	$53064, %r14                    # imm = 0xCF48
	cmpq	$201, %r15
	jne	.LBB3_1
# %bb.4:
	movq	%rbx, %rdi
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end3:
	.size	_Z4Outpv, .Lfunc_end3-_Z4Outpv
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__CollisionP9attribute # -- Begin function _Z24__device_stub__CollisionP9attribute
	.type	_Z24__device_stub__CollisionP9attribute,@function
_Z24__device_stub__CollisionP9attribute: # @_Z24__device_stub__CollisionP9attribute
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9CollisionP9attribute, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z24__device_stub__CollisionP9attribute, .Lfunc_end4-_Z24__device_stub__CollisionP9attribute
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__PreStreamingP9attribute # -- Begin function _Z27__device_stub__PreStreamingP9attribute
	.type	_Z27__device_stub__PreStreamingP9attribute,@function
_Z27__device_stub__PreStreamingP9attribute: # @_Z27__device_stub__PreStreamingP9attribute
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12PreStreamingP9attribute, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z27__device_stub__PreStreamingP9attribute, .Lfunc_end5-_Z27__device_stub__PreStreamingP9attribute
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__StreamingP9attribute # -- Begin function _Z24__device_stub__StreamingP9attribute
	.type	_Z24__device_stub__StreamingP9attribute,@function
_Z24__device_stub__StreamingP9attribute: # @_Z24__device_stub__StreamingP9attribute
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9StreamingP9attribute, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z24__device_stub__StreamingP9attribute, .Lfunc_end6-_Z24__device_stub__StreamingP9attribute
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__PhysicsP9attribute # -- Begin function _Z22__device_stub__PhysicsP9attribute
	.type	_Z22__device_stub__PhysicsP9attribute,@function
_Z22__device_stub__PhysicsP9attribute:  # @_Z22__device_stub__PhysicsP9attribute
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7PhysicsP9attribute, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z22__device_stub__PhysicsP9attribute, .Lfunc_end7-_Z22__device_stub__PhysicsP9attribute
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__MovingBoundaryP9attribute # -- Begin function _Z29__device_stub__MovingBoundaryP9attribute
	.type	_Z29__device_stub__MovingBoundaryP9attribute,@function
_Z29__device_stub__MovingBoundaryP9attribute: # @_Z29__device_stub__MovingBoundaryP9attribute
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14MovingBoundaryP9attribute, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z29__device_stub__MovingBoundaryP9attribute, .Lfunc_end8-_Z29__device_stub__MovingBoundaryP9attribute
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__StaticBoundaryP9attribute # -- Begin function _Z29__device_stub__StaticBoundaryP9attribute
	.type	_Z29__device_stub__StaticBoundaryP9attribute,@function
_Z29__device_stub__StaticBoundaryP9attribute: # @_Z29__device_stub__StaticBoundaryP9attribute
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14StaticBoundaryP9attribute, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z29__device_stub__StaticBoundaryP9attribute, .Lfunc_end9-_Z29__device_stub__StaticBoundaryP9attribute
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__ErrorP9attributePd # -- Begin function _Z20__device_stub__ErrorP9attributePd
	.type	_Z20__device_stub__ErrorP9attributePd,@function
_Z20__device_stub__ErrorP9attributePd:  # @_Z20__device_stub__ErrorP9attributePd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5ErrorP9attributePd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z20__device_stub__ErrorP9attributePd, .Lfunc_end10-_Z20__device_stub__ErrorP9attributePd
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__WatchP9attributePd # -- Begin function _Z20__device_stub__WatchP9attributePd
	.type	_Z20__device_stub__WatchP9attributePd,@function
_Z20__device_stub__WatchP9attributePd:  # @_Z20__device_stub__WatchP9attributePd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5WatchP9attributePd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z20__device_stub__WatchP9attributePd, .Lfunc_end11-_Z20__device_stub__WatchP9attributePd
	.cfi_endproc
                                        # -- End function
	.globl	_Z8OutWatchidd                  # -- Begin function _Z8OutWatchidd
	.type	_Z8OutWatchidd,@function
_Z8OutWatchidd:                         # @_Z8OutWatchidd
	.cfi_startproc
# %bb.0:
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movsd	%xmm1, 16(%rsp)                 # 8-byte Spill
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movl	%edi, %esi
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.3, %edi
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movl	$.L.str.4, %edi
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.Lfunc_end12:
	.size	_Z8OutWatchidd, .Lfunc_end12-_Z8OutWatchidd
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__CvorP9attribute # -- Begin function _Z19__device_stub__CvorP9attribute
	.type	_Z19__device_stub__CvorP9attribute,@function
_Z19__device_stub__CvorP9attribute:     # @_Z19__device_stub__CvorP9attribute
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4CvorP9attribute, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z19__device_stub__CvorP9attribute, .Lfunc_end13-_Z19__device_stub__CvorP9attribute
	.cfi_endproc
                                        # -- End function
	.globl	_Z4Ord2iii                      # -- Begin function _Z4Ord2iii
	.type	_Z4Ord2iii,@function
_Z4Ord2iii:                             # @_Z4Ord2iii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
                                        # kill: def $edi killed $edi def $rdi
	imull	%edx, %esi
	leal	(%rsi,%rdi), %eax
	retq
.Lfunc_end14:
	.size	_Z4Ord2iii, .Lfunc_end14-_Z4Ord2iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z4CfeqPddi
.LCPI15_0:
	.quad	0x3ff0000000000000              # double 1
	.text
	.globl	_Z4CfeqPddi
	.type	_Z4CfeqPddi,@function
_Z4CfeqPddi:                            # @_Z4CfeqPddi
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
	leal	(%rsi,%rsi), %eax
	cltq
	cvtsi2sdl	e(,%rax,4), %xmm3
	movsd	(%rdi), %xmm4                   # xmm4 = mem[0],zero
	movsd	8(%rdi), %xmm1                  # xmm1 = mem[0],zero
	mulsd	%xmm4, %xmm3
	leal	1(%rsi,%rsi), %eax
	cltq
	cvtsi2sdl	e(,%rax,4), %xmm2
	mulsd	%xmm1, %xmm2
	addsd	%xmm3, %xmm2
	mulsd	%xmm4, %xmm4
	mulsd	%xmm1, %xmm1
	addsd	%xmm4, %xmm1
	movslq	%esi, %rax
	mulsd	_ZL1w(,%rax,8), %xmm0
	movq	CS2(%rip), %rax
	movsd	(%rax), %xmm3                   # xmm3 = mem[0],zero
	movapd	%xmm2, %xmm4
	divsd	%xmm3, %xmm4
	addsd	.LCPI15_0(%rip), %xmm4
	mulsd	%xmm2, %xmm2
	movapd	%xmm3, %xmm5
	addsd	%xmm3, %xmm5
	mulsd	%xmm5, %xmm3
	divsd	%xmm3, %xmm2
	addsd	%xmm4, %xmm2
	divsd	%xmm5, %xmm1
	subsd	%xmm1, %xmm2
	mulsd	%xmm2, %xmm0
	retq
.Lfunc_end15:
	.size	_Z4CfeqPddi, .Lfunc_end15-_Z4CfeqPddi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB16_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB16_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9CollisionP9attribute, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12PreStreamingP9attribute, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9StreamingP9attribute, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7PhysicsP9attribute, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14MovingBoundaryP9attribute, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14StaticBoundaryP9attribute, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5ErrorP9attributePd, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5WatchP9attributePd, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4CvorP9attribute, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$dev_CS2, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$dev_NU, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$dev_TAO, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$dev_w, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$dev_e, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end16:
	.size	__hip_module_ctor, .Lfunc_end16-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB17_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB17_2:
	retq
.Lfunc_end17:
	.size	__hip_module_dtor, .Lfunc_end17-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	dev_CS2,@object                 # @dev_CS2
	.local	dev_CS2
	.comm	dev_CS2,8,8
	.type	dev_NU,@object                  # @dev_NU
	.local	dev_NU
	.comm	dev_NU,8,8
	.type	dev_TAO,@object                 # @dev_TAO
	.local	dev_TAO
	.comm	dev_TAO,8,8
	.type	dev_w,@object                   # @dev_w
	.local	dev_w
	.comm	dev_w,72,16
	.type	dev_e,@object                   # @dev_e
	.local	dev_e
	.comm	dev_e,72,16
	.type	C,@object                       # @C
	.data
	.globl	C
	.p2align	2, 0x0
C:
	.long	1                               # 0x1
	.size	C, 4

	.type	e,@object                       # @e
	.globl	e
	.p2align	4, 0x0
e:
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	4294967295                      # 0xffffffff
	.long	0                               # 0x0
	.long	0                               # 0x0
	.long	4294967295                      # 0xffffffff
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	4294967295                      # 0xffffffff
	.long	1                               # 0x1
	.long	4294967295                      # 0xffffffff
	.long	4294967295                      # 0xffffffff
	.long	1                               # 0x1
	.long	4294967295                      # 0xffffffff
	.size	e, 72

	.type	CS2,@object                     # @CS2
	.bss
	.globl	CS2
	.p2align	3, 0x0
CS2:
	.quad	0
	.size	CS2, 8

	.type	NU,@object                      # @NU
	.globl	NU
	.p2align	3, 0x0
NU:
	.quad	0
	.size	NU, 8

	.type	TAO,@object                     # @TAO
	.globl	TAO
	.p2align	3, 0x0
TAO:
	.quad	0
	.size	TAO, 8

	.type	domain,@object                  # @domain
	.globl	domain
	.p2align	3, 0x0
domain:
	.quad	0
	.size	domain, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Cuda LBM Failed!"
	.size	.L.str, 17

	.type	_ZL1w,@object                   # @_ZL1w
	.section	.rodata,"a",@progbits
	.p2align	4, 0x0
_ZL1w:
	.quad	0x3fdc71c71c71c71c              # double 0.44444444444444442
	.quad	0x3fbc71c71c71c71c              # double 0.1111111111111111
	.quad	0x3fbc71c71c71c71c              # double 0.1111111111111111
	.quad	0x3fbc71c71c71c71c              # double 0.1111111111111111
	.quad	0x3fbc71c71c71c71c              # double 0.1111111111111111
	.quad	0x3f9c71c71c71c71c              # double 0.027777777777777776
	.quad	0x3f9c71c71c71c71c              # double 0.027777777777777776
	.quad	0x3f9c71c71c71c71c              # double 0.027777777777777776
	.quad	0x3f9c71c71c71c71c              # double 0.027777777777777776
	.size	_ZL1w, 72

	.type	_Z9CollisionP9attribute,@object # @_Z9CollisionP9attribute
	.globl	_Z9CollisionP9attribute
	.p2align	3, 0x0
_Z9CollisionP9attribute:
	.quad	_Z24__device_stub__CollisionP9attribute
	.size	_Z9CollisionP9attribute, 8

	.type	_Z12PreStreamingP9attribute,@object # @_Z12PreStreamingP9attribute
	.globl	_Z12PreStreamingP9attribute
	.p2align	3, 0x0
_Z12PreStreamingP9attribute:
	.quad	_Z27__device_stub__PreStreamingP9attribute
	.size	_Z12PreStreamingP9attribute, 8

	.type	_Z9StreamingP9attribute,@object # @_Z9StreamingP9attribute
	.globl	_Z9StreamingP9attribute
	.p2align	3, 0x0
_Z9StreamingP9attribute:
	.quad	_Z24__device_stub__StreamingP9attribute
	.size	_Z9StreamingP9attribute, 8

	.type	_Z7PhysicsP9attribute,@object   # @_Z7PhysicsP9attribute
	.globl	_Z7PhysicsP9attribute
	.p2align	3, 0x0
_Z7PhysicsP9attribute:
	.quad	_Z22__device_stub__PhysicsP9attribute
	.size	_Z7PhysicsP9attribute, 8

	.type	_Z14MovingBoundaryP9attribute,@object # @_Z14MovingBoundaryP9attribute
	.globl	_Z14MovingBoundaryP9attribute
	.p2align	3, 0x0
_Z14MovingBoundaryP9attribute:
	.quad	_Z29__device_stub__MovingBoundaryP9attribute
	.size	_Z14MovingBoundaryP9attribute, 8

	.type	_Z14StaticBoundaryP9attribute,@object # @_Z14StaticBoundaryP9attribute
	.globl	_Z14StaticBoundaryP9attribute
	.p2align	3, 0x0
_Z14StaticBoundaryP9attribute:
	.quad	_Z29__device_stub__StaticBoundaryP9attribute
	.size	_Z14StaticBoundaryP9attribute, 8

	.type	_Z5ErrorP9attributePd,@object   # @_Z5ErrorP9attributePd
	.globl	_Z5ErrorP9attributePd
	.p2align	3, 0x0
_Z5ErrorP9attributePd:
	.quad	_Z20__device_stub__ErrorP9attributePd
	.size	_Z5ErrorP9attributePd, 8

	.type	_Z5WatchP9attributePd,@object   # @_Z5WatchP9attributePd
	.globl	_Z5WatchP9attributePd
	.p2align	3, 0x0
_Z5WatchP9attributePd:
	.quad	_Z20__device_stub__WatchP9attributePd
	.size	_Z5WatchP9attributePd, 8

	.type	_Z4CvorP9attribute,@object      # @_Z4CvorP9attribute
	.globl	_Z4CvorP9attribute
	.p2align	3, 0x0
_Z4CvorP9attribute:
	.quad	_Z19__device_stub__CvorP9attribute
	.size	_Z4CvorP9attribute, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Time Take : %7.2lfs\n"
	.size	.L.str.1, 21

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Time Step %d, "
	.size	.L.str.2, 15

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Error = %lf, "
	.size	.L.str.3, 14

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Average Density = %lf\n"
	.size	.L.str.4, 23

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"output.dat"
	.size	.L.str.5, 11

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"w"
	.size	.L.str.6, 2

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Title=\"LBM Lid Driven Cavity\"\n"
	.size	.L.str.7, 31

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"VARIABLES=\"X\",\"Y\",\"U\",\"V\",\"P\",\"OMG\"\n"
	.size	.L.str.8, 37

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"ZONE T=\"BOX\",I=%d,J=%d,F=POINT\n"
	.size	.L.str.9, 32

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"%lf "
	.size	.L.str.10, 5

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"%lf\n"
	.size	.L.str.11, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9CollisionP9attribute"
	.size	.L__unnamed_1, 24

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12PreStreamingP9attribute"
	.size	.L__unnamed_2, 28

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9StreamingP9attribute"
	.size	.L__unnamed_3, 24

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z7PhysicsP9attribute"
	.size	.L__unnamed_4, 22

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z14MovingBoundaryP9attribute"
	.size	.L__unnamed_5, 30

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z14StaticBoundaryP9attribute"
	.size	.L__unnamed_6, 30

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z5ErrorP9attributePd"
	.size	.L__unnamed_7, 22

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z5WatchP9attributePd"
	.size	.L__unnamed_8, 22

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z4CvorP9attribute"
	.size	.L__unnamed_9, 19

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"dev_CS2"
	.size	.L__unnamed_10, 8

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"dev_NU"
	.size	.L__unnamed_11, 7

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"dev_TAO"
	.size	.L__unnamed_12, 8

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"dev_w"
	.size	.L__unnamed_13, 6

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"dev_e"
	.size	.L__unnamed_14, 6

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__CollisionP9attribute
	.addrsig_sym _Z27__device_stub__PreStreamingP9attribute
	.addrsig_sym _Z24__device_stub__StreamingP9attribute
	.addrsig_sym _Z22__device_stub__PhysicsP9attribute
	.addrsig_sym _Z29__device_stub__MovingBoundaryP9attribute
	.addrsig_sym _Z29__device_stub__StaticBoundaryP9attribute
	.addrsig_sym _Z20__device_stub__ErrorP9attributePd
	.addrsig_sym _Z20__device_stub__WatchP9attributePd
	.addrsig_sym _Z19__device_stub__CvorP9attribute
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym dev_CS2
	.addrsig_sym dev_NU
	.addrsig_sym dev_TAO
	.addrsig_sym dev_w
	.addrsig_sym dev_e
	.addrsig_sym e
	.addrsig_sym _ZL1w
	.addrsig_sym _Z9CollisionP9attribute
	.addrsig_sym _Z12PreStreamingP9attribute
	.addrsig_sym _Z9StreamingP9attribute
	.addrsig_sym _Z7PhysicsP9attribute
	.addrsig_sym _Z14MovingBoundaryP9attribute
	.addrsig_sym _Z14StaticBoundaryP9attribute
	.addrsig_sym _Z5ErrorP9attributePd
	.addrsig_sym _Z5WatchP9attributePd
	.addrsig_sym _Z4CvorP9attribute
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9CollisionP9attribute ; -- Begin function _Z9CollisionP9attribute
	.globl	_Z9CollisionP9attribute
	.p2align	8
	.type	_Z9CollisionP9attribute,@function
_Z9CollisionP9attribute:                ; @_Z9CollisionP9attribute
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	s_add_u32 s4, s0, 8
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s2, 0xffff
	s_mov_b32 s2, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x9dd1, v1
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.preheader.lr.ph
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dev_CS2@rel32@lo+4
	s_addc_u32 s3, s3, dev_CS2@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, dev_TAO@rel32@lo+4
	s_addc_u32 s7, s7, dev_TAO@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b32 s10, s[4:5], 0x0
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b64 s[6:7], s[6:7], 0x0
	s_mov_b32 s11, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s10, s10, s8
	v_add_f64 v[2:3], s[2:3], s[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[4:5], s[2:3], v[2:3]
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	v_mad_i64_i32 v[6:7], null, 0x108, v1, s[4:5]
	s_mov_b64 s[8:9], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, 0xd8, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, 0xf8, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v7, vcc_lo
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b128 v[12:15], v[8:9], off
	global_load_b64 v[16:17], v[10:11], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_e@rel32@lo+4
	s_addc_u32 s1, s1, dev_e@rel32@hi+12
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[18:19], s1
	v_cvt_f64_i32_e32 v[20:21], s0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[14:15], v[18:19]
	v_mul_f64 v[14:15], v[14:15], v[14:15]
	v_fma_f64 v[18:19], v[12:13], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[12:13], v[12:13], v[14:15]
	v_div_scale_f64 v[20:21], null, s[2:3], s[2:3], v[18:19]
	v_mul_f64 v[22:23], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[26:27], null, v[2:3], v[2:3], v[12:13]
	v_rcp_f64_e32 v[14:15], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[24:25], null, v[4:5], v[4:5], v[22:23]
	v_rcp_f64_e32 v[32:33], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[28:29], v[24:25]
	v_fma_f64 v[30:31], -v[20:21], v[14:15], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[34:35], -v[26:27], v[32:33], 1.0
	v_fma_f64 v[14:15], v[14:15], v[30:31], v[14:15]
	v_fma_f64 v[30:31], -v[24:25], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[32:33], v[32:33], v[34:35], v[32:33]
	v_fma_f64 v[36:37], -v[20:21], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[28:29], v[28:29], v[30:31], v[28:29]
	v_add_co_u32 v30, vcc_lo, v6, s8
	v_add_co_ci_u32_e32 v31, vcc_lo, s9, v7, vcc_lo
	v_div_scale_f64 v[40:41], vcc_lo, v[18:19], s[2:3], v[18:19]
	v_fma_f64 v[42:43], -v[26:27], v[32:33], 1.0
	global_load_b64 v[38:39], v[30:31], off
	v_fma_f64 v[14:15], v[14:15], v[36:37], v[14:15]
	v_fma_f64 v[34:35], -v[24:25], v[28:29], 1.0
	v_div_scale_f64 v[36:37], s0, v[22:23], v[4:5], v[22:23]
	v_fma_f64 v[32:33], v[32:33], v[42:43], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[44:45], v[40:41], v[14:15]
	v_fma_f64 v[28:29], v[28:29], v[34:35], v[28:29]
	v_div_scale_f64 v[34:35], s1, v[12:13], v[2:3], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], -v[20:21], v[44:45], v[40:41]
	v_mul_f64 v[40:41], v[36:37], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[42:43], v[34:35], v[32:33]
	v_div_fmas_f64 v[14:15], v[20:21], v[14:15], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], -v[24:25], v[40:41], v[36:37]
	s_mov_b32 vcc_lo, s0
	v_fma_f64 v[24:25], -v[26:27], v[42:43], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[14:15], v[14:15], s[2:3], v[18:19]
	v_div_fmas_f64 v[18:19], v[20:21], v[28:29], v[40:41]
	s_mov_b32 vcc_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_w@rel32@lo+4
	s_addc_u32 s1, s1, dev_w@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fmas_f64 v[20:21], v[24:25], v[32:33], v[42:43]
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	s_add_u32 s8, s8, 8
	s_load_b64 s[0:1], s[0:1], 0x0
	s_addc_u32 s9, s9, 0
	s_cmpk_eq_i32 s8, 0x48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[16:17], v[16:17], s[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[14:15], 1.0
	v_div_fixup_f64 v[18:19], v[18:19], v[4:5], v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[12:13], v[20:21], v[2:3], v[12:13]
	v_add_f64 v[14:15], v[14:15], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[14:15], -v[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], -v[16:17], v[12:13], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[14:15], null, s[6:7], s[6:7], v[12:13]
	v_div_scale_f64 v[20:21], vcc_lo, v[12:13], s[6:7], v[12:13]
	v_rcp_f64_e32 v[16:17], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_mul_f64 v[18:19], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[14:15], v[18:19], v[20:21]
	v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[12:13], v[14:15], s[6:7], v[12:13]
	v_add_f64 v[12:13], v[38:39], -v[12:13]
	global_store_b64 v[30:31], v[12:13], off offset:72
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v1, s10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0x9dd0, v1
	s_or_b32 s11, vcc_lo, s11
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_2
.LBB0_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9CollisionP9attribute
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9CollisionP9attribute, .Lfunc_end0-_Z9CollisionP9attribute
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 936
; NumSgprs: 18
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12PreStreamingP9attribute ; -- Begin function _Z12PreStreamingP9attribute
	.globl	_Z12PreStreamingP9attribute
	.p2align	8
	.type	_Z12PreStreamingP9attribute,@function
_Z12PreStreamingP9attribute:            ; @_Z12PreStreamingP9attribute
; %bb.0:
	s_load_b32 s4, s[0:1], 0x14
	s_add_u32 s2, s0, 8
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmpx_gt_i32_e32 0x9dd1, v1
	s_cbranch_execz .LBB1_5
; %bb.1:                                ; %.preheader.lr.ph
	s_load_b32 s2, s[2:3], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mov_b32 s5, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s4
.LBB1_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
	v_mad_i64_i32 v[2:3], null, 0x108, v1, s[0:1]
	s_mov_b64 s[2:3], 0
.LBB1_3:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v2, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s2, 0x48
	global_load_b64 v[6:7], v[4:5], off offset:72
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[6:7], off offset:144
	s_cbranch_scc0 .LBB1_3
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add_nc_u32_e32 v1, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0x9dd0, v1
	s_or_b32 s5, vcc_lo, s5
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB1_2
.LBB1_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12PreStreamingP9attribute
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12PreStreamingP9attribute, .Lfunc_end1-_Z12PreStreamingP9attribute
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9StreamingP9attribute ; -- Begin function _Z9StreamingP9attribute
	.globl	_Z9StreamingP9attribute
	.p2align	8
	.type	_Z9StreamingP9attribute,@function
_Z9StreamingP9attribute:                ; @_Z9StreamingP9attribute
; %bb.0:
	s_load_b32 s4, s[0:1], 0x14
	s_add_u32 s2, s0, 8
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmpx_gt_i32_e32 0x9dd1, v1
	s_cbranch_execz .LBB2_5
; %bb.1:                                ; %.lr.ph
	s_load_b32 s5, s[2:3], 0x0
	s_load_b64 s[2:3], s[0:1], 0x0
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s5, s4
	s_add_u32 s0, s2, 0x90
	s_addc_u32 s1, s3, 0
	s_add_u32 s5, s2, 0x48
	s_addc_u32 s6, s3, 0
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
	v_mul_hi_i32 v0, 0x28c1979, v1
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 31, v0
	v_ashrrev_i32_e32 v0, 1, v0
	v_add_nc_u32_e32 v4, v0, v2
	v_mad_i64_i32 v[2:3], null, 0x108, v1, s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, 0xc9, v4
	v_add_nc_u32_e32 v4, 0xc9, v4
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 0xc9, v0
.LBB2_3:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_co_u32 v5, vcc_lo, v2, s2
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v3, vcc_lo
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, dev_e@rel32@lo+4
	s_addc_u32 s9, s9, dev_e@rel32@hi+12
	s_add_u32 s8, s2, s8
	s_addc_u32 s9, s3, s9
	global_load_b64 v[5:6], v[5:6], off
	s_load_b64 s[8:9], s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v7, s8, v0
	v_add_nc_u32_e32 v8, s9, v4
	s_add_u32 s8, s5, s2
	s_addc_u32 s9, s6, s3
	s_add_u32 s2, s2, 8
	v_mul_hi_i32 v9, 0x28c1979, v7
	v_mul_hi_i32 v10, 0x28c1979, v8
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s2, 0x48
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v11, 31, v9
	v_ashrrev_i32_e32 v9, 1, v9
	v_lshrrev_b32_e32 v12, 31, v10
	v_lshrrev_b32_e32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v11
	v_add_nc_u32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, 0xc9, v9
	v_mul_lo_u32 v10, 0xc9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v9
	v_sub_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_i32_i24 v9, 0xc9, v8, v7
	v_mad_i64_i32 v[7:8], null, 0x108, v9, s[8:9]
	s_waitcnt vmcnt(0)
	global_store_b64 v[7:8], v[5:6], off
	s_cbranch_scc0 .LBB2_3
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v1, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0x9dd0, v1
	s_or_b32 s7, vcc_lo, s7
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB2_2
.LBB2_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9StreamingP9attribute
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9StreamingP9attribute, .Lfunc_end2-_Z9StreamingP9attribute
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7PhysicsP9attribute   ; -- Begin function _Z7PhysicsP9attribute
	.globl	_Z7PhysicsP9attribute
	.p2align	8
	.type	_Z7PhysicsP9attribute,@function
_Z7PhysicsP9attribute:                  ; @_Z7PhysicsP9attribute
; %bb.0:
	s_load_b32 s4, s[0:1], 0x14
	s_add_u32 s2, s0, 8
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
	v_cmpx_gt_i32_e32 0x9dd1, v4
	s_cbranch_execz .LBB3_7
; %bb.1:                                ; %.lr.ph
	s_load_b32 s5, s[2:3], 0x0
	s_load_b64 s[2:3], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s5, s4
	s_mov_b32 s5, 0
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_4 Depth 2
	v_mul_hi_i32 v1, 0x28c1979, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v1, 1, v1
	v_add_nc_u32_e32 v1, v1, v2
	v_add_nc_u32_e32 v2, 0xffffff37, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, 0xc9, v1
	v_cmp_gt_u32_e64 s0, 0x9c3f, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xad_u32 v1, v1, -1, v4
	v_cmp_gt_u32_e32 vcc_lo, 0xc7, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB3_6
; %bb.3:                                ;   in Loop: Header=BB3_2 Depth=1
	v_mad_u64_u32 v[7:8], null, 0x108, v4, s[2:3]
	v_mov_b32_e32 v1, v0
	v_mov_b32_e32 v2, v0
	v_mov_b32_e32 v3, v0
	s_mov_b64 s[0:1], 0
	global_load_b128 v[13:16], v[7:8], off offset:216
	v_add_co_u32 v5, vcc_lo, 0xd8, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0xf8, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v11, vcc_lo, v7, 0xd8
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v8, vcc_lo
	global_store_b64 v[7:8], v[0:1], off offset:248
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b128 v[7:8], v[13:16], off offset:232
	global_store_b128 v[7:8], v[0:3], off offset:216
.LBB3_4:                                ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_co_u32 v17, vcc_lo, v7, s0
	v_add_co_ci_u32_e32 v18, vcc_lo, s1, v8, vcc_lo
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, dev_e@rel32@lo+4
	s_addc_u32 s9, s9, dev_e@rel32@hi+12
	s_add_u32 s8, s0, s8
	s_addc_u32 s9, s1, s9
	global_load_b64 v[1:2], v[17:18], off offset:72
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x48
	s_waitcnt vmcnt(0)
	global_store_b64 v[17:18], v[1:2], off
	s_clause 0x1
	global_load_b64 v[19:20], v[9:10], off
	global_load_b128 v[13:16], v[5:6], off
	s_load_b64 s[8:9], s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[21:22], s8
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[19:20]
	global_store_b64 v[11:12], v[1:2], off offset:32
	global_load_b64 v[19:20], v[17:18], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[13:14], v[19:20], v[21:22], v[13:14]
	v_cvt_f64_i32_e32 v[19:20], s9
	global_store_b64 v[11:12], v[13:14], off
	global_load_b64 v[17:18], v[17:18], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[15:16], v[17:18], v[19:20], v[15:16]
	global_store_b64 v[5:6], v[15:16], off offset:8
	s_cbranch_scc0 .LBB3_4
; %bb.5:                                ;   in Loop: Header=BB3_2 Depth=1
	v_div_scale_f64 v[7:8], null, v[1:2], v[1:2], v[13:14]
	v_div_scale_f64 v[9:10], null, v[1:2], v[1:2], v[15:16]
	v_div_scale_f64 v[23:24], vcc_lo, v[13:14], v[1:2], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[11:12], v[7:8]
	v_rcp_f64_e32 v[17:18], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[7:8], v[11:12], 1.0
	v_fma_f64 v[21:22], -v[9:10], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[11:12], v[19:20], v[11:12]
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], -v[7:8], v[11:12], 1.0
	v_fma_f64 v[21:22], -v[9:10], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[11:12], v[19:20], v[11:12]
	v_div_scale_f64 v[19:20], s0, v[15:16], v[1:2], v[15:16]
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[21:22], v[23:24], v[11:12]
	v_mul_f64 v[25:26], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], -v[7:8], v[21:22], v[23:24]
	v_fma_f64 v[9:10], -v[9:10], v[25:26], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[7:8], v[7:8], v[11:12], v[21:22]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[9:10], v[9:10], v[17:18], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[7:8], v[7:8], v[1:2], v[13:14]
	v_div_fixup_f64 v[9:10], v[9:10], v[1:2], v[15:16]
	global_store_b128 v[5:6], v[7:10], off
.LBB3_6:                                ; %Flow
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	v_add_nc_u32_e32 v4, s4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0x9dd0, v4
	s_or_b32 s5, vcc_lo, s5
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB3_2
.LBB3_7:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7PhysicsP9attribute
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z7PhysicsP9attribute, .Lfunc_end3-_Z7PhysicsP9attribute
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 756
; NumSgprs: 18
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14MovingBoundaryP9attribute ; -- Begin function _Z14MovingBoundaryP9attribute
	.globl	_Z14MovingBoundaryP9attribute
	.p2align	8
	.type	_Z14MovingBoundaryP9attribute,@function
_Z14MovingBoundaryP9attribute:          ; @_Z14MovingBoundaryP9attribute
; %bb.0:
	s_load_b32 s4, s[0:1], 0x14
	s_add_u32 s2, s0, 8
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0xc9, v4
	s_cbranch_execz .LBB4_5
; %bb.1:                                ; %.lr.ph
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, dev_CS2@rel32@lo+4
	s_addc_u32 s5, s5, dev_CS2@rel32@hi+12
	s_load_b32 s10, s[2:3], 0x0
	s_load_b64 s[6:7], s[0:1], 0x0
	s_load_b64 s[4:5], s[4:5], 0x0
	v_add_nc_u32_e32 v23, 0x9d08, v4
	v_add_nc_u32_e32 v24, 0x9c3f, v4
	v_mov_b32_e32 v9, 0x9999999a
	v_mov_b32_e32 v10, 0x3fb99999
	s_mov_b32 s11, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s10, s10, s8
	v_add_f64 v[5:6], s[4:5], s[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[7:8], s[4:5], v[5:6]
.LBB4_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_3 Depth 2
	v_add_nc_u32_e32 v0, 0x9c3f, v4
	s_mov_b64 s[8:9], 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[11:12], null, 0x108, v0, s[6:7]
	s_clause 0x1
	global_load_b128 v[0:3], v[11:12], off offset:216
	global_load_b64 v[11:12], v[11:12], off offset:248
	s_waitcnt vmcnt(1)
	v_mul_f64 v[13:14], v[2:3], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[0:1], v[0:1], v[13:14]
	v_div_scale_f64 v[15:16], null, v[5:6], v[5:6], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_div_scale_f64 v[19:20], vcc_lo, v[13:14], v[5:6], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[19:20], v[17:18]
	v_fma_f64 v[15:16], -v[15:16], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[21:22]
	v_mad_i64_i32 v[17:18], null, 0x108, v24, s[6:7]
	v_div_fixup_f64 v[13:14], v[15:16], v[5:6], v[13:14]
	v_add_nc_u32_e32 v15, 0x9d08, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[25:26], null, 0x108, v15, s[6:7]
	v_mad_i64_i32 v[15:16], null, 0x108, v23, s[6:7]
	s_waitcnt vmcnt(0)
	s_clause 0x1
	global_store_b64 v[25:26], v[11:12], off offset:248
	global_store_b64 v[25:26], v[9:10], off offset:216
	v_add_co_u32 v19, vcc_lo, 0xf8, v25
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v26, vcc_lo
	v_add_co_u32 v21, vcc_lo, 0xd8, v25
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v26, vcc_lo
.LBB4_3:                                ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b128 v[25:28], v[21:22], off
	global_load_b64 v[29:30], v[19:20], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_e@rel32@lo+4
	s_addc_u32 s1, s1, dev_e@rel32@hi+12
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[31:32], s1
	v_cvt_f64_i32_e32 v[33:34], s0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[35:36], v[27:28], v[31:32]
	v_mul_f64 v[27:28], v[27:28], v[27:28]
	v_mul_f64 v[31:32], v[2:3], v[31:32]
	v_fma_f64 v[35:36], v[25:26], v[33:34], v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[25:26], v[25:26], v[27:28]
	v_fma_f64 v[31:32], v[0:1], v[33:34], v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[27:28], v[35:36], v[35:36]
	v_div_scale_f64 v[33:34], null, s[4:5], s[4:5], v[35:36]
	v_div_scale_f64 v[37:38], null, s[4:5], s[4:5], v[31:32]
	v_mul_f64 v[39:40], v[31:32], v[31:32]
	v_div_scale_f64 v[41:42], null, v[5:6], v[5:6], v[25:26]
	v_div_scale_f64 v[69:70], s1, v[25:26], v[5:6], v[25:26]
	v_div_scale_f64 v[43:44], null, v[7:8], v[7:8], v[27:28]
	v_rcp_f64_e32 v[45:46], v[33:34]
	v_rcp_f64_e32 v[47:48], v[37:38]
	v_div_scale_f64 v[71:72], s2, v[27:28], v[7:8], v[27:28]
	v_div_scale_f64 v[49:50], null, v[7:8], v[7:8], v[39:40]
	v_rcp_f64_e32 v[51:52], v[41:42]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[53:54], v[43:44]
	v_fma_f64 v[55:56], -v[33:34], v[45:46], 1.0
	v_fma_f64 v[59:60], -v[37:38], v[47:48], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[57:58], v[49:50]
	v_fma_f64 v[61:62], -v[41:42], v[51:52], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[63:64], -v[43:44], v[53:54], 1.0
	v_fma_f64 v[45:46], v[45:46], v[55:56], v[45:46]
	v_fma_f64 v[47:48], v[47:48], v[59:60], v[47:48]
	v_fma_f64 v[55:56], -v[49:50], v[57:58], 1.0
	v_fma_f64 v[51:52], v[51:52], v[61:62], v[51:52]
	v_add_co_u32 v61, vcc_lo, v17, s8
	v_add_co_ci_u32_e32 v62, vcc_lo, s9, v18, vcc_lo
	global_load_b64 v[61:62], v[61:62], off
	v_fma_f64 v[53:54], v[53:54], v[63:64], v[53:54]
	v_fma_f64 v[59:60], -v[33:34], v[45:46], 1.0
	v_fma_f64 v[63:64], -v[37:38], v[47:48], 1.0
	v_fma_f64 v[55:56], v[57:58], v[55:56], v[57:58]
	v_div_scale_f64 v[57:58], vcc_lo, v[35:36], s[4:5], v[35:36]
	v_fma_f64 v[65:66], -v[41:42], v[51:52], 1.0
	v_fma_f64 v[67:68], -v[43:44], v[53:54], 1.0
	v_fma_f64 v[45:46], v[45:46], v[59:60], v[45:46]
	v_fma_f64 v[47:48], v[47:48], v[63:64], v[47:48]
	v_div_scale_f64 v[59:60], s0, v[31:32], s[4:5], v[31:32]
	v_fma_f64 v[63:64], -v[49:50], v[55:56], 1.0
	v_fma_f64 v[51:52], v[51:52], v[65:66], v[51:52]
	v_fma_f64 v[53:54], v[53:54], v[67:68], v[53:54]
	v_div_scale_f64 v[67:68], s3, v[39:40], v[7:8], v[39:40]
	v_mul_f64 v[65:66], v[57:58], v[45:46]
	v_mul_f64 v[73:74], v[59:60], v[47:48]
	v_fma_f64 v[55:56], v[55:56], v[63:64], v[55:56]
	v_mul_f64 v[63:64], v[69:70], v[51:52]
	v_mul_f64 v[75:76], v[71:72], v[53:54]
	v_fma_f64 v[33:34], -v[33:34], v[65:66], v[57:58]
	v_fma_f64 v[37:38], -v[37:38], v[73:74], v[59:60]
	v_mul_f64 v[57:58], v[67:68], v[55:56]
	v_fma_f64 v[41:42], -v[41:42], v[63:64], v[69:70]
	v_fma_f64 v[43:44], -v[43:44], v[75:76], v[71:72]
	v_div_fmas_f64 v[33:34], v[33:34], v[45:46], v[65:66]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[45:46], -v[49:50], v[57:58], v[67:68]
	v_div_fixup_f64 v[33:34], v[33:34], s[4:5], v[35:36]
	s_delay_alu instid0(VALU_DEP_4)
	v_div_fmas_f64 v[35:36], v[43:44], v[53:54], v[75:76]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[41:42], v[41:42], v[51:52], v[63:64]
	s_mov_b32 vcc_lo, s0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_w@rel32@lo+4
	s_addc_u32 s1, s1, dev_w@rel32@hi+12
	v_div_fmas_f64 v[37:38], v[37:38], v[47:48], v[73:74]
	s_mov_b32 vcc_lo, s3
	s_add_u32 s0, s8, s0
	v_div_fmas_f64 v[43:44], v[45:46], v[55:56], v[57:58]
	s_addc_u32 s1, s9, s1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[29:30], v[29:30], s[0:1]
	v_add_f64 v[33:34], v[33:34], 1.0
	v_div_fixup_f64 v[27:28], v[35:36], v[7:8], v[27:28]
	v_div_fixup_f64 v[25:26], v[41:42], v[5:6], v[25:26]
	v_div_fixup_f64 v[31:32], v[37:38], s[4:5], v[31:32]
	v_div_fixup_f64 v[35:36], v[43:44], v[7:8], v[39:40]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[33:34], v[27:28]
	v_add_f64 v[31:32], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[27:28], -v[25:26]
	v_add_f64 v[27:28], v[31:32], v[35:36]
	v_mul_f64 v[31:32], s[0:1], v[11:12]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[29:30], v[25:26], v[61:62]
	v_add_f64 v[27:28], v[27:28], -v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[25:26], -v[31:32], v[27:28], v[25:26]
	v_add_co_u32 v27, vcc_lo, v15, s8
	v_add_co_ci_u32_e32 v28, vcc_lo, s9, v16, vcc_lo
	s_add_u32 s8, s8, 8
	s_addc_u32 s9, s9, 0
	s_cmpk_eq_i32 s8, 0x48
	global_store_b64 v[27:28], v[25:26], off
	s_cbranch_scc0 .LBB4_3
; %bb.4:                                ;   in Loop: Header=BB4_2 Depth=1
	v_add_nc_u32_e32 v4, s10, v4
	v_add_nc_u32_e32 v23, s10, v23
	v_add_nc_u32_e32 v24, s10, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0xc8, v4
	s_or_b32 s11, vcc_lo, s11
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB4_2
.LBB4_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14MovingBoundaryP9attribute
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 77
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z14MovingBoundaryP9attribute, .Lfunc_end4-_Z14MovingBoundaryP9attribute
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1292
; NumSgprs: 18
; NumVgprs: 77
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 77
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14StaticBoundaryP9attribute ; -- Begin function _Z14StaticBoundaryP9attribute
	.globl	_Z14StaticBoundaryP9attribute
	.p2align	8
	.type	_Z14StaticBoundaryP9attribute,@function
_Z14StaticBoundaryP9attribute:          ; @_Z14StaticBoundaryP9attribute
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x14
	s_load_b32 s5, s[0:1], 0x8
	s_load_b64 s[6:7], s[0:1], 0x0
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_mul_i32 s5, s5, s0
	v_cmpx_gt_i32_e32 0xc9, v1
	s_cbranch_execz .LBB5_5
; %bb.1:                                ; %.lr.ph
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_CS2@rel32@lo+4
	s_addc_u32 s1, s1, dev_CS2@rel32@hi+12
	v_add_nc_u32_e32 v0, 0xc9, v1
	s_load_b64 s[8:9], s[0:1], 0x0
	v_mov_b32_e32 v18, v1
	s_mov_b32 s13, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], s[8:9], s[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[4:5], s[8:9], v[2:3]
.LBB5_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_3 Depth 2
	v_add_nc_u32_e32 v6, 0xc9, v18
	v_mad_i64_i32 v[8:9], null, 0x108, v0, s[6:7]
	s_mov_b64 s[10:11], 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_i64_i32 v[16:17], null, 0x108, v6, s[6:7]
	v_mad_i64_i32 v[6:7], null, 0x108, v18, s[6:7]
	global_load_b64 v[19:20], v[16:17], off offset:248
	v_add_co_u32 v10, vcc_lo, 0xf8, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v17, vcc_lo
	v_add_co_u32 v12, vcc_lo, 0xf8, v6
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v14, vcc_lo, 0xd8, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v16, vcc_lo, 0xd8, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[19:20], off offset:248
.LBB5_3:                                ;   Parent Loop BB5_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b128 v[19:22], v[14:15], off
	global_load_b128 v[23:26], v[16:17], off
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_e@rel32@lo+4
	s_addc_u32 s1, s1, dev_e@rel32@hi+12
	s_add_u32 s0, s10, s0
	s_addc_u32 s1, s11, s1
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[27:28], s1
	v_cvt_f64_i32_e32 v[29:30], s0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f64 v[31:32], v[21:22], v[27:28]
	v_mul_f64 v[21:22], v[21:22], v[21:22]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[27:28], v[25:26], v[27:28]
	v_mul_f64 v[25:26], v[25:26], v[25:26]
	v_fma_f64 v[31:32], v[19:20], v[29:30], v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[19:20], v[19:20], v[19:20], v[21:22]
	v_fma_f64 v[21:22], v[23:24], v[29:30], v[27:28]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[23:24], v[23:24], v[25:26]
	v_mul_f64 v[27:28], v[31:32], v[31:32]
	v_div_scale_f64 v[29:30], null, s[8:9], s[8:9], v[31:32]
	v_div_scale_f64 v[33:34], null, v[2:3], v[2:3], v[19:20]
	v_div_scale_f64 v[35:36], null, s[8:9], s[8:9], v[21:22]
	v_mul_f64 v[37:38], v[21:22], v[21:22]
	v_div_scale_f64 v[51:52], null, v[2:3], v[2:3], v[23:24]
	v_div_scale_f64 v[73:74], s1, v[21:22], s[8:9], v[21:22]
	v_div_scale_f64 v[39:40], null, v[4:5], v[4:5], v[27:28]
	v_rcp_f64_e32 v[41:42], v[29:30]
	v_rcp_f64_e32 v[25:26], v[33:34]
	v_div_scale_f64 v[75:76], s2, v[27:28], v[4:5], v[27:28]
	v_rcp_f64_e32 v[43:44], v[35:36]
	v_div_scale_f64 v[45:46], null, v[4:5], v[4:5], v[37:38]
	v_rcp_f64_e32 v[61:62], v[51:52]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[47:48], v[39:40]
	v_fma_f64 v[49:50], -v[29:30], v[41:42], 1.0
	v_fma_f64 v[55:56], -v[33:34], v[25:26], 1.0
	v_rcp_f64_e32 v[53:54], v[45:46]
	v_fma_f64 v[57:58], -v[35:36], v[43:44], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[67:68], -v[51:52], v[61:62], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[59:60], -v[39:40], v[47:48], 1.0
	v_fma_f64 v[41:42], v[41:42], v[49:50], v[41:42]
	global_load_b64 v[49:50], v[12:13], off
	v_fma_f64 v[25:26], v[25:26], v[55:56], v[25:26]
	v_fma_f64 v[43:44], v[43:44], v[57:58], v[43:44]
	v_fma_f64 v[55:56], -v[45:46], v[53:54], 1.0
	v_fma_f64 v[61:62], v[61:62], v[67:68], v[61:62]
	v_fma_f64 v[47:48], v[47:48], v[59:60], v[47:48]
	v_add_co_u32 v59, vcc_lo, v8, s10
	v_fma_f64 v[57:58], -v[29:30], v[41:42], 1.0
	v_add_co_ci_u32_e32 v60, vcc_lo, s11, v9, vcc_lo
	s_clause 0x1
	global_load_b64 v[63:64], v[10:11], off
	global_load_b64 v[59:60], v[59:60], off
	v_div_scale_f64 v[65:66], vcc_lo, v[31:32], s[8:9], v[31:32]
	v_fma_f64 v[53:54], v[53:54], v[55:56], v[53:54]
	v_fma_f64 v[69:70], -v[33:34], v[25:26], 1.0
	v_fma_f64 v[71:72], -v[35:36], v[43:44], 1.0
	v_fma_f64 v[55:56], -v[39:40], v[47:48], 1.0
	v_fma_f64 v[41:42], v[41:42], v[57:58], v[41:42]
	v_div_scale_f64 v[57:58], s0, v[19:20], v[2:3], v[19:20]
	v_fma_f64 v[67:68], -v[45:46], v[53:54], 1.0
	v_fma_f64 v[25:26], v[25:26], v[69:70], v[25:26]
	v_fma_f64 v[43:44], v[43:44], v[71:72], v[43:44]
	v_div_scale_f64 v[69:70], s3, v[37:38], v[4:5], v[37:38]
	v_fma_f64 v[71:72], -v[51:52], v[61:62], 1.0
	v_fma_f64 v[47:48], v[47:48], v[55:56], v[47:48]
	v_mul_f64 v[55:56], v[65:66], v[41:42]
	v_fma_f64 v[53:54], v[53:54], v[67:68], v[53:54]
	v_mul_f64 v[77:78], v[57:58], v[25:26]
	v_mul_f64 v[79:80], v[73:74], v[43:44]
	v_fma_f64 v[61:62], v[61:62], v[71:72], v[61:62]
	v_mul_f64 v[67:68], v[75:76], v[47:48]
	v_fma_f64 v[29:30], -v[29:30], v[55:56], v[65:66]
	v_div_scale_f64 v[65:66], s4, v[23:24], v[2:3], v[23:24]
	v_fma_f64 v[33:34], -v[33:34], v[77:78], v[57:58]
	v_fma_f64 v[35:36], -v[35:36], v[79:80], v[73:74]
	v_mul_f64 v[57:58], v[69:70], v[53:54]
	v_fma_f64 v[39:40], -v[39:40], v[67:68], v[75:76]
	v_div_fmas_f64 v[29:30], v[29:30], v[41:42], v[55:56]
	s_mov_b32 vcc_lo, s2
	v_mul_f64 v[41:42], v[65:66], v[61:62]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[45:46], -v[45:46], v[57:58], v[69:70]
	v_div_fixup_f64 v[29:30], v[29:30], s[8:9], v[31:32]
	v_div_fmas_f64 v[31:32], v[39:40], v[47:48], v[67:68]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[25:26], v[33:34], v[25:26], v[77:78]
	s_mov_b32 vcc_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_w@rel32@lo+4
	s_addc_u32 s1, s1, dev_w@rel32@hi+12
	v_div_fmas_f64 v[33:34], v[35:36], v[43:44], v[79:80]
	s_mov_b32 vcc_lo, s3
	v_fma_f64 v[35:36], -v[51:52], v[41:42], v[65:66]
	s_add_u32 s0, s10, s0
	v_div_fmas_f64 v[39:40], v[45:46], v[53:54], v[57:58]
	s_mov_b32 vcc_lo, s4
	s_addc_u32 s1, s11, s1
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_f64 v[29:30], v[29:30], 1.0
	v_div_fixup_f64 v[27:28], v[31:32], v[4:5], v[27:28]
	v_div_fixup_f64 v[19:20], v[25:26], v[2:3], v[19:20]
	v_div_fixup_f64 v[21:22], v[33:34], s[8:9], v[21:22]
	v_div_fmas_f64 v[31:32], v[35:36], v[61:62], v[41:42]
	v_div_fixup_f64 v[25:26], v[39:40], v[4:5], v[37:38]
	v_add_f64 v[27:28], v[29:30], v[27:28]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[21:22], 1.0
	v_div_fixup_f64 v[23:24], v[31:32], v[2:3], v[23:24]
	s_waitcnt vmcnt(2) lgkmcnt(0)
	v_mul_f64 v[29:30], v[49:50], s[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[19:20], v[27:28], -v[19:20]
	v_add_f64 v[21:22], v[21:22], v[25:26]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[25:26], s[0:1], v[63:64]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[29:30], v[19:20], v[59:60]
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[25:26], v[21:22], v[19:20]
	v_add_co_u32 v21, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v22, vcc_lo, s11, v7, vcc_lo
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmpk_eq_i32 s10, 0x48
	global_store_b64 v[21:22], v[19:20], off
	s_cbranch_scc0 .LBB5_3
; %bb.4:                                ;   in Loop: Header=BB5_2 Depth=1
	v_add_nc_u32_e32 v18, s5, v18
	v_add_nc_u32_e32 v0, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0xc8, v18
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB5_2
.LBB5_5:                                ; %Flow122
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e32 0xc8, v1
	s_cbranch_execz .LBB5_11
; %bb.6:                                ; %.lr.ph77
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_CS2@rel32@lo+4
	s_addc_u32 s1, s1, dev_CS2@rel32@hi+12
	v_mul_lo_u32 v0, 0xc9, v1
	s_load_b64 s[8:9], s[0:1], 0x0
	s_add_u32 s10, s6, 0x108
	s_addc_u32 s11, s7, 0
	s_mul_i32 s16, s5, 0xc9
	s_mov_b32 s17, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v24, 0xc8, v0
	v_add_nc_u32_e32 v25, 0xc7, v0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], s[8:9], s[8:9]
	v_mul_f64 v[4:5], s[8:9], v[2:3]
.LBB5_7:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_9 Depth 2
	s_mov_b32 s18, exec_lo
	v_cmpx_lt_i32_e32 0, v1
	s_cbranch_execz .LBB5_10
; %bb.8:                                ;   in Loop: Header=BB5_7 Depth=1
	v_mul_lo_u32 v8, 0xc9, v1
	v_mad_u64_u32 v[10:11], null, 0x108, v25, s[6:7]
	s_mov_b64 s[12:13], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v6, 0xc7, v8
	v_mad_u64_u32 v[26:27], null, 0x108, v8, s[6:7]
	v_add_nc_u32_e32 v12, 0xc8, v8
	v_mad_u64_u32 v[8:9], null, 0x108, v24, s[6:7]
	v_mad_u64_u32 v[22:23], null, 0x108, v6, s[6:7]
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[32:33], null, 0x108, v12, s[6:7]
	v_add_co_u32 v12, vcc_lo, 0xf8, v26
	s_clause 0x1
	global_load_b64 v[28:29], v[26:27], off offset:512
	global_load_b64 v[30:31], v[22:23], off offset:248
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v27, vcc_lo
	v_add_co_u32 v14, vcc_lo, 0xf8, v22
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v23, vcc_lo
	v_add_co_u32 v16, vcc_lo, 0xf8, v32
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v33, vcc_lo
	v_add_co_u32 v18, vcc_lo, 0xd8, v26
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v27, vcc_lo
	v_add_co_u32 v20, vcc_lo, 0xd8, v32
	v_mad_u64_u32 v[6:7], null, 0x108, v0, s[10:11]
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v33, vcc_lo
	v_add_co_u32 v22, vcc_lo, 0xd8, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo
	s_waitcnt vmcnt(1)
	global_store_b64 v[26:27], v[28:29], off offset:248
	s_waitcnt vmcnt(0)
	global_store_b64 v[32:33], v[30:31], off offset:248
.LBB5_9:                                ;   Parent Loop BB5_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b128 v[26:29], v[18:19], off
	global_load_b128 v[30:33], v[18:19], off offset:264
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_e@rel32@lo+4
	s_addc_u32 s1, s1, dev_e@rel32@hi+12
	s_add_u32 s0, s12, s0
	s_addc_u32 s1, s13, s1
	v_add_co_u32 v72, vcc_lo, v6, s12
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_co_ci_u32_e32 v73, vcc_lo, s13, v7, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[34:35], s1
	v_cvt_f64_i32_e32 v[36:37], s0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f64 v[38:39], v[28:29], v[34:35]
	v_mul_f64 v[28:29], v[28:29], v[28:29]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[40:41], v[32:33], v[34:35]
	v_mul_f64 v[32:33], v[32:33], v[32:33]
	v_fma_f64 v[38:39], v[26:27], v[36:37], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[26:27], v[26:27], v[28:29]
	v_fma_f64 v[28:29], v[30:31], v[36:37], v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[30:31], v[30:31], v[30:31], v[32:33]
	v_mul_f64 v[40:41], v[38:39], v[38:39]
	v_div_scale_f64 v[42:43], null, s[8:9], s[8:9], v[38:39]
	v_div_scale_f64 v[44:45], null, v[2:3], v[2:3], v[26:27]
	v_div_scale_f64 v[46:47], null, s[8:9], s[8:9], v[28:29]
	v_mul_f64 v[48:49], v[28:29], v[28:29]
	v_div_scale_f64 v[62:63], null, v[2:3], v[2:3], v[30:31]
	v_div_scale_f64 v[78:79], vcc_lo, v[38:39], s[8:9], v[38:39]
	v_div_scale_f64 v[86:87], s1, v[28:29], s[8:9], v[28:29]
	v_div_scale_f64 v[50:51], null, v[4:5], v[4:5], v[40:41]
	v_rcp_f64_e32 v[52:53], v[42:43]
	v_rcp_f64_e32 v[32:33], v[44:45]
	v_div_scale_f64 v[88:89], s2, v[40:41], v[4:5], v[40:41]
	v_rcp_f64_e32 v[54:55], v[46:47]
	v_div_scale_f64 v[56:57], null, v[4:5], v[4:5], v[48:49]
	v_rcp_f64_e32 v[74:75], v[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[58:59], v[50:51]
	v_fma_f64 v[60:61], -v[42:43], v[52:53], 1.0
	v_fma_f64 v[66:67], -v[44:45], v[32:33], 1.0
	v_rcp_f64_e32 v[64:65], v[56:57]
	v_fma_f64 v[68:69], -v[46:47], v[54:55], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[80:81], -v[62:63], v[74:75], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[70:71], -v[50:51], v[58:59], 1.0
	v_fma_f64 v[52:53], v[52:53], v[60:61], v[52:53]
	global_load_b64 v[60:61], v[12:13], off
	v_fma_f64 v[32:33], v[32:33], v[66:67], v[32:33]
	v_fma_f64 v[54:55], v[54:55], v[68:69], v[54:55]
	v_fma_f64 v[66:67], -v[56:57], v[64:65], 1.0
	v_fma_f64 v[74:75], v[74:75], v[80:81], v[74:75]
	v_fma_f64 v[58:59], v[58:59], v[70:71], v[58:59]
	s_clause 0x1
	global_load_b64 v[70:71], v[12:13], off offset:264
	global_load_b64 v[76:77], v[72:73], off
	v_fma_f64 v[68:69], -v[42:43], v[52:53], 1.0
	v_fma_f64 v[82:83], -v[44:45], v[32:33], 1.0
	v_fma_f64 v[84:85], -v[46:47], v[54:55], 1.0
	v_fma_f64 v[64:65], v[64:65], v[66:67], v[64:65]
	v_fma_f64 v[66:67], -v[50:51], v[58:59], 1.0
	v_fma_f64 v[52:53], v[52:53], v[68:69], v[52:53]
	v_div_scale_f64 v[68:69], s0, v[26:27], v[2:3], v[26:27]
	v_fma_f64 v[32:33], v[32:33], v[82:83], v[32:33]
	v_fma_f64 v[54:55], v[54:55], v[84:85], v[54:55]
	v_fma_f64 v[80:81], -v[56:57], v[64:65], 1.0
	v_div_scale_f64 v[82:83], s3, v[48:49], v[4:5], v[48:49]
	v_fma_f64 v[84:85], -v[62:63], v[74:75], 1.0
	v_fma_f64 v[58:59], v[58:59], v[66:67], v[58:59]
	v_mul_f64 v[66:67], v[78:79], v[52:53]
	v_mul_f64 v[90:91], v[68:69], v[32:33]
	v_mul_f64 v[92:93], v[86:87], v[54:55]
	v_fma_f64 v[64:65], v[64:65], v[80:81], v[64:65]
	v_fma_f64 v[74:75], v[74:75], v[84:85], v[74:75]
	v_mul_f64 v[80:81], v[88:89], v[58:59]
	v_fma_f64 v[42:43], -v[42:43], v[66:67], v[78:79]
	v_div_scale_f64 v[78:79], s4, v[30:31], v[2:3], v[30:31]
	v_fma_f64 v[44:45], -v[44:45], v[90:91], v[68:69]
	v_fma_f64 v[46:47], -v[46:47], v[92:93], v[86:87]
	v_mul_f64 v[68:69], v[82:83], v[64:65]
	v_fma_f64 v[50:51], -v[50:51], v[80:81], v[88:89]
	v_div_fmas_f64 v[42:43], v[42:43], v[52:53], v[66:67]
	s_mov_b32 vcc_lo, s2
	v_mul_f64 v[52:53], v[78:79], v[74:75]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[56:57], -v[56:57], v[68:69], v[82:83]
	v_div_fixup_f64 v[38:39], v[42:43], s[8:9], v[38:39]
	v_div_fmas_f64 v[42:43], v[50:51], v[58:59], v[80:81]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[32:33], v[44:45], v[32:33], v[90:91]
	s_mov_b32 vcc_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dev_w@rel32@lo+4
	s_addc_u32 s1, s1, dev_w@rel32@hi+12
	v_div_fmas_f64 v[44:45], v[46:47], v[54:55], v[92:93]
	s_mov_b32 vcc_lo, s3
	v_fma_f64 v[46:47], -v[62:63], v[52:53], v[78:79]
	v_div_fmas_f64 v[50:51], v[56:57], v[64:65], v[68:69]
	s_mov_b32 vcc_lo, s4
	s_add_u32 s0, s12, s0
	s_addc_u32 s1, s13, s1
	s_load_b64 s[14:15], s[0:1], 0x0
	v_add_f64 v[38:39], v[38:39], 1.0
	v_div_fixup_f64 v[40:41], v[42:43], v[4:5], v[40:41]
	v_div_fixup_f64 v[26:27], v[32:33], v[2:3], v[26:27]
	v_div_fixup_f64 v[28:29], v[44:45], s[8:9], v[28:29]
	v_div_fmas_f64 v[42:43], v[46:47], v[74:75], v[52:53]
	v_div_fixup_f64 v[32:33], v[50:51], v[4:5], v[48:49]
	v_add_f64 v[38:39], v[38:39], v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], 1.0
	v_div_fixup_f64 v[30:31], v[42:43], v[2:3], v[30:31]
	s_waitcnt vmcnt(2) lgkmcnt(0)
	v_mul_f64 v[40:41], v[60:61], s[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[38:39], -v[26:27]
	v_add_f64 v[28:29], v[28:29], v[32:33]
	v_add_co_u32 v32, vcc_lo, v10, s12
	v_add_co_ci_u32_e32 v33, vcc_lo, s13, v11, vcc_lo
	global_load_b64 v[38:39], v[32:33], off
	s_waitcnt vmcnt(2)
	v_mul_f64 v[32:33], s[14:15], v[70:71]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[26:27], v[40:41], v[26:27], v[76:77]
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[26:27], -v[32:33], v[28:29], v[26:27]
	global_store_b64 v[72:73], v[26:27], off offset:-264
	s_clause 0x1
	global_load_b128 v[26:29], v[20:21], off
	global_load_b128 v[30:33], v[22:23], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[40:41], v[28:29], v[34:35]
	v_mul_f64 v[28:29], v[28:29], v[28:29]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[34:35], v[32:33], v[34:35]
	v_mul_f64 v[32:33], v[32:33], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], v[26:27], v[36:37], v[40:41]
	v_fma_f64 v[26:27], v[26:27], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[28:29], v[30:31], v[36:37], v[34:35]
	v_fma_f64 v[30:31], v[30:31], v[30:31], v[32:33]
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f64 v[34:35], v[40:41], v[40:41]
	v_div_scale_f64 v[36:37], null, s[8:9], s[8:9], v[40:41]
	v_div_scale_f64 v[42:43], null, v[2:3], v[2:3], v[26:27]
	v_div_scale_f64 v[44:45], null, s[8:9], s[8:9], v[28:29]
	v_mul_f64 v[46:47], v[28:29], v[28:29]
	v_div_scale_f64 v[60:61], null, v[2:3], v[2:3], v[30:31]
	v_div_scale_f64 v[72:73], vcc_lo, v[40:41], s[8:9], v[40:41]
	v_div_scale_f64 v[80:81], s1, v[28:29], s[8:9], v[28:29]
	v_div_scale_f64 v[48:49], null, v[4:5], v[4:5], v[34:35]
	v_rcp_f64_e32 v[50:51], v[36:37]
	v_rcp_f64_e32 v[32:33], v[42:43]
	v_div_scale_f64 v[82:83], s2, v[34:35], v[4:5], v[34:35]
	v_rcp_f64_e32 v[52:53], v[44:45]
	v_div_scale_f64 v[54:55], null, v[4:5], v[4:5], v[46:47]
	v_rcp_f64_e32 v[70:71], v[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[56:57], v[48:49]
	v_fma_f64 v[58:59], -v[36:37], v[50:51], 1.0
	v_fma_f64 v[64:65], -v[42:43], v[32:33], 1.0
	v_rcp_f64_e32 v[62:63], v[54:55]
	v_fma_f64 v[66:67], -v[44:45], v[52:53], 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f64 v[74:75], -v[60:61], v[70:71], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[68:69], -v[48:49], v[56:57], 1.0
	v_fma_f64 v[50:51], v[50:51], v[58:59], v[50:51]
	global_load_b64 v[58:59], v[16:17], off
	v_fma_f64 v[32:33], v[32:33], v[64:65], v[32:33]
	v_fma_f64 v[52:53], v[52:53], v[66:67], v[52:53]
	v_fma_f64 v[64:65], -v[54:55], v[62:63], 1.0
	v_fma_f64 v[70:71], v[70:71], v[74:75], v[70:71]
	v_fma_f64 v[56:57], v[56:57], v[68:69], v[56:57]
	global_load_b64 v[68:69], v[14:15], off
	v_fma_f64 v[66:67], -v[36:37], v[50:51], 1.0
	v_fma_f64 v[76:77], -v[42:43], v[32:33], 1.0
	v_fma_f64 v[78:79], -v[44:45], v[52:53], 1.0
	v_fma_f64 v[62:63], v[62:63], v[64:65], v[62:63]
	v_fma_f64 v[64:65], -v[48:49], v[56:57], 1.0
	v_fma_f64 v[50:51], v[50:51], v[66:67], v[50:51]
	v_div_scale_f64 v[66:67], s0, v[26:27], v[2:3], v[26:27]
	v_fma_f64 v[32:33], v[32:33], v[76:77], v[32:33]
	v_fma_f64 v[52:53], v[52:53], v[78:79], v[52:53]
	v_fma_f64 v[74:75], -v[54:55], v[62:63], 1.0
	v_div_scale_f64 v[76:77], s3, v[46:47], v[4:5], v[46:47]
	v_fma_f64 v[78:79], -v[60:61], v[70:71], 1.0
	v_fma_f64 v[56:57], v[56:57], v[64:65], v[56:57]
	v_mul_f64 v[64:65], v[72:73], v[50:51]
	v_mul_f64 v[84:85], v[66:67], v[32:33]
	v_mul_f64 v[86:87], v[80:81], v[52:53]
	v_fma_f64 v[62:63], v[62:63], v[74:75], v[62:63]
	v_fma_f64 v[70:71], v[70:71], v[78:79], v[70:71]
	v_mul_f64 v[74:75], v[82:83], v[56:57]
	v_fma_f64 v[36:37], -v[36:37], v[64:65], v[72:73]
	v_div_scale_f64 v[72:73], s4, v[30:31], v[2:3], v[30:31]
	v_fma_f64 v[42:43], -v[42:43], v[84:85], v[66:67]
	v_fma_f64 v[44:45], -v[44:45], v[86:87], v[80:81]
	v_mul_f64 v[66:67], v[76:77], v[62:63]
	v_fma_f64 v[48:49], -v[48:49], v[74:75], v[82:83]
	v_div_fmas_f64 v[36:37], v[36:37], v[50:51], v[64:65]
	s_mov_b32 vcc_lo, s2
	v_mul_f64 v[50:51], v[72:73], v[70:71]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[54:55], -v[54:55], v[66:67], v[76:77]
	v_div_fixup_f64 v[36:37], v[36:37], s[8:9], v[40:41]
	v_div_fmas_f64 v[40:41], v[48:49], v[56:57], v[74:75]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[32:33], v[42:43], v[32:33], v[84:85]
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f64 v[42:43], v[44:45], v[52:53], v[86:87]
	s_mov_b32 vcc_lo, s3
	v_fma_f64 v[44:45], -v[60:61], v[50:51], v[72:73]
	v_div_fmas_f64 v[48:49], v[54:55], v[62:63], v[66:67]
	s_mov_b32 vcc_lo, s4
	v_add_f64 v[36:37], v[36:37], 1.0
	v_div_fixup_f64 v[34:35], v[40:41], v[4:5], v[34:35]
	v_div_fixup_f64 v[26:27], v[32:33], v[2:3], v[26:27]
	v_div_fixup_f64 v[28:29], v[42:43], s[8:9], v[28:29]
	v_div_fmas_f64 v[40:41], v[44:45], v[70:71], v[50:51]
	v_div_fixup_f64 v[32:33], v[48:49], v[4:5], v[46:47]
	v_add_f64 v[34:35], v[36:37], v[34:35]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], 1.0
	v_div_fixup_f64 v[30:31], v[40:41], v[2:3], v[30:31]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[36:37], s[14:15], v[58:59]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[34:35], -v[26:27]
	v_add_f64 v[28:29], v[28:29], v[32:33]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[32:33], s[14:15], v[68:69]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[36:37], v[26:27], v[38:39]
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[26:27], -v[32:33], v[28:29], v[26:27]
	v_add_co_u32 v28, vcc_lo, v8, s12
	v_add_co_ci_u32_e32 v29, vcc_lo, s13, v9, vcc_lo
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmpk_lg_i32 s12, 0x48
	global_store_b64 v[28:29], v[26:27], off
	s_cbranch_scc1 .LBB5_9
.LBB5_10:                               ; %Flow118
                                        ;   in Loop: Header=BB5_7 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	v_add_nc_u32_e32 v1, s5, v1
	v_add_nc_u32_e32 v0, s16, v0
	v_add_nc_u32_e32 v24, s16, v24
	v_add_nc_u32_e32 v25, s16, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0xc7, v1
	s_or_b32 s17, vcc_lo, s17
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB5_7
.LBB5_11:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14StaticBoundaryP9attribute
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 94
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z14StaticBoundaryP9attribute, .Lfunc_end5-_Z14StaticBoundaryP9attribute
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3416
; NumSgprs: 21
; NumVgprs: 94
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 94
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5ErrorP9attributePd   ; -- Begin function _Z5ErrorP9attributePd
	.globl	_Z5ErrorP9attributePd
	.p2align	8
	.type	_Z5ErrorP9attributePd,@function
_Z5ErrorP9attributePd:                  ; @_Z5ErrorP9attributePd
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x1c
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v8, v0
	v_dual_mov_b32 v12, v9 :: v_dual_lshlrev_b32 v7, 4, v0
	v_mov_b32_e32 v10, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v2, v4
	s_mov_b32 s2, 0
	ds_store_b128 v7, v[9:12]
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[5:6], null, 0x108, v0, s[4:5]
	s_and_b32 s1, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s3, s1, 0x108
	v_add_co_u32 v5, vcc_lo, 0xd8, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB6_1:                                ; =>This Inner Loop Header: Depth=1
	v_and_b32_e32 v9, 0xffff, v8
	v_add_nc_u16 v10, v8, 0xff37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_u32_u24_e32 v9, 0xa307, v9
	v_cmp_gt_u16_e64 s0, 0x9c3f, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v9, 23, v9
	v_mul_lo_u16 v9, 0xc9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u16 v9, v8, v9
	v_and_b32_e32 v9, 0xffff, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, -1, v9
	v_cmp_gt_u32_e32 vcc_lo, 0xc7, v9
	s_and_b32 s4, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s4
	s_cbranch_execz .LBB6_3
; %bb.2:                                ;   in Loop: Header=BB6_1 Depth=1
	s_clause 0x1
	global_load_b128 v[9:12], v[5:6], off offset:16
	global_load_b128 v[13:16], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	v_add_f64 v[9:10], v[13:14], -v[9:10]
	v_mul_f64 v[15:16], v[15:16], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[11:12], v[11:12]
	v_fma_f64 v[9:10], v[9:10], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[13:14], v[13:14], v[15:16]
	v_add_f64 v[1:2], v[1:2], v[9:10]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[3:4], v[11:12], v[3:4]
	ds_store_b128 v7, v[1:4]
.LBB6_3:                                ;   in Loop: Header=BB6_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v8, s1, v8
	v_add_co_u32 v5, s0, v5, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
	v_cmp_lt_u32_e32 vcc_lo, 0x9dd0, v8
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB6_1
; %bb.4:
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_lt_u32 s1, 2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB6_9
; %bb.5:                                ; %.lr.ph.preheader
	s_lshr_b32 s0, s1, 1
.LBB6_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB6_8
; %bb.7:                                ;   in Loop: Header=BB6_6 Depth=1
	v_lshl_add_u32 v1, s0, 4, v7
	ds_load_b128 v[1:4], v1
	ds_load_b128 v[8:11], v7
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	v_add_f64 v[3:4], v[3:4], v[10:11]
	ds_store_b128 v7, v[1:4]
.LBB6_8:                                ;   in Loop: Header=BB6_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s0, 1
	s_cmp_gt_u32 s0, 1
	s_mov_b32 s0, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB6_6
.LBB6_9:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB6_11
; %bb.10:
	ds_load_b128 v[0:3], v7
	s_mov_b32 s0, 0xd9d7bdbb
	s_mov_b32 s1, 0x3ddb7cdf
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[2:3], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 8, v2
	v_ldexp_f64 v[0:1], v[0:1], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rsq_f64_e32 v[2:3], v[0:1]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[4:5], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
	v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[6:7], v[2:3], v[4:5]
	v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
	v_ldexp_f64 v[2:3], v[2:3], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v1, v3, v1
	v_cndmask_b32_e32 v0, v2, v0, vcc_lo
	global_store_b64 v4, v[0:1], s[6:7]
.LBB6_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5ErrorP9attributePd
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z5ErrorP9attributePd, .Lfunc_end6-_Z5ErrorP9attributePd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 900
; NumSgprs: 10
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5WatchP9attributePd   ; -- Begin function _Z5WatchP9attributePd
	.globl	_Z5WatchP9attributePd
	.p2align	8
	.type	_Z5WatchP9attributePd,@function
_Z5WatchP9attributePd:                  ; @_Z5WatchP9attributePd
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x1c
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v10, 2, v0
	v_mov_b32_e32 v3, 0
	v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v7, 3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v2, v1
	v_or_b32_e32 v8, 0x1000, v10
	v_mov_b32_e32 v9, v0
	s_mov_b32 s2, 0
	ds_store_b32 v10, v1 offset:4096
	ds_store_b64 v7, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[5:6], null, 0x108, v0, s[4:5]
	s_and_b32 s1, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s3, s1, 0x108
	v_add_co_u32 v5, vcc_lo, 0xf8, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
.LBB7_1:                                ; =>This Inner Loop Header: Depth=1
	v_and_b32_e32 v2, 0xffff, v9
	v_add_nc_u16 v10, v9, 0xff37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_u32_u24_e32 v2, 0xa307, v2
	v_cmp_gt_u16_e64 s0, 0x9c3f, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 23, v2
	v_mul_lo_u16 v2, 0xc9, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u16 v2, v9, v2
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, -1, v2
	v_cmp_gt_u32_e32 vcc_lo, 0xc7, v2
	s_and_b32 s4, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s4
	s_cbranch_execz .LBB7_3
; %bb.2:                                ;   in Loop: Header=BB7_1 Depth=1
	global_load_b64 v[10:11], v[5:6], off
	v_add_nc_u32_e32 v1, 1, v1
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[10:11], v[3:4]
	ds_store_b32 v8, v1
	ds_store_b64 v7, v[3:4]
.LBB7_3:                                ;   in Loop: Header=BB7_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v9, s1, v9
	v_add_co_u32 v5, s0, v5, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
	v_cmp_lt_u32_e32 vcc_lo, 0x9dd0, v9
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB7_1
; %bb.4:
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_lt_u32 s1, 2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB7_9
; %bb.5:                                ; %.lr.ph.preheader
	s_lshr_b32 s0, s1, 1
.LBB7_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB7_8
; %bb.7:                                ;   in Loop: Header=BB7_6 Depth=1
	v_lshl_add_u32 v1, s0, 2, v8
	v_lshl_add_u32 v2, s0, 3, v7
	ds_load_b32 v5, v1
	ds_load_b64 v[1:2], v2
	ds_load_b64 v[3:4], v7
	ds_load_b32 v6, v8
	s_waitcnt lgkmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v6, v5
	ds_store_b64 v7, v[1:2]
	ds_store_b32 v8, v3
.LBB7_8:                                ;   in Loop: Header=BB7_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_lshr_b32 s1, s0, 1
	s_cmp_gt_u32 s0, 1
	s_mov_b32 s0, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB7_6
.LBB7_9:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB7_11
; %bb.10:
	ds_load_b32 v0, v8
	ds_load_b64 v[2:3], v7
	s_mov_b32 s0, 0xd9d7bdbb
	s_mov_b32 s1, 0x3ddb7cdf
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_i32_e32 v[0:1], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], s[0:1]
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_div_scale_f64 v[8:9], vcc_lo, v[2:3], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[8:9], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
	v_div_fixup_f64 v[0:1], v[4:5], v[0:1], v[2:3]
	v_mov_b32_e32 v2, 0
	global_store_b64 v2, v[0:1], s[6:7]
.LBB7_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5WatchP9attributePd
		.amdhsa_group_segment_fixed_size 6144
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z5WatchP9attributePd, .Lfunc_end7-_Z5WatchP9attributePd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 708
; NumSgprs: 10
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 6144 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z4CvorP9attribute      ; -- Begin function _Z4CvorP9attribute
	.globl	_Z4CvorP9attribute
	.p2align	8
	.type	_Z4CvorP9attribute,@function
_Z4CvorP9attribute:                     ; @_Z4CvorP9attribute
; %bb.0:
	s_load_b32 s4, s[0:1], 0x14
	s_add_u32 s2, s0, 8
	s_addc_u32 s3, s1, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmpx_gt_i32_e32 0x9dd1, v1
	s_cbranch_execz .LBB8_5
; %bb.1:                                ; %.lr.ph
	s_load_b32 s5, s[2:3], 0x0
	s_load_b64 s[2:3], s[0:1], 0x0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s5, s4
	s_add_u32 s4, s2, 0x110
	s_addc_u32 s5, s3, 0
	s_add_u32 s6, s2, 8
	s_addc_u32 s7, s3, 0
.LBB8_2:                                ; =>This Inner Loop Header: Depth=1
	v_mul_hi_i32 v0, 0x28c1979, v1
	v_add_nc_u32_e32 v3, 0xffffff37, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_u32_e64 s0, 0x9c3f, v3
	v_lshrrev_b32_e32 v2, 31, v0
	v_ashrrev_i32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_lo_u32 v0, 0xc9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v1, v0
	v_add_nc_u32_e32 v0, -1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, 0xc7, v0
	s_and_b32 s9, s0, vcc_lo
	s_and_saveexec_b32 s0, s9
	s_cbranch_execz .LBB8_4
; %bb.3:                                ;   in Loop: Header=BB8_2 Depth=1
	v_and_b32_e32 v3, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_u32_u24_e32 v3, 0xa307, v3
	v_lshrrev_b32_e32 v3, 23, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u16 v3, 0xc9, v3
	v_sub_nc_u16 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, 0xffff, v3
	v_sub_nc_u32_e32 v9, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v3, v2, v9
	v_add_co_u32 v2, s9, v2, v9
	v_add_nc_u32_e32 v0, v9, v0
	v_add_co_ci_u32_e64 v11, null, 0, 0, s9
	v_add_nc_u32_e32 v5, 0xc9, v3
	v_add_nc_u32_e32 v7, 0xffffff37, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[9:10], null, 0x108, v0, s[6:7]
	v_mad_u64_u32 v[3:4], null, 0x108, v5, s[2:3]
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[5:6], null, 0x108, v7, s[2:3]
	v_mad_u64_u32 v[7:8], null, 0x108, v2, s[4:5]
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off offset:216
	global_load_b64 v[5:6], v[5:6], off offset:216
	v_mad_u32_u24 v8, 0x108, v11, v8
	s_clause 0x1
	global_load_b64 v[7:8], v[7:8], off offset:216
	global_load_b64 v[9:10], v[9:10], off offset:216
	s_waitcnt vmcnt(2)
	v_add_f64 v[2:3], v[3:4], -v[5:6]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[7:8], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], 0.5
	v_fma_f64 v[2:3], v[4:5], 0.5, -v[2:3]
	v_mad_u64_u32 v[4:5], null, 0x108, v1, s[2:3]
	global_store_b64 v[4:5], v[2:3], off offset:256
.LBB8_4:                                ;   in Loop: Header=BB8_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v1, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0x9dd0, v1
	s_or_b32 s8, vcc_lo, s8
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB8_2
.LBB8_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4CvorP9attribute
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z4CvorP9attribute, .Lfunc_end8-_Z4CvorP9attribute
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 528
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	dev_CS2                 ; @dev_CS2
	.type	dev_CS2,@object
	.section	.bss,"aw",@nobits
	.globl	dev_CS2
	.p2align	3, 0x0
dev_CS2:
	.zero	8
	.size	dev_CS2, 8

	.protected	dev_NU                  ; @dev_NU
	.type	dev_NU,@object
	.globl	dev_NU
	.p2align	3, 0x0
dev_NU:
	.zero	8
	.size	dev_NU, 8

	.protected	dev_TAO                 ; @dev_TAO
	.type	dev_TAO,@object
	.globl	dev_TAO
	.p2align	3, 0x0
dev_TAO:
	.zero	8
	.size	dev_TAO, 8

	.protected	dev_w                   ; @dev_w
	.type	dev_w,@object
	.globl	dev_w
	.p2align	4, 0x0
dev_w:
	.zero	72
	.size	dev_w, 72

	.protected	dev_e                   ; @dev_e
	.type	dev_e,@object
	.globl	dev_e
	.p2align	4, 0x0
dev_e:
	.zero	72
	.size	dev_e, 72

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym dev_CS2
	.addrsig_sym dev_NU
	.addrsig_sym dev_TAO
	.addrsig_sym dev_w
	.addrsig_sym dev_e
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9CollisionP9attribute
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9CollisionP9attribute.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     46
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12PreStreamingP9attribute
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12PreStreamingP9attribute.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9StreamingP9attribute
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9StreamingP9attribute.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7PhysicsP9attribute
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7PhysicsP9attribute.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14MovingBoundaryP9attribute
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14MovingBoundaryP9attribute.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     77
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14StaticBoundaryP9attribute
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z14StaticBoundaryP9attribute.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     94
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5ErrorP9attributePd
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z5ErrorP9attributePd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 6144
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5WatchP9attributePd
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z5WatchP9attributePd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4CvorP9attribute
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4CvorP9attribute.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
