
#ifndef block_size_x
#define block_size_x 128
#endif

#ifndef threshold
#define threshold 3
#endif



/*
 * Helper function that does the reduction step of the algorithm
 *
 * This function reduces the values in a thread block to a single value
 *
 */
__device__ __forceinline__ void reduce_min_num(int *sh_min, int *sh_sum, int lmin, int lnum, int ti) {
    sh_min[ti] = lmin;
    sh_sum[ti] = lnum;
    __syncthreads();
    #pragma unroll
    for (unsigned int s=block_size_x/2; s>0; s>>=1) {
        if (ti < s) {
            int self = sh_min[ti];
            int other = sh_min[ti+s];
            if (other >= threshold) {
                if (self < threshold || other < self) {
                    sh_min[ti] = other;
                }
            }
            sh_sum[ti] += sh_sum[ti + s];
        }
        __syncthreads();
    }
}





/*
 * This kernel recomputes the degree of each node in the graph and computes
 * the minimum degree of all nodes with at least one edge.
 *
 * output arguments:
 *
 *  minimum an array containing a per-thread block minimum degree
 *
 *  num_nodes will contain the per-thread block sum of the number of nodes
 *      with at least 'threshold' edges
 *
 *  degrees contains the degree of all nodes and is updated with the current degree
 *
 * input arguments:
 *
 *  row_idx is the index of the node
 *  col_idx is the index of the node to which this node has an edge, this index
 *      can be -1 if the edge has been removed
 *
 *  prefix_sum contains the start index of each row, because elements can be removed
 *          this subtracting two consecutive numbers no longer indicates the degree
 *
 *  n is the number of nodes in the graph
 */
__global__ void minimum_degree(int *minimum, int *num_nodes, int *degrees, int *row_idx, int *col_idx, int *prefix_sum, int n) {

    int ti = threadIdx.x;
    int i = blockIdx.x * block_size_x + ti;

    int degree = 0;

    if (i<n) {

        
        //obtain indices for reading col_idx
        int start = 0;
        if (i>0) {
            start = prefix_sum[i-1];
        }
        int end = prefix_sum[i];

        int max_degree = degrees[i];

        //get the degree of this node
        for (int k=start; k<end && degree < max_degree; k++) {
            if (col_idx[k] != -1) {
                degree++;
            }
        }

        //update degrees array
        degrees[i] = degree;

    }

    //start the reduce
    //get the minimum value larger than 0
    //and the total number of nodes with degree >= theshold (at least 'threshold' edges)
    __shared__ int sh_min[block_size_x];
    __shared__ int sh_sum[block_size_x];
    int lnum = 0;
    if (degree >= threshold) {
        lnum = 1;
    }
    reduce_min_num(sh_min, sh_sum, degree, lnum, ti);

    //write output
    if (ti == 0) {
        minimum[blockIdx.x] = sh_min[0];
        num_nodes[blockIdx.x] = sh_sum[0];
    }

}





/*
 * Helper kernel to combine per-thread block results into single values
 *
 * call with 1 thread block, block_size_x should be sufficiently large
 */
__global__ void combine_blocked_min_num(int *minimum, int *num_nodes, int n) {
    int ti = threadIdx.x;

    __shared__ int sh_min[block_size_x];
    __shared__ int sh_sum[block_size_x];

    int lmin = 0;
    int lnum = 0;

    if (ti < n) {
        lmin = minimum[ti];
        lnum = num_nodes[ti];
    }

    reduce_min_num(sh_min, sh_sum, lmin, lnum, ti);

    if (ti==0) {
        minimum[0] = sh_min[0];
        num_nodes[0] = sh_sum[0];
    }

}

	.file	"tmpxft_0029dac2_00000000-6_minimum_degree.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i
	.type	_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i, @function
_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z14minimum_degreePiS_S_S_S_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i, .-_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i
	.globl	_Z14minimum_degreePiS_S_S_S_S_i
	.type	_Z14minimum_degreePiS_S_S_S_S_i, @function
_Z14minimum_degreePiS_S_S_S_S_i:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z14minimum_degreePiS_S_S_S_S_iPiS_S_S_S_S_i
	.cfi_endproc
.LFE2034:
	.size	_Z14minimum_degreePiS_S_S_S_S_i, .-_Z14minimum_degreePiS_S_S_S_S_i
	.globl	_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i
	.type	_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i, @function
_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z23combine_blocked_min_numPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i, .-_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i
	.globl	_Z23combine_blocked_min_numPiS_i
	.type	_Z23combine_blocked_min_numPiS_i, @function
_Z23combine_blocked_min_numPiS_i:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z23combine_blocked_min_numPiS_iPiS_i
	.cfi_endproc
.LFE2036:
	.size	_Z23combine_blocked_min_numPiS_i, .-_Z23combine_blocked_min_numPiS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z23combine_blocked_min_numPiS_i"
.LC1:
	.string	"_Z14minimum_degreePiS_S_S_S_S_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z23combine_blocked_min_numPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14minimum_degreePiS_S_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>

#ifndef block_size_x
#define block_size_x 128
#endif

#ifndef threshold
#define threshold 3
#endif



/*
 * Helper function that does the reduction step of the algorithm
 *
 * This function reduces the values in a thread block to a single value
 *
 */
__device__ __forceinline__ void reduce_min_num(int *sh_min, int *sh_sum, int lmin, int lnum, int ti) {
    sh_min[ti] = lmin;
    sh_sum[ti] = lnum;
    __syncthreads();
    #pragma unroll
    for (unsigned int s=block_size_x/2; s>0; s>>=1) {
        if (ti < s) {
            int self = sh_min[ti];
            int other = sh_min[ti+s];
            if (other >= threshold) {
                if (self < threshold || other < self) {
                    sh_min[ti] = other;
                }
            }
            sh_sum[ti] += sh_sum[ti + s];
        }
        __syncthreads();
    }
}





/*
 * This kernel recomputes the degree of each node in the graph and computes
 * the minimum degree of all nodes with at least one edge.
 *
 * output arguments:
 *
 *  minimum an array containing a per-thread block minimum degree
 *
 *  num_nodes will contain the per-thread block sum of the number of nodes
 *      with at least 'threshold' edges
 *
 *  degrees contains the degree of all nodes and is updated with the current degree
 *
 * input arguments:
 *
 *  row_idx is the index of the node
 *  col_idx is the index of the node to which this node has an edge, this index
 *      can be -1 if the edge has been removed
 *
 *  prefix_sum contains the start index of each row, because elements can be removed
 *          this subtracting two consecutive numbers no longer indicates the degree
 *
 *  n is the number of nodes in the graph
 */
__global__ void minimum_degree(int *minimum, int *num_nodes, int *degrees, int *row_idx, int *col_idx, int *prefix_sum, int n) {

    int ti = threadIdx.x;
    int i = blockIdx.x * block_size_x + ti;

    int degree = 0;

    if (i<n) {

        
        //obtain indices for reading col_idx
        int start = 0;
        if (i>0) {
            start = prefix_sum[i-1];
        }
        int end = prefix_sum[i];

        int max_degree = degrees[i];

        //get the degree of this node
        for (int k=start; k<end && degree < max_degree; k++) {
            if (col_idx[k] != -1) {
                degree++;
            }
        }

        //update degrees array
        degrees[i] = degree;

    }

    //start the reduce
    //get the minimum value larger than 0
    //and the total number of nodes with degree >= theshold (at least 'threshold' edges)
    __shared__ int sh_min[block_size_x];
    __shared__ int sh_sum[block_size_x];
    int lnum = 0;
    if (degree >= threshold) {
        lnum = 1;
    }
    reduce_min_num(sh_min, sh_sum, degree, lnum, ti);

    //write output
    if (ti == 0) {
        minimum[blockIdx.x] = sh_min[0];
        num_nodes[blockIdx.x] = sh_sum[0];
    }

}





/*
 * Helper kernel to combine per-thread block results into single values
 *
 * call with 1 thread block, block_size_x should be sufficiently large
 */
__global__ void combine_blocked_min_num(int *minimum, int *num_nodes, int n) {
    int ti = threadIdx.x;

    __shared__ int sh_min[block_size_x];
    __shared__ int sh_sum[block_size_x];

    int lmin = 0;
    int lnum = 0;

    if (ti < n) {
        lmin = minimum[ti];
        lnum = num_nodes[ti];
    }

    reduce_min_num(sh_min, sh_sum, lmin, lnum, ti);

    if (ti==0) {
        minimum[0] = sh_min[0];
        num_nodes[0] = sh_sum[0];
    }

}

	.text
	.file	"minimum_degree.hip"
	.globl	_Z29__device_stub__minimum_degreePiS_S_S_S_S_i # -- Begin function _Z29__device_stub__minimum_degreePiS_S_S_S_S_i
	.type	_Z29__device_stub__minimum_degreePiS_S_S_S_S_i,@function
_Z29__device_stub__minimum_degreePiS_S_S_S_S_i: # @_Z29__device_stub__minimum_degreePiS_S_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14minimum_degreePiS_S_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__minimum_degreePiS_S_S_S_S_i, .Lfunc_end0-_Z29__device_stub__minimum_degreePiS_S_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__combine_blocked_min_numPiS_i # -- Begin function _Z38__device_stub__combine_blocked_min_numPiS_i
	.type	_Z38__device_stub__combine_blocked_min_numPiS_i,@function
_Z38__device_stub__combine_blocked_min_numPiS_i: # @_Z38__device_stub__combine_blocked_min_numPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23combine_blocked_min_numPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z38__device_stub__combine_blocked_min_numPiS_i, .Lfunc_end1-_Z38__device_stub__combine_blocked_min_numPiS_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14minimum_degreePiS_S_S_S_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23combine_blocked_min_numPiS_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14minimum_degreePiS_S_S_S_S_i,@object # @_Z14minimum_degreePiS_S_S_S_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z14minimum_degreePiS_S_S_S_S_i
	.p2align	3, 0x0
_Z14minimum_degreePiS_S_S_S_S_i:
	.quad	_Z29__device_stub__minimum_degreePiS_S_S_S_S_i
	.size	_Z14minimum_degreePiS_S_S_S_S_i, 8

	.type	_Z23combine_blocked_min_numPiS_i,@object # @_Z23combine_blocked_min_numPiS_i
	.globl	_Z23combine_blocked_min_numPiS_i
	.p2align	3, 0x0
_Z23combine_blocked_min_numPiS_i:
	.quad	_Z38__device_stub__combine_blocked_min_numPiS_i
	.size	_Z23combine_blocked_min_numPiS_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14minimum_degreePiS_S_S_S_S_i"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z23combine_blocked_min_numPiS_i"
	.size	.L__unnamed_2, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__minimum_degreePiS_S_S_S_S_i
	.addrsig_sym _Z38__device_stub__combine_blocked_min_numPiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14minimum_degreePiS_S_S_S_S_i
	.addrsig_sym _Z23combine_blocked_min_numPiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14minimum_degreePiS_S_S_S_S_i ; -- Begin function _Z14minimum_degreePiS_S_S_S_S_i
	.globl	_Z14minimum_degreePiS_S_S_S_S_i
	.p2align	8
	.type	_Z14minimum_degreePiS_S_S_S_S_i,@function
_Z14minimum_degreePiS_S_S_S_S_i:        ; @_Z14minimum_degreePiS_S_S_S_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x30
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x10
	s_mov_b32 s2, s15
	v_mov_b32_e32 v5, 0
	v_lshl_add_u32 v1, s2, 7, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x20
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i32_e32 0, v1
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_load_b32 v3, v[2:3], off offset:-4
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s12, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[1:2], off
	s_waitcnt vmcnt(1)
	v_cmp_lt_i32_e32 vcc_lo, v3, v6
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_nc_u32_e32 v8, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
	v_mov_b32_e32 v5, 0
	s_mov_b32 s8, 0
.LBB0_5:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v9, v[3:4], off
	v_add_co_u32 v3, s1, v3, 4
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, -1, v9
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v8, v6
	v_add_nc_u32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, v5, v7
	s_or_b32 s0, vcc_lo, s0
	v_add_co_ci_u32_e64 v4, vcc_lo, 0, v4, s1
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s8, s0, s8
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow70
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_7:                                ; %Flow71
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
	global_store_b32 v[1:2], v5, off
.LBB0_8:                                ; %Flow72
	s_or_b32 exec_lo, exec_lo, s3
	v_lshlrev_b32_e32 v2, 2, v0
	v_cmp_lt_i32_e32 vcc_lo, 2, v5
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v1, 0x200, v2
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	ds_store_2addr_stride64_b32 v2, v5, v3 offset1:2
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB0_13
; %bb.9:
	v_or_b32_e32 v3, 64, v0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB0_12
; %bb.10:
	ds_load_b32 v5, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_12
; %bb.11:
	ds_store_b32 v2, v4
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s3
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v1, v3
.LBB0_13:                               ; %Flow69
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_18
; %bb.14:
	v_or_b32_e32 v3, 32, v0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB0_17
; %bb.15:
	ds_load_b32 v5, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_17
; %bb.16:
	ds_store_b32 v2, v4
.LBB0_17:
	s_or_b32 exec_lo, exec_lo, s3
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v1, v3
.LBB0_18:                               ; %Flow67
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB0_23
; %bb.19:
	v_or_b32_e32 v3, 16, v0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB0_22
; %bb.20:
	ds_load_b32 v5, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_22
; %bb.21:
	ds_store_b32 v2, v4
.LBB0_22:
	s_or_b32 exec_lo, exec_lo, s3
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v1, v3
.LBB0_23:                               ; %Flow65
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB0_28
; %bb.24:
	v_or_b32_e32 v3, 8, v0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB0_27
; %bb.25:
	ds_load_b32 v5, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_27
; %bb.26:
	ds_store_b32 v2, v4
.LBB0_27:
	s_or_b32 exec_lo, exec_lo, s3
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v1, v3
.LBB0_28:                               ; %Flow63
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB0_33
; %bb.29:
	v_or_b32_e32 v3, 4, v0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB0_32
; %bb.30:
	ds_load_b32 v5, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_32
; %bb.31:
	ds_store_b32 v2, v4
.LBB0_32:
	s_or_b32 exec_lo, exec_lo, s3
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v1, v3
.LBB0_33:                               ; %Flow61
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB0_38
; %bb.34:
	v_or_b32_e32 v3, 2, v0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB0_37
; %bb.35:
	ds_load_b32 v5, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_37
; %bb.36:
	ds_store_b32 v2, v4
.LBB0_37:
	s_or_b32 exec_lo, exec_lo, s3
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v1, v3
.LBB0_38:                               ; %Flow59
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_eq_u32_e64 s0, 0, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_44
; %bb.39:
	v_mov_b32_e32 v0, 0
	ds_load_b32 v3, v0 offset:4
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v3
	s_cbranch_vccnz .LBB0_43
; %bb.40:
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v4
	v_cmp_lt_i32_e64 s1, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s8, vcc_lo, s1
	s_and_saveexec_b32 s1, s8
	s_cbranch_execz .LBB0_42
; %bb.41:
	ds_store_b32 v2, v3
.LBB0_42:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_43:
	ds_load_b32 v0, v0 offset:516
	ds_load_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v2, v0
	ds_store_b32 v1, v0
.LBB0_44:                               ; %Flow57
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_46
; %bb.45:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 2
	s_add_u32 s2, s6, s0
	ds_load_2addr_stride64_b32 v[0:1], v2 offset1:2
	s_addc_u32 s3, s7, s1
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b32 v2, v0, s[0:1]
	global_store_b32 v2, v1, s[2:3]
.LBB0_46:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14minimum_degreePiS_S_S_S_S_i
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 52
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14minimum_degreePiS_S_S_S_S_i, .Lfunc_end0-_Z14minimum_degreePiS_S_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1604
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z23combine_blocked_min_numPiS_i ; -- Begin function _Z23combine_blocked_min_numPiS_i
	.globl	_Z23combine_blocked_min_numPiS_i
	.p2align	8
	.type	_Z23combine_blocked_min_numPiS_i,@function
_Z23combine_blocked_min_numPiS_i:       ; @_Z23combine_blocked_min_numPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	v_lshlrev_b32_e32 v1, 2, v0
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s2, v0
; %bb.1:
	s_clause 0x1
	global_load_b32 v3, v1, s[4:5]
	global_load_b32 v4, v1, s[6:7]
; %bb.2:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v2, 0x200, v1
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v1, v3, v4 offset1:2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB1_7
; %bb.3:
	v_or_b32_e32 v3, 64, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB1_6
; %bb.4:
	ds_load_b32 v5, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_6
; %bb.5:
	ds_store_b32 v1, v4
.LBB1_6:
	s_or_b32 exec_lo, exec_lo, s2
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v2, v3
.LBB1_7:                                ; %Flow34
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB1_12
; %bb.8:
	v_or_b32_e32 v3, 32, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB1_11
; %bb.9:
	ds_load_b32 v5, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_11
; %bb.10:
	ds_store_b32 v1, v4
.LBB1_11:
	s_or_b32 exec_lo, exec_lo, s2
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v2, v3
.LBB1_12:                               ; %Flow32
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB1_17
; %bb.13:
	v_or_b32_e32 v3, 16, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB1_16
; %bb.14:
	ds_load_b32 v5, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_16
; %bb.15:
	ds_store_b32 v1, v4
.LBB1_16:
	s_or_b32 exec_lo, exec_lo, s2
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v2, v3
.LBB1_17:                               ; %Flow30
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 8, v0
	s_cbranch_execz .LBB1_22
; %bb.18:
	v_or_b32_e32 v3, 8, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB1_21
; %bb.19:
	ds_load_b32 v5, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_21
; %bb.20:
	ds_store_b32 v1, v4
.LBB1_21:
	s_or_b32 exec_lo, exec_lo, s2
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v2, v3
.LBB1_22:                               ; %Flow28
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 4, v0
	s_cbranch_execz .LBB1_27
; %bb.23:
	v_or_b32_e32 v3, 4, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB1_26
; %bb.24:
	ds_load_b32 v5, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_26
; %bb.25:
	ds_store_b32 v1, v4
.LBB1_26:
	s_or_b32 exec_lo, exec_lo, s2
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v2, v3
.LBB1_27:                               ; %Flow26
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB1_32
; %bb.28:
	v_or_b32_e32 v3, 2, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 2, v3
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e32 2, v4
	s_cbranch_execz .LBB1_31
; %bb.29:
	ds_load_b32 v5, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB1_31
; %bb.30:
	ds_store_b32 v1, v4
.LBB1_31:
	s_or_b32 exec_lo, exec_lo, s2
	ds_load_b32 v3, v3 offset:512
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v3, v4, v3
	ds_store_b32 v2, v3
.LBB1_32:                               ; %Flow24
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_eq_u32_e64 s0, 0, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB1_38
; %bb.33:
	v_mov_b32_e32 v0, 0
	ds_load_b32 v3, v0 offset:4
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v3
	s_cbranch_vccnz .LBB1_37
; %bb.34:
	ds_load_b32 v4, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 3, v4
	v_cmp_lt_i32_e64 s1, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, vcc_lo, s1
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB1_36
; %bb.35:
	ds_store_b32 v1, v3
.LBB1_36:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_37:
	ds_load_b32 v0, v0 offset:516
	ds_load_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v1, v0
	ds_store_b32 v2, v0
.LBB1_38:                               ; %Flow22
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_40
; %bb.39:
	v_mov_b32_e32 v2, 0
	ds_load_2addr_stride64_b32 v[0:1], v2 offset1:2
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b32 v2, v0, s[4:5]
	global_store_b32 v2, v1, s[6:7]
.LBB1_40:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23combine_blocked_min_numPiS_i
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z23combine_blocked_min_numPiS_i, .Lfunc_end1-_Z23combine_blocked_min_numPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1240
; NumSgprs: 10
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 52
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14minimum_degreePiS_S_S_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14minimum_degreePiS_S_S_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23combine_blocked_min_numPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z23combine_blocked_min_numPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
