#include <stdio.h>
#include "cuda.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	cudaError_t error = cudaGetLastError ();
	if (error != cudaSuccess) {
		printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
		exit(-1);
	}
}

__global__ void sw4 (float * __restrict__ uacc_0, float * __restrict__ uacc_1, float * __restrict__ uacc_2, float * __restrict__ u_0, float * __restrict__ u_1, float * __restrict__ u_2, float * __restrict__ mu, float * __restrict__ la, float * __restrict__ strx, float * __restrict__ stry, float * __restrict__ strz, int N) {
	//Determing the block's indices
	int blockdim_i= (int)(blockDim.x);
	int i0 = (int)(blockIdx.x)*(blockdim_i);
	int i = max (i0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);
	int blockdim_k= (int)(blockDim.z);
	int k0 = (int)(blockIdx.z)*(blockdim_k);
	int k = max (k0, 0) + (int)(threadIdx.z);

	// Assumptions 
	int a1 = 1;
	float h = 3.7;
	float cof = 1e0 / ( h *  h);

	if (i>=2 & j>=2 & k>=2 & i<=N-3 & j<=N-3 & k<=N-3) {
			/* 28 * 3 = 84 flops */
			float mux1 = mu[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-2] * strx[i-2]);
			float mux2 = mu[k*N*N+j*N+i-2] * strx[i-2] + mu[k*N*N+j*N+i+1] * strx[i+1] + 3 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-1] * strx[i-1]);
			float mux3 = mu[k*N*N+j*N+i-1] * strx[i-1] + mu[k*N*N+j*N+i+2] * strx[i+2] + 3 * (mu[k*N*N+j*N+i+1] * strx[i+1] + mu[k*N*N+j*N+i] * strx[i]);
			float mux4 = mu[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i+2] * strx[i+2]);
			float muy1 = mu[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-2)*N+i] * stry[j-2]);
			float muy2 = mu[k*N*N+(j-2)*N+i] * stry[j-2] + mu[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-1)*N+i] * stry[j-1]);
			float muy3 = mu[k*N*N+(j-1)*N+i] * stry[j-1] + mu[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (mu[k*N*N+(j+1)*N+i] * stry[j+1] + mu[k*N*N+j*N+i] * stry[j]);
			float muy4 = mu[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j+2)*N+i] * stry[j+2]);
			float muz1 = mu[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-2)*N*N+j*N+i] * strz[k-2]);
			float muz2 = mu[(k-2)*N*N+j*N+i] * strz[k-2] + mu[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-1)*N*N+j*N+i] * strz[k-1]);
			float muz3 = mu[(k-1)*N*N+j*N+i] * strz[k-1] + mu[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (mu[(k+1)*N*N+j*N+i] * strz[k+1] + mu[k*N*N+j*N+i] * strz[k]);
			float muz4 = mu[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k+2)*N*N+j*N+i] * strz[k+2]);

			/* 78 * 3 = 234 flops */
			float r1 = 1e0 / 6 * (strx[i] * ((2 * mux1 + la[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-2] * strx[i-2])) * (u_0[k*N*N+j*N+i-2] - u_0[k*N*N+j*N+i]) + (2 * mux2 + la[k*N*N+j*N+i-2] * strx[i-2] + la[k*N*N+j*N+i+1] * strx[i+1] + 3 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-1] * strx[i-1])) * (u_0[k*N*N+j*N+i-1] - u_0[k*N*N+j*N+i]) + (2 * mux3 + la[k*N*N+j*N+i-1] * strx[i-1] + la[k*N*N+j*N+i+2] * strx[i+2] + 3 * (la[k*N*N+j*N+i+1] * strx[i+1] + la[k*N*N+j*N+i] * strx[i])) * (u_0[k*N*N+j*N+i+1] - u_0[k*N*N+j*N+i]) + (2 * mux4 + la[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i+2] * strx[i+2])) * (u_0[k*N*N+j*N+i+2] - u_0[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_0[k*N*N+(j-2)*N+i] - u_0[k*N*N+j*N+i]) + muy2 * (u_0[k*N*N+(j-1)*N+i] - u_0[k*N*N+j*N+i]) + muy3 * (u_0[k*N*N+(j+1)*N+i] - u_0[k*N*N+j*N+i]) + muy4 * (u_0[k*N*N+(j+2)*N+i] - u_0[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_0[(k-2)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz2 * (u_0[(k-1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz3 * (u_0[(k+1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz4 * (u_0[(k+2)*N*N+j*N+i] - u_0[k*N*N+j*N+i])));
			float r2 = 1e0 / 6 * (strx[i] * (mux1 * (u_1[k*N*N+j*N+i-2] - u_1[k*N*N+j*N+i]) + mux2 * (u_1[k*N*N+j*N+i-1] - u_1[k*N*N+j*N+i]) + mux3 * (u_1[k*N*N+j*N+i+1] - u_1[k*N*N+j*N+i]) + mux4 * (u_1[k*N*N+j*N+i+2] - u_1[k*N*N+j*N+i])) + stry[j] * ((2 * muy1 + la[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-2)*N+i] * stry[j-2])) * (u_1[k*N*N+(j-2)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy2 + la[k*N*N+(j-2)*N+i] * stry[j-2] + la[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-1)*N+i] * stry[j-1])) * (u_1[k*N*N+(j-1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy3 + la[k*N*N+(j-1)*N+i] * stry[j-1] + la[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (la[k*N*N+(j+1)*N+i] * stry[j+1] + la[k*N*N+j*N+i] * stry[j])) * (u_1[k*N*N+(j+1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy4 + la[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j+2)*N+i] * stry[j+2])) * (u_1[k*N*N+(j+2)*N+i] - u_1[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_1[(k-2)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz2 * (u_1[(k-1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz3 * (u_1[(k+1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz4 * (u_1[(k+2)*N*N+j*N+i] - u_1[k*N*N+j*N+i])));
			float r3 = 1e0 / 6 * (strx[i] * (mux1 * (u_2[k*N*N+j*N+i-2] - u_2[k*N*N+j*N+i]) + mux2 * (u_2[k*N*N+j*N+i-1] - u_2[k*N*N+j*N+i]) + mux3 * (u_2[k*N*N+j*N+i+1] - u_2[k*N*N+j*N+i]) + mux4 * (u_2[k*N*N+j*N+i+2] - u_2[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_2[k*N*N+(j-2)*N+i] - u_2[k*N*N+j*N+i]) + muy2 * (u_2[k*N*N+(j-1)*N+i] - u_2[k*N*N+j*N+i]) + muy3 * (u_2[k*N*N+(j+1)*N+i] - u_2[k*N*N+j*N+i]) + muy4 * (u_2[k*N*N+(j+2)*N+i] - u_2[k*N*N+j*N+i])) + strz[k] * ((2 * muz1 + la[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k-2)*N*N+j*N+i] * strz[k-2])) * (u_2[(k-2)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz2 + la[(k-2)*N*N+j*N+i] * strz[k-2] + la[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (la[k*N*N+j*N+i] * strz[k] + la[(k-1)*N*N+j*N+i] * strz[k-1])) * (u_2[(k-1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz3 + la[(k-1)*N*N+j*N+i] * strz[k-1] + la[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (la[(k+1)*N*N+j*N+i] * strz[k+1] + la[k*N*N+j*N+i] * strz[k])) * (u_2[(k+1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz4 + la[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k+2)*N*N+j*N+i] * strz[k+2])) * (u_2[(k+2)*N*N+j*N+i] - u_2[k*N*N+j*N+i])));

			/* 120 * 3 = 360 flops */
			r1 = r1 + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j+2)*N+i-2] + 8 * (-u_1[k*N*N+(j-1)*N+i-2] + u_1[k*N*N+(j+1)*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_1[k*N*N+(j-2)*N+i-1] - u_1[k*N*N+(j+2)*N+i-1] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j+1)*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_1[k*N*N+(j-2)*N+i+1] - u_1[k*N*N+(j+2)*N+i+1] + 8 * (-u_1[k*N*N+(j-1)*N+i+1] + u_1[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_1[k*N*N+(j-2)*N+i+2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i+2] + u_1[k*N*N+(j+1)*N+i+2])))) + strx[i] * strz[k] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i-2] + 8 * (-u_2[(k-1)*N*N+j*N+i-2] + u_2[(k+1)*N*N+j*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_2[(k-2)*N*N+j*N+i-1] - u_2[(k+2)*N*N+j*N+i-1] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_2[(k-2)*N*N+j*N+i+1] - u_2[(k+2)*N*N+j*N+i+1] + 8 * (-u_2[(k-1)*N*N+j*N+i+1] + u_2[(k+1)*N*N+j*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_2[(k-2)*N*N+j*N+i+2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i+2] + u_2[(k+1)*N*N+j*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j-2)*N+i+2] + 8 * (-u_1[k*N*N+(j-2)*N+i-1] + u_1[k*N*N+(j-2)*N+i+1])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[k*N*N+(j-1)*N+i-2] - u_1[k*N*N+(j-1)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j-1)*N+i+1]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[k*N*N+(j+1)*N+i-2] - u_1[k*N*N+(j+1)*N+i+2] + 8 * (-u_1[k*N*N+(j+1)*N+i-1] + u_1[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[k*N*N+(j+2)*N+i-2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j+2)*N+i-1] + u_1[k*N*N+(j+2)*N+i+1])))) + strx[i] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k-2)*N*N+j*N+i+2] + 8 * (-u_2[(k-2)*N*N+j*N+i-1] + u_2[(k-2)*N*N+j*N+i+1])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+j*N+i-2] - u_2[(k-1)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k-1)*N*N+j*N+i+1]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+j*N+i-2] - u_2[(k+1)*N*N+j*N+i+2] + 8 * (-u_2[(k+1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i+1]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k+2)*N*N+j*N+i-1] + u_2[(k+2)*N*N+j*N+i+1])))); 
			r2 = r2 + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j+2)*N+i-2] + 8 * (-u_0[k*N*N+(j-1)*N+i-2] + u_0[k*N*N+(j+1)*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[k*N*N+(j-2)*N+i-1] - u_0[k*N*N+(j+2)*N+i-1] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j+1)*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[k*N*N+(j-2)*N+i+1] - u_0[k*N*N+(j+2)*N+i+1] + 8 * (-u_0[k*N*N+(j-1)*N+i+1] + u_0[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[k*N*N+(j-2)*N+i+2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i+2] + u_0[k*N*N+(j+1)*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j-2)*N+i+2] + 8 * (-u_0[k*N*N+(j-2)*N+i-1] + u_0[k*N*N+(j-2)*N+i+1])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_0[k*N*N+(j-1)*N+i-2] - u_0[k*N*N+(j-1)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j-1)*N+i+1]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_0[k*N*N+(j+1)*N+i-2] - u_0[k*N*N+(j+1)*N+i+2] + 8 * (-u_0[k*N*N+(j+1)*N+i-1] + u_0[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+(j+2)*N+i] * (u_0[k*N*N+(j+2)*N+i-2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j+2)*N+i-1] + u_0[k*N*N+(j+2)*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-2)*N+i] + u_2[(k+1)*N*N+(j-2)*N+i])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_2[(k-2)*N*N+(j-1)*N+i] - u_2[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j-1)*N+i]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_2[(k-2)*N*N+(j+1)*N+i] - u_2[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (la[k*N*N+(j+2)*N+i] * (u_2[(k-2)*N*N+(j+2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+2)*N+i] + u_2[(k+1)*N*N+(j+2)*N+i])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-2)*N*N+(j-1)*N+i] + u_2[(k-2)*N*N+(j+1)*N+i])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+(j-2)*N+i] - u_2[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k-1)*N*N+(j+1)*N+i]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+(j-2)*N+i] - u_2[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+2)*N*N+(j-1)*N+i] + u_2[(k+2)*N*N+(j+1)*N+i])))); 
			r3 = r3 + strx[i] * strz[k] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i-2] + 8 * (-u_0[(k-1)*N*N+j*N+i-2] + u_0[(k+1)*N*N+j*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[(k-2)*N*N+j*N+i-1] - u_0[(k+2)*N*N+j*N+i-1] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[(k-2)*N*N+j*N+i+1] - u_0[(k+2)*N*N+j*N+i+1] + 8 * (-u_0[(k-1)*N*N+j*N+i+1] + u_0[(k+1)*N*N+j*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[(k-2)*N*N+j*N+i+2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i+2] + u_0[(k+1)*N*N+j*N+i+2])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-2)*N+i] + u_1[(k+1)*N*N+(j-2)*N+i])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[(k-2)*N*N+(j-1)*N+i] - u_1[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j-1)*N+i]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[(k-2)*N*N+(j+1)*N+i] - u_1[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[(k-2)*N*N+(j+2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+2)*N+i] + u_1[(k+1)*N*N+(j+2)*N+i])))) + strx[i] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k-2)*N*N+j*N+i+2] + 8 * (-u_0[(k-2)*N*N+j*N+i-1] + u_0[(k-2)*N*N+j*N+i+1])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_0[(k-1)*N*N+j*N+i-2] - u_0[(k-1)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k-1)*N*N+j*N+i+1]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_0[(k+1)*N*N+j*N+i-2] - u_0[(k+1)*N*N+j*N+i+2] + 8 * (-u_0[(k+1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i+1]))) - (la[(k+2)*N*N+j*N+i] * (u_0[(k+2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k+2)*N*N+j*N+i-1] + u_0[(k+2)*N*N+j*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-2)*N*N+(j-1)*N+i] + u_1[(k-2)*N*N+(j+1)*N+i])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_1[(k-1)*N*N+(j-2)*N+i] - u_1[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k-1)*N*N+(j+1)*N+i]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_1[(k+1)*N*N+(j-2)*N+i] - u_1[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (la[(k+2)*N*N+j*N+i] * (u_1[(k+2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+2)*N*N+(j-1)*N+i] + u_1[(k+2)*N*N+(j+1)*N+i]))));

			/* 3 * 3 = 9 flops */
			uacc_0[k*N*N+j*N+i] = a1 * uacc_0[k*N*N+j*N+i] + cof * r1;
			uacc_1[k*N*N+j*N+i] = a1 * uacc_1[k*N*N+j*N+i] + cof * r2;
			uacc_2[k*N*N+j*N+i] = a1 * uacc_2[k*N*N+j*N+i] + cof * r3;
		} 
}

extern "C" void host_code (float *h_uacc_0, float *h_uacc_1, float *h_uacc_2, float *h_u_0, float *h_u_1, float *h_u_2, float *h_mu, float *h_la, float *h_strx, float *h_stry, float *h_strz, int N) {
	float *uacc_0;
	cudaMalloc (&uacc_0, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for uacc_0\n");
	cudaMemcpy (uacc_0, h_uacc_0, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *uacc_1;
	cudaMalloc (&uacc_1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for uacc_1\n");
	cudaMemcpy (uacc_1, h_uacc_1, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *uacc_2;
	cudaMalloc (&uacc_2, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for uacc_2\n");
	cudaMemcpy (uacc_2, h_uacc_2, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *u_0;
	cudaMalloc (&u_0, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u_0\n");
	cudaMemcpy (u_0, h_u_0, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *u_1;
	cudaMalloc (&u_1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u_1\n");
	cudaMemcpy (u_1, h_u_1, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *u_2;
	cudaMalloc (&u_2, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u_2\n");
	cudaMemcpy (u_2, h_u_2, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *mu;
	cudaMalloc (&mu, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for mu\n");
	cudaMemcpy (mu, h_mu, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *la;
	cudaMalloc (&la, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for la\n");
	cudaMemcpy (la, h_la, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *strx;
	cudaMalloc (&strx, sizeof(float)*N);
	check_error ("Failed to allocate device memory for strx\n");
	cudaMemcpy (strx, h_strx, sizeof(float)*N, cudaMemcpyHostToDevice);
	float *stry;
	cudaMalloc (&stry, sizeof(float)*N);
	check_error ("Failed to allocate device memory for stry\n");
	cudaMemcpy (stry, h_stry, sizeof(float)*N, cudaMemcpyHostToDevice);
	float *strz;
	cudaMalloc (&strz, sizeof(float)*N);
	check_error ("Failed to allocate device memory for strz\n");
	cudaMemcpy (strz, h_strz, sizeof(float)*N, cudaMemcpyHostToDevice);

	dim3 blockconfig (32, 4, 2);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), ceil(N, blockconfig.z));

	sw4 <<<gridconfig, blockconfig>>> (uacc_0, uacc_1, uacc_2, u_0, u_1, u_2, mu, la, strx, stry, strz, N);

	cudaMemcpy (h_uacc_0, uacc_0, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_uacc_1, uacc_1, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_uacc_2, uacc_2, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);

	cudaFree (uacc_0); 
	cudaFree (uacc_1);
	cudaFree (uacc_2);
	cudaFree (u_0);
	cudaFree (u_1);
	cudaFree (u_2);
	cudaFree (mu);
	cudaFree (la);
	cudaFree (strx);
	cudaFree (stry);
	cudaFree (strz);
}

	.file	"tmpxft_0025eeed_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0:
.LFB2173:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2173:
	.size	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error : %s, %s\n"
	.text
	.globl	_Z11check_errorPKc
	.type	_Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L3
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L3:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11check_errorPKc, .-_Z11check_errorPKc
	.globl	_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
	.type	_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i, @function
_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	104(%rsp), %rdi
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	272(%rsp), %rax
	movq	%rsi, 8(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 48(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	280(%rsp), %rax
	movq	%rdx, 16(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 56(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 208(%rsp)
	movq	288(%rsp), %rax
	movq	%rcx, 24(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 64(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	296(%rsp), %rax
	movq	%r8, 32(%rsp)
	movq	%rax, 72(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 224(%rsp)
	movq	304(%rsp), %rax
	movq	%r9, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	96(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 288
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L7:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i, .-_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
	.globl	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
	.type	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, @function
_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, .-_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
	.section	.rodata.str1.1
.LC1:
	.string	"Failed to allocate device memory for uacc_0\n"
.LC2:
	.string	"Failed to allocate device memory for uacc_1\n"
.LC3:
	.string	"Failed to allocate device memory for uacc_2\n"
.LC4:
	.string	"Failed to allocate device memory for u_0\n"
.LC5:
	.string	"Failed to allocate device memory for u_1\n"
.LC6:
	.string	"Failed to allocate device memory for u_2\n"
.LC7:
	.string	"Failed to allocate device memory for mu\n"
.LC8:
	.string	"Failed to allocate device memory for la\n"
.LC9:
	.string	"Failed to allocate device memory for strx\n"
.LC10:
	.string	"Failed to allocate device memory for stry\n"
.LC11:
	.string	"Failed to allocate device memory for strz\n"
	.text
	.globl	host_code
	.type	host_code, @function
host_code:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r8, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	movq	272(%rsp), %rax
	movq	%r9, 32(%rsp)
	movq	%rdx, 24(%rsp)
	movslq	296(%rsp), %rbp
	movq	%rax, 40(%rsp)
	movq	280(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rbp, %rbx
	movq	256(%rsp), %r15
	movq	%rax, 48(%rsp)
	movq	288(%rsp), %rax
	movq	%rsi, 16(%rsp)
	movq	264(%rsp), %r14
	movq	%rax, 56(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	movq	%rbp, %rax
	imulq	%rbp, %rax
	imulq	%rbp, %rax
	salq	$2, %rbp
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC1(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	72(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	80(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC2(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	80(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	88(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC3(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	88(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	96(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC4(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	96(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	104(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC5(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	104(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	112(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC6(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	112(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	120(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC7(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	120(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	128(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC8(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movl	$1, %ecx
	movq	%r14, %rsi
	movq	128(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	leaq	136(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC9(%rip), %rdi
	call	_Z11check_errorPKc
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	%rbp, %rdx
	movq	136(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	leaq	144(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC10(%rip), %rdi
	call	_Z11check_errorPKc
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	%rbp, %rdx
	movq	144(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	leaq	152(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC11(%rip), %rdi
	call	_Z11check_errorPKc
	movq	56(%rsp), %rsi
	movl	$1, %ecx
	movq	%rbp, %rdx
	movq	152(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	%ebx, %eax
	movl	%ebx, %esi
	movl	%ebx, %edx
	andl	$1, %eax
	shrl	%esi
	movl	%ebx, %ecx
	cmpl	$1, %eax
	movl	%ebx, %eax
	sbbl	$-1, %esi
	andl	$3, %edx
	shrl	$2, %eax
	cmpl	$1, %edx
	movl	%ebx, %edx
	sbbl	$-1, %eax
	andl	$31, %ecx
	shrl	$5, %edx
	cmpl	$1, %ecx
	movl	%eax, 176(%rsp)
	movl	$2, %ecx
	sbbl	$-1, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%edx, 172(%rsp)
	movl	$536870913, %edx
	movq	172(%rsp), %rdi
	salq	$5, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	%rbx
	.cfi_def_cfa_offset 264
	pushq	160(%rsp)
	.cfi_def_cfa_offset 272
	pushq	160(%rsp)
	.cfi_def_cfa_offset 280
	pushq	160(%rsp)
	.cfi_def_cfa_offset 288
	pushq	160(%rsp)
	.cfi_def_cfa_offset 296
	pushq	160(%rsp)
	.cfi_def_cfa_offset 304
	movq	160(%rsp), %r9
	movq	152(%rsp), %r8
	movq	144(%rsp), %rcx
	movq	136(%rsp), %rdx
	movq	128(%rsp), %rsi
	movq	120(%rsp), %rdi
	call	_Z43__device_stub__Z3sw4PfS_S_S_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_S_S_i
	addq	$48, %rsp
	.cfi_def_cfa_offset 256
.L16:
	movq	(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	$2, %ecx
	movq	24(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	host_code, .-host_code
	.section	.rodata.str1.1
.LC12:
	.string	"_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	hipError_t error = hipGetLastError ();
	if (error != hipSuccess) {
		printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
		exit(-1);
	}
}

__global__ void sw4 (float * __restrict__ uacc_0, float * __restrict__ uacc_1, float * __restrict__ uacc_2, float * __restrict__ u_0, float * __restrict__ u_1, float * __restrict__ u_2, float * __restrict__ mu, float * __restrict__ la, float * __restrict__ strx, float * __restrict__ stry, float * __restrict__ strz, int N) {
	//Determing the block's indices
	int blockdim_i= (int)(blockDim.x);
	int i0 = (int)(blockIdx.x)*(blockdim_i);
	int i = max (i0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);
	int blockdim_k= (int)(blockDim.z);
	int k0 = (int)(blockIdx.z)*(blockdim_k);
	int k = max (k0, 0) + (int)(threadIdx.z);

	// Assumptions 
	int a1 = 1;
	float h = 3.7;
	float cof = 1e0 / ( h *  h);

	if (i>=2 & j>=2 & k>=2 & i<=N-3 & j<=N-3 & k<=N-3) {
			/* 28 * 3 = 84 flops */
			float mux1 = mu[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-2] * strx[i-2]);
			float mux2 = mu[k*N*N+j*N+i-2] * strx[i-2] + mu[k*N*N+j*N+i+1] * strx[i+1] + 3 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i-1] * strx[i-1]);
			float mux3 = mu[k*N*N+j*N+i-1] * strx[i-1] + mu[k*N*N+j*N+i+2] * strx[i+2] + 3 * (mu[k*N*N+j*N+i+1] * strx[i+1] + mu[k*N*N+j*N+i] * strx[i]);
			float mux4 = mu[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strx[i] + mu[k*N*N+j*N+i+2] * strx[i+2]);
			float muy1 = mu[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-2)*N+i] * stry[j-2]);
			float muy2 = mu[k*N*N+(j-2)*N+i] * stry[j-2] + mu[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j-1)*N+i] * stry[j-1]);
			float muy3 = mu[k*N*N+(j-1)*N+i] * stry[j-1] + mu[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (mu[k*N*N+(j+1)*N+i] * stry[j+1] + mu[k*N*N+j*N+i] * stry[j]);
			float muy4 = mu[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * stry[j] + mu[k*N*N+(j+2)*N+i] * stry[j+2]);
			float muz1 = mu[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-2)*N*N+j*N+i] * strz[k-2]);
			float muz2 = mu[(k-2)*N*N+j*N+i] * strz[k-2] + mu[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k-1)*N*N+j*N+i] * strz[k-1]);
			float muz3 = mu[(k-1)*N*N+j*N+i] * strz[k-1] + mu[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (mu[(k+1)*N*N+j*N+i] * strz[k+1] + mu[k*N*N+j*N+i] * strz[k]);
			float muz4 = mu[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (mu[k*N*N+j*N+i] * strz[k] + mu[(k+2)*N*N+j*N+i] * strz[k+2]);

			/* 78 * 3 = 234 flops */
			float r1 = 1e0 / 6 * (strx[i] * ((2 * mux1 + la[k*N*N+j*N+i-1] * strx[i-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-2] * strx[i-2])) * (u_0[k*N*N+j*N+i-2] - u_0[k*N*N+j*N+i]) + (2 * mux2 + la[k*N*N+j*N+i-2] * strx[i-2] + la[k*N*N+j*N+i+1] * strx[i+1] + 3 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i-1] * strx[i-1])) * (u_0[k*N*N+j*N+i-1] - u_0[k*N*N+j*N+i]) + (2 * mux3 + la[k*N*N+j*N+i-1] * strx[i-1] + la[k*N*N+j*N+i+2] * strx[i+2] + 3 * (la[k*N*N+j*N+i+1] * strx[i+1] + la[k*N*N+j*N+i] * strx[i])) * (u_0[k*N*N+j*N+i+1] - u_0[k*N*N+j*N+i]) + (2 * mux4 + la[k*N*N+j*N+i+1] * strx[i+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strx[i] + la[k*N*N+j*N+i+2] * strx[i+2])) * (u_0[k*N*N+j*N+i+2] - u_0[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_0[k*N*N+(j-2)*N+i] - u_0[k*N*N+j*N+i]) + muy2 * (u_0[k*N*N+(j-1)*N+i] - u_0[k*N*N+j*N+i]) + muy3 * (u_0[k*N*N+(j+1)*N+i] - u_0[k*N*N+j*N+i]) + muy4 * (u_0[k*N*N+(j+2)*N+i] - u_0[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_0[(k-2)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz2 * (u_0[(k-1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz3 * (u_0[(k+1)*N*N+j*N+i] - u_0[k*N*N+j*N+i]) + muz4 * (u_0[(k+2)*N*N+j*N+i] - u_0[k*N*N+j*N+i])));
			float r2 = 1e0 / 6 * (strx[i] * (mux1 * (u_1[k*N*N+j*N+i-2] - u_1[k*N*N+j*N+i]) + mux2 * (u_1[k*N*N+j*N+i-1] - u_1[k*N*N+j*N+i]) + mux3 * (u_1[k*N*N+j*N+i+1] - u_1[k*N*N+j*N+i]) + mux4 * (u_1[k*N*N+j*N+i+2] - u_1[k*N*N+j*N+i])) + stry[j] * ((2 * muy1 + la[k*N*N+(j-1)*N+i] * stry[j-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-2)*N+i] * stry[j-2])) * (u_1[k*N*N+(j-2)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy2 + la[k*N*N+(j-2)*N+i] * stry[j-2] + la[k*N*N+(j+1)*N+i] * stry[j+1] + 3 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j-1)*N+i] * stry[j-1])) * (u_1[k*N*N+(j-1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy3 + la[k*N*N+(j-1)*N+i] * stry[j-1] + la[k*N*N+(j+2)*N+i] * stry[j+2] + 3 * (la[k*N*N+(j+1)*N+i] * stry[j+1] + la[k*N*N+j*N+i] * stry[j])) * (u_1[k*N*N+(j+1)*N+i] - u_1[k*N*N+j*N+i]) + (2 * muy4 + la[k*N*N+(j+1)*N+i] * stry[j+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * stry[j] + la[k*N*N+(j+2)*N+i] * stry[j+2])) * (u_1[k*N*N+(j+2)*N+i] - u_1[k*N*N+j*N+i])) + strz[k] * (muz1 * (u_1[(k-2)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz2 * (u_1[(k-1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz3 * (u_1[(k+1)*N*N+j*N+i] - u_1[k*N*N+j*N+i]) + muz4 * (u_1[(k+2)*N*N+j*N+i] - u_1[k*N*N+j*N+i])));
			float r3 = 1e0 / 6 * (strx[i] * (mux1 * (u_2[k*N*N+j*N+i-2] - u_2[k*N*N+j*N+i]) + mux2 * (u_2[k*N*N+j*N+i-1] - u_2[k*N*N+j*N+i]) + mux3 * (u_2[k*N*N+j*N+i+1] - u_2[k*N*N+j*N+i]) + mux4 * (u_2[k*N*N+j*N+i+2] - u_2[k*N*N+j*N+i])) + stry[j] * (muy1 * (u_2[k*N*N+(j-2)*N+i] - u_2[k*N*N+j*N+i]) + muy2 * (u_2[k*N*N+(j-1)*N+i] - u_2[k*N*N+j*N+i]) + muy3 * (u_2[k*N*N+(j+1)*N+i] - u_2[k*N*N+j*N+i]) + muy4 * (u_2[k*N*N+(j+2)*N+i] - u_2[k*N*N+j*N+i])) + strz[k] * ((2 * muz1 + la[(k-1)*N*N+j*N+i] * strz[k-1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k-2)*N*N+j*N+i] * strz[k-2])) * (u_2[(k-2)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz2 + la[(k-2)*N*N+j*N+i] * strz[k-2] + la[(k+1)*N*N+j*N+i] * strz[k+1] + 3 * (la[k*N*N+j*N+i] * strz[k] + la[(k-1)*N*N+j*N+i] * strz[k-1])) * (u_2[(k-1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz3 + la[(k-1)*N*N+j*N+i] * strz[k-1] + la[(k+2)*N*N+j*N+i] * strz[k+2] + 3 * (la[(k+1)*N*N+j*N+i] * strz[k+1] + la[k*N*N+j*N+i] * strz[k])) * (u_2[(k+1)*N*N+j*N+i] - u_2[k*N*N+j*N+i]) + (2 * muz4 + la[(k+1)*N*N+j*N+i] * strz[k+1] - 3e0 / 4 * (la[k*N*N+j*N+i] * strz[k] + la[(k+2)*N*N+j*N+i] * strz[k+2])) * (u_2[(k+2)*N*N+j*N+i] - u_2[k*N*N+j*N+i])));

			/* 120 * 3 = 360 flops */
			r1 = r1 + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j+2)*N+i-2] + 8 * (-u_1[k*N*N+(j-1)*N+i-2] + u_1[k*N*N+(j+1)*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_1[k*N*N+(j-2)*N+i-1] - u_1[k*N*N+(j+2)*N+i-1] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j+1)*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_1[k*N*N+(j-2)*N+i+1] - u_1[k*N*N+(j+2)*N+i+1] + 8 * (-u_1[k*N*N+(j-1)*N+i+1] + u_1[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_1[k*N*N+(j-2)*N+i+2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i+2] + u_1[k*N*N+(j+1)*N+i+2])))) + strx[i] * strz[k] * (1e0 / 144) * (la[k*N*N+j*N+i-2] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i-2] + 8 * (-u_2[(k-1)*N*N+j*N+i-2] + u_2[(k+1)*N*N+j*N+i-2])) - 8 * (la[k*N*N+j*N+i-1] * (u_2[(k-2)*N*N+j*N+i-1] - u_2[(k+2)*N*N+j*N+i-1] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i-1]))) + 8 * (la[k*N*N+j*N+i+1] * (u_2[(k-2)*N*N+j*N+i+1] - u_2[(k+2)*N*N+j*N+i+1] + 8 * (-u_2[(k-1)*N*N+j*N+i+1] + u_2[(k+1)*N*N+j*N+i+1]))) - (la[k*N*N+j*N+i+2] * (u_2[(k-2)*N*N+j*N+i+2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i+2] + u_2[(k+1)*N*N+j*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[k*N*N+(j-2)*N+i-2] - u_1[k*N*N+(j-2)*N+i+2] + 8 * (-u_1[k*N*N+(j-2)*N+i-1] + u_1[k*N*N+(j-2)*N+i+1])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[k*N*N+(j-1)*N+i-2] - u_1[k*N*N+(j-1)*N+i+2] + 8 * (-u_1[k*N*N+(j-1)*N+i-1] + u_1[k*N*N+(j-1)*N+i+1]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[k*N*N+(j+1)*N+i-2] - u_1[k*N*N+(j+1)*N+i+2] + 8 * (-u_1[k*N*N+(j+1)*N+i-1] + u_1[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[k*N*N+(j+2)*N+i-2] - u_1[k*N*N+(j+2)*N+i+2] + 8 * (-u_1[k*N*N+(j+2)*N+i-1] + u_1[k*N*N+(j+2)*N+i+1])))) + strx[i] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+j*N+i-2] - u_2[(k-2)*N*N+j*N+i+2] + 8 * (-u_2[(k-2)*N*N+j*N+i-1] + u_2[(k-2)*N*N+j*N+i+1])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+j*N+i-2] - u_2[(k-1)*N*N+j*N+i+2] + 8 * (-u_2[(k-1)*N*N+j*N+i-1] + u_2[(k-1)*N*N+j*N+i+1]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+j*N+i-2] - u_2[(k+1)*N*N+j*N+i+2] + 8 * (-u_2[(k+1)*N*N+j*N+i-1] + u_2[(k+1)*N*N+j*N+i+1]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+j*N+i-2] - u_2[(k+2)*N*N+j*N+i+2] + 8 * (-u_2[(k+2)*N*N+j*N+i-1] + u_2[(k+2)*N*N+j*N+i+1])))); 
			r2 = r2 + strx[i] * stry[j] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j+2)*N+i-2] + 8 * (-u_0[k*N*N+(j-1)*N+i-2] + u_0[k*N*N+(j+1)*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[k*N*N+(j-2)*N+i-1] - u_0[k*N*N+(j+2)*N+i-1] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j+1)*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[k*N*N+(j-2)*N+i+1] - u_0[k*N*N+(j+2)*N+i+1] + 8 * (-u_0[k*N*N+(j-1)*N+i+1] + u_0[k*N*N+(j+1)*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[k*N*N+(j-2)*N+i+2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i+2] + u_0[k*N*N+(j+1)*N+i+2])))) + strx[i] * stry[j] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_0[k*N*N+(j-2)*N+i-2] - u_0[k*N*N+(j-2)*N+i+2] + 8 * (-u_0[k*N*N+(j-2)*N+i-1] + u_0[k*N*N+(j-2)*N+i+1])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_0[k*N*N+(j-1)*N+i-2] - u_0[k*N*N+(j-1)*N+i+2] + 8 * (-u_0[k*N*N+(j-1)*N+i-1] + u_0[k*N*N+(j-1)*N+i+1]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_0[k*N*N+(j+1)*N+i-2] - u_0[k*N*N+(j+1)*N+i+2] + 8 * (-u_0[k*N*N+(j+1)*N+i-1] + u_0[k*N*N+(j+1)*N+i+1]))) - (la[k*N*N+(j+2)*N+i] * (u_0[k*N*N+(j+2)*N+i-2] - u_0[k*N*N+(j+2)*N+i+2] + 8 * (-u_0[k*N*N+(j+2)*N+i-1] + u_0[k*N*N+(j+2)*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[k*N*N+(j-2)*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-2)*N+i] + u_2[(k+1)*N*N+(j-2)*N+i])) - 8 * (la[k*N*N+(j-1)*N+i] * (u_2[(k-2)*N*N+(j-1)*N+i] - u_2[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j-1)*N+i]))) + 8 * (la[k*N*N+(j+1)*N+i] * (u_2[(k-2)*N*N+(j+1)*N+i] - u_2[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (la[k*N*N+(j+2)*N+i] * (u_2[(k-2)*N*N+(j+2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j+2)*N+i] + u_2[(k+1)*N*N+(j+2)*N+i])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[(k-2)*N*N+j*N+i] * (u_2[(k-2)*N*N+(j-2)*N+i] - u_2[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-2)*N*N+(j-1)*N+i] + u_2[(k-2)*N*N+(j+1)*N+i])) - 8 * (mu[(k-1)*N*N+j*N+i] * (u_2[(k-1)*N*N+(j-2)*N+i] - u_2[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k-1)*N*N+(j-1)*N+i] + u_2[(k-1)*N*N+(j+1)*N+i]))) + 8 * (mu[(k+1)*N*N+j*N+i] * (u_2[(k+1)*N*N+(j-2)*N+i] - u_2[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+1)*N*N+(j-1)*N+i] + u_2[(k+1)*N*N+(j+1)*N+i]))) - (mu[(k+2)*N*N+j*N+i] * (u_2[(k+2)*N*N+(j-2)*N+i] - u_2[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_2[(k+2)*N*N+(j-1)*N+i] + u_2[(k+2)*N*N+(j+1)*N+i])))); 
			r3 = r3 + strx[i] * strz[k] * (1e0 / 144) * (mu[k*N*N+j*N+i-2] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i-2] + 8 * (-u_0[(k-1)*N*N+j*N+i-2] + u_0[(k+1)*N*N+j*N+i-2])) - 8 * (mu[k*N*N+j*N+i-1] * (u_0[(k-2)*N*N+j*N+i-1] - u_0[(k+2)*N*N+j*N+i-1] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i-1]))) + 8 * (mu[k*N*N+j*N+i+1] * (u_0[(k-2)*N*N+j*N+i+1] - u_0[(k+2)*N*N+j*N+i+1] + 8 * (-u_0[(k-1)*N*N+j*N+i+1] + u_0[(k+1)*N*N+j*N+i+1]))) - (mu[k*N*N+j*N+i+2] * (u_0[(k-2)*N*N+j*N+i+2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i+2] + u_0[(k+1)*N*N+j*N+i+2])))) + stry[j] * strz[k] * (1e0 / 144) * (mu[k*N*N+(j-2)*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j-2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-2)*N+i] + u_1[(k+1)*N*N+(j-2)*N+i])) - 8 * (mu[k*N*N+(j-1)*N+i] * (u_1[(k-2)*N*N+(j-1)*N+i] - u_1[(k+2)*N*N+(j-1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j-1)*N+i]))) + 8 * (mu[k*N*N+(j+1)*N+i] * (u_1[(k-2)*N*N+(j+1)*N+i] - u_1[(k+2)*N*N+(j+1)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (mu[k*N*N+(j+2)*N+i] * (u_1[(k-2)*N*N+(j+2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j+2)*N+i] + u_1[(k+1)*N*N+(j+2)*N+i])))) + strx[i] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_0[(k-2)*N*N+j*N+i-2] - u_0[(k-2)*N*N+j*N+i+2] + 8 * (-u_0[(k-2)*N*N+j*N+i-1] + u_0[(k-2)*N*N+j*N+i+1])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_0[(k-1)*N*N+j*N+i-2] - u_0[(k-1)*N*N+j*N+i+2] + 8 * (-u_0[(k-1)*N*N+j*N+i-1] + u_0[(k-1)*N*N+j*N+i+1]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_0[(k+1)*N*N+j*N+i-2] - u_0[(k+1)*N*N+j*N+i+2] + 8 * (-u_0[(k+1)*N*N+j*N+i-1] + u_0[(k+1)*N*N+j*N+i+1]))) - (la[(k+2)*N*N+j*N+i] * (u_0[(k+2)*N*N+j*N+i-2] - u_0[(k+2)*N*N+j*N+i+2] + 8 * (-u_0[(k+2)*N*N+j*N+i-1] + u_0[(k+2)*N*N+j*N+i+1])))) + stry[j] * strz[k] * (1e0 / 144) * (la[(k-2)*N*N+j*N+i] * (u_1[(k-2)*N*N+(j-2)*N+i] - u_1[(k-2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-2)*N*N+(j-1)*N+i] + u_1[(k-2)*N*N+(j+1)*N+i])) - 8 * (la[(k-1)*N*N+j*N+i] * (u_1[(k-1)*N*N+(j-2)*N+i] - u_1[(k-1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k-1)*N*N+(j-1)*N+i] + u_1[(k-1)*N*N+(j+1)*N+i]))) + 8 * (la[(k+1)*N*N+j*N+i] * (u_1[(k+1)*N*N+(j-2)*N+i] - u_1[(k+1)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+1)*N*N+(j-1)*N+i] + u_1[(k+1)*N*N+(j+1)*N+i]))) - (la[(k+2)*N*N+j*N+i] * (u_1[(k+2)*N*N+(j-2)*N+i] - u_1[(k+2)*N*N+(j+2)*N+i] + 8 * (-u_1[(k+2)*N*N+(j-1)*N+i] + u_1[(k+2)*N*N+(j+1)*N+i]))));

			/* 3 * 3 = 9 flops */
			uacc_0[k*N*N+j*N+i] = a1 * uacc_0[k*N*N+j*N+i] + cof * r1;
			uacc_1[k*N*N+j*N+i] = a1 * uacc_1[k*N*N+j*N+i] + cof * r2;
			uacc_2[k*N*N+j*N+i] = a1 * uacc_2[k*N*N+j*N+i] + cof * r3;
		} 
}

extern "C" void host_code (float *h_uacc_0, float *h_uacc_1, float *h_uacc_2, float *h_u_0, float *h_u_1, float *h_u_2, float *h_mu, float *h_la, float *h_strx, float *h_stry, float *h_strz, int N) {
	float *uacc_0;
	hipMalloc (&uacc_0, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for uacc_0\n");
	hipMemcpy (uacc_0, h_uacc_0, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *uacc_1;
	hipMalloc (&uacc_1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for uacc_1\n");
	hipMemcpy (uacc_1, h_uacc_1, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *uacc_2;
	hipMalloc (&uacc_2, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for uacc_2\n");
	hipMemcpy (uacc_2, h_uacc_2, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *u_0;
	hipMalloc (&u_0, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u_0\n");
	hipMemcpy (u_0, h_u_0, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *u_1;
	hipMalloc (&u_1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u_1\n");
	hipMemcpy (u_1, h_u_1, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *u_2;
	hipMalloc (&u_2, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u_2\n");
	hipMemcpy (u_2, h_u_2, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *mu;
	hipMalloc (&mu, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for mu\n");
	hipMemcpy (mu, h_mu, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *la;
	hipMalloc (&la, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for la\n");
	hipMemcpy (la, h_la, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *strx;
	hipMalloc (&strx, sizeof(float)*N);
	check_error ("Failed to allocate device memory for strx\n");
	hipMemcpy (strx, h_strx, sizeof(float)*N, hipMemcpyHostToDevice);
	float *stry;
	hipMalloc (&stry, sizeof(float)*N);
	check_error ("Failed to allocate device memory for stry\n");
	hipMemcpy (stry, h_stry, sizeof(float)*N, hipMemcpyHostToDevice);
	float *strz;
	hipMalloc (&strz, sizeof(float)*N);
	check_error ("Failed to allocate device memory for strz\n");
	hipMemcpy (strz, h_strz, sizeof(float)*N, hipMemcpyHostToDevice);

	dim3 blockconfig (32, 4, 2);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), ceil(N, blockconfig.z));

	sw4 <<<gridconfig, blockconfig>>> (uacc_0, uacc_1, uacc_2, u_0, u_1, u_2, mu, la, strx, stry, strz, N);

	hipMemcpy (h_uacc_0, uacc_0, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_uacc_1, uacc_1, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_uacc_2, uacc_2, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);

	hipFree (uacc_0); 
	hipFree (uacc_1);
	hipFree (uacc_2);
	hipFree (u_0);
	hipFree (u_1);
	hipFree (u_2);
	hipFree (mu);
	hipFree (la);
	hipFree (strx);
	hipFree (stry);
	hipFree (strz);
}

	.text
	.file	"kernel.hip"
	.globl	_Z11check_errorPKc              # -- Begin function _Z11check_errorPKc
	.type	_Z11check_errorPKc,@function
_Z11check_errorPKc:                     # @_Z11check_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i # -- Begin function _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
	.type	_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i,@function
_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i: # @_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end1-_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
	.cfi_endproc
                                        # -- End function
	.globl	host_code                       # -- Begin function host_code
	.type	host_code,@function
host_code:                              # @host_code
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 112(%rsp)                  # 8-byte Spill
	movq	%r8, 104(%rsp)                  # 8-byte Spill
	movq	%rcx, 96(%rsp)                  # 8-byte Spill
	movq	%rdx, %rbx
	movq	%rsi, %r15
	movq	%rdi, %r13
	movslq	248(%rsp), %r14
	movq	%r14, 120(%rsp)                 # 8-byte Spill
	leaq	(,%r14,4), %rbp
	imulq	%r14, %r14
	imulq	%rbp, %r14
	leaq	24(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z11check_errorPKc
	movq	(%r12), %rdi
	movq	%r13, 128(%rsp)                 # 8-byte Spill
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z11check_errorPKc
	movq	(%r12), %rdi
	movq	%r15, 136(%rsp)                 # 8-byte Spill
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.3, %edi
	callq	_Z11check_errorPKc
	movq	(%r12), %rdi
	movq	%rbx, 144(%rsp)                 # 8-byte Spill
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	88(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.4, %edi
	callq	_Z11check_errorPKc
	movq	(%r12), %rdi
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	80(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.5, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	104(%rsp), %rsi                 # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	72(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.6, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	112(%rsp), %rsi                 # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.7, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	208(%rsp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.8, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	216(%rsp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	48(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	$.L.str.9, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	224(%rsp), %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	$.L.str.10, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	232(%rsp), %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	$.L.str.11, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	120(%rsp), %rbx                 # 8-byte Reload
	movq	240(%rsp), %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebx, %eax
	andl	$31, %eax
	movl	%ebx, %ecx
	shrl	$5, %ecx
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movl	%ebx, %eax
	andl	$3, %eax
	movl	%ebx, %edi
	shrl	$2, %edi
	cmpl	$1, %eax
	sbbl	$-1, %edi
	movl	%ebx, %eax
	andl	$1, %eax
	movl	%ebx, %esi
	shrl	%esi
	addl	%eax, %esi
	shlq	$32, %rdi
	orq	%rcx, %rdi
	movabsq	$17179869216, %rdx              # imm = 0x400000020
	movl	$2, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	88(%rsp), %rcx
	movq	80(%rsp), %r8
	movq	72(%rsp), %r9
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB2_2:
	movq	24(%rsp), %rsi
	movq	128(%rsp), %rdi                 # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	136(%rsp), %rdi                 # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movq	144(%rsp), %rdi                 # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	host_code, .Lfunc_end2-host_code
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error : %s, %s\n"
	.size	.L.str, 21

	.type	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i,@object # @_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
	.p2align	3, 0x0
_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i:
	.quad	_Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
	.size	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Failed to allocate device memory for uacc_0\n"
	.size	.L.str.1, 45

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate device memory for uacc_1\n"
	.size	.L.str.2, 45

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate device memory for uacc_2\n"
	.size	.L.str.3, 45

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate device memory for u_0\n"
	.size	.L.str.4, 42

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to allocate device memory for u_1\n"
	.size	.L.str.5, 42

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Failed to allocate device memory for u_2\n"
	.size	.L.str.6, 42

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Failed to allocate device memory for mu\n"
	.size	.L.str.7, 41

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to allocate device memory for la\n"
	.size	.L.str.8, 41

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Failed to allocate device memory for strx\n"
	.size	.L.str.9, 43

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Failed to allocate device memory for stry\n"
	.size	.L.str.10, 43

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Failed to allocate device memory for strz\n"
	.size	.L.str.11, 43

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i"
	.size	.L__unnamed_1, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__sw4PfS_S_S_S_S_S_S_S_S_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i ; -- Begin function _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
	.globl	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
	.p2align	8
	.type	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i,@function
_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i:          ; @_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x6c
	s_load_b32 s24, s[0:1], 0x58
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v4, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_and_b32 s4, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s13, s13, s4
	s_mul_i32 s14, s14, s2
	s_mul_i32 s15, s15, s3
	s_max_i32 s2, s13, 0
	s_max_i32 s3, s14, 0
	s_max_i32 s4, s15, 0
	v_add_nc_u32_e32 v0, s2, v1
	v_add_nc_u32_e32 v3, s3, v2
	v_add_nc_u32_e32 v2, s4, v4
	s_add_i32 s2, s24, -3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min3_u32 v1, v0, v3, v2
	v_max3_i32 v4, v0, v3, v2
	v_cmp_lt_u32_e32 vcc_lo, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s2, v4
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mul_lo_u32 v11, v3, s24
	s_clause 0x3
	s_load_b64 s[2:3], s[0:1], 0x50
	s_load_b128 s[20:23], s[0:1], 0x40
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	s_mul_i32 s0, s24, s24
	v_mov_b32_e32 v1, 0
	v_mul_lo_u32 v10, s0, v2
	v_add_nc_u32_e32 v16, v11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v16, v10
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[72:73], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s16, v72
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v73, vcc_lo
	s_clause 0x1
	global_load_b32 v94, v[4:5], off offset:8
	global_load_b128 v[12:15], v[4:5], off offset:-8
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_add_co_u32 v6, vcc_lo, s20, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s21, v5, vcc_lo
	s_clause 0x1
	global_load_b32 v5, v[6:7], off offset:8
	global_load_b128 v[28:31], v[6:7], off offset:-8
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v119, v13, v29 :: v_dual_mul_f32 v4, v14, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[6:7], v119
	v_fma_f32 v8, v12, v28, v4
	v_fmac_f32_e32 v119, v94, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[8:9], v8
	v_fma_f64 v[6:7], 0xbfe80000, v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v120, v[6:7]
	v_mul_f32_e32 v6, v15, v31
	v_fma_f32 v7, v13, v29, v4
	v_fma_f32 v121, v12, v28, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v121, 0x40400000, v7
	v_fma_f32 v7, v15, v31, v4
	v_dual_fmac_f32 v4, v94, v5 :: v_dual_fmac_f32 v119, 0x40400000, v7
	v_cvt_f64_f32_e32 v[6:7], v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[8:9], v4
	v_mov_b32_e32 v4, v1
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], 0xbfe80000, v[8:9], v[6:7]
	v_subrev_nc_u32_e32 v8, s24, v11
	v_add_nc_u32_e32 v102, v8, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v122, v[6:7]
	v_add_nc_u32_e32 v6, v102, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[86:87], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s16, v86
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v87, vcc_lo
	v_add_co_u32 v3, vcc_lo, s22, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s23, v4, vcc_lo
	global_load_b32 v95, v[6:7], off
	s_clause 0x1
	global_load_b32 v64, v[3:4], off offset:8
	global_load_b128 v[20:23], v[3:4], off offset:-8
	v_subrev_nc_u32_e32 v6, s24, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v77, v6, v0
	v_mad_u64_u32 v[74:75], null, s24, 3, v[77:78]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v99, s24, v74
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v123, v95, v21 :: v_dual_add_nc_u32 v6, v77, v10
	v_mul_f32_e32 v9, v14, v22
	v_cvt_f64_f32_e32 v[3:4], v123
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[88:89], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s16, v88
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v89, vcc_lo
	global_load_b32 v98, v[6:7], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v0, v98, v20, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[6:7], v0
	v_fma_f64 v[3:4], 0xbfe80000, v[6:7], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v124, v[3:4]
	v_add_nc_u32_e32 v3, v74, v10
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[90:91], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s16, v90
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v91, vcc_lo
	global_load_b32 v97, v[3:4], off
	v_fma_f32 v3, v95, v21, v9
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v97, v23
	v_fma_f32 v125, v98, v20, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v125, 0x40400000, v3
	v_add_nc_u32_e32 v3, v99, v10
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[92:93], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s16, v92
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v93, vcc_lo
	global_load_b32 v96, v[3:4], off
	v_fma_f32 v3, v97, v23, v9
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v123, v96, v64
	v_fmac_f32_e32 v9, v96, v64
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v123, 0x40400000, v3
	v_cvt_f64_f32_e32 v[3:4], v0
	v_add_nc_u32_e32 v0, -1, v2
	v_cvt_f64_f32_e32 v[6:7], v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v103, s0, v0
	v_fma_f64 v[3:4], 0xbfe80000, v[6:7], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v126, v[3:4]
	v_add_nc_u32_e32 v3, v16, v103
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[82:83], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s16, v82
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v83, vcc_lo
	global_load_b32 v100, v[3:4], off
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v107, v[0:1], off offset:8
	global_load_b128 v[24:27], v[0:1], off offset:-8
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, v14, v26
	v_subrev_nc_u32_e32 v14, s0, v103
	v_mul_f32_e32 v108, v100, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v16, v14
	v_cvt_f64_f32_e32 v[0:1], v108
	v_mad_u64_u32 v[75:76], null, s0, 3, v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[84:85], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v106, s0, v75
	s_mov_b32 s0, 0x55555555
	s_mov_b32 s1, 0x3fc55555
	v_add_co_u32 v2, vcc_lo, s16, v84
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v85, vcc_lo
	global_load_b32 v101, v[2:3], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v2, v101, v24, v4
	v_cvt_f64_f32_e32 v[2:3], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], 0xbfe80000, v[2:3], v[0:1]
	v_cvt_f32_f64_e32 v111, v[0:1]
	v_add_nc_u32_e32 v0, v16, v75
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[80:81], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s16, v80
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v81, vcc_lo
	global_load_b32 v104, v[0:1], off
	v_fma_f32 v0, v100, v25, v4
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v104, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v110, v101, v24, v2
	v_fmac_f32_e32 v110, 0x40400000, v0
	v_add_nc_u32_e32 v0, v16, v106
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[78:79], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s16, v78
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v79, vcc_lo
	global_load_b32 v105, v[0:1], off
	v_fma_f32 v0, v104, v27, v4
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v108, v105, v107
	v_fmac_f32_e32 v4, v105, v107
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v108, 0x40400000, v0
	v_cvt_f64_f32_e32 v[0:1], v2
	v_cvt_f64_f32_e32 v[2:3], v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], 0xbfe80000, v[2:3], v[0:1]
	v_add_co_u32 v2, vcc_lo, s18, v72
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v73, vcc_lo
	s_clause 0x1
	global_load_b32 v112, v[2:3], off offset:8
	global_load_b128 v[32:35], v[2:3], off offset:-8
	v_cvt_f32_f64_e32 v109, v[0:1]
	v_cvt_f64_f32_e32 v[0:1], v30
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, v29, v33
	v_mul_f32_e32 v10, v30, v34
	v_mul_f32_e32 v8, v28, v32
	v_mul_f32_e32 v16, v31, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v2, 2.0, v120, v4
	v_fma_f32 v6, v28, v32, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v8, 2.0, v121
	v_fmac_f32_e32 v4, 2.0, v119
	v_fmac_f32_e32 v16, 2.0, v122
	v_cvt_f64_f32_e32 v[2:3], v2
	v_cvt_f64_f32_e32 v[6:7], v6
	v_fmac_f32_e32 v8, v31, v35
	v_fmac_f32_e32 v4, v5, v112
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[2:3], 0xbfe80000, v[6:7], v[2:3]
	v_add_co_u32 v6, vcc_lo, s10, v72
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v73, vcc_lo
	s_clause 0x1
	global_load_b32 v11, v[6:7], off offset:8
	global_load_b128 v[50:53], v[6:7], off offset:-8
	v_fma_f32 v9, v29, v33, v10
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v8, 0x40400000, v9 :: v_dual_sub_f32 v9, v51, v52
	v_sub_f32_e32 v6, v50, v52
	v_mul_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[6:7], v6
	v_cvt_f64_f32_e32 v[8:9], v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[2:3], v[6:7], v[8:9]
	v_fma_f32 v6, v31, v35, v10
	v_fmac_f32_e32 v10, v5, v112
	v_fmac_f32_e32 v4, 0x40400000, v6
	v_sub_f32_e32 v6, v53, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v6, v4
	v_cvt_f64_f32_e32 v[6:7], v4
	v_cvt_f64_f32_e32 v[4:5], v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[6:7]
	v_cvt_f64_f32_e32 v[6:7], v16
	v_fma_f64 v[4:5], 0xbfe80000, v[4:5], v[6:7]
	v_sub_f32_e32 v6, v11, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[6:7], v6
	v_fma_f64 v[2:3], v[4:5], v[6:7], v[2:3]
	v_add_co_u32 v4, vcc_lo, s10, v88
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v89, vcc_lo
	s_clause 0x1
	global_load_b32 v31, v[4:5], off offset:8
	global_load_b128 v[36:39], v[4:5], off offset:-8
	v_add_co_u32 v4, vcc_lo, s10, v86
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v87, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v6, v38, v52
	s_clause 0x1
	global_load_b32 v38, v[4:5], off offset:8
	global_load_b128 v[40:43], v[4:5], off offset:-8
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v4, v42, v52
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v7, v125, v4
	v_add_co_u32 v4, vcc_lo, s10, v90
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v91, vcc_lo
	s_clause 0x1
	global_load_b32 v42, v[4:5], off offset:8
	global_load_b128 v[44:47], v[4:5], off offset:-8
	v_fmac_f32_e32 v7, v6, v124
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v4, v46, v52
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v7, v123, v4
	v_add_co_u32 v4, vcc_lo, s10, v92
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v93, vcc_lo
	s_clause 0x1
	global_load_b32 v46, v[4:5], off offset:8
	global_load_b128 v[48:51], v[4:5], off offset:-8
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v4, v50, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v4, v126
	v_mul_f32_e32 v4, v22, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[4:5], v4
	v_fma_f64 v[28:29], v[2:3], v[0:1], v[4:5]
	v_add_co_u32 v0, vcc_lo, s10, v84
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v85, vcc_lo
	s_clause 0x1
	global_load_b32 v76, v[0:1], off offset:8
	global_load_b128 v[16:19], v[0:1], off offset:-8
	v_add_co_u32 v0, vcc_lo, s10, v82
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v83, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v18, v52
	s_clause 0x1
	global_load_b32 v18, v[0:1], off offset:8
	global_load_b128 v[8:11], v[0:1], off offset:-8
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v10, v52
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v50, v110, v0
	v_add_co_u32 v0, vcc_lo, s10, v80
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v81, vcc_lo
	s_clause 0x1
	global_load_b32 v10, v[0:1], off offset:8
	global_load_b128 v[4:7], v[0:1], off offset:-8
	v_fmac_f32_e32 v50, v2, v111
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v0, v6, v52
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v50, v108, v0
	v_add_co_u32 v0, vcc_lo, s10, v78
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v79, vcc_lo
	s_clause 0x1
	global_load_b32 v6, v[0:1], off offset:8
	global_load_b128 v[0:3], v[0:1], off offset:-8
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v2, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v50, v2, v109
	v_mul_f32_e32 v2, v26, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[52:53], v2
	v_add_f64 v[28:29], v[28:29], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[28:29], v[28:29], s[0:1]
	v_cvt_f32_f64_e32 v2, v[28:29]
	v_add_co_u32 v28, vcc_lo, s12, v72
	v_add_co_ci_u32_e32 v29, vcc_lo, s13, v73, vcc_lo
	s_clause 0x1
	global_load_b32 v50, v[28:29], off offset:8
	global_load_b128 v[66:69], v[28:29], off offset:-8
	v_add_co_u32 v52, vcc_lo, s18, v86
	v_add_co_ci_u32_e32 v53, vcc_lo, s19, v87, vcc_lo
	v_add_co_u32 v54, vcc_lo, s18, v88
	v_add_co_ci_u32_e32 v55, vcc_lo, s19, v89, vcc_lo
	global_load_b32 v113, v[54:55], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v29, v67, v68
	v_sub_f32_e32 v28, v66, v68
	v_mul_f32_e32 v67, v22, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v121, v29
	v_fmac_f32_e32 v29, v28, v120
	v_sub_f32_e32 v28, v69, v68
	v_cvt_f64_f32_e32 v[69:70], v22
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v66, v20, v113
	v_fma_f32 v20, v20, v113, v67
	v_fmac_f32_e32 v29, v119, v28
	v_sub_f32_e32 v28, v50, v68
	global_load_b32 v50, v[52:53], off
	v_cvt_f64_f32_e32 v[54:55], v20
	v_dual_fmac_f32 v66, 2.0, v125 :: v_dual_fmac_f32 v29, v28, v122
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, v30, v29
	v_cvt_f64_f32_e32 v[28:29], v28
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v65, v21, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v52, 2.0, v124, v65
	v_fmac_f32_e32 v65, 2.0, v123
	v_cvt_f64_f32_e32 v[52:53], v52
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[60:61], 0xbfe80000, v[54:55], v[52:53]
	v_add_co_u32 v52, vcc_lo, s12, v88
	v_add_co_ci_u32_e32 v53, vcc_lo, s13, v89, vcc_lo
	s_clause 0x1
	global_load_b32 v114, v[52:53], off offset:8
	global_load_b128 v[52:55], v[52:53], off offset:-8
	v_add_co_u32 v56, vcc_lo, s18, v90
	v_add_co_ci_u32_e32 v57, vcc_lo, s19, v91, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v20, v54, v68
	global_load_b32 v54, v[56:57], off
	v_cvt_f64_f32_e32 v[62:63], v20
	v_fma_f32 v20, v21, v50, v67
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v66, v23, v54
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v71, v23, v54 :: v_dual_fmac_f32 v66, 0x40400000, v20
	v_add_co_u32 v20, vcc_lo, s12, v86
	v_add_co_ci_u32_e32 v21, vcc_lo, s13, v87, vcc_lo
	s_clause 0x1
	global_load_b32 v115, v[20:21], off offset:8
	global_load_b128 v[56:59], v[20:21], off offset:-8
	v_fma_f32 v23, v23, v54, v67
	v_fmac_f32_e32 v71, 2.0, v126
	v_mul_f32_e32 v34, v26, v34
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v20, v58, v68
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v20, v20, v66
	v_cvt_f64_f32_e32 v[20:21], v20
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[20:21], v[60:61], v[62:63], v[20:21]
	v_add_co_u32 v60, vcc_lo, s18, v92
	v_add_co_ci_u32_e32 v61, vcc_lo, s19, v93, vcc_lo
	global_load_b32 v58, v[60:61], off
	v_add_co_u32 v60, vcc_lo, s12, v90
	v_add_co_ci_u32_e32 v61, vcc_lo, s13, v91, vcc_lo
	s_clause 0x1
	global_load_b32 v116, v[60:61], off offset:8
	global_load_b128 v[60:63], v[60:61], off offset:-8
	s_waitcnt vmcnt(2)
	v_fmac_f32_e32 v65, v64, v58
	v_fmac_f32_e32 v67, v64, v58
	v_add_co_u32 v64, vcc_lo, s12, v92
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v65, 0x40400000, v23
	v_cvt_f64_f32_e32 v[117:118], v67
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v23, v62, v68
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v23, v65
	v_cvt_f64_f32_e32 v[65:66], v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[65:66]
	v_cvt_f64_f32_e32 v[65:66], v71
	v_fma_f64 v[127:128], 0xbfe80000, v[117:118], v[65:66]
	v_add_co_ci_u32_e32 v65, vcc_lo, s13, v93, vcc_lo
	s_clause 0x1
	global_load_b32 v117, v[64:65], off offset:8
	global_load_b128 v[64:67], v[64:65], off offset:-8
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v23, v66, v68
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[129:130], v23
	v_fma_f64 v[20:21], v[127:128], v[129:130], v[20:21]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[69:70], v[28:29]
	v_add_co_u32 v28, vcc_lo, s12, v84
	v_add_co_ci_u32_e32 v29, vcc_lo, s13, v85, vcc_lo
	global_load_b32 v23, v[28:29], off
	v_add_co_u32 v28, vcc_lo, s12, v82
	v_add_co_ci_u32_e32 v29, vcc_lo, s13, v83, vcc_lo
	global_load_b32 v28, v[28:29], off
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v23, v23, v68
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v28, v28, v68
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v62, v110, v28
	v_add_co_u32 v28, vcc_lo, s12, v80
	v_add_co_ci_u32_e32 v29, vcc_lo, s13, v81, vcc_lo
	v_fmac_f32_e32 v62, v23, v111
	global_load_b32 v23, v[28:29], off
	v_add_co_u32 v28, vcc_lo, s12, v78
	v_add_co_ci_u32_e32 v29, vcc_lo, s13, v79, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v23, v23, v68
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v62, v108, v23
	global_load_b32 v23, v[28:29], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v23, v23, v68
	v_fmac_f32_e32 v62, v23, v109
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v26, v62
	v_cvt_f64_f32_e32 v[28:29], v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], v[28:29]
	v_mul_f64 v[20:21], v[20:21], s[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v118, v[20:21]
	v_add_co_u32 v20, vcc_lo, s14, v72
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v73, vcc_lo
	s_clause 0x1
	global_load_b32 v23, v[20:21], off offset:8
	global_load_b128 v[68:71], v[20:21], off offset:-8
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v21, v69, v70
	v_sub_f32_e32 v20, v68, v70
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, v121, v21
	v_fmac_f32_e32 v28, v20, v120
	v_sub_f32_e32 v20, v71, v70
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v119, v20
	v_sub_f32_e32 v20, v23, v70
	v_fmac_f32_e32 v28, v20, v122
	v_add_co_u32 v20, vcc_lo, s14, v88
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v89, vcc_lo
	global_load_b32 v20, v[20:21], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v23, v20, v70
	v_add_co_u32 v20, vcc_lo, s14, v86
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v87, vcc_lo
	global_load_b32 v20, v[20:21], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v20, v20, v70
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v29, v125, v20
	v_add_co_u32 v20, vcc_lo, s14, v90
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v91, vcc_lo
	v_fmac_f32_e32 v29, v23, v124
	global_load_b32 v20, v[20:21], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v20, v20, v70
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v29, v123, v20
	v_add_co_u32 v20, vcc_lo, s14, v92
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v93, vcc_lo
	v_add_co_u32 v68, vcc_lo, s18, v82
	v_add_co_ci_u32_e32 v69, vcc_lo, s19, v83, vcc_lo
	v_add_co_u32 v86, vcc_lo, s18, v84
	v_add_co_ci_u32_e32 v87, vcc_lo, s19, v85, vcc_lo
	global_load_b32 v62, v[68:69], off
	global_load_b32 v20, v[20:21], off
	global_load_b32 v66, v[86:87], off
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v71, v25, v62
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v20, v20, v70
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v23, 2.0, v111, v71
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v111, v24, v66
	v_fmac_f32_e32 v71, 2.0, v108
	v_fmac_f32_e32 v29, v20, v126
	v_cvt_f64_f32_e32 v[68:69], v23
	v_fma_f32 v23, v24, v66, v34
	v_fmac_f32_e32 v111, 2.0, v110
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[23:24], v23
	v_fma_f64 v[23:24], 0xbfe80000, v[23:24], v[68:69]
	v_add_co_u32 v68, vcc_lo, s14, v84
	v_add_co_ci_u32_e32 v69, vcc_lo, s15, v85, vcc_lo
	s_clause 0x1
	global_load_b32 v119, v[68:69], off offset:8
	global_load_b128 v[84:87], v[68:69], off offset:-8
	v_fma_f32 v25, v25, v62, v34
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v68, v86, v70
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[92:93], v68
	v_add_co_u32 v68, vcc_lo, s18, v80
	v_add_co_ci_u32_e32 v69, vcc_lo, s19, v81, vcc_lo
	v_add_co_u32 v82, vcc_lo, s14, v82
	v_add_co_ci_u32_e32 v83, vcc_lo, s15, v83, vcc_lo
	global_load_b32 v68, v[68:69], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v111, v27, v68
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v86, v27, v68 :: v_dual_fmac_f32 v111, 0x40400000, v25
	s_clause 0x1
	global_load_b32 v25, v[82:83], off offset:8
	global_load_b128 v[88:91], v[82:83], off offset:-8
	v_fma_f32 v27, v27, v68, v34
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v86, 2.0, v109 :: v_dual_sub_f32 v69, v90, v70
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v69, v69, v111
	v_cvt_f64_f32_e32 v[82:83], v69
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[92:93], v[82:83]
	v_add_co_u32 v82, vcc_lo, s18, v78
	v_add_co_ci_u32_e32 v83, vcc_lo, s19, v79, vcc_lo
	v_add_co_u32 v80, vcc_lo, s14, v80
	v_add_co_ci_u32_e32 v81, vcc_lo, s15, v81, vcc_lo
	global_load_b32 v69, v[82:83], off
	s_clause 0x1
	global_load_b32 v90, v[80:81], off offset:8
	global_load_b128 v[80:83], v[80:81], off offset:-8
	v_add_co_u32 v78, vcc_lo, s14, v78
	v_add_co_ci_u32_e32 v79, vcc_lo, s15, v79, vcc_lo
	s_waitcnt vmcnt(2)
	v_fmac_f32_e32 v71, v107, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v34, v107, v69 :: v_dual_fmac_f32 v71, 0x40400000, v27
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v27, v82, v70
	v_cvt_f64_f32_e32 v[107:108], v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v27, v71
	v_cvt_f64_f32_e32 v[92:93], v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[23:24], v[92:93]
	v_cvt_f64_f32_e32 v[92:93], v86
	v_fma_f64 v[92:93], 0xbfe80000, v[107:108], v[92:93]
	s_clause 0x1
	global_load_b32 v34, v[78:79], off offset:8
	global_load_b128 v[107:110], v[78:79], off offset:-8
	v_mul_f32_e32 v20, v22, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v30, v28
	v_cvt_f64_f32_e32 v[28:29], v26
	v_cvt_f64_f32_e32 v[20:21], v20
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v27, v109, v70
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[70:71], v27
	v_fma_f64 v[23:24], v[92:93], v[70:71], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[23:24], v[28:29], v[20:21]
	v_sub_f32_e32 v29, v80, v88
	v_mul_f64 v[20:21], v[20:21], s[0:1]
	s_mov_b32 s0, 0x1c71c71c
	s_mov_b32 s1, 0x3f7c71c7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v70, v[20:21]
	v_cvt_f64_f32_e32 v[20:21], v2
	v_mul_f32_e32 v2, v30, v22
	v_cvt_f64_f32_e32 v[23:24], v2
	v_sub_f32_e32 v2, v52, v64
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[27:28], v[23:24], s[0:1]
	v_dual_sub_f32 v23, v60, v56 :: v_dual_sub_f32 v24, v61, v57
	v_dual_fmac_f32 v2, 0x41000000, v23 :: v_dual_sub_f32 v23, v53, v65
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v23, 0x41000000, v24 :: v_dual_sub_f32 v24, v63, v59
	v_mul_f32_e32 v23, v33, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, 0x41000000, v23
	v_fma_f32 v2, v32, v2, -v23
	v_sub_f32_e32 v23, v55, v67
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v23, 0x41000000, v24 :: v_dual_sub_f32 v24, v116, v115
	v_mul_f32_e32 v23, v35, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v2, 0x41000000, v23 :: v_dual_sub_f32 v23, v114, v117
	v_fmac_f32_e32 v23, 0x41000000, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v112, v23, v2
	v_cvt_f64_f32_e32 v[23:24], v2
	v_mul_f32_e32 v2, v30, v26
	v_sub_f32_e32 v30, v81, v89
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[27:28], v[23:24], v[20:21]
	v_cvt_f64_f32_e32 v[23:24], v2
	v_sub_f32_e32 v2, v84, v107
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v2, 0x41000000, v29 :: v_dual_sub_f32 v29, v85, v108
	v_dual_fmac_f32 v29, 0x41000000, v30 :: v_dual_sub_f32 v30, v83, v91
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v33, v29
	v_mul_f32_e32 v29, 0x41000000, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v2, v32, v2, -v29
	v_sub_f32_e32 v29, v87, v110
	v_dual_fmac_f32 v29, 0x41000000, v30 :: v_dual_sub_f32 v30, v90, v25
	v_sub_f32_e32 v25, v88, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v29, v35, v29
	v_mul_f64 v[23:24], v[23:24], s[0:1]
	v_dual_fmac_f32 v2, 0x41000000, v29 :: v_dual_sub_f32 v29, v119, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, 0x41000000, v30
	v_fma_f32 v2, -v112, v29, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[29:30], v2
	v_sub_f32_e32 v2, v52, v114
	v_fma_f64 v[20:21], v[23:24], v[29:30], v[20:21]
	v_sub_f32_e32 v29, v55, v53
	v_sub_f32_e32 v30, v59, v57
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v2, 0x41000000, v29 :: v_dual_sub_f32 v29, v56, v115
	v_dual_fmac_f32 v29, 0x41000000, v30 :: v_dual_sub_f32 v30, v63, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v95, v29
	v_mul_f32_e32 v29, 0x41000000, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v2, v98, v2, -v29
	v_sub_f32_e32 v29, v60, v116
	v_dual_fmac_f32 v29, 0x41000000, v30 :: v_dual_sub_f32 v30, v67, v65
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v97, v29
	v_fmac_f32_e32 v2, 0x41000000, v29
	v_sub_f32_e32 v29, v64, v117
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, 0x41000000, v30
	v_fma_f32 v2, -v96, v29, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[29:30], v2
	v_sub_f32_e32 v2, v84, v119
	v_fma_f64 v[20:21], v[27:28], v[29:30], v[20:21]
	v_sub_f32_e32 v29, v87, v85
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0x41000000, v29
	v_sub_f32_e32 v29, v91, v89
	v_fmac_f32_e32 v25, 0x41000000, v29
	v_sub_f32_e32 v29, v83, v81
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v25, v100, v25
	v_mul_f32_e32 v25, 0x41000000, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v2, v101, v2, -v25
	v_sub_f32_e32 v25, v80, v90
	v_fmac_f32_e32 v25, 0x41000000, v29
	v_sub_f32_e32 v29, v110, v108
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v25, v104, v25
	v_dual_fmac_f32 v2, 0x41000000, v25 :: v_dual_sub_f32 v25, v107, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, 0x41000000, v29
	v_fma_f32 v2, -v105, v25, v2
	v_sub_f32_e32 v25, v36, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[29:30], v2
	v_fma_f64 v[20:21], v[23:24], v[29:30], v[20:21]
	v_dual_sub_f32 v29, v44, v40 :: v_dual_sub_f32 v30, v45, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, 0x41000000, v29
	v_sub_f32_e32 v29, v37, v49
	v_dual_fmac_f32 v29, 0x41000000, v30 :: v_dual_sub_f32 v30, v47, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v13, v29
	v_mul_f32_e32 v29, 0x41000000, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v25, v12, v25, -v29
	v_sub_f32_e32 v29, v39, v51
	v_fmac_f32_e32 v29, 0x41000000, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v30, v42, v38 :: v_dual_mul_f32 v29, v15, v29
	v_cvt_f32_f64_e32 v2, v[20:21]
	v_cvt_f64_f32_e32 v[20:21], v118
	v_fmac_f32_e32 v25, 0x41000000, v29
	v_sub_f32_e32 v29, v31, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, 0x41000000, v30
	v_fma_f32 v25, -v94, v29, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[29:30], v25
	v_sub_f32_e32 v25, v36, v31
	v_fma_f64 v[20:21], v[27:28], v[29:30], v[20:21]
	v_sub_f32_e32 v30, v43, v41
	v_sub_f32_e32 v29, v39, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, 0x41000000, v29
	v_sub_f32_e32 v29, v40, v38
	v_dual_fmac_f32 v29, 0x41000000, v30 :: v_dual_sub_f32 v30, v47, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v50, v29
	v_mul_f32_e32 v29, 0x41000000, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v25, v113, v25, -v29
	v_sub_f32_e32 v29, v44, v42
	v_dual_fmac_f32 v29, 0x41000000, v30 :: v_dual_sub_f32 v30, v51, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v54, v29
	v_fmac_f32_e32 v25, 0x41000000, v29
	v_sub_f32_e32 v29, v48, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, 0x41000000, v30
	v_fma_f32 v25, -v58, v29, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[29:30], v25
	v_add_nc_u32_e32 v25, v77, v14
	v_fma_f64 v[59:60], v[27:28], v[29:30], v[20:21]
	v_mul_f32_e32 v20, v22, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v26, 31, v25
	v_cvt_f64_f32_e32 v[20:21], v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	v_add_co_u32 v27, vcc_lo, s14, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v28, vcc_lo, s15, v26, vcc_lo
	global_load_b32 v22, v[27:28], off
	v_add_nc_u32_e32 v27, v77, v106
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	v_add_co_u32 v29, vcc_lo, s14, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v30, vcc_lo, s15, v28, vcc_lo
	global_load_b32 v61, v[29:30], off
	v_add_nc_u32_e32 v29, v77, v103
	v_mul_f64 v[20:21], v[20:21], s[0:1]
	v_ashrrev_i32_e32 v30, 31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	v_add_co_u32 v31, vcc_lo, s14, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v32, vcc_lo, s15, v30, vcc_lo
	global_load_b32 v65, v[31:32], off
	v_add_nc_u32_e32 v31, v77, v75
	v_ashrrev_i32_e32 v32, 31, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[31:32], 2, v[31:32]
	v_add_co_u32 v33, vcc_lo, s14, v31
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v34, vcc_lo, s15, v32, vcc_lo
	global_load_b32 v67, v[33:34], off
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v43, v22, v61
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v33, v67, v65
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v43, 0x41000000, v33
	v_add_nc_u32_e32 v33, v102, v14
	v_ashrrev_i32_e32 v34, 31, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[33:34], 2, v[33:34]
	v_add_co_u32 v35, vcc_lo, s14, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v36, vcc_lo, s15, v34, vcc_lo
	global_load_b32 v71, v[35:36], off
	v_add_nc_u32_e32 v35, v102, v106
	v_ashrrev_i32_e32 v36, 31, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[35:36], 2, v[35:36]
	v_add_co_u32 v37, vcc_lo, s14, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v38, vcc_lo, s15, v36, vcc_lo
	global_load_b32 v77, v[37:38], off
	v_add_nc_u32_e32 v37, v102, v103
	v_ashrrev_i32_e32 v38, 31, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[37:38], 2, v[37:38]
	v_add_co_u32 v39, vcc_lo, s14, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v40, vcc_lo, s15, v38, vcc_lo
	global_load_b32 v78, v[39:40], off
	v_add_nc_u32_e32 v39, v102, v75
	v_ashrrev_i32_e32 v40, 31, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[39:40], 2, v[39:40]
	v_add_co_u32 v41, vcc_lo, s14, v39
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v42, vcc_lo, s15, v40, vcc_lo
	global_load_b32 v79, v[41:42], off
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v44, v71, v77
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v41, v79, v78
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v44, 0x41000000, v41
	v_mul_f32_e32 v41, v50, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v41, 0x41000000, v41
	v_fma_f32 v57, v113, v43, -v41
	v_add_nc_u32_e32 v41, v74, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v42, 31, v41
	v_lshlrev_b64 v[41:42], 2, v[41:42]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, s14, v41
	v_add_co_ci_u32_e32 v44, vcc_lo, s15, v42, vcc_lo
	global_load_b32 v80, v[43:44], off
	v_add_nc_u32_e32 v43, v74, v106
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v44, 31, v43
	v_lshlrev_b64 v[43:44], 2, v[43:44]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v45, vcc_lo, s14, v43
	v_add_co_ci_u32_e32 v46, vcc_lo, s15, v44, vcc_lo
	global_load_b32 v81, v[45:46], off
	v_add_nc_u32_e32 v45, v74, v103
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v46, 31, v45
	v_lshlrev_b64 v[45:46], 2, v[45:46]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v47, vcc_lo, s14, v45
	v_add_co_ci_u32_e32 v48, vcc_lo, s15, v46, vcc_lo
	global_load_b32 v82, v[47:48], off
	v_add_nc_u32_e32 v47, v74, v75
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v48, 31, v47
	v_lshlrev_b64 v[47:48], 2, v[47:48]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v49, vcc_lo, s14, v47
	v_add_co_ci_u32_e32 v50, vcc_lo, s15, v48, vcc_lo
	global_load_b32 v74, v[49:50], off
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v51, v80, v81
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v49, v74, v82
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v51, 0x41000000, v49
	v_mul_f32_e32 v49, v54, v51
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v57, 0x41000000, v49
	v_add_nc_u32_e32 v49, v99, v14
	v_ashrrev_i32_e32 v50, 31, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[49:50], 2, v[49:50]
	v_add_co_u32 v51, vcc_lo, s14, v49
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v52, vcc_lo, s15, v50, vcc_lo
	global_load_b32 v14, v[51:52], off
	v_add_nc_u32_e32 v51, v99, v106
	v_ashrrev_i32_e32 v52, 31, v51
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[51:52], 2, v[51:52]
	v_add_co_u32 v53, vcc_lo, s14, v51
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v54, vcc_lo, s15, v52, vcc_lo
	global_load_b32 v83, v[53:54], off
	v_add_nc_u32_e32 v53, v99, v103
	v_ashrrev_i32_e32 v54, 31, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[53:54], 2, v[53:54]
	v_add_co_u32 v55, vcc_lo, s14, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v56, vcc_lo, s15, v54, vcc_lo
	global_load_b32 v85, v[55:56], off
	v_add_nc_u32_e32 v55, v99, v75
	v_ashrrev_i32_e32 v56, 31, v55
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[55:56], 2, v[55:56]
	v_add_co_u32 v63, vcc_lo, s14, v55
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v64, vcc_lo, s15, v56, vcc_lo
	v_add_co_u32 v25, vcc_lo, s12, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, s13, v26, vcc_lo
	global_load_b32 v63, v[63:64], off
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v84, v14, v83
	v_sub_f32_e32 v14, v22, v14
	v_sub_f32_e32 v22, v80, v71
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, 0x41000000, v22
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v22, v65, v85
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v64, v63, v85
	v_fmac_f32_e32 v84, 0x41000000, v64
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v57, -v58, v84, v57
	v_cvt_f64_f32_e32 v[57:58], v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[57:58], v[20:21], v[57:58], v[59:60]
	v_sub_f32_e32 v59, v82, v78
	v_fmac_f32_e32 v22, 0x41000000, v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v59, v74, v79 :: v_dual_mul_f32 v22, v100, v22
	v_mul_f32_e32 v22, 0x41000000, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v14, v101, v14, -v22
	v_sub_f32_e32 v22, v67, v63
	v_dual_fmac_f32 v22, 0x41000000, v59 :: v_dual_sub_f32 v59, v81, v77
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v104, v22
	v_fmac_f32_e32 v14, 0x41000000, v22
	v_sub_f32_e32 v22, v61, v83
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, 0x41000000, v59
	v_fma_f32 v14, -v105, v22, v14
	v_sub_f32_e32 v22, v16, v0
	v_sub_f32_e32 v16, v16, v76
	v_sub_f32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[59:60], v14
	v_fma_f64 v[57:58], v[20:21], v[59:60], v[57:58]
	v_dual_sub_f32 v59, v4, v8 :: v_dual_sub_f32 v60, v5, v9
	v_dual_sub_f32 v8, v8, v18 :: v_dual_sub_f32 v9, v11, v9
	v_sub_f32_e32 v4, v4, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v22, 0x41000000, v59 :: v_dual_sub_f32 v59, v17, v1
	v_sub_f32_e32 v17, v19, v17
	v_fmac_f32_e32 v8, 0x41000000, v9
	v_sub_f32_e32 v5, v7, v5
	v_sub_f32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v59, 0x41000000, v60 :: v_dual_fmac_f32 v16, 0x41000000, v17
	v_mul_f32_e32 v8, v62, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v4, 0x41000000, v5
	v_dual_fmac_f32 v0, 0x41000000, v1 :: v_dual_mul_f32 v13, v13, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v8, 0x41000000, v8
	v_dual_mul_f32 v4, v68, v4 :: v_dual_mul_f32 v13, 0x41000000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, v66, v16, -v8
	v_fma_f32 v12, v12, v22, -v13
	v_sub_f32_e32 v13, v19, v3
	v_sub_f32_e32 v22, v7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v8, 0x41000000, v4 :: v_dual_fmac_f32 v13, 0x41000000, v22
	v_fma_f32 v0, -v69, v0, v8
	v_cvt_f32_f64_e32 v14, v[57:58]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v13, v15, v13
	v_sub_f32_e32 v15, v10, v18
	v_cvt_f64_f32_e32 v[57:58], v70
	v_cvt_f64_f32_e32 v[0:1], v0
	v_dual_fmac_f32 v12, 0x41000000, v13 :: v_dual_sub_f32 v13, v76, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, 0x41000000, v15
	v_fma_f32 v12, -v94, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[12:13], v12
	v_fma_f64 v[12:13], v[23:24], v[12:13], v[57:58]
	global_load_b32 v57, v[25:26], off
	v_add_co_u32 v25, vcc_lo, s12, v27
	v_add_co_ci_u32_e32 v26, vcc_lo, s13, v28, vcc_lo
	global_load_b32 v15, v[25:26], off
	v_add_co_u32 v25, vcc_lo, s12, v29
	v_add_co_ci_u32_e32 v26, vcc_lo, s13, v30, vcc_lo
	v_add_co_u32 v27, vcc_lo, s12, v31
	v_add_co_ci_u32_e32 v28, vcc_lo, s13, v32, vcc_lo
	s_clause 0x1
	global_load_b32 v26, v[25:26], off
	global_load_b32 v22, v[27:28], off
	v_add_co_u32 v27, vcc_lo, s12, v33
	v_add_co_ci_u32_e32 v28, vcc_lo, s13, v34, vcc_lo
	global_load_b32 v58, v[27:28], off
	v_add_co_u32 v27, vcc_lo, s12, v35
	v_add_co_ci_u32_e32 v28, vcc_lo, s13, v36, vcc_lo
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v59, v57, v15
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v25, v22, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v59, 0x41000000, v25
	global_load_b32 v25, v[27:28], off
	v_add_co_u32 v27, vcc_lo, s12, v37
	v_add_co_ci_u32_e32 v28, vcc_lo, s13, v38, vcc_lo
	global_load_b32 v29, v[27:28], off
	v_add_co_u32 v27, vcc_lo, s12, v39
	v_add_co_ci_u32_e32 v28, vcc_lo, s13, v40, vcc_lo
	global_load_b32 v27, v[27:28], off
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v30, v58, v25
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v28, v27, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, 0x41000000, v28
	v_mul_f32_e32 v28, v95, v30
	v_add_co_u32 v30, vcc_lo, s12, v41
	v_add_co_ci_u32_e32 v31, vcc_lo, s13, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v28, 0x41000000, v28
	global_load_b32 v35, v[30:31], off
	v_add_co_u32 v30, vcc_lo, s12, v43
	v_add_co_ci_u32_e32 v31, vcc_lo, s13, v44, vcc_lo
	v_fma_f32 v39, v98, v59, -v28
	global_load_b32 v28, v[30:31], off
	v_add_co_u32 v30, vcc_lo, s12, v45
	v_add_co_ci_u32_e32 v31, vcc_lo, s13, v46, vcc_lo
	global_load_b32 v32, v[30:31], off
	v_add_co_u32 v30, vcc_lo, s12, v47
	v_add_co_ci_u32_e32 v31, vcc_lo, s13, v48, vcc_lo
	global_load_b32 v30, v[30:31], off
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v4, v35, v58
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v33, v35, v28
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v5, v32, v29
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v31, v30, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, 0x41000000, v31
	v_mul_f32_e32 v31, v97, v33
	v_add_co_u32 v33, vcc_lo, s12, v49
	v_add_co_ci_u32_e32 v34, vcc_lo, s13, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v39, 0x41000000, v31
	global_load_b32 v36, v[33:34], off
	v_add_co_u32 v33, vcc_lo, s12, v51
	v_add_co_ci_u32_e32 v34, vcc_lo, s13, v52, vcc_lo
	global_load_b32 v31, v[33:34], off
	v_add_co_u32 v33, vcc_lo, s12, v53
	v_add_co_ci_u32_e32 v34, vcc_lo, s13, v54, vcc_lo
	v_add_co_u32 v37, vcc_lo, s12, v55
	v_add_co_ci_u32_e32 v38, vcc_lo, s13, v56, vcc_lo
	s_clause 0x1
	global_load_b32 v34, v[33:34], off
	global_load_b32 v33, v[37:38], off
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v3, v57, v36
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v3, 0x41000000, v4 :: v_dual_sub_f32 v40, v36, v31
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v4, v26, v34
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v37, v33, v34 :: v_dual_fmac_f32 v4, 0x41000000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v5, v30, v27 :: v_dual_fmac_f32 v40, 0x41000000, v37
	v_mul_f32_e32 v4, v62, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v96, v40, v39
	v_mul_f32_e32 v4, 0x41000000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[37:38], v37
	v_fma_f32 v3, v66, v3, -v4
	v_sub_f32_e32 v4, v22, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v4, 0x41000000, v5
	v_sub_f32_e32 v5, v28, v25
	v_mul_f32_e32 v4, v68, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v3, 0x41000000, v4 :: v_dual_sub_f32 v4, v15, v31
	v_fmac_f32_e32 v4, 0x41000000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v69, v4, v3
	v_cvt_f64_f32_e32 v[3:4], v3
	v_fma_f64 v[12:13], v[20:21], v[37:38], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[23:24], v[0:1], v[12:13]
	v_fma_f64 v[0:1], v[20:21], v[3:4], v[0:1]
	v_add_co_u32 v3, vcc_lo, s4, v72
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v73, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f32_f64_e32 v0, v[0:1]
	global_load_b32 v1, v[3:4], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v1, 0x3d959926, v2
	global_store_b32 v[3:4], v1, off
	v_add_co_u32 v1, vcc_lo, s6, v72
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v73, vcc_lo
	global_load_b32 v3, v[1:2], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v3, 0x3d959926, v14
	global_store_b32 v[1:2], v3, off
	v_add_co_u32 v1, vcc_lo, s8, v72
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v73, vcc_lo
	global_load_b32 v3, v[1:2], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v3, 0x3d959926, v0
	global_store_b32 v[1:2], v3, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 131
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i, .Lfunc_end0-_Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6548
; NumSgprs: 27
; NumVgprs: 131
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 16
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 131
; Occupancy: 10
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     27
    .sgpr_spill_count: 0
    .symbol:         _Z3sw4PfS_S_S_S_S_S_S_S_S_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     131
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
