



#define M_PI 3.14159265358979323846   // pi
#define DEG2RAD (M_PI/180.0f)
__global__ void computeAccum(unsigned char* result, unsigned char* bw_image, unsigned int* accum, int w, int h, int w_accum, int h_accum, double hough_h)
{
	int x = blockDim.x * blockIdx.x + threadIdx.x;
	int y = blockDim.y * blockIdx.y + threadIdx.y;

	int tid = y * w + x;
    int _r = w * h * 0;
    int _g = w * h * 1;
    int _b = w * h * 2;
    int _a = w * h * 3;	

	if (x >= w || y >= h)
		return;

    double center_x = w / 2;
    double center_y = h / 2;

	if (result[tid + _r] > 128 && result[tid + _g] > 128 && result[tid + _b] > 128) {
		
		for (int t = 0; t < 180; t++) {
			double r = (((double)x - center_x) * cos((double)t * DEG2RAD)) + (((double)y - center_y) * sin((double)t * DEG2RAD));
			//accum[(int)((round(r + hough_h) * 180.0)) + t]++;
            int help = (int)((round(r + hough_h) * 180.0)) + t;
            int ind = 0;
            int alma = help / h_accum;
            int korte = help % h_accum;

            ind = alma + (korte * w_accum);
            atomicAdd(&accum[(int)((round(r + hough_h) * 180.0)) + t], 1);
            //atomicAdd(&accum[ind], 1);
		}
		bw_image[tid + _r] = 255;
		bw_image[tid + _g] = 255;
        bw_image[tid + _b] = 255;
		bw_image[tid + _a] = 255;
	}
	else {
		bw_image[tid + _r] = 0;
		bw_image[tid + _g] = 0;
        bw_image[tid + _b] = 0;
		bw_image[tid + _a] = 255;
	}
	

	return;
}


	.file	"tmpxft_0021b427_00000000-6_computeAccum.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z12computeAccumPhS_PjiiiidPhS_Pjiiiid
	.type	_Z41__device_stub__Z12computeAccumPhS_PjiiiidPhS_Pjiiiid, @function
_Z41__device_stub__Z12computeAccumPhS_PjiiiidPhS_Pjiiiid:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movsd	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z12computeAccumPhS_Pjiiiid(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z41__device_stub__Z12computeAccumPhS_PjiiiidPhS_Pjiiiid, .-_Z41__device_stub__Z12computeAccumPhS_PjiiiidPhS_Pjiiiid
	.globl	_Z12computeAccumPhS_Pjiiiid
	.type	_Z12computeAccumPhS_Pjiiiid, @function
_Z12computeAccumPhS_Pjiiiid:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z12computeAccumPhS_PjiiiidPhS_Pjiiiid
	.cfi_endproc
.LFE2033:
	.size	_Z12computeAccumPhS_Pjiiiid, .-_Z12computeAccumPhS_Pjiiiid
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12computeAccumPhS_Pjiiiid"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12computeAccumPhS_Pjiiiid(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>




#define M_PI 3.14159265358979323846   // pi
#define DEG2RAD (M_PI/180.0f)
__global__ void computeAccum(unsigned char* result, unsigned char* bw_image, unsigned int* accum, int w, int h, int w_accum, int h_accum, double hough_h)
{
	int x = blockDim.x * blockIdx.x + threadIdx.x;
	int y = blockDim.y * blockIdx.y + threadIdx.y;

	int tid = y * w + x;
    int _r = w * h * 0;
    int _g = w * h * 1;
    int _b = w * h * 2;
    int _a = w * h * 3;	

	if (x >= w || y >= h)
		return;

    double center_x = w / 2;
    double center_y = h / 2;

	if (result[tid + _r] > 128 && result[tid + _g] > 128 && result[tid + _b] > 128) {
		
		for (int t = 0; t < 180; t++) {
			double r = (((double)x - center_x) * cos((double)t * DEG2RAD)) + (((double)y - center_y) * sin((double)t * DEG2RAD));
			//accum[(int)((round(r + hough_h) * 180.0)) + t]++;
            int help = (int)((round(r + hough_h) * 180.0)) + t;
            int ind = 0;
            int alma = help / h_accum;
            int korte = help % h_accum;

            ind = alma + (korte * w_accum);
            atomicAdd(&accum[(int)((round(r + hough_h) * 180.0)) + t], 1);
            //atomicAdd(&accum[ind], 1);
		}
		bw_image[tid + _r] = 255;
		bw_image[tid + _g] = 255;
        bw_image[tid + _b] = 255;
		bw_image[tid + _a] = 255;
	}
	else {
		bw_image[tid + _r] = 0;
		bw_image[tid + _g] = 0;
        bw_image[tid + _b] = 0;
		bw_image[tid + _a] = 255;
	}
	

	return;
}


	.text
	.file	"computeAccum.hip"
	.globl	_Z27__device_stub__computeAccumPhS_Pjiiiid # -- Begin function _Z27__device_stub__computeAccumPhS_Pjiiiid
	.type	_Z27__device_stub__computeAccumPhS_Pjiiiid,@function
_Z27__device_stub__computeAccumPhS_Pjiiiid: # @_Z27__device_stub__computeAccumPhS_Pjiiiid
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	32(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12computeAccumPhS_Pjiiiid, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__computeAccumPhS_Pjiiiid, .Lfunc_end0-_Z27__device_stub__computeAccumPhS_Pjiiiid
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12computeAccumPhS_Pjiiiid, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12computeAccumPhS_Pjiiiid,@object # @_Z12computeAccumPhS_Pjiiiid
	.section	.rodata,"a",@progbits
	.globl	_Z12computeAccumPhS_Pjiiiid
	.p2align	3, 0x0
_Z12computeAccumPhS_Pjiiiid:
	.quad	_Z27__device_stub__computeAccumPhS_Pjiiiid
	.size	_Z12computeAccumPhS_Pjiiiid, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12computeAccumPhS_Pjiiiid"
	.size	.L__unnamed_1, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__computeAccumPhS_Pjiiiid
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12computeAccumPhS_Pjiiiid
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12computeAccumPhS_Pjiiiid ; -- Begin function _Z12computeAccumPhS_Pjiiiid
	.globl	_Z12computeAccumPhS_Pjiiiid
	.p2align	8
	.type	_Z12computeAccumPhS_Pjiiiid,@function
_Z12computeAccumPhS_Pjiiiid:            ; @_Z12computeAccumPhS_Pjiiiid
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b64 s[8:9], s[0:1], 0x18
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
	v_mad_u64_u32 v[5:6], null, s14, s2, v[1:2]
	v_cmp_gt_i32_e64 s2, s9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s8, v5
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_22
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s8, v[5:6]
	s_mul_i32 s2, s9, s8
	s_mov_b32 s12, -1
	s_mov_b32 s10, 0
	v_ashrrev_i32_e32 v25, 31, v0
	v_add_nc_u32_e32 v24, s2, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v25, vcc_lo
	global_load_u8 v1, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_u16_e32 vcc_lo, 0x80, v1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s11, vcc_lo
                                        ; implicit-def: $sgpr2_sgpr3
	s_cbranch_execz .LBB0_5
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_add_co_u32 v1, vcc_lo, v6, s2
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v7, vcc_lo
	global_load_u8 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_u16_e64 s12, 0x81, v1
	v_cmp_lt_u16_e32 vcc_lo, 0x80, v1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_add_nc_u32_e32 v1, s2, v24
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v6, vcc_lo, s4, v1
	s_and_not1_b32 s4, s12, exec_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v2, vcc_lo
	global_load_u8 v4, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_u16_e32 vcc_lo, 0x81, v4
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s12, s4, s5
.LBB0_4:                                ; %Flow231
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s10, s10, exec_lo
	s_or_not1_b32 s12, s12, exec_lo
.LBB0_5:                                ; %Flow230
	s_or_b32 exec_lo, exec_lo, s11
                                        ; implicit-def: $sgpr5
                                        ; implicit-def: $vgpr6_vgpr7
	s_and_saveexec_b32 s4, s12
	s_cbranch_execz .LBB0_7
; %bb.6:                                ; %._crit_edge
	v_add_co_u32 v8, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v25, vcc_lo
	s_ashr_i32 s5, s2, 31
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v8, s2
	v_mov_b32_e32 v4, 0
	v_add_nc_u32_e32 v6, s2, v24
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
	s_mov_b32 s5, 0
	global_store_b8 v[8:9], v4, off
	v_ashrrev_i32_e32 v7, 31, v6
	s_and_not1_b32 s10, s10, exec_lo
	global_store_b8 v[10:11], v4, off
.LBB0_7:                                ; %Flow232
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v4, s5
	s_and_saveexec_b32 s33, s10
	s_cbranch_execz .LBB0_21
; %bb.8:                                ; %.preheader
	s_lshr_b32 s4, s8, 31
	s_lshr_b32 s5, s9, 31
	s_add_i32 s4, s8, s4
	s_add_i32 s5, s9, s5
	s_ashr_i32 s4, s4, 1
	s_ashr_i32 s5, s5, 1
	v_cvt_f64_i32_e32 v[6:7], s4
	v_cvt_f64_i32_e32 v[8:9], v5
	v_cvt_f64_i32_e32 v[10:11], v3
	v_cvt_f64_i32_e32 v[12:13], s5
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b64 s[8:9], s[0:1], 0x28
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v26, 1
	v_mov_b32_e32 v4, 0
	s_mov_b32 s12, 0xa2529d39
	s_mov_b32 s18, 0x54442d18
	s_mov_b32 s20, 0x6dc9c883
	s_mov_b32 s22, 0x33145c00
	s_mov_b32 s24, 0x252049c0
	s_mov_b32 s26, 0x9037ab78
	s_mov_b32 s28, 0x46cc5e42
	s_mov_b32 s30, 0xa17f65f6
	s_mov_b32 s34, 0x19f4ec90
	s_mov_b32 s36, 0x16c16967
	s_mov_b32 s38, 0x55555555
	s_mov_b32 s40, 0xb42fdfa7
	s_mov_b32 s42, 0xf9a43bb8
	s_mov_b32 s44, 0x796cde01
	s_mov_b32 s46, 0x19e83e5c
	s_mov_b32 s48, 0x11110bb3
	s_mov_b64 s[10:11], 0
	s_mov_b32 s13, 0x3f91df46
	s_mov_b32 s14, 0
	s_mov_b32 s17, 0x3ff921fb
	s_mov_b32 s19, 0xbff921fb
	s_mov_b32 s21, 0x3fe45f30
	s_mov_b32 s23, 0xbc91a626
	s_mov_b32 s25, 0xb97b839a
	s_mov_b32 s27, 0x3e21eeb6
	s_mov_b32 s29, 0xbda907db
	s_mov_b32 s31, 0xbe927e4f
	s_mov_b32 s35, 0x3efa01a0
	s_mov_b32 s37, 0xbf56c16c
	s_mov_b32 s39, 0x3fa55555
	s_mov_b32 s41, 0xbe5ae600
	v_add_f64 v[5:6], v[8:9], -v[6:7]
	v_mov_b32_e32 v9, 0
	v_add_f64 v[7:8], v[10:11], -v[12:13]
	s_mov_b32 s43, 0x3de5e0b2
	s_mov_b32 s45, 0x3ec71de3
	s_mov_b32 s47, 0xbf2a01a0
	s_mov_b32 s49, 0x3f811111
	s_mov_b32 s51, 0x3c91a626
	s_mov_b32 s52, 0x33145c07
	s_mov_b32 s55, 0xbfc55555
.LBB0_9:                                ; =>This Inner Loop Header: Depth=1
	v_mul_f64 v[10:11], v[3:4], s[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s1, 0x41d00000, |v[10:11]|
	v_trig_preop_f64 v[20:21], |v[10:11]|, 0
	v_trig_preop_f64 v[18:19], |v[10:11]|, 1
	v_cmp_le_f64_e64 s0, 0x7b000000, |v[10:11]|
	v_ldexp_f64 v[22:23], |v[10:11]|, 0xffffff80
	v_trig_preop_f64 v[16:17], |v[10:11]|, 2
	v_and_b32_e32 v28, 0x7fffffff, v11
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, v28, v23, s0
	v_cndmask_b32_e64 v12, v10, v22, s0
	s_mov_b32 s16, s18
	s_mov_b32 s53, s51
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[20:21], v[12:13]
	v_mul_f64 v[29:30], v[18:19], v[12:13]
	v_mul_f64 v[41:42], v[16:17], v[12:13]
	v_fma_f64 v[31:32], v[20:21], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[43:44], v[18:19], v[12:13], -v[29:30]
	v_fma_f64 v[12:13], v[16:17], v[12:13], -v[41:42]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[33:34], v[29:30], v[31:32]
	v_add_f64 v[35:36], v[33:34], -v[29:30]
	v_add_f64 v[39:40], v[14:15], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[33:34], -v[35:36]
	v_add_f64 v[31:32], v[31:32], -v[35:36]
	v_ldexp_f64 v[35:36], v[39:40], -2
	v_add_f64 v[14:15], v[39:40], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[29:30], v[29:30], -v[37:38]
	v_add_f64 v[37:38], v[41:42], v[43:44]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[35:36]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[33:34], -v[14:15]
	v_add_f64 v[29:30], v[31:32], v[29:30]
	v_fract_f64_e32 v[31:32], v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[33:34], v[37:38], v[29:30]
	v_dual_cndmask_b32 v32, 0, v32 :: v_dual_cndmask_b32 v31, 0, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[31:32], v[31:32], 2
	v_add_f64 v[35:36], v[14:15], v[33:34]
	v_add_f64 v[45:46], v[33:34], -v[37:38]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[39:40], v[35:36], v[31:32]
	v_add_f64 v[51:52], v[33:34], -v[45:46]
	v_add_f64 v[29:30], v[29:30], -v[45:46]
	v_add_f64 v[14:15], v[35:36], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[39:40]
	v_add_f64 v[39:40], v[37:38], -v[41:42]
	v_add_f64 v[14:15], v[33:34], -v[14:15]
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s15, 0x40100000, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f64 v[49:50], v[37:38], -v[39:40]
	v_add_f64 v[31:32], v[31:32], s[14:15]
	v_add_f64 v[39:40], v[43:44], -v[39:40]
	v_add_f64 v[37:38], v[37:38], -v[51:52]
	v_add_f64 v[43:44], v[41:42], -v[49:50]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[47:48], v[35:36], v[31:32]
	v_add_f64 v[29:30], v[29:30], v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[39:40], v[39:40], v[43:44]
	v_cvt_i32_f64_e32 v27, v[47:48]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[39:40], v[29:30]
	v_cvt_f64_i32_e32 v[45:46], v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[29:30]
	v_add_f64 v[31:32], v[31:32], -v[45:46]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[14:15], v[12:13]
	v_add_f64 v[37:38], v[35:36], v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[37:38], -v[31:32]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[37:38]
	v_add_f64 v[14:15], v[35:36], -v[29:30]
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s15, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v27, s0, 0, v27, vcc_lo
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_add_f64 v[14:15], v[37:38], -s[14:15]
	v_add_f64 v[29:30], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[31:32], v[29:30], s[16:17]
	v_add_f64 v[14:15], v[29:30], -v[14:15]
	v_fma_f64 v[33:34], v[29:30], s[16:17], -v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_fma_f64 v[14:15], v[29:30], s[52:53], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], s[16:17], v[14:15]
	v_add_f64 v[12:13], v[31:32], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[29:30], v[12:13], -v[31:32]
	v_add_f64 v[14:15], v[14:15], -v[29:30]
	s_branch .LBB0_12
.LBB0_11:                               ;   in Loop: Header=BB0_9 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr14_vgpr15
.LBB0_12:                               ; %Flow228
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_9 Depth=1
	v_mul_f64 v[12:13], |v[10:11]|, s[20:21]
	s_mov_b32 s50, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[29:30], v[12:13]
	v_fma_f64 v[12:13], v[29:30], s[18:19], |v[10:11]|
	v_mul_f64 v[14:15], v[29:30], s[22:23]
	v_cvt_i32_f64_e32 v27, v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[33:34], v[29:30], s[22:23], v[12:13]
	v_add_f64 v[31:32], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[31:32]
	v_add_f64 v[31:32], v[31:32], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_fma_f64 v[14:15], v[29:30], s[50:51], v[14:15]
	v_add_f64 v[12:13], v[31:32], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_fma_f64 v[14:15], v[29:30], s[24:25], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[33:34], v[14:15]
	v_add_f64 v[31:32], v[12:13], -v[33:34]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[14:15], v[14:15], -v[31:32]
.LBB0_14:                               ; %_ZL3cosd.exit
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_9 Depth=1
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[10:11]|
	s_mov_b32 s16, s18
	s_mov_b32 s53, s51
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v23, v28, v23 :: v_dual_cndmask_b32 v22, v10, v22
	v_mul_f64 v[28:29], v[20:21], v[22:23]
	v_mul_f64 v[30:31], v[18:19], v[22:23]
	v_mul_f64 v[40:41], v[16:17], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[20:21], v[22:23], -v[28:29]
	v_fma_f64 v[18:19], v[18:19], v[22:23], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[16:17], v[22:23], -v[40:41]
	v_add_f64 v[32:33], v[30:31], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[32:33], -v[30:31]
	v_add_f64 v[38:39], v[28:29], v[32:33]
	v_add_f64 v[36:37], v[32:33], -v[34:35]
	v_add_f64 v[20:21], v[20:21], -v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[34:35], v[38:39], -2
	v_add_f64 v[28:29], v[38:39], -v[28:29]
	v_add_f64 v[30:31], v[30:31], -v[36:37]
	v_add_f64 v[36:37], v[40:41], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[34:35]|
	v_add_f64 v[28:29], v[32:33], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[30:31]
	v_fract_f64_e32 v[30:31], v[34:35]
	v_add_f64 v[32:33], v[36:37], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v31, 0, v31 :: v_dual_cndmask_b32 v30, 0, v30
	v_ldexp_f64 v[30:31], v[30:31], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[28:29], v[32:33]
	v_add_f64 v[42:43], v[32:33], -v[36:37]
	v_add_f64 v[38:39], v[34:35], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[48:49], v[32:33], -v[42:43]
	v_add_f64 v[20:21], v[20:21], -v[42:43]
	v_add_f64 v[22:23], v[34:35], -v[28:29]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[38:39]
	v_add_f64 v[38:39], v[36:37], -v[40:41]
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s15, 0x40100000, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f64 v[46:47], v[36:37], -v[38:39]
	v_add_f64 v[30:31], v[30:31], s[14:15]
	v_add_f64 v[18:19], v[18:19], -v[38:39]
	v_add_f64 v[36:37], v[36:37], -v[48:49]
	v_add_f64 v[38:39], v[40:41], -v[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[44:45], v[34:35], v[30:31]
	v_add_f64 v[20:21], v[20:21], v[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], v[38:39]
	v_cvt_i32_f64_e32 v44, v[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_cvt_f64_i32_e32 v[42:43], v44
	v_add_f64 v[20:21], v[32:33], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[30:31], v[30:31], -v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[20:21], v[16:17]
	v_add_f64 v[28:29], v[34:35], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[28:29], -v[30:31]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[28:29]
	v_add_f64 v[18:19], v[34:35], -v[18:19]
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s15, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v20, s0, 0, v44, vcc_lo
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[18:19], v[28:29], -s[14:15]
	v_add_f64 v[21:22], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[28:29], v[21:22], s[16:17]
	v_add_f64 v[18:19], v[21:22], -v[18:19]
	v_fma_f64 v[30:31], v[21:22], s[16:17], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_fma_f64 v[18:19], v[21:22], s[52:53], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], s[16:17], v[18:19]
	v_add_f64 v[16:17], v[28:29], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[16:17], -v[28:29]
	v_add_f64 v[18:19], v[18:19], -v[21:22]
	s_branch .LBB0_17
.LBB0_16:                               ;   in Loop: Header=BB0_9 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr18_vgpr19
.LBB0_17:                               ; %Flow
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_9 Depth=1
	v_mul_f64 v[16:17], |v[10:11]|, s[20:21]
	s_mov_b32 s50, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[20:21], v[16:17]
	v_fma_f64 v[16:17], v[20:21], s[18:19], |v[10:11]|
	v_mul_f64 v[18:19], v[20:21], s[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[20:21], s[22:23], v[16:17]
	v_add_f64 v[22:23], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	v_add_f64 v[22:23], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_fma_f64 v[18:19], v[20:21], s[50:51], v[18:19]
	v_add_f64 v[16:17], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_fma_f64 v[18:19], v[20:21], s[24:25], v[16:17]
	v_cvt_i32_f64_e32 v20, v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[28:29], v[18:19]
	v_add_f64 v[22:23], v[16:17], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
.LBB0_19:                               ; %_ZL3sind.exit
                                        ;   in Loop: Header=BB0_9 Depth=1
	v_mul_f64 v[21:22], v[12:13], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[28:29], v[16:17], v[16:17]
	v_mul_f64 v[46:47], v[14:15], 0.5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_f64 v[52:53], v[18:19], 0.5
	s_mov_b32 s54, s38
	v_cmp_class_f64_e64 s0, v[10:11], 0x1f8
	v_lshlrev_b32_e32 v10, 30, v20
	v_add_f64 v[3:4], v[3:4], 1.0
	v_xor_b32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v10, 0x80000000, v10
	v_fma_f64 v[30:31], v[21:22], s[42:43], s[40:41]
	v_fma_f64 v[32:33], v[28:29], s[42:43], s[40:41]
	v_fma_f64 v[34:35], v[21:22], s[28:29], s[26:27]
	v_mul_f64 v[36:37], v[21:22], 0.5
	v_fma_f64 v[38:39], v[28:29], s[28:29], s[26:27]
	v_mul_f64 v[40:41], v[28:29], 0.5
	v_mul_f64 v[48:49], v[12:13], -v[21:22]
	v_mul_f64 v[54:55], v[16:17], -v[28:29]
	v_fma_f64 v[30:31], v[21:22], v[30:31], s[44:45]
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[44:45]
	v_fma_f64 v[34:35], v[21:22], v[34:35], s[30:31]
	v_add_f64 v[42:43], -v[36:37], 1.0
	v_fma_f64 v[38:39], v[28:29], v[38:39], s[30:31]
	v_add_f64 v[44:45], -v[40:41], 1.0
	v_fma_f64 v[30:31], v[21:22], v[30:31], s[46:47]
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[46:47]
	v_fma_f64 v[34:35], v[21:22], v[34:35], s[34:35]
	v_add_f64 v[50:51], -v[42:43], 1.0
	v_fma_f64 v[38:39], v[28:29], v[38:39], s[34:35]
	v_add_f64 v[56:57], -v[44:45], 1.0
	v_fma_f64 v[30:31], v[21:22], v[30:31], s[48:49]
	v_fma_f64 v[32:33], v[28:29], v[32:33], s[48:49]
	v_fma_f64 v[34:35], v[21:22], v[34:35], s[36:37]
	v_add_f64 v[36:37], v[50:51], -v[36:37]
	v_fma_f64 v[38:39], v[28:29], v[38:39], s[36:37]
	v_add_f64 v[40:41], v[56:57], -v[40:41]
	v_fma_f64 v[30:31], v[48:49], v[30:31], v[46:47]
	v_fma_f64 v[32:33], v[54:55], v[32:33], v[52:53]
	v_mul_f64 v[46:47], v[21:22], v[21:22]
	v_fma_f64 v[34:35], v[21:22], v[34:35], s[38:39]
	v_fma_f64 v[36:37], v[12:13], -v[14:15], v[36:37]
	v_fma_f64 v[14:15], v[21:22], v[30:31], -v[14:15]
	v_mul_f64 v[21:22], v[28:29], v[28:29]
	v_fma_f64 v[30:31], v[28:29], v[38:39], s[38:39]
	v_fma_f64 v[38:39], v[16:17], -v[18:19], v[40:41]
	v_fma_f64 v[18:19], v[28:29], v[32:33], -v[18:19]
	v_fma_f64 v[28:29], v[46:47], v[34:35], v[36:37]
	v_fma_f64 v[14:15], v[48:49], s[54:55], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], v[21:22], v[30:31], v[38:39]
	v_fma_f64 v[18:19], v[54:55], s[54:55], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[42:43], v[28:29]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[44:45], v[21:22]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_and_b32_e32 v18, 1, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_and_b32_e32 v18, 1, v20
	v_cmp_eq_u32_e64 s1, 0, v18
	v_cndmask_b32_e32 v12, v12, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v14, v16, s1
	v_cndmask_b32_e64 v14, v15, v17, s1
	v_cndmask_b32_e64 v11, 0, v11, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v14, v14, v10
	v_cndmask_b32_e64 v10, 0, v12, s0
	v_cndmask_b32_e64 v12, 0x7ff80000, v14, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[14:15], v[7:8], v[11:12]
	v_lshlrev_b32_e32 v11, 30, v27
	v_xor_b32_e32 v12, 0x80000000, v13
	v_dual_cndmask_b32 v12, v12, v29 :: v_dual_and_b32 v11, 0x80000000, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v11, v12, v11
	v_cndmask_b32_e64 v11, 0x7ff80000, v11, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[5:6], v[10:11], v[14:15]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[10:11], v[10:11], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f64_e32 v[12:13], v[10:11]
	v_add_f64 v[14:15], v[10:11], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f64_e64 s0, |v[14:15]|, 0.5
	v_cndmask_b32_e64 v10, 0, 0x3ff00000, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v10, 0x7fffffff, v10, v11
	v_add_f64 v[10:11], v[12:13], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], 0x40668000, v[10:11]
	v_cvt_i32_f64_e32 v10, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_u32 v10, vcc_lo, s10, v10
	s_add_u32 s10, s10, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	s_addc_u32 s11, s11, 0
	s_cmpk_eq_i32 s10, 0xb4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s4, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	global_atomic_add_u32 v[10:11], v26, off
	s_cbranch_scc0 .LBB0_9
; %bb.20:
	v_add_co_u32 v8, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v25, vcc_lo
	v_dual_mov_b32 v4, 0xff :: v_dual_mov_b32 v7, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, v8, s2
	v_mov_b32_e32 v6, v1
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v9, vcc_lo
	s_clause 0x1
	global_store_b8 v[8:9], v4, off
	global_store_b8 v[10:11], v4, off
.LBB0_21:                               ; %Flow233
	s_or_b32 exec_lo, exec_lo, s33
	v_lshl_add_u32 v2, s2, 1, v24
	v_add_co_u32 v0, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_mov_b32_e32 v5, 0xff
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_clause 0x1
	global_store_b8 v[0:1], v4, off
	global_store_b8 v[2:3], v5, off
.LBB0_22:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12computeAccumPhS_Pjiiiid
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 58
		.amdhsa_next_free_sgpr 56
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12computeAccumPhS_Pjiiiid, .Lfunc_end0-_Z12computeAccumPhS_Pjiiiid
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3432
; NumSgprs: 58
; NumVgprs: 58
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 58
; NumVGPRsForWavesPerEU: 58
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12computeAccumPhS_Pjiiiid
    .private_segment_fixed_size: 0
    .sgpr_count:     58
    .sgpr_spill_count: 0
    .symbol:         _Z12computeAccumPhS_Pjiiiid.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     58
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
