/***************************************************************************
 *
 *            (C) Copyright 2010 The Board of Trustees of the
 *                        University of Illinois
 *                         All Rights Reserved
 *
 ***************************************************************************/

#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>

#include "UDTypes.h"

#define TILE 64
#define LOG_TILE 6

__constant__ float cutoff2_c;
__constant__ float cutoff_c;
__constant__ int gridSize_c[3];
__constant__ int size_xy_c;
__constant__ float _1overCutoff2_c;

__global__ void binning_kernel (unsigned int n, ReconstructionSample* sample_g, unsigned int* idxKey_g,
                                unsigned int* idxValue_g, unsigned int* binCount_g, unsigned int binsize, unsigned int gridNumElems){
  unsigned int key;
  unsigned int sampleIdx = blockIdx.x*blockDim.x+threadIdx.x;
  ReconstructionSample pt;
  unsigned int binIdx;
  unsigned int count;

  if (sampleIdx < n){
    pt = sample_g[sampleIdx];

    binIdx = (unsigned int)(pt.kZ)*size_xy_c + (unsigned int)(pt.kY)*gridSize_c[0] + (unsigned int)(pt.kX);

    count = atomicAdd(binCount_g+binIdx, 1);
    if (count < binsize){
      key = binIdx;
    } else {
      atomicSub(binCount_g+binIdx, 1);
      key = gridNumElems;
    }

    idxKey_g[sampleIdx] = key;
    idxValue_g[sampleIdx] = sampleIdx;
  }
}

__global__ void reorder_kernel(int n, unsigned int* idxValue_g, ReconstructionSample* samples_g, ReconstructionSample* sortedSample_g){
  unsigned int index = blockIdx.x*blockDim.x + threadIdx.x;
  unsigned int old_index;
  ReconstructionSample pt;

  if (index < n){
    old_index = idxValue_g[index];
    pt = samples_g[old_index];
    sortedSample_g[index] = pt;
  }
}

__device__ float kernel_value(float v){

  float rValue = 0;

  float z = v*v;

  // polynomials taken from http://ccrma.stanford.edu/CCRMA/Courses/422/projects/kbd/kbdwindow.cpp
  float num = (z* (z* (z* (z* (z* (z* (z* (z* (z* (z* (z* (z* (z*
                (z* 0.210580722890567e-22f  + 0.380715242345326e-19f ) +
                 0.479440257548300e-16f) + 0.435125971262668e-13f ) +
                 0.300931127112960e-10f) + 0.160224679395361e-7f  ) +
                 0.654858370096785e-5f)  + 0.202591084143397e-2f  ) +
                 0.463076284721000e0f)   + 0.754337328948189e2f   ) +
                 0.830792541809429e4f)   + 0.571661130563785e6f   ) +
                 0.216415572361227e8f)   + 0.356644482244025e9f   ) +
                 0.144048298227235e10f);

  float den = (z*(z*(z-0.307646912682801e4f)+0.347626332405882e7f)-0.144048298227235e10f);

  rValue = __fdividef(-num,den);

  return rValue;
}

__global__ void gridding_GPU (ReconstructionSample* sample_g, unsigned int* binStartAddr_g, float2* gridData_g, float* sampleDensity_g, float beta){
  __shared__ ReconstructionSample sharedBin[TILE];

  const int flatIdx = threadIdx.z*blockDim.y*blockDim.x+threadIdx.y*blockDim.x+threadIdx.x;

  // figure out starting point of the tile
  const int z0 = blockDim.z*(blockIdx.y/(gridSize_c[1]/blockDim.y));
  const int y0 = blockDim.y*(blockIdx.y%(gridSize_c[1]/blockDim.y));
  const int x0 = blockIdx.x*blockDim.x;

  const int X  = x0+threadIdx.x;
  const int Y  = y0+threadIdx.y;
  const int Z  = z0+threadIdx.z;

  const int xl = x0-ceil(cutoff_c);
  const int xL = (xl < 0) ? 0 : xl;
  const int xh = x0+blockDim.x+cutoff_c;
  const int xH = (xh >= gridSize_c[0]) ? gridSize_c[0]-1 : xh;

  const int yl = y0-ceil(cutoff_c);
  const int yL = (yl < 0) ? 0 : yl;
  const int yh = y0+blockDim.y+cutoff_c;
  const int yH = (yh >= gridSize_c[1]) ? gridSize_c[1]-1 : yh;

  const int zl = z0-ceil(cutoff_c);
  const int zL = (zl < 0) ? 0 : zl;
  const int zh = z0+blockDim.z+cutoff_c;
  const int zH = (zh >= gridSize_c[2]) ? gridSize_c[2]-1 : zh;

  const int idx = Z*size_xy_c + Y*gridSize_c[0] + X;

  float2 pt;
  pt.x = 0.0;
  pt.y = 0.0;
  float density = 0.0;

  for (int z = zL; z <= zH; z++){
    for (int y = yL; y <= yH; y++){
      const unsigned int *addr = binStartAddr_g+z*size_xy_c+ y*gridSize_c[0];
      const unsigned int start = *(addr+xL);
      const unsigned int end   = *(addr+xH+1);
      const unsigned int delta = end-start;
      for (int x = 0; x < ((delta+TILE-1)>>LOG_TILE); x++){
        int tileSize = ((delta-(x<<LOG_TILE)) > TILE) ? TILE : (delta-(x<<LOG_TILE));
        int globalIdx = flatIdx+(x<<LOG_TILE);
        __syncthreads();
        if(flatIdx < tileSize){
          sharedBin[flatIdx] = sample_g[start+globalIdx];
        }
        __syncthreads();

        for (int j=0; j< tileSize; j++){
          const float real = sharedBin[j].real;
          const float imag = sharedBin[j].imag;
          const float sdc = sharedBin[j].sdc;

          if((real != 0.0 || imag != 0.0) && sdc != 0.0){
            float v = (sharedBin[j].kX-X)*(sharedBin[j].kX-X);
            v += (sharedBin[j].kY-Y)*(sharedBin[j].kY-Y);
            v += (sharedBin[j].kZ-Z)*(sharedBin[j].kZ-Z);
            if(v<cutoff2_c){
              const float w = kernel_value(beta*sqrtf(1.0-(v*_1overCutoff2_c))) *sdc;
              pt.x += w*real;
              pt.y += w*imag;
              density += 1.0;
            }
          }
        }
      }
    }
  }

  gridData_g[idx] = pt;
  sampleDensity_g[idx] = density;
}


	.file	"tmpxft_00250cca_00000000-6_GPU_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12kernel_valuef
	.type	_Z12kernel_valuef, @function
_Z12kernel_valuef:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z12kernel_valuef, .-_Z12kernel_valuef
	.globl	_Z66__device_stub__Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jjjP20ReconstructionSamplePjS1_S1_jj
	.type	_Z66__device_stub__Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jjjP20ReconstructionSamplePjS1_S1_jj, @function
_Z66__device_stub__Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jjjP20ReconstructionSamplePjS1_S1_jj:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L4:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z66__device_stub__Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jjjP20ReconstructionSamplePjS1_S1_jj, .-_Z66__device_stub__Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jjjP20ReconstructionSamplePjS1_S1_jj
	.globl	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.type	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj, @function
_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z66__device_stub__Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jjjP20ReconstructionSamplePjS1_S1_jj
	.cfi_endproc
.LFE2053:
	.size	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj, .-_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.globl	_Z61__device_stub__Z14reorder_kerneliPjP20ReconstructionSampleS1_iPjP20ReconstructionSampleS1_
	.type	_Z61__device_stub__Z14reorder_kerneliPjP20ReconstructionSampleS1_iPjP20ReconstructionSampleS1_, @function
_Z61__device_stub__Z14reorder_kerneliPjP20ReconstructionSampleS1_iPjP20ReconstructionSampleS1_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14reorder_kerneliPjP20ReconstructionSampleS1_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z61__device_stub__Z14reorder_kerneliPjP20ReconstructionSampleS1_iPjP20ReconstructionSampleS1_, .-_Z61__device_stub__Z14reorder_kerneliPjP20ReconstructionSampleS1_iPjP20ReconstructionSampleS1_
	.globl	_Z14reorder_kerneliPjP20ReconstructionSampleS1_
	.type	_Z14reorder_kerneliPjP20ReconstructionSampleS1_, @function
_Z14reorder_kerneliPjP20ReconstructionSampleS1_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z14reorder_kerneliPjP20ReconstructionSampleS1_iPjP20ReconstructionSampleS1_
	.cfi_endproc
.LFE2055:
	.size	_Z14reorder_kerneliPjP20ReconstructionSampleS1_, .-_Z14reorder_kerneliPjP20ReconstructionSampleS1_
	.globl	_Z66__device_stub__Z12gridding_GPUP20ReconstructionSamplePjP6float2PffP20ReconstructionSamplePjP6float2Pff
	.type	_Z66__device_stub__Z12gridding_GPUP20ReconstructionSamplePjP6float2PffP20ReconstructionSamplePjP6float2Pff, @function
_Z66__device_stub__Z12gridding_GPUP20ReconstructionSamplePjP6float2PffP20ReconstructionSamplePjP6float2Pff:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z12gridding_GPUP20ReconstructionSamplePjP6float2Pff(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L15:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z66__device_stub__Z12gridding_GPUP20ReconstructionSamplePjP6float2PffP20ReconstructionSamplePjP6float2Pff, .-_Z66__device_stub__Z12gridding_GPUP20ReconstructionSamplePjP6float2PffP20ReconstructionSamplePjP6float2Pff
	.globl	_Z12gridding_GPUP20ReconstructionSamplePjP6float2Pff
	.type	_Z12gridding_GPUP20ReconstructionSamplePjP6float2Pff, @function
_Z12gridding_GPUP20ReconstructionSamplePjP6float2Pff:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z66__device_stub__Z12gridding_GPUP20ReconstructionSamplePjP6float2PffP20ReconstructionSamplePjP6float2Pff
	.cfi_endproc
.LFE2057:
	.size	_Z12gridding_GPUP20ReconstructionSamplePjP6float2Pff, .-_Z12gridding_GPUP20ReconstructionSamplePjP6float2Pff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12gridding_GPUP20ReconstructionSamplePjP6float2Pff"
.LC1:
	.string	"_Z14reorder_kerneliPjP20ReconstructionSampleS1_"
.LC2:
	.string	"_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj"
.LC3:
	.string	"cutoff2_c"
.LC4:
	.string	"cutoff_c"
.LC5:
	.string	"gridSize_c"
.LC6:
	.string	"size_xy_c"
.LC7:
	.string	"_1overCutoff2_c"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12gridding_GPUP20ReconstructionSamplePjP6float2Pff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14reorder_kerneliPjP20ReconstructionSampleS1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$4, %r9d
	leaq	_ZL9cutoff2_c(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL8cutoff_c(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$12, %r9d
	leaq	_ZL10gridSize_c(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL9size_xy_c(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$4, %r9d
	movq	%rdx, %rcx
	leaq	_ZL15_1overCutoff2_c(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL15_1overCutoff2_c
	.comm	_ZL15_1overCutoff2_c,4,4
	.local	_ZL9size_xy_c
	.comm	_ZL9size_xy_c,4,4
	.local	_ZL10gridSize_c
	.comm	_ZL10gridSize_c,12,8
	.local	_ZL8cutoff_c
	.comm	_ZL8cutoff_c,4,4
	.local	_ZL9cutoff2_c
	.comm	_ZL9cutoff2_c,4,4
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/***************************************************************************
 *
 *            (C) Copyright 2010 The Board of Trustees of the
 *                        University of Illinois
 *                         All Rights Reserved
 *
 ***************************************************************************/

#include <stdio.h>
#include <hip/hip_runtime.h>

#include <math.h>
#include <stdlib.h>
#include <string.h>

#include "UDTypes.h"

#define TILE 64
#define LOG_TILE 6

__constant__ float cutoff2_c;
__constant__ float cutoff_c;
__constant__ int gridSize_c[3];
__constant__ int size_xy_c;
__constant__ float _1overCutoff2_c;

__global__ void binning_kernel (unsigned int n, ReconstructionSample* sample_g, unsigned int* idxKey_g,
                                unsigned int* idxValue_g, unsigned int* binCount_g, unsigned int binsize, unsigned int gridNumElems){
  unsigned int key;
  unsigned int sampleIdx = blockIdx.x*blockDim.x+threadIdx.x;
  ReconstructionSample pt;
  unsigned int binIdx;
  unsigned int count;

  if (sampleIdx < n){
    pt = sample_g[sampleIdx];

    binIdx = (unsigned int)(pt.kZ)*size_xy_c + (unsigned int)(pt.kY)*gridSize_c[0] + (unsigned int)(pt.kX);

    count = atomicAdd(binCount_g+binIdx, 1);
    if (count < binsize){
      key = binIdx;
    } else {
      atomicSub(binCount_g+binIdx, 1);
      key = gridNumElems;
    }

    idxKey_g[sampleIdx] = key;
    idxValue_g[sampleIdx] = sampleIdx;
  }
}

__global__ void reorder_kernel(int n, unsigned int* idxValue_g, ReconstructionSample* samples_g, ReconstructionSample* sortedSample_g){
  unsigned int index = blockIdx.x*blockDim.x + threadIdx.x;
  unsigned int old_index;
  ReconstructionSample pt;

  if (index < n){
    old_index = idxValue_g[index];
    pt = samples_g[old_index];
    sortedSample_g[index] = pt;
  }
}

__device__ float kernel_value(float v){

  float rValue = 0;

  float z = v*v;

  // polynomials taken from http://ccrma.stanford.edu/CCRMA/Courses/422/projects/kbd/kbdwindow.cpp
  float num = (z* (z* (z* (z* (z* (z* (z* (z* (z* (z* (z* (z* (z*
                (z* 0.210580722890567e-22f  + 0.380715242345326e-19f ) +
                 0.479440257548300e-16f) + 0.435125971262668e-13f ) +
                 0.300931127112960e-10f) + 0.160224679395361e-7f  ) +
                 0.654858370096785e-5f)  + 0.202591084143397e-2f  ) +
                 0.463076284721000e0f)   + 0.754337328948189e2f   ) +
                 0.830792541809429e4f)   + 0.571661130563785e6f   ) +
                 0.216415572361227e8f)   + 0.356644482244025e9f   ) +
                 0.144048298227235e10f);

  float den = (z*(z*(z-0.307646912682801e4f)+0.347626332405882e7f)-0.144048298227235e10f);

  rValue = __fdividef(-num,den);

  return rValue;
}

__global__ void gridding_GPU (ReconstructionSample* sample_g, unsigned int* binStartAddr_g, float2* gridData_g, float* sampleDensity_g, float beta){
  __shared__ ReconstructionSample sharedBin[TILE];

  const int flatIdx = threadIdx.z*blockDim.y*blockDim.x+threadIdx.y*blockDim.x+threadIdx.x;

  // figure out starting point of the tile
  const int z0 = blockDim.z*(blockIdx.y/(gridSize_c[1]/blockDim.y));
  const int y0 = blockDim.y*(blockIdx.y%(gridSize_c[1]/blockDim.y));
  const int x0 = blockIdx.x*blockDim.x;

  const int X  = x0+threadIdx.x;
  const int Y  = y0+threadIdx.y;
  const int Z  = z0+threadIdx.z;

  const int xl = x0-ceil(cutoff_c);
  const int xL = (xl < 0) ? 0 : xl;
  const int xh = x0+blockDim.x+cutoff_c;
  const int xH = (xh >= gridSize_c[0]) ? gridSize_c[0]-1 : xh;

  const int yl = y0-ceil(cutoff_c);
  const int yL = (yl < 0) ? 0 : yl;
  const int yh = y0+blockDim.y+cutoff_c;
  const int yH = (yh >= gridSize_c[1]) ? gridSize_c[1]-1 : yh;

  const int zl = z0-ceil(cutoff_c);
  const int zL = (zl < 0) ? 0 : zl;
  const int zh = z0+blockDim.z+cutoff_c;
  const int zH = (zh >= gridSize_c[2]) ? gridSize_c[2]-1 : zh;

  const int idx = Z*size_xy_c + Y*gridSize_c[0] + X;

  float2 pt;
  pt.x = 0.0;
  pt.y = 0.0;
  float density = 0.0;

  for (int z = zL; z <= zH; z++){
    for (int y = yL; y <= yH; y++){
      const unsigned int *addr = binStartAddr_g+z*size_xy_c+ y*gridSize_c[0];
      const unsigned int start = *(addr+xL);
      const unsigned int end   = *(addr+xH+1);
      const unsigned int delta = end-start;
      for (int x = 0; x < ((delta+TILE-1)>>LOG_TILE); x++){
        int tileSize = ((delta-(x<<LOG_TILE)) > TILE) ? TILE : (delta-(x<<LOG_TILE));
        int globalIdx = flatIdx+(x<<LOG_TILE);
        __syncthreads();
        if(flatIdx < tileSize){
          sharedBin[flatIdx] = sample_g[start+globalIdx];
        }
        __syncthreads();

        for (int j=0; j< tileSize; j++){
          const float real = sharedBin[j].real;
          const float imag = sharedBin[j].imag;
          const float sdc = sharedBin[j].sdc;

          if((real != 0.0 || imag != 0.0) && sdc != 0.0){
            float v = (sharedBin[j].kX-X)*(sharedBin[j].kX-X);
            v += (sharedBin[j].kY-Y)*(sharedBin[j].kY-Y);
            v += (sharedBin[j].kZ-Z)*(sharedBin[j].kZ-Z);
            if(v<cutoff2_c){
              const float w = kernel_value(beta*sqrtf(1.0-(v*_1overCutoff2_c))) *sdc;
              pt.x += w*real;
              pt.y += w*imag;
              density += 1.0;
            }
          }
        }
      }
    }
  }

  gridData_g[idx] = pt;
  sampleDensity_g[idx] = density;
}


	.text
	.file	"GPU_kernels.hip"
	.globl	_Z29__device_stub__binning_kerneljP20ReconstructionSamplePjS1_S1_jj # -- Begin function _Z29__device_stub__binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.type	_Z29__device_stub__binning_kerneljP20ReconstructionSamplePjS1_S1_jj,@function
_Z29__device_stub__binning_kerneljP20ReconstructionSamplePjS1_S1_jj: # @_Z29__device_stub__binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__binning_kerneljP20ReconstructionSamplePjS1_S1_jj, .Lfunc_end0-_Z29__device_stub__binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__reorder_kerneliPjP20ReconstructionSampleS1_ # -- Begin function _Z29__device_stub__reorder_kerneliPjP20ReconstructionSampleS1_
	.type	_Z29__device_stub__reorder_kerneliPjP20ReconstructionSampleS1_,@function
_Z29__device_stub__reorder_kerneliPjP20ReconstructionSampleS1_: # @_Z29__device_stub__reorder_kerneliPjP20ReconstructionSampleS1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14reorder_kerneliPjP20ReconstructionSampleS1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__reorder_kerneliPjP20ReconstructionSampleS1_, .Lfunc_end1-_Z29__device_stub__reorder_kerneliPjP20ReconstructionSampleS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff # -- Begin function _Z27__device_stub__gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.type	_Z27__device_stub__gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff,@function
_Z27__device_stub__gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff: # @_Z27__device_stub__gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z27__device_stub__gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff, .Lfunc_end2-_Z27__device_stub__gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14reorder_kerneliPjP20ReconstructionSampleS1_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$cutoff2_c, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$cutoff_c, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$gridSize_c, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movl	$12, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$size_xy_c, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$_1overCutoff2_c, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	cutoff2_c,@object               # @cutoff2_c
	.local	cutoff2_c
	.comm	cutoff2_c,4,4
	.type	cutoff_c,@object                # @cutoff_c
	.local	cutoff_c
	.comm	cutoff_c,4,4
	.type	gridSize_c,@object              # @gridSize_c
	.local	gridSize_c
	.comm	gridSize_c,12,4
	.type	size_xy_c,@object               # @size_xy_c
	.local	size_xy_c
	.comm	size_xy_c,4,4
	.type	_1overCutoff2_c,@object         # @_1overCutoff2_c
	.local	_1overCutoff2_c
	.comm	_1overCutoff2_c,4,4
	.type	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj,@object # @_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.section	.rodata,"a",@progbits
	.globl	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.p2align	3, 0x0
_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj:
	.quad	_Z29__device_stub__binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.size	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj, 8

	.type	_Z14reorder_kerneliPjP20ReconstructionSampleS1_,@object # @_Z14reorder_kerneliPjP20ReconstructionSampleS1_
	.globl	_Z14reorder_kerneliPjP20ReconstructionSampleS1_
	.p2align	3, 0x0
_Z14reorder_kerneliPjP20ReconstructionSampleS1_:
	.quad	_Z29__device_stub__reorder_kerneliPjP20ReconstructionSampleS1_
	.size	_Z14reorder_kerneliPjP20ReconstructionSampleS1_, 8

	.type	_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff,@object # @_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.globl	_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.p2align	3, 0x0
_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff:
	.quad	_Z27__device_stub__gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.size	_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj"
	.size	.L__unnamed_1, 53

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14reorder_kerneliPjP20ReconstructionSampleS1_"
	.size	.L__unnamed_2, 48

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff"
	.size	.L__unnamed_3, 70

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"cutoff2_c"
	.size	.L__unnamed_4, 10

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"cutoff_c"
	.size	.L__unnamed_5, 9

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"gridSize_c"
	.size	.L__unnamed_6, 11

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"size_xy_c"
	.size	.L__unnamed_7, 10

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_1overCutoff2_c"
	.size	.L__unnamed_8, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.addrsig_sym _Z29__device_stub__reorder_kerneliPjP20ReconstructionSampleS1_
	.addrsig_sym _Z27__device_stub__gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym cutoff2_c
	.addrsig_sym cutoff_c
	.addrsig_sym gridSize_c
	.addrsig_sym size_xy_c
	.addrsig_sym _1overCutoff2_c
	.addrsig_sym _Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.addrsig_sym _Z14reorder_kerneliPjP20ReconstructionSampleS1_
	.addrsig_sym _Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj ; -- Begin function _Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.globl	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
	.p2align	8
	.type	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj,@function
_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj: ; @_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x8
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, size_xy_c@rel32@lo+4
	s_addc_u32 s3, s3, size_xy_c@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, v1, 24, s[4:5]
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gridSize_c@rel32@lo+4
	s_addc_u32 s5, s5, gridSize_c@rel32@hi+12
	global_load_b96 v[3:5], v[2:3], off offset:8
	s_load_b32 s2, s[2:3], 0x0
	s_load_b32 s3, s[4:5], 0x0
	s_waitcnt vmcnt(0)
	v_cvt_u32_f32_e32 v0, v5
	v_cvt_u32_f32_e32 v2, v4
	v_cvt_u32_f32_e32 v3, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, s2, v0
	v_mul_lo_u32 v5, s3, v2
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v4, v2
	v_add3_u32 v3, v0, v3, v5
	v_mov_b32_e32 v0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_add_co_u32 v4, vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_atomic_add_u32 v0, v[4:5], v0, off glc
	s_waitcnt vmcnt(0)
	v_cmp_le_u32_e32 vcc_lo, s0, v0
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v3, s1
	global_atomic_add_u32 v[4:5], v0, off
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_store_b32 v[6:7], v3, off
	global_store_b32 v[4:5], v1, off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj, .Lfunc_end0-_Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 352
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14reorder_kerneliPjP20ReconstructionSampleS1_ ; -- Begin function _Z14reorder_kerneliPjP20ReconstructionSampleS1_
	.globl	_Z14reorder_kerneliPjP20ReconstructionSampleS1_
	.p2align	8
	.type	_Z14reorder_kerneliPjP20ReconstructionSampleS1_,@function
_Z14reorder_kerneliPjP20ReconstructionSampleS1_: ; @_Z14reorder_kerneliPjP20ReconstructionSampleS1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_mov_b32_e32 v2, 0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	v_mad_u64_u32 v[8:9], null, v1, 24, s[0:1]
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v0, 24, s[6:7]
	s_clause 0x1
	global_load_b64 v[6:7], v[2:3], off offset:16
	global_load_b128 v[2:5], v[2:3], off
	s_waitcnt vmcnt(1)
	global_store_b64 v[8:9], v[6:7], off offset:16
	s_waitcnt vmcnt(0)
	global_store_b128 v[8:9], v[2:5], off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14reorder_kerneliPjP20ReconstructionSampleS1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14reorder_kerneliPjP20ReconstructionSampleS1_, .Lfunc_end1-_Z14reorder_kerneliPjP20ReconstructionSampleS1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff ; -- Begin function _Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.globl	_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
	.p2align	8
	.type	_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff,@function
_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff: ; @_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x34
	v_bfe_u32 v10, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	v_mov_b32_e32 v9, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s16, s2, 16
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gridSize_c@rel32@lo+4
	s_addc_u32 s5, s5, gridSize_c@rel32@hi+12
	v_cvt_f32_u32_e32 v1, s16
	s_load_b64 s[12:13], s[4:5], 0x0
	s_sub_i32 s7, 0, s16
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, gridSize_c@rel32@lo+12
	s_addc_u32 s5, s5, gridSize_c@rel32@hi+20
	s_and_b32 s3, s3, 0xffff
	v_rcp_iflag_f32_e32 v1, v1
	s_load_b32 s20, s[4:5], 0x0
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s14, s14, s2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v1
	s_mul_i32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s6, s7
	s_add_i32 s6, s6, s7
	s_waitcnt lgkmcnt(0)
	s_mul_hi_u32 s4, s13, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s4, s16
	s_add_i32 s6, s4, 1
	s_sub_i32 s5, s13, s5
	s_sub_i32 s7, s5, s16
	s_cmp_ge_u32 s5, s16
	s_cselect_b32 s4, s6, s4
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s4, 1
	s_cmp_ge_u32 s5, s16
	s_cselect_b32 s21, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s21
	s_sub_i32 s5, 0, s21
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, s4
	s_mul_hi_u32 s5, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s4, s5
	s_mul_hi_u32 s4, s15, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s4, s21
	s_add_i32 s6, s4, 1
	s_sub_i32 s5, s15, s5
	s_sub_i32 s7, s5, s21
	s_cmp_ge_u32 s5, s21
	s_cselect_b32 s4, s6, s4
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s4, 1
	s_cmp_ge_u32 s5, s21
	s_cselect_b32 s22, s6, s4
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, cutoff_c@rel32@lo+4
	s_addc_u32 s5, s5, cutoff_c@rel32@hi+12
	s_mul_i32 s23, s22, s3
	s_load_b32 s17, s[4:5], 0x0
	s_add_i32 s3, s23, s3
	v_cvt_f32_i32_e32 v1, s23
	v_cvt_f32_u32_e32 v4, s3
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, size_xy_c@rel32@lo+4
	s_addc_u32 s19, s19, size_xy_c@rel32@hi+12
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s18, s[18:19], 0x0
	s_add_i32 s19, s20, -1
	s_mul_i32 s22, s22, s21
	v_add_nc_u32_e32 v7, s23, v3
	s_sub_i32 s15, s15, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s16
	v_add_nc_u32_e32 v6, s15, v10
	s_waitcnt lgkmcnt(0)
	v_ceil_f32_e32 v2, s17
	v_add_f32_e32 v5, s17, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v1, v2 :: v_dual_and_b32 v4, 0x3ff, v0
	v_cvt_i32_f32_e32 v0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v1, v5
	v_add_nc_u32_e32 v5, s14, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s3, v0
	v_cmp_gt_i32_e32 vcc_lo, s20, v1
	v_mov_b32_e32 v0, 0
	v_dual_cndmask_b32 v8, s19, v1 :: v_dual_mov_b32 v1, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_max_i32 s19, s3, 0
	s_mov_b32 s3, 0
	v_cmp_gt_i32_e32 vcc_lo, s19, v8
	s_cbranch_vccnz .LBB2_18
; %bb.1:                                ; %.preheader.lr.ph
	s_add_i32 s20, s14, s2
	v_cvt_f32_i32_e32 v0, s15
	v_cvt_f32_u32_e32 v1, s20
	s_add_i32 s15, s15, s16
	v_mad_u32_u24 v9, v3, s16, v10
	v_cvt_f32_u32_e32 v10, s15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v0, v0, v2 :: v_dual_add_f32 v1, s17, v1
	s_load_b32 s20, s[0:1], 0x20
	v_cvt_f32_i32_e32 v3, s14
	s_add_i32 s24, s13, -1
	v_cvt_i32_f32_e32 v0, v0
	v_cvt_i32_f32_e32 v1, v1
	s_add_i32 s14, s12, -1
	v_cvt_f32_i32_e32 v12, v5
	v_cvt_f32_i32_e32 v13, v6
	v_readfirstlane_b32 s0, v0
	v_readfirstlane_b32 s1, v1
	v_add_f32_e32 v1, s17, v10
	v_sub_f32_e32 v0, v3, v2
	v_mad_u64_u32 v[2:3], null, v9, s2, v[4:5]
	s_max_i32 s21, s0, 0
	s_cmp_gt_i32 s12, s1
	v_cvt_i32_f32_e32 v1, v1
	s_cselect_b32 s16, s1, s14
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, cutoff2_c@rel32@lo+4
	s_addc_u32 s1, s1, cutoff2_c@rel32@hi+12
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, _1overCutoff2_c@rel32@lo+4
	s_addc_u32 s15, s15, _1overCutoff2_c@rel32@hi+12
	s_load_b32 s22, s[0:1], 0x0
	s_load_b32 s23, s[14:15], 0x0
	v_cmp_gt_i32_e32 vcc_lo, s13, v1
	v_mul_lo_u32 v11, v2, 24
	v_cvt_f32_i32_e32 v14, v7
	v_mov_b32_e32 v9, 0
	s_ashr_i32 s17, s16, 31
	v_dual_cndmask_b32 v10, s24, v1 :: v_dual_mov_b32 v1, 0
	v_cvt_i32_f32_e32 v0, v0
	s_lshl_b64 s[16:17], s[16:17], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e64 s0, s21, v10
	v_readfirstlane_b32 s2, v0
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_max_i32 s2, s2, 0
	s_lshl_b64 s[14:15], s[2:3], 2
	s_mov_b32 s3, 0x19cba943
.LBB2_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
                                        ;       Child Loop BB2_6 Depth 3
                                        ;         Child Loop BB2_10 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_17
; %bb.3:                                ; %.lr.ph138
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mul_i32 s24, s19, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s25, s24, 31
	s_lshl_b64 s[24:25], s[24:25], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s13, s6, s24
	s_addc_u32 s24, s7, s25
	s_mov_b32 s25, s21
.LBB2_4:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_6 Depth 3
                                        ;         Child Loop BB2_10 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s26, s25, s12
	s_ashr_i32 s27, s26, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[26:27], s[26:27], 2
	s_add_u32 s1, s13, s26
	s_addc_u32 s2, s24, s27
	s_add_u32 s26, s1, s14
	s_addc_u32 s27, s2, s15
	s_add_u32 s28, s1, s16
	s_addc_u32 s29, s2, s17
	s_clause 0x1
	s_load_b32 s1, s[26:27], 0x0
	s_load_b32 s2, s[28:29], 0x4
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s26, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s26, 63
	s_cmp_lt_u32 s2, 64
	s_cbranch_scc1 .LBB2_16
; %bb.5:                                ; %.lr.ph128
                                        ;   in Loop: Header=BB2_4 Depth=2
	v_add_nc_u32_e32 v15, s1, v2
	s_lshr_b32 s27, s2, 6
	s_mov_b32 s28, 0
	s_mov_b32 s29, s26
.LBB2_6:                                ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB2_10 Depth 4
	s_lshl_b32 s1, s28, 6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s2, s26, s1
	s_barrier
	s_min_u32 s2, s2, 64
	buffer_gl0_inv
	v_cmp_gt_i32_e32 vcc_lo, s2, v2
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_8
; %bb.7:                                ;   in Loop: Header=BB2_6 Depth=3
	v_add_nc_u32_e32 v16, s1, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v16, 24, s[4:5]
	s_clause 0x1
	global_load_b128 v[16:19], v[3:4], off offset:8
	global_load_b128 v[20:23], v[3:4], off
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v11, v18, v19 offset0:4 offset1:5
	ds_store_2addr_b32 v11, v16, v17 offset0:2 offset1:3
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v11, v22, v23 offset0:2 offset1:3
	ds_store_2addr_b32 v11, v20, v21 offset1:1
.LBB2_8:                                ;   in Loop: Header=BB2_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_eq_u32 s26, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_15
; %bb.9:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB2_6 Depth=3
	v_med3_u32 v16, s29, 1, 64
	s_mov_b32 s30, 0
.LBB2_10:                               ; %.lr.ph
                                        ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_4 Depth=2
                                        ;       Parent Loop BB2_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v17, s30
	ds_load_b64 v[3:4], v17
	ds_load_b32 v17, v17 offset:20
	s_waitcnt lgkmcnt(1)
	v_cmp_neq_f32_e32 vcc_lo, 0, v3
	v_cmp_neq_f32_e64 s1, 0, v4
	s_waitcnt lgkmcnt(0)
	v_cmp_neq_f32_e64 s2, 0, v17
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_14
; %bb.11:                               ;   in Loop: Header=BB2_10 Depth=4
	v_mov_b32_e32 v20, s30
	s_mov_b32 s2, exec_lo
	ds_load_b64 v[18:19], v20 offset:8
	ds_load_b32 v20, v20 offset:16
	s_waitcnt lgkmcnt(1)
	v_sub_f32_e32 v19, v19, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v21, v18, v12 :: v_dual_mul_f32 v18, v19, v19
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v19, v20, v14 :: v_dual_fmac_f32 v18, v21, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v19, v19
	v_cmpx_gt_f32_e32 s22, v18
	s_cbranch_execz .LBB2_13
; %bb.12:                               ;   in Loop: Header=BB2_10 Depth=4
	v_fma_f32 v18, -v18, s23, 1.0
	v_add_f32_e32 v9, 1.0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x4f800000, v18
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v18
	v_cndmask_b32_e32 v18, v18, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v19, v18
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v20, -1, v19
	v_add_nc_u32_e32 v21, 1, v19
	v_fma_f32 v22, -v20, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, -v21, v19, v18
	v_cmp_ge_f32_e64 s1, 0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v20, s1
	v_cmp_lt_f32_e64 s1, 0, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v19, v19, v21, s1
	v_mul_f32_e32 v20, 0x37800000, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, v19, v20, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v18, 0x260
	v_cndmask_b32_e32 v18, v19, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, s20, v18
	v_mul_f32_e32 v19, v18, v18
	v_fmaak_f32 v18, v18, v18, 0xc5404782
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v20, s3, v19, 0x1f33c9a6
	v_fmaak_f32 v18, v19, v18, 0x4a542c9d
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v20, v19, v20, 0x245d1a51
	v_fmaak_f32 v18, v19, v18, 0xceabb80d
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v20, v19, v20, 0x2943f69c
	v_fmaak_f32 v20, v19, v20, 0x2e0459d5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v20, v19, v20, 0x3289a1c8
	v_fmaak_f32 v20, v19, v20, 0x36dbbbe8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v20, v19, v20, 0x3b04c525
	v_fmaak_f32 v20, v19, v20, 0x3eed1856
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v20, v19, v20, 0x4296de12
	v_fmaak_f32 v20, v19, v20, 0x4601cfb4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v20, v19, v20, 0x490b90d2
	v_fmaak_f32 v20, v19, v20, 0x4ba51cab
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v20, v19, v20, 0x4daa0fb4
	v_fmaak_f32 v19, v19, v20, 0x4eabb80d
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v20, null, v18, v18, -v19
	v_div_scale_f32 v23, vcc_lo, -v19, v18, -v19
	v_rcp_f32_e32 v21, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v20, v21, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v22, v21
	v_mul_f32_e32 v22, v23, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v20, v22, v23
	v_fmac_f32_e32 v22, v24, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, -v20, v22, v23
	v_div_fmas_f32 v20, v20, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v18, v20, v18, -v19
	v_mul_f32_e32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, v3, v17
	v_fmac_f32_e32 v1, v4, v17
.LBB2_13:                               ; %Flow
                                        ;   in Loop: Header=BB2_10 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_14:                               ;   in Loop: Header=BB2_10 Depth=4
	v_add_nc_u32_e32 v16, -1, v16
	s_add_i32 s30, s30, 24
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v16
	s_cbranch_vccz .LBB2_10
.LBB2_15:                               ; %._crit_edge
                                        ;   in Loop: Header=BB2_6 Depth=3
	s_add_i32 s28, s28, 1
	s_sub_i32 s29, s29, 64
	s_cmp_eq_u32 s28, s27
	s_cbranch_scc0 .LBB2_6
.LBB2_16:                               ; %._crit_edge129
                                        ;   in Loop: Header=BB2_4 Depth=2
	v_cmp_ge_i32_e32 vcc_lo, s25, v10
	s_add_i32 s25, s25, 1
	s_cbranch_vccz .LBB2_4
.LBB2_17:                               ; %._crit_edge139
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_ge_i32_e32 vcc_lo, s19, v8
	s_add_i32 s19, s19, 1
	s_cbranch_vccz .LBB2_2
.LBB2_18:                               ; %._crit_edge148
	v_mul_lo_u32 v2, s18, v7
	v_mul_lo_u32 v3, v6, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v5, v2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 3, v[2:3]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b64 v[4:5], v[0:1], off
	global_store_b32 v[2:3], v9, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
		.amdhsa_group_segment_fixed_size 1536
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 31
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff, .Lfunc_end2-_Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1844
; NumSgprs: 33
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1536 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 33
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	cutoff2_c               ; @cutoff2_c
	.type	cutoff2_c,@object
	.section	.bss,"aw",@nobits
	.globl	cutoff2_c
	.p2align	2, 0x0
cutoff2_c:
	.long	0x00000000                      ; float 0
	.size	cutoff2_c, 4

	.protected	cutoff_c                ; @cutoff_c
	.type	cutoff_c,@object
	.globl	cutoff_c
	.p2align	2, 0x0
cutoff_c:
	.long	0x00000000                      ; float 0
	.size	cutoff_c, 4

	.protected	gridSize_c              ; @gridSize_c
	.type	gridSize_c,@object
	.globl	gridSize_c
	.p2align	2, 0x0
gridSize_c:
	.zero	12
	.size	gridSize_c, 12

	.protected	size_xy_c               ; @size_xy_c
	.type	size_xy_c,@object
	.globl	size_xy_c
	.p2align	2, 0x0
size_xy_c:
	.long	0                               ; 0x0
	.size	size_xy_c, 4

	.protected	_1overCutoff2_c         ; @_1overCutoff2_c
	.type	_1overCutoff2_c,@object
	.globl	_1overCutoff2_c
	.p2align	2, 0x0
_1overCutoff2_c:
	.long	0x00000000                      ; float 0
	.size	_1overCutoff2_c, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym cutoff2_c
	.addrsig_sym cutoff_c
	.addrsig_sym gridSize_c
	.addrsig_sym size_xy_c
	.addrsig_sym _1overCutoff2_c
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14binning_kerneljP20ReconstructionSamplePjS1_S1_jj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14reorder_kerneliPjP20ReconstructionSampleS1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14reorder_kerneliPjP20ReconstructionSampleS1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1536
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff
    .private_segment_fixed_size: 0
    .sgpr_count:     33
    .sgpr_spill_count: 0
    .symbol:         _Z12gridding_GPUP20ReconstructionSamplePjP15HIP_vector_typeIfLj2EEPff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
