/* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  * Neither the name of NVIDIA CORPORATION nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
    Parallel reduction kernels
*/

#ifndef _REDUCE_KERNEL_H_
#define _REDUCE_KERNEL_H_

#include <cooperative_groups.h>
#include <stdio.h>

namespace cg = cooperative_groups;

// Utility class used to avoid linker errors with extern
// unsized shared memory arrays with templated type
template <class T>
struct SharedMemory {
  __device__ inline operator T *() {
    extern __shared__ int __smem[];
    return (T *)__smem;
  }

  __device__ inline operator const T *() const {
    extern __shared__ int __smem[];
    return (T *)__smem;
  }
};

// specialize for double to avoid unaligned memory
// access compile errors
template <>
struct SharedMemory<double> {
  __device__ inline operator double *() {
    extern __shared__ double __smem_d[];
    return (double *)__smem_d;
  }

  __device__ inline operator const double *() const {
    extern __shared__ double __smem_d[];
    return (double *)__smem_d;
  }
};

/*
    Parallel sum reduction using shared memory
    - takes log(n) steps for n input elements
    - uses n threads
    - only works for power-of-2 arrays
*/

/* This reduction interleaves which threads are active by using the modulo
   operator.  This operator is very expensive on GPUs, and the interleaved
   inactivity means that no whole warps are active, which is also very
   inefficient */
template <class T>
__global__ void reduce0(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // load shared mem
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;

  sdata[tid] = (i < n) ? g_idata[i] : 0;

  cg::sync(cta);

  // do reduction in shared mem
  for (unsigned int s = 1; s < blockDim.x; s *= 2) {
    // modulo arithmetic is slow!
    if ((tid % (2 * s)) == 0) {
      sdata[tid] += sdata[tid + s];
    }

    cg::sync(cta);
  }

  // write result for this block to global mem
  if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}

/* This version uses contiguous threads, but its interleaved
   addressing results in many shared memory bank conflicts.
*/
template <class T>
__global__ void reduce1(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // load shared mem
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;

  sdata[tid] = (i < n) ? g_idata[i] : 0;

  cg::sync(cta);

  // do reduction in shared mem
  for (unsigned int s = 1; s < blockDim.x; s *= 2) {
    int index = 2 * s * tid;

    if (index < blockDim.x) {
      sdata[index] += sdata[index + s];
    }

    cg::sync(cta);
  }

  // write result for this block to global mem
  if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}

/*
    This version uses sequential addressing -- no divergence or bank conflicts.
*/
template <class T>
__global__ void reduce2(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // load shared mem
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;

  sdata[tid] = (i < n) ? g_idata[i] : 0;

  cg::sync(cta);

  // do reduction in shared mem
  for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
    if (tid < s) {
      sdata[tid] += sdata[tid + s];
    }

    cg::sync(cta);
  }

  // write result for this block to global mem
  if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}

/*
    This version uses n/2 threads --
    it performs the first level of reduction when reading from global memory.
*/
template <class T>
__global__ void reduce3(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();

  // perform first level of reduction,
  // reading from global memory, writing to shared memory
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;

  T mySum = (i < n) ? g_idata[i] : 0;

  if (i + blockDim.x < n) mySum += g_idata[i + blockDim.x];

  g_odata[i] = mySum;
  cg::sync(cta);

  // do reduction in global mem
  for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
    if (tid < s) {
      g_odata[i] = mySum = mySum + g_odata[i + s];
    }
    cg::sync(cta);
  }

  // write result for this block to global mem
  if (tid == 0) g_odata[blockIdx.x] = mySum;
}

/*
    This version uses the warp shuffle operation if available to reduce
    warp synchronization. When shuffle is not available the final warp's
    worth of work is unrolled to reduce looping overhead.

    See
   http://devblogs.nvidia.com/parallelforall/faster-parallel-reductions-kepler/
    for additional information about using shuffle to perform a reduction
    within a warp.

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T, unsigned int blockSize>
__global__ void reduce4(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // perform first level of reduction,
  // reading from global memory, writing to shared memory
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;

  T mySum = (i < n) ? g_idata[i] : 0;

  if (i + blockSize < n) mySum += g_idata[i + blockSize];

  sdata[tid] = mySum;
  cg::sync(cta);

  // do reduction in shared mem
  for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
    if (tid < s) {
      sdata[tid] = mySum = mySum + sdata[tid + s];
    }

    cg::sync(cta);
  }

  cg::thread_block_tile<32> tile32 = cg::tiled_partition<32>(cta);

  if (cta.thread_rank() < 32) {
    // Fetch final intermediate sum from 2nd warp
    if (blockSize >= 64) mySum += sdata[tid + 32];
    // Reduce final warp using shuffle
    for (int offset = tile32.size() / 2; offset > 0; offset /= 2) {
      mySum += tile32.shfl_down(mySum, offset);
    }
  }

  // write result for this block to global mem
  if (cta.thread_rank() == 0) g_odata[blockIdx.x] = mySum;
}

/*
    This version is completely unrolled, unless warp shuffle is available, then
    shuffle is used within a loop.  It uses a template parameter to achieve
    optimal code for any (power of 2) number of threads.  This requires a switch
    statement in the host code to handle all the different thread block sizes at
    compile time. When shuffle is available, it is used to reduce warp
   synchronization.

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T, unsigned int blockSize>
__global__ void reduce5(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // perform first level of reduction,
  // reading from global memory, writing to shared memory
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * (blockSize * 2) + threadIdx.x;

  T mySum = (i < n) ? g_idata[i] : 0;

  if (i + blockSize < n) mySum += g_idata[i + blockSize];

  sdata[tid] = mySum;
  cg::sync(cta);

  // do reduction in shared mem
  if ((blockSize >= 512) && (tid < 256)) {
    sdata[tid] = mySum = mySum + sdata[tid + 256];
  }

  cg::sync(cta);

  if ((blockSize >= 256) && (tid < 128)) {
    sdata[tid] = mySum = mySum + sdata[tid + 128];
  }

  cg::sync(cta);

  if ((blockSize >= 128) && (tid < 64)) {
    sdata[tid] = mySum = mySum + sdata[tid + 64];
  }

  cg::sync(cta);

  cg::thread_block_tile<32> tile32 = cg::tiled_partition<32>(cta);

  if (cta.thread_rank() < 32) {
    // Fetch final intermediate sum from 2nd warp
    if (blockSize >= 64) mySum += sdata[tid + 32];
    // Reduce final warp using shuffle
    for (int offset = tile32.size() / 2; offset > 0; offset /= 2) {
      mySum += tile32.shfl_down(mySum, offset);
    }
  }

  // write result for this block to global mem
  if (cta.thread_rank() == 0) g_odata[blockIdx.x] = mySum;
}

/*
    This version adds multiple elements per thread sequentially.  This reduces
   the overall cost of the algorithm while keeping the work complexity O(n) and
   the step complexity O(log n). (Brent's Theorem optimization)

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T, unsigned int blockSize, bool nIsPow2>
__global__ void reduce6(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // perform first level of reduction,
  // reading from global memory, writing to shared memory
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * blockSize * 2 + threadIdx.x;
  unsigned int gridSize = blockSize * 2 * gridDim.x;

  T mySum = 0;

  // we reduce multiple elements per thread.  The number is determined by the
  // number of active thread blocks (via gridDim).  More blocks will result
  // in a larger gridSize and therefore fewer elements per thread
  while (i < n) {
    mySum += g_idata[i];

    // ensure we don't read out of bounds -- this is optimized away for powerOf2
    // sized arrays
    if (nIsPow2 || i + blockSize < n) mySum += g_idata[i + blockSize];

    i += gridSize;
  }

  // each thread puts its local sum into shared memory
  sdata[tid] = mySum;
  cg::sync(cta);

  // do reduction in shared mem
  if ((blockSize >= 512) && (tid < 256)) {
    sdata[tid] = mySum = mySum + sdata[tid + 256];
  }

  cg::sync(cta);

  if ((blockSize >= 256) && (tid < 128)) {
    sdata[tid] = mySum = mySum + sdata[tid + 128];
  }

  cg::sync(cta);

  if ((blockSize >= 128) && (tid < 64)) {
    sdata[tid] = mySum = mySum + sdata[tid + 64];
  }

  cg::sync(cta);

  cg::thread_block_tile<32> tile32 = cg::tiled_partition<32>(cta);

  if (cta.thread_rank() < 32) {
    // Fetch final intermediate sum from 2nd warp
    if (blockSize >= 64) mySum += sdata[tid + 32];
    // Reduce final warp using shuffle
    for (int offset = tile32.size() / 2; offset > 0; offset /= 2) {
      mySum += tile32.shfl_down(mySum, offset);
    }
  }

  // write result for this block to global mem
  if (cta.thread_rank() == 0) g_odata[blockIdx.x] = mySum;
}

extern "C" bool isPow2(unsigned int x);

////////////////////////////////////////////////////////////////////////////////
// Wrapper function for kernel launch
////////////////////////////////////////////////////////////////////////////////
template <class T>
void reduce(int size, int threads, int blocks, int whichKernel, T *d_idata,
            T *d_odata) {
  dim3 dimBlock(threads, 1, 1);
  dim3 dimGrid(blocks, 1, 1);

  // when there is only one warp per block, we need to allocate two warps
  // worth of shared memory so that we don't index shared memory out of bounds
  int smemSize =
      (threads <= 32) ? 2 * threads * sizeof(T) : threads * sizeof(T);

  // choose which of the optimized versions of reduction to launch
  switch (whichKernel) {
    case 0:
      reduce0<T><<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
      break;

    case 1:
      reduce1<T><<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
      break;

    case 2:
      reduce2<T><<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
      break;

    case 3:
      reduce3<T><<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
      break;

    case 4:
      switch (threads) {
        case 512:
          reduce4<T, 512>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 256:
          reduce4<T, 256>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 128:
          reduce4<T, 128>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 64:
          reduce4<T, 64>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 32:
          reduce4<T, 32>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 16:
          reduce4<T, 16>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 8:
          reduce4<T, 8>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 4:
          reduce4<T, 4>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 2:
          reduce4<T, 2>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 1:
          reduce4<T, 1>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;
      }

      break;

    case 5:
      switch (threads) {
        case 512:
          reduce5<T, 512>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 256:
          reduce5<T, 256>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 128:
          reduce5<T, 128>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 64:
          reduce5<T, 64>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 32:
          reduce5<T, 32>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 16:
          reduce5<T, 16>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 8:
          reduce5<T, 8>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 4:
          reduce5<T, 4>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 2:
          reduce5<T, 2>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 1:
          reduce5<T, 1>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;
      }

      break;

    case 6:
    default:
      if (isPow2(size)) {
        switch (threads) {
          case 512:
            reduce6<T, 512, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 256:
            reduce6<T, 256, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 128:
            reduce6<T, 128, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 64:
            reduce6<T, 64, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 32:
            reduce6<T, 32, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 16:
            reduce6<T, 16, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 8:
            reduce6<T, 8, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 4:
            reduce6<T, 4, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 2:
            reduce6<T, 2, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 1:
            reduce6<T, 1, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;
        }
      } else {
        switch (threads) {
          case 512:
            reduce6<T, 512, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 256:
            reduce6<T, 256, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 128:
            reduce6<T, 128, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 64:
            reduce6<T, 64, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 32:
            reduce6<T, 32, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 16:
            reduce6<T, 16, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 8:
            reduce6<T, 8, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 4:
            reduce6<T, 4, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 2:
            reduce6<T, 2, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 1:
            reduce6<T, 1, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;
        }
      }

      break;
  }
}

// Instantiate the reduction function for 3 types
template void reduce<int>(int size, int threads, int blocks, int whichKernel,
                          int *d_idata, int *d_odata);

template void reduce<float>(int size, int threads, int blocks, int whichKernel,
                            float *d_idata, float *d_odata);

template void reduce<double>(int size, int threads, int blocks, int whichKernel,
                             double *d_idata, double *d_odata);

#endif  // #ifndef _REDUCE_KERNEL_H_

	.file	"tmpxft_003ae9d8_00000000-6_reduction_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6580:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE6580:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB7849:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE7849:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.type	_ZL43__device_stub__Z7reduce6IdLj1ELb0EEvPT_S1_jPdS_j, @function
_ZL43__device_stub__Z7reduce6IdLj1ELb0EEvPT_S1_jPdS_j:
.LFB6864:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj1ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6864:
	.size	_ZL43__device_stub__Z7reduce6IdLj1ELb0EEvPT_S1_jPdS_j, .-_ZL43__device_stub__Z7reduce6IdLj1ELb0EEvPT_S1_jPdS_j
	.type	_ZL43__device_stub__Z7reduce6IdLj2ELb0EEvPT_S1_jPdS_j, @function
_ZL43__device_stub__Z7reduce6IdLj2ELb0EEvPT_S1_jPdS_j:
.LFB6862:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj2ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6862:
	.size	_ZL43__device_stub__Z7reduce6IdLj2ELb0EEvPT_S1_jPdS_j, .-_ZL43__device_stub__Z7reduce6IdLj2ELb0EEvPT_S1_jPdS_j
	.type	_ZL43__device_stub__Z7reduce6IdLj4ELb0EEvPT_S1_jPdS_j, @function
_ZL43__device_stub__Z7reduce6IdLj4ELb0EEvPT_S1_jPdS_j:
.LFB6860:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj4ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L12:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6860:
	.size	_ZL43__device_stub__Z7reduce6IdLj4ELb0EEvPT_S1_jPdS_j, .-_ZL43__device_stub__Z7reduce6IdLj4ELb0EEvPT_S1_jPdS_j
	.type	_ZL43__device_stub__Z7reduce6IdLj8ELb0EEvPT_S1_jPdS_j, @function
_ZL43__device_stub__Z7reduce6IdLj8ELb0EEvPT_S1_jPdS_j:
.LFB6858:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj8ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L16:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6858:
	.size	_ZL43__device_stub__Z7reduce6IdLj8ELb0EEvPT_S1_jPdS_j, .-_ZL43__device_stub__Z7reduce6IdLj8ELb0EEvPT_S1_jPdS_j
	.type	_ZL44__device_stub__Z7reduce6IdLj16ELb0EEvPT_S1_jPdS_j, @function
_ZL44__device_stub__Z7reduce6IdLj16ELb0EEvPT_S1_jPdS_j:
.LFB6856:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj16ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L20:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6856:
	.size	_ZL44__device_stub__Z7reduce6IdLj16ELb0EEvPT_S1_jPdS_j, .-_ZL44__device_stub__Z7reduce6IdLj16ELb0EEvPT_S1_jPdS_j
	.type	_ZL44__device_stub__Z7reduce6IdLj32ELb0EEvPT_S1_jPdS_j, @function
_ZL44__device_stub__Z7reduce6IdLj32ELb0EEvPT_S1_jPdS_j:
.LFB6854:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj32ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L24:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6854:
	.size	_ZL44__device_stub__Z7reduce6IdLj32ELb0EEvPT_S1_jPdS_j, .-_ZL44__device_stub__Z7reduce6IdLj32ELb0EEvPT_S1_jPdS_j
	.type	_ZL44__device_stub__Z7reduce6IdLj64ELb0EEvPT_S1_jPdS_j, @function
_ZL44__device_stub__Z7reduce6IdLj64ELb0EEvPT_S1_jPdS_j:
.LFB6852:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj64ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L28:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6852:
	.size	_ZL44__device_stub__Z7reduce6IdLj64ELb0EEvPT_S1_jPdS_j, .-_ZL44__device_stub__Z7reduce6IdLj64ELb0EEvPT_S1_jPdS_j
	.type	_ZL45__device_stub__Z7reduce6IdLj128ELb0EEvPT_S1_jPdS_j, @function
_ZL45__device_stub__Z7reduce6IdLj128ELb0EEvPT_S1_jPdS_j:
.LFB6850:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj128ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L32:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6850:
	.size	_ZL45__device_stub__Z7reduce6IdLj128ELb0EEvPT_S1_jPdS_j, .-_ZL45__device_stub__Z7reduce6IdLj128ELb0EEvPT_S1_jPdS_j
	.type	_ZL45__device_stub__Z7reduce6IdLj256ELb0EEvPT_S1_jPdS_j, @function
_ZL45__device_stub__Z7reduce6IdLj256ELb0EEvPT_S1_jPdS_j:
.LFB6848:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj256ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L36:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6848:
	.size	_ZL45__device_stub__Z7reduce6IdLj256ELb0EEvPT_S1_jPdS_j, .-_ZL45__device_stub__Z7reduce6IdLj256ELb0EEvPT_S1_jPdS_j
	.type	_ZL45__device_stub__Z7reduce6IdLj512ELb0EEvPT_S1_jPdS_j, @function
_ZL45__device_stub__Z7reduce6IdLj512ELb0EEvPT_S1_jPdS_j:
.LFB6846:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj512ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L40:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6846:
	.size	_ZL45__device_stub__Z7reduce6IdLj512ELb0EEvPT_S1_jPdS_j, .-_ZL45__device_stub__Z7reduce6IdLj512ELb0EEvPT_S1_jPdS_j
	.type	_ZL43__device_stub__Z7reduce6IdLj1ELb1EEvPT_S1_jPdS_j, @function
_ZL43__device_stub__Z7reduce6IdLj1ELb1EEvPT_S1_jPdS_j:
.LFB6844:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj1ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L44:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6844:
	.size	_ZL43__device_stub__Z7reduce6IdLj1ELb1EEvPT_S1_jPdS_j, .-_ZL43__device_stub__Z7reduce6IdLj1ELb1EEvPT_S1_jPdS_j
	.type	_ZL43__device_stub__Z7reduce6IdLj2ELb1EEvPT_S1_jPdS_j, @function
_ZL43__device_stub__Z7reduce6IdLj2ELb1EEvPT_S1_jPdS_j:
.LFB6842:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj2ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L48:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6842:
	.size	_ZL43__device_stub__Z7reduce6IdLj2ELb1EEvPT_S1_jPdS_j, .-_ZL43__device_stub__Z7reduce6IdLj2ELb1EEvPT_S1_jPdS_j
	.type	_ZL43__device_stub__Z7reduce6IdLj4ELb1EEvPT_S1_jPdS_j, @function
_ZL43__device_stub__Z7reduce6IdLj4ELb1EEvPT_S1_jPdS_j:
.LFB6840:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj4ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L52:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L54
	call	__stack_chk_fail@PLT
.L54:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6840:
	.size	_ZL43__device_stub__Z7reduce6IdLj4ELb1EEvPT_S1_jPdS_j, .-_ZL43__device_stub__Z7reduce6IdLj4ELb1EEvPT_S1_jPdS_j
	.type	_ZL43__device_stub__Z7reduce6IdLj8ELb1EEvPT_S1_jPdS_j, @function
_ZL43__device_stub__Z7reduce6IdLj8ELb1EEvPT_S1_jPdS_j:
.LFB6838:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj8ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L56:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6838:
	.size	_ZL43__device_stub__Z7reduce6IdLj8ELb1EEvPT_S1_jPdS_j, .-_ZL43__device_stub__Z7reduce6IdLj8ELb1EEvPT_S1_jPdS_j
	.type	_ZL44__device_stub__Z7reduce6IdLj16ELb1EEvPT_S1_jPdS_j, @function
_ZL44__device_stub__Z7reduce6IdLj16ELb1EEvPT_S1_jPdS_j:
.LFB6836:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj16ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L60:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L62
	call	__stack_chk_fail@PLT
.L62:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6836:
	.size	_ZL44__device_stub__Z7reduce6IdLj16ELb1EEvPT_S1_jPdS_j, .-_ZL44__device_stub__Z7reduce6IdLj16ELb1EEvPT_S1_jPdS_j
	.type	_ZL44__device_stub__Z7reduce6IdLj32ELb1EEvPT_S1_jPdS_j, @function
_ZL44__device_stub__Z7reduce6IdLj32ELb1EEvPT_S1_jPdS_j:
.LFB6834:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj32ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L64:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6834:
	.size	_ZL44__device_stub__Z7reduce6IdLj32ELb1EEvPT_S1_jPdS_j, .-_ZL44__device_stub__Z7reduce6IdLj32ELb1EEvPT_S1_jPdS_j
	.type	_ZL44__device_stub__Z7reduce6IdLj64ELb1EEvPT_S1_jPdS_j, @function
_ZL44__device_stub__Z7reduce6IdLj64ELb1EEvPT_S1_jPdS_j:
.LFB6832:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L68
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj64ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L68:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L70
	call	__stack_chk_fail@PLT
.L70:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6832:
	.size	_ZL44__device_stub__Z7reduce6IdLj64ELb1EEvPT_S1_jPdS_j, .-_ZL44__device_stub__Z7reduce6IdLj64ELb1EEvPT_S1_jPdS_j
	.type	_ZL45__device_stub__Z7reduce6IdLj128ELb1EEvPT_S1_jPdS_j, @function
_ZL45__device_stub__Z7reduce6IdLj128ELb1EEvPT_S1_jPdS_j:
.LFB6830:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L72
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj128ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L72:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L74
	call	__stack_chk_fail@PLT
.L74:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6830:
	.size	_ZL45__device_stub__Z7reduce6IdLj128ELb1EEvPT_S1_jPdS_j, .-_ZL45__device_stub__Z7reduce6IdLj128ELb1EEvPT_S1_jPdS_j
	.type	_ZL45__device_stub__Z7reduce6IdLj256ELb1EEvPT_S1_jPdS_j, @function
_ZL45__device_stub__Z7reduce6IdLj256ELb1EEvPT_S1_jPdS_j:
.LFB6828:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L76
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj256ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L76:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L78
	call	__stack_chk_fail@PLT
.L78:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6828:
	.size	_ZL45__device_stub__Z7reduce6IdLj256ELb1EEvPT_S1_jPdS_j, .-_ZL45__device_stub__Z7reduce6IdLj256ELb1EEvPT_S1_jPdS_j
	.type	_ZL45__device_stub__Z7reduce6IdLj512ELb1EEvPT_S1_jPdS_j, @function
_ZL45__device_stub__Z7reduce6IdLj512ELb1EEvPT_S1_jPdS_j:
.LFB6826:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L80
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IdLj512ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L80:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L82
	call	__stack_chk_fail@PLT
.L82:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6826:
	.size	_ZL45__device_stub__Z7reduce6IdLj512ELb1EEvPT_S1_jPdS_j, .-_ZL45__device_stub__Z7reduce6IdLj512ELb1EEvPT_S1_jPdS_j
	.type	_ZL39__device_stub__Z7reduce5IdLj1EEvPT_S1_jPdS_j, @function
_ZL39__device_stub__Z7reduce5IdLj1EEvPT_S1_jPdS_j:
.LFB6824:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L84
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L84:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L86
	call	__stack_chk_fail@PLT
.L86:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6824:
	.size	_ZL39__device_stub__Z7reduce5IdLj1EEvPT_S1_jPdS_j, .-_ZL39__device_stub__Z7reduce5IdLj1EEvPT_S1_jPdS_j
	.type	_ZL39__device_stub__Z7reduce5IdLj2EEvPT_S1_jPdS_j, @function
_ZL39__device_stub__Z7reduce5IdLj2EEvPT_S1_jPdS_j:
.LFB6822:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L88
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj2EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L88:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L90
	call	__stack_chk_fail@PLT
.L90:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6822:
	.size	_ZL39__device_stub__Z7reduce5IdLj2EEvPT_S1_jPdS_j, .-_ZL39__device_stub__Z7reduce5IdLj2EEvPT_S1_jPdS_j
	.type	_ZL39__device_stub__Z7reduce5IdLj4EEvPT_S1_jPdS_j, @function
_ZL39__device_stub__Z7reduce5IdLj4EEvPT_S1_jPdS_j:
.LFB6820:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L92
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj4EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L92:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L94
	call	__stack_chk_fail@PLT
.L94:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6820:
	.size	_ZL39__device_stub__Z7reduce5IdLj4EEvPT_S1_jPdS_j, .-_ZL39__device_stub__Z7reduce5IdLj4EEvPT_S1_jPdS_j
	.type	_ZL39__device_stub__Z7reduce5IdLj8EEvPT_S1_jPdS_j, @function
_ZL39__device_stub__Z7reduce5IdLj8EEvPT_S1_jPdS_j:
.LFB6818:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L96
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj8EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L96:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L98
	call	__stack_chk_fail@PLT
.L98:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6818:
	.size	_ZL39__device_stub__Z7reduce5IdLj8EEvPT_S1_jPdS_j, .-_ZL39__device_stub__Z7reduce5IdLj8EEvPT_S1_jPdS_j
	.type	_ZL40__device_stub__Z7reduce5IdLj16EEvPT_S1_jPdS_j, @function
_ZL40__device_stub__Z7reduce5IdLj16EEvPT_S1_jPdS_j:
.LFB6816:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L100
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj16EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L100:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L102
	call	__stack_chk_fail@PLT
.L102:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6816:
	.size	_ZL40__device_stub__Z7reduce5IdLj16EEvPT_S1_jPdS_j, .-_ZL40__device_stub__Z7reduce5IdLj16EEvPT_S1_jPdS_j
	.type	_ZL40__device_stub__Z7reduce5IdLj32EEvPT_S1_jPdS_j, @function
_ZL40__device_stub__Z7reduce5IdLj32EEvPT_S1_jPdS_j:
.LFB6814:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L104
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj32EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L104:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L106
	call	__stack_chk_fail@PLT
.L106:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6814:
	.size	_ZL40__device_stub__Z7reduce5IdLj32EEvPT_S1_jPdS_j, .-_ZL40__device_stub__Z7reduce5IdLj32EEvPT_S1_jPdS_j
	.type	_ZL40__device_stub__Z7reduce5IdLj64EEvPT_S1_jPdS_j, @function
_ZL40__device_stub__Z7reduce5IdLj64EEvPT_S1_jPdS_j:
.LFB6812:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L108
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj64EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L108:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L110
	call	__stack_chk_fail@PLT
.L110:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6812:
	.size	_ZL40__device_stub__Z7reduce5IdLj64EEvPT_S1_jPdS_j, .-_ZL40__device_stub__Z7reduce5IdLj64EEvPT_S1_jPdS_j
	.type	_ZL41__device_stub__Z7reduce5IdLj128EEvPT_S1_jPdS_j, @function
_ZL41__device_stub__Z7reduce5IdLj128EEvPT_S1_jPdS_j:
.LFB6810:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L112
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj128EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L112:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L114
	call	__stack_chk_fail@PLT
.L114:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6810:
	.size	_ZL41__device_stub__Z7reduce5IdLj128EEvPT_S1_jPdS_j, .-_ZL41__device_stub__Z7reduce5IdLj128EEvPT_S1_jPdS_j
	.type	_ZL41__device_stub__Z7reduce5IdLj256EEvPT_S1_jPdS_j, @function
_ZL41__device_stub__Z7reduce5IdLj256EEvPT_S1_jPdS_j:
.LFB6808:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L116
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj256EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L116:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L118
	call	__stack_chk_fail@PLT
.L118:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6808:
	.size	_ZL41__device_stub__Z7reduce5IdLj256EEvPT_S1_jPdS_j, .-_ZL41__device_stub__Z7reduce5IdLj256EEvPT_S1_jPdS_j
	.type	_ZL41__device_stub__Z7reduce5IdLj512EEvPT_S1_jPdS_j, @function
_ZL41__device_stub__Z7reduce5IdLj512EEvPT_S1_jPdS_j:
.LFB6806:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L120
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IdLj512EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L120:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L122
	call	__stack_chk_fail@PLT
.L122:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6806:
	.size	_ZL41__device_stub__Z7reduce5IdLj512EEvPT_S1_jPdS_j, .-_ZL41__device_stub__Z7reduce5IdLj512EEvPT_S1_jPdS_j
	.type	_ZL39__device_stub__Z7reduce4IdLj1EEvPT_S1_jPdS_j, @function
_ZL39__device_stub__Z7reduce4IdLj1EEvPT_S1_jPdS_j:
.LFB6804:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L124
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L124:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L126
	call	__stack_chk_fail@PLT
.L126:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6804:
	.size	_ZL39__device_stub__Z7reduce4IdLj1EEvPT_S1_jPdS_j, .-_ZL39__device_stub__Z7reduce4IdLj1EEvPT_S1_jPdS_j
	.type	_ZL39__device_stub__Z7reduce4IdLj2EEvPT_S1_jPdS_j, @function
_ZL39__device_stub__Z7reduce4IdLj2EEvPT_S1_jPdS_j:
.LFB6802:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L128
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj2EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L128:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L130
	call	__stack_chk_fail@PLT
.L130:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6802:
	.size	_ZL39__device_stub__Z7reduce4IdLj2EEvPT_S1_jPdS_j, .-_ZL39__device_stub__Z7reduce4IdLj2EEvPT_S1_jPdS_j
	.type	_ZL39__device_stub__Z7reduce4IdLj4EEvPT_S1_jPdS_j, @function
_ZL39__device_stub__Z7reduce4IdLj4EEvPT_S1_jPdS_j:
.LFB6800:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L132
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj4EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L132:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L134
	call	__stack_chk_fail@PLT
.L134:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6800:
	.size	_ZL39__device_stub__Z7reduce4IdLj4EEvPT_S1_jPdS_j, .-_ZL39__device_stub__Z7reduce4IdLj4EEvPT_S1_jPdS_j
	.type	_ZL39__device_stub__Z7reduce4IdLj8EEvPT_S1_jPdS_j, @function
_ZL39__device_stub__Z7reduce4IdLj8EEvPT_S1_jPdS_j:
.LFB6798:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L136
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj8EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L136:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L138
	call	__stack_chk_fail@PLT
.L138:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6798:
	.size	_ZL39__device_stub__Z7reduce4IdLj8EEvPT_S1_jPdS_j, .-_ZL39__device_stub__Z7reduce4IdLj8EEvPT_S1_jPdS_j
	.type	_ZL40__device_stub__Z7reduce4IdLj16EEvPT_S1_jPdS_j, @function
_ZL40__device_stub__Z7reduce4IdLj16EEvPT_S1_jPdS_j:
.LFB6796:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L140
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj16EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L140:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L142
	call	__stack_chk_fail@PLT
.L142:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6796:
	.size	_ZL40__device_stub__Z7reduce4IdLj16EEvPT_S1_jPdS_j, .-_ZL40__device_stub__Z7reduce4IdLj16EEvPT_S1_jPdS_j
	.type	_ZL40__device_stub__Z7reduce4IdLj32EEvPT_S1_jPdS_j, @function
_ZL40__device_stub__Z7reduce4IdLj32EEvPT_S1_jPdS_j:
.LFB6794:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L144
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj32EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L144:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L146
	call	__stack_chk_fail@PLT
.L146:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6794:
	.size	_ZL40__device_stub__Z7reduce4IdLj32EEvPT_S1_jPdS_j, .-_ZL40__device_stub__Z7reduce4IdLj32EEvPT_S1_jPdS_j
	.type	_ZL40__device_stub__Z7reduce4IdLj64EEvPT_S1_jPdS_j, @function
_ZL40__device_stub__Z7reduce4IdLj64EEvPT_S1_jPdS_j:
.LFB6792:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L148
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj64EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L148:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L150
	call	__stack_chk_fail@PLT
.L150:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6792:
	.size	_ZL40__device_stub__Z7reduce4IdLj64EEvPT_S1_jPdS_j, .-_ZL40__device_stub__Z7reduce4IdLj64EEvPT_S1_jPdS_j
	.type	_ZL41__device_stub__Z7reduce4IdLj128EEvPT_S1_jPdS_j, @function
_ZL41__device_stub__Z7reduce4IdLj128EEvPT_S1_jPdS_j:
.LFB6790:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L152
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj128EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L152:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L154
	call	__stack_chk_fail@PLT
.L154:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6790:
	.size	_ZL41__device_stub__Z7reduce4IdLj128EEvPT_S1_jPdS_j, .-_ZL41__device_stub__Z7reduce4IdLj128EEvPT_S1_jPdS_j
	.type	_ZL41__device_stub__Z7reduce4IdLj256EEvPT_S1_jPdS_j, @function
_ZL41__device_stub__Z7reduce4IdLj256EEvPT_S1_jPdS_j:
.LFB6788:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L156
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj256EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L156:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L158
	call	__stack_chk_fail@PLT
.L158:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6788:
	.size	_ZL41__device_stub__Z7reduce4IdLj256EEvPT_S1_jPdS_j, .-_ZL41__device_stub__Z7reduce4IdLj256EEvPT_S1_jPdS_j
	.type	_ZL41__device_stub__Z7reduce4IdLj512EEvPT_S1_jPdS_j, @function
_ZL41__device_stub__Z7reduce4IdLj512EEvPT_S1_jPdS_j:
.LFB6786:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L160
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IdLj512EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L160:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L162
	call	__stack_chk_fail@PLT
.L162:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6786:
	.size	_ZL41__device_stub__Z7reduce4IdLj512EEvPT_S1_jPdS_j, .-_ZL41__device_stub__Z7reduce4IdLj512EEvPT_S1_jPdS_j
	.type	_ZL35__device_stub__Z7reduce3IdEvPT_S1_jPdS_j, @function
_ZL35__device_stub__Z7reduce3IdEvPT_S1_jPdS_j:
.LFB6784:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L164
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce3IdEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L164:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L166
	call	__stack_chk_fail@PLT
.L166:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6784:
	.size	_ZL35__device_stub__Z7reduce3IdEvPT_S1_jPdS_j, .-_ZL35__device_stub__Z7reduce3IdEvPT_S1_jPdS_j
	.type	_ZL35__device_stub__Z7reduce2IdEvPT_S1_jPdS_j, @function
_ZL35__device_stub__Z7reduce2IdEvPT_S1_jPdS_j:
.LFB6782:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L168
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce2IdEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L168:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L170
	call	__stack_chk_fail@PLT
.L170:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6782:
	.size	_ZL35__device_stub__Z7reduce2IdEvPT_S1_jPdS_j, .-_ZL35__device_stub__Z7reduce2IdEvPT_S1_jPdS_j
	.type	_ZL35__device_stub__Z7reduce1IdEvPT_S1_jPdS_j, @function
_ZL35__device_stub__Z7reduce1IdEvPT_S1_jPdS_j:
.LFB6780:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L172
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce1IdEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L172:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L174
	call	__stack_chk_fail@PLT
.L174:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6780:
	.size	_ZL35__device_stub__Z7reduce1IdEvPT_S1_jPdS_j, .-_ZL35__device_stub__Z7reduce1IdEvPT_S1_jPdS_j
	.type	_ZL35__device_stub__Z7reduce0IdEvPT_S1_jPdS_j, @function
_ZL35__device_stub__Z7reduce0IdEvPT_S1_jPdS_j:
.LFB6778:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L176
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce0IdEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L176:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L178
	call	__stack_chk_fail@PLT
.L178:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6778:
	.size	_ZL35__device_stub__Z7reduce0IdEvPT_S1_jPdS_j, .-_ZL35__device_stub__Z7reduce0IdEvPT_S1_jPdS_j
	.type	_ZL43__device_stub__Z7reduce6IfLj1ELb0EEvPT_S1_jPfS_j, @function
_ZL43__device_stub__Z7reduce6IfLj1ELb0EEvPT_S1_jPfS_j:
.LFB6776:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L180
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj1ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L180:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L182
	call	__stack_chk_fail@PLT
.L182:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6776:
	.size	_ZL43__device_stub__Z7reduce6IfLj1ELb0EEvPT_S1_jPfS_j, .-_ZL43__device_stub__Z7reduce6IfLj1ELb0EEvPT_S1_jPfS_j
	.type	_ZL43__device_stub__Z7reduce6IfLj2ELb0EEvPT_S1_jPfS_j, @function
_ZL43__device_stub__Z7reduce6IfLj2ELb0EEvPT_S1_jPfS_j:
.LFB6774:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L184
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj2ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L184:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L186
	call	__stack_chk_fail@PLT
.L186:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6774:
	.size	_ZL43__device_stub__Z7reduce6IfLj2ELb0EEvPT_S1_jPfS_j, .-_ZL43__device_stub__Z7reduce6IfLj2ELb0EEvPT_S1_jPfS_j
	.type	_ZL43__device_stub__Z7reduce6IfLj4ELb0EEvPT_S1_jPfS_j, @function
_ZL43__device_stub__Z7reduce6IfLj4ELb0EEvPT_S1_jPfS_j:
.LFB6772:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L188
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj4ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L188:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L190
	call	__stack_chk_fail@PLT
.L190:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6772:
	.size	_ZL43__device_stub__Z7reduce6IfLj4ELb0EEvPT_S1_jPfS_j, .-_ZL43__device_stub__Z7reduce6IfLj4ELb0EEvPT_S1_jPfS_j
	.type	_ZL43__device_stub__Z7reduce6IfLj8ELb0EEvPT_S1_jPfS_j, @function
_ZL43__device_stub__Z7reduce6IfLj8ELb0EEvPT_S1_jPfS_j:
.LFB6770:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L192
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj8ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L192:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L194
	call	__stack_chk_fail@PLT
.L194:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6770:
	.size	_ZL43__device_stub__Z7reduce6IfLj8ELb0EEvPT_S1_jPfS_j, .-_ZL43__device_stub__Z7reduce6IfLj8ELb0EEvPT_S1_jPfS_j
	.type	_ZL44__device_stub__Z7reduce6IfLj16ELb0EEvPT_S1_jPfS_j, @function
_ZL44__device_stub__Z7reduce6IfLj16ELb0EEvPT_S1_jPfS_j:
.LFB6768:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L196
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj16ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L196:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L198
	call	__stack_chk_fail@PLT
.L198:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6768:
	.size	_ZL44__device_stub__Z7reduce6IfLj16ELb0EEvPT_S1_jPfS_j, .-_ZL44__device_stub__Z7reduce6IfLj16ELb0EEvPT_S1_jPfS_j
	.type	_ZL44__device_stub__Z7reduce6IfLj32ELb0EEvPT_S1_jPfS_j, @function
_ZL44__device_stub__Z7reduce6IfLj32ELb0EEvPT_S1_jPfS_j:
.LFB6766:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L200
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj32ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L200:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L202
	call	__stack_chk_fail@PLT
.L202:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6766:
	.size	_ZL44__device_stub__Z7reduce6IfLj32ELb0EEvPT_S1_jPfS_j, .-_ZL44__device_stub__Z7reduce6IfLj32ELb0EEvPT_S1_jPfS_j
	.type	_ZL44__device_stub__Z7reduce6IfLj64ELb0EEvPT_S1_jPfS_j, @function
_ZL44__device_stub__Z7reduce6IfLj64ELb0EEvPT_S1_jPfS_j:
.LFB6764:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L204
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj64ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L204:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L206
	call	__stack_chk_fail@PLT
.L206:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6764:
	.size	_ZL44__device_stub__Z7reduce6IfLj64ELb0EEvPT_S1_jPfS_j, .-_ZL44__device_stub__Z7reduce6IfLj64ELb0EEvPT_S1_jPfS_j
	.type	_ZL45__device_stub__Z7reduce6IfLj128ELb0EEvPT_S1_jPfS_j, @function
_ZL45__device_stub__Z7reduce6IfLj128ELb0EEvPT_S1_jPfS_j:
.LFB6762:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L208
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj128ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L208:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L210
	call	__stack_chk_fail@PLT
.L210:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6762:
	.size	_ZL45__device_stub__Z7reduce6IfLj128ELb0EEvPT_S1_jPfS_j, .-_ZL45__device_stub__Z7reduce6IfLj128ELb0EEvPT_S1_jPfS_j
	.type	_ZL45__device_stub__Z7reduce6IfLj256ELb0EEvPT_S1_jPfS_j, @function
_ZL45__device_stub__Z7reduce6IfLj256ELb0EEvPT_S1_jPfS_j:
.LFB6760:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L212
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj256ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L212:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L214
	call	__stack_chk_fail@PLT
.L214:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6760:
	.size	_ZL45__device_stub__Z7reduce6IfLj256ELb0EEvPT_S1_jPfS_j, .-_ZL45__device_stub__Z7reduce6IfLj256ELb0EEvPT_S1_jPfS_j
	.type	_ZL45__device_stub__Z7reduce6IfLj512ELb0EEvPT_S1_jPfS_j, @function
_ZL45__device_stub__Z7reduce6IfLj512ELb0EEvPT_S1_jPfS_j:
.LFB6758:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L216
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj512ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L216:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L218
	call	__stack_chk_fail@PLT
.L218:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6758:
	.size	_ZL45__device_stub__Z7reduce6IfLj512ELb0EEvPT_S1_jPfS_j, .-_ZL45__device_stub__Z7reduce6IfLj512ELb0EEvPT_S1_jPfS_j
	.type	_ZL43__device_stub__Z7reduce6IfLj1ELb1EEvPT_S1_jPfS_j, @function
_ZL43__device_stub__Z7reduce6IfLj1ELb1EEvPT_S1_jPfS_j:
.LFB6756:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L220
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj1ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L220:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L222
	call	__stack_chk_fail@PLT
.L222:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6756:
	.size	_ZL43__device_stub__Z7reduce6IfLj1ELb1EEvPT_S1_jPfS_j, .-_ZL43__device_stub__Z7reduce6IfLj1ELb1EEvPT_S1_jPfS_j
	.type	_ZL43__device_stub__Z7reduce6IfLj2ELb1EEvPT_S1_jPfS_j, @function
_ZL43__device_stub__Z7reduce6IfLj2ELb1EEvPT_S1_jPfS_j:
.LFB6754:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L224
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj2ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L224:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L226
	call	__stack_chk_fail@PLT
.L226:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6754:
	.size	_ZL43__device_stub__Z7reduce6IfLj2ELb1EEvPT_S1_jPfS_j, .-_ZL43__device_stub__Z7reduce6IfLj2ELb1EEvPT_S1_jPfS_j
	.type	_ZL43__device_stub__Z7reduce6IfLj4ELb1EEvPT_S1_jPfS_j, @function
_ZL43__device_stub__Z7reduce6IfLj4ELb1EEvPT_S1_jPfS_j:
.LFB6752:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L228
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj4ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L228:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L230
	call	__stack_chk_fail@PLT
.L230:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6752:
	.size	_ZL43__device_stub__Z7reduce6IfLj4ELb1EEvPT_S1_jPfS_j, .-_ZL43__device_stub__Z7reduce6IfLj4ELb1EEvPT_S1_jPfS_j
	.type	_ZL43__device_stub__Z7reduce6IfLj8ELb1EEvPT_S1_jPfS_j, @function
_ZL43__device_stub__Z7reduce6IfLj8ELb1EEvPT_S1_jPfS_j:
.LFB6750:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L232
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj8ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L232:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L234
	call	__stack_chk_fail@PLT
.L234:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6750:
	.size	_ZL43__device_stub__Z7reduce6IfLj8ELb1EEvPT_S1_jPfS_j, .-_ZL43__device_stub__Z7reduce6IfLj8ELb1EEvPT_S1_jPfS_j
	.type	_ZL44__device_stub__Z7reduce6IfLj16ELb1EEvPT_S1_jPfS_j, @function
_ZL44__device_stub__Z7reduce6IfLj16ELb1EEvPT_S1_jPfS_j:
.LFB6748:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L236
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj16ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L236:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L238
	call	__stack_chk_fail@PLT
.L238:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6748:
	.size	_ZL44__device_stub__Z7reduce6IfLj16ELb1EEvPT_S1_jPfS_j, .-_ZL44__device_stub__Z7reduce6IfLj16ELb1EEvPT_S1_jPfS_j
	.type	_ZL44__device_stub__Z7reduce6IfLj32ELb1EEvPT_S1_jPfS_j, @function
_ZL44__device_stub__Z7reduce6IfLj32ELb1EEvPT_S1_jPfS_j:
.LFB6746:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L240
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj32ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L240:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L242
	call	__stack_chk_fail@PLT
.L242:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6746:
	.size	_ZL44__device_stub__Z7reduce6IfLj32ELb1EEvPT_S1_jPfS_j, .-_ZL44__device_stub__Z7reduce6IfLj32ELb1EEvPT_S1_jPfS_j
	.type	_ZL44__device_stub__Z7reduce6IfLj64ELb1EEvPT_S1_jPfS_j, @function
_ZL44__device_stub__Z7reduce6IfLj64ELb1EEvPT_S1_jPfS_j:
.LFB6744:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L244
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj64ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L244:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L246
	call	__stack_chk_fail@PLT
.L246:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6744:
	.size	_ZL44__device_stub__Z7reduce6IfLj64ELb1EEvPT_S1_jPfS_j, .-_ZL44__device_stub__Z7reduce6IfLj64ELb1EEvPT_S1_jPfS_j
	.type	_ZL45__device_stub__Z7reduce6IfLj128ELb1EEvPT_S1_jPfS_j, @function
_ZL45__device_stub__Z7reduce6IfLj128ELb1EEvPT_S1_jPfS_j:
.LFB6742:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L248
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj128ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L248:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L250
	call	__stack_chk_fail@PLT
.L250:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6742:
	.size	_ZL45__device_stub__Z7reduce6IfLj128ELb1EEvPT_S1_jPfS_j, .-_ZL45__device_stub__Z7reduce6IfLj128ELb1EEvPT_S1_jPfS_j
	.type	_ZL45__device_stub__Z7reduce6IfLj256ELb1EEvPT_S1_jPfS_j, @function
_ZL45__device_stub__Z7reduce6IfLj256ELb1EEvPT_S1_jPfS_j:
.LFB6740:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L252
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj256ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L252:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L254
	call	__stack_chk_fail@PLT
.L254:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6740:
	.size	_ZL45__device_stub__Z7reduce6IfLj256ELb1EEvPT_S1_jPfS_j, .-_ZL45__device_stub__Z7reduce6IfLj256ELb1EEvPT_S1_jPfS_j
	.type	_ZL45__device_stub__Z7reduce6IfLj512ELb1EEvPT_S1_jPfS_j, @function
_ZL45__device_stub__Z7reduce6IfLj512ELb1EEvPT_S1_jPfS_j:
.LFB6738:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L256
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IfLj512ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L256:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L258
	call	__stack_chk_fail@PLT
.L258:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6738:
	.size	_ZL45__device_stub__Z7reduce6IfLj512ELb1EEvPT_S1_jPfS_j, .-_ZL45__device_stub__Z7reduce6IfLj512ELb1EEvPT_S1_jPfS_j
	.type	_ZL39__device_stub__Z7reduce5IfLj1EEvPT_S1_jPfS_j, @function
_ZL39__device_stub__Z7reduce5IfLj1EEvPT_S1_jPfS_j:
.LFB6736:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L260
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L260:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L262
	call	__stack_chk_fail@PLT
.L262:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6736:
	.size	_ZL39__device_stub__Z7reduce5IfLj1EEvPT_S1_jPfS_j, .-_ZL39__device_stub__Z7reduce5IfLj1EEvPT_S1_jPfS_j
	.type	_ZL39__device_stub__Z7reduce5IfLj2EEvPT_S1_jPfS_j, @function
_ZL39__device_stub__Z7reduce5IfLj2EEvPT_S1_jPfS_j:
.LFB6734:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L264
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj2EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L264:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L266
	call	__stack_chk_fail@PLT
.L266:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6734:
	.size	_ZL39__device_stub__Z7reduce5IfLj2EEvPT_S1_jPfS_j, .-_ZL39__device_stub__Z7reduce5IfLj2EEvPT_S1_jPfS_j
	.type	_ZL39__device_stub__Z7reduce5IfLj4EEvPT_S1_jPfS_j, @function
_ZL39__device_stub__Z7reduce5IfLj4EEvPT_S1_jPfS_j:
.LFB6732:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L268
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj4EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L268:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L270
	call	__stack_chk_fail@PLT
.L270:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6732:
	.size	_ZL39__device_stub__Z7reduce5IfLj4EEvPT_S1_jPfS_j, .-_ZL39__device_stub__Z7reduce5IfLj4EEvPT_S1_jPfS_j
	.type	_ZL39__device_stub__Z7reduce5IfLj8EEvPT_S1_jPfS_j, @function
_ZL39__device_stub__Z7reduce5IfLj8EEvPT_S1_jPfS_j:
.LFB6730:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L272
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj8EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L272:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L274
	call	__stack_chk_fail@PLT
.L274:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6730:
	.size	_ZL39__device_stub__Z7reduce5IfLj8EEvPT_S1_jPfS_j, .-_ZL39__device_stub__Z7reduce5IfLj8EEvPT_S1_jPfS_j
	.type	_ZL40__device_stub__Z7reduce5IfLj16EEvPT_S1_jPfS_j, @function
_ZL40__device_stub__Z7reduce5IfLj16EEvPT_S1_jPfS_j:
.LFB6728:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L276
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj16EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L276:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L278
	call	__stack_chk_fail@PLT
.L278:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6728:
	.size	_ZL40__device_stub__Z7reduce5IfLj16EEvPT_S1_jPfS_j, .-_ZL40__device_stub__Z7reduce5IfLj16EEvPT_S1_jPfS_j
	.type	_ZL40__device_stub__Z7reduce5IfLj32EEvPT_S1_jPfS_j, @function
_ZL40__device_stub__Z7reduce5IfLj32EEvPT_S1_jPfS_j:
.LFB6726:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L280
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj32EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L280:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L282
	call	__stack_chk_fail@PLT
.L282:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6726:
	.size	_ZL40__device_stub__Z7reduce5IfLj32EEvPT_S1_jPfS_j, .-_ZL40__device_stub__Z7reduce5IfLj32EEvPT_S1_jPfS_j
	.type	_ZL40__device_stub__Z7reduce5IfLj64EEvPT_S1_jPfS_j, @function
_ZL40__device_stub__Z7reduce5IfLj64EEvPT_S1_jPfS_j:
.LFB6724:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L284
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj64EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L284:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L286
	call	__stack_chk_fail@PLT
.L286:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6724:
	.size	_ZL40__device_stub__Z7reduce5IfLj64EEvPT_S1_jPfS_j, .-_ZL40__device_stub__Z7reduce5IfLj64EEvPT_S1_jPfS_j
	.type	_ZL41__device_stub__Z7reduce5IfLj128EEvPT_S1_jPfS_j, @function
_ZL41__device_stub__Z7reduce5IfLj128EEvPT_S1_jPfS_j:
.LFB6722:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L288
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj128EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L288:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L290
	call	__stack_chk_fail@PLT
.L290:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6722:
	.size	_ZL41__device_stub__Z7reduce5IfLj128EEvPT_S1_jPfS_j, .-_ZL41__device_stub__Z7reduce5IfLj128EEvPT_S1_jPfS_j
	.type	_ZL41__device_stub__Z7reduce5IfLj256EEvPT_S1_jPfS_j, @function
_ZL41__device_stub__Z7reduce5IfLj256EEvPT_S1_jPfS_j:
.LFB6720:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L292
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj256EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L292:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L294
	call	__stack_chk_fail@PLT
.L294:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6720:
	.size	_ZL41__device_stub__Z7reduce5IfLj256EEvPT_S1_jPfS_j, .-_ZL41__device_stub__Z7reduce5IfLj256EEvPT_S1_jPfS_j
	.type	_ZL41__device_stub__Z7reduce5IfLj512EEvPT_S1_jPfS_j, @function
_ZL41__device_stub__Z7reduce5IfLj512EEvPT_S1_jPfS_j:
.LFB6718:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L296
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IfLj512EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L296:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L298
	call	__stack_chk_fail@PLT
.L298:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6718:
	.size	_ZL41__device_stub__Z7reduce5IfLj512EEvPT_S1_jPfS_j, .-_ZL41__device_stub__Z7reduce5IfLj512EEvPT_S1_jPfS_j
	.type	_ZL39__device_stub__Z7reduce4IfLj1EEvPT_S1_jPfS_j, @function
_ZL39__device_stub__Z7reduce4IfLj1EEvPT_S1_jPfS_j:
.LFB6716:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L300
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L300:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L302
	call	__stack_chk_fail@PLT
.L302:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6716:
	.size	_ZL39__device_stub__Z7reduce4IfLj1EEvPT_S1_jPfS_j, .-_ZL39__device_stub__Z7reduce4IfLj1EEvPT_S1_jPfS_j
	.type	_ZL39__device_stub__Z7reduce4IfLj2EEvPT_S1_jPfS_j, @function
_ZL39__device_stub__Z7reduce4IfLj2EEvPT_S1_jPfS_j:
.LFB6714:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L304
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj2EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L304:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L306
	call	__stack_chk_fail@PLT
.L306:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6714:
	.size	_ZL39__device_stub__Z7reduce4IfLj2EEvPT_S1_jPfS_j, .-_ZL39__device_stub__Z7reduce4IfLj2EEvPT_S1_jPfS_j
	.type	_ZL39__device_stub__Z7reduce4IfLj4EEvPT_S1_jPfS_j, @function
_ZL39__device_stub__Z7reduce4IfLj4EEvPT_S1_jPfS_j:
.LFB6712:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L308
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj4EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L308:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L310
	call	__stack_chk_fail@PLT
.L310:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6712:
	.size	_ZL39__device_stub__Z7reduce4IfLj4EEvPT_S1_jPfS_j, .-_ZL39__device_stub__Z7reduce4IfLj4EEvPT_S1_jPfS_j
	.type	_ZL39__device_stub__Z7reduce4IfLj8EEvPT_S1_jPfS_j, @function
_ZL39__device_stub__Z7reduce4IfLj8EEvPT_S1_jPfS_j:
.LFB6710:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L312
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj8EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L312:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L314
	call	__stack_chk_fail@PLT
.L314:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6710:
	.size	_ZL39__device_stub__Z7reduce4IfLj8EEvPT_S1_jPfS_j, .-_ZL39__device_stub__Z7reduce4IfLj8EEvPT_S1_jPfS_j
	.type	_ZL40__device_stub__Z7reduce4IfLj16EEvPT_S1_jPfS_j, @function
_ZL40__device_stub__Z7reduce4IfLj16EEvPT_S1_jPfS_j:
.LFB6708:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L316
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj16EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L316:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L318
	call	__stack_chk_fail@PLT
.L318:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6708:
	.size	_ZL40__device_stub__Z7reduce4IfLj16EEvPT_S1_jPfS_j, .-_ZL40__device_stub__Z7reduce4IfLj16EEvPT_S1_jPfS_j
	.type	_ZL40__device_stub__Z7reduce4IfLj32EEvPT_S1_jPfS_j, @function
_ZL40__device_stub__Z7reduce4IfLj32EEvPT_S1_jPfS_j:
.LFB6706:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L320
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj32EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L320:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L322
	call	__stack_chk_fail@PLT
.L322:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6706:
	.size	_ZL40__device_stub__Z7reduce4IfLj32EEvPT_S1_jPfS_j, .-_ZL40__device_stub__Z7reduce4IfLj32EEvPT_S1_jPfS_j
	.type	_ZL40__device_stub__Z7reduce4IfLj64EEvPT_S1_jPfS_j, @function
_ZL40__device_stub__Z7reduce4IfLj64EEvPT_S1_jPfS_j:
.LFB6704:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L324
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj64EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L324:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L326
	call	__stack_chk_fail@PLT
.L326:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6704:
	.size	_ZL40__device_stub__Z7reduce4IfLj64EEvPT_S1_jPfS_j, .-_ZL40__device_stub__Z7reduce4IfLj64EEvPT_S1_jPfS_j
	.type	_ZL41__device_stub__Z7reduce4IfLj128EEvPT_S1_jPfS_j, @function
_ZL41__device_stub__Z7reduce4IfLj128EEvPT_S1_jPfS_j:
.LFB6702:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L328
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj128EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L328:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L330
	call	__stack_chk_fail@PLT
.L330:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6702:
	.size	_ZL41__device_stub__Z7reduce4IfLj128EEvPT_S1_jPfS_j, .-_ZL41__device_stub__Z7reduce4IfLj128EEvPT_S1_jPfS_j
	.type	_ZL41__device_stub__Z7reduce4IfLj256EEvPT_S1_jPfS_j, @function
_ZL41__device_stub__Z7reduce4IfLj256EEvPT_S1_jPfS_j:
.LFB6700:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L332
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj256EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L332:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L334
	call	__stack_chk_fail@PLT
.L334:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6700:
	.size	_ZL41__device_stub__Z7reduce4IfLj256EEvPT_S1_jPfS_j, .-_ZL41__device_stub__Z7reduce4IfLj256EEvPT_S1_jPfS_j
	.type	_ZL41__device_stub__Z7reduce4IfLj512EEvPT_S1_jPfS_j, @function
_ZL41__device_stub__Z7reduce4IfLj512EEvPT_S1_jPfS_j:
.LFB6698:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L336
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IfLj512EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L336:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L338
	call	__stack_chk_fail@PLT
.L338:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6698:
	.size	_ZL41__device_stub__Z7reduce4IfLj512EEvPT_S1_jPfS_j, .-_ZL41__device_stub__Z7reduce4IfLj512EEvPT_S1_jPfS_j
	.type	_ZL35__device_stub__Z7reduce3IfEvPT_S1_jPfS_j, @function
_ZL35__device_stub__Z7reduce3IfEvPT_S1_jPfS_j:
.LFB6696:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L340
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce3IfEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L340:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L342
	call	__stack_chk_fail@PLT
.L342:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6696:
	.size	_ZL35__device_stub__Z7reduce3IfEvPT_S1_jPfS_j, .-_ZL35__device_stub__Z7reduce3IfEvPT_S1_jPfS_j
	.type	_ZL35__device_stub__Z7reduce2IfEvPT_S1_jPfS_j, @function
_ZL35__device_stub__Z7reduce2IfEvPT_S1_jPfS_j:
.LFB6694:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L344
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce2IfEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L344:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L346
	call	__stack_chk_fail@PLT
.L346:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6694:
	.size	_ZL35__device_stub__Z7reduce2IfEvPT_S1_jPfS_j, .-_ZL35__device_stub__Z7reduce2IfEvPT_S1_jPfS_j
	.type	_ZL35__device_stub__Z7reduce1IfEvPT_S1_jPfS_j, @function
_ZL35__device_stub__Z7reduce1IfEvPT_S1_jPfS_j:
.LFB6692:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L348
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce1IfEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L348:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L350
	call	__stack_chk_fail@PLT
.L350:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6692:
	.size	_ZL35__device_stub__Z7reduce1IfEvPT_S1_jPfS_j, .-_ZL35__device_stub__Z7reduce1IfEvPT_S1_jPfS_j
	.type	_ZL35__device_stub__Z7reduce0IfEvPT_S1_jPfS_j, @function
_ZL35__device_stub__Z7reduce0IfEvPT_S1_jPfS_j:
.LFB6690:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L352
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce0IfEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L352:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L354
	call	__stack_chk_fail@PLT
.L354:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6690:
	.size	_ZL35__device_stub__Z7reduce0IfEvPT_S1_jPfS_j, .-_ZL35__device_stub__Z7reduce0IfEvPT_S1_jPfS_j
	.type	_ZL43__device_stub__Z7reduce6IiLj1ELb0EEvPT_S1_jPiS_j, @function
_ZL43__device_stub__Z7reduce6IiLj1ELb0EEvPT_S1_jPiS_j:
.LFB6688:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L356
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj1ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L356:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L358
	call	__stack_chk_fail@PLT
.L358:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6688:
	.size	_ZL43__device_stub__Z7reduce6IiLj1ELb0EEvPT_S1_jPiS_j, .-_ZL43__device_stub__Z7reduce6IiLj1ELb0EEvPT_S1_jPiS_j
	.type	_ZL43__device_stub__Z7reduce6IiLj2ELb0EEvPT_S1_jPiS_j, @function
_ZL43__device_stub__Z7reduce6IiLj2ELb0EEvPT_S1_jPiS_j:
.LFB6686:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L360
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj2ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L360:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L362
	call	__stack_chk_fail@PLT
.L362:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6686:
	.size	_ZL43__device_stub__Z7reduce6IiLj2ELb0EEvPT_S1_jPiS_j, .-_ZL43__device_stub__Z7reduce6IiLj2ELb0EEvPT_S1_jPiS_j
	.type	_ZL43__device_stub__Z7reduce6IiLj4ELb0EEvPT_S1_jPiS_j, @function
_ZL43__device_stub__Z7reduce6IiLj4ELb0EEvPT_S1_jPiS_j:
.LFB6684:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L364
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj4ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L364:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L366
	call	__stack_chk_fail@PLT
.L366:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6684:
	.size	_ZL43__device_stub__Z7reduce6IiLj4ELb0EEvPT_S1_jPiS_j, .-_ZL43__device_stub__Z7reduce6IiLj4ELb0EEvPT_S1_jPiS_j
	.type	_ZL43__device_stub__Z7reduce6IiLj8ELb0EEvPT_S1_jPiS_j, @function
_ZL43__device_stub__Z7reduce6IiLj8ELb0EEvPT_S1_jPiS_j:
.LFB6682:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L368
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj8ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L368:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L370
	call	__stack_chk_fail@PLT
.L370:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6682:
	.size	_ZL43__device_stub__Z7reduce6IiLj8ELb0EEvPT_S1_jPiS_j, .-_ZL43__device_stub__Z7reduce6IiLj8ELb0EEvPT_S1_jPiS_j
	.type	_ZL44__device_stub__Z7reduce6IiLj16ELb0EEvPT_S1_jPiS_j, @function
_ZL44__device_stub__Z7reduce6IiLj16ELb0EEvPT_S1_jPiS_j:
.LFB6680:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L372
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj16ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L372:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L374
	call	__stack_chk_fail@PLT
.L374:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6680:
	.size	_ZL44__device_stub__Z7reduce6IiLj16ELb0EEvPT_S1_jPiS_j, .-_ZL44__device_stub__Z7reduce6IiLj16ELb0EEvPT_S1_jPiS_j
	.type	_ZL44__device_stub__Z7reduce6IiLj32ELb0EEvPT_S1_jPiS_j, @function
_ZL44__device_stub__Z7reduce6IiLj32ELb0EEvPT_S1_jPiS_j:
.LFB6678:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L376
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj32ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L376:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L378
	call	__stack_chk_fail@PLT
.L378:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6678:
	.size	_ZL44__device_stub__Z7reduce6IiLj32ELb0EEvPT_S1_jPiS_j, .-_ZL44__device_stub__Z7reduce6IiLj32ELb0EEvPT_S1_jPiS_j
	.type	_ZL44__device_stub__Z7reduce6IiLj64ELb0EEvPT_S1_jPiS_j, @function
_ZL44__device_stub__Z7reduce6IiLj64ELb0EEvPT_S1_jPiS_j:
.LFB6676:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L380
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj64ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L380:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L382
	call	__stack_chk_fail@PLT
.L382:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6676:
	.size	_ZL44__device_stub__Z7reduce6IiLj64ELb0EEvPT_S1_jPiS_j, .-_ZL44__device_stub__Z7reduce6IiLj64ELb0EEvPT_S1_jPiS_j
	.type	_ZL45__device_stub__Z7reduce6IiLj128ELb0EEvPT_S1_jPiS_j, @function
_ZL45__device_stub__Z7reduce6IiLj128ELb0EEvPT_S1_jPiS_j:
.LFB6674:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L384
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj128ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L384:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L386
	call	__stack_chk_fail@PLT
.L386:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6674:
	.size	_ZL45__device_stub__Z7reduce6IiLj128ELb0EEvPT_S1_jPiS_j, .-_ZL45__device_stub__Z7reduce6IiLj128ELb0EEvPT_S1_jPiS_j
	.type	_ZL45__device_stub__Z7reduce6IiLj256ELb0EEvPT_S1_jPiS_j, @function
_ZL45__device_stub__Z7reduce6IiLj256ELb0EEvPT_S1_jPiS_j:
.LFB6672:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L388
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj256ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L388:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L390
	call	__stack_chk_fail@PLT
.L390:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6672:
	.size	_ZL45__device_stub__Z7reduce6IiLj256ELb0EEvPT_S1_jPiS_j, .-_ZL45__device_stub__Z7reduce6IiLj256ELb0EEvPT_S1_jPiS_j
	.type	_ZL45__device_stub__Z7reduce6IiLj512ELb0EEvPT_S1_jPiS_j, @function
_ZL45__device_stub__Z7reduce6IiLj512ELb0EEvPT_S1_jPiS_j:
.LFB6670:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L392
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj512ELb0EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L392:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L394
	call	__stack_chk_fail@PLT
.L394:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6670:
	.size	_ZL45__device_stub__Z7reduce6IiLj512ELb0EEvPT_S1_jPiS_j, .-_ZL45__device_stub__Z7reduce6IiLj512ELb0EEvPT_S1_jPiS_j
	.type	_ZL43__device_stub__Z7reduce6IiLj1ELb1EEvPT_S1_jPiS_j, @function
_ZL43__device_stub__Z7reduce6IiLj1ELb1EEvPT_S1_jPiS_j:
.LFB6668:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L396
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj1ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L396:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L398
	call	__stack_chk_fail@PLT
.L398:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6668:
	.size	_ZL43__device_stub__Z7reduce6IiLj1ELb1EEvPT_S1_jPiS_j, .-_ZL43__device_stub__Z7reduce6IiLj1ELb1EEvPT_S1_jPiS_j
	.type	_ZL43__device_stub__Z7reduce6IiLj2ELb1EEvPT_S1_jPiS_j, @function
_ZL43__device_stub__Z7reduce6IiLj2ELb1EEvPT_S1_jPiS_j:
.LFB6666:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L400
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj2ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L400:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L402
	call	__stack_chk_fail@PLT
.L402:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6666:
	.size	_ZL43__device_stub__Z7reduce6IiLj2ELb1EEvPT_S1_jPiS_j, .-_ZL43__device_stub__Z7reduce6IiLj2ELb1EEvPT_S1_jPiS_j
	.type	_ZL43__device_stub__Z7reduce6IiLj4ELb1EEvPT_S1_jPiS_j, @function
_ZL43__device_stub__Z7reduce6IiLj4ELb1EEvPT_S1_jPiS_j:
.LFB6664:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L404
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj4ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L404:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L406
	call	__stack_chk_fail@PLT
.L406:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6664:
	.size	_ZL43__device_stub__Z7reduce6IiLj4ELb1EEvPT_S1_jPiS_j, .-_ZL43__device_stub__Z7reduce6IiLj4ELb1EEvPT_S1_jPiS_j
	.type	_ZL43__device_stub__Z7reduce6IiLj8ELb1EEvPT_S1_jPiS_j, @function
_ZL43__device_stub__Z7reduce6IiLj8ELb1EEvPT_S1_jPiS_j:
.LFB6662:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L408
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj8ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L408:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L410
	call	__stack_chk_fail@PLT
.L410:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6662:
	.size	_ZL43__device_stub__Z7reduce6IiLj8ELb1EEvPT_S1_jPiS_j, .-_ZL43__device_stub__Z7reduce6IiLj8ELb1EEvPT_S1_jPiS_j
	.type	_ZL44__device_stub__Z7reduce6IiLj16ELb1EEvPT_S1_jPiS_j, @function
_ZL44__device_stub__Z7reduce6IiLj16ELb1EEvPT_S1_jPiS_j:
.LFB6660:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L412
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj16ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L412:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L414
	call	__stack_chk_fail@PLT
.L414:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6660:
	.size	_ZL44__device_stub__Z7reduce6IiLj16ELb1EEvPT_S1_jPiS_j, .-_ZL44__device_stub__Z7reduce6IiLj16ELb1EEvPT_S1_jPiS_j
	.type	_ZL44__device_stub__Z7reduce6IiLj32ELb1EEvPT_S1_jPiS_j, @function
_ZL44__device_stub__Z7reduce6IiLj32ELb1EEvPT_S1_jPiS_j:
.LFB6658:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L416
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj32ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L416:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L418
	call	__stack_chk_fail@PLT
.L418:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6658:
	.size	_ZL44__device_stub__Z7reduce6IiLj32ELb1EEvPT_S1_jPiS_j, .-_ZL44__device_stub__Z7reduce6IiLj32ELb1EEvPT_S1_jPiS_j
	.type	_ZL44__device_stub__Z7reduce6IiLj64ELb1EEvPT_S1_jPiS_j, @function
_ZL44__device_stub__Z7reduce6IiLj64ELb1EEvPT_S1_jPiS_j:
.LFB6656:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L420
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj64ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L420:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L422
	call	__stack_chk_fail@PLT
.L422:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6656:
	.size	_ZL44__device_stub__Z7reduce6IiLj64ELb1EEvPT_S1_jPiS_j, .-_ZL44__device_stub__Z7reduce6IiLj64ELb1EEvPT_S1_jPiS_j
	.type	_ZL45__device_stub__Z7reduce6IiLj128ELb1EEvPT_S1_jPiS_j, @function
_ZL45__device_stub__Z7reduce6IiLj128ELb1EEvPT_S1_jPiS_j:
.LFB6654:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L424
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj128ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L424:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L426
	call	__stack_chk_fail@PLT
.L426:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6654:
	.size	_ZL45__device_stub__Z7reduce6IiLj128ELb1EEvPT_S1_jPiS_j, .-_ZL45__device_stub__Z7reduce6IiLj128ELb1EEvPT_S1_jPiS_j
	.type	_ZL45__device_stub__Z7reduce6IiLj256ELb1EEvPT_S1_jPiS_j, @function
_ZL45__device_stub__Z7reduce6IiLj256ELb1EEvPT_S1_jPiS_j:
.LFB6652:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L428
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj256ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L428:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L430
	call	__stack_chk_fail@PLT
.L430:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6652:
	.size	_ZL45__device_stub__Z7reduce6IiLj256ELb1EEvPT_S1_jPiS_j, .-_ZL45__device_stub__Z7reduce6IiLj256ELb1EEvPT_S1_jPiS_j
	.type	_ZL45__device_stub__Z7reduce6IiLj512ELb1EEvPT_S1_jPiS_j, @function
_ZL45__device_stub__Z7reduce6IiLj512ELb1EEvPT_S1_jPiS_j:
.LFB6650:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L432
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce6IiLj512ELb1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L432:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L434
	call	__stack_chk_fail@PLT
.L434:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6650:
	.size	_ZL45__device_stub__Z7reduce6IiLj512ELb1EEvPT_S1_jPiS_j, .-_ZL45__device_stub__Z7reduce6IiLj512ELb1EEvPT_S1_jPiS_j
	.type	_ZL39__device_stub__Z7reduce5IiLj1EEvPT_S1_jPiS_j, @function
_ZL39__device_stub__Z7reduce5IiLj1EEvPT_S1_jPiS_j:
.LFB6648:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L436
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L436:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L438
	call	__stack_chk_fail@PLT
.L438:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6648:
	.size	_ZL39__device_stub__Z7reduce5IiLj1EEvPT_S1_jPiS_j, .-_ZL39__device_stub__Z7reduce5IiLj1EEvPT_S1_jPiS_j
	.type	_ZL39__device_stub__Z7reduce5IiLj2EEvPT_S1_jPiS_j, @function
_ZL39__device_stub__Z7reduce5IiLj2EEvPT_S1_jPiS_j:
.LFB6646:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L440
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj2EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L440:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L442
	call	__stack_chk_fail@PLT
.L442:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6646:
	.size	_ZL39__device_stub__Z7reduce5IiLj2EEvPT_S1_jPiS_j, .-_ZL39__device_stub__Z7reduce5IiLj2EEvPT_S1_jPiS_j
	.type	_ZL39__device_stub__Z7reduce5IiLj4EEvPT_S1_jPiS_j, @function
_ZL39__device_stub__Z7reduce5IiLj4EEvPT_S1_jPiS_j:
.LFB6644:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L444
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj4EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L444:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L446
	call	__stack_chk_fail@PLT
.L446:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6644:
	.size	_ZL39__device_stub__Z7reduce5IiLj4EEvPT_S1_jPiS_j, .-_ZL39__device_stub__Z7reduce5IiLj4EEvPT_S1_jPiS_j
	.type	_ZL39__device_stub__Z7reduce5IiLj8EEvPT_S1_jPiS_j, @function
_ZL39__device_stub__Z7reduce5IiLj8EEvPT_S1_jPiS_j:
.LFB6642:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L448
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj8EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L448:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L450
	call	__stack_chk_fail@PLT
.L450:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6642:
	.size	_ZL39__device_stub__Z7reduce5IiLj8EEvPT_S1_jPiS_j, .-_ZL39__device_stub__Z7reduce5IiLj8EEvPT_S1_jPiS_j
	.type	_ZL40__device_stub__Z7reduce5IiLj16EEvPT_S1_jPiS_j, @function
_ZL40__device_stub__Z7reduce5IiLj16EEvPT_S1_jPiS_j:
.LFB6640:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L452
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj16EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L452:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L454
	call	__stack_chk_fail@PLT
.L454:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6640:
	.size	_ZL40__device_stub__Z7reduce5IiLj16EEvPT_S1_jPiS_j, .-_ZL40__device_stub__Z7reduce5IiLj16EEvPT_S1_jPiS_j
	.type	_ZL40__device_stub__Z7reduce5IiLj32EEvPT_S1_jPiS_j, @function
_ZL40__device_stub__Z7reduce5IiLj32EEvPT_S1_jPiS_j:
.LFB6638:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L456
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj32EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L456:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L458
	call	__stack_chk_fail@PLT
.L458:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6638:
	.size	_ZL40__device_stub__Z7reduce5IiLj32EEvPT_S1_jPiS_j, .-_ZL40__device_stub__Z7reduce5IiLj32EEvPT_S1_jPiS_j
	.type	_ZL40__device_stub__Z7reduce5IiLj64EEvPT_S1_jPiS_j, @function
_ZL40__device_stub__Z7reduce5IiLj64EEvPT_S1_jPiS_j:
.LFB6636:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L460
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj64EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L460:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L462
	call	__stack_chk_fail@PLT
.L462:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6636:
	.size	_ZL40__device_stub__Z7reduce5IiLj64EEvPT_S1_jPiS_j, .-_ZL40__device_stub__Z7reduce5IiLj64EEvPT_S1_jPiS_j
	.type	_ZL41__device_stub__Z7reduce5IiLj128EEvPT_S1_jPiS_j, @function
_ZL41__device_stub__Z7reduce5IiLj128EEvPT_S1_jPiS_j:
.LFB6634:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L464
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj128EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L464:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L466
	call	__stack_chk_fail@PLT
.L466:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6634:
	.size	_ZL41__device_stub__Z7reduce5IiLj128EEvPT_S1_jPiS_j, .-_ZL41__device_stub__Z7reduce5IiLj128EEvPT_S1_jPiS_j
	.type	_ZL41__device_stub__Z7reduce5IiLj256EEvPT_S1_jPiS_j, @function
_ZL41__device_stub__Z7reduce5IiLj256EEvPT_S1_jPiS_j:
.LFB6632:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L468
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj256EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L468:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L470
	call	__stack_chk_fail@PLT
.L470:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6632:
	.size	_ZL41__device_stub__Z7reduce5IiLj256EEvPT_S1_jPiS_j, .-_ZL41__device_stub__Z7reduce5IiLj256EEvPT_S1_jPiS_j
	.type	_ZL41__device_stub__Z7reduce5IiLj512EEvPT_S1_jPiS_j, @function
_ZL41__device_stub__Z7reduce5IiLj512EEvPT_S1_jPiS_j:
.LFB6630:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L472
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce5IiLj512EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L472:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L474
	call	__stack_chk_fail@PLT
.L474:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6630:
	.size	_ZL41__device_stub__Z7reduce5IiLj512EEvPT_S1_jPiS_j, .-_ZL41__device_stub__Z7reduce5IiLj512EEvPT_S1_jPiS_j
	.type	_ZL39__device_stub__Z7reduce4IiLj1EEvPT_S1_jPiS_j, @function
_ZL39__device_stub__Z7reduce4IiLj1EEvPT_S1_jPiS_j:
.LFB6628:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L476
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj1EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L476:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L478
	call	__stack_chk_fail@PLT
.L478:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6628:
	.size	_ZL39__device_stub__Z7reduce4IiLj1EEvPT_S1_jPiS_j, .-_ZL39__device_stub__Z7reduce4IiLj1EEvPT_S1_jPiS_j
	.type	_ZL39__device_stub__Z7reduce4IiLj2EEvPT_S1_jPiS_j, @function
_ZL39__device_stub__Z7reduce4IiLj2EEvPT_S1_jPiS_j:
.LFB6626:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L480
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj2EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L480:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L482
	call	__stack_chk_fail@PLT
.L482:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6626:
	.size	_ZL39__device_stub__Z7reduce4IiLj2EEvPT_S1_jPiS_j, .-_ZL39__device_stub__Z7reduce4IiLj2EEvPT_S1_jPiS_j
	.type	_ZL39__device_stub__Z7reduce4IiLj4EEvPT_S1_jPiS_j, @function
_ZL39__device_stub__Z7reduce4IiLj4EEvPT_S1_jPiS_j:
.LFB6624:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L484
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj4EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L484:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L486
	call	__stack_chk_fail@PLT
.L486:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6624:
	.size	_ZL39__device_stub__Z7reduce4IiLj4EEvPT_S1_jPiS_j, .-_ZL39__device_stub__Z7reduce4IiLj4EEvPT_S1_jPiS_j
	.type	_ZL39__device_stub__Z7reduce4IiLj8EEvPT_S1_jPiS_j, @function
_ZL39__device_stub__Z7reduce4IiLj8EEvPT_S1_jPiS_j:
.LFB6622:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L488
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj8EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L488:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L490
	call	__stack_chk_fail@PLT
.L490:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6622:
	.size	_ZL39__device_stub__Z7reduce4IiLj8EEvPT_S1_jPiS_j, .-_ZL39__device_stub__Z7reduce4IiLj8EEvPT_S1_jPiS_j
	.type	_ZL40__device_stub__Z7reduce4IiLj16EEvPT_S1_jPiS_j, @function
_ZL40__device_stub__Z7reduce4IiLj16EEvPT_S1_jPiS_j:
.LFB6620:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L492
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj16EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L492:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L494
	call	__stack_chk_fail@PLT
.L494:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6620:
	.size	_ZL40__device_stub__Z7reduce4IiLj16EEvPT_S1_jPiS_j, .-_ZL40__device_stub__Z7reduce4IiLj16EEvPT_S1_jPiS_j
	.type	_ZL40__device_stub__Z7reduce4IiLj32EEvPT_S1_jPiS_j, @function
_ZL40__device_stub__Z7reduce4IiLj32EEvPT_S1_jPiS_j:
.LFB6618:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L496
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj32EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L496:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L498
	call	__stack_chk_fail@PLT
.L498:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6618:
	.size	_ZL40__device_stub__Z7reduce4IiLj32EEvPT_S1_jPiS_j, .-_ZL40__device_stub__Z7reduce4IiLj32EEvPT_S1_jPiS_j
	.type	_ZL40__device_stub__Z7reduce4IiLj64EEvPT_S1_jPiS_j, @function
_ZL40__device_stub__Z7reduce4IiLj64EEvPT_S1_jPiS_j:
.LFB6616:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L500
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj64EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L500:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L502
	call	__stack_chk_fail@PLT
.L502:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6616:
	.size	_ZL40__device_stub__Z7reduce4IiLj64EEvPT_S1_jPiS_j, .-_ZL40__device_stub__Z7reduce4IiLj64EEvPT_S1_jPiS_j
	.type	_ZL41__device_stub__Z7reduce4IiLj128EEvPT_S1_jPiS_j, @function
_ZL41__device_stub__Z7reduce4IiLj128EEvPT_S1_jPiS_j:
.LFB6614:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L504
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj128EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L504:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L506
	call	__stack_chk_fail@PLT
.L506:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6614:
	.size	_ZL41__device_stub__Z7reduce4IiLj128EEvPT_S1_jPiS_j, .-_ZL41__device_stub__Z7reduce4IiLj128EEvPT_S1_jPiS_j
	.type	_ZL41__device_stub__Z7reduce4IiLj256EEvPT_S1_jPiS_j, @function
_ZL41__device_stub__Z7reduce4IiLj256EEvPT_S1_jPiS_j:
.LFB6612:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L508
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj256EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L508:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L510
	call	__stack_chk_fail@PLT
.L510:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6612:
	.size	_ZL41__device_stub__Z7reduce4IiLj256EEvPT_S1_jPiS_j, .-_ZL41__device_stub__Z7reduce4IiLj256EEvPT_S1_jPiS_j
	.type	_ZL41__device_stub__Z7reduce4IiLj512EEvPT_S1_jPiS_j, @function
_ZL41__device_stub__Z7reduce4IiLj512EEvPT_S1_jPiS_j:
.LFB6610:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L512
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce4IiLj512EEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L512:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L514
	call	__stack_chk_fail@PLT
.L514:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6610:
	.size	_ZL41__device_stub__Z7reduce4IiLj512EEvPT_S1_jPiS_j, .-_ZL41__device_stub__Z7reduce4IiLj512EEvPT_S1_jPiS_j
	.type	_ZL35__device_stub__Z7reduce3IiEvPT_S1_jPiS_j, @function
_ZL35__device_stub__Z7reduce3IiEvPT_S1_jPiS_j:
.LFB6608:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L516
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce3IiEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L516:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L518
	call	__stack_chk_fail@PLT
.L518:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6608:
	.size	_ZL35__device_stub__Z7reduce3IiEvPT_S1_jPiS_j, .-_ZL35__device_stub__Z7reduce3IiEvPT_S1_jPiS_j
	.type	_ZL35__device_stub__Z7reduce2IiEvPT_S1_jPiS_j, @function
_ZL35__device_stub__Z7reduce2IiEvPT_S1_jPiS_j:
.LFB6606:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L520
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce2IiEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L520:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L522
	call	__stack_chk_fail@PLT
.L522:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6606:
	.size	_ZL35__device_stub__Z7reduce2IiEvPT_S1_jPiS_j, .-_ZL35__device_stub__Z7reduce2IiEvPT_S1_jPiS_j
	.type	_ZL35__device_stub__Z7reduce1IiEvPT_S1_jPiS_j, @function
_ZL35__device_stub__Z7reduce1IiEvPT_S1_jPiS_j:
.LFB6604:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L524
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce1IiEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L524:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L526
	call	__stack_chk_fail@PLT
.L526:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6604:
	.size	_ZL35__device_stub__Z7reduce1IiEvPT_S1_jPiS_j, .-_ZL35__device_stub__Z7reduce1IiEvPT_S1_jPiS_j
	.type	_ZL35__device_stub__Z7reduce0IiEvPT_S1_jPiS_j, @function
_ZL35__device_stub__Z7reduce0IiEvPT_S1_jPiS_j:
.LFB6602:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L528
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7reduce0IiEvPT_S1_j(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L528:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L530
	call	__stack_chk_fail@PLT
.L530:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6602:
	.size	_ZL35__device_stub__Z7reduce0IiEvPT_S1_jPiS_j, .-_ZL35__device_stub__Z7reduce0IiEvPT_S1_jPiS_j
	.section	.text._Z7reduce6IdLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj1ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj1ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj1ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj1ELb0EEvPT_S1_j:
.LFB7441:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IdLj1ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7441:
	.size	_Z7reduce6IdLj1ELb0EEvPT_S1_j, .-_Z7reduce6IdLj1ELb0EEvPT_S1_j
	.section	.text._Z7reduce0IiEvPT_S1_j,"axG",@progbits,_Z7reduce0IiEvPT_S1_j,comdat
	.weak	_Z7reduce0IiEvPT_S1_j
	.type	_Z7reduce0IiEvPT_S1_j, @function
_Z7reduce0IiEvPT_S1_j:
.LFB7309:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce0IiEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7309:
	.size	_Z7reduce0IiEvPT_S1_j, .-_Z7reduce0IiEvPT_S1_j
	.section	.text._Z7reduce1IiEvPT_S1_j,"axG",@progbits,_Z7reduce1IiEvPT_S1_j,comdat
	.weak	_Z7reduce1IiEvPT_S1_j
	.type	_Z7reduce1IiEvPT_S1_j, @function
_Z7reduce1IiEvPT_S1_j:
.LFB7311:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce1IiEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7311:
	.size	_Z7reduce1IiEvPT_S1_j, .-_Z7reduce1IiEvPT_S1_j
	.section	.text._Z7reduce2IiEvPT_S1_j,"axG",@progbits,_Z7reduce2IiEvPT_S1_j,comdat
	.weak	_Z7reduce2IiEvPT_S1_j
	.type	_Z7reduce2IiEvPT_S1_j, @function
_Z7reduce2IiEvPT_S1_j:
.LFB7312:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce2IiEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7312:
	.size	_Z7reduce2IiEvPT_S1_j, .-_Z7reduce2IiEvPT_S1_j
	.section	.text._Z7reduce3IiEvPT_S1_j,"axG",@progbits,_Z7reduce3IiEvPT_S1_j,comdat
	.weak	_Z7reduce3IiEvPT_S1_j
	.type	_Z7reduce3IiEvPT_S1_j, @function
_Z7reduce3IiEvPT_S1_j:
.LFB7313:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce3IiEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7313:
	.size	_Z7reduce3IiEvPT_S1_j, .-_Z7reduce3IiEvPT_S1_j
	.section	.text._Z7reduce4IiLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj512EEvPT_S1_j
	.type	_Z7reduce4IiLj512EEvPT_S1_j, @function
_Z7reduce4IiLj512EEvPT_S1_j:
.LFB7314:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce4IiLj512EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7314:
	.size	_Z7reduce4IiLj512EEvPT_S1_j, .-_Z7reduce4IiLj512EEvPT_S1_j
	.section	.text._Z7reduce4IiLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj256EEvPT_S1_j
	.type	_Z7reduce4IiLj256EEvPT_S1_j, @function
_Z7reduce4IiLj256EEvPT_S1_j:
.LFB7315:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce4IiLj256EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7315:
	.size	_Z7reduce4IiLj256EEvPT_S1_j, .-_Z7reduce4IiLj256EEvPT_S1_j
	.section	.text._Z7reduce4IiLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj128EEvPT_S1_j
	.type	_Z7reduce4IiLj128EEvPT_S1_j, @function
_Z7reduce4IiLj128EEvPT_S1_j:
.LFB7316:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce4IiLj128EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7316:
	.size	_Z7reduce4IiLj128EEvPT_S1_j, .-_Z7reduce4IiLj128EEvPT_S1_j
	.section	.text._Z7reduce4IiLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj64EEvPT_S1_j
	.type	_Z7reduce4IiLj64EEvPT_S1_j, @function
_Z7reduce4IiLj64EEvPT_S1_j:
.LFB7317:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce4IiLj64EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7317:
	.size	_Z7reduce4IiLj64EEvPT_S1_j, .-_Z7reduce4IiLj64EEvPT_S1_j
	.section	.text._Z7reduce4IiLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj32EEvPT_S1_j
	.type	_Z7reduce4IiLj32EEvPT_S1_j, @function
_Z7reduce4IiLj32EEvPT_S1_j:
.LFB7318:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce4IiLj32EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7318:
	.size	_Z7reduce4IiLj32EEvPT_S1_j, .-_Z7reduce4IiLj32EEvPT_S1_j
	.section	.text._Z7reduce4IiLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj16EEvPT_S1_j
	.type	_Z7reduce4IiLj16EEvPT_S1_j, @function
_Z7reduce4IiLj16EEvPT_S1_j:
.LFB7319:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce4IiLj16EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7319:
	.size	_Z7reduce4IiLj16EEvPT_S1_j, .-_Z7reduce4IiLj16EEvPT_S1_j
	.section	.text._Z7reduce4IiLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj8EEvPT_S1_j
	.type	_Z7reduce4IiLj8EEvPT_S1_j, @function
_Z7reduce4IiLj8EEvPT_S1_j:
.LFB7320:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IiLj8EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7320:
	.size	_Z7reduce4IiLj8EEvPT_S1_j, .-_Z7reduce4IiLj8EEvPT_S1_j
	.section	.text._Z7reduce4IiLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj4EEvPT_S1_j
	.type	_Z7reduce4IiLj4EEvPT_S1_j, @function
_Z7reduce4IiLj4EEvPT_S1_j:
.LFB7321:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IiLj4EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7321:
	.size	_Z7reduce4IiLj4EEvPT_S1_j, .-_Z7reduce4IiLj4EEvPT_S1_j
	.section	.text._Z7reduce4IiLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj2EEvPT_S1_j
	.type	_Z7reduce4IiLj2EEvPT_S1_j, @function
_Z7reduce4IiLj2EEvPT_S1_j:
.LFB7322:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IiLj2EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7322:
	.size	_Z7reduce4IiLj2EEvPT_S1_j, .-_Z7reduce4IiLj2EEvPT_S1_j
	.section	.text._Z7reduce4IiLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj1EEvPT_S1_j
	.type	_Z7reduce4IiLj1EEvPT_S1_j, @function
_Z7reduce4IiLj1EEvPT_S1_j:
.LFB7323:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IiLj1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7323:
	.size	_Z7reduce4IiLj1EEvPT_S1_j, .-_Z7reduce4IiLj1EEvPT_S1_j
	.section	.text._Z7reduce5IiLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj512EEvPT_S1_j
	.type	_Z7reduce5IiLj512EEvPT_S1_j, @function
_Z7reduce5IiLj512EEvPT_S1_j:
.LFB7324:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce5IiLj512EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7324:
	.size	_Z7reduce5IiLj512EEvPT_S1_j, .-_Z7reduce5IiLj512EEvPT_S1_j
	.section	.text._Z7reduce5IiLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj256EEvPT_S1_j
	.type	_Z7reduce5IiLj256EEvPT_S1_j, @function
_Z7reduce5IiLj256EEvPT_S1_j:
.LFB7325:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce5IiLj256EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7325:
	.size	_Z7reduce5IiLj256EEvPT_S1_j, .-_Z7reduce5IiLj256EEvPT_S1_j
	.section	.text._Z7reduce5IiLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj128EEvPT_S1_j
	.type	_Z7reduce5IiLj128EEvPT_S1_j, @function
_Z7reduce5IiLj128EEvPT_S1_j:
.LFB7326:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce5IiLj128EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7326:
	.size	_Z7reduce5IiLj128EEvPT_S1_j, .-_Z7reduce5IiLj128EEvPT_S1_j
	.section	.text._Z7reduce5IiLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj64EEvPT_S1_j
	.type	_Z7reduce5IiLj64EEvPT_S1_j, @function
_Z7reduce5IiLj64EEvPT_S1_j:
.LFB7327:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce5IiLj64EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7327:
	.size	_Z7reduce5IiLj64EEvPT_S1_j, .-_Z7reduce5IiLj64EEvPT_S1_j
	.section	.text._Z7reduce5IiLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj32EEvPT_S1_j
	.type	_Z7reduce5IiLj32EEvPT_S1_j, @function
_Z7reduce5IiLj32EEvPT_S1_j:
.LFB7328:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce5IiLj32EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7328:
	.size	_Z7reduce5IiLj32EEvPT_S1_j, .-_Z7reduce5IiLj32EEvPT_S1_j
	.section	.text._Z7reduce5IiLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj16EEvPT_S1_j
	.type	_Z7reduce5IiLj16EEvPT_S1_j, @function
_Z7reduce5IiLj16EEvPT_S1_j:
.LFB7329:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce5IiLj16EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7329:
	.size	_Z7reduce5IiLj16EEvPT_S1_j, .-_Z7reduce5IiLj16EEvPT_S1_j
	.section	.text._Z7reduce5IiLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj8EEvPT_S1_j
	.type	_Z7reduce5IiLj8EEvPT_S1_j, @function
_Z7reduce5IiLj8EEvPT_S1_j:
.LFB7330:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IiLj8EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7330:
	.size	_Z7reduce5IiLj8EEvPT_S1_j, .-_Z7reduce5IiLj8EEvPT_S1_j
	.section	.text._Z7reduce5IiLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj4EEvPT_S1_j
	.type	_Z7reduce5IiLj4EEvPT_S1_j, @function
_Z7reduce5IiLj4EEvPT_S1_j:
.LFB7331:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IiLj4EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7331:
	.size	_Z7reduce5IiLj4EEvPT_S1_j, .-_Z7reduce5IiLj4EEvPT_S1_j
	.section	.text._Z7reduce5IiLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj2EEvPT_S1_j
	.type	_Z7reduce5IiLj2EEvPT_S1_j, @function
_Z7reduce5IiLj2EEvPT_S1_j:
.LFB7332:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IiLj2EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7332:
	.size	_Z7reduce5IiLj2EEvPT_S1_j, .-_Z7reduce5IiLj2EEvPT_S1_j
	.section	.text._Z7reduce5IiLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj1EEvPT_S1_j
	.type	_Z7reduce5IiLj1EEvPT_S1_j, @function
_Z7reduce5IiLj1EEvPT_S1_j:
.LFB7333:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IiLj1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7333:
	.size	_Z7reduce5IiLj1EEvPT_S1_j, .-_Z7reduce5IiLj1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj512ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj512ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj512ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj512ELb1EEvPT_S1_j:
.LFB7334:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IiLj512ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7334:
	.size	_Z7reduce6IiLj512ELb1EEvPT_S1_j, .-_Z7reduce6IiLj512ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj256ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj256ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj256ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj256ELb1EEvPT_S1_j:
.LFB7335:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IiLj256ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7335:
	.size	_Z7reduce6IiLj256ELb1EEvPT_S1_j, .-_Z7reduce6IiLj256ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj128ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj128ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj128ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj128ELb1EEvPT_S1_j:
.LFB7336:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IiLj128ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7336:
	.size	_Z7reduce6IiLj128ELb1EEvPT_S1_j, .-_Z7reduce6IiLj128ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj64ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj64ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj64ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj64ELb1EEvPT_S1_j:
.LFB7337:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IiLj64ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7337:
	.size	_Z7reduce6IiLj64ELb1EEvPT_S1_j, .-_Z7reduce6IiLj64ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj32ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj32ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj32ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj32ELb1EEvPT_S1_j:
.LFB7338:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IiLj32ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7338:
	.size	_Z7reduce6IiLj32ELb1EEvPT_S1_j, .-_Z7reduce6IiLj32ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj16ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj16ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj16ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj16ELb1EEvPT_S1_j:
.LFB7339:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IiLj16ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7339:
	.size	_Z7reduce6IiLj16ELb1EEvPT_S1_j, .-_Z7reduce6IiLj16ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj8ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj8ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj8ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj8ELb1EEvPT_S1_j:
.LFB7340:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IiLj8ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7340:
	.size	_Z7reduce6IiLj8ELb1EEvPT_S1_j, .-_Z7reduce6IiLj8ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj4ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj4ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj4ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj4ELb1EEvPT_S1_j:
.LFB7341:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IiLj4ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7341:
	.size	_Z7reduce6IiLj4ELb1EEvPT_S1_j, .-_Z7reduce6IiLj4ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj2ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj2ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj2ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj2ELb1EEvPT_S1_j:
.LFB7342:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IiLj2ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7342:
	.size	_Z7reduce6IiLj2ELb1EEvPT_S1_j, .-_Z7reduce6IiLj2ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj1ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj1ELb1EEvPT_S1_j
	.type	_Z7reduce6IiLj1ELb1EEvPT_S1_j, @function
_Z7reduce6IiLj1ELb1EEvPT_S1_j:
.LFB7343:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IiLj1ELb1EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7343:
	.size	_Z7reduce6IiLj1ELb1EEvPT_S1_j, .-_Z7reduce6IiLj1ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IiLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj512ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj512ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj512ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj512ELb0EEvPT_S1_j:
.LFB7344:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IiLj512ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7344:
	.size	_Z7reduce6IiLj512ELb0EEvPT_S1_j, .-_Z7reduce6IiLj512ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IiLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj256ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj256ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj256ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj256ELb0EEvPT_S1_j:
.LFB7345:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IiLj256ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7345:
	.size	_Z7reduce6IiLj256ELb0EEvPT_S1_j, .-_Z7reduce6IiLj256ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IiLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj128ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj128ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj128ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj128ELb0EEvPT_S1_j:
.LFB7346:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IiLj128ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7346:
	.size	_Z7reduce6IiLj128ELb0EEvPT_S1_j, .-_Z7reduce6IiLj128ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IiLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj64ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj64ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj64ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj64ELb0EEvPT_S1_j:
.LFB7347:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IiLj64ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7347:
	.size	_Z7reduce6IiLj64ELb0EEvPT_S1_j, .-_Z7reduce6IiLj64ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IiLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj32ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj32ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj32ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj32ELb0EEvPT_S1_j:
.LFB7348:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IiLj32ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7348:
	.size	_Z7reduce6IiLj32ELb0EEvPT_S1_j, .-_Z7reduce6IiLj32ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IiLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj16ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj16ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj16ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj16ELb0EEvPT_S1_j:
.LFB7349:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IiLj16ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7349:
	.size	_Z7reduce6IiLj16ELb0EEvPT_S1_j, .-_Z7reduce6IiLj16ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IiLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj8ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj8ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj8ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj8ELb0EEvPT_S1_j:
.LFB7350:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IiLj8ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7350:
	.size	_Z7reduce6IiLj8ELb0EEvPT_S1_j, .-_Z7reduce6IiLj8ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IiLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj4ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj4ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj4ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj4ELb0EEvPT_S1_j:
.LFB7351:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IiLj4ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7351:
	.size	_Z7reduce6IiLj4ELb0EEvPT_S1_j, .-_Z7reduce6IiLj4ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IiLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj2ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj2ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj2ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj2ELb0EEvPT_S1_j:
.LFB7352:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IiLj2ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7352:
	.size	_Z7reduce6IiLj2ELb0EEvPT_S1_j, .-_Z7reduce6IiLj2ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IiLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj1ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj1ELb0EEvPT_S1_j
	.type	_Z7reduce6IiLj1ELb0EEvPT_S1_j, @function
_Z7reduce6IiLj1ELb0EEvPT_S1_j:
.LFB7353:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IiLj1ELb0EEvPT_S1_jPiS_j
	.cfi_endproc
.LFE7353:
	.size	_Z7reduce6IiLj1ELb0EEvPT_S1_j, .-_Z7reduce6IiLj1ELb0EEvPT_S1_j
	.section	.text._Z7reduce0IfEvPT_S1_j,"axG",@progbits,_Z7reduce0IfEvPT_S1_j,comdat
	.weak	_Z7reduce0IfEvPT_S1_j
	.type	_Z7reduce0IfEvPT_S1_j, @function
_Z7reduce0IfEvPT_S1_j:
.LFB7354:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce0IfEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7354:
	.size	_Z7reduce0IfEvPT_S1_j, .-_Z7reduce0IfEvPT_S1_j
	.section	.text._Z7reduce1IfEvPT_S1_j,"axG",@progbits,_Z7reduce1IfEvPT_S1_j,comdat
	.weak	_Z7reduce1IfEvPT_S1_j
	.type	_Z7reduce1IfEvPT_S1_j, @function
_Z7reduce1IfEvPT_S1_j:
.LFB7355:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce1IfEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7355:
	.size	_Z7reduce1IfEvPT_S1_j, .-_Z7reduce1IfEvPT_S1_j
	.section	.text._Z7reduce2IfEvPT_S1_j,"axG",@progbits,_Z7reduce2IfEvPT_S1_j,comdat
	.weak	_Z7reduce2IfEvPT_S1_j
	.type	_Z7reduce2IfEvPT_S1_j, @function
_Z7reduce2IfEvPT_S1_j:
.LFB7356:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce2IfEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7356:
	.size	_Z7reduce2IfEvPT_S1_j, .-_Z7reduce2IfEvPT_S1_j
	.section	.text._Z7reduce3IfEvPT_S1_j,"axG",@progbits,_Z7reduce3IfEvPT_S1_j,comdat
	.weak	_Z7reduce3IfEvPT_S1_j
	.type	_Z7reduce3IfEvPT_S1_j, @function
_Z7reduce3IfEvPT_S1_j:
.LFB7357:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce3IfEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7357:
	.size	_Z7reduce3IfEvPT_S1_j, .-_Z7reduce3IfEvPT_S1_j
	.section	.text._Z7reduce4IfLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj512EEvPT_S1_j
	.type	_Z7reduce4IfLj512EEvPT_S1_j, @function
_Z7reduce4IfLj512EEvPT_S1_j:
.LFB7358:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce4IfLj512EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7358:
	.size	_Z7reduce4IfLj512EEvPT_S1_j, .-_Z7reduce4IfLj512EEvPT_S1_j
	.section	.text._Z7reduce4IfLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj256EEvPT_S1_j
	.type	_Z7reduce4IfLj256EEvPT_S1_j, @function
_Z7reduce4IfLj256EEvPT_S1_j:
.LFB7359:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce4IfLj256EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7359:
	.size	_Z7reduce4IfLj256EEvPT_S1_j, .-_Z7reduce4IfLj256EEvPT_S1_j
	.section	.text._Z7reduce4IfLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj128EEvPT_S1_j
	.type	_Z7reduce4IfLj128EEvPT_S1_j, @function
_Z7reduce4IfLj128EEvPT_S1_j:
.LFB7360:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce4IfLj128EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7360:
	.size	_Z7reduce4IfLj128EEvPT_S1_j, .-_Z7reduce4IfLj128EEvPT_S1_j
	.section	.text._Z7reduce4IfLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj64EEvPT_S1_j
	.type	_Z7reduce4IfLj64EEvPT_S1_j, @function
_Z7reduce4IfLj64EEvPT_S1_j:
.LFB7361:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce4IfLj64EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7361:
	.size	_Z7reduce4IfLj64EEvPT_S1_j, .-_Z7reduce4IfLj64EEvPT_S1_j
	.section	.text._Z7reduce4IfLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj32EEvPT_S1_j
	.type	_Z7reduce4IfLj32EEvPT_S1_j, @function
_Z7reduce4IfLj32EEvPT_S1_j:
.LFB7362:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce4IfLj32EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7362:
	.size	_Z7reduce4IfLj32EEvPT_S1_j, .-_Z7reduce4IfLj32EEvPT_S1_j
	.section	.text._Z7reduce4IfLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj16EEvPT_S1_j
	.type	_Z7reduce4IfLj16EEvPT_S1_j, @function
_Z7reduce4IfLj16EEvPT_S1_j:
.LFB7363:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce4IfLj16EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7363:
	.size	_Z7reduce4IfLj16EEvPT_S1_j, .-_Z7reduce4IfLj16EEvPT_S1_j
	.section	.text._Z7reduce4IfLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj8EEvPT_S1_j
	.type	_Z7reduce4IfLj8EEvPT_S1_j, @function
_Z7reduce4IfLj8EEvPT_S1_j:
.LFB7364:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IfLj8EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7364:
	.size	_Z7reduce4IfLj8EEvPT_S1_j, .-_Z7reduce4IfLj8EEvPT_S1_j
	.section	.text._Z7reduce4IfLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj4EEvPT_S1_j
	.type	_Z7reduce4IfLj4EEvPT_S1_j, @function
_Z7reduce4IfLj4EEvPT_S1_j:
.LFB7365:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IfLj4EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7365:
	.size	_Z7reduce4IfLj4EEvPT_S1_j, .-_Z7reduce4IfLj4EEvPT_S1_j
	.section	.text._Z7reduce4IfLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj2EEvPT_S1_j
	.type	_Z7reduce4IfLj2EEvPT_S1_j, @function
_Z7reduce4IfLj2EEvPT_S1_j:
.LFB7366:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IfLj2EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7366:
	.size	_Z7reduce4IfLj2EEvPT_S1_j, .-_Z7reduce4IfLj2EEvPT_S1_j
	.section	.text._Z7reduce4IfLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj1EEvPT_S1_j
	.type	_Z7reduce4IfLj1EEvPT_S1_j, @function
_Z7reduce4IfLj1EEvPT_S1_j:
.LFB7367:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IfLj1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7367:
	.size	_Z7reduce4IfLj1EEvPT_S1_j, .-_Z7reduce4IfLj1EEvPT_S1_j
	.section	.text._Z7reduce5IfLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj512EEvPT_S1_j
	.type	_Z7reduce5IfLj512EEvPT_S1_j, @function
_Z7reduce5IfLj512EEvPT_S1_j:
.LFB7368:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce5IfLj512EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7368:
	.size	_Z7reduce5IfLj512EEvPT_S1_j, .-_Z7reduce5IfLj512EEvPT_S1_j
	.section	.text._Z7reduce5IfLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj256EEvPT_S1_j
	.type	_Z7reduce5IfLj256EEvPT_S1_j, @function
_Z7reduce5IfLj256EEvPT_S1_j:
.LFB7369:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce5IfLj256EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7369:
	.size	_Z7reduce5IfLj256EEvPT_S1_j, .-_Z7reduce5IfLj256EEvPT_S1_j
	.section	.text._Z7reduce5IfLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj128EEvPT_S1_j
	.type	_Z7reduce5IfLj128EEvPT_S1_j, @function
_Z7reduce5IfLj128EEvPT_S1_j:
.LFB7370:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce5IfLj128EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7370:
	.size	_Z7reduce5IfLj128EEvPT_S1_j, .-_Z7reduce5IfLj128EEvPT_S1_j
	.section	.text._Z7reduce5IfLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj64EEvPT_S1_j
	.type	_Z7reduce5IfLj64EEvPT_S1_j, @function
_Z7reduce5IfLj64EEvPT_S1_j:
.LFB7371:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce5IfLj64EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7371:
	.size	_Z7reduce5IfLj64EEvPT_S1_j, .-_Z7reduce5IfLj64EEvPT_S1_j
	.section	.text._Z7reduce5IfLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj32EEvPT_S1_j
	.type	_Z7reduce5IfLj32EEvPT_S1_j, @function
_Z7reduce5IfLj32EEvPT_S1_j:
.LFB7372:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce5IfLj32EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7372:
	.size	_Z7reduce5IfLj32EEvPT_S1_j, .-_Z7reduce5IfLj32EEvPT_S1_j
	.section	.text._Z7reduce5IfLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj16EEvPT_S1_j
	.type	_Z7reduce5IfLj16EEvPT_S1_j, @function
_Z7reduce5IfLj16EEvPT_S1_j:
.LFB7373:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce5IfLj16EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7373:
	.size	_Z7reduce5IfLj16EEvPT_S1_j, .-_Z7reduce5IfLj16EEvPT_S1_j
	.section	.text._Z7reduce5IfLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj8EEvPT_S1_j
	.type	_Z7reduce5IfLj8EEvPT_S1_j, @function
_Z7reduce5IfLj8EEvPT_S1_j:
.LFB7374:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IfLj8EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7374:
	.size	_Z7reduce5IfLj8EEvPT_S1_j, .-_Z7reduce5IfLj8EEvPT_S1_j
	.section	.text._Z7reduce5IfLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj4EEvPT_S1_j
	.type	_Z7reduce5IfLj4EEvPT_S1_j, @function
_Z7reduce5IfLj4EEvPT_S1_j:
.LFB7375:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IfLj4EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7375:
	.size	_Z7reduce5IfLj4EEvPT_S1_j, .-_Z7reduce5IfLj4EEvPT_S1_j
	.section	.text._Z7reduce5IfLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj2EEvPT_S1_j
	.type	_Z7reduce5IfLj2EEvPT_S1_j, @function
_Z7reduce5IfLj2EEvPT_S1_j:
.LFB7376:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IfLj2EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7376:
	.size	_Z7reduce5IfLj2EEvPT_S1_j, .-_Z7reduce5IfLj2EEvPT_S1_j
	.section	.text._Z7reduce5IfLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj1EEvPT_S1_j
	.type	_Z7reduce5IfLj1EEvPT_S1_j, @function
_Z7reduce5IfLj1EEvPT_S1_j:
.LFB7377:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IfLj1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7377:
	.size	_Z7reduce5IfLj1EEvPT_S1_j, .-_Z7reduce5IfLj1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj512ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj512ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj512ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj512ELb1EEvPT_S1_j:
.LFB7378:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IfLj512ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7378:
	.size	_Z7reduce6IfLj512ELb1EEvPT_S1_j, .-_Z7reduce6IfLj512ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj256ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj256ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj256ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj256ELb1EEvPT_S1_j:
.LFB7379:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IfLj256ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7379:
	.size	_Z7reduce6IfLj256ELb1EEvPT_S1_j, .-_Z7reduce6IfLj256ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj128ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj128ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj128ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj128ELb1EEvPT_S1_j:
.LFB7380:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IfLj128ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7380:
	.size	_Z7reduce6IfLj128ELb1EEvPT_S1_j, .-_Z7reduce6IfLj128ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj64ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj64ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj64ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj64ELb1EEvPT_S1_j:
.LFB7381:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IfLj64ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7381:
	.size	_Z7reduce6IfLj64ELb1EEvPT_S1_j, .-_Z7reduce6IfLj64ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj32ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj32ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj32ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj32ELb1EEvPT_S1_j:
.LFB7382:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IfLj32ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7382:
	.size	_Z7reduce6IfLj32ELb1EEvPT_S1_j, .-_Z7reduce6IfLj32ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj16ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj16ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj16ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj16ELb1EEvPT_S1_j:
.LFB7383:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IfLj16ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7383:
	.size	_Z7reduce6IfLj16ELb1EEvPT_S1_j, .-_Z7reduce6IfLj16ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj8ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj8ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj8ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj8ELb1EEvPT_S1_j:
.LFB7384:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IfLj8ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7384:
	.size	_Z7reduce6IfLj8ELb1EEvPT_S1_j, .-_Z7reduce6IfLj8ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj4ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj4ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj4ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj4ELb1EEvPT_S1_j:
.LFB7385:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IfLj4ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7385:
	.size	_Z7reduce6IfLj4ELb1EEvPT_S1_j, .-_Z7reduce6IfLj4ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj2ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj2ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj2ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj2ELb1EEvPT_S1_j:
.LFB7386:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IfLj2ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7386:
	.size	_Z7reduce6IfLj2ELb1EEvPT_S1_j, .-_Z7reduce6IfLj2ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj1ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj1ELb1EEvPT_S1_j
	.type	_Z7reduce6IfLj1ELb1EEvPT_S1_j, @function
_Z7reduce6IfLj1ELb1EEvPT_S1_j:
.LFB7387:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IfLj1ELb1EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7387:
	.size	_Z7reduce6IfLj1ELb1EEvPT_S1_j, .-_Z7reduce6IfLj1ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IfLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj512ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj512ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj512ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj512ELb0EEvPT_S1_j:
.LFB7388:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IfLj512ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7388:
	.size	_Z7reduce6IfLj512ELb0EEvPT_S1_j, .-_Z7reduce6IfLj512ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IfLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj256ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj256ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj256ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj256ELb0EEvPT_S1_j:
.LFB7389:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IfLj256ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7389:
	.size	_Z7reduce6IfLj256ELb0EEvPT_S1_j, .-_Z7reduce6IfLj256ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IfLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj128ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj128ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj128ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj128ELb0EEvPT_S1_j:
.LFB7390:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IfLj128ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7390:
	.size	_Z7reduce6IfLj128ELb0EEvPT_S1_j, .-_Z7reduce6IfLj128ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IfLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj64ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj64ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj64ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj64ELb0EEvPT_S1_j:
.LFB7391:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IfLj64ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7391:
	.size	_Z7reduce6IfLj64ELb0EEvPT_S1_j, .-_Z7reduce6IfLj64ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IfLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj32ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj32ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj32ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj32ELb0EEvPT_S1_j:
.LFB7392:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IfLj32ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7392:
	.size	_Z7reduce6IfLj32ELb0EEvPT_S1_j, .-_Z7reduce6IfLj32ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IfLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj16ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj16ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj16ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj16ELb0EEvPT_S1_j:
.LFB7393:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IfLj16ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7393:
	.size	_Z7reduce6IfLj16ELb0EEvPT_S1_j, .-_Z7reduce6IfLj16ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IfLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj8ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj8ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj8ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj8ELb0EEvPT_S1_j:
.LFB7394:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IfLj8ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7394:
	.size	_Z7reduce6IfLj8ELb0EEvPT_S1_j, .-_Z7reduce6IfLj8ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IfLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj4ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj4ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj4ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj4ELb0EEvPT_S1_j:
.LFB7395:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IfLj4ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7395:
	.size	_Z7reduce6IfLj4ELb0EEvPT_S1_j, .-_Z7reduce6IfLj4ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IfLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj2ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj2ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj2ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj2ELb0EEvPT_S1_j:
.LFB7396:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IfLj2ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7396:
	.size	_Z7reduce6IfLj2ELb0EEvPT_S1_j, .-_Z7reduce6IfLj2ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IfLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj1ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj1ELb0EEvPT_S1_j
	.type	_Z7reduce6IfLj1ELb0EEvPT_S1_j, @function
_Z7reduce6IfLj1ELb0EEvPT_S1_j:
.LFB7397:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IfLj1ELb0EEvPT_S1_jPfS_j
	.cfi_endproc
.LFE7397:
	.size	_Z7reduce6IfLj1ELb0EEvPT_S1_j, .-_Z7reduce6IfLj1ELb0EEvPT_S1_j
	.section	.text._Z7reduce0IdEvPT_S1_j,"axG",@progbits,_Z7reduce0IdEvPT_S1_j,comdat
	.weak	_Z7reduce0IdEvPT_S1_j
	.type	_Z7reduce0IdEvPT_S1_j, @function
_Z7reduce0IdEvPT_S1_j:
.LFB7398:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce0IdEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7398:
	.size	_Z7reduce0IdEvPT_S1_j, .-_Z7reduce0IdEvPT_S1_j
	.section	.text._Z7reduce1IdEvPT_S1_j,"axG",@progbits,_Z7reduce1IdEvPT_S1_j,comdat
	.weak	_Z7reduce1IdEvPT_S1_j
	.type	_Z7reduce1IdEvPT_S1_j, @function
_Z7reduce1IdEvPT_S1_j:
.LFB7399:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce1IdEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7399:
	.size	_Z7reduce1IdEvPT_S1_j, .-_Z7reduce1IdEvPT_S1_j
	.section	.text._Z7reduce2IdEvPT_S1_j,"axG",@progbits,_Z7reduce2IdEvPT_S1_j,comdat
	.weak	_Z7reduce2IdEvPT_S1_j
	.type	_Z7reduce2IdEvPT_S1_j, @function
_Z7reduce2IdEvPT_S1_j:
.LFB7400:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce2IdEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7400:
	.size	_Z7reduce2IdEvPT_S1_j, .-_Z7reduce2IdEvPT_S1_j
	.section	.text._Z7reduce3IdEvPT_S1_j,"axG",@progbits,_Z7reduce3IdEvPT_S1_j,comdat
	.weak	_Z7reduce3IdEvPT_S1_j
	.type	_Z7reduce3IdEvPT_S1_j, @function
_Z7reduce3IdEvPT_S1_j:
.LFB7401:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z7reduce3IdEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7401:
	.size	_Z7reduce3IdEvPT_S1_j, .-_Z7reduce3IdEvPT_S1_j
	.section	.text._Z7reduce4IdLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj512EEvPT_S1_j
	.type	_Z7reduce4IdLj512EEvPT_S1_j, @function
_Z7reduce4IdLj512EEvPT_S1_j:
.LFB7402:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce4IdLj512EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7402:
	.size	_Z7reduce4IdLj512EEvPT_S1_j, .-_Z7reduce4IdLj512EEvPT_S1_j
	.section	.text._Z7reduce4IdLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj256EEvPT_S1_j
	.type	_Z7reduce4IdLj256EEvPT_S1_j, @function
_Z7reduce4IdLj256EEvPT_S1_j:
.LFB7403:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce4IdLj256EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7403:
	.size	_Z7reduce4IdLj256EEvPT_S1_j, .-_Z7reduce4IdLj256EEvPT_S1_j
	.section	.text._Z7reduce4IdLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj128EEvPT_S1_j
	.type	_Z7reduce4IdLj128EEvPT_S1_j, @function
_Z7reduce4IdLj128EEvPT_S1_j:
.LFB7404:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce4IdLj128EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7404:
	.size	_Z7reduce4IdLj128EEvPT_S1_j, .-_Z7reduce4IdLj128EEvPT_S1_j
	.section	.text._Z7reduce4IdLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj64EEvPT_S1_j
	.type	_Z7reduce4IdLj64EEvPT_S1_j, @function
_Z7reduce4IdLj64EEvPT_S1_j:
.LFB7405:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce4IdLj64EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7405:
	.size	_Z7reduce4IdLj64EEvPT_S1_j, .-_Z7reduce4IdLj64EEvPT_S1_j
	.section	.text._Z7reduce4IdLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj32EEvPT_S1_j
	.type	_Z7reduce4IdLj32EEvPT_S1_j, @function
_Z7reduce4IdLj32EEvPT_S1_j:
.LFB7406:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce4IdLj32EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7406:
	.size	_Z7reduce4IdLj32EEvPT_S1_j, .-_Z7reduce4IdLj32EEvPT_S1_j
	.section	.text._Z7reduce4IdLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj16EEvPT_S1_j
	.type	_Z7reduce4IdLj16EEvPT_S1_j, @function
_Z7reduce4IdLj16EEvPT_S1_j:
.LFB7407:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce4IdLj16EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7407:
	.size	_Z7reduce4IdLj16EEvPT_S1_j, .-_Z7reduce4IdLj16EEvPT_S1_j
	.section	.text._Z7reduce4IdLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj8EEvPT_S1_j
	.type	_Z7reduce4IdLj8EEvPT_S1_j, @function
_Z7reduce4IdLj8EEvPT_S1_j:
.LFB7408:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IdLj8EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7408:
	.size	_Z7reduce4IdLj8EEvPT_S1_j, .-_Z7reduce4IdLj8EEvPT_S1_j
	.section	.text._Z7reduce4IdLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj4EEvPT_S1_j
	.type	_Z7reduce4IdLj4EEvPT_S1_j, @function
_Z7reduce4IdLj4EEvPT_S1_j:
.LFB7409:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IdLj4EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7409:
	.size	_Z7reduce4IdLj4EEvPT_S1_j, .-_Z7reduce4IdLj4EEvPT_S1_j
	.section	.text._Z7reduce4IdLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj2EEvPT_S1_j
	.type	_Z7reduce4IdLj2EEvPT_S1_j, @function
_Z7reduce4IdLj2EEvPT_S1_j:
.LFB7410:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IdLj2EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7410:
	.size	_Z7reduce4IdLj2EEvPT_S1_j, .-_Z7reduce4IdLj2EEvPT_S1_j
	.section	.text._Z7reduce4IdLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj1EEvPT_S1_j
	.type	_Z7reduce4IdLj1EEvPT_S1_j, @function
_Z7reduce4IdLj1EEvPT_S1_j:
.LFB7411:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce4IdLj1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7411:
	.size	_Z7reduce4IdLj1EEvPT_S1_j, .-_Z7reduce4IdLj1EEvPT_S1_j
	.section	.text._Z7reduce5IdLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj512EEvPT_S1_j
	.type	_Z7reduce5IdLj512EEvPT_S1_j, @function
_Z7reduce5IdLj512EEvPT_S1_j:
.LFB7412:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce5IdLj512EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7412:
	.size	_Z7reduce5IdLj512EEvPT_S1_j, .-_Z7reduce5IdLj512EEvPT_S1_j
	.section	.text._Z7reduce5IdLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj256EEvPT_S1_j
	.type	_Z7reduce5IdLj256EEvPT_S1_j, @function
_Z7reduce5IdLj256EEvPT_S1_j:
.LFB7413:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce5IdLj256EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7413:
	.size	_Z7reduce5IdLj256EEvPT_S1_j, .-_Z7reduce5IdLj256EEvPT_S1_j
	.section	.text._Z7reduce5IdLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj128EEvPT_S1_j
	.type	_Z7reduce5IdLj128EEvPT_S1_j, @function
_Z7reduce5IdLj128EEvPT_S1_j:
.LFB7414:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z7reduce5IdLj128EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7414:
	.size	_Z7reduce5IdLj128EEvPT_S1_j, .-_Z7reduce5IdLj128EEvPT_S1_j
	.section	.text._Z7reduce5IdLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj64EEvPT_S1_j
	.type	_Z7reduce5IdLj64EEvPT_S1_j, @function
_Z7reduce5IdLj64EEvPT_S1_j:
.LFB7415:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce5IdLj64EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7415:
	.size	_Z7reduce5IdLj64EEvPT_S1_j, .-_Z7reduce5IdLj64EEvPT_S1_j
	.section	.text._Z7reduce5IdLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj32EEvPT_S1_j
	.type	_Z7reduce5IdLj32EEvPT_S1_j, @function
_Z7reduce5IdLj32EEvPT_S1_j:
.LFB7416:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce5IdLj32EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7416:
	.size	_Z7reduce5IdLj32EEvPT_S1_j, .-_Z7reduce5IdLj32EEvPT_S1_j
	.section	.text._Z7reduce5IdLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj16EEvPT_S1_j
	.type	_Z7reduce5IdLj16EEvPT_S1_j, @function
_Z7reduce5IdLj16EEvPT_S1_j:
.LFB7417:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z7reduce5IdLj16EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7417:
	.size	_Z7reduce5IdLj16EEvPT_S1_j, .-_Z7reduce5IdLj16EEvPT_S1_j
	.section	.text._Z7reduce5IdLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj8EEvPT_S1_j
	.type	_Z7reduce5IdLj8EEvPT_S1_j, @function
_Z7reduce5IdLj8EEvPT_S1_j:
.LFB7418:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IdLj8EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7418:
	.size	_Z7reduce5IdLj8EEvPT_S1_j, .-_Z7reduce5IdLj8EEvPT_S1_j
	.section	.text._Z7reduce5IdLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj4EEvPT_S1_j
	.type	_Z7reduce5IdLj4EEvPT_S1_j, @function
_Z7reduce5IdLj4EEvPT_S1_j:
.LFB7419:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IdLj4EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7419:
	.size	_Z7reduce5IdLj4EEvPT_S1_j, .-_Z7reduce5IdLj4EEvPT_S1_j
	.section	.text._Z7reduce5IdLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj2EEvPT_S1_j
	.type	_Z7reduce5IdLj2EEvPT_S1_j, @function
_Z7reduce5IdLj2EEvPT_S1_j:
.LFB7420:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IdLj2EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7420:
	.size	_Z7reduce5IdLj2EEvPT_S1_j, .-_Z7reduce5IdLj2EEvPT_S1_j
	.section	.text._Z7reduce5IdLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj1EEvPT_S1_j
	.type	_Z7reduce5IdLj1EEvPT_S1_j, @function
_Z7reduce5IdLj1EEvPT_S1_j:
.LFB7421:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z7reduce5IdLj1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7421:
	.size	_Z7reduce5IdLj1EEvPT_S1_j, .-_Z7reduce5IdLj1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj512ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj512ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj512ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj512ELb1EEvPT_S1_j:
.LFB7422:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IdLj512ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7422:
	.size	_Z7reduce6IdLj512ELb1EEvPT_S1_j, .-_Z7reduce6IdLj512ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj256ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj256ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj256ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj256ELb1EEvPT_S1_j:
.LFB7423:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IdLj256ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7423:
	.size	_Z7reduce6IdLj256ELb1EEvPT_S1_j, .-_Z7reduce6IdLj256ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj128ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj128ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj128ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj128ELb1EEvPT_S1_j:
.LFB7424:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IdLj128ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7424:
	.size	_Z7reduce6IdLj128ELb1EEvPT_S1_j, .-_Z7reduce6IdLj128ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj64ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj64ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj64ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj64ELb1EEvPT_S1_j:
.LFB7425:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IdLj64ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7425:
	.size	_Z7reduce6IdLj64ELb1EEvPT_S1_j, .-_Z7reduce6IdLj64ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj32ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj32ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj32ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj32ELb1EEvPT_S1_j:
.LFB7426:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IdLj32ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7426:
	.size	_Z7reduce6IdLj32ELb1EEvPT_S1_j, .-_Z7reduce6IdLj32ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj16ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj16ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj16ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj16ELb1EEvPT_S1_j:
.LFB7427:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IdLj16ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7427:
	.size	_Z7reduce6IdLj16ELb1EEvPT_S1_j, .-_Z7reduce6IdLj16ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj8ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj8ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj8ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj8ELb1EEvPT_S1_j:
.LFB7428:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IdLj8ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7428:
	.size	_Z7reduce6IdLj8ELb1EEvPT_S1_j, .-_Z7reduce6IdLj8ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj4ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj4ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj4ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj4ELb1EEvPT_S1_j:
.LFB7429:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IdLj4ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7429:
	.size	_Z7reduce6IdLj4ELb1EEvPT_S1_j, .-_Z7reduce6IdLj4ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj2ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj2ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj2ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj2ELb1EEvPT_S1_j:
.LFB7430:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IdLj2ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7430:
	.size	_Z7reduce6IdLj2ELb1EEvPT_S1_j, .-_Z7reduce6IdLj2ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj1ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj1ELb1EEvPT_S1_j
	.type	_Z7reduce6IdLj1ELb1EEvPT_S1_j, @function
_Z7reduce6IdLj1ELb1EEvPT_S1_j:
.LFB7431:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IdLj1ELb1EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7431:
	.size	_Z7reduce6IdLj1ELb1EEvPT_S1_j, .-_Z7reduce6IdLj1ELb1EEvPT_S1_j
	.section	.text._Z7reduce6IdLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj512ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj512ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj512ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj512ELb0EEvPT_S1_j:
.LFB7432:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IdLj512ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7432:
	.size	_Z7reduce6IdLj512ELb0EEvPT_S1_j, .-_Z7reduce6IdLj512ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IdLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj256ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj256ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj256ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj256ELb0EEvPT_S1_j:
.LFB7433:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IdLj256ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7433:
	.size	_Z7reduce6IdLj256ELb0EEvPT_S1_j, .-_Z7reduce6IdLj256ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IdLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj128ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj128ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj128ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj128ELb0EEvPT_S1_j:
.LFB7434:
	.cfi_startproc
	endbr64
	jmp	_ZL45__device_stub__Z7reduce6IdLj128ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7434:
	.size	_Z7reduce6IdLj128ELb0EEvPT_S1_j, .-_Z7reduce6IdLj128ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IdLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj64ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj64ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj64ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj64ELb0EEvPT_S1_j:
.LFB7435:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IdLj64ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7435:
	.size	_Z7reduce6IdLj64ELb0EEvPT_S1_j, .-_Z7reduce6IdLj64ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IdLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj32ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj32ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj32ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj32ELb0EEvPT_S1_j:
.LFB7436:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IdLj32ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7436:
	.size	_Z7reduce6IdLj32ELb0EEvPT_S1_j, .-_Z7reduce6IdLj32ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IdLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj16ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj16ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj16ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj16ELb0EEvPT_S1_j:
.LFB7437:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z7reduce6IdLj16ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7437:
	.size	_Z7reduce6IdLj16ELb0EEvPT_S1_j, .-_Z7reduce6IdLj16ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IdLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj8ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj8ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj8ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj8ELb0EEvPT_S1_j:
.LFB7438:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IdLj8ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7438:
	.size	_Z7reduce6IdLj8ELb0EEvPT_S1_j, .-_Z7reduce6IdLj8ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IdLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj4ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj4ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj4ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj4ELb0EEvPT_S1_j:
.LFB7439:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IdLj4ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7439:
	.size	_Z7reduce6IdLj4ELb0EEvPT_S1_j, .-_Z7reduce6IdLj4ELb0EEvPT_S1_j
	.section	.text._Z7reduce6IdLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj2ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj2ELb0EEvPT_S1_j
	.type	_Z7reduce6IdLj2ELb0EEvPT_S1_j, @function
_Z7reduce6IdLj2ELb0EEvPT_S1_j:
.LFB7440:
	.cfi_startproc
	endbr64
	jmp	_ZL43__device_stub__Z7reduce6IdLj2ELb0EEvPT_S1_jPdS_j
	.cfi_endproc
.LFE7440:
	.size	_Z7reduce6IdLj2ELb0EEvPT_S1_j, .-_Z7reduce6IdLj2ELb0EEvPT_S1_j
	.section	.text._Z6reduceIiEviiiiPT_S1_,"axG",@progbits,_Z6reduceIiEviiiiPT_S1_,comdat
	.weak	_Z6reduceIiEviiiiPT_S1_
	.type	_Z6reduceIiEviiiiPT_S1_, @function
_Z6reduceIiEviiiiPT_S1_:
.LFB7306:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%r8, %rbp
	leal	0(,%rsi,8), %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edi, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movl	%esi, 24(%rsp)
	movq	%rax, 28(%rsp)
	movl	%edx, 36(%rsp)
	movq	%rax, 40(%rsp)
	cmpl	$32, %esi
	jle	.L666
	leal	0(,%rsi,4), %r8d
.L666:
	cmpl	$5, %ecx
	ja	.L667
	leaq	.L669(%rip), %rdx
	movl	%ecx, %ecx
	movslq	(%rdx,%rcx,4), %rax
	addq	%rdx, %rax
	notrack jmp	*%rax
	.section	.rodata._Z6reduceIiEviiiiPT_S1_,"aG",@progbits,_Z6reduceIiEviiiiPT_S1_,comdat
	.align 4
	.align 4
.L669:
	.long	.L674-.L669
	.long	.L673-.L669
	.long	.L672-.L669
	.long	.L671-.L669
	.long	.L670-.L669
	.long	.L668-.L669
	.section	.text._Z6reduceIiEviiiiPT_S1_,"axG",@progbits,_Z6reduceIiEviiiiPT_S1_,comdat
.L674:
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce0IiEvPT_S1_jPiS_j
.L673:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce1IiEvPT_S1_jPiS_j
.L672:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce2IiEvPT_S1_jPiS_j
.L671:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce3IiEvPT_S1_jPiS_j
.L670:
	.cfi_restore_state
	cmpl	$32, %r13d
	je	.L678
	jg	.L679
	cmpl	$4, %r13d
	je	.L680
	jg	.L681
	cmpl	$1, %r13d
	je	.L682
	cmpl	$2, %r13d
	je	.L683
	jmp	.L664
.L681:
	cmpl	$8, %r13d
	je	.L685
	cmpl	$16, %r13d
	je	.L686
	jmp	.L664
.L679:
	cmpl	$256, %r13d
	je	.L687
	jg	.L688
	cmpl	$64, %r13d
	je	.L689
	cmpl	$128, %r13d
	je	.L690
	jmp	.L664
.L688:
	cmpl	$512, %r13d
	jne	.L664
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce4IiLj512EEvPT_S1_jPiS_j
.L687:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce4IiLj256EEvPT_S1_jPiS_j
.L690:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce4IiLj128EEvPT_S1_jPiS_j
.L689:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce4IiLj64EEvPT_S1_jPiS_j
.L678:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce4IiLj32EEvPT_S1_jPiS_j
.L686:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce4IiLj16EEvPT_S1_jPiS_j
.L685:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IiLj8EEvPT_S1_jPiS_j
.L680:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IiLj4EEvPT_S1_jPiS_j
.L683:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IiLj2EEvPT_S1_jPiS_j
.L682:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IiLj1EEvPT_S1_jPiS_j
.L668:
	.cfi_restore_state
	cmpl	$32, %r13d
	je	.L692
	jg	.L693
	cmpl	$4, %r13d
	je	.L694
	jg	.L695
	cmpl	$1, %r13d
	je	.L696
	cmpl	$2, %r13d
	je	.L697
	jmp	.L664
.L695:
	cmpl	$8, %r13d
	je	.L698
	cmpl	$16, %r13d
	je	.L699
	jmp	.L664
.L693:
	cmpl	$256, %r13d
	je	.L700
	jg	.L701
	cmpl	$64, %r13d
	je	.L702
	cmpl	$128, %r13d
	je	.L703
	jmp	.L664
.L701:
	cmpl	$512, %r13d
	jne	.L664
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce5IiLj512EEvPT_S1_jPiS_j
.L700:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce5IiLj256EEvPT_S1_jPiS_j
.L703:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce5IiLj128EEvPT_S1_jPiS_j
.L702:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce5IiLj64EEvPT_S1_jPiS_j
.L692:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce5IiLj32EEvPT_S1_jPiS_j
.L699:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce5IiLj16EEvPT_S1_jPiS_j
.L698:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IiLj8EEvPT_S1_jPiS_j
.L694:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IiLj4EEvPT_S1_jPiS_j
.L697:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IiLj2EEvPT_S1_jPiS_j
.L696:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IiLj1EEvPT_S1_jPiS_j
.L667:
	.cfi_restore_state
	movl	%ebx, %edi
	movl	%r8d, 12(%rsp)
	call	isPow2@PLT
	movslq	12(%rsp), %r8
	testb	%al, %al
	je	.L704
	cmpl	$32, %r13d
	je	.L705
	jg	.L706
	cmpl	$4, %r13d
	je	.L707
	jg	.L708
	cmpl	$1, %r13d
	je	.L709
	cmpl	$2, %r13d
	je	.L710
	jmp	.L664
.L708:
	cmpl	$8, %r13d
	je	.L711
	cmpl	$16, %r13d
	je	.L712
	jmp	.L664
.L706:
	cmpl	$256, %r13d
	je	.L713
	jg	.L714
	cmpl	$64, %r13d
	je	.L715
	cmpl	$128, %r13d
	je	.L716
	jmp	.L664
.L714:
	cmpl	$512, %r13d
	jne	.L664
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IiLj512ELb1EEvPT_S1_jPiS_j
.L713:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IiLj256ELb1EEvPT_S1_jPiS_j
.L716:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IiLj128ELb1EEvPT_S1_jPiS_j
.L715:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IiLj64ELb1EEvPT_S1_jPiS_j
.L705:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IiLj32ELb1EEvPT_S1_jPiS_j
.L712:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IiLj16ELb1EEvPT_S1_jPiS_j
.L711:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IiLj8ELb1EEvPT_S1_jPiS_j
.L707:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IiLj4ELb1EEvPT_S1_jPiS_j
.L710:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IiLj2ELb1EEvPT_S1_jPiS_j
.L709:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IiLj1ELb1EEvPT_S1_jPiS_j
.L704:
	.cfi_restore_state
	cmpl	$32, %r13d
	je	.L717
	jg	.L718
	cmpl	$4, %r13d
	je	.L719
	jg	.L720
	cmpl	$1, %r13d
	je	.L721
	cmpl	$2, %r13d
	je	.L722
	jmp	.L664
.L720:
	cmpl	$8, %r13d
	je	.L723
	cmpl	$16, %r13d
	je	.L724
	jmp	.L664
.L718:
	cmpl	$256, %r13d
	je	.L725
	jg	.L726
	cmpl	$64, %r13d
	je	.L727
	cmpl	$128, %r13d
	je	.L728
	jmp	.L664
.L726:
	cmpl	$512, %r13d
	jne	.L664
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IiLj512ELb0EEvPT_S1_jPiS_j
.L725:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IiLj256ELb0EEvPT_S1_jPiS_j
.L728:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IiLj128ELb0EEvPT_S1_jPiS_j
.L727:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IiLj64ELb0EEvPT_S1_jPiS_j
.L717:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IiLj32ELb0EEvPT_S1_jPiS_j
.L724:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IiLj16ELb0EEvPT_S1_jPiS_j
.L723:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IiLj8ELb0EEvPT_S1_jPiS_j
.L719:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IiLj4ELb0EEvPT_S1_jPiS_j
.L722:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IiLj2ELb0EEvPT_S1_jPiS_j
.L721:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IiLj1ELb0EEvPT_S1_jPiS_j
.L664:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7306:
	.size	_Z6reduceIiEviiiiPT_S1_, .-_Z6reduceIiEviiiiPT_S1_
	.section	.text._Z6reduceIfEviiiiPT_S1_,"axG",@progbits,_Z6reduceIfEviiiiPT_S1_,comdat
	.weak	_Z6reduceIfEviiiiPT_S1_
	.type	_Z6reduceIfEviiiiPT_S1_, @function
_Z6reduceIfEviiiiPT_S1_:
.LFB7307:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%r8, %rbp
	leal	0(,%rsi,8), %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edi, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movl	%esi, 24(%rsp)
	movq	%rax, 28(%rsp)
	movl	%edx, 36(%rsp)
	movq	%rax, 40(%rsp)
	cmpl	$32, %esi
	jle	.L733
	leal	0(,%rsi,4), %r8d
.L733:
	cmpl	$5, %ecx
	ja	.L734
	leaq	.L736(%rip), %rdx
	movl	%ecx, %ecx
	movslq	(%rdx,%rcx,4), %rax
	addq	%rdx, %rax
	notrack jmp	*%rax
	.section	.rodata._Z6reduceIfEviiiiPT_S1_,"aG",@progbits,_Z6reduceIfEviiiiPT_S1_,comdat
	.align 4
	.align 4
.L736:
	.long	.L741-.L736
	.long	.L740-.L736
	.long	.L739-.L736
	.long	.L738-.L736
	.long	.L737-.L736
	.long	.L735-.L736
	.section	.text._Z6reduceIfEviiiiPT_S1_,"axG",@progbits,_Z6reduceIfEviiiiPT_S1_,comdat
.L741:
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce0IfEvPT_S1_jPfS_j
.L740:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce1IfEvPT_S1_jPfS_j
.L739:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce2IfEvPT_S1_jPfS_j
.L738:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce3IfEvPT_S1_jPfS_j
.L737:
	.cfi_restore_state
	cmpl	$32, %r13d
	je	.L745
	jg	.L746
	cmpl	$4, %r13d
	je	.L747
	jg	.L748
	cmpl	$1, %r13d
	je	.L749
	cmpl	$2, %r13d
	je	.L750
	jmp	.L731
.L748:
	cmpl	$8, %r13d
	je	.L752
	cmpl	$16, %r13d
	je	.L753
	jmp	.L731
.L746:
	cmpl	$256, %r13d
	je	.L754
	jg	.L755
	cmpl	$64, %r13d
	je	.L756
	cmpl	$128, %r13d
	je	.L757
	jmp	.L731
.L755:
	cmpl	$512, %r13d
	jne	.L731
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce4IfLj512EEvPT_S1_jPfS_j
.L754:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce4IfLj256EEvPT_S1_jPfS_j
.L757:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce4IfLj128EEvPT_S1_jPfS_j
.L756:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce4IfLj64EEvPT_S1_jPfS_j
.L745:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce4IfLj32EEvPT_S1_jPfS_j
.L753:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce4IfLj16EEvPT_S1_jPfS_j
.L752:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IfLj8EEvPT_S1_jPfS_j
.L747:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IfLj4EEvPT_S1_jPfS_j
.L750:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IfLj2EEvPT_S1_jPfS_j
.L749:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IfLj1EEvPT_S1_jPfS_j
.L735:
	.cfi_restore_state
	cmpl	$32, %r13d
	je	.L759
	jg	.L760
	cmpl	$4, %r13d
	je	.L761
	jg	.L762
	cmpl	$1, %r13d
	je	.L763
	cmpl	$2, %r13d
	je	.L764
	jmp	.L731
.L762:
	cmpl	$8, %r13d
	je	.L765
	cmpl	$16, %r13d
	je	.L766
	jmp	.L731
.L760:
	cmpl	$256, %r13d
	je	.L767
	jg	.L768
	cmpl	$64, %r13d
	je	.L769
	cmpl	$128, %r13d
	je	.L770
	jmp	.L731
.L768:
	cmpl	$512, %r13d
	jne	.L731
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce5IfLj512EEvPT_S1_jPfS_j
.L767:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce5IfLj256EEvPT_S1_jPfS_j
.L770:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce5IfLj128EEvPT_S1_jPfS_j
.L769:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce5IfLj64EEvPT_S1_jPfS_j
.L759:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce5IfLj32EEvPT_S1_jPfS_j
.L766:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce5IfLj16EEvPT_S1_jPfS_j
.L765:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IfLj8EEvPT_S1_jPfS_j
.L761:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IfLj4EEvPT_S1_jPfS_j
.L764:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IfLj2EEvPT_S1_jPfS_j
.L763:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IfLj1EEvPT_S1_jPfS_j
.L734:
	.cfi_restore_state
	movl	%ebx, %edi
	movl	%r8d, 12(%rsp)
	call	isPow2@PLT
	movslq	12(%rsp), %r8
	testb	%al, %al
	je	.L771
	cmpl	$32, %r13d
	je	.L772
	jg	.L773
	cmpl	$4, %r13d
	je	.L774
	jg	.L775
	cmpl	$1, %r13d
	je	.L776
	cmpl	$2, %r13d
	je	.L777
	jmp	.L731
.L775:
	cmpl	$8, %r13d
	je	.L778
	cmpl	$16, %r13d
	je	.L779
	jmp	.L731
.L773:
	cmpl	$256, %r13d
	je	.L780
	jg	.L781
	cmpl	$64, %r13d
	je	.L782
	cmpl	$128, %r13d
	je	.L783
	jmp	.L731
.L781:
	cmpl	$512, %r13d
	jne	.L731
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IfLj512ELb1EEvPT_S1_jPfS_j
.L780:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IfLj256ELb1EEvPT_S1_jPfS_j
.L783:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IfLj128ELb1EEvPT_S1_jPfS_j
.L782:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IfLj64ELb1EEvPT_S1_jPfS_j
.L772:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IfLj32ELb1EEvPT_S1_jPfS_j
.L779:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IfLj16ELb1EEvPT_S1_jPfS_j
.L778:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IfLj8ELb1EEvPT_S1_jPfS_j
.L774:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IfLj4ELb1EEvPT_S1_jPfS_j
.L777:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IfLj2ELb1EEvPT_S1_jPfS_j
.L776:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IfLj1ELb1EEvPT_S1_jPfS_j
.L771:
	.cfi_restore_state
	cmpl	$32, %r13d
	je	.L784
	jg	.L785
	cmpl	$4, %r13d
	je	.L786
	jg	.L787
	cmpl	$1, %r13d
	je	.L788
	cmpl	$2, %r13d
	je	.L789
	jmp	.L731
.L787:
	cmpl	$8, %r13d
	je	.L790
	cmpl	$16, %r13d
	je	.L791
	jmp	.L731
.L785:
	cmpl	$256, %r13d
	je	.L792
	jg	.L793
	cmpl	$64, %r13d
	je	.L794
	cmpl	$128, %r13d
	je	.L795
	jmp	.L731
.L793:
	cmpl	$512, %r13d
	jne	.L731
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IfLj512ELb0EEvPT_S1_jPfS_j
.L792:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IfLj256ELb0EEvPT_S1_jPfS_j
.L795:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IfLj128ELb0EEvPT_S1_jPfS_j
.L794:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IfLj64ELb0EEvPT_S1_jPfS_j
.L784:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IfLj32ELb0EEvPT_S1_jPfS_j
.L791:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IfLj16ELb0EEvPT_S1_jPfS_j
.L790:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IfLj8ELb0EEvPT_S1_jPfS_j
.L786:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IfLj4ELb0EEvPT_S1_jPfS_j
.L789:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IfLj2ELb0EEvPT_S1_jPfS_j
.L788:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L731
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IfLj1ELb0EEvPT_S1_jPfS_j
.L731:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7307:
	.size	_Z6reduceIfEviiiiPT_S1_, .-_Z6reduceIfEviiiiPT_S1_
	.section	.text._Z6reduceIdEviiiiPT_S1_,"axG",@progbits,_Z6reduceIdEviiiiPT_S1_,comdat
	.weak	_Z6reduceIdEviiiiPT_S1_
	.type	_Z6reduceIdEviiiiPT_S1_, @function
_Z6reduceIdEviiiiPT_S1_:
.LFB7308:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%r8, %rbp
	leal	0(,%rsi,8), %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edi, %ebx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movl	%esi, 24(%rsp)
	movq	%rax, 28(%rsp)
	movl	%edx, 36(%rsp)
	movq	%rax, 40(%rsp)
	cmpl	$32, %esi
	jg	.L800
	movl	%esi, %r8d
	sall	$4, %r8d
.L800:
	cmpl	$5, %ecx
	ja	.L801
	leaq	.L803(%rip), %rdx
	movl	%ecx, %ecx
	movslq	(%rdx,%rcx,4), %rax
	addq	%rdx, %rax
	notrack jmp	*%rax
	.section	.rodata._Z6reduceIdEviiiiPT_S1_,"aG",@progbits,_Z6reduceIdEviiiiPT_S1_,comdat
	.align 4
	.align 4
.L803:
	.long	.L808-.L803
	.long	.L807-.L803
	.long	.L806-.L803
	.long	.L805-.L803
	.long	.L804-.L803
	.long	.L802-.L803
	.section	.text._Z6reduceIdEviiiiPT_S1_,"axG",@progbits,_Z6reduceIdEviiiiPT_S1_,comdat
.L808:
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce0IdEvPT_S1_jPdS_j
.L807:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce1IdEvPT_S1_jPdS_j
.L806:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce2IdEvPT_S1_jPdS_j
.L805:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL35__device_stub__Z7reduce3IdEvPT_S1_jPdS_j
.L804:
	.cfi_restore_state
	cmpl	$32, %r13d
	je	.L812
	jg	.L813
	cmpl	$4, %r13d
	je	.L814
	jg	.L815
	cmpl	$1, %r13d
	je	.L816
	cmpl	$2, %r13d
	je	.L817
	jmp	.L798
.L815:
	cmpl	$8, %r13d
	je	.L819
	cmpl	$16, %r13d
	je	.L820
	jmp	.L798
.L813:
	cmpl	$256, %r13d
	je	.L821
	jg	.L822
	cmpl	$64, %r13d
	je	.L823
	cmpl	$128, %r13d
	je	.L824
	jmp	.L798
.L822:
	cmpl	$512, %r13d
	jne	.L798
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce4IdLj512EEvPT_S1_jPdS_j
.L821:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce4IdLj256EEvPT_S1_jPdS_j
.L824:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce4IdLj128EEvPT_S1_jPdS_j
.L823:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce4IdLj64EEvPT_S1_jPdS_j
.L812:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce4IdLj32EEvPT_S1_jPdS_j
.L820:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce4IdLj16EEvPT_S1_jPdS_j
.L819:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IdLj8EEvPT_S1_jPdS_j
.L814:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IdLj4EEvPT_S1_jPdS_j
.L817:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IdLj2EEvPT_S1_jPdS_j
.L816:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce4IdLj1EEvPT_S1_jPdS_j
.L802:
	.cfi_restore_state
	cmpl	$32, %r13d
	je	.L826
	jg	.L827
	cmpl	$4, %r13d
	je	.L828
	jg	.L829
	cmpl	$1, %r13d
	je	.L830
	cmpl	$2, %r13d
	je	.L831
	jmp	.L798
.L829:
	cmpl	$8, %r13d
	je	.L832
	cmpl	$16, %r13d
	je	.L833
	jmp	.L798
.L827:
	cmpl	$256, %r13d
	je	.L834
	jg	.L835
	cmpl	$64, %r13d
	je	.L836
	cmpl	$128, %r13d
	je	.L837
	jmp	.L798
.L835:
	cmpl	$512, %r13d
	jne	.L798
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce5IdLj512EEvPT_S1_jPdS_j
.L834:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce5IdLj256EEvPT_S1_jPdS_j
.L837:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z7reduce5IdLj128EEvPT_S1_jPdS_j
.L836:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce5IdLj64EEvPT_S1_jPdS_j
.L826:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce5IdLj32EEvPT_S1_jPdS_j
.L833:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__Z7reduce5IdLj16EEvPT_S1_jPdS_j
.L832:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IdLj8EEvPT_S1_jPdS_j
.L828:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IdLj4EEvPT_S1_jPdS_j
.L831:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IdLj2EEvPT_S1_jPdS_j
.L830:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movslq	%r8d, %r8
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__Z7reduce5IdLj1EEvPT_S1_jPdS_j
.L801:
	.cfi_restore_state
	movl	%ebx, %edi
	movl	%r8d, 12(%rsp)
	call	isPow2@PLT
	movslq	12(%rsp), %r8
	testb	%al, %al
	je	.L838
	cmpl	$32, %r13d
	je	.L839
	jg	.L840
	cmpl	$4, %r13d
	je	.L841
	jg	.L842
	cmpl	$1, %r13d
	je	.L843
	cmpl	$2, %r13d
	je	.L844
	jmp	.L798
.L842:
	cmpl	$8, %r13d
	je	.L845
	cmpl	$16, %r13d
	je	.L846
	jmp	.L798
.L840:
	cmpl	$256, %r13d
	je	.L847
	jg	.L848
	cmpl	$64, %r13d
	je	.L849
	cmpl	$128, %r13d
	je	.L850
	jmp	.L798
.L848:
	cmpl	$512, %r13d
	jne	.L798
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IdLj512ELb1EEvPT_S1_jPdS_j
.L847:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IdLj256ELb1EEvPT_S1_jPdS_j
.L850:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IdLj128ELb1EEvPT_S1_jPdS_j
.L849:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IdLj64ELb1EEvPT_S1_jPdS_j
.L839:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IdLj32ELb1EEvPT_S1_jPdS_j
.L846:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IdLj16ELb1EEvPT_S1_jPdS_j
.L845:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IdLj8ELb1EEvPT_S1_jPdS_j
.L841:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IdLj4ELb1EEvPT_S1_jPdS_j
.L844:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IdLj2ELb1EEvPT_S1_jPdS_j
.L843:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IdLj1ELb1EEvPT_S1_jPdS_j
.L838:
	.cfi_restore_state
	cmpl	$32, %r13d
	je	.L851
	jg	.L852
	cmpl	$4, %r13d
	je	.L853
	jg	.L854
	cmpl	$1, %r13d
	je	.L855
	cmpl	$2, %r13d
	je	.L856
	jmp	.L798
.L854:
	cmpl	$8, %r13d
	je	.L857
	cmpl	$16, %r13d
	je	.L858
	jmp	.L798
.L852:
	cmpl	$256, %r13d
	je	.L859
	jg	.L860
	cmpl	$64, %r13d
	je	.L861
	cmpl	$128, %r13d
	je	.L862
	jmp	.L798
.L860:
	cmpl	$512, %r13d
	jne	.L798
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IdLj512ELb0EEvPT_S1_jPdS_j
.L859:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IdLj256ELb0EEvPT_S1_jPdS_j
.L862:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL45__device_stub__Z7reduce6IdLj128ELb0EEvPT_S1_jPdS_j
.L861:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IdLj64ELb0EEvPT_S1_jPdS_j
.L851:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IdLj32ELb0EEvPT_S1_jPdS_j
.L858:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL44__device_stub__Z7reduce6IdLj16ELb0EEvPT_S1_jPdS_j
.L857:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IdLj8ELb0EEvPT_S1_jPdS_j
.L853:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IdLj4ELb0EEvPT_S1_jPdS_j
.L856:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IdLj2ELb0EEvPT_S1_jPdS_j
.L855:
	.cfi_restore_state
	movl	32(%rsp), %ecx
	movq	24(%rsp), %rdx
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdi
	movl	44(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L798
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %edx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__Z7reduce6IdLj1ELb0EEvPT_S1_jPdS_j
.L798:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE7308:
	.size	_Z6reduceIdEviiiiPT_S1_, .-_Z6reduceIdEviiiiPT_S1_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7reduce6IdLj1ELb0EEvPT_S1_j"
.LC1:
	.string	"_Z7reduce6IdLj2ELb0EEvPT_S1_j"
.LC2:
	.string	"_Z7reduce6IdLj4ELb0EEvPT_S1_j"
.LC3:
	.string	"_Z7reduce6IdLj8ELb0EEvPT_S1_j"
.LC4:
	.string	"_Z7reduce6IdLj16ELb0EEvPT_S1_j"
.LC5:
	.string	"_Z7reduce6IdLj32ELb0EEvPT_S1_j"
.LC6:
	.string	"_Z7reduce6IdLj64ELb0EEvPT_S1_j"
.LC7:
	.string	"_Z7reduce6IdLj128ELb0EEvPT_S1_j"
.LC8:
	.string	"_Z7reduce6IdLj256ELb0EEvPT_S1_j"
.LC9:
	.string	"_Z7reduce6IdLj512ELb0EEvPT_S1_j"
.LC10:
	.string	"_Z7reduce6IdLj1ELb1EEvPT_S1_j"
.LC11:
	.string	"_Z7reduce6IdLj2ELb1EEvPT_S1_j"
.LC12:
	.string	"_Z7reduce6IdLj4ELb1EEvPT_S1_j"
.LC13:
	.string	"_Z7reduce6IdLj8ELb1EEvPT_S1_j"
.LC14:
	.string	"_Z7reduce6IdLj16ELb1EEvPT_S1_j"
.LC15:
	.string	"_Z7reduce6IdLj32ELb1EEvPT_S1_j"
.LC16:
	.string	"_Z7reduce6IdLj64ELb1EEvPT_S1_j"
.LC17:
	.string	"_Z7reduce6IdLj128ELb1EEvPT_S1_j"
.LC18:
	.string	"_Z7reduce6IdLj256ELb1EEvPT_S1_j"
.LC19:
	.string	"_Z7reduce6IdLj512ELb1EEvPT_S1_j"
.LC20:
	.string	"_Z7reduce5IdLj1EEvPT_S1_j"
.LC21:
	.string	"_Z7reduce5IdLj2EEvPT_S1_j"
.LC22:
	.string	"_Z7reduce5IdLj4EEvPT_S1_j"
.LC23:
	.string	"_Z7reduce5IdLj8EEvPT_S1_j"
.LC24:
	.string	"_Z7reduce5IdLj16EEvPT_S1_j"
.LC25:
	.string	"_Z7reduce5IdLj32EEvPT_S1_j"
.LC26:
	.string	"_Z7reduce5IdLj64EEvPT_S1_j"
.LC27:
	.string	"_Z7reduce5IdLj128EEvPT_S1_j"
.LC28:
	.string	"_Z7reduce5IdLj256EEvPT_S1_j"
.LC29:
	.string	"_Z7reduce5IdLj512EEvPT_S1_j"
.LC30:
	.string	"_Z7reduce4IdLj1EEvPT_S1_j"
.LC31:
	.string	"_Z7reduce4IdLj2EEvPT_S1_j"
.LC32:
	.string	"_Z7reduce4IdLj4EEvPT_S1_j"
.LC33:
	.string	"_Z7reduce4IdLj8EEvPT_S1_j"
.LC34:
	.string	"_Z7reduce4IdLj16EEvPT_S1_j"
.LC35:
	.string	"_Z7reduce4IdLj32EEvPT_S1_j"
.LC36:
	.string	"_Z7reduce4IdLj64EEvPT_S1_j"
.LC37:
	.string	"_Z7reduce4IdLj128EEvPT_S1_j"
.LC38:
	.string	"_Z7reduce4IdLj256EEvPT_S1_j"
.LC39:
	.string	"_Z7reduce4IdLj512EEvPT_S1_j"
.LC40:
	.string	"_Z7reduce3IdEvPT_S1_j"
.LC41:
	.string	"_Z7reduce2IdEvPT_S1_j"
.LC42:
	.string	"_Z7reduce1IdEvPT_S1_j"
.LC43:
	.string	"_Z7reduce0IdEvPT_S1_j"
.LC44:
	.string	"_Z7reduce6IfLj1ELb0EEvPT_S1_j"
.LC45:
	.string	"_Z7reduce6IfLj2ELb0EEvPT_S1_j"
.LC46:
	.string	"_Z7reduce6IfLj4ELb0EEvPT_S1_j"
.LC47:
	.string	"_Z7reduce6IfLj8ELb0EEvPT_S1_j"
.LC48:
	.string	"_Z7reduce6IfLj16ELb0EEvPT_S1_j"
.LC49:
	.string	"_Z7reduce6IfLj32ELb0EEvPT_S1_j"
.LC50:
	.string	"_Z7reduce6IfLj64ELb0EEvPT_S1_j"
.LC51:
	.string	"_Z7reduce6IfLj128ELb0EEvPT_S1_j"
.LC52:
	.string	"_Z7reduce6IfLj256ELb0EEvPT_S1_j"
.LC53:
	.string	"_Z7reduce6IfLj512ELb0EEvPT_S1_j"
.LC54:
	.string	"_Z7reduce6IfLj1ELb1EEvPT_S1_j"
.LC55:
	.string	"_Z7reduce6IfLj2ELb1EEvPT_S1_j"
.LC56:
	.string	"_Z7reduce6IfLj4ELb1EEvPT_S1_j"
.LC57:
	.string	"_Z7reduce6IfLj8ELb1EEvPT_S1_j"
.LC58:
	.string	"_Z7reduce6IfLj16ELb1EEvPT_S1_j"
.LC59:
	.string	"_Z7reduce6IfLj32ELb1EEvPT_S1_j"
.LC60:
	.string	"_Z7reduce6IfLj64ELb1EEvPT_S1_j"
.LC61:
	.string	"_Z7reduce6IfLj128ELb1EEvPT_S1_j"
.LC62:
	.string	"_Z7reduce6IfLj256ELb1EEvPT_S1_j"
.LC63:
	.string	"_Z7reduce6IfLj512ELb1EEvPT_S1_j"
.LC64:
	.string	"_Z7reduce5IfLj1EEvPT_S1_j"
.LC65:
	.string	"_Z7reduce5IfLj2EEvPT_S1_j"
.LC66:
	.string	"_Z7reduce5IfLj4EEvPT_S1_j"
.LC67:
	.string	"_Z7reduce5IfLj8EEvPT_S1_j"
.LC68:
	.string	"_Z7reduce5IfLj16EEvPT_S1_j"
.LC69:
	.string	"_Z7reduce5IfLj32EEvPT_S1_j"
.LC70:
	.string	"_Z7reduce5IfLj64EEvPT_S1_j"
.LC71:
	.string	"_Z7reduce5IfLj128EEvPT_S1_j"
.LC72:
	.string	"_Z7reduce5IfLj256EEvPT_S1_j"
.LC73:
	.string	"_Z7reduce5IfLj512EEvPT_S1_j"
.LC74:
	.string	"_Z7reduce4IfLj1EEvPT_S1_j"
.LC75:
	.string	"_Z7reduce4IfLj2EEvPT_S1_j"
.LC76:
	.string	"_Z7reduce4IfLj4EEvPT_S1_j"
.LC77:
	.string	"_Z7reduce4IfLj8EEvPT_S1_j"
.LC78:
	.string	"_Z7reduce4IfLj16EEvPT_S1_j"
.LC79:
	.string	"_Z7reduce4IfLj32EEvPT_S1_j"
.LC80:
	.string	"_Z7reduce4IfLj64EEvPT_S1_j"
.LC81:
	.string	"_Z7reduce4IfLj128EEvPT_S1_j"
.LC82:
	.string	"_Z7reduce4IfLj256EEvPT_S1_j"
.LC83:
	.string	"_Z7reduce4IfLj512EEvPT_S1_j"
.LC84:
	.string	"_Z7reduce3IfEvPT_S1_j"
.LC85:
	.string	"_Z7reduce2IfEvPT_S1_j"
.LC86:
	.string	"_Z7reduce1IfEvPT_S1_j"
.LC87:
	.string	"_Z7reduce0IfEvPT_S1_j"
.LC88:
	.string	"_Z7reduce6IiLj1ELb0EEvPT_S1_j"
.LC89:
	.string	"_Z7reduce6IiLj2ELb0EEvPT_S1_j"
.LC90:
	.string	"_Z7reduce6IiLj4ELb0EEvPT_S1_j"
.LC91:
	.string	"_Z7reduce6IiLj8ELb0EEvPT_S1_j"
.LC92:
	.string	"_Z7reduce6IiLj16ELb0EEvPT_S1_j"
.LC93:
	.string	"_Z7reduce6IiLj32ELb0EEvPT_S1_j"
.LC94:
	.string	"_Z7reduce6IiLj64ELb0EEvPT_S1_j"
.LC95:
	.string	"_Z7reduce6IiLj128ELb0EEvPT_S1_j"
.LC96:
	.string	"_Z7reduce6IiLj256ELb0EEvPT_S1_j"
.LC97:
	.string	"_Z7reduce6IiLj512ELb0EEvPT_S1_j"
.LC98:
	.string	"_Z7reduce6IiLj1ELb1EEvPT_S1_j"
.LC99:
	.string	"_Z7reduce6IiLj2ELb1EEvPT_S1_j"
.LC100:
	.string	"_Z7reduce6IiLj4ELb1EEvPT_S1_j"
.LC101:
	.string	"_Z7reduce6IiLj8ELb1EEvPT_S1_j"
.LC102:
	.string	"_Z7reduce6IiLj16ELb1EEvPT_S1_j"
.LC103:
	.string	"_Z7reduce6IiLj32ELb1EEvPT_S1_j"
.LC104:
	.string	"_Z7reduce6IiLj64ELb1EEvPT_S1_j"
.LC105:
	.string	"_Z7reduce6IiLj128ELb1EEvPT_S1_j"
.LC106:
	.string	"_Z7reduce6IiLj256ELb1EEvPT_S1_j"
.LC107:
	.string	"_Z7reduce6IiLj512ELb1EEvPT_S1_j"
.LC108:
	.string	"_Z7reduce5IiLj1EEvPT_S1_j"
.LC109:
	.string	"_Z7reduce5IiLj2EEvPT_S1_j"
.LC110:
	.string	"_Z7reduce5IiLj4EEvPT_S1_j"
.LC111:
	.string	"_Z7reduce5IiLj8EEvPT_S1_j"
.LC112:
	.string	"_Z7reduce5IiLj16EEvPT_S1_j"
.LC113:
	.string	"_Z7reduce5IiLj32EEvPT_S1_j"
.LC114:
	.string	"_Z7reduce5IiLj64EEvPT_S1_j"
.LC115:
	.string	"_Z7reduce5IiLj128EEvPT_S1_j"
.LC116:
	.string	"_Z7reduce5IiLj256EEvPT_S1_j"
.LC117:
	.string	"_Z7reduce5IiLj512EEvPT_S1_j"
.LC118:
	.string	"_Z7reduce4IiLj1EEvPT_S1_j"
.LC119:
	.string	"_Z7reduce4IiLj2EEvPT_S1_j"
.LC120:
	.string	"_Z7reduce4IiLj4EEvPT_S1_j"
.LC121:
	.string	"_Z7reduce4IiLj8EEvPT_S1_j"
.LC122:
	.string	"_Z7reduce4IiLj16EEvPT_S1_j"
.LC123:
	.string	"_Z7reduce4IiLj32EEvPT_S1_j"
.LC124:
	.string	"_Z7reduce4IiLj64EEvPT_S1_j"
.LC125:
	.string	"_Z7reduce4IiLj128EEvPT_S1_j"
.LC126:
	.string	"_Z7reduce4IiLj256EEvPT_S1_j"
.LC127:
	.string	"_Z7reduce4IiLj512EEvPT_S1_j"
.LC128:
	.string	"_Z7reduce3IiEvPT_S1_j"
.LC129:
	.string	"_Z7reduce2IiEvPT_S1_j"
.LC130:
	.string	"_Z7reduce1IiEvPT_S1_j"
.LC131:
	.string	"_Z7reduce0IiEvPT_S1_j"
.LC132:
	.string	"_ZN58_INTERNAL_8a803066_19_reduction_kernel_cu_ea23c857_38610714cuda3std3__419piecewise_constructE"
.LC133:
	.string	"_ZN58_INTERNAL_8a803066_19_reduction_kernel_cu_ea23c857_38610714cuda3std6ranges3__45__cpo4swapE"
.LC134:
	.string	"_ZN58_INTERNAL_8a803066_19_reduction_kernel_cu_ea23c857_38610714cuda3std6ranges3__45__cpo9iter_moveE"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6867:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7reduce6IdLj1ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj2ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj4ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj8ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj16ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj32ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj64ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj128ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce6IdLj256ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj512ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj1ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj2ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj4ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj8ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj16ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj32ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC16(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce6IdLj64ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj128ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj256ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IdLj512ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IdLj1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IdLj2EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IdLj4EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IdLj8EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC24(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce5IdLj16EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IdLj32EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IdLj64EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC27(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IdLj128EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC28(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IdLj256EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC29(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IdLj512EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC30(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IdLj1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC31(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IdLj2EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC32(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce4IdLj4EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC33(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IdLj8EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC34(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IdLj16EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC35(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IdLj32EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC36(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IdLj64EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC37(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IdLj128EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC38(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IdLj256EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC39(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IdLj512EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC40(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce3IdEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC41(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce2IdEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC42(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce1IdEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC43(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce0IdEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC44(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj1ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC45(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj2ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC46(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj4ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC47(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj8ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC48(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce6IfLj16ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC49(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj32ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC50(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj64ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC51(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj128ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC52(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj256ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC53(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj512ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC54(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj1ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC55(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj2ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC56(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce6IfLj4ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC57(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj8ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC58(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj16ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC59(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj32ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC60(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj64ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC61(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj128ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC62(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj256ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC63(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IfLj512ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC64(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce5IfLj1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC65(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IfLj2EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC66(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IfLj4EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC67(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IfLj8EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC68(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IfLj16EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC69(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IfLj32EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC70(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IfLj64EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC71(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IfLj128EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC72(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce5IfLj256EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC73(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IfLj512EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC74(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IfLj1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC75(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IfLj2EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC76(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IfLj4EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC77(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IfLj8EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC78(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IfLj16EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC79(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IfLj32EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC80(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce4IfLj64EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC81(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IfLj128EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC82(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IfLj256EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC83(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IfLj512EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC84(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce3IfEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC85(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce2IfEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC86(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce1IfEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC87(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce0IfEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC88(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce6IiLj1ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC89(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj2ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC90(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj4ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC91(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj8ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC92(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj16ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC93(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj32ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC94(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj64ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC95(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj128ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC96(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce6IiLj256ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC97(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj512ELb0EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC98(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj1ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC99(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj2ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC100(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj4ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC101(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj8ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC102(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj16ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC103(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj32ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC104(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce6IiLj64ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC105(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj128ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC106(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj256ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC107(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce6IiLj512ELb1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC108(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IiLj1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC109(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IiLj2EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC110(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IiLj4EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC111(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IiLj8EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC112(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce5IiLj16EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC113(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IiLj32EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC114(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IiLj64EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC115(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IiLj128EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC116(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IiLj256EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC117(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce5IiLj512EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC118(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IiLj1EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC119(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IiLj2EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC120(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce4IiLj4EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC121(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IiLj8EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC122(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IiLj16EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC123(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IiLj32EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC124(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IiLj64EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC125(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IiLj128EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC126(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IiLj256EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC127(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7reduce4IiLj512EEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC128(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce3IiEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC129(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7reduce2IiEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC130(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7reduce1IiEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC131(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7reduce0IiEvPT_S1_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC132(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC133(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC134(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE6867:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  * Neither the name of NVIDIA CORPORATION nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
    Parallel reduction kernels
*/

#ifndef _REDUCE_KERNEL_H_
#define _REDUCE_KERNEL_H_

#include <hip/hip_cooperative_groups.h>
#include <stdio.h>

namespace cg = cooperative_groups;

// Utility class used to avoid linker errors with extern
// unsized shared memory arrays with templated type
template <class T>
struct SharedMemory {
  __device__ inline operator T *() {
    extern __shared__ int __smem[];
    return (T *)__smem;
  }

  __device__ inline operator const T *() const {
    extern __shared__ int __smem[];
    return (T *)__smem;
  }
};

// specialize for double to avoid unaligned memory
// access compile errors
template <>
struct SharedMemory<double> {
  __device__ inline operator double *() {
    extern __shared__ double __smem_d[];
    return (double *)__smem_d;
  }

  __device__ inline operator const double *() const {
    extern __shared__ double __smem_d[];
    return (double *)__smem_d;
  }
};

/*
    Parallel sum reduction using shared memory
    - takes log(n) steps for n input elements
    - uses n threads
    - only works for power-of-2 arrays
*/

/* This reduction interleaves which threads are active by using the modulo
   operator.  This operator is very expensive on GPUs, and the interleaved
   inactivity means that no whole warps are active, which is also very
   inefficient */
template <class T>
__global__ void reduce0(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // load shared mem
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;

  sdata[tid] = (i < n) ? g_idata[i] : 0;

  cg::sync(cta);

  // do reduction in shared mem
  for (unsigned int s = 1; s < blockDim.x; s *= 2) {
    // modulo arithmetic is slow!
    if ((tid % (2 * s)) == 0) {
      sdata[tid] += sdata[tid + s];
    }

    cg::sync(cta);
  }

  // write result for this block to global mem
  if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}

/* This version uses contiguous threads, but its interleaved
   addressing results in many shared memory bank conflicts.
*/
template <class T>
__global__ void reduce1(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // load shared mem
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;

  sdata[tid] = (i < n) ? g_idata[i] : 0;

  cg::sync(cta);

  // do reduction in shared mem
  for (unsigned int s = 1; s < blockDim.x; s *= 2) {
    int index = 2 * s * tid;

    if (index < blockDim.x) {
      sdata[index] += sdata[index + s];
    }

    cg::sync(cta);
  }

  // write result for this block to global mem
  if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}

/*
    This version uses sequential addressing -- no divergence or bank conflicts.
*/
template <class T>
__global__ void reduce2(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // load shared mem
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;

  sdata[tid] = (i < n) ? g_idata[i] : 0;

  cg::sync(cta);

  // do reduction in shared mem
  for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
    if (tid < s) {
      sdata[tid] += sdata[tid + s];
    }

    cg::sync(cta);
  }

  // write result for this block to global mem
  if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}

/*
    This version uses n/2 threads --
    it performs the first level of reduction when reading from global memory.
*/
template <class T>
__global__ void reduce3(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();

  // perform first level of reduction,
  // reading from global memory, writing to shared memory
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;

  T mySum = (i < n) ? g_idata[i] : 0;

  if (i + blockDim.x < n) mySum += g_idata[i + blockDim.x];

  g_odata[i] = mySum;
  cg::sync(cta);

  // do reduction in global mem
  for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
    if (tid < s) {
      g_odata[i] = mySum = mySum + g_odata[i + s];
    }
    cg::sync(cta);
  }

  // write result for this block to global mem
  if (tid == 0) g_odata[blockIdx.x] = mySum;
}

/*
    This version uses the warp shuffle operation if available to reduce
    warp synchronization. When shuffle is not available the final warp's
    worth of work is unrolled to reduce looping overhead.

    See
   http://devblogs.nvidia.com/parallelforall/faster-parallel-reductions-kepler/
    for additional information about using shuffle to perform a reduction
    within a warp.

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T, unsigned int blockSize>
__global__ void reduce4(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // perform first level of reduction,
  // reading from global memory, writing to shared memory
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;

  T mySum = (i < n) ? g_idata[i] : 0;

  if (i + blockSize < n) mySum += g_idata[i + blockSize];

  sdata[tid] = mySum;
  cg::sync(cta);

  // do reduction in shared mem
  for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
    if (tid < s) {
      sdata[tid] = mySum = mySum + sdata[tid + s];
    }

    cg::sync(cta);
  }

  cg::thread_block_tile<32> tile32 = cg::tiled_partition<32>(cta);

  if (cta.thread_rank() < 32) {
    // Fetch final intermediate sum from 2nd warp
    if (blockSize >= 64) mySum += sdata[tid + 32];
    // Reduce final warp using shuffle
    for (int offset = tile32.size() / 2; offset > 0; offset /= 2) {
      mySum += tile32.shfl_down(mySum, offset);
    }
  }

  // write result for this block to global mem
  if (cta.thread_rank() == 0) g_odata[blockIdx.x] = mySum;
}

/*
    This version is completely unrolled, unless warp shuffle is available, then
    shuffle is used within a loop.  It uses a template parameter to achieve
    optimal code for any (power of 2) number of threads.  This requires a switch
    statement in the host code to handle all the different thread block sizes at
    compile time. When shuffle is available, it is used to reduce warp
   synchronization.

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T, unsigned int blockSize>
__global__ void reduce5(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // perform first level of reduction,
  // reading from global memory, writing to shared memory
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * (blockSize * 2) + threadIdx.x;

  T mySum = (i < n) ? g_idata[i] : 0;

  if (i + blockSize < n) mySum += g_idata[i + blockSize];

  sdata[tid] = mySum;
  cg::sync(cta);

  // do reduction in shared mem
  if ((blockSize >= 512) && (tid < 256)) {
    sdata[tid] = mySum = mySum + sdata[tid + 256];
  }

  cg::sync(cta);

  if ((blockSize >= 256) && (tid < 128)) {
    sdata[tid] = mySum = mySum + sdata[tid + 128];
  }

  cg::sync(cta);

  if ((blockSize >= 128) && (tid < 64)) {
    sdata[tid] = mySum = mySum + sdata[tid + 64];
  }

  cg::sync(cta);

  cg::thread_block_tile<32> tile32 = cg::tiled_partition<32>(cta);

  if (cta.thread_rank() < 32) {
    // Fetch final intermediate sum from 2nd warp
    if (blockSize >= 64) mySum += sdata[tid + 32];
    // Reduce final warp using shuffle
    for (int offset = tile32.size() / 2; offset > 0; offset /= 2) {
      mySum += tile32.shfl_down(mySum, offset);
    }
  }

  // write result for this block to global mem
  if (cta.thread_rank() == 0) g_odata[blockIdx.x] = mySum;
}

/*
    This version adds multiple elements per thread sequentially.  This reduces
   the overall cost of the algorithm while keeping the work complexity O(n) and
   the step complexity O(log n). (Brent's Theorem optimization)

    Note, this kernel needs a minimum of 64*sizeof(T) bytes of shared memory.
    In other words if blockSize <= 32, allocate 64*sizeof(T) bytes.
    If blockSize > 32, allocate blockSize*sizeof(T) bytes.
*/
template <class T, unsigned int blockSize, bool nIsPow2>
__global__ void reduce6(T *g_idata, T *g_odata, unsigned int n) {
  // Handle to thread block group
  cg::thread_block cta = cg::this_thread_block();
  T *sdata = SharedMemory<T>();

  // perform first level of reduction,
  // reading from global memory, writing to shared memory
  unsigned int tid = threadIdx.x;
  unsigned int i = blockIdx.x * blockSize * 2 + threadIdx.x;
  unsigned int gridSize = blockSize * 2 * gridDim.x;

  T mySum = 0;

  // we reduce multiple elements per thread.  The number is determined by the
  // number of active thread blocks (via gridDim).  More blocks will result
  // in a larger gridSize and therefore fewer elements per thread
  while (i < n) {
    mySum += g_idata[i];

    // ensure we don't read out of bounds -- this is optimized away for powerOf2
    // sized arrays
    if (nIsPow2 || i + blockSize < n) mySum += g_idata[i + blockSize];

    i += gridSize;
  }

  // each thread puts its local sum into shared memory
  sdata[tid] = mySum;
  cg::sync(cta);

  // do reduction in shared mem
  if ((blockSize >= 512) && (tid < 256)) {
    sdata[tid] = mySum = mySum + sdata[tid + 256];
  }

  cg::sync(cta);

  if ((blockSize >= 256) && (tid < 128)) {
    sdata[tid] = mySum = mySum + sdata[tid + 128];
  }

  cg::sync(cta);

  if ((blockSize >= 128) && (tid < 64)) {
    sdata[tid] = mySum = mySum + sdata[tid + 64];
  }

  cg::sync(cta);

  cg::thread_block_tile<32> tile32 = cg::tiled_partition<32>(cta);

  if (cta.thread_rank() < 32) {
    // Fetch final intermediate sum from 2nd warp
    if (blockSize >= 64) mySum += sdata[tid + 32];
    // Reduce final warp using shuffle
    for (int offset = tile32.size() / 2; offset > 0; offset /= 2) {
      mySum += tile32.shfl_down(mySum, offset);
    }
  }

  // write result for this block to global mem
  if (cta.thread_rank() == 0) g_odata[blockIdx.x] = mySum;
}

extern "C" bool isPow2(unsigned int x);

////////////////////////////////////////////////////////////////////////////////
// Wrapper function for kernel launch
////////////////////////////////////////////////////////////////////////////////
template <class T>
void reduce(int size, int threads, int blocks, int whichKernel, T *d_idata,
            T *d_odata) {
  dim3 dimBlock(threads, 1, 1);
  dim3 dimGrid(blocks, 1, 1);

  // when there is only one warp per block, we need to allocate two warps
  // worth of shared memory so that we don't index shared memory out of bounds
  int smemSize =
      (threads <= 32) ? 2 * threads * sizeof(T) : threads * sizeof(T);

  // choose which of the optimized versions of reduction to launch
  switch (whichKernel) {
    case 0:
      reduce0<T><<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
      break;

    case 1:
      reduce1<T><<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
      break;

    case 2:
      reduce2<T><<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
      break;

    case 3:
      reduce3<T><<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
      break;

    case 4:
      switch (threads) {
        case 512:
          reduce4<T, 512>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 256:
          reduce4<T, 256>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 128:
          reduce4<T, 128>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 64:
          reduce4<T, 64>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 32:
          reduce4<T, 32>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 16:
          reduce4<T, 16>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 8:
          reduce4<T, 8>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 4:
          reduce4<T, 4>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 2:
          reduce4<T, 2>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 1:
          reduce4<T, 1>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;
      }

      break;

    case 5:
      switch (threads) {
        case 512:
          reduce5<T, 512>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 256:
          reduce5<T, 256>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 128:
          reduce5<T, 128>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 64:
          reduce5<T, 64>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 32:
          reduce5<T, 32>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 16:
          reduce5<T, 16>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 8:
          reduce5<T, 8>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 4:
          reduce5<T, 4>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 2:
          reduce5<T, 2>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;

        case 1:
          reduce5<T, 1>
              <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
          break;
      }

      break;

    case 6:
    default:
      if (isPow2(size)) {
        switch (threads) {
          case 512:
            reduce6<T, 512, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 256:
            reduce6<T, 256, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 128:
            reduce6<T, 128, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 64:
            reduce6<T, 64, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 32:
            reduce6<T, 32, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 16:
            reduce6<T, 16, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 8:
            reduce6<T, 8, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 4:
            reduce6<T, 4, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 2:
            reduce6<T, 2, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 1:
            reduce6<T, 1, true>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;
        }
      } else {
        switch (threads) {
          case 512:
            reduce6<T, 512, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 256:
            reduce6<T, 256, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 128:
            reduce6<T, 128, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 64:
            reduce6<T, 64, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 32:
            reduce6<T, 32, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 16:
            reduce6<T, 16, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 8:
            reduce6<T, 8, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 4:
            reduce6<T, 4, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 2:
            reduce6<T, 2, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;

          case 1:
            reduce6<T, 1, false>
                <<<dimGrid, dimBlock, smemSize>>>(d_idata, d_odata, size);
            break;
        }
      }

      break;
  }
}

// Instantiate the reduction function for 3 types
template void reduce<int>(int size, int threads, int blocks, int whichKernel,
                          int *d_idata, int *d_odata);

template void reduce<float>(int size, int threads, int blocks, int whichKernel,
                            float *d_idata, float *d_odata);

template void reduce<double>(int size, int threads, int blocks, int whichKernel,
                             double *d_idata, double *d_odata);

#endif  // #ifndef _REDUCE_KERNEL_H_

	.text
	.file	"reduction_kernel.hip"
	.section	.text._Z6reduceIiEviiiiPT_S1_,"axG",@progbits,_Z6reduceIiEviiiiPT_S1_,comdat
	.weak	_Z6reduceIiEviiiiPT_S1_         # -- Begin function _Z6reduceIiEviiiiPT_S1_
	.type	_Z6reduceIiEviiiiPT_S1_,@function
_Z6reduceIiEviiiiPT_S1_:                # @_Z6reduceIiEviiiiPT_S1_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %eax
	movl	%esi, %ebp
	movl	%esi, %r12d
	btsq	$32, %r12
	movl	%edx, %r13d
	btsq	$32, %r13
	cmpl	$33, %esi
	setl	%cl
	movl	%esi, %r14d
	shll	%cl, %r14d
	movq	%r8, %r15
	movl	%edi, %ebx
	shll	$2, %r14d
	cmpl	$5, %eax
	ja	.LBB0_70
# %bb.1:
	movl	%eax, %eax
	jmpq	*.LJTI0_0(,%rax,8)
.LBB0_2:
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.3:
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce0IiEvPT_S1_j # TAILCALL
.LBB0_10:
	.cfi_def_cfa_offset 64
	cmpl	$31, %ebp
	movq	%r9, (%rsp)                     # 8-byte Spill
	jg	.LBB0_16
# %bb.11:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB0_12
# %bb.15:
	jmpq	*.LJTI0_2(,%rax,8)
.LBB0_38:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.39:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj1EEvPT_S1_j # TAILCALL
.LBB0_6:
	.cfi_def_cfa_offset 64
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.7:
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce2IiEvPT_S1_j # TAILCALL
.LBB0_8:
	.cfi_def_cfa_offset 64
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.9:
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce3IiEvPT_S1_j # TAILCALL
.LBB0_4:
	.cfi_def_cfa_offset 64
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB0_5
.LBB0_130:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_40:
	.cfi_def_cfa_offset 64
	cmpl	$31, %ebp
	movq	%r9, (%rsp)                     # 8-byte Spill
	jg	.LBB0_46
# %bb.41:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB0_42
# %bb.45:
	jmpq	*.LJTI0_1(,%rax,8)
.LBB0_68:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.69:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj1EEvPT_S1_j # TAILCALL
.LBB0_70:
	.cfi_def_cfa_offset 64
	movq	%r9, (%rsp)                     # 8-byte Spill
	movl	%ebx, %edi
	callq	isPow2
	testb	%al, %al
	je	.LBB0_101
# %bb.71:
	cmpl	$31, %ebp
	jg	.LBB0_77
# %bb.72:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB0_73
# %bb.76:
	jmpq	*.LJTI0_4(,%rax,8)
.LBB0_99:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.100:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j # TAILCALL
.LBB0_16:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB0_17
# %bb.21:
	cmpl	$128, %ebp
	je	.LBB0_28
# %bb.22:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB0_26
# %bb.23:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB0_130
# %bb.24:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.25:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj512EEvPT_S1_j # TAILCALL
.LBB0_46:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB0_47
# %bb.51:
	cmpl	$128, %ebp
	je	.LBB0_58
# %bb.52:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB0_56
# %bb.53:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB0_130
# %bb.54:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.55:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj512EEvPT_S1_j # TAILCALL
.LBB0_101:
	.cfi_def_cfa_offset 64
	cmpl	$31, %ebp
	jg	.LBB0_107
# %bb.102:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB0_103
# %bb.106:
	jmpq	*.LJTI0_3(,%rax,8)
.LBB0_129:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.131:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j # TAILCALL
.LBB0_5:
	.cfi_def_cfa_offset 64
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce1IiEvPT_S1_j # TAILCALL
.LBB0_77:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB0_78
# %bb.82:
	cmpl	$128, %ebp
	je	.LBB0_89
# %bb.83:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB0_87
# %bb.84:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB0_130
# %bb.85:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.86:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j # TAILCALL
.LBB0_107:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB0_108
# %bb.112:
	cmpl	$128, %ebp
	je	.LBB0_119
# %bb.113:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB0_117
# %bb.114:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB0_130
# %bb.115:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.116:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j # TAILCALL
.LBB0_17:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB0_30
# %bb.18:
	cmpl	$64, %ebp
	jne	.LBB0_130
# %bb.19:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.20:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj64EEvPT_S1_j # TAILCALL
.LBB0_47:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB0_60
# %bb.48:
	cmpl	$64, %ebp
	jne	.LBB0_130
# %bb.49:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.50:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj64EEvPT_S1_j # TAILCALL
.LBB0_12:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB0_130
# %bb.13:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.14:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj16EEvPT_S1_j # TAILCALL
.LBB0_42:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB0_130
# %bb.43:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.44:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj16EEvPT_S1_j # TAILCALL
.LBB0_78:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB0_91
# %bb.79:
	cmpl	$64, %ebp
	jne	.LBB0_130
# %bb.80:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.81:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j # TAILCALL
.LBB0_108:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB0_121
# %bb.109:
	cmpl	$64, %ebp
	jne	.LBB0_130
# %bb.110:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.111:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j # TAILCALL
.LBB0_34:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.35:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj4EEvPT_S1_j # TAILCALL
.LBB0_36:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.37:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj2EEvPT_S1_j # TAILCALL
.LBB0_32:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.33:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj8EEvPT_S1_j # TAILCALL
.LBB0_64:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.65:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj4EEvPT_S1_j # TAILCALL
.LBB0_66:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.67:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj2EEvPT_S1_j # TAILCALL
.LBB0_62:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.63:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj8EEvPT_S1_j # TAILCALL
.LBB0_30:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.31:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj32EEvPT_S1_j # TAILCALL
.LBB0_28:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.29:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj128EEvPT_S1_j # TAILCALL
.LBB0_26:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.27:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IiLj256EEvPT_S1_j # TAILCALL
.LBB0_60:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.61:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj32EEvPT_S1_j # TAILCALL
.LBB0_58:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.59:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj128EEvPT_S1_j # TAILCALL
.LBB0_56:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.57:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IiLj256EEvPT_S1_j # TAILCALL
.LBB0_73:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB0_130
# %bb.74:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.75:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j # TAILCALL
.LBB0_103:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB0_130
# %bb.104:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.105:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j # TAILCALL
.LBB0_95:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.96:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j # TAILCALL
.LBB0_125:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.126:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j # TAILCALL
.LBB0_97:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.98:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j # TAILCALL
.LBB0_127:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.128:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j # TAILCALL
.LBB0_93:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.94:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j # TAILCALL
.LBB0_123:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.124:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j # TAILCALL
.LBB0_91:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.92:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j # TAILCALL
.LBB0_121:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.122:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j # TAILCALL
.LBB0_89:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.90:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j # TAILCALL
.LBB0_119:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.120:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j # TAILCALL
.LBB0_87:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.88:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j # TAILCALL
.LBB0_117:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_130
# %bb.118:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j # TAILCALL
.Lfunc_end0:
	.size	_Z6reduceIiEviiiiPT_S1_, .Lfunc_end0-_Z6reduceIiEviiiiPT_S1_
	.cfi_endproc
	.section	.rodata._Z6reduceIiEviiiiPT_S1_,"aG",@progbits,_Z6reduceIiEviiiiPT_S1_,comdat
	.p2align	3, 0x0
.LJTI0_0:
	.quad	.LBB0_2
	.quad	.LBB0_4
	.quad	.LBB0_6
	.quad	.LBB0_8
	.quad	.LBB0_10
	.quad	.LBB0_40
.LJTI0_1:
	.quad	.LBB0_68
	.quad	.LBB0_66
	.quad	.LBB0_130
	.quad	.LBB0_64
	.quad	.LBB0_130
	.quad	.LBB0_130
	.quad	.LBB0_130
	.quad	.LBB0_62
.LJTI0_2:
	.quad	.LBB0_38
	.quad	.LBB0_36
	.quad	.LBB0_130
	.quad	.LBB0_34
	.quad	.LBB0_130
	.quad	.LBB0_130
	.quad	.LBB0_130
	.quad	.LBB0_32
.LJTI0_3:
	.quad	.LBB0_129
	.quad	.LBB0_127
	.quad	.LBB0_130
	.quad	.LBB0_125
	.quad	.LBB0_130
	.quad	.LBB0_130
	.quad	.LBB0_130
	.quad	.LBB0_123
.LJTI0_4:
	.quad	.LBB0_99
	.quad	.LBB0_97
	.quad	.LBB0_130
	.quad	.LBB0_95
	.quad	.LBB0_130
	.quad	.LBB0_130
	.quad	.LBB0_130
	.quad	.LBB0_93
                                        # -- End function
	.section	.text._Z22__device_stub__reduce0IiEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce0IiEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce0IiEvPT_S1_j # -- Begin function _Z22__device_stub__reduce0IiEvPT_S1_j
	.type	_Z22__device_stub__reduce0IiEvPT_S1_j,@function
_Z22__device_stub__reduce0IiEvPT_S1_j:  # @_Z22__device_stub__reduce0IiEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce0IiEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__reduce0IiEvPT_S1_j, .Lfunc_end1-_Z22__device_stub__reduce0IiEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce1IiEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce1IiEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce1IiEvPT_S1_j # -- Begin function _Z22__device_stub__reduce1IiEvPT_S1_j
	.type	_Z22__device_stub__reduce1IiEvPT_S1_j,@function
_Z22__device_stub__reduce1IiEvPT_S1_j:  # @_Z22__device_stub__reduce1IiEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce1IiEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__reduce1IiEvPT_S1_j, .Lfunc_end2-_Z22__device_stub__reduce1IiEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce2IiEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce2IiEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce2IiEvPT_S1_j # -- Begin function _Z22__device_stub__reduce2IiEvPT_S1_j
	.type	_Z22__device_stub__reduce2IiEvPT_S1_j,@function
_Z22__device_stub__reduce2IiEvPT_S1_j:  # @_Z22__device_stub__reduce2IiEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce2IiEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__reduce2IiEvPT_S1_j, .Lfunc_end3-_Z22__device_stub__reduce2IiEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce3IiEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce3IiEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce3IiEvPT_S1_j # -- Begin function _Z22__device_stub__reduce3IiEvPT_S1_j
	.type	_Z22__device_stub__reduce3IiEvPT_S1_j,@function
_Z22__device_stub__reduce3IiEvPT_S1_j:  # @_Z22__device_stub__reduce3IiEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce3IiEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z22__device_stub__reduce3IiEvPT_S1_j, .Lfunc_end4-_Z22__device_stub__reduce3IiEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj512EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj512EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj512EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj512EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj512EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj512EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj512EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj512EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z22__device_stub__reduce4IiLj512EEvPT_S1_j, .Lfunc_end5-_Z22__device_stub__reduce4IiLj512EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj256EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj256EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj256EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj256EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj256EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj256EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj256EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj256EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z22__device_stub__reduce4IiLj256EEvPT_S1_j, .Lfunc_end6-_Z22__device_stub__reduce4IiLj256EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj128EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj128EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj128EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj128EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj128EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj128EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj128EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj128EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z22__device_stub__reduce4IiLj128EEvPT_S1_j, .Lfunc_end7-_Z22__device_stub__reduce4IiLj128EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj64EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj64EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj64EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj64EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj64EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj64EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj64EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj64EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z22__device_stub__reduce4IiLj64EEvPT_S1_j, .Lfunc_end8-_Z22__device_stub__reduce4IiLj64EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj32EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj32EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj32EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj32EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj32EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj32EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj32EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj32EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z22__device_stub__reduce4IiLj32EEvPT_S1_j, .Lfunc_end9-_Z22__device_stub__reduce4IiLj32EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj16EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj16EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj16EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj16EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj16EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj16EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj16EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj16EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z22__device_stub__reduce4IiLj16EEvPT_S1_j, .Lfunc_end10-_Z22__device_stub__reduce4IiLj16EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj8EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj8EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj8EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj8EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj8EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj8EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj8EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj8EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z22__device_stub__reduce4IiLj8EEvPT_S1_j, .Lfunc_end11-_Z22__device_stub__reduce4IiLj8EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj4EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj4EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj4EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj4EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj4EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj4EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj4EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj4EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z22__device_stub__reduce4IiLj4EEvPT_S1_j, .Lfunc_end12-_Z22__device_stub__reduce4IiLj4EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj2EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj2EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj2EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj2EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj2EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj2EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj2EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj2EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z22__device_stub__reduce4IiLj2EEvPT_S1_j, .Lfunc_end13-_Z22__device_stub__reduce4IiLj2EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IiLj1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IiLj1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IiLj1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IiLj1EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IiLj1EEvPT_S1_j,@function
_Z22__device_stub__reduce4IiLj1EEvPT_S1_j: # @_Z22__device_stub__reduce4IiLj1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IiLj1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z22__device_stub__reduce4IiLj1EEvPT_S1_j, .Lfunc_end14-_Z22__device_stub__reduce4IiLj1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj512EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj512EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj512EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj512EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj512EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj512EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj512EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj512EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z22__device_stub__reduce5IiLj512EEvPT_S1_j, .Lfunc_end15-_Z22__device_stub__reduce5IiLj512EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj256EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj256EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj256EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj256EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj256EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj256EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj256EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj256EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z22__device_stub__reduce5IiLj256EEvPT_S1_j, .Lfunc_end16-_Z22__device_stub__reduce5IiLj256EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj128EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj128EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj128EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj128EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj128EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj128EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj128EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj128EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	_Z22__device_stub__reduce5IiLj128EEvPT_S1_j, .Lfunc_end17-_Z22__device_stub__reduce5IiLj128EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj64EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj64EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj64EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj64EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj64EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj64EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj64EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj64EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end18:
	.size	_Z22__device_stub__reduce5IiLj64EEvPT_S1_j, .Lfunc_end18-_Z22__device_stub__reduce5IiLj64EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj32EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj32EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj32EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj32EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj32EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj32EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj32EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj32EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	_Z22__device_stub__reduce5IiLj32EEvPT_S1_j, .Lfunc_end19-_Z22__device_stub__reduce5IiLj32EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj16EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj16EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj16EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj16EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj16EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj16EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj16EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj16EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	_Z22__device_stub__reduce5IiLj16EEvPT_S1_j, .Lfunc_end20-_Z22__device_stub__reduce5IiLj16EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj8EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj8EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj8EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj8EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj8EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj8EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj8EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj8EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end21:
	.size	_Z22__device_stub__reduce5IiLj8EEvPT_S1_j, .Lfunc_end21-_Z22__device_stub__reduce5IiLj8EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj4EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj4EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj4EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj4EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj4EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj4EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj4EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj4EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end22:
	.size	_Z22__device_stub__reduce5IiLj4EEvPT_S1_j, .Lfunc_end22-_Z22__device_stub__reduce5IiLj4EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj2EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj2EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj2EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj2EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj2EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj2EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj2EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj2EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end23:
	.size	_Z22__device_stub__reduce5IiLj2EEvPT_S1_j, .Lfunc_end23-_Z22__device_stub__reduce5IiLj2EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IiLj1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IiLj1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IiLj1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IiLj1EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IiLj1EEvPT_S1_j,@function
_Z22__device_stub__reduce5IiLj1EEvPT_S1_j: # @_Z22__device_stub__reduce5IiLj1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IiLj1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end24:
	.size	_Z22__device_stub__reduce5IiLj1EEvPT_S1_j, .Lfunc_end24-_Z22__device_stub__reduce5IiLj1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj512ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end25:
	.size	_Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j, .Lfunc_end25-_Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj256ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end26:
	.size	_Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j, .Lfunc_end26-_Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj128ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end27:
	.size	_Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j, .Lfunc_end27-_Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj64ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end28:
	.size	_Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j, .Lfunc_end28-_Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj32ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end29:
	.size	_Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j, .Lfunc_end29-_Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj16ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end30:
	.size	_Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j, .Lfunc_end30-_Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj8ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end31:
	.size	_Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j, .Lfunc_end31-_Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj4ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end32:
	.size	_Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j, .Lfunc_end32-_Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj2ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end33:
	.size	_Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j, .Lfunc_end33-_Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj1ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end34:
	.size	_Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j, .Lfunc_end34-_Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj512ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end35:
	.size	_Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j, .Lfunc_end35-_Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj256ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end36:
	.size	_Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j, .Lfunc_end36-_Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj128ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end37:
	.size	_Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j, .Lfunc_end37-_Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj64ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end38:
	.size	_Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j, .Lfunc_end38-_Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj32ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end39:
	.size	_Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j, .Lfunc_end39-_Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj16ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end40:
	.size	_Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j, .Lfunc_end40-_Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj8ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end41:
	.size	_Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j, .Lfunc_end41-_Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj4ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end42:
	.size	_Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j, .Lfunc_end42-_Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj2ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end43:
	.size	_Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j, .Lfunc_end43-_Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IiLj1ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end44:
	.size	_Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j, .Lfunc_end44-_Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z6reduceIfEviiiiPT_S1_,"axG",@progbits,_Z6reduceIfEviiiiPT_S1_,comdat
	.weak	_Z6reduceIfEviiiiPT_S1_         # -- Begin function _Z6reduceIfEviiiiPT_S1_
	.type	_Z6reduceIfEviiiiPT_S1_,@function
_Z6reduceIfEviiiiPT_S1_:                # @_Z6reduceIfEviiiiPT_S1_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %eax
	movl	%esi, %ebp
	movl	%esi, %r12d
	btsq	$32, %r12
	movl	%edx, %r13d
	btsq	$32, %r13
	cmpl	$33, %esi
	setl	%cl
	movl	%esi, %r14d
	shll	%cl, %r14d
	movq	%r8, %r15
	movl	%edi, %ebx
	shll	$2, %r14d
	cmpl	$5, %eax
	ja	.LBB45_70
# %bb.1:
	movl	%eax, %eax
	jmpq	*.LJTI45_0(,%rax,8)
.LBB45_2:
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.3:
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce0IfEvPT_S1_j # TAILCALL
.LBB45_10:
	.cfi_def_cfa_offset 64
	cmpl	$31, %ebp
	movq	%r9, (%rsp)                     # 8-byte Spill
	jg	.LBB45_16
# %bb.11:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB45_12
# %bb.15:
	jmpq	*.LJTI45_2(,%rax,8)
.LBB45_38:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.39:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj1EEvPT_S1_j # TAILCALL
.LBB45_6:
	.cfi_def_cfa_offset 64
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.7:
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce2IfEvPT_S1_j # TAILCALL
.LBB45_8:
	.cfi_def_cfa_offset 64
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.9:
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce3IfEvPT_S1_j # TAILCALL
.LBB45_4:
	.cfi_def_cfa_offset 64
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB45_5
.LBB45_130:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB45_40:
	.cfi_def_cfa_offset 64
	cmpl	$31, %ebp
	movq	%r9, (%rsp)                     # 8-byte Spill
	jg	.LBB45_46
# %bb.41:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB45_42
# %bb.45:
	jmpq	*.LJTI45_1(,%rax,8)
.LBB45_68:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.69:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj1EEvPT_S1_j # TAILCALL
.LBB45_70:
	.cfi_def_cfa_offset 64
	movq	%r9, (%rsp)                     # 8-byte Spill
	movl	%ebx, %edi
	callq	isPow2
	testb	%al, %al
	je	.LBB45_101
# %bb.71:
	cmpl	$31, %ebp
	jg	.LBB45_77
# %bb.72:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB45_73
# %bb.76:
	jmpq	*.LJTI45_4(,%rax,8)
.LBB45_99:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.100:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j # TAILCALL
.LBB45_16:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB45_17
# %bb.21:
	cmpl	$128, %ebp
	je	.LBB45_28
# %bb.22:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB45_26
# %bb.23:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB45_130
# %bb.24:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.25:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj512EEvPT_S1_j # TAILCALL
.LBB45_46:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB45_47
# %bb.51:
	cmpl	$128, %ebp
	je	.LBB45_58
# %bb.52:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB45_56
# %bb.53:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB45_130
# %bb.54:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.55:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj512EEvPT_S1_j # TAILCALL
.LBB45_101:
	.cfi_def_cfa_offset 64
	cmpl	$31, %ebp
	jg	.LBB45_107
# %bb.102:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB45_103
# %bb.106:
	jmpq	*.LJTI45_3(,%rax,8)
.LBB45_129:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.131:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j # TAILCALL
.LBB45_5:
	.cfi_def_cfa_offset 64
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce1IfEvPT_S1_j # TAILCALL
.LBB45_77:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB45_78
# %bb.82:
	cmpl	$128, %ebp
	je	.LBB45_89
# %bb.83:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB45_87
# %bb.84:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB45_130
# %bb.85:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.86:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j # TAILCALL
.LBB45_107:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB45_108
# %bb.112:
	cmpl	$128, %ebp
	je	.LBB45_119
# %bb.113:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB45_117
# %bb.114:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB45_130
# %bb.115:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.116:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j # TAILCALL
.LBB45_17:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB45_30
# %bb.18:
	cmpl	$64, %ebp
	jne	.LBB45_130
# %bb.19:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.20:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj64EEvPT_S1_j # TAILCALL
.LBB45_47:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB45_60
# %bb.48:
	cmpl	$64, %ebp
	jne	.LBB45_130
# %bb.49:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.50:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj64EEvPT_S1_j # TAILCALL
.LBB45_12:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB45_130
# %bb.13:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.14:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj16EEvPT_S1_j # TAILCALL
.LBB45_42:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB45_130
# %bb.43:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.44:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj16EEvPT_S1_j # TAILCALL
.LBB45_78:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB45_91
# %bb.79:
	cmpl	$64, %ebp
	jne	.LBB45_130
# %bb.80:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.81:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j # TAILCALL
.LBB45_108:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB45_121
# %bb.109:
	cmpl	$64, %ebp
	jne	.LBB45_130
# %bb.110:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.111:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j # TAILCALL
.LBB45_34:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.35:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj4EEvPT_S1_j # TAILCALL
.LBB45_36:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.37:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj2EEvPT_S1_j # TAILCALL
.LBB45_32:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.33:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj8EEvPT_S1_j # TAILCALL
.LBB45_64:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.65:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj4EEvPT_S1_j # TAILCALL
.LBB45_66:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.67:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj2EEvPT_S1_j # TAILCALL
.LBB45_62:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.63:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj8EEvPT_S1_j # TAILCALL
.LBB45_30:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.31:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj32EEvPT_S1_j # TAILCALL
.LBB45_28:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.29:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj128EEvPT_S1_j # TAILCALL
.LBB45_26:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.27:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IfLj256EEvPT_S1_j # TAILCALL
.LBB45_60:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.61:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj32EEvPT_S1_j # TAILCALL
.LBB45_58:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.59:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj128EEvPT_S1_j # TAILCALL
.LBB45_56:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.57:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IfLj256EEvPT_S1_j # TAILCALL
.LBB45_73:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB45_130
# %bb.74:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.75:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j # TAILCALL
.LBB45_103:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB45_130
# %bb.104:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.105:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j # TAILCALL
.LBB45_95:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.96:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j # TAILCALL
.LBB45_125:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.126:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j # TAILCALL
.LBB45_97:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.98:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j # TAILCALL
.LBB45_127:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.128:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j # TAILCALL
.LBB45_93:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.94:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j # TAILCALL
.LBB45_123:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.124:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j # TAILCALL
.LBB45_91:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.92:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j # TAILCALL
.LBB45_121:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.122:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j # TAILCALL
.LBB45_89:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.90:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j # TAILCALL
.LBB45_119:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.120:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j # TAILCALL
.LBB45_87:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.88:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j # TAILCALL
.LBB45_117:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB45_130
# %bb.118:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j # TAILCALL
.Lfunc_end45:
	.size	_Z6reduceIfEviiiiPT_S1_, .Lfunc_end45-_Z6reduceIfEviiiiPT_S1_
	.cfi_endproc
	.section	.rodata._Z6reduceIfEviiiiPT_S1_,"aG",@progbits,_Z6reduceIfEviiiiPT_S1_,comdat
	.p2align	3, 0x0
.LJTI45_0:
	.quad	.LBB45_2
	.quad	.LBB45_4
	.quad	.LBB45_6
	.quad	.LBB45_8
	.quad	.LBB45_10
	.quad	.LBB45_40
.LJTI45_1:
	.quad	.LBB45_68
	.quad	.LBB45_66
	.quad	.LBB45_130
	.quad	.LBB45_64
	.quad	.LBB45_130
	.quad	.LBB45_130
	.quad	.LBB45_130
	.quad	.LBB45_62
.LJTI45_2:
	.quad	.LBB45_38
	.quad	.LBB45_36
	.quad	.LBB45_130
	.quad	.LBB45_34
	.quad	.LBB45_130
	.quad	.LBB45_130
	.quad	.LBB45_130
	.quad	.LBB45_32
.LJTI45_3:
	.quad	.LBB45_129
	.quad	.LBB45_127
	.quad	.LBB45_130
	.quad	.LBB45_125
	.quad	.LBB45_130
	.quad	.LBB45_130
	.quad	.LBB45_130
	.quad	.LBB45_123
.LJTI45_4:
	.quad	.LBB45_99
	.quad	.LBB45_97
	.quad	.LBB45_130
	.quad	.LBB45_95
	.quad	.LBB45_130
	.quad	.LBB45_130
	.quad	.LBB45_130
	.quad	.LBB45_93
                                        # -- End function
	.section	.text._Z22__device_stub__reduce0IfEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce0IfEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce0IfEvPT_S1_j # -- Begin function _Z22__device_stub__reduce0IfEvPT_S1_j
	.type	_Z22__device_stub__reduce0IfEvPT_S1_j,@function
_Z22__device_stub__reduce0IfEvPT_S1_j:  # @_Z22__device_stub__reduce0IfEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce0IfEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end46:
	.size	_Z22__device_stub__reduce0IfEvPT_S1_j, .Lfunc_end46-_Z22__device_stub__reduce0IfEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce1IfEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce1IfEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce1IfEvPT_S1_j # -- Begin function _Z22__device_stub__reduce1IfEvPT_S1_j
	.type	_Z22__device_stub__reduce1IfEvPT_S1_j,@function
_Z22__device_stub__reduce1IfEvPT_S1_j:  # @_Z22__device_stub__reduce1IfEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce1IfEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end47:
	.size	_Z22__device_stub__reduce1IfEvPT_S1_j, .Lfunc_end47-_Z22__device_stub__reduce1IfEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce2IfEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce2IfEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce2IfEvPT_S1_j # -- Begin function _Z22__device_stub__reduce2IfEvPT_S1_j
	.type	_Z22__device_stub__reduce2IfEvPT_S1_j,@function
_Z22__device_stub__reduce2IfEvPT_S1_j:  # @_Z22__device_stub__reduce2IfEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce2IfEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end48:
	.size	_Z22__device_stub__reduce2IfEvPT_S1_j, .Lfunc_end48-_Z22__device_stub__reduce2IfEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce3IfEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce3IfEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce3IfEvPT_S1_j # -- Begin function _Z22__device_stub__reduce3IfEvPT_S1_j
	.type	_Z22__device_stub__reduce3IfEvPT_S1_j,@function
_Z22__device_stub__reduce3IfEvPT_S1_j:  # @_Z22__device_stub__reduce3IfEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce3IfEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end49:
	.size	_Z22__device_stub__reduce3IfEvPT_S1_j, .Lfunc_end49-_Z22__device_stub__reduce3IfEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj512EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj512EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj512EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj512EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj512EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj512EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj512EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj512EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end50:
	.size	_Z22__device_stub__reduce4IfLj512EEvPT_S1_j, .Lfunc_end50-_Z22__device_stub__reduce4IfLj512EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj256EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj256EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj256EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj256EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj256EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj256EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj256EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj256EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end51:
	.size	_Z22__device_stub__reduce4IfLj256EEvPT_S1_j, .Lfunc_end51-_Z22__device_stub__reduce4IfLj256EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj128EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj128EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj128EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj128EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj128EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj128EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj128EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj128EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end52:
	.size	_Z22__device_stub__reduce4IfLj128EEvPT_S1_j, .Lfunc_end52-_Z22__device_stub__reduce4IfLj128EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj64EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj64EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj64EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj64EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj64EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj64EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj64EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj64EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end53:
	.size	_Z22__device_stub__reduce4IfLj64EEvPT_S1_j, .Lfunc_end53-_Z22__device_stub__reduce4IfLj64EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj32EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj32EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj32EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj32EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj32EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj32EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj32EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj32EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end54:
	.size	_Z22__device_stub__reduce4IfLj32EEvPT_S1_j, .Lfunc_end54-_Z22__device_stub__reduce4IfLj32EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj16EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj16EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj16EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj16EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj16EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj16EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj16EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj16EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end55:
	.size	_Z22__device_stub__reduce4IfLj16EEvPT_S1_j, .Lfunc_end55-_Z22__device_stub__reduce4IfLj16EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj8EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj8EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj8EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj8EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj8EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj8EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj8EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj8EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end56:
	.size	_Z22__device_stub__reduce4IfLj8EEvPT_S1_j, .Lfunc_end56-_Z22__device_stub__reduce4IfLj8EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj4EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj4EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj4EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj4EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj4EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj4EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj4EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj4EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end57:
	.size	_Z22__device_stub__reduce4IfLj4EEvPT_S1_j, .Lfunc_end57-_Z22__device_stub__reduce4IfLj4EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj2EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj2EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj2EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj2EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj2EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj2EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj2EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj2EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end58:
	.size	_Z22__device_stub__reduce4IfLj2EEvPT_S1_j, .Lfunc_end58-_Z22__device_stub__reduce4IfLj2EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IfLj1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IfLj1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IfLj1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IfLj1EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IfLj1EEvPT_S1_j,@function
_Z22__device_stub__reduce4IfLj1EEvPT_S1_j: # @_Z22__device_stub__reduce4IfLj1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IfLj1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end59:
	.size	_Z22__device_stub__reduce4IfLj1EEvPT_S1_j, .Lfunc_end59-_Z22__device_stub__reduce4IfLj1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj512EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj512EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj512EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj512EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj512EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj512EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj512EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj512EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end60:
	.size	_Z22__device_stub__reduce5IfLj512EEvPT_S1_j, .Lfunc_end60-_Z22__device_stub__reduce5IfLj512EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj256EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj256EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj256EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj256EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj256EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj256EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj256EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj256EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end61:
	.size	_Z22__device_stub__reduce5IfLj256EEvPT_S1_j, .Lfunc_end61-_Z22__device_stub__reduce5IfLj256EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj128EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj128EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj128EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj128EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj128EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj128EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj128EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj128EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end62:
	.size	_Z22__device_stub__reduce5IfLj128EEvPT_S1_j, .Lfunc_end62-_Z22__device_stub__reduce5IfLj128EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj64EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj64EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj64EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj64EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj64EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj64EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj64EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj64EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end63:
	.size	_Z22__device_stub__reduce5IfLj64EEvPT_S1_j, .Lfunc_end63-_Z22__device_stub__reduce5IfLj64EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj32EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj32EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj32EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj32EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj32EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj32EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj32EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj32EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end64:
	.size	_Z22__device_stub__reduce5IfLj32EEvPT_S1_j, .Lfunc_end64-_Z22__device_stub__reduce5IfLj32EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj16EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj16EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj16EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj16EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj16EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj16EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj16EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj16EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end65:
	.size	_Z22__device_stub__reduce5IfLj16EEvPT_S1_j, .Lfunc_end65-_Z22__device_stub__reduce5IfLj16EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj8EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj8EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj8EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj8EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj8EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj8EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj8EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj8EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end66:
	.size	_Z22__device_stub__reduce5IfLj8EEvPT_S1_j, .Lfunc_end66-_Z22__device_stub__reduce5IfLj8EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj4EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj4EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj4EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj4EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj4EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj4EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj4EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj4EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end67:
	.size	_Z22__device_stub__reduce5IfLj4EEvPT_S1_j, .Lfunc_end67-_Z22__device_stub__reduce5IfLj4EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj2EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj2EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj2EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj2EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj2EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj2EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj2EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj2EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end68:
	.size	_Z22__device_stub__reduce5IfLj2EEvPT_S1_j, .Lfunc_end68-_Z22__device_stub__reduce5IfLj2EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IfLj1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IfLj1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IfLj1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IfLj1EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IfLj1EEvPT_S1_j,@function
_Z22__device_stub__reduce5IfLj1EEvPT_S1_j: # @_Z22__device_stub__reduce5IfLj1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IfLj1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end69:
	.size	_Z22__device_stub__reduce5IfLj1EEvPT_S1_j, .Lfunc_end69-_Z22__device_stub__reduce5IfLj1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj512ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end70:
	.size	_Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j, .Lfunc_end70-_Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj256ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end71:
	.size	_Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j, .Lfunc_end71-_Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj128ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end72:
	.size	_Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j, .Lfunc_end72-_Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj64ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end73:
	.size	_Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j, .Lfunc_end73-_Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj32ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end74:
	.size	_Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j, .Lfunc_end74-_Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj16ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end75:
	.size	_Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j, .Lfunc_end75-_Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj8ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end76:
	.size	_Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j, .Lfunc_end76-_Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj4ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end77:
	.size	_Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j, .Lfunc_end77-_Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj2ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end78:
	.size	_Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j, .Lfunc_end78-_Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj1ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end79:
	.size	_Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j, .Lfunc_end79-_Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj512ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end80:
	.size	_Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j, .Lfunc_end80-_Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj256ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end81:
	.size	_Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j, .Lfunc_end81-_Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj128ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end82:
	.size	_Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j, .Lfunc_end82-_Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj64ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end83:
	.size	_Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j, .Lfunc_end83-_Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj32ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end84:
	.size	_Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j, .Lfunc_end84-_Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj16ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end85:
	.size	_Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j, .Lfunc_end85-_Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj8ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end86:
	.size	_Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j, .Lfunc_end86-_Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj4ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end87:
	.size	_Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j, .Lfunc_end87-_Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj2ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end88:
	.size	_Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j, .Lfunc_end88-_Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IfLj1ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end89:
	.size	_Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j, .Lfunc_end89-_Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z6reduceIdEviiiiPT_S1_,"axG",@progbits,_Z6reduceIdEviiiiPT_S1_,comdat
	.weak	_Z6reduceIdEviiiiPT_S1_         # -- Begin function _Z6reduceIdEviiiiPT_S1_
	.type	_Z6reduceIdEviiiiPT_S1_,@function
_Z6reduceIdEviiiiPT_S1_:                # @_Z6reduceIdEviiiiPT_S1_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %eax
	movl	%esi, %ebp
	movl	%esi, %r12d
	btsq	$32, %r12
	movl	%edx, %r13d
	btsq	$32, %r13
	cmpl	$33, %esi
	setl	%cl
	movl	%esi, %r14d
	shll	%cl, %r14d
	movq	%r8, %r15
	movl	%edi, %ebx
	shll	$3, %r14d
	cmpl	$5, %eax
	ja	.LBB90_70
# %bb.1:
	movl	%eax, %eax
	jmpq	*.LJTI90_0(,%rax,8)
.LBB90_2:
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.3:
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce0IdEvPT_S1_j # TAILCALL
.LBB90_10:
	.cfi_def_cfa_offset 64
	cmpl	$31, %ebp
	movq	%r9, (%rsp)                     # 8-byte Spill
	jg	.LBB90_16
# %bb.11:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB90_12
# %bb.15:
	jmpq	*.LJTI90_2(,%rax,8)
.LBB90_38:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.39:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj1EEvPT_S1_j # TAILCALL
.LBB90_6:
	.cfi_def_cfa_offset 64
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.7:
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce2IdEvPT_S1_j # TAILCALL
.LBB90_8:
	.cfi_def_cfa_offset 64
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.9:
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce3IdEvPT_S1_j # TAILCALL
.LBB90_4:
	.cfi_def_cfa_offset 64
	movq	%r9, %rbp
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB90_5
.LBB90_130:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB90_40:
	.cfi_def_cfa_offset 64
	cmpl	$31, %ebp
	movq	%r9, (%rsp)                     # 8-byte Spill
	jg	.LBB90_46
# %bb.41:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB90_42
# %bb.45:
	jmpq	*.LJTI90_1(,%rax,8)
.LBB90_68:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.69:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj1EEvPT_S1_j # TAILCALL
.LBB90_70:
	.cfi_def_cfa_offset 64
	movq	%r9, (%rsp)                     # 8-byte Spill
	movl	%ebx, %edi
	callq	isPow2
	testb	%al, %al
	je	.LBB90_101
# %bb.71:
	cmpl	$31, %ebp
	jg	.LBB90_77
# %bb.72:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB90_73
# %bb.76:
	jmpq	*.LJTI90_4(,%rax,8)
.LBB90_99:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.100:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j # TAILCALL
.LBB90_16:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB90_17
# %bb.21:
	cmpl	$128, %ebp
	je	.LBB90_28
# %bb.22:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB90_26
# %bb.23:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB90_130
# %bb.24:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.25:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj512EEvPT_S1_j # TAILCALL
.LBB90_46:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB90_47
# %bb.51:
	cmpl	$128, %ebp
	je	.LBB90_58
# %bb.52:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB90_56
# %bb.53:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB90_130
# %bb.54:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.55:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj512EEvPT_S1_j # TAILCALL
.LBB90_101:
	.cfi_def_cfa_offset 64
	cmpl	$31, %ebp
	jg	.LBB90_107
# %bb.102:
	leal	-1(%rbp), %eax
	cmpl	$7, %eax
	ja	.LBB90_103
# %bb.106:
	jmpq	*.LJTI90_3(,%rax,8)
.LBB90_129:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.131:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j # TAILCALL
.LBB90_5:
	.cfi_def_cfa_offset 64
	movq	%r15, %rdi
	movq	%rbp, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce1IdEvPT_S1_j # TAILCALL
.LBB90_77:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB90_78
# %bb.82:
	cmpl	$128, %ebp
	je	.LBB90_89
# %bb.83:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB90_87
# %bb.84:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB90_130
# %bb.85:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.86:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j # TAILCALL
.LBB90_107:
	.cfi_def_cfa_offset 64
	cmpl	$127, %ebp
	jle	.LBB90_108
# %bb.112:
	cmpl	$128, %ebp
	je	.LBB90_119
# %bb.113:
	cmpl	$256, %ebp                      # imm = 0x100
	je	.LBB90_117
# %bb.114:
	cmpl	$512, %ebp                      # imm = 0x200
	jne	.LBB90_130
# %bb.115:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.116:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j # TAILCALL
.LBB90_17:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB90_30
# %bb.18:
	cmpl	$64, %ebp
	jne	.LBB90_130
# %bb.19:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.20:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj64EEvPT_S1_j # TAILCALL
.LBB90_47:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB90_60
# %bb.48:
	cmpl	$64, %ebp
	jne	.LBB90_130
# %bb.49:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.50:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj64EEvPT_S1_j # TAILCALL
.LBB90_12:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB90_130
# %bb.13:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.14:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj16EEvPT_S1_j # TAILCALL
.LBB90_42:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB90_130
# %bb.43:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.44:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj16EEvPT_S1_j # TAILCALL
.LBB90_78:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB90_91
# %bb.79:
	cmpl	$64, %ebp
	jne	.LBB90_130
# %bb.80:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.81:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j # TAILCALL
.LBB90_108:
	.cfi_def_cfa_offset 64
	cmpl	$32, %ebp
	je	.LBB90_121
# %bb.109:
	cmpl	$64, %ebp
	jne	.LBB90_130
# %bb.110:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.111:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j # TAILCALL
.LBB90_34:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.35:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj4EEvPT_S1_j # TAILCALL
.LBB90_36:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.37:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj2EEvPT_S1_j # TAILCALL
.LBB90_32:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.33:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj8EEvPT_S1_j # TAILCALL
.LBB90_64:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.65:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj4EEvPT_S1_j # TAILCALL
.LBB90_66:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.67:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj2EEvPT_S1_j # TAILCALL
.LBB90_62:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.63:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj8EEvPT_S1_j # TAILCALL
.LBB90_30:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.31:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj32EEvPT_S1_j # TAILCALL
.LBB90_28:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.29:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj128EEvPT_S1_j # TAILCALL
.LBB90_26:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.27:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce4IdLj256EEvPT_S1_j # TAILCALL
.LBB90_60:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.61:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj32EEvPT_S1_j # TAILCALL
.LBB90_58:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.59:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj128EEvPT_S1_j # TAILCALL
.LBB90_56:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.57:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce5IdLj256EEvPT_S1_j # TAILCALL
.LBB90_73:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB90_130
# %bb.74:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.75:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j # TAILCALL
.LBB90_103:
	.cfi_def_cfa_offset 64
	cmpl	$16, %ebp
	jne	.LBB90_130
# %bb.104:
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.105:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j # TAILCALL
.LBB90_95:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.96:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j # TAILCALL
.LBB90_125:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.126:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j # TAILCALL
.LBB90_97:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.98:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j # TAILCALL
.LBB90_127:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.128:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j # TAILCALL
.LBB90_93:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.94:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j # TAILCALL
.LBB90_123:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.124:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j # TAILCALL
.LBB90_91:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.92:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j # TAILCALL
.LBB90_121:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.122:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j # TAILCALL
.LBB90_89:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.90:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j # TAILCALL
.LBB90_119:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.120:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j # TAILCALL
.LBB90_87:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.88:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j # TAILCALL
.LBB90_117:
	.cfi_def_cfa_offset 64
	movslq	%r14d, %r8
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB90_130
# %bb.118:
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	%ebx, %edx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j # TAILCALL
.Lfunc_end90:
	.size	_Z6reduceIdEviiiiPT_S1_, .Lfunc_end90-_Z6reduceIdEviiiiPT_S1_
	.cfi_endproc
	.section	.rodata._Z6reduceIdEviiiiPT_S1_,"aG",@progbits,_Z6reduceIdEviiiiPT_S1_,comdat
	.p2align	3, 0x0
.LJTI90_0:
	.quad	.LBB90_2
	.quad	.LBB90_4
	.quad	.LBB90_6
	.quad	.LBB90_8
	.quad	.LBB90_10
	.quad	.LBB90_40
.LJTI90_1:
	.quad	.LBB90_68
	.quad	.LBB90_66
	.quad	.LBB90_130
	.quad	.LBB90_64
	.quad	.LBB90_130
	.quad	.LBB90_130
	.quad	.LBB90_130
	.quad	.LBB90_62
.LJTI90_2:
	.quad	.LBB90_38
	.quad	.LBB90_36
	.quad	.LBB90_130
	.quad	.LBB90_34
	.quad	.LBB90_130
	.quad	.LBB90_130
	.quad	.LBB90_130
	.quad	.LBB90_32
.LJTI90_3:
	.quad	.LBB90_129
	.quad	.LBB90_127
	.quad	.LBB90_130
	.quad	.LBB90_125
	.quad	.LBB90_130
	.quad	.LBB90_130
	.quad	.LBB90_130
	.quad	.LBB90_123
.LJTI90_4:
	.quad	.LBB90_99
	.quad	.LBB90_97
	.quad	.LBB90_130
	.quad	.LBB90_95
	.quad	.LBB90_130
	.quad	.LBB90_130
	.quad	.LBB90_130
	.quad	.LBB90_93
                                        # -- End function
	.section	.text._Z22__device_stub__reduce0IdEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce0IdEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce0IdEvPT_S1_j # -- Begin function _Z22__device_stub__reduce0IdEvPT_S1_j
	.type	_Z22__device_stub__reduce0IdEvPT_S1_j,@function
_Z22__device_stub__reduce0IdEvPT_S1_j:  # @_Z22__device_stub__reduce0IdEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce0IdEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end91:
	.size	_Z22__device_stub__reduce0IdEvPT_S1_j, .Lfunc_end91-_Z22__device_stub__reduce0IdEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce1IdEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce1IdEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce1IdEvPT_S1_j # -- Begin function _Z22__device_stub__reduce1IdEvPT_S1_j
	.type	_Z22__device_stub__reduce1IdEvPT_S1_j,@function
_Z22__device_stub__reduce1IdEvPT_S1_j:  # @_Z22__device_stub__reduce1IdEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce1IdEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end92:
	.size	_Z22__device_stub__reduce1IdEvPT_S1_j, .Lfunc_end92-_Z22__device_stub__reduce1IdEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce2IdEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce2IdEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce2IdEvPT_S1_j # -- Begin function _Z22__device_stub__reduce2IdEvPT_S1_j
	.type	_Z22__device_stub__reduce2IdEvPT_S1_j,@function
_Z22__device_stub__reduce2IdEvPT_S1_j:  # @_Z22__device_stub__reduce2IdEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce2IdEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end93:
	.size	_Z22__device_stub__reduce2IdEvPT_S1_j, .Lfunc_end93-_Z22__device_stub__reduce2IdEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce3IdEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce3IdEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce3IdEvPT_S1_j # -- Begin function _Z22__device_stub__reduce3IdEvPT_S1_j
	.type	_Z22__device_stub__reduce3IdEvPT_S1_j,@function
_Z22__device_stub__reduce3IdEvPT_S1_j:  # @_Z22__device_stub__reduce3IdEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce3IdEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end94:
	.size	_Z22__device_stub__reduce3IdEvPT_S1_j, .Lfunc_end94-_Z22__device_stub__reduce3IdEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj512EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj512EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj512EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj512EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj512EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj512EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj512EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj512EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end95:
	.size	_Z22__device_stub__reduce4IdLj512EEvPT_S1_j, .Lfunc_end95-_Z22__device_stub__reduce4IdLj512EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj256EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj256EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj256EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj256EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj256EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj256EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj256EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj256EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end96:
	.size	_Z22__device_stub__reduce4IdLj256EEvPT_S1_j, .Lfunc_end96-_Z22__device_stub__reduce4IdLj256EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj128EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj128EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj128EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj128EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj128EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj128EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj128EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj128EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end97:
	.size	_Z22__device_stub__reduce4IdLj128EEvPT_S1_j, .Lfunc_end97-_Z22__device_stub__reduce4IdLj128EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj64EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj64EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj64EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj64EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj64EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj64EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj64EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj64EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end98:
	.size	_Z22__device_stub__reduce4IdLj64EEvPT_S1_j, .Lfunc_end98-_Z22__device_stub__reduce4IdLj64EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj32EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj32EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj32EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj32EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj32EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj32EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj32EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj32EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end99:
	.size	_Z22__device_stub__reduce4IdLj32EEvPT_S1_j, .Lfunc_end99-_Z22__device_stub__reduce4IdLj32EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj16EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj16EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj16EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj16EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj16EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj16EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj16EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj16EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end100:
	.size	_Z22__device_stub__reduce4IdLj16EEvPT_S1_j, .Lfunc_end100-_Z22__device_stub__reduce4IdLj16EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj8EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj8EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj8EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj8EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj8EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj8EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj8EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj8EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end101:
	.size	_Z22__device_stub__reduce4IdLj8EEvPT_S1_j, .Lfunc_end101-_Z22__device_stub__reduce4IdLj8EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj4EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj4EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj4EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj4EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj4EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj4EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj4EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj4EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end102:
	.size	_Z22__device_stub__reduce4IdLj4EEvPT_S1_j, .Lfunc_end102-_Z22__device_stub__reduce4IdLj4EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj2EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj2EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj2EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj2EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj2EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj2EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj2EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj2EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end103:
	.size	_Z22__device_stub__reduce4IdLj2EEvPT_S1_j, .Lfunc_end103-_Z22__device_stub__reduce4IdLj2EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce4IdLj1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce4IdLj1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce4IdLj1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce4IdLj1EEvPT_S1_j
	.type	_Z22__device_stub__reduce4IdLj1EEvPT_S1_j,@function
_Z22__device_stub__reduce4IdLj1EEvPT_S1_j: # @_Z22__device_stub__reduce4IdLj1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce4IdLj1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end104:
	.size	_Z22__device_stub__reduce4IdLj1EEvPT_S1_j, .Lfunc_end104-_Z22__device_stub__reduce4IdLj1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj512EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj512EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj512EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj512EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj512EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj512EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj512EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj512EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end105:
	.size	_Z22__device_stub__reduce5IdLj512EEvPT_S1_j, .Lfunc_end105-_Z22__device_stub__reduce5IdLj512EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj256EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj256EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj256EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj256EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj256EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj256EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj256EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj256EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end106:
	.size	_Z22__device_stub__reduce5IdLj256EEvPT_S1_j, .Lfunc_end106-_Z22__device_stub__reduce5IdLj256EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj128EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj128EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj128EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj128EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj128EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj128EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj128EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj128EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end107:
	.size	_Z22__device_stub__reduce5IdLj128EEvPT_S1_j, .Lfunc_end107-_Z22__device_stub__reduce5IdLj128EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj64EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj64EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj64EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj64EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj64EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj64EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj64EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj64EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end108:
	.size	_Z22__device_stub__reduce5IdLj64EEvPT_S1_j, .Lfunc_end108-_Z22__device_stub__reduce5IdLj64EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj32EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj32EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj32EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj32EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj32EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj32EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj32EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj32EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end109:
	.size	_Z22__device_stub__reduce5IdLj32EEvPT_S1_j, .Lfunc_end109-_Z22__device_stub__reduce5IdLj32EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj16EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj16EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj16EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj16EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj16EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj16EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj16EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj16EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end110:
	.size	_Z22__device_stub__reduce5IdLj16EEvPT_S1_j, .Lfunc_end110-_Z22__device_stub__reduce5IdLj16EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj8EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj8EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj8EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj8EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj8EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj8EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj8EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj8EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end111:
	.size	_Z22__device_stub__reduce5IdLj8EEvPT_S1_j, .Lfunc_end111-_Z22__device_stub__reduce5IdLj8EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj4EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj4EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj4EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj4EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj4EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj4EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj4EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj4EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end112:
	.size	_Z22__device_stub__reduce5IdLj4EEvPT_S1_j, .Lfunc_end112-_Z22__device_stub__reduce5IdLj4EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj2EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj2EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj2EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj2EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj2EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj2EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj2EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj2EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end113:
	.size	_Z22__device_stub__reduce5IdLj2EEvPT_S1_j, .Lfunc_end113-_Z22__device_stub__reduce5IdLj2EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce5IdLj1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce5IdLj1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce5IdLj1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce5IdLj1EEvPT_S1_j
	.type	_Z22__device_stub__reduce5IdLj1EEvPT_S1_j,@function
_Z22__device_stub__reduce5IdLj1EEvPT_S1_j: # @_Z22__device_stub__reduce5IdLj1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce5IdLj1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end114:
	.size	_Z22__device_stub__reduce5IdLj1EEvPT_S1_j, .Lfunc_end114-_Z22__device_stub__reduce5IdLj1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj512ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end115:
	.size	_Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j, .Lfunc_end115-_Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj256ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end116:
	.size	_Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j, .Lfunc_end116-_Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj128ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end117:
	.size	_Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j, .Lfunc_end117-_Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj64ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end118:
	.size	_Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j, .Lfunc_end118-_Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj32ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end119:
	.size	_Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j, .Lfunc_end119-_Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj16ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end120:
	.size	_Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j, .Lfunc_end120-_Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj8ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end121:
	.size	_Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j, .Lfunc_end121-_Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj4ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end122:
	.size	_Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j, .Lfunc_end122-_Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj2ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end123:
	.size	_Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j, .Lfunc_end123-_Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj1ELb1EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end124:
	.size	_Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j, .Lfunc_end124-_Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj512ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end125:
	.size	_Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j, .Lfunc_end125-_Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj256ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end126:
	.size	_Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j, .Lfunc_end126-_Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj128ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end127:
	.size	_Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j, .Lfunc_end127-_Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj64ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end128:
	.size	_Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j, .Lfunc_end128-_Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj32ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end129:
	.size	_Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j, .Lfunc_end129-_Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj16ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end130:
	.size	_Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j, .Lfunc_end130-_Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj8ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end131:
	.size	_Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j, .Lfunc_end131-_Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj4ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end132:
	.size	_Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j, .Lfunc_end132-_Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj2ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end133:
	.size	_Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j, .Lfunc_end133-_Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j,comdat
	.weak	_Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j # -- Begin function _Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j
	.type	_Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j,@function
_Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j: # @_Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce6IdLj1ELb0EEvPT_S1_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end134:
	.size	_Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j, .Lfunc_end134-_Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB135_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB135_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce0IiEvPT_S1_j, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce1IiEvPT_S1_j, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce2IiEvPT_S1_j, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce3IiEvPT_S1_j, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj512EEvPT_S1_j, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj256EEvPT_S1_j, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj128EEvPT_S1_j, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj64EEvPT_S1_j, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj32EEvPT_S1_j, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj16EEvPT_S1_j, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj8EEvPT_S1_j, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj4EEvPT_S1_j, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj2EEvPT_S1_j, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IiLj1EEvPT_S1_j, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj512EEvPT_S1_j, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj256EEvPT_S1_j, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj128EEvPT_S1_j, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj64EEvPT_S1_j, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj32EEvPT_S1_j, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj16EEvPT_S1_j, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj8EEvPT_S1_j, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj4EEvPT_S1_j, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj2EEvPT_S1_j, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce5IiLj1EEvPT_S1_j, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj512ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_25, %edx
	movl	$.L__unnamed_25, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj256ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_26, %edx
	movl	$.L__unnamed_26, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj128ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_27, %edx
	movl	$.L__unnamed_27, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj64ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_28, %edx
	movl	$.L__unnamed_28, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj32ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_29, %edx
	movl	$.L__unnamed_29, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj16ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_30, %edx
	movl	$.L__unnamed_30, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj8ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_31, %edx
	movl	$.L__unnamed_31, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj4ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_32, %edx
	movl	$.L__unnamed_32, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj2ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_33, %edx
	movl	$.L__unnamed_33, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj1ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_34, %edx
	movl	$.L__unnamed_34, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj512ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_35, %edx
	movl	$.L__unnamed_35, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj256ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_36, %edx
	movl	$.L__unnamed_36, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj128ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_37, %edx
	movl	$.L__unnamed_37, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj64ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_38, %edx
	movl	$.L__unnamed_38, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj32ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_39, %edx
	movl	$.L__unnamed_39, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj16ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_40, %edx
	movl	$.L__unnamed_40, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj8ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_41, %edx
	movl	$.L__unnamed_41, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj4ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_42, %edx
	movl	$.L__unnamed_42, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj2ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_43, %edx
	movl	$.L__unnamed_43, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce6IiLj1ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_44, %edx
	movl	$.L__unnamed_44, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce0IfEvPT_S1_j, %esi
	movl	$.L__unnamed_45, %edx
	movl	$.L__unnamed_45, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce1IfEvPT_S1_j, %esi
	movl	$.L__unnamed_46, %edx
	movl	$.L__unnamed_46, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce2IfEvPT_S1_j, %esi
	movl	$.L__unnamed_47, %edx
	movl	$.L__unnamed_47, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce3IfEvPT_S1_j, %esi
	movl	$.L__unnamed_48, %edx
	movl	$.L__unnamed_48, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IfLj512EEvPT_S1_j, %esi
	movl	$.L__unnamed_49, %edx
	movl	$.L__unnamed_49, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IfLj256EEvPT_S1_j, %esi
	movl	$.L__unnamed_50, %edx
	movl	$.L__unnamed_50, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IfLj128EEvPT_S1_j, %esi
	movl	$.L__unnamed_51, %edx
	movl	$.L__unnamed_51, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce4IfLj64EEvPT_S1_j, %esi
	movl	$.L__unnamed_52, %edx
	movl	$.L__unnamed_52, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IfLj32EEvPT_S1_j, %esi
	movl	$.L__unnamed_53, %edx
	movl	$.L__unnamed_53, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IfLj16EEvPT_S1_j, %esi
	movl	$.L__unnamed_54, %edx
	movl	$.L__unnamed_54, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IfLj8EEvPT_S1_j, %esi
	movl	$.L__unnamed_55, %edx
	movl	$.L__unnamed_55, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IfLj4EEvPT_S1_j, %esi
	movl	$.L__unnamed_56, %edx
	movl	$.L__unnamed_56, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IfLj2EEvPT_S1_j, %esi
	movl	$.L__unnamed_57, %edx
	movl	$.L__unnamed_57, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IfLj1EEvPT_S1_j, %esi
	movl	$.L__unnamed_58, %edx
	movl	$.L__unnamed_58, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj512EEvPT_S1_j, %esi
	movl	$.L__unnamed_59, %edx
	movl	$.L__unnamed_59, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj256EEvPT_S1_j, %esi
	movl	$.L__unnamed_60, %edx
	movl	$.L__unnamed_60, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj128EEvPT_S1_j, %esi
	movl	$.L__unnamed_61, %edx
	movl	$.L__unnamed_61, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj64EEvPT_S1_j, %esi
	movl	$.L__unnamed_62, %edx
	movl	$.L__unnamed_62, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj32EEvPT_S1_j, %esi
	movl	$.L__unnamed_63, %edx
	movl	$.L__unnamed_63, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj16EEvPT_S1_j, %esi
	movl	$.L__unnamed_64, %edx
	movl	$.L__unnamed_64, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj8EEvPT_S1_j, %esi
	movl	$.L__unnamed_65, %edx
	movl	$.L__unnamed_65, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj4EEvPT_S1_j, %esi
	movl	$.L__unnamed_66, %edx
	movl	$.L__unnamed_66, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj2EEvPT_S1_j, %esi
	movl	$.L__unnamed_67, %edx
	movl	$.L__unnamed_67, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IfLj1EEvPT_S1_j, %esi
	movl	$.L__unnamed_68, %edx
	movl	$.L__unnamed_68, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj512ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_69, %edx
	movl	$.L__unnamed_69, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj256ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_70, %edx
	movl	$.L__unnamed_70, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj128ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_71, %edx
	movl	$.L__unnamed_71, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj64ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_72, %edx
	movl	$.L__unnamed_72, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj32ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_73, %edx
	movl	$.L__unnamed_73, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj16ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_74, %edx
	movl	$.L__unnamed_74, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj8ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_75, %edx
	movl	$.L__unnamed_75, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj4ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_76, %edx
	movl	$.L__unnamed_76, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj2ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_77, %edx
	movl	$.L__unnamed_77, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj1ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_78, %edx
	movl	$.L__unnamed_78, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj512ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_79, %edx
	movl	$.L__unnamed_79, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj256ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_80, %edx
	movl	$.L__unnamed_80, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj128ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_81, %edx
	movl	$.L__unnamed_81, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj64ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_82, %edx
	movl	$.L__unnamed_82, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj32ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_83, %edx
	movl	$.L__unnamed_83, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj16ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_84, %edx
	movl	$.L__unnamed_84, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj8ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_85, %edx
	movl	$.L__unnamed_85, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj4ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_86, %edx
	movl	$.L__unnamed_86, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj2ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_87, %edx
	movl	$.L__unnamed_87, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IfLj1ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_88, %edx
	movl	$.L__unnamed_88, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce0IdEvPT_S1_j, %esi
	movl	$.L__unnamed_89, %edx
	movl	$.L__unnamed_89, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce1IdEvPT_S1_j, %esi
	movl	$.L__unnamed_90, %edx
	movl	$.L__unnamed_90, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce2IdEvPT_S1_j, %esi
	movl	$.L__unnamed_91, %edx
	movl	$.L__unnamed_91, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce3IdEvPT_S1_j, %esi
	movl	$.L__unnamed_92, %edx
	movl	$.L__unnamed_92, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj512EEvPT_S1_j, %esi
	movl	$.L__unnamed_93, %edx
	movl	$.L__unnamed_93, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj256EEvPT_S1_j, %esi
	movl	$.L__unnamed_94, %edx
	movl	$.L__unnamed_94, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj128EEvPT_S1_j, %esi
	movl	$.L__unnamed_95, %edx
	movl	$.L__unnamed_95, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj64EEvPT_S1_j, %esi
	movl	$.L__unnamed_96, %edx
	movl	$.L__unnamed_96, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj32EEvPT_S1_j, %esi
	movl	$.L__unnamed_97, %edx
	movl	$.L__unnamed_97, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj16EEvPT_S1_j, %esi
	movl	$.L__unnamed_98, %edx
	movl	$.L__unnamed_98, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj8EEvPT_S1_j, %esi
	movl	$.L__unnamed_99, %edx
	movl	$.L__unnamed_99, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj4EEvPT_S1_j, %esi
	movl	$.L__unnamed_100, %edx
	movl	$.L__unnamed_100, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj2EEvPT_S1_j, %esi
	movl	$.L__unnamed_101, %edx
	movl	$.L__unnamed_101, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce4IdLj1EEvPT_S1_j, %esi
	movl	$.L__unnamed_102, %edx
	movl	$.L__unnamed_102, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj512EEvPT_S1_j, %esi
	movl	$.L__unnamed_103, %edx
	movl	$.L__unnamed_103, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj256EEvPT_S1_j, %esi
	movl	$.L__unnamed_104, %edx
	movl	$.L__unnamed_104, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj128EEvPT_S1_j, %esi
	movl	$.L__unnamed_105, %edx
	movl	$.L__unnamed_105, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj64EEvPT_S1_j, %esi
	movl	$.L__unnamed_106, %edx
	movl	$.L__unnamed_106, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj32EEvPT_S1_j, %esi
	movl	$.L__unnamed_107, %edx
	movl	$.L__unnamed_107, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj16EEvPT_S1_j, %esi
	movl	$.L__unnamed_108, %edx
	movl	$.L__unnamed_108, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj8EEvPT_S1_j, %esi
	movl	$.L__unnamed_109, %edx
	movl	$.L__unnamed_109, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj4EEvPT_S1_j, %esi
	movl	$.L__unnamed_110, %edx
	movl	$.L__unnamed_110, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj2EEvPT_S1_j, %esi
	movl	$.L__unnamed_111, %edx
	movl	$.L__unnamed_111, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce5IdLj1EEvPT_S1_j, %esi
	movl	$.L__unnamed_112, %edx
	movl	$.L__unnamed_112, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj512ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_113, %edx
	movl	$.L__unnamed_113, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj256ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_114, %edx
	movl	$.L__unnamed_114, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj128ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_115, %edx
	movl	$.L__unnamed_115, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj64ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_116, %edx
	movl	$.L__unnamed_116, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj32ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_117, %edx
	movl	$.L__unnamed_117, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj16ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_118, %edx
	movl	$.L__unnamed_118, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj8ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_119, %edx
	movl	$.L__unnamed_119, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj4ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_120, %edx
	movl	$.L__unnamed_120, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj2ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_121, %edx
	movl	$.L__unnamed_121, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj1ELb1EEvPT_S1_j, %esi
	movl	$.L__unnamed_122, %edx
	movl	$.L__unnamed_122, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj512ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_123, %edx
	movl	$.L__unnamed_123, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj256ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_124, %edx
	movl	$.L__unnamed_124, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj128ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_125, %edx
	movl	$.L__unnamed_125, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj64ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_126, %edx
	movl	$.L__unnamed_126, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj32ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_127, %edx
	movl	$.L__unnamed_127, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj16ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_128, %edx
	movl	$.L__unnamed_128, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj8ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_129, %edx
	movl	$.L__unnamed_129, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj4ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_130, %edx
	movl	$.L__unnamed_130, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj2ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_131, %edx
	movl	$.L__unnamed_131, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$_Z7reduce6IdLj1ELb0EEvPT_S1_j, %esi
	movl	$.L__unnamed_132, %edx
	movl	$.L__unnamed_132, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$0
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end135:
	.size	__hip_module_ctor, .Lfunc_end135-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB136_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB136_2:
	retq
.Lfunc_end136:
	.size	__hip_module_dtor, .Lfunc_end136-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7reduce0IiEvPT_S1_j,@object   # @_Z7reduce0IiEvPT_S1_j
	.section	.rodata._Z7reduce0IiEvPT_S1_j,"aG",@progbits,_Z7reduce0IiEvPT_S1_j,comdat
	.weak	_Z7reduce0IiEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce0IiEvPT_S1_j:
	.quad	_Z22__device_stub__reduce0IiEvPT_S1_j
	.size	_Z7reduce0IiEvPT_S1_j, 8

	.type	_Z7reduce1IiEvPT_S1_j,@object   # @_Z7reduce1IiEvPT_S1_j
	.section	.rodata._Z7reduce1IiEvPT_S1_j,"aG",@progbits,_Z7reduce1IiEvPT_S1_j,comdat
	.weak	_Z7reduce1IiEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce1IiEvPT_S1_j:
	.quad	_Z22__device_stub__reduce1IiEvPT_S1_j
	.size	_Z7reduce1IiEvPT_S1_j, 8

	.type	_Z7reduce2IiEvPT_S1_j,@object   # @_Z7reduce2IiEvPT_S1_j
	.section	.rodata._Z7reduce2IiEvPT_S1_j,"aG",@progbits,_Z7reduce2IiEvPT_S1_j,comdat
	.weak	_Z7reduce2IiEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce2IiEvPT_S1_j:
	.quad	_Z22__device_stub__reduce2IiEvPT_S1_j
	.size	_Z7reduce2IiEvPT_S1_j, 8

	.type	_Z7reduce3IiEvPT_S1_j,@object   # @_Z7reduce3IiEvPT_S1_j
	.section	.rodata._Z7reduce3IiEvPT_S1_j,"aG",@progbits,_Z7reduce3IiEvPT_S1_j,comdat
	.weak	_Z7reduce3IiEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce3IiEvPT_S1_j:
	.quad	_Z22__device_stub__reduce3IiEvPT_S1_j
	.size	_Z7reduce3IiEvPT_S1_j, 8

	.type	_Z7reduce4IiLj512EEvPT_S1_j,@object # @_Z7reduce4IiLj512EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj512EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj512EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj512EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj512EEvPT_S1_j
	.size	_Z7reduce4IiLj512EEvPT_S1_j, 8

	.type	_Z7reduce4IiLj256EEvPT_S1_j,@object # @_Z7reduce4IiLj256EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj256EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj256EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj256EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj256EEvPT_S1_j
	.size	_Z7reduce4IiLj256EEvPT_S1_j, 8

	.type	_Z7reduce4IiLj128EEvPT_S1_j,@object # @_Z7reduce4IiLj128EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj128EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj128EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj128EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj128EEvPT_S1_j
	.size	_Z7reduce4IiLj128EEvPT_S1_j, 8

	.type	_Z7reduce4IiLj64EEvPT_S1_j,@object # @_Z7reduce4IiLj64EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj64EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj64EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj64EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj64EEvPT_S1_j
	.size	_Z7reduce4IiLj64EEvPT_S1_j, 8

	.type	_Z7reduce4IiLj32EEvPT_S1_j,@object # @_Z7reduce4IiLj32EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj32EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj32EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj32EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj32EEvPT_S1_j
	.size	_Z7reduce4IiLj32EEvPT_S1_j, 8

	.type	_Z7reduce4IiLj16EEvPT_S1_j,@object # @_Z7reduce4IiLj16EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj16EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj16EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj16EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj16EEvPT_S1_j
	.size	_Z7reduce4IiLj16EEvPT_S1_j, 8

	.type	_Z7reduce4IiLj8EEvPT_S1_j,@object # @_Z7reduce4IiLj8EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj8EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj8EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj8EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj8EEvPT_S1_j
	.size	_Z7reduce4IiLj8EEvPT_S1_j, 8

	.type	_Z7reduce4IiLj4EEvPT_S1_j,@object # @_Z7reduce4IiLj4EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj4EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj4EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj4EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj4EEvPT_S1_j
	.size	_Z7reduce4IiLj4EEvPT_S1_j, 8

	.type	_Z7reduce4IiLj2EEvPT_S1_j,@object # @_Z7reduce4IiLj2EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj2EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj2EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj2EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj2EEvPT_S1_j
	.size	_Z7reduce4IiLj2EEvPT_S1_j, 8

	.type	_Z7reduce4IiLj1EEvPT_S1_j,@object # @_Z7reduce4IiLj1EEvPT_S1_j
	.section	.rodata._Z7reduce4IiLj1EEvPT_S1_j,"aG",@progbits,_Z7reduce4IiLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce4IiLj1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IiLj1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IiLj1EEvPT_S1_j
	.size	_Z7reduce4IiLj1EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj512EEvPT_S1_j,@object # @_Z7reduce5IiLj512EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj512EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj512EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj512EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj512EEvPT_S1_j
	.size	_Z7reduce5IiLj512EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj256EEvPT_S1_j,@object # @_Z7reduce5IiLj256EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj256EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj256EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj256EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj256EEvPT_S1_j
	.size	_Z7reduce5IiLj256EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj128EEvPT_S1_j,@object # @_Z7reduce5IiLj128EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj128EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj128EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj128EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj128EEvPT_S1_j
	.size	_Z7reduce5IiLj128EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj64EEvPT_S1_j,@object # @_Z7reduce5IiLj64EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj64EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj64EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj64EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj64EEvPT_S1_j
	.size	_Z7reduce5IiLj64EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj32EEvPT_S1_j,@object # @_Z7reduce5IiLj32EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj32EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj32EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj32EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj32EEvPT_S1_j
	.size	_Z7reduce5IiLj32EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj16EEvPT_S1_j,@object # @_Z7reduce5IiLj16EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj16EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj16EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj16EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj16EEvPT_S1_j
	.size	_Z7reduce5IiLj16EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj8EEvPT_S1_j,@object # @_Z7reduce5IiLj8EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj8EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj8EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj8EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj8EEvPT_S1_j
	.size	_Z7reduce5IiLj8EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj4EEvPT_S1_j,@object # @_Z7reduce5IiLj4EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj4EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj4EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj4EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj4EEvPT_S1_j
	.size	_Z7reduce5IiLj4EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj2EEvPT_S1_j,@object # @_Z7reduce5IiLj2EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj2EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj2EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj2EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj2EEvPT_S1_j
	.size	_Z7reduce5IiLj2EEvPT_S1_j, 8

	.type	_Z7reduce5IiLj1EEvPT_S1_j,@object # @_Z7reduce5IiLj1EEvPT_S1_j
	.section	.rodata._Z7reduce5IiLj1EEvPT_S1_j,"aG",@progbits,_Z7reduce5IiLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce5IiLj1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IiLj1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IiLj1EEvPT_S1_j
	.size	_Z7reduce5IiLj1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj512ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj512ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj512ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj512ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj512ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj512ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj512ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj256ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj256ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj256ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj256ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj256ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj256ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj256ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj128ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj128ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj128ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj128ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj128ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj128ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj128ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj64ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj64ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj64ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj64ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj64ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj64ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj64ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj32ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj32ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj32ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj32ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj32ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj32ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj32ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj16ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj16ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj16ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj16ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj16ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj16ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj16ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj8ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj8ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj8ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj8ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj8ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj8ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj8ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj4ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj4ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj4ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj4ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj4ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj4ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj4ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj2ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj2ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj2ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj2ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj2ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj2ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj2ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj1ELb1EEvPT_S1_j,@object # @_Z7reduce6IiLj1ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj1ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj1ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj1ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj1ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j
	.size	_Z7reduce6IiLj1ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj512ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj512ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj512ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj512ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj512ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj512ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj512ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj256ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj256ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj256ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj256ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj256ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj256ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj256ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj128ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj128ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj128ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj128ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj128ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj128ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj128ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj64ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj64ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj64ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj64ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj64ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj64ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj64ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj32ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj32ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj32ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj32ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj32ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj32ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj32ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj16ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj16ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj16ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj16ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj16ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj16ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj16ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj8ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj8ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj8ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj8ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj8ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj8ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj8ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj4ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj4ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj4ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj4ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj4ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj4ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj4ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj2ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj2ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj2ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj2ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj2ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj2ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj2ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IiLj1ELb0EEvPT_S1_j,@object # @_Z7reduce6IiLj1ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IiLj1ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IiLj1ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IiLj1ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IiLj1ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j
	.size	_Z7reduce6IiLj1ELb0EEvPT_S1_j, 8

	.type	_Z7reduce0IfEvPT_S1_j,@object   # @_Z7reduce0IfEvPT_S1_j
	.section	.rodata._Z7reduce0IfEvPT_S1_j,"aG",@progbits,_Z7reduce0IfEvPT_S1_j,comdat
	.weak	_Z7reduce0IfEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce0IfEvPT_S1_j:
	.quad	_Z22__device_stub__reduce0IfEvPT_S1_j
	.size	_Z7reduce0IfEvPT_S1_j, 8

	.type	_Z7reduce1IfEvPT_S1_j,@object   # @_Z7reduce1IfEvPT_S1_j
	.section	.rodata._Z7reduce1IfEvPT_S1_j,"aG",@progbits,_Z7reduce1IfEvPT_S1_j,comdat
	.weak	_Z7reduce1IfEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce1IfEvPT_S1_j:
	.quad	_Z22__device_stub__reduce1IfEvPT_S1_j
	.size	_Z7reduce1IfEvPT_S1_j, 8

	.type	_Z7reduce2IfEvPT_S1_j,@object   # @_Z7reduce2IfEvPT_S1_j
	.section	.rodata._Z7reduce2IfEvPT_S1_j,"aG",@progbits,_Z7reduce2IfEvPT_S1_j,comdat
	.weak	_Z7reduce2IfEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce2IfEvPT_S1_j:
	.quad	_Z22__device_stub__reduce2IfEvPT_S1_j
	.size	_Z7reduce2IfEvPT_S1_j, 8

	.type	_Z7reduce3IfEvPT_S1_j,@object   # @_Z7reduce3IfEvPT_S1_j
	.section	.rodata._Z7reduce3IfEvPT_S1_j,"aG",@progbits,_Z7reduce3IfEvPT_S1_j,comdat
	.weak	_Z7reduce3IfEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce3IfEvPT_S1_j:
	.quad	_Z22__device_stub__reduce3IfEvPT_S1_j
	.size	_Z7reduce3IfEvPT_S1_j, 8

	.type	_Z7reduce4IfLj512EEvPT_S1_j,@object # @_Z7reduce4IfLj512EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj512EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj512EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj512EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj512EEvPT_S1_j
	.size	_Z7reduce4IfLj512EEvPT_S1_j, 8

	.type	_Z7reduce4IfLj256EEvPT_S1_j,@object # @_Z7reduce4IfLj256EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj256EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj256EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj256EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj256EEvPT_S1_j
	.size	_Z7reduce4IfLj256EEvPT_S1_j, 8

	.type	_Z7reduce4IfLj128EEvPT_S1_j,@object # @_Z7reduce4IfLj128EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj128EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj128EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj128EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj128EEvPT_S1_j
	.size	_Z7reduce4IfLj128EEvPT_S1_j, 8

	.type	_Z7reduce4IfLj64EEvPT_S1_j,@object # @_Z7reduce4IfLj64EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj64EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj64EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj64EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj64EEvPT_S1_j
	.size	_Z7reduce4IfLj64EEvPT_S1_j, 8

	.type	_Z7reduce4IfLj32EEvPT_S1_j,@object # @_Z7reduce4IfLj32EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj32EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj32EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj32EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj32EEvPT_S1_j
	.size	_Z7reduce4IfLj32EEvPT_S1_j, 8

	.type	_Z7reduce4IfLj16EEvPT_S1_j,@object # @_Z7reduce4IfLj16EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj16EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj16EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj16EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj16EEvPT_S1_j
	.size	_Z7reduce4IfLj16EEvPT_S1_j, 8

	.type	_Z7reduce4IfLj8EEvPT_S1_j,@object # @_Z7reduce4IfLj8EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj8EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj8EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj8EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj8EEvPT_S1_j
	.size	_Z7reduce4IfLj8EEvPT_S1_j, 8

	.type	_Z7reduce4IfLj4EEvPT_S1_j,@object # @_Z7reduce4IfLj4EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj4EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj4EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj4EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj4EEvPT_S1_j
	.size	_Z7reduce4IfLj4EEvPT_S1_j, 8

	.type	_Z7reduce4IfLj2EEvPT_S1_j,@object # @_Z7reduce4IfLj2EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj2EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj2EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj2EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj2EEvPT_S1_j
	.size	_Z7reduce4IfLj2EEvPT_S1_j, 8

	.type	_Z7reduce4IfLj1EEvPT_S1_j,@object # @_Z7reduce4IfLj1EEvPT_S1_j
	.section	.rodata._Z7reduce4IfLj1EEvPT_S1_j,"aG",@progbits,_Z7reduce4IfLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce4IfLj1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IfLj1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IfLj1EEvPT_S1_j
	.size	_Z7reduce4IfLj1EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj512EEvPT_S1_j,@object # @_Z7reduce5IfLj512EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj512EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj512EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj512EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj512EEvPT_S1_j
	.size	_Z7reduce5IfLj512EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj256EEvPT_S1_j,@object # @_Z7reduce5IfLj256EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj256EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj256EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj256EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj256EEvPT_S1_j
	.size	_Z7reduce5IfLj256EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj128EEvPT_S1_j,@object # @_Z7reduce5IfLj128EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj128EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj128EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj128EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj128EEvPT_S1_j
	.size	_Z7reduce5IfLj128EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj64EEvPT_S1_j,@object # @_Z7reduce5IfLj64EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj64EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj64EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj64EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj64EEvPT_S1_j
	.size	_Z7reduce5IfLj64EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj32EEvPT_S1_j,@object # @_Z7reduce5IfLj32EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj32EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj32EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj32EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj32EEvPT_S1_j
	.size	_Z7reduce5IfLj32EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj16EEvPT_S1_j,@object # @_Z7reduce5IfLj16EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj16EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj16EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj16EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj16EEvPT_S1_j
	.size	_Z7reduce5IfLj16EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj8EEvPT_S1_j,@object # @_Z7reduce5IfLj8EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj8EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj8EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj8EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj8EEvPT_S1_j
	.size	_Z7reduce5IfLj8EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj4EEvPT_S1_j,@object # @_Z7reduce5IfLj4EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj4EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj4EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj4EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj4EEvPT_S1_j
	.size	_Z7reduce5IfLj4EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj2EEvPT_S1_j,@object # @_Z7reduce5IfLj2EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj2EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj2EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj2EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj2EEvPT_S1_j
	.size	_Z7reduce5IfLj2EEvPT_S1_j, 8

	.type	_Z7reduce5IfLj1EEvPT_S1_j,@object # @_Z7reduce5IfLj1EEvPT_S1_j
	.section	.rodata._Z7reduce5IfLj1EEvPT_S1_j,"aG",@progbits,_Z7reduce5IfLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce5IfLj1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IfLj1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IfLj1EEvPT_S1_j
	.size	_Z7reduce5IfLj1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj512ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj512ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj512ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj512ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj512ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj512ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj512ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj256ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj256ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj256ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj256ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj256ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj256ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj256ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj128ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj128ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj128ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj128ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj128ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj128ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj128ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj64ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj64ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj64ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj64ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj64ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj64ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj64ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj32ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj32ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj32ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj32ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj32ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj32ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj32ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj16ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj16ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj16ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj16ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj16ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj16ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj16ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj8ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj8ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj8ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj8ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj8ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj8ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj8ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj4ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj4ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj4ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj4ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj4ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj4ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj4ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj2ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj2ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj2ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj2ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj2ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj2ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj2ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj1ELb1EEvPT_S1_j,@object # @_Z7reduce6IfLj1ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj1ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj1ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj1ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj1ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j
	.size	_Z7reduce6IfLj1ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj512ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj512ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj512ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj512ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj512ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj512ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj512ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj256ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj256ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj256ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj256ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj256ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj256ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj256ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj128ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj128ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj128ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj128ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj128ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj128ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj128ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj64ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj64ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj64ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj64ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj64ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj64ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj64ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj32ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj32ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj32ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj32ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj32ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj32ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj32ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj16ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj16ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj16ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj16ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj16ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj16ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj16ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj8ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj8ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj8ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj8ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj8ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj8ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj8ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj4ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj4ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj4ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj4ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj4ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj4ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj4ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj2ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj2ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj2ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj2ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj2ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj2ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj2ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IfLj1ELb0EEvPT_S1_j,@object # @_Z7reduce6IfLj1ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IfLj1ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IfLj1ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IfLj1ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IfLj1ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j
	.size	_Z7reduce6IfLj1ELb0EEvPT_S1_j, 8

	.type	_Z7reduce0IdEvPT_S1_j,@object   # @_Z7reduce0IdEvPT_S1_j
	.section	.rodata._Z7reduce0IdEvPT_S1_j,"aG",@progbits,_Z7reduce0IdEvPT_S1_j,comdat
	.weak	_Z7reduce0IdEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce0IdEvPT_S1_j:
	.quad	_Z22__device_stub__reduce0IdEvPT_S1_j
	.size	_Z7reduce0IdEvPT_S1_j, 8

	.type	_Z7reduce1IdEvPT_S1_j,@object   # @_Z7reduce1IdEvPT_S1_j
	.section	.rodata._Z7reduce1IdEvPT_S1_j,"aG",@progbits,_Z7reduce1IdEvPT_S1_j,comdat
	.weak	_Z7reduce1IdEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce1IdEvPT_S1_j:
	.quad	_Z22__device_stub__reduce1IdEvPT_S1_j
	.size	_Z7reduce1IdEvPT_S1_j, 8

	.type	_Z7reduce2IdEvPT_S1_j,@object   # @_Z7reduce2IdEvPT_S1_j
	.section	.rodata._Z7reduce2IdEvPT_S1_j,"aG",@progbits,_Z7reduce2IdEvPT_S1_j,comdat
	.weak	_Z7reduce2IdEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce2IdEvPT_S1_j:
	.quad	_Z22__device_stub__reduce2IdEvPT_S1_j
	.size	_Z7reduce2IdEvPT_S1_j, 8

	.type	_Z7reduce3IdEvPT_S1_j,@object   # @_Z7reduce3IdEvPT_S1_j
	.section	.rodata._Z7reduce3IdEvPT_S1_j,"aG",@progbits,_Z7reduce3IdEvPT_S1_j,comdat
	.weak	_Z7reduce3IdEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce3IdEvPT_S1_j:
	.quad	_Z22__device_stub__reduce3IdEvPT_S1_j
	.size	_Z7reduce3IdEvPT_S1_j, 8

	.type	_Z7reduce4IdLj512EEvPT_S1_j,@object # @_Z7reduce4IdLj512EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj512EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj512EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj512EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj512EEvPT_S1_j
	.size	_Z7reduce4IdLj512EEvPT_S1_j, 8

	.type	_Z7reduce4IdLj256EEvPT_S1_j,@object # @_Z7reduce4IdLj256EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj256EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj256EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj256EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj256EEvPT_S1_j
	.size	_Z7reduce4IdLj256EEvPT_S1_j, 8

	.type	_Z7reduce4IdLj128EEvPT_S1_j,@object # @_Z7reduce4IdLj128EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj128EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj128EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj128EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj128EEvPT_S1_j
	.size	_Z7reduce4IdLj128EEvPT_S1_j, 8

	.type	_Z7reduce4IdLj64EEvPT_S1_j,@object # @_Z7reduce4IdLj64EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj64EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj64EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj64EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj64EEvPT_S1_j
	.size	_Z7reduce4IdLj64EEvPT_S1_j, 8

	.type	_Z7reduce4IdLj32EEvPT_S1_j,@object # @_Z7reduce4IdLj32EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj32EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj32EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj32EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj32EEvPT_S1_j
	.size	_Z7reduce4IdLj32EEvPT_S1_j, 8

	.type	_Z7reduce4IdLj16EEvPT_S1_j,@object # @_Z7reduce4IdLj16EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj16EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj16EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj16EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj16EEvPT_S1_j
	.size	_Z7reduce4IdLj16EEvPT_S1_j, 8

	.type	_Z7reduce4IdLj8EEvPT_S1_j,@object # @_Z7reduce4IdLj8EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj8EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj8EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj8EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj8EEvPT_S1_j
	.size	_Z7reduce4IdLj8EEvPT_S1_j, 8

	.type	_Z7reduce4IdLj4EEvPT_S1_j,@object # @_Z7reduce4IdLj4EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj4EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj4EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj4EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj4EEvPT_S1_j
	.size	_Z7reduce4IdLj4EEvPT_S1_j, 8

	.type	_Z7reduce4IdLj2EEvPT_S1_j,@object # @_Z7reduce4IdLj2EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj2EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj2EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj2EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj2EEvPT_S1_j
	.size	_Z7reduce4IdLj2EEvPT_S1_j, 8

	.type	_Z7reduce4IdLj1EEvPT_S1_j,@object # @_Z7reduce4IdLj1EEvPT_S1_j
	.section	.rodata._Z7reduce4IdLj1EEvPT_S1_j,"aG",@progbits,_Z7reduce4IdLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce4IdLj1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce4IdLj1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce4IdLj1EEvPT_S1_j
	.size	_Z7reduce4IdLj1EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj512EEvPT_S1_j,@object # @_Z7reduce5IdLj512EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj512EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj512EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj512EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj512EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj512EEvPT_S1_j
	.size	_Z7reduce5IdLj512EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj256EEvPT_S1_j,@object # @_Z7reduce5IdLj256EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj256EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj256EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj256EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj256EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj256EEvPT_S1_j
	.size	_Z7reduce5IdLj256EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj128EEvPT_S1_j,@object # @_Z7reduce5IdLj128EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj128EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj128EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj128EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj128EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj128EEvPT_S1_j
	.size	_Z7reduce5IdLj128EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj64EEvPT_S1_j,@object # @_Z7reduce5IdLj64EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj64EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj64EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj64EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj64EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj64EEvPT_S1_j
	.size	_Z7reduce5IdLj64EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj32EEvPT_S1_j,@object # @_Z7reduce5IdLj32EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj32EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj32EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj32EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj32EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj32EEvPT_S1_j
	.size	_Z7reduce5IdLj32EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj16EEvPT_S1_j,@object # @_Z7reduce5IdLj16EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj16EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj16EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj16EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj16EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj16EEvPT_S1_j
	.size	_Z7reduce5IdLj16EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj8EEvPT_S1_j,@object # @_Z7reduce5IdLj8EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj8EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj8EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj8EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj8EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj8EEvPT_S1_j
	.size	_Z7reduce5IdLj8EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj4EEvPT_S1_j,@object # @_Z7reduce5IdLj4EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj4EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj4EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj4EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj4EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj4EEvPT_S1_j
	.size	_Z7reduce5IdLj4EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj2EEvPT_S1_j,@object # @_Z7reduce5IdLj2EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj2EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj2EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj2EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj2EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj2EEvPT_S1_j
	.size	_Z7reduce5IdLj2EEvPT_S1_j, 8

	.type	_Z7reduce5IdLj1EEvPT_S1_j,@object # @_Z7reduce5IdLj1EEvPT_S1_j
	.section	.rodata._Z7reduce5IdLj1EEvPT_S1_j,"aG",@progbits,_Z7reduce5IdLj1EEvPT_S1_j,comdat
	.weak	_Z7reduce5IdLj1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce5IdLj1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce5IdLj1EEvPT_S1_j
	.size	_Z7reduce5IdLj1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj512ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj512ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj512ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj512ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj512ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj512ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj512ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj256ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj256ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj256ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj256ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj256ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj256ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj256ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj128ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj128ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj128ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj128ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj128ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj128ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj128ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj64ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj64ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj64ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj64ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj64ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj64ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj64ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj32ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj32ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj32ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj32ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj32ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj32ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj32ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj16ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj16ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj16ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj16ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj16ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj16ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj16ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj8ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj8ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj8ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj8ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj8ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj8ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj8ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj4ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj4ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj4ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj4ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj4ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj4ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj4ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj2ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj2ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj2ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj2ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj2ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj2ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj2ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj1ELb1EEvPT_S1_j,@object # @_Z7reduce6IdLj1ELb1EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj1ELb1EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj1ELb1EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj1ELb1EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj1ELb1EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j
	.size	_Z7reduce6IdLj1ELb1EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj512ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj512ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj512ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj512ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj512ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj512ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj512ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj256ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj256ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj256ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj256ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj256ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj256ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj256ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj128ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj128ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj128ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj128ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj128ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj128ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj128ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj64ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj64ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj64ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj64ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj64ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj64ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj64ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj32ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj32ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj32ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj32ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj32ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj32ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj32ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj16ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj16ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj16ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj16ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj16ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj16ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj16ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj8ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj8ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj8ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj8ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj8ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj8ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj8ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj4ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj4ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj4ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj4ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj4ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj4ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj4ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj2ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj2ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj2ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj2ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj2ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj2ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj2ELb0EEvPT_S1_j, 8

	.type	_Z7reduce6IdLj1ELb0EEvPT_S1_j,@object # @_Z7reduce6IdLj1ELb0EEvPT_S1_j
	.section	.rodata._Z7reduce6IdLj1ELb0EEvPT_S1_j,"aG",@progbits,_Z7reduce6IdLj1ELb0EEvPT_S1_j,comdat
	.weak	_Z7reduce6IdLj1ELb0EEvPT_S1_j
	.p2align	3, 0x0
_Z7reduce6IdLj1ELb0EEvPT_S1_j:
	.quad	_Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j
	.size	_Z7reduce6IdLj1ELb0EEvPT_S1_j, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7reduce0IiEvPT_S1_j"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7reduce1IiEvPT_S1_j"
	.size	.L__unnamed_2, 22

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7reduce2IiEvPT_S1_j"
	.size	.L__unnamed_3, 22

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z7reduce3IiEvPT_S1_j"
	.size	.L__unnamed_4, 22

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z7reduce4IiLj512EEvPT_S1_j"
	.size	.L__unnamed_5, 28

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z7reduce4IiLj256EEvPT_S1_j"
	.size	.L__unnamed_6, 28

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z7reduce4IiLj128EEvPT_S1_j"
	.size	.L__unnamed_7, 28

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z7reduce4IiLj64EEvPT_S1_j"
	.size	.L__unnamed_8, 27

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z7reduce4IiLj32EEvPT_S1_j"
	.size	.L__unnamed_9, 27

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z7reduce4IiLj16EEvPT_S1_j"
	.size	.L__unnamed_10, 27

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z7reduce4IiLj8EEvPT_S1_j"
	.size	.L__unnamed_11, 26

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_Z7reduce4IiLj4EEvPT_S1_j"
	.size	.L__unnamed_12, 26

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"_Z7reduce4IiLj2EEvPT_S1_j"
	.size	.L__unnamed_13, 26

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"_Z7reduce4IiLj1EEvPT_S1_j"
	.size	.L__unnamed_14, 26

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"_Z7reduce5IiLj512EEvPT_S1_j"
	.size	.L__unnamed_15, 28

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"_Z7reduce5IiLj256EEvPT_S1_j"
	.size	.L__unnamed_16, 28

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"_Z7reduce5IiLj128EEvPT_S1_j"
	.size	.L__unnamed_17, 28

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"_Z7reduce5IiLj64EEvPT_S1_j"
	.size	.L__unnamed_18, 27

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"_Z7reduce5IiLj32EEvPT_S1_j"
	.size	.L__unnamed_19, 27

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"_Z7reduce5IiLj16EEvPT_S1_j"
	.size	.L__unnamed_20, 27

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"_Z7reduce5IiLj8EEvPT_S1_j"
	.size	.L__unnamed_21, 26

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"_Z7reduce5IiLj4EEvPT_S1_j"
	.size	.L__unnamed_22, 26

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"_Z7reduce5IiLj2EEvPT_S1_j"
	.size	.L__unnamed_23, 26

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"_Z7reduce5IiLj1EEvPT_S1_j"
	.size	.L__unnamed_24, 26

	.type	.L__unnamed_25,@object          # @24
.L__unnamed_25:
	.asciz	"_Z7reduce6IiLj512ELb1EEvPT_S1_j"
	.size	.L__unnamed_25, 32

	.type	.L__unnamed_26,@object          # @25
.L__unnamed_26:
	.asciz	"_Z7reduce6IiLj256ELb1EEvPT_S1_j"
	.size	.L__unnamed_26, 32

	.type	.L__unnamed_27,@object          # @26
.L__unnamed_27:
	.asciz	"_Z7reduce6IiLj128ELb1EEvPT_S1_j"
	.size	.L__unnamed_27, 32

	.type	.L__unnamed_28,@object          # @27
.L__unnamed_28:
	.asciz	"_Z7reduce6IiLj64ELb1EEvPT_S1_j"
	.size	.L__unnamed_28, 31

	.type	.L__unnamed_29,@object          # @28
.L__unnamed_29:
	.asciz	"_Z7reduce6IiLj32ELb1EEvPT_S1_j"
	.size	.L__unnamed_29, 31

	.type	.L__unnamed_30,@object          # @29
.L__unnamed_30:
	.asciz	"_Z7reduce6IiLj16ELb1EEvPT_S1_j"
	.size	.L__unnamed_30, 31

	.type	.L__unnamed_31,@object          # @30
.L__unnamed_31:
	.asciz	"_Z7reduce6IiLj8ELb1EEvPT_S1_j"
	.size	.L__unnamed_31, 30

	.type	.L__unnamed_32,@object          # @31
.L__unnamed_32:
	.asciz	"_Z7reduce6IiLj4ELb1EEvPT_S1_j"
	.size	.L__unnamed_32, 30

	.type	.L__unnamed_33,@object          # @32
.L__unnamed_33:
	.asciz	"_Z7reduce6IiLj2ELb1EEvPT_S1_j"
	.size	.L__unnamed_33, 30

	.type	.L__unnamed_34,@object          # @33
.L__unnamed_34:
	.asciz	"_Z7reduce6IiLj1ELb1EEvPT_S1_j"
	.size	.L__unnamed_34, 30

	.type	.L__unnamed_35,@object          # @34
.L__unnamed_35:
	.asciz	"_Z7reduce6IiLj512ELb0EEvPT_S1_j"
	.size	.L__unnamed_35, 32

	.type	.L__unnamed_36,@object          # @35
.L__unnamed_36:
	.asciz	"_Z7reduce6IiLj256ELb0EEvPT_S1_j"
	.size	.L__unnamed_36, 32

	.type	.L__unnamed_37,@object          # @36
.L__unnamed_37:
	.asciz	"_Z7reduce6IiLj128ELb0EEvPT_S1_j"
	.size	.L__unnamed_37, 32

	.type	.L__unnamed_38,@object          # @37
.L__unnamed_38:
	.asciz	"_Z7reduce6IiLj64ELb0EEvPT_S1_j"
	.size	.L__unnamed_38, 31

	.type	.L__unnamed_39,@object          # @38
.L__unnamed_39:
	.asciz	"_Z7reduce6IiLj32ELb0EEvPT_S1_j"
	.size	.L__unnamed_39, 31

	.type	.L__unnamed_40,@object          # @39
.L__unnamed_40:
	.asciz	"_Z7reduce6IiLj16ELb0EEvPT_S1_j"
	.size	.L__unnamed_40, 31

	.type	.L__unnamed_41,@object          # @40
.L__unnamed_41:
	.asciz	"_Z7reduce6IiLj8ELb0EEvPT_S1_j"
	.size	.L__unnamed_41, 30

	.type	.L__unnamed_42,@object          # @41
.L__unnamed_42:
	.asciz	"_Z7reduce6IiLj4ELb0EEvPT_S1_j"
	.size	.L__unnamed_42, 30

	.type	.L__unnamed_43,@object          # @42
.L__unnamed_43:
	.asciz	"_Z7reduce6IiLj2ELb0EEvPT_S1_j"
	.size	.L__unnamed_43, 30

	.type	.L__unnamed_44,@object          # @43
.L__unnamed_44:
	.asciz	"_Z7reduce6IiLj1ELb0EEvPT_S1_j"
	.size	.L__unnamed_44, 30

	.type	.L__unnamed_45,@object          # @44
.L__unnamed_45:
	.asciz	"_Z7reduce0IfEvPT_S1_j"
	.size	.L__unnamed_45, 22

	.type	.L__unnamed_46,@object          # @45
.L__unnamed_46:
	.asciz	"_Z7reduce1IfEvPT_S1_j"
	.size	.L__unnamed_46, 22

	.type	.L__unnamed_47,@object          # @46
.L__unnamed_47:
	.asciz	"_Z7reduce2IfEvPT_S1_j"
	.size	.L__unnamed_47, 22

	.type	.L__unnamed_48,@object          # @47
.L__unnamed_48:
	.asciz	"_Z7reduce3IfEvPT_S1_j"
	.size	.L__unnamed_48, 22

	.type	.L__unnamed_49,@object          # @48
.L__unnamed_49:
	.asciz	"_Z7reduce4IfLj512EEvPT_S1_j"
	.size	.L__unnamed_49, 28

	.type	.L__unnamed_50,@object          # @49
.L__unnamed_50:
	.asciz	"_Z7reduce4IfLj256EEvPT_S1_j"
	.size	.L__unnamed_50, 28

	.type	.L__unnamed_51,@object          # @50
.L__unnamed_51:
	.asciz	"_Z7reduce4IfLj128EEvPT_S1_j"
	.size	.L__unnamed_51, 28

	.type	.L__unnamed_52,@object          # @51
.L__unnamed_52:
	.asciz	"_Z7reduce4IfLj64EEvPT_S1_j"
	.size	.L__unnamed_52, 27

	.type	.L__unnamed_53,@object          # @52
.L__unnamed_53:
	.asciz	"_Z7reduce4IfLj32EEvPT_S1_j"
	.size	.L__unnamed_53, 27

	.type	.L__unnamed_54,@object          # @53
.L__unnamed_54:
	.asciz	"_Z7reduce4IfLj16EEvPT_S1_j"
	.size	.L__unnamed_54, 27

	.type	.L__unnamed_55,@object          # @54
.L__unnamed_55:
	.asciz	"_Z7reduce4IfLj8EEvPT_S1_j"
	.size	.L__unnamed_55, 26

	.type	.L__unnamed_56,@object          # @55
.L__unnamed_56:
	.asciz	"_Z7reduce4IfLj4EEvPT_S1_j"
	.size	.L__unnamed_56, 26

	.type	.L__unnamed_57,@object          # @56
.L__unnamed_57:
	.asciz	"_Z7reduce4IfLj2EEvPT_S1_j"
	.size	.L__unnamed_57, 26

	.type	.L__unnamed_58,@object          # @57
.L__unnamed_58:
	.asciz	"_Z7reduce4IfLj1EEvPT_S1_j"
	.size	.L__unnamed_58, 26

	.type	.L__unnamed_59,@object          # @58
.L__unnamed_59:
	.asciz	"_Z7reduce5IfLj512EEvPT_S1_j"
	.size	.L__unnamed_59, 28

	.type	.L__unnamed_60,@object          # @59
.L__unnamed_60:
	.asciz	"_Z7reduce5IfLj256EEvPT_S1_j"
	.size	.L__unnamed_60, 28

	.type	.L__unnamed_61,@object          # @60
.L__unnamed_61:
	.asciz	"_Z7reduce5IfLj128EEvPT_S1_j"
	.size	.L__unnamed_61, 28

	.type	.L__unnamed_62,@object          # @61
.L__unnamed_62:
	.asciz	"_Z7reduce5IfLj64EEvPT_S1_j"
	.size	.L__unnamed_62, 27

	.type	.L__unnamed_63,@object          # @62
.L__unnamed_63:
	.asciz	"_Z7reduce5IfLj32EEvPT_S1_j"
	.size	.L__unnamed_63, 27

	.type	.L__unnamed_64,@object          # @63
.L__unnamed_64:
	.asciz	"_Z7reduce5IfLj16EEvPT_S1_j"
	.size	.L__unnamed_64, 27

	.type	.L__unnamed_65,@object          # @64
.L__unnamed_65:
	.asciz	"_Z7reduce5IfLj8EEvPT_S1_j"
	.size	.L__unnamed_65, 26

	.type	.L__unnamed_66,@object          # @65
.L__unnamed_66:
	.asciz	"_Z7reduce5IfLj4EEvPT_S1_j"
	.size	.L__unnamed_66, 26

	.type	.L__unnamed_67,@object          # @66
.L__unnamed_67:
	.asciz	"_Z7reduce5IfLj2EEvPT_S1_j"
	.size	.L__unnamed_67, 26

	.type	.L__unnamed_68,@object          # @67
.L__unnamed_68:
	.asciz	"_Z7reduce5IfLj1EEvPT_S1_j"
	.size	.L__unnamed_68, 26

	.type	.L__unnamed_69,@object          # @68
.L__unnamed_69:
	.asciz	"_Z7reduce6IfLj512ELb1EEvPT_S1_j"
	.size	.L__unnamed_69, 32

	.type	.L__unnamed_70,@object          # @69
.L__unnamed_70:
	.asciz	"_Z7reduce6IfLj256ELb1EEvPT_S1_j"
	.size	.L__unnamed_70, 32

	.type	.L__unnamed_71,@object          # @70
.L__unnamed_71:
	.asciz	"_Z7reduce6IfLj128ELb1EEvPT_S1_j"
	.size	.L__unnamed_71, 32

	.type	.L__unnamed_72,@object          # @71
.L__unnamed_72:
	.asciz	"_Z7reduce6IfLj64ELb1EEvPT_S1_j"
	.size	.L__unnamed_72, 31

	.type	.L__unnamed_73,@object          # @72
.L__unnamed_73:
	.asciz	"_Z7reduce6IfLj32ELb1EEvPT_S1_j"
	.size	.L__unnamed_73, 31

	.type	.L__unnamed_74,@object          # @73
.L__unnamed_74:
	.asciz	"_Z7reduce6IfLj16ELb1EEvPT_S1_j"
	.size	.L__unnamed_74, 31

	.type	.L__unnamed_75,@object          # @74
.L__unnamed_75:
	.asciz	"_Z7reduce6IfLj8ELb1EEvPT_S1_j"
	.size	.L__unnamed_75, 30

	.type	.L__unnamed_76,@object          # @75
.L__unnamed_76:
	.asciz	"_Z7reduce6IfLj4ELb1EEvPT_S1_j"
	.size	.L__unnamed_76, 30

	.type	.L__unnamed_77,@object          # @76
.L__unnamed_77:
	.asciz	"_Z7reduce6IfLj2ELb1EEvPT_S1_j"
	.size	.L__unnamed_77, 30

	.type	.L__unnamed_78,@object          # @77
.L__unnamed_78:
	.asciz	"_Z7reduce6IfLj1ELb1EEvPT_S1_j"
	.size	.L__unnamed_78, 30

	.type	.L__unnamed_79,@object          # @78
.L__unnamed_79:
	.asciz	"_Z7reduce6IfLj512ELb0EEvPT_S1_j"
	.size	.L__unnamed_79, 32

	.type	.L__unnamed_80,@object          # @79
.L__unnamed_80:
	.asciz	"_Z7reduce6IfLj256ELb0EEvPT_S1_j"
	.size	.L__unnamed_80, 32

	.type	.L__unnamed_81,@object          # @80
.L__unnamed_81:
	.asciz	"_Z7reduce6IfLj128ELb0EEvPT_S1_j"
	.size	.L__unnamed_81, 32

	.type	.L__unnamed_82,@object          # @81
.L__unnamed_82:
	.asciz	"_Z7reduce6IfLj64ELb0EEvPT_S1_j"
	.size	.L__unnamed_82, 31

	.type	.L__unnamed_83,@object          # @82
.L__unnamed_83:
	.asciz	"_Z7reduce6IfLj32ELb0EEvPT_S1_j"
	.size	.L__unnamed_83, 31

	.type	.L__unnamed_84,@object          # @83
.L__unnamed_84:
	.asciz	"_Z7reduce6IfLj16ELb0EEvPT_S1_j"
	.size	.L__unnamed_84, 31

	.type	.L__unnamed_85,@object          # @84
.L__unnamed_85:
	.asciz	"_Z7reduce6IfLj8ELb0EEvPT_S1_j"
	.size	.L__unnamed_85, 30

	.type	.L__unnamed_86,@object          # @85
.L__unnamed_86:
	.asciz	"_Z7reduce6IfLj4ELb0EEvPT_S1_j"
	.size	.L__unnamed_86, 30

	.type	.L__unnamed_87,@object          # @86
.L__unnamed_87:
	.asciz	"_Z7reduce6IfLj2ELb0EEvPT_S1_j"
	.size	.L__unnamed_87, 30

	.type	.L__unnamed_88,@object          # @87
.L__unnamed_88:
	.asciz	"_Z7reduce6IfLj1ELb0EEvPT_S1_j"
	.size	.L__unnamed_88, 30

	.type	.L__unnamed_89,@object          # @88
.L__unnamed_89:
	.asciz	"_Z7reduce0IdEvPT_S1_j"
	.size	.L__unnamed_89, 22

	.type	.L__unnamed_90,@object          # @89
.L__unnamed_90:
	.asciz	"_Z7reduce1IdEvPT_S1_j"
	.size	.L__unnamed_90, 22

	.type	.L__unnamed_91,@object          # @90
.L__unnamed_91:
	.asciz	"_Z7reduce2IdEvPT_S1_j"
	.size	.L__unnamed_91, 22

	.type	.L__unnamed_92,@object          # @91
.L__unnamed_92:
	.asciz	"_Z7reduce3IdEvPT_S1_j"
	.size	.L__unnamed_92, 22

	.type	.L__unnamed_93,@object          # @92
.L__unnamed_93:
	.asciz	"_Z7reduce4IdLj512EEvPT_S1_j"
	.size	.L__unnamed_93, 28

	.type	.L__unnamed_94,@object          # @93
.L__unnamed_94:
	.asciz	"_Z7reduce4IdLj256EEvPT_S1_j"
	.size	.L__unnamed_94, 28

	.type	.L__unnamed_95,@object          # @94
.L__unnamed_95:
	.asciz	"_Z7reduce4IdLj128EEvPT_S1_j"
	.size	.L__unnamed_95, 28

	.type	.L__unnamed_96,@object          # @95
.L__unnamed_96:
	.asciz	"_Z7reduce4IdLj64EEvPT_S1_j"
	.size	.L__unnamed_96, 27

	.type	.L__unnamed_97,@object          # @96
.L__unnamed_97:
	.asciz	"_Z7reduce4IdLj32EEvPT_S1_j"
	.size	.L__unnamed_97, 27

	.type	.L__unnamed_98,@object          # @97
.L__unnamed_98:
	.asciz	"_Z7reduce4IdLj16EEvPT_S1_j"
	.size	.L__unnamed_98, 27

	.type	.L__unnamed_99,@object          # @98
.L__unnamed_99:
	.asciz	"_Z7reduce4IdLj8EEvPT_S1_j"
	.size	.L__unnamed_99, 26

	.type	.L__unnamed_100,@object         # @99
.L__unnamed_100:
	.asciz	"_Z7reduce4IdLj4EEvPT_S1_j"
	.size	.L__unnamed_100, 26

	.type	.L__unnamed_101,@object         # @100
.L__unnamed_101:
	.asciz	"_Z7reduce4IdLj2EEvPT_S1_j"
	.size	.L__unnamed_101, 26

	.type	.L__unnamed_102,@object         # @101
.L__unnamed_102:
	.asciz	"_Z7reduce4IdLj1EEvPT_S1_j"
	.size	.L__unnamed_102, 26

	.type	.L__unnamed_103,@object         # @102
.L__unnamed_103:
	.asciz	"_Z7reduce5IdLj512EEvPT_S1_j"
	.size	.L__unnamed_103, 28

	.type	.L__unnamed_104,@object         # @103
.L__unnamed_104:
	.asciz	"_Z7reduce5IdLj256EEvPT_S1_j"
	.size	.L__unnamed_104, 28

	.type	.L__unnamed_105,@object         # @104
.L__unnamed_105:
	.asciz	"_Z7reduce5IdLj128EEvPT_S1_j"
	.size	.L__unnamed_105, 28

	.type	.L__unnamed_106,@object         # @105
.L__unnamed_106:
	.asciz	"_Z7reduce5IdLj64EEvPT_S1_j"
	.size	.L__unnamed_106, 27

	.type	.L__unnamed_107,@object         # @106
.L__unnamed_107:
	.asciz	"_Z7reduce5IdLj32EEvPT_S1_j"
	.size	.L__unnamed_107, 27

	.type	.L__unnamed_108,@object         # @107
.L__unnamed_108:
	.asciz	"_Z7reduce5IdLj16EEvPT_S1_j"
	.size	.L__unnamed_108, 27

	.type	.L__unnamed_109,@object         # @108
.L__unnamed_109:
	.asciz	"_Z7reduce5IdLj8EEvPT_S1_j"
	.size	.L__unnamed_109, 26

	.type	.L__unnamed_110,@object         # @109
.L__unnamed_110:
	.asciz	"_Z7reduce5IdLj4EEvPT_S1_j"
	.size	.L__unnamed_110, 26

	.type	.L__unnamed_111,@object         # @110
.L__unnamed_111:
	.asciz	"_Z7reduce5IdLj2EEvPT_S1_j"
	.size	.L__unnamed_111, 26

	.type	.L__unnamed_112,@object         # @111
.L__unnamed_112:
	.asciz	"_Z7reduce5IdLj1EEvPT_S1_j"
	.size	.L__unnamed_112, 26

	.type	.L__unnamed_113,@object         # @112
.L__unnamed_113:
	.asciz	"_Z7reduce6IdLj512ELb1EEvPT_S1_j"
	.size	.L__unnamed_113, 32

	.type	.L__unnamed_114,@object         # @113
.L__unnamed_114:
	.asciz	"_Z7reduce6IdLj256ELb1EEvPT_S1_j"
	.size	.L__unnamed_114, 32

	.type	.L__unnamed_115,@object         # @114
.L__unnamed_115:
	.asciz	"_Z7reduce6IdLj128ELb1EEvPT_S1_j"
	.size	.L__unnamed_115, 32

	.type	.L__unnamed_116,@object         # @115
.L__unnamed_116:
	.asciz	"_Z7reduce6IdLj64ELb1EEvPT_S1_j"
	.size	.L__unnamed_116, 31

	.type	.L__unnamed_117,@object         # @116
.L__unnamed_117:
	.asciz	"_Z7reduce6IdLj32ELb1EEvPT_S1_j"
	.size	.L__unnamed_117, 31

	.type	.L__unnamed_118,@object         # @117
.L__unnamed_118:
	.asciz	"_Z7reduce6IdLj16ELb1EEvPT_S1_j"
	.size	.L__unnamed_118, 31

	.type	.L__unnamed_119,@object         # @118
.L__unnamed_119:
	.asciz	"_Z7reduce6IdLj8ELb1EEvPT_S1_j"
	.size	.L__unnamed_119, 30

	.type	.L__unnamed_120,@object         # @119
.L__unnamed_120:
	.asciz	"_Z7reduce6IdLj4ELb1EEvPT_S1_j"
	.size	.L__unnamed_120, 30

	.type	.L__unnamed_121,@object         # @120
.L__unnamed_121:
	.asciz	"_Z7reduce6IdLj2ELb1EEvPT_S1_j"
	.size	.L__unnamed_121, 30

	.type	.L__unnamed_122,@object         # @121
.L__unnamed_122:
	.asciz	"_Z7reduce6IdLj1ELb1EEvPT_S1_j"
	.size	.L__unnamed_122, 30

	.type	.L__unnamed_123,@object         # @122
.L__unnamed_123:
	.asciz	"_Z7reduce6IdLj512ELb0EEvPT_S1_j"
	.size	.L__unnamed_123, 32

	.type	.L__unnamed_124,@object         # @123
.L__unnamed_124:
	.asciz	"_Z7reduce6IdLj256ELb0EEvPT_S1_j"
	.size	.L__unnamed_124, 32

	.type	.L__unnamed_125,@object         # @124
.L__unnamed_125:
	.asciz	"_Z7reduce6IdLj128ELb0EEvPT_S1_j"
	.size	.L__unnamed_125, 32

	.type	.L__unnamed_126,@object         # @125
.L__unnamed_126:
	.asciz	"_Z7reduce6IdLj64ELb0EEvPT_S1_j"
	.size	.L__unnamed_126, 31

	.type	.L__unnamed_127,@object         # @126
.L__unnamed_127:
	.asciz	"_Z7reduce6IdLj32ELb0EEvPT_S1_j"
	.size	.L__unnamed_127, 31

	.type	.L__unnamed_128,@object         # @127
.L__unnamed_128:
	.asciz	"_Z7reduce6IdLj16ELb0EEvPT_S1_j"
	.size	.L__unnamed_128, 31

	.type	.L__unnamed_129,@object         # @128
.L__unnamed_129:
	.asciz	"_Z7reduce6IdLj8ELb0EEvPT_S1_j"
	.size	.L__unnamed_129, 30

	.type	.L__unnamed_130,@object         # @129
.L__unnamed_130:
	.asciz	"_Z7reduce6IdLj4ELb0EEvPT_S1_j"
	.size	.L__unnamed_130, 30

	.type	.L__unnamed_131,@object         # @130
.L__unnamed_131:
	.asciz	"_Z7reduce6IdLj2ELb0EEvPT_S1_j"
	.size	.L__unnamed_131, 30

	.type	.L__unnamed_132,@object         # @131
.L__unnamed_132:
	.asciz	"_Z7reduce6IdLj1ELb0EEvPT_S1_j"
	.size	.L__unnamed_132, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__reduce0IiEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce1IiEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce2IiEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce3IiEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj512EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj256EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj128EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj64EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj32EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj16EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj8EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj4EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj2EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IiLj1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj512EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj256EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj128EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj64EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj32EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj16EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj8EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj4EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj2EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IiLj1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj512ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj256ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj128ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj64ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj32ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj16ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj8ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj4ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj2ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj1ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj512ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj256ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj128ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj64ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj32ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj16ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj8ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj4ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj2ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IiLj1ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce0IfEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce1IfEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce2IfEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce3IfEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj512EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj256EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj128EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj64EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj32EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj16EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj8EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj4EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj2EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IfLj1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj512EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj256EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj128EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj64EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj32EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj16EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj8EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj4EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj2EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IfLj1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj512ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj256ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj128ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj64ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj32ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj16ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj8ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj4ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj2ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj1ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj512ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj256ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj128ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj64ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj32ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj16ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj8ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj4ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj2ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IfLj1ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce0IdEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce1IdEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce2IdEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce3IdEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj512EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj256EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj128EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj64EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj32EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj16EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj8EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj4EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj2EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce4IdLj1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj512EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj256EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj128EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj64EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj32EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj16EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj8EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj4EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj2EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce5IdLj1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj512ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj256ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj128ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj64ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj32ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj16ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj8ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj4ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj2ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj1ELb1EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj512ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj256ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj128ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj64ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj32ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj16ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj8ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj4ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj2ELb0EEvPT_S1_j
	.addrsig_sym _Z22__device_stub__reduce6IdLj1ELb0EEvPT_S1_j
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7reduce0IiEvPT_S1_j
	.addrsig_sym _Z7reduce1IiEvPT_S1_j
	.addrsig_sym _Z7reduce2IiEvPT_S1_j
	.addrsig_sym _Z7reduce3IiEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj512EEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj256EEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj128EEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj64EEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj32EEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj16EEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj8EEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj4EEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj2EEvPT_S1_j
	.addrsig_sym _Z7reduce4IiLj1EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj512EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj256EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj128EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj64EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj32EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj16EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj8EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj4EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj2EEvPT_S1_j
	.addrsig_sym _Z7reduce5IiLj1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj512ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj256ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj128ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj64ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj32ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj16ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj8ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj4ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj2ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj1ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj512ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj256ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj128ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj64ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj32ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj16ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj8ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj4ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj2ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IiLj1ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce0IfEvPT_S1_j
	.addrsig_sym _Z7reduce1IfEvPT_S1_j
	.addrsig_sym _Z7reduce2IfEvPT_S1_j
	.addrsig_sym _Z7reduce3IfEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj512EEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj256EEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj128EEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj64EEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj32EEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj16EEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj8EEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj4EEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj2EEvPT_S1_j
	.addrsig_sym _Z7reduce4IfLj1EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj512EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj256EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj128EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj64EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj32EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj16EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj8EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj4EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj2EEvPT_S1_j
	.addrsig_sym _Z7reduce5IfLj1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj512ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj256ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj128ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj64ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj32ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj16ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj8ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj4ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj2ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj1ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj512ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj256ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj128ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj64ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj32ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj16ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj8ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj4ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj2ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IfLj1ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce0IdEvPT_S1_j
	.addrsig_sym _Z7reduce1IdEvPT_S1_j
	.addrsig_sym _Z7reduce2IdEvPT_S1_j
	.addrsig_sym _Z7reduce3IdEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj512EEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj256EEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj128EEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj64EEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj32EEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj16EEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj8EEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj4EEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj2EEvPT_S1_j
	.addrsig_sym _Z7reduce4IdLj1EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj512EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj256EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj128EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj64EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj32EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj16EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj8EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj4EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj2EEvPT_S1_j
	.addrsig_sym _Z7reduce5IdLj1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj512ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj256ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj128ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj64ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj32ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj16ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj8ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj4ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj2ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj1ELb1EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj512ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj256ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj128ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj64ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj32ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj16ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj8ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj4ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj2ELb0EEvPT_S1_j
	.addrsig_sym _Z7reduce6IdLj1ELb0EEvPT_S1_j
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z7reduce0IiEvPT_S1_j,"axG",@progbits,_Z7reduce0IiEvPT_S1_j,comdat
	.protected	_Z7reduce0IiEvPT_S1_j   ; -- Begin function _Z7reduce0IiEvPT_S1_j
	.globl	_Z7reduce0IiEvPT_S1_j
	.p2align	8
	.type	_Z7reduce0IiEvPT_S1_j,@function
_Z7reduce0IiEvPT_S1_j:                  ; @_Z7reduce0IiEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v1
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_7
; %bb.3:                                ; %.lr.ph.preheader
	s_mov_b32 s1, 1
.LBB0_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s1, 1
	s_add_i32 s6, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, s6, v0
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	v_lshl_add_u32 v2, s1, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s0, s5
	s_mov_b32 s1, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_4
.LBB0_7:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce0IiEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce0IiEvPT_S1_j,"axG",@progbits,_Z7reduce0IiEvPT_S1_j,comdat
.Lfunc_end0:
	.size	_Z7reduce0IiEvPT_S1_j, .Lfunc_end0-_Z7reduce0IiEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce1IiEvPT_S1_j,"axG",@progbits,_Z7reduce1IiEvPT_S1_j,comdat
	.protected	_Z7reduce1IiEvPT_S1_j   ; -- Begin function _Z7reduce1IiEvPT_S1_j
	.globl	_Z7reduce1IiEvPT_S1_j
	.p2align	8
	.type	_Z7reduce1IiEvPT_S1_j,@function
_Z7reduce1IiEvPT_S1_j:                  ; @_Z7reduce1IiEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v1
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_7
; %bb.3:                                ; %.lr.ph.preheader
	s_mov_b32 s1, 1
.LBB1_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_lshl_b32 s0, s1, 1
	s_mov_b32 s6, exec_lo
	v_mul_lo_u32 v1, s0, v0
	v_cmpx_gt_u32_e64 s5, v1
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=1
	v_lshl_add_u32 v1, v1, 2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v2, s1, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB1_6:                                ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s0, s5
	s_mov_b32 s1, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_4
.LBB1_7:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB1_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB1_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce1IiEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce1IiEvPT_S1_j,"axG",@progbits,_Z7reduce1IiEvPT_S1_j,comdat
.Lfunc_end1:
	.size	_Z7reduce1IiEvPT_S1_j, .Lfunc_end1-_Z7reduce1IiEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 348
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce2IiEvPT_S1_j,"axG",@progbits,_Z7reduce2IiEvPT_S1_j,comdat
	.protected	_Z7reduce2IiEvPT_S1_j   ; -- Begin function _Z7reduce2IiEvPT_S1_j
	.globl	_Z7reduce2IiEvPT_S1_j
	.p2align	8
	.type	_Z7reduce2IiEvPT_S1_j,@function
_Z7reduce2IiEvPT_S1_j:                  ; @_Z7reduce2IiEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v1
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_7
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_3 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB2_6:                                ;   in Loop: Header=BB2_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB2_3
.LBB2_7:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB2_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce2IiEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce2IiEvPT_S1_j,"axG",@progbits,_Z7reduce2IiEvPT_S1_j,comdat
.Lfunc_end2:
	.size	_Z7reduce2IiEvPT_S1_j, .Lfunc_end2-_Z7reduce2IiEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce3IiEvPT_S1_j,"axG",@progbits,_Z7reduce3IiEvPT_S1_j,comdat
	.protected	_Z7reduce3IiEvPT_S1_j   ; -- Begin function _Z7reduce3IiEvPT_S1_j
	.globl	_Z7reduce3IiEvPT_S1_j
	.p2align	8
	.type	_Z7reduce3IiEvPT_S1_j,@function
_Z7reduce3IiEvPT_S1_j:                  ; @_Z7reduce3IiEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v6, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s15, s5
	v_lshl_add_u32 v1, s7, 1, v0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v6, v[2:3], off
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v2, s5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s6, v2
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB3_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v2, v6
.LBB3_4:
	s_or_b32 exec_lo, exec_lo, s6
	v_mov_b32_e32 v3, 0
	s_cmp_lt_u32 s5, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v3
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v6, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB3_9
.LBB3_5:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB3_7
; %bb.6:                                ;   in Loop: Header=BB3_5 Depth=1
	v_add_nc_u32_e32 v2, s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_co_u32 v7, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v2, v[7:8], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v2, v6
	global_store_b32 v[4:5], v6, off
.LBB3_7:                                ;   in Loop: Header=BB3_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_lt_u32 s5, 4
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB3_9
; %bb.8:                                ;   in Loop: Header=BB3_5 Depth=1
	s_mov_b32 s5, s0
	s_branch .LBB3_5
.LBB3_9:                                ; %Flow43
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_11
; %bb.10:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v6, s[0:1]
.LBB3_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce3IiEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce3IiEvPT_S1_j,"axG",@progbits,_Z7reduce3IiEvPT_S1_j,comdat
.Lfunc_end3:
	.size	_Z7reduce3IiEvPT_S1_j, .Lfunc_end3-_Z7reduce3IiEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 436
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce4IiLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj512EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj512EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj512EEvPT_S1_j
	.globl	_Z7reduce4IiLj512EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj512EEvPT_S1_j,@function
_Z7reduce4IiLj512EEvPT_S1_j:            ; @_Z7reduce4IiLj512EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB4_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x200, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB4_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB4_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v5, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB4_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB4_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB4_8
; %bb.7:                                ;   in Loop: Header=BB4_6 Depth=1
	v_lshl_add_u32 v2, s1, 2, v5
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB4_8:                                ;   in Loop: Header=BB4_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB4_10
; %bb.9:                                ;   in Loop: Header=BB4_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB4_6
.LBB4_10:                               ; %Flow99
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB4_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB4_12:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB4_12
.LBB4_13:                               ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB4_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB4_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj512EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj512EEvPT_S1_j,comdat
.Lfunc_end4:
	.size	_Z7reduce4IiLj512EEvPT_S1_j, .Lfunc_end4-_Z7reduce4IiLj512EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IiLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj256EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj256EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj256EEvPT_S1_j
	.globl	_Z7reduce4IiLj256EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj256EEvPT_S1_j,@function
_Z7reduce4IiLj256EEvPT_S1_j:            ; @_Z7reduce4IiLj256EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB5_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB5_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x100, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB5_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB5_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v5, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB5_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB5_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB5_8
; %bb.7:                                ;   in Loop: Header=BB5_6 Depth=1
	v_lshl_add_u32 v2, s1, 2, v5
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB5_8:                                ;   in Loop: Header=BB5_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB5_10
; %bb.9:                                ;   in Loop: Header=BB5_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB5_6
.LBB5_10:                               ; %Flow99
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB5_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB5_12:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB5_12
.LBB5_13:                               ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB5_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB5_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj256EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj256EEvPT_S1_j,comdat
.Lfunc_end5:
	.size	_Z7reduce4IiLj256EEvPT_S1_j, .Lfunc_end5-_Z7reduce4IiLj256EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IiLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj128EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj128EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj128EEvPT_S1_j
	.globl	_Z7reduce4IiLj128EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj128EEvPT_S1_j,@function
_Z7reduce4IiLj128EEvPT_S1_j:            ; @_Z7reduce4IiLj128EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB6_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB6_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x80, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB6_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB6_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v5, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB6_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB6_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB6_8
; %bb.7:                                ;   in Loop: Header=BB6_6 Depth=1
	v_lshl_add_u32 v2, s1, 2, v5
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB6_8:                                ;   in Loop: Header=BB6_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB6_10
; %bb.9:                                ;   in Loop: Header=BB6_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB6_6
.LBB6_10:                               ; %Flow99
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB6_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB6_12:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB6_12
.LBB6_13:                               ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB6_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB6_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj128EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj128EEvPT_S1_j,comdat
.Lfunc_end6:
	.size	_Z7reduce4IiLj128EEvPT_S1_j, .Lfunc_end6-_Z7reduce4IiLj128EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IiLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj64EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj64EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj64EEvPT_S1_j
	.globl	_Z7reduce4IiLj64EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj64EEvPT_S1_j,@function
_Z7reduce4IiLj64EEvPT_S1_j:             ; @_Z7reduce4IiLj64EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB7_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB7_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 64, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB7_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB7_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v5, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB7_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB7_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB7_8
; %bb.7:                                ;   in Loop: Header=BB7_6 Depth=1
	v_lshl_add_u32 v2, s1, 2, v5
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB7_8:                                ;   in Loop: Header=BB7_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB7_10
; %bb.9:                                ;   in Loop: Header=BB7_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB7_6
.LBB7_10:                               ; %Flow99
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB7_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB7_12:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB7_12
.LBB7_13:                               ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB7_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB7_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj64EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj64EEvPT_S1_j,comdat
.Lfunc_end7:
	.size	_Z7reduce4IiLj64EEvPT_S1_j, .Lfunc_end7-_Z7reduce4IiLj64EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 552
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IiLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj32EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj32EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj32EEvPT_S1_j
	.globl	_Z7reduce4IiLj32EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj32EEvPT_S1_j,@function
_Z7reduce4IiLj32EEvPT_S1_j:             ; @_Z7reduce4IiLj32EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB8_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB8_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 32, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB8_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB8_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB8_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB8_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB8_8
; %bb.7:                                ;   in Loop: Header=BB8_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v3, v4
	ds_store_b32 v2, v4
.LBB8_8:                                ;   in Loop: Header=BB8_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB8_10
; %bb.9:                                ;   in Loop: Header=BB8_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB8_6
.LBB8_10:                               ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB8_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB8_12:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB8_12
.LBB8_13:                               ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB8_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB8_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj32EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj32EEvPT_S1_j,comdat
.Lfunc_end8:
	.size	_Z7reduce4IiLj32EEvPT_S1_j, .Lfunc_end8-_Z7reduce4IiLj32EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IiLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj16EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj16EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj16EEvPT_S1_j
	.globl	_Z7reduce4IiLj16EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj16EEvPT_S1_j,@function
_Z7reduce4IiLj16EEvPT_S1_j:             ; @_Z7reduce4IiLj16EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB9_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB9_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 16, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB9_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB9_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB9_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB9_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB9_8
; %bb.7:                                ;   in Loop: Header=BB9_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v3, v4
	ds_store_b32 v2, v4
.LBB9_8:                                ;   in Loop: Header=BB9_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB9_10
; %bb.9:                                ;   in Loop: Header=BB9_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB9_6
.LBB9_10:                               ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB9_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB9_12:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB9_12
.LBB9_13:                               ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB9_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB9_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj16EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj16EEvPT_S1_j,comdat
.Lfunc_end9:
	.size	_Z7reduce4IiLj16EEvPT_S1_j, .Lfunc_end9-_Z7reduce4IiLj16EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IiLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj8EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj8EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj8EEvPT_S1_j
	.globl	_Z7reduce4IiLj8EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj8EEvPT_S1_j,@function
_Z7reduce4IiLj8EEvPT_S1_j:              ; @_Z7reduce4IiLj8EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB10_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB10_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB10_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB10_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB10_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB10_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB10_8
; %bb.7:                                ;   in Loop: Header=BB10_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v3, v4
	ds_store_b32 v2, v4
.LBB10_8:                               ;   in Loop: Header=BB10_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB10_10
; %bb.9:                                ;   in Loop: Header=BB10_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB10_6
.LBB10_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB10_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB10_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB10_12
.LBB10_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB10_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB10_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj8EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj8EEvPT_S1_j,comdat
.Lfunc_end10:
	.size	_Z7reduce4IiLj8EEvPT_S1_j, .Lfunc_end10-_Z7reduce4IiLj8EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IiLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj4EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj4EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj4EEvPT_S1_j
	.globl	_Z7reduce4IiLj4EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj4EEvPT_S1_j,@function
_Z7reduce4IiLj4EEvPT_S1_j:              ; @_Z7reduce4IiLj4EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB11_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB11_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB11_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB11_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB11_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB11_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB11_8
; %bb.7:                                ;   in Loop: Header=BB11_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v3, v4
	ds_store_b32 v2, v4
.LBB11_8:                               ;   in Loop: Header=BB11_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB11_10
; %bb.9:                                ;   in Loop: Header=BB11_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB11_6
.LBB11_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB11_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB11_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB11_12
.LBB11_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB11_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB11_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj4EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj4EEvPT_S1_j,comdat
.Lfunc_end11:
	.size	_Z7reduce4IiLj4EEvPT_S1_j, .Lfunc_end11-_Z7reduce4IiLj4EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IiLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj2EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj2EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj2EEvPT_S1_j
	.globl	_Z7reduce4IiLj2EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj2EEvPT_S1_j,@function
_Z7reduce4IiLj2EEvPT_S1_j:              ; @_Z7reduce4IiLj2EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB12_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB12_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 2, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB12_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB12_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB12_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB12_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB12_8
; %bb.7:                                ;   in Loop: Header=BB12_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v3, v4
	ds_store_b32 v2, v4
.LBB12_8:                               ;   in Loop: Header=BB12_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB12_10
; %bb.9:                                ;   in Loop: Header=BB12_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB12_6
.LBB12_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB12_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB12_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB12_12
.LBB12_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB12_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB12_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj2EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj2EEvPT_S1_j,comdat
.Lfunc_end12:
	.size	_Z7reduce4IiLj2EEvPT_S1_j, .Lfunc_end12-_Z7reduce4IiLj2EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IiLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj1EEvPT_S1_j,comdat
	.protected	_Z7reduce4IiLj1EEvPT_S1_j ; -- Begin function _Z7reduce4IiLj1EEvPT_S1_j
	.globl	_Z7reduce4IiLj1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IiLj1EEvPT_S1_j,@function
_Z7reduce4IiLj1EEvPT_S1_j:              ; @_Z7reduce4IiLj1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB13_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB13_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB13_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB13_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB13_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB13_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB13_8
; %bb.7:                                ;   in Loop: Header=BB13_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v3, v4
	ds_store_b32 v2, v4
.LBB13_8:                               ;   in Loop: Header=BB13_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB13_10
; %bb.9:                                ;   in Loop: Header=BB13_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB13_6
.LBB13_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB13_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB13_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB13_12
.LBB13_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB13_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB13_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IiLj1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IiLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce4IiLj1EEvPT_S1_j,comdat
.Lfunc_end13:
	.size	_Z7reduce4IiLj1EEvPT_S1_j, .Lfunc_end13-_Z7reduce4IiLj1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj512EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj512EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj512EEvPT_S1_j
	.globl	_Z7reduce5IiLj512EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj512EEvPT_S1_j,@function
_Z7reduce5IiLj512EEvPT_S1_j:            ; @_Z7reduce5IiLj512EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v2, s2, 10, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB14_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB14_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x200, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB14_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB14_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s0, s[0:1], 0x24
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v1
	s_cbranch_execz .LBB14_6
; %bb.5:
	ds_load_b32 v2, v5 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB14_6:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB14_8
; %bb.7:
	ds_load_b32 v2, v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB14_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB14_10
; %bb.9:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB14_10:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s1, v2
	s_mov_b32 s1, 16
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB14_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB14_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB14_12
.LBB14_13:                              ; %Flow102
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB14_15
; %bb.14:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB14_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj512EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj512EEvPT_S1_j,comdat
.Lfunc_end14:
	.size	_Z7reduce5IiLj512EEvPT_S1_j, .Lfunc_end14-_Z7reduce5IiLj512EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 624
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj256EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj256EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj256EEvPT_S1_j
	.globl	_Z7reduce5IiLj256EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj256EEvPT_S1_j,@function
_Z7reduce5IiLj256EEvPT_S1_j:            ; @_Z7reduce5IiLj256EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 9, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB15_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB15_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x100, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB15_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB15_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s0, s[0:1], 0x24
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB15_6
; %bb.5:
	ds_load_b32 v2, v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB15_6:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB15_8
; %bb.7:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB15_8:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s1, v2
	s_mov_b32 s1, 16
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB15_11
; %bb.9:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB15_10:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB15_10
.LBB15_11:                              ; %Flow95
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB15_13
; %bb.12:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB15_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj256EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj256EEvPT_S1_j,comdat
.Lfunc_end15:
	.size	_Z7reduce5IiLj256EEvPT_S1_j, .Lfunc_end15-_Z7reduce5IiLj256EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 572
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj128EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj128EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj128EEvPT_S1_j
	.globl	_Z7reduce5IiLj128EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj128EEvPT_S1_j,@function
_Z7reduce5IiLj128EEvPT_S1_j:            ; @_Z7reduce5IiLj128EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 8, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB16_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB16_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x80, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB16_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB16_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s0, s[0:1], 0x24
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB16_6
; %bb.5:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB16_6:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s1, v2
	s_mov_b32 s1, 16
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB16_9
; %bb.7:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB16_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB16_8
.LBB16_9:                               ; %Flow88
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB16_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB16_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj128EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj128EEvPT_S1_j,comdat
.Lfunc_end16:
	.size	_Z7reduce5IiLj128EEvPT_S1_j, .Lfunc_end16-_Z7reduce5IiLj128EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 520
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj64EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj64EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj64EEvPT_S1_j
	.globl	_Z7reduce5IiLj64EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj64EEvPT_S1_j,@function
_Z7reduce5IiLj64EEvPT_S1_j:             ; @_Z7reduce5IiLj64EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 7, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB17_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB17_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 64, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB17_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB17_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	s_and_b32 s0, s0, 0xffff
	v_lshl_add_u32 v0, v1, 2, 0
	s_mov_b32 s1, 16
	v_mad_u32_u24 v5, v3, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v4
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, v5, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB17_7
; %bb.5:
	ds_load_b32 v0, v0 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB17_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB17_6
.LBB17_7:                               ; %Flow81
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB17_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB17_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj64EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj64EEvPT_S1_j,comdat
.Lfunc_end17:
	.size	_Z7reduce5IiLj64EEvPT_S1_j, .Lfunc_end17-_Z7reduce5IiLj64EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 476
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj32EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj32EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj32EEvPT_S1_j
	.globl	_Z7reduce5IiLj32EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj32EEvPT_S1_j,@function
_Z7reduce5IiLj32EEvPT_S1_j:             ; @_Z7reduce5IiLj32EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 6, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB18_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB18_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 32, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB18_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB18_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB18_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB18_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB18_6
.LBB18_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB18_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB18_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj32EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj32EEvPT_S1_j,comdat
.Lfunc_end18:
	.size	_Z7reduce5IiLj32EEvPT_S1_j, .Lfunc_end18-_Z7reduce5IiLj32EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj16EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj16EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj16EEvPT_S1_j
	.globl	_Z7reduce5IiLj16EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj16EEvPT_S1_j,@function
_Z7reduce5IiLj16EEvPT_S1_j:             ; @_Z7reduce5IiLj16EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 5, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB19_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB19_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 16, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB19_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB19_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	v_mad_u32_u24 v0, v0, s1, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB19_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_mov_b32 s1, 16
.LBB19_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB19_6
.LBB19_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB19_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB19_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj16EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj16EEvPT_S1_j,comdat
.Lfunc_end19:
	.size	_Z7reduce5IiLj16EEvPT_S1_j, .Lfunc_end19-_Z7reduce5IiLj16EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj8EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj8EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj8EEvPT_S1_j
	.globl	_Z7reduce5IiLj8EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj8EEvPT_S1_j,@function
_Z7reduce5IiLj8EEvPT_S1_j:              ; @_Z7reduce5IiLj8EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 4, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB20_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB20_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 8, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB20_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB20_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB20_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB20_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB20_6
.LBB20_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB20_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB20_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj8EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj8EEvPT_S1_j,comdat
.Lfunc_end20:
	.size	_Z7reduce5IiLj8EEvPT_S1_j, .Lfunc_end20-_Z7reduce5IiLj8EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj4EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj4EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj4EEvPT_S1_j
	.globl	_Z7reduce5IiLj4EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj4EEvPT_S1_j,@function
_Z7reduce5IiLj4EEvPT_S1_j:              ; @_Z7reduce5IiLj4EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 3, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB21_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB21_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 4, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB21_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB21_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB21_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB21_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB21_6
.LBB21_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB21_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB21_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj4EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj4EEvPT_S1_j,comdat
.Lfunc_end21:
	.size	_Z7reduce5IiLj4EEvPT_S1_j, .Lfunc_end21-_Z7reduce5IiLj4EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj2EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj2EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj2EEvPT_S1_j
	.globl	_Z7reduce5IiLj2EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj2EEvPT_S1_j,@function
_Z7reduce5IiLj2EEvPT_S1_j:              ; @_Z7reduce5IiLj2EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 2, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB22_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB22_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 2, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB22_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB22_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB22_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB22_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB22_6
.LBB22_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB22_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB22_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj2EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj2EEvPT_S1_j,comdat
.Lfunc_end22:
	.size	_Z7reduce5IiLj2EEvPT_S1_j, .Lfunc_end22-_Z7reduce5IiLj2EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IiLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj1EEvPT_S1_j,comdat
	.protected	_Z7reduce5IiLj1EEvPT_S1_j ; -- Begin function _Z7reduce5IiLj1EEvPT_S1_j
	.globl	_Z7reduce5IiLj1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IiLj1EEvPT_S1_j,@function
_Z7reduce5IiLj1EEvPT_S1_j:              ; @_Z7reduce5IiLj1EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 1, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB23_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB23_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 1, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB23_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
.LBB23_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB23_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB23_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB23_6
.LBB23_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB23_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB23_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IiLj1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IiLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce5IiLj1EEvPT_S1_j,comdat
.Lfunc_end23:
	.size	_Z7reduce5IiLj1EEvPT_S1_j, .Lfunc_end23-_Z7reduce5IiLj1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj512ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj512ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj512ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj512ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj512ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj512ELb1EEvPT_S1_j:        ; @_Z7reduce6IiLj512ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v2, s2, 10, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB24_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 10
	s_mov_b32 s0, 0
.LBB24_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 0x200, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB24_2
; %bb.3:                                ; %Flow111
	s_or_b32 exec_lo, exec_lo, s0
.LBB24_4:                               ; %Flow112
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v1
	s_cbranch_execz .LBB24_6
; %bb.5:
	ds_load_b32 v2, v5 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB24_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB24_8
; %bb.7:
	ds_load_b32 v2, v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB24_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB24_10
; %bb.9:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB24_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB24_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB24_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB24_12
.LBB24_13:                              ; %Flow110
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB24_15
; %bb.14:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB24_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj512ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj512ELb1EEvPT_S1_j,comdat
.Lfunc_end24:
	.size	_Z7reduce6IiLj512ELb1EEvPT_S1_j, .Lfunc_end24-_Z7reduce6IiLj512ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 664
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj256ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj256ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj256ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj256ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj256ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj256ELb1EEvPT_S1_j:        ; @_Z7reduce6IiLj256ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 9, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB25_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 9
	s_mov_b32 s0, 0
.LBB25_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 0x100, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB25_2
; %bb.3:                                ; %Flow104
	s_or_b32 exec_lo, exec_lo, s0
.LBB25_4:                               ; %Flow105
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB25_6
; %bb.5:
	ds_load_b32 v2, v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB25_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB25_8
; %bb.7:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB25_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB25_11
; %bb.9:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB25_10:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB25_10
.LBB25_11:                              ; %Flow103
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB25_13
; %bb.12:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB25_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj256ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj256ELb1EEvPT_S1_j,comdat
.Lfunc_end25:
	.size	_Z7reduce6IiLj256ELb1EEvPT_S1_j, .Lfunc_end25-_Z7reduce6IiLj256ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 612
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj128ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj128ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj128ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj128ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj128ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj128ELb1EEvPT_S1_j:        ; @_Z7reduce6IiLj128ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 8, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB26_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 8
	s_mov_b32 s0, 0
.LBB26_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 0x80, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB26_2
; %bb.3:                                ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
.LBB26_4:                               ; %Flow98
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB26_6
; %bb.5:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v2, v4
	ds_store_b32 v5, v4
.LBB26_6:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB26_9
; %bb.7:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB26_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB26_8
.LBB26_9:                               ; %Flow96
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB26_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB26_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj128ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj128ELb1EEvPT_S1_j,comdat
.Lfunc_end26:
	.size	_Z7reduce6IiLj128ELb1EEvPT_S1_j, .Lfunc_end26-_Z7reduce6IiLj128ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj64ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj64ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj64ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj64ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj64ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj64ELb1EEvPT_S1_j:         ; @_Z7reduce6IiLj64ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 7, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB27_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 7
	s_mov_b32 s0, 0
.LBB27_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 64, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB27_2
; %bb.3:                                ; %Flow90
	s_or_b32 exec_lo, exec_lo, s0
.LBB27_4:                               ; %Flow91
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v0, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v5, v3, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v0, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v5, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB27_7
; %bb.5:
	ds_load_b32 v0, v0 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v0, v4
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB27_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB27_6
.LBB27_7:                               ; %Flow89
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB27_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB27_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj64ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj64ELb1EEvPT_S1_j,comdat
.Lfunc_end27:
	.size	_Z7reduce6IiLj64ELb1EEvPT_S1_j, .Lfunc_end27-_Z7reduce6IiLj64ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 512
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj32ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj32ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj32ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj32ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj32ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj32ELb1EEvPT_S1_j:         ; @_Z7reduce6IiLj32ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 6, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB28_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 6
	s_mov_b32 s0, 0
.LBB28_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 32, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB28_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB28_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB28_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB28_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB28_6
.LBB28_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB28_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB28_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj32ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj32ELb1EEvPT_S1_j,comdat
.Lfunc_end28:
	.size	_Z7reduce6IiLj32ELb1EEvPT_S1_j, .Lfunc_end28-_Z7reduce6IiLj32ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 496
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj16ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj16ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj16ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj16ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj16ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj16ELb1EEvPT_S1_j:         ; @_Z7reduce6IiLj16ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 5, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB29_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 5
	s_mov_b32 s0, 0
.LBB29_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 16, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB29_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB29_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB29_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB29_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB29_6
.LBB29_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB29_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB29_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj16ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj16ELb1EEvPT_S1_j,comdat
.Lfunc_end29:
	.size	_Z7reduce6IiLj16ELb1EEvPT_S1_j, .Lfunc_end29-_Z7reduce6IiLj16ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 496
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj8ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj8ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj8ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj8ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj8ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj8ELb1EEvPT_S1_j:          ; @_Z7reduce6IiLj8ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 4, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB30_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 4
	s_mov_b32 s0, 0
.LBB30_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 8, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB30_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB30_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB30_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB30_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB30_6
.LBB30_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB30_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB30_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj8ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj8ELb1EEvPT_S1_j,comdat
.Lfunc_end30:
	.size	_Z7reduce6IiLj8ELb1EEvPT_S1_j, .Lfunc_end30-_Z7reduce6IiLj8ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 496
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj4ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj4ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj4ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj4ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj4ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj4ELb1EEvPT_S1_j:          ; @_Z7reduce6IiLj4ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 3, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB31_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 3
	s_mov_b32 s0, 0
.LBB31_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 4, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB31_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB31_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB31_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB31_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB31_6
.LBB31_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB31_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB31_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj4ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj4ELb1EEvPT_S1_j,comdat
.Lfunc_end31:
	.size	_Z7reduce6IiLj4ELb1EEvPT_S1_j, .Lfunc_end31-_Z7reduce6IiLj4ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 496
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj2ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj2ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj2ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj2ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj2ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj2ELb1EEvPT_S1_j:          ; @_Z7reduce6IiLj2ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 2, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB32_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 2
	s_mov_b32 s0, 0
.LBB32_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 2, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB32_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB32_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB32_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB32_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB32_6
.LBB32_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB32_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB32_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj2ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj2ELb1EEvPT_S1_j,comdat
.Lfunc_end32:
	.size	_Z7reduce6IiLj2ELb1EEvPT_S1_j, .Lfunc_end32-_Z7reduce6IiLj2ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 496
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj1ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj1ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj1ELb1EEvPT_S1_j
	.globl	_Z7reduce6IiLj1ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj1ELb1EEvPT_S1_j,@function
_Z7reduce6IiLj1ELb1EEvPT_S1_j:          ; @_Z7reduce6IiLj1ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 1, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB33_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 1
	s_mov_b32 s0, 0
.LBB33_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	global_load_b64 v[5:6], v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v5, v4, v6
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB33_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB33_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB33_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB33_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v1, v4
	s_cbranch_scc1 .LBB33_6
.LBB33_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB33_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB33_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj1ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj1ELb1EEvPT_S1_j,comdat
.Lfunc_end33:
	.size	_Z7reduce6IiLj1ELb1EEvPT_S1_j, .Lfunc_end33-_Z7reduce6IiLj1ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 452
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj512ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj512ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj512ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj512ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj512ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj512ELb0EEvPT_S1_j:        ; @_Z7reduce6IiLj512ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v2, s2, 10, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB34_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 10
	s_mov_b32 s0, 0
.LBB34_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 0x200, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v5, v6
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB34_4
; %bb.3:                                ;   in Loop: Header=BB34_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB34_4:                               ;   in Loop: Header=BB34_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB34_2
; %bb.5:                                ; %Flow109
	s_or_b32 exec_lo, exec_lo, s0
.LBB34_6:                               ; %Flow110
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v4, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v4, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v1
	s_cbranch_execz .LBB34_8
; %bb.7:
	ds_load_b32 v2, v4 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v2, v6
	ds_store_b32 v4, v6
.LBB34_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB34_10
; %bb.9:
	ds_load_b32 v2, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v2, v6
	ds_store_b32 v4, v6
.LBB34_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB34_12
; %bb.11:
	ds_load_b32 v2, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v2, v6
	ds_store_b32 v4, v6
.LBB34_12:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB34_15
; %bb.13:
	ds_load_b32 v0, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v0, v6
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB34_14:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB34_14
.LBB34_15:                              ; %Flow108
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB34_17
; %bb.16:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB34_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj512ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj512ELb0EEvPT_S1_j,comdat
.Lfunc_end34:
	.size	_Z7reduce6IiLj512ELb0EEvPT_S1_j, .Lfunc_end34-_Z7reduce6IiLj512ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 692
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj256ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj256ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj256ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj256ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj256ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj256ELb0EEvPT_S1_j:        ; @_Z7reduce6IiLj256ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 9, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB35_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 9
	s_mov_b32 s0, 0
.LBB35_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 0x100, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v5, v6
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB35_4
; %bb.3:                                ;   in Loop: Header=BB35_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB35_4:                               ;   in Loop: Header=BB35_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB35_2
; %bb.5:                                ; %Flow102
	s_or_b32 exec_lo, exec_lo, s0
.LBB35_6:                               ; %Flow103
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v4, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v4, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB35_8
; %bb.7:
	ds_load_b32 v2, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v2, v6
	ds_store_b32 v4, v6
.LBB35_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB35_10
; %bb.9:
	ds_load_b32 v2, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v2, v6
	ds_store_b32 v4, v6
.LBB35_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB35_13
; %bb.11:
	ds_load_b32 v0, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v0, v6
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB35_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB35_12
.LBB35_13:                              ; %Flow101
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB35_15
; %bb.14:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB35_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj256ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj256ELb0EEvPT_S1_j,comdat
.Lfunc_end35:
	.size	_Z7reduce6IiLj256ELb0EEvPT_S1_j, .Lfunc_end35-_Z7reduce6IiLj256ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 640
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj128ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj128ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj128ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj128ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj128ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj128ELb0EEvPT_S1_j:        ; @_Z7reduce6IiLj128ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 8, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB36_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 8
	s_mov_b32 s0, 0
.LBB36_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 0x80, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v5, v6
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB36_4
; %bb.3:                                ;   in Loop: Header=BB36_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB36_4:                               ;   in Loop: Header=BB36_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB36_2
; %bb.5:                                ; %Flow95
	s_or_b32 exec_lo, exec_lo, s0
.LBB36_6:                               ; %Flow96
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v4, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v4, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB36_8
; %bb.7:
	ds_load_b32 v2, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v2, v6
	ds_store_b32 v4, v6
.LBB36_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB36_11
; %bb.9:
	ds_load_b32 v0, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v0, v6
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB36_10:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB36_10
.LBB36_11:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB36_13
; %bb.12:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB36_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj128ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj128ELb0EEvPT_S1_j,comdat
.Lfunc_end36:
	.size	_Z7reduce6IiLj128ELb0EEvPT_S1_j, .Lfunc_end36-_Z7reduce6IiLj128ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj64ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj64ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj64ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj64ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj64ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj64ELb0EEvPT_S1_j:         ; @_Z7reduce6IiLj64ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 7, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB37_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 7
	s_mov_b32 s0, 0
.LBB37_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 64, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v5, v6
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB37_4
; %bb.3:                                ;   in Loop: Header=BB37_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB37_4:                               ;   in Loop: Header=BB37_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB37_2
; %bb.5:                                ; %Flow88
	s_or_b32 exec_lo, exec_lo, s0
.LBB37_6:                               ; %Flow89
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v0, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v4, v3, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v0, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v4, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB37_9
; %bb.7:
	ds_load_b32 v0, v0 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v0, v6
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB37_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB37_8
.LBB37_9:                               ; %Flow87
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB37_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB37_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj64ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj64ELb0EEvPT_S1_j,comdat
.Lfunc_end37:
	.size	_Z7reduce6IiLj64ELb0EEvPT_S1_j, .Lfunc_end37-_Z7reduce6IiLj64ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 540
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj32ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj32ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj32ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj32ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj32ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj32ELb0EEvPT_S1_j:         ; @_Z7reduce6IiLj32ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 6, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB38_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 6
	s_mov_b32 s0, 0
.LBB38_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 32, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v5, v6
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB38_4
; %bb.3:                                ;   in Loop: Header=BB38_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB38_4:                               ;   in Loop: Header=BB38_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB38_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB38_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB38_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB38_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB38_8
.LBB38_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB38_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB38_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj32ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj32ELb0EEvPT_S1_j,comdat
.Lfunc_end38:
	.size	_Z7reduce6IiLj32ELb0EEvPT_S1_j, .Lfunc_end38-_Z7reduce6IiLj32ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj16ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj16ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj16ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj16ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj16ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj16ELb0EEvPT_S1_j:         ; @_Z7reduce6IiLj16ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 5, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB39_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 5
	s_mov_b32 s0, 0
.LBB39_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 16, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v5, v6
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB39_4
; %bb.3:                                ;   in Loop: Header=BB39_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB39_4:                               ;   in Loop: Header=BB39_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB39_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB39_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB39_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB39_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB39_8
.LBB39_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB39_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB39_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj16ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj16ELb0EEvPT_S1_j,comdat
.Lfunc_end39:
	.size	_Z7reduce6IiLj16ELb0EEvPT_S1_j, .Lfunc_end39-_Z7reduce6IiLj16ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj8ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj8ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj8ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj8ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj8ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj8ELb0EEvPT_S1_j:          ; @_Z7reduce6IiLj8ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 4, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB40_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 4
	s_mov_b32 s0, 0
.LBB40_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 8, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v5, v6
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB40_4
; %bb.3:                                ;   in Loop: Header=BB40_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB40_4:                               ;   in Loop: Header=BB40_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB40_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB40_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB40_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB40_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB40_8
.LBB40_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB40_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB40_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj8ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj8ELb0EEvPT_S1_j,comdat
.Lfunc_end40:
	.size	_Z7reduce6IiLj8ELb0EEvPT_S1_j, .Lfunc_end40-_Z7reduce6IiLj8ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj4ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj4ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj4ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj4ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj4ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj4ELb0EEvPT_S1_j:          ; @_Z7reduce6IiLj4ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 3, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB41_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 3
	s_mov_b32 s0, 0
.LBB41_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 4, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v5, v6
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB41_4
; %bb.3:                                ;   in Loop: Header=BB41_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB41_4:                               ;   in Loop: Header=BB41_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB41_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB41_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB41_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB41_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB41_8
.LBB41_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB41_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB41_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj4ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj4ELb0EEvPT_S1_j,comdat
.Lfunc_end41:
	.size	_Z7reduce6IiLj4ELb0EEvPT_S1_j, .Lfunc_end41-_Z7reduce6IiLj4ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj2ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj2ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj2ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj2ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj2ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj2ELb0EEvPT_S1_j:          ; @_Z7reduce6IiLj2ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 2, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB42_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 2
	s_mov_b32 s0, 0
.LBB42_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 2, v2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v5, v6
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB42_4
; %bb.3:                                ;   in Loop: Header=BB42_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB42_4:                               ;   in Loop: Header=BB42_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB42_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB42_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB42_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB42_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB42_8
.LBB42_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB42_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB42_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj2ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj2ELb0EEvPT_S1_j,comdat
.Lfunc_end42:
	.size	_Z7reduce6IiLj2ELb0EEvPT_S1_j, .Lfunc_end42-_Z7reduce6IiLj2ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IiLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj1ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IiLj1ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IiLj1ELb0EEvPT_S1_j
	.globl	_Z7reduce6IiLj1ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IiLj1ELb0EEvPT_S1_j,@function
_Z7reduce6IiLj1ELb0EEvPT_S1_j:          ; @_Z7reduce6IiLj1ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 1, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB43_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 1
	s_mov_b32 s0, 0
.LBB43_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_nc_u32_e32 v8, 1, v2
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v7, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v7, v6
	v_cmpx_gt_u32_e64 s8, v8
	s_cbranch_execz .LBB43_4
; %bb.3:                                ;   in Loop: Header=BB43_2 Depth=1
	global_load_b32 v4, v[4:5], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, v4, v6
.LBB43_4:                               ;   in Loop: Header=BB43_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB43_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB43_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB43_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB43_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v1, v6
	s_cbranch_scc1 .LBB43_8
.LBB43_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB43_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB43_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IiLj1ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IiLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IiLj1ELb0EEvPT_S1_j,comdat
.Lfunc_end43:
	.size	_Z7reduce6IiLj1ELb0EEvPT_S1_j, .Lfunc_end43-_Z7reduce6IiLj1ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 492
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce0IfEvPT_S1_j,"axG",@progbits,_Z7reduce0IfEvPT_S1_j,comdat
	.protected	_Z7reduce0IfEvPT_S1_j   ; -- Begin function _Z7reduce0IfEvPT_S1_j
	.globl	_Z7reduce0IfEvPT_S1_j
	.p2align	8
	.type	_Z7reduce0IfEvPT_S1_j,@function
_Z7reduce0IfEvPT_S1_j:                  ; @_Z7reduce0IfEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v1
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB44_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB44_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB44_7
; %bb.3:                                ; %.lr.ph.preheader
	s_mov_b32 s1, 1
.LBB44_4:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s1, 1
	s_add_i32 s6, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, s6, v0
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB44_6
; %bb.5:                                ;   in Loop: Header=BB44_4 Depth=1
	v_lshl_add_u32 v2, s1, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB44_6:                               ;   in Loop: Header=BB44_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s0, s5
	s_mov_b32 s1, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB44_4
.LBB44_7:                               ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB44_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB44_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce0IfEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce0IfEvPT_S1_j,"axG",@progbits,_Z7reduce0IfEvPT_S1_j,comdat
.Lfunc_end44:
	.size	_Z7reduce0IfEvPT_S1_j, .Lfunc_end44-_Z7reduce0IfEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce1IfEvPT_S1_j,"axG",@progbits,_Z7reduce1IfEvPT_S1_j,comdat
	.protected	_Z7reduce1IfEvPT_S1_j   ; -- Begin function _Z7reduce1IfEvPT_S1_j
	.globl	_Z7reduce1IfEvPT_S1_j
	.p2align	8
	.type	_Z7reduce1IfEvPT_S1_j,@function
_Z7reduce1IfEvPT_S1_j:                  ; @_Z7reduce1IfEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v1
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB45_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB45_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB45_7
; %bb.3:                                ; %.lr.ph.preheader
	s_mov_b32 s1, 1
.LBB45_4:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_lshl_b32 s0, s1, 1
	s_mov_b32 s6, exec_lo
	v_mul_lo_u32 v1, s0, v0
	v_cmpx_gt_u32_e64 s5, v1
	s_cbranch_execz .LBB45_6
; %bb.5:                                ;   in Loop: Header=BB45_4 Depth=1
	v_lshl_add_u32 v1, v1, 2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v2, s1, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB45_6:                               ;   in Loop: Header=BB45_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s0, s5
	s_mov_b32 s1, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB45_4
.LBB45_7:                               ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB45_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB45_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce1IfEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce1IfEvPT_S1_j,"axG",@progbits,_Z7reduce1IfEvPT_S1_j,comdat
.Lfunc_end45:
	.size	_Z7reduce1IfEvPT_S1_j, .Lfunc_end45-_Z7reduce1IfEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 348
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce2IfEvPT_S1_j,"axG",@progbits,_Z7reduce2IfEvPT_S1_j,comdat
	.protected	_Z7reduce2IfEvPT_S1_j   ; -- Begin function _Z7reduce2IfEvPT_S1_j
	.globl	_Z7reduce2IfEvPT_S1_j
	.p2align	8
	.type	_Z7reduce2IfEvPT_S1_j,@function
_Z7reduce2IfEvPT_S1_j:                  ; @_Z7reduce2IfEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v1
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB46_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB46_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB46_3:                               ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB46_7
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB46_3 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB46_6
; %bb.5:                                ;   in Loop: Header=BB46_3 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v2, v2
	ds_load_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v1, v2
.LBB46_6:                               ;   in Loop: Header=BB46_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB46_3
.LBB46_7:                               ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB46_9
; %bb.8:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 2
	s_add_u32 s0, s2, s0
	ds_load_b32 v1, v0
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB46_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce2IfEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce2IfEvPT_S1_j,"axG",@progbits,_Z7reduce2IfEvPT_S1_j,comdat
.Lfunc_end46:
	.size	_Z7reduce2IfEvPT_S1_j, .Lfunc_end46-_Z7reduce2IfEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce3IfEvPT_S1_j,"axG",@progbits,_Z7reduce3IfEvPT_S1_j,comdat
	.protected	_Z7reduce3IfEvPT_S1_j   ; -- Begin function _Z7reduce3IfEvPT_S1_j
	.globl	_Z7reduce3IfEvPT_S1_j
	.p2align	8
	.type	_Z7reduce3IfEvPT_S1_j,@function
_Z7reduce3IfEvPT_S1_j:                  ; @_Z7reduce3IfEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v6, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s15, s5
	v_lshl_add_u32 v1, s7, 1, v0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s6, v1
	s_cbranch_execz .LBB47_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v6, v[2:3], off
.LBB47_2:
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v2, s5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s6, v2
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB47_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v2
.LBB47_4:
	s_or_b32 exec_lo, exec_lo, s6
	v_mov_b32_e32 v3, 0
	s_cmp_lt_u32 s5, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v3
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[4:5], v6, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB47_9
.LBB47_5:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB47_7
; %bb.6:                                ;   in Loop: Header=BB47_5 Depth=1
	v_add_nc_u32_e32 v2, s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_co_u32 v7, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v2, v[7:8], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v2
	global_store_b32 v[4:5], v6, off
.LBB47_7:                               ;   in Loop: Header=BB47_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_lt_u32 s5, 4
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB47_9
; %bb.8:                                ;   in Loop: Header=BB47_5 Depth=1
	s_mov_b32 s5, s0
	s_branch .LBB47_5
.LBB47_9:                               ; %Flow43
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB47_11
; %bb.10:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v6, s[0:1]
.LBB47_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce3IfEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce3IfEvPT_S1_j,"axG",@progbits,_Z7reduce3IfEvPT_S1_j,comdat
.Lfunc_end47:
	.size	_Z7reduce3IfEvPT_S1_j, .Lfunc_end47-_Z7reduce3IfEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 436
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce4IfLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj512EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj512EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj512EEvPT_S1_j
	.globl	_Z7reduce4IfLj512EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj512EEvPT_S1_j,@function
_Z7reduce4IfLj512EEvPT_S1_j:            ; @_Z7reduce4IfLj512EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB48_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB48_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x200, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB48_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB48_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v5, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB48_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB48_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB48_8
; %bb.7:                                ;   in Loop: Header=BB48_6 Depth=1
	v_lshl_add_u32 v2, s1, 2, v5
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB48_8:                               ;   in Loop: Header=BB48_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB48_10
; %bb.9:                                ;   in Loop: Header=BB48_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB48_6
.LBB48_10:                              ; %Flow99
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB48_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB48_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB48_12
.LBB48_13:                              ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB48_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB48_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj512EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj512EEvPT_S1_j,comdat
.Lfunc_end48:
	.size	_Z7reduce4IfLj512EEvPT_S1_j, .Lfunc_end48-_Z7reduce4IfLj512EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IfLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj256EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj256EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj256EEvPT_S1_j
	.globl	_Z7reduce4IfLj256EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj256EEvPT_S1_j,@function
_Z7reduce4IfLj256EEvPT_S1_j:            ; @_Z7reduce4IfLj256EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB49_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB49_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x100, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB49_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB49_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v5, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB49_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB49_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB49_8
; %bb.7:                                ;   in Loop: Header=BB49_6 Depth=1
	v_lshl_add_u32 v2, s1, 2, v5
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB49_8:                               ;   in Loop: Header=BB49_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB49_10
; %bb.9:                                ;   in Loop: Header=BB49_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB49_6
.LBB49_10:                              ; %Flow99
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB49_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB49_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB49_12
.LBB49_13:                              ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB49_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB49_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj256EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj256EEvPT_S1_j,comdat
.Lfunc_end49:
	.size	_Z7reduce4IfLj256EEvPT_S1_j, .Lfunc_end49-_Z7reduce4IfLj256EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IfLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj128EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj128EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj128EEvPT_S1_j
	.globl	_Z7reduce4IfLj128EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj128EEvPT_S1_j,@function
_Z7reduce4IfLj128EEvPT_S1_j:            ; @_Z7reduce4IfLj128EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB50_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB50_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x80, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB50_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB50_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v5, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB50_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB50_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB50_8
; %bb.7:                                ;   in Loop: Header=BB50_6 Depth=1
	v_lshl_add_u32 v2, s1, 2, v5
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB50_8:                               ;   in Loop: Header=BB50_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB50_10
; %bb.9:                                ;   in Loop: Header=BB50_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB50_6
.LBB50_10:                              ; %Flow99
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB50_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB50_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB50_12
.LBB50_13:                              ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB50_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB50_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj128EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj128EEvPT_S1_j,comdat
.Lfunc_end50:
	.size	_Z7reduce4IfLj128EEvPT_S1_j, .Lfunc_end50-_Z7reduce4IfLj128EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IfLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj64EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj64EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj64EEvPT_S1_j
	.globl	_Z7reduce4IfLj64EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj64EEvPT_S1_j,@function
_Z7reduce4IfLj64EEvPT_S1_j:             ; @_Z7reduce4IfLj64EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB51_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB51_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 64, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB51_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB51_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v5, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB51_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB51_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB51_8
; %bb.7:                                ;   in Loop: Header=BB51_6 Depth=1
	v_lshl_add_u32 v2, s1, 2, v5
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB51_8:                               ;   in Loop: Header=BB51_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB51_10
; %bb.9:                                ;   in Loop: Header=BB51_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB51_6
.LBB51_10:                              ; %Flow99
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB51_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB51_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB51_12
.LBB51_13:                              ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB51_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB51_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj64EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj64EEvPT_S1_j,comdat
.Lfunc_end51:
	.size	_Z7reduce4IfLj64EEvPT_S1_j, .Lfunc_end51-_Z7reduce4IfLj64EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 552
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IfLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj32EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj32EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj32EEvPT_S1_j
	.globl	_Z7reduce4IfLj32EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj32EEvPT_S1_j,@function
_Z7reduce4IfLj32EEvPT_S1_j:             ; @_Z7reduce4IfLj32EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB52_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB52_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 32, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB52_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB52_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB52_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB52_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB52_8
; %bb.7:                                ;   in Loop: Header=BB52_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v3
	ds_store_b32 v2, v4
.LBB52_8:                               ;   in Loop: Header=BB52_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB52_10
; %bb.9:                                ;   in Loop: Header=BB52_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB52_6
.LBB52_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB52_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB52_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB52_12
.LBB52_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB52_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB52_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj32EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj32EEvPT_S1_j,comdat
.Lfunc_end52:
	.size	_Z7reduce4IfLj32EEvPT_S1_j, .Lfunc_end52-_Z7reduce4IfLj32EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IfLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj16EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj16EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj16EEvPT_S1_j
	.globl	_Z7reduce4IfLj16EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj16EEvPT_S1_j,@function
_Z7reduce4IfLj16EEvPT_S1_j:             ; @_Z7reduce4IfLj16EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB53_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB53_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 16, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB53_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB53_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB53_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB53_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB53_8
; %bb.7:                                ;   in Loop: Header=BB53_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v3
	ds_store_b32 v2, v4
.LBB53_8:                               ;   in Loop: Header=BB53_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB53_10
; %bb.9:                                ;   in Loop: Header=BB53_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB53_6
.LBB53_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB53_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB53_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB53_12
.LBB53_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB53_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB53_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj16EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj16EEvPT_S1_j,comdat
.Lfunc_end53:
	.size	_Z7reduce4IfLj16EEvPT_S1_j, .Lfunc_end53-_Z7reduce4IfLj16EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IfLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj8EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj8EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj8EEvPT_S1_j
	.globl	_Z7reduce4IfLj8EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj8EEvPT_S1_j,@function
_Z7reduce4IfLj8EEvPT_S1_j:              ; @_Z7reduce4IfLj8EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB54_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB54_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB54_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB54_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB54_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB54_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB54_8
; %bb.7:                                ;   in Loop: Header=BB54_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v3
	ds_store_b32 v2, v4
.LBB54_8:                               ;   in Loop: Header=BB54_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB54_10
; %bb.9:                                ;   in Loop: Header=BB54_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB54_6
.LBB54_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB54_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB54_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB54_12
.LBB54_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB54_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB54_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj8EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj8EEvPT_S1_j,comdat
.Lfunc_end54:
	.size	_Z7reduce4IfLj8EEvPT_S1_j, .Lfunc_end54-_Z7reduce4IfLj8EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IfLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj4EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj4EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj4EEvPT_S1_j
	.globl	_Z7reduce4IfLj4EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj4EEvPT_S1_j,@function
_Z7reduce4IfLj4EEvPT_S1_j:              ; @_Z7reduce4IfLj4EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB55_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB55_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB55_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB55_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB55_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB55_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB55_8
; %bb.7:                                ;   in Loop: Header=BB55_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v3
	ds_store_b32 v2, v4
.LBB55_8:                               ;   in Loop: Header=BB55_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB55_10
; %bb.9:                                ;   in Loop: Header=BB55_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB55_6
.LBB55_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB55_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB55_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB55_12
.LBB55_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB55_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB55_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj4EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj4EEvPT_S1_j,comdat
.Lfunc_end55:
	.size	_Z7reduce4IfLj4EEvPT_S1_j, .Lfunc_end55-_Z7reduce4IfLj4EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IfLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj2EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj2EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj2EEvPT_S1_j
	.globl	_Z7reduce4IfLj2EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj2EEvPT_S1_j,@function
_Z7reduce4IfLj2EEvPT_S1_j:              ; @_Z7reduce4IfLj2EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB56_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB56_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 2, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB56_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB56_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB56_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB56_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB56_8
; %bb.7:                                ;   in Loop: Header=BB56_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v3
	ds_store_b32 v2, v4
.LBB56_8:                               ;   in Loop: Header=BB56_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB56_10
; %bb.9:                                ;   in Loop: Header=BB56_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB56_6
.LBB56_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB56_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB56_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB56_12
.LBB56_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB56_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB56_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj2EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj2EEvPT_S1_j,comdat
.Lfunc_end56:
	.size	_Z7reduce4IfLj2EEvPT_S1_j, .Lfunc_end56-_Z7reduce4IfLj2EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IfLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj1EEvPT_S1_j,comdat
	.protected	_Z7reduce4IfLj1EEvPT_S1_j ; -- Begin function _Z7reduce4IfLj1EEvPT_S1_j
	.globl	_Z7reduce4IfLj1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IfLj1EEvPT_S1_j,@function
_Z7reduce4IfLj1EEvPT_S1_j:              ; @_Z7reduce4IfLj1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v2, s8, 1, v1
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v2
	s_cbranch_execz .LBB57_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s0, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB57_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB57_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB57_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v2, v1, 2, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB57_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB57_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v1
	s_cbranch_execz .LBB57_8
; %bb.7:                                ;   in Loop: Header=BB57_6 Depth=1
	v_lshl_add_u32 v3, s1, 2, v2
	ds_load_b32 v3, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v3
	ds_store_b32 v2, v4
.LBB57_8:                               ;   in Loop: Header=BB57_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB57_10
; %bb.9:                                ;   in Loop: Header=BB57_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB57_6
.LBB57_10:                              ; %._crit_edge
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v2
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB57_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB57_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB57_12
.LBB57_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB57_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v4, s[0:1]
.LBB57_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IfLj1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IfLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce4IfLj1EEvPT_S1_j,comdat
.Lfunc_end57:
	.size	_Z7reduce4IfLj1EEvPT_S1_j, .Lfunc_end57-_Z7reduce4IfLj1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj512EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj512EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj512EEvPT_S1_j
	.globl	_Z7reduce5IfLj512EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj512EEvPT_S1_j,@function
_Z7reduce5IfLj512EEvPT_S1_j:            ; @_Z7reduce5IfLj512EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v2, s2, 10, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB58_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB58_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x200, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB58_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB58_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s0, s[0:1], 0x24
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v1
	s_cbranch_execz .LBB58_6
; %bb.5:
	ds_load_b32 v2, v5 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB58_6:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB58_8
; %bb.7:
	ds_load_b32 v2, v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB58_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB58_10
; %bb.9:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB58_10:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s1, v2
	s_mov_b32 s1, 16
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB58_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB58_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB58_12
.LBB58_13:                              ; %Flow102
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB58_15
; %bb.14:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB58_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj512EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj512EEvPT_S1_j,comdat
.Lfunc_end58:
	.size	_Z7reduce5IfLj512EEvPT_S1_j, .Lfunc_end58-_Z7reduce5IfLj512EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 624
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj256EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj256EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj256EEvPT_S1_j
	.globl	_Z7reduce5IfLj256EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj256EEvPT_S1_j,@function
_Z7reduce5IfLj256EEvPT_S1_j:            ; @_Z7reduce5IfLj256EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 9, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB59_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB59_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x100, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB59_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB59_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s0, s[0:1], 0x24
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB59_6
; %bb.5:
	ds_load_b32 v2, v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB59_6:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB59_8
; %bb.7:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB59_8:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s1, v2
	s_mov_b32 s1, 16
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB59_11
; %bb.9:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB59_10:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB59_10
.LBB59_11:                              ; %Flow95
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB59_13
; %bb.12:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB59_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj256EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj256EEvPT_S1_j,comdat
.Lfunc_end59:
	.size	_Z7reduce5IfLj256EEvPT_S1_j, .Lfunc_end59-_Z7reduce5IfLj256EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 572
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj128EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj128EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj128EEvPT_S1_j
	.globl	_Z7reduce5IfLj128EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj128EEvPT_S1_j,@function
_Z7reduce5IfLj128EEvPT_S1_j:            ; @_Z7reduce5IfLj128EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 8, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB60_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB60_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v2, 0x80, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB60_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB60_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s0, s[0:1], 0x24
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB60_6
; %bb.5:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB60_6:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s1, v2
	s_mov_b32 s1, 16
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB60_9
; %bb.7:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB60_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB60_8
.LBB60_9:                               ; %Flow88
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB60_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB60_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj128EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj128EEvPT_S1_j,comdat
.Lfunc_end60:
	.size	_Z7reduce5IfLj128EEvPT_S1_j, .Lfunc_end60-_Z7reduce5IfLj128EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 520
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj64EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj64EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj64EEvPT_S1_j
	.globl	_Z7reduce5IfLj64EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj64EEvPT_S1_j,@function
_Z7reduce5IfLj64EEvPT_S1_j:             ; @_Z7reduce5IfLj64EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 7, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB61_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB61_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 64, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB61_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB61_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	s_and_b32 s0, s0, 0xffff
	v_lshl_add_u32 v0, v1, 2, 0
	s_mov_b32 s1, 16
	v_mad_u32_u24 v5, v3, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v4
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, v5, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB61_7
; %bb.5:
	ds_load_b32 v0, v0 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB61_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB61_6
.LBB61_7:                               ; %Flow81
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB61_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB61_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj64EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj64EEvPT_S1_j,comdat
.Lfunc_end61:
	.size	_Z7reduce5IfLj64EEvPT_S1_j, .Lfunc_end61-_Z7reduce5IfLj64EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 476
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj32EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj32EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj32EEvPT_S1_j
	.globl	_Z7reduce5IfLj32EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj32EEvPT_S1_j,@function
_Z7reduce5IfLj32EEvPT_S1_j:             ; @_Z7reduce5IfLj32EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 6, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB62_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB62_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 32, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB62_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB62_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB62_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB62_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB62_6
.LBB62_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB62_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB62_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj32EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj32EEvPT_S1_j,comdat
.Lfunc_end62:
	.size	_Z7reduce5IfLj32EEvPT_S1_j, .Lfunc_end62-_Z7reduce5IfLj32EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj16EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj16EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj16EEvPT_S1_j
	.globl	_Z7reduce5IfLj16EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj16EEvPT_S1_j,@function
_Z7reduce5IfLj16EEvPT_S1_j:             ; @_Z7reduce5IfLj16EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 5, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB63_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB63_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 16, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB63_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB63_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	v_mad_u32_u24 v0, v0, s1, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB63_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_mov_b32 s1, 16
.LBB63_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB63_6
.LBB63_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB63_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB63_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj16EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj16EEvPT_S1_j,comdat
.Lfunc_end63:
	.size	_Z7reduce5IfLj16EEvPT_S1_j, .Lfunc_end63-_Z7reduce5IfLj16EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj8EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj8EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj8EEvPT_S1_j
	.globl	_Z7reduce5IfLj8EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj8EEvPT_S1_j,@function
_Z7reduce5IfLj8EEvPT_S1_j:              ; @_Z7reduce5IfLj8EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 4, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB64_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB64_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 8, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB64_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB64_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB64_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB64_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB64_6
.LBB64_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB64_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB64_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj8EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj8EEvPT_S1_j,comdat
.Lfunc_end64:
	.size	_Z7reduce5IfLj8EEvPT_S1_j, .Lfunc_end64-_Z7reduce5IfLj8EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj4EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj4EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj4EEvPT_S1_j
	.globl	_Z7reduce5IfLj4EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj4EEvPT_S1_j,@function
_Z7reduce5IfLj4EEvPT_S1_j:              ; @_Z7reduce5IfLj4EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 3, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB65_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB65_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 4, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB65_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB65_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB65_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB65_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB65_6
.LBB65_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB65_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB65_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj4EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj4EEvPT_S1_j,comdat
.Lfunc_end65:
	.size	_Z7reduce5IfLj4EEvPT_S1_j, .Lfunc_end65-_Z7reduce5IfLj4EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj2EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj2EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj2EEvPT_S1_j
	.globl	_Z7reduce5IfLj2EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj2EEvPT_S1_j,@function
_Z7reduce5IfLj2EEvPT_S1_j:              ; @_Z7reduce5IfLj2EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 2, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB66_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB66_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 2, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB66_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB66_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB66_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB66_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB66_6
.LBB66_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB66_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB66_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj2EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj2EEvPT_S1_j,comdat
.Lfunc_end66:
	.size	_Z7reduce5IfLj2EEvPT_S1_j, .Lfunc_end66-_Z7reduce5IfLj2EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IfLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj1EEvPT_S1_j,comdat
	.protected	_Z7reduce5IfLj1EEvPT_S1_j ; -- Begin function _Z7reduce5IfLj1EEvPT_S1_j
	.globl	_Z7reduce5IfLj1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IfLj1EEvPT_S1_j,@function
_Z7reduce5IfLj1EEvPT_S1_j:              ; @_Z7reduce5IfLj1EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 1, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB67_2
; %bb.1:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
.LBB67_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v2, 1, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v2
	s_cbranch_execz .LBB67_4
; %bb.3:
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v2
.LBB67_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB67_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB67_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB67_6
.LBB67_7:                               ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB67_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB67_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IfLj1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IfLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce5IfLj1EEvPT_S1_j,comdat
.Lfunc_end67:
	.size	_Z7reduce5IfLj1EEvPT_S1_j, .Lfunc_end67-_Z7reduce5IfLj1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 460
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj512ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj512ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj512ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj512ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj512ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj512ELb1EEvPT_S1_j:        ; @_Z7reduce6IfLj512ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v2, s2, 10, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB68_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 10
	s_mov_b32 s0, 0
.LBB68_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 0x200, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB68_2
; %bb.3:                                ; %Flow111
	s_or_b32 exec_lo, exec_lo, s0
.LBB68_4:                               ; %Flow112
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v1
	s_cbranch_execz .LBB68_6
; %bb.5:
	ds_load_b32 v2, v5 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB68_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB68_8
; %bb.7:
	ds_load_b32 v2, v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB68_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB68_10
; %bb.9:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB68_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB68_13
; %bb.11:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB68_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB68_12
.LBB68_13:                              ; %Flow110
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB68_15
; %bb.14:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB68_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj512ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj512ELb1EEvPT_S1_j,comdat
.Lfunc_end68:
	.size	_Z7reduce6IfLj512ELb1EEvPT_S1_j, .Lfunc_end68-_Z7reduce6IfLj512ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 672
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj256ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj256ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj256ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj256ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj256ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj256ELb1EEvPT_S1_j:        ; @_Z7reduce6IfLj256ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 9, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB69_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 9
	s_mov_b32 s0, 0
.LBB69_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 0x100, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB69_2
; %bb.3:                                ; %Flow104
	s_or_b32 exec_lo, exec_lo, s0
.LBB69_4:                               ; %Flow105
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB69_6
; %bb.5:
	ds_load_b32 v2, v5 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB69_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB69_8
; %bb.7:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB69_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB69_11
; %bb.9:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB69_10:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB69_10
.LBB69_11:                              ; %Flow103
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB69_13
; %bb.12:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB69_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj256ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj256ELb1EEvPT_S1_j,comdat
.Lfunc_end69:
	.size	_Z7reduce6IfLj256ELb1EEvPT_S1_j, .Lfunc_end69-_Z7reduce6IfLj256ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 620
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj128ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj128ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj128ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj128ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj128ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj128ELb1EEvPT_S1_j:        ; @_Z7reduce6IfLj128ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 8, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB70_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 8
	s_mov_b32 s0, 0
.LBB70_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 0x80, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB70_2
; %bb.3:                                ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
.LBB70_4:                               ; %Flow98
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v5, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v5, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB70_6
; %bb.5:
	ds_load_b32 v2, v5 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v2
	ds_store_b32 v5, v4
.LBB70_6:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB70_9
; %bb.7:
	ds_load_b32 v0, v5 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB70_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB70_8
.LBB70_9:                               ; %Flow96
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB70_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB70_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj128ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj128ELb1EEvPT_S1_j,comdat
.Lfunc_end70:
	.size	_Z7reduce6IfLj128ELb1EEvPT_S1_j, .Lfunc_end70-_Z7reduce6IfLj128ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 568
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj64ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj64ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj64ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj64ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj64ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj64ELb1EEvPT_S1_j:         ; @_Z7reduce6IfLj64ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 7, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB71_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 7
	s_mov_b32 s0, 0
.LBB71_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 64, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB71_2
; %bb.3:                                ; %Flow90
	s_or_b32 exec_lo, exec_lo, s0
.LBB71_4:                               ; %Flow91
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v0, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v5, v3, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v0, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v5, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB71_7
; %bb.5:
	ds_load_b32 v0, v0 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB71_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB71_6
.LBB71_7:                               ; %Flow89
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB71_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB71_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj64ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj64ELb1EEvPT_S1_j,comdat
.Lfunc_end71:
	.size	_Z7reduce6IfLj64ELb1EEvPT_S1_j, .Lfunc_end71-_Z7reduce6IfLj64ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 520
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj32ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj32ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj32ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj32ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj32ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj32ELb1EEvPT_S1_j:         ; @_Z7reduce6IfLj32ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 6, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB72_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 6
	s_mov_b32 s0, 0
.LBB72_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 32, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB72_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB72_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB72_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB72_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB72_6
.LBB72_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB72_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB72_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj32ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj32ELb1EEvPT_S1_j,comdat
.Lfunc_end72:
	.size	_Z7reduce6IfLj32ELb1EEvPT_S1_j, .Lfunc_end72-_Z7reduce6IfLj32ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 504
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj16ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj16ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj16ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj16ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj16ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj16ELb1EEvPT_S1_j:         ; @_Z7reduce6IfLj16ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 5, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB73_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 5
	s_mov_b32 s0, 0
.LBB73_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 16, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB73_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB73_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB73_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB73_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB73_6
.LBB73_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB73_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB73_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj16ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj16ELb1EEvPT_S1_j,comdat
.Lfunc_end73:
	.size	_Z7reduce6IfLj16ELb1EEvPT_S1_j, .Lfunc_end73-_Z7reduce6IfLj16ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 504
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj8ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj8ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj8ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj8ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj8ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj8ELb1EEvPT_S1_j:          ; @_Z7reduce6IfLj8ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 4, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB74_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 4
	s_mov_b32 s0, 0
.LBB74_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 8, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB74_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB74_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB74_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB74_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB74_6
.LBB74_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB74_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB74_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj8ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj8ELb1EEvPT_S1_j,comdat
.Lfunc_end74:
	.size	_Z7reduce6IfLj8ELb1EEvPT_S1_j, .Lfunc_end74-_Z7reduce6IfLj8ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 504
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj4ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj4ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj4ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj4ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj4ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj4ELb1EEvPT_S1_j:          ; @_Z7reduce6IfLj4ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 3, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB75_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 3
	s_mov_b32 s0, 0
.LBB75_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 4, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB75_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB75_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB75_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB75_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB75_6
.LBB75_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB75_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB75_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj4ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj4ELb1EEvPT_S1_j,comdat
.Lfunc_end75:
	.size	_Z7reduce6IfLj4ELb1EEvPT_S1_j, .Lfunc_end75-_Z7reduce6IfLj4ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 504
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj2ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj2ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj2ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj2ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj2ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj2ELb1EEvPT_S1_j:          ; @_Z7reduce6IfLj2ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 2, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB76_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 2
	s_mov_b32 s0, 0
.LBB76_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 2, v2
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_clause 0x1
	global_load_b32 v7, v[7:8], off
	global_load_b32 v5, v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v4, v4, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v5
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB76_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB76_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB76_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB76_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB76_6
.LBB76_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB76_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB76_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj2ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj2ELb1EEvPT_S1_j,comdat
.Lfunc_end76:
	.size	_Z7reduce6IfLj2ELb1EEvPT_S1_j, .Lfunc_end76-_Z7reduce6IfLj2ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 504
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj1ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj1ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj1ELb1EEvPT_S1_j
	.globl	_Z7reduce6IfLj1ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj1ELb1EEvPT_S1_j,@function
_Z7reduce6IfLj1ELb1EEvPT_S1_j:          ; @_Z7reduce6IfLj1ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 1, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB77_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 1
	s_mov_b32 s0, 0
.LBB77_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	global_load_b64 v[5:6], v[5:6], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v6
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB77_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB77_4:                               ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB77_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB77_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc1 .LBB77_6
.LBB77_7:                               ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB77_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v4, s[0:1]
.LBB77_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj1ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj1ELb1EEvPT_S1_j,comdat
.Lfunc_end77:
	.size	_Z7reduce6IfLj1ELb1EEvPT_S1_j, .Lfunc_end77-_Z7reduce6IfLj1ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 456
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj512ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj512ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj512ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj512ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj512ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj512ELb0EEvPT_S1_j:        ; @_Z7reduce6IfLj512ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v2, s2, 10, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB78_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 10
	s_mov_b32 s0, 0
.LBB78_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 0x200, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB78_4
; %bb.3:                                ;   in Loop: Header=BB78_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB78_4:                               ;   in Loop: Header=BB78_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB78_2
; %bb.5:                                ; %Flow109
	s_or_b32 exec_lo, exec_lo, s0
.LBB78_6:                               ; %Flow110
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v4, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v4, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v1
	s_cbranch_execz .LBB78_8
; %bb.7:
	ds_load_b32 v2, v4 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v2
	ds_store_b32 v4, v6
.LBB78_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB78_10
; %bb.9:
	ds_load_b32 v2, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v2
	ds_store_b32 v4, v6
.LBB78_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB78_12
; %bb.11:
	ds_load_b32 v2, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v2
	ds_store_b32 v4, v6
.LBB78_12:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB78_15
; %bb.13:
	ds_load_b32 v0, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB78_14:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB78_14
.LBB78_15:                              ; %Flow108
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB78_17
; %bb.16:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB78_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj512ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj512ELb0EEvPT_S1_j,comdat
.Lfunc_end78:
	.size	_Z7reduce6IfLj512ELb0EEvPT_S1_j, .Lfunc_end78-_Z7reduce6IfLj512ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 692
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj256ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj256ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj256ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj256ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj256ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj256ELb0EEvPT_S1_j:        ; @_Z7reduce6IfLj256ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 9, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB79_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 9
	s_mov_b32 s0, 0
.LBB79_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 0x100, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB79_4
; %bb.3:                                ;   in Loop: Header=BB79_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB79_4:                               ;   in Loop: Header=BB79_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB79_2
; %bb.5:                                ; %Flow102
	s_or_b32 exec_lo, exec_lo, s0
.LBB79_6:                               ; %Flow103
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v4, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v4, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v1
	s_cbranch_execz .LBB79_8
; %bb.7:
	ds_load_b32 v2, v4 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v2
	ds_store_b32 v4, v6
.LBB79_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB79_10
; %bb.9:
	ds_load_b32 v2, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v2
	ds_store_b32 v4, v6
.LBB79_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB79_13
; %bb.11:
	ds_load_b32 v0, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB79_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB79_12
.LBB79_13:                              ; %Flow101
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB79_15
; %bb.14:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB79_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj256ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj256ELb0EEvPT_S1_j,comdat
.Lfunc_end79:
	.size	_Z7reduce6IfLj256ELb0EEvPT_S1_j, .Lfunc_end79-_Z7reduce6IfLj256ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 640
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj128ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj128ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj128ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj128ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj128ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj128ELb0EEvPT_S1_j:        ; @_Z7reduce6IfLj128ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 8, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB80_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 8
	s_mov_b32 s0, 0
.LBB80_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 0x80, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB80_4
; %bb.3:                                ;   in Loop: Header=BB80_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB80_4:                               ;   in Loop: Header=BB80_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB80_2
; %bb.5:                                ; %Flow95
	s_or_b32 exec_lo, exec_lo, s0
.LBB80_6:                               ; %Flow96
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v4, v1, 2, 0
	s_mov_b32 s0, exec_lo
	ds_store_b32 v4, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v1
	s_cbranch_execz .LBB80_8
; %bb.7:
	ds_load_b32 v2, v4 offset:256
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v2
	ds_store_b32 v4, v6
.LBB80_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v2
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB80_11
; %bb.9:
	ds_load_b32 v0, v4 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB80_10:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB80_10
.LBB80_11:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB80_13
; %bb.12:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB80_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj128ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj128ELb0EEvPT_S1_j,comdat
.Lfunc_end80:
	.size	_Z7reduce6IfLj128ELb0EEvPT_S1_j, .Lfunc_end80-_Z7reduce6IfLj128ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj64ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj64ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj64ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj64ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj64ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj64ELb0EEvPT_S1_j:         ; @_Z7reduce6IfLj64ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 7, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB81_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 7
	s_mov_b32 s0, 0
.LBB81_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 64, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB81_4
; %bb.3:                                ;   in Loop: Header=BB81_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB81_4:                               ;   in Loop: Header=BB81_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB81_2
; %bb.5:                                ; %Flow88
	s_or_b32 exec_lo, exec_lo, s0
.LBB81_6:                               ; %Flow89
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v0, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v4, v3, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v0, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v4, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB81_9
; %bb.7:
	ds_load_b32 v0, v0 offset:128
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v0
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB81_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB81_8
.LBB81_9:                               ; %Flow87
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB81_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB81_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj64ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj64ELb0EEvPT_S1_j,comdat
.Lfunc_end81:
	.size	_Z7reduce6IfLj64ELb0EEvPT_S1_j, .Lfunc_end81-_Z7reduce6IfLj64ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 540
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj32ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj32ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj32ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj32ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj32ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj32ELb0EEvPT_S1_j:         ; @_Z7reduce6IfLj32ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 6, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB82_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 6
	s_mov_b32 s0, 0
.LBB82_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 32, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB82_4
; %bb.3:                                ;   in Loop: Header=BB82_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB82_4:                               ;   in Loop: Header=BB82_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB82_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB82_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB82_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB82_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB82_8
.LBB82_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB82_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB82_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj32ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj32ELb0EEvPT_S1_j,comdat
.Lfunc_end82:
	.size	_Z7reduce6IfLj32ELb0EEvPT_S1_j, .Lfunc_end82-_Z7reduce6IfLj32ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj16ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj16ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj16ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj16ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj16ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj16ELb0EEvPT_S1_j:         ; @_Z7reduce6IfLj16ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 5, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB83_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 5
	s_mov_b32 s0, 0
.LBB83_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 16, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB83_4
; %bb.3:                                ;   in Loop: Header=BB83_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB83_4:                               ;   in Loop: Header=BB83_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB83_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB83_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB83_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB83_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB83_8
.LBB83_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB83_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB83_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj16ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj16ELb0EEvPT_S1_j,comdat
.Lfunc_end83:
	.size	_Z7reduce6IfLj16ELb0EEvPT_S1_j, .Lfunc_end83-_Z7reduce6IfLj16ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj8ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj8ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj8ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj8ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj8ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj8ELb0EEvPT_S1_j:          ; @_Z7reduce6IfLj8ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 4, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB84_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 4
	s_mov_b32 s0, 0
.LBB84_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 8, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB84_4
; %bb.3:                                ;   in Loop: Header=BB84_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB84_4:                               ;   in Loop: Header=BB84_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB84_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB84_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB84_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB84_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB84_8
.LBB84_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB84_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB84_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj8ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj8ELb0EEvPT_S1_j,comdat
.Lfunc_end84:
	.size	_Z7reduce6IfLj8ELb0EEvPT_S1_j, .Lfunc_end84-_Z7reduce6IfLj8ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj4ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj4ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj4ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj4ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj4ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj4ELb0EEvPT_S1_j:          ; @_Z7reduce6IfLj4ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 3, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB85_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 3
	s_mov_b32 s0, 0
.LBB85_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 4, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB85_4
; %bb.3:                                ;   in Loop: Header=BB85_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB85_4:                               ;   in Loop: Header=BB85_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB85_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB85_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB85_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB85_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB85_8
.LBB85_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB85_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB85_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj4ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj4ELb0EEvPT_S1_j,comdat
.Lfunc_end85:
	.size	_Z7reduce6IfLj4ELb0EEvPT_S1_j, .Lfunc_end85-_Z7reduce6IfLj4ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj2ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj2ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj2ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj2ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj2ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj2ELb0EEvPT_S1_j:          ; @_Z7reduce6IfLj2ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 2, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB86_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 2
	s_mov_b32 s0, 0
.LBB86_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_add_nc_u32_e32 v4, 2, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB86_4
; %bb.3:                                ;   in Loop: Header=BB86_2 Depth=1
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB86_4:                               ;   in Loop: Header=BB86_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB86_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB86_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB86_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB86_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB86_8
.LBB86_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB86_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB86_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj2ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj2ELb0EEvPT_S1_j,comdat
.Lfunc_end86:
	.size	_Z7reduce6IfLj2ELb0EEvPT_S1_j, .Lfunc_end86-_Z7reduce6IfLj2ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IfLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj1ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IfLj1ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IfLj1ELb0EEvPT_S1_j
	.globl	_Z7reduce6IfLj1ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IfLj1ELb0EEvPT_S1_j,@function
_Z7reduce6IfLj1ELb0EEvPT_S1_j:          ; @_Z7reduce6IfLj1ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, s2, 1, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s8, v2
	s_cbranch_execz .LBB87_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 1
	s_mov_b32 s0, 0
.LBB87_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_add_nc_u32_e32 v8, 1, v2
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v7, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v7
	v_cmpx_gt_u32_e64 s8, v8
	s_cbranch_execz .LBB87_4
; %bb.3:                                ;   in Loop: Header=BB87_2 Depth=1
	global_load_b32 v4, v[4:5], off offset:4
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v4
.LBB87_4:                               ;   in Loop: Header=BB87_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v2
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB87_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB87_6:                               ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v3, v1, 2, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v2
	s_and_b32 s1, s3, 0xffff
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[2:3], null, v0, s1, v[1:2]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v2
	s_cbranch_execz .LBB87_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB87_8:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v1
	v_cndmask_b32_e64 v1, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v0, 2
	ds_bpermute_b32 v1, v1, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v1
	s_cbranch_scc1 .LBB87_8
.LBB87_9:                               ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB87_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v0, v6, s[0:1]
.LBB87_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IfLj1ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IfLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IfLj1ELb0EEvPT_S1_j,comdat
.Lfunc_end87:
	.size	_Z7reduce6IfLj1ELb0EEvPT_S1_j, .Lfunc_end87-_Z7reduce6IfLj1ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 492
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce0IdEvPT_S1_j,"axG",@progbits,_Z7reduce0IdEvPT_S1_j,comdat
	.protected	_Z7reduce0IdEvPT_S1_j   ; -- Begin function _Z7reduce0IdEvPT_S1_j
	.globl	_Z7reduce0IdEvPT_S1_j
	.p2align	8
	.type	_Z7reduce0IdEvPT_S1_j,@function
_Z7reduce0IdEvPT_S1_j:                  ; @_Z7reduce0IdEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, s4, s5, v[0:1]
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v3
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB88_2
; %bb.1:
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[3:4]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB88_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v3, v0, 3, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b64 v3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB88_7
; %bb.3:                                ; %.lr.ph.preheader
	s_mov_b32 s1, 1
.LBB88_4:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s1, 1
	s_add_i32 s6, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, s6, v0
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB88_6
; %bb.5:                                ;   in Loop: Header=BB88_4 Depth=1
	v_lshl_add_u32 v1, s1, 3, v3
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v3, v[1:2]
.LBB88_6:                               ;   in Loop: Header=BB88_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s0, s5
	s_mov_b32 s1, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB88_4
.LBB88_7:                               ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB88_9
; %bb.8:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB88_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce0IdEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce0IdEvPT_S1_j,"axG",@progbits,_Z7reduce0IdEvPT_S1_j,comdat
.Lfunc_end88:
	.size	_Z7reduce0IdEvPT_S1_j, .Lfunc_end88-_Z7reduce0IdEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce1IdEvPT_S1_j,"axG",@progbits,_Z7reduce1IdEvPT_S1_j,comdat
	.protected	_Z7reduce1IdEvPT_S1_j   ; -- Begin function _Z7reduce1IdEvPT_S1_j
	.globl	_Z7reduce1IdEvPT_S1_j
	.p2align	8
	.type	_Z7reduce1IdEvPT_S1_j,@function
_Z7reduce1IdEvPT_S1_j:                  ; @_Z7reduce1IdEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, s4, s5, v[0:1]
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v3
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB89_2
; %bb.1:
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[3:4]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB89_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v3, v0, 3, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b64 v3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB89_7
; %bb.3:                                ; %.lr.ph.preheader
	s_mov_b32 s1, 1
.LBB89_4:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_lshl_b32 s0, s1, 1
	s_mov_b32 s6, exec_lo
	v_mul_lo_u32 v1, s0, v0
	v_cmpx_gt_u32_e64 s5, v1
	s_cbranch_execz .LBB89_6
; %bb.5:                                ;   in Loop: Header=BB89_4 Depth=1
	v_lshl_add_u32 v5, v1, 3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v1, s1, 3, v5
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[3:4], v5
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[3:4]
	ds_store_b64 v5, v[1:2]
.LBB89_6:                               ;   in Loop: Header=BB89_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_u32 s0, s5
	s_mov_b32 s1, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB89_4
.LBB89_7:                               ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB89_9
; %bb.8:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB89_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce1IdEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce1IdEvPT_S1_j,"axG",@progbits,_Z7reduce1IdEvPT_S1_j,comdat
.Lfunc_end89:
	.size	_Z7reduce1IdEvPT_S1_j, .Lfunc_end89-_Z7reduce1IdEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 356
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce2IdEvPT_S1_j,"axG",@progbits,_Z7reduce2IdEvPT_S1_j,comdat
	.protected	_Z7reduce2IdEvPT_S1_j   ; -- Begin function _Z7reduce2IdEvPT_S1_j
	.globl	_Z7reduce2IdEvPT_S1_j
	.p2align	8
	.type	_Z7reduce2IdEvPT_S1_j,@function
_Z7reduce2IdEvPT_S1_j:                  ; @_Z7reduce2IdEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, s4, s5, v[0:1]
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s6, v3
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB90_2
; %bb.1:
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[3:4]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB90_2:
	s_or_b32 exec_lo, exec_lo, s6
	v_lshl_add_u32 v3, v0, 3, 0
	s_cmp_lt_u32 s5, 2
	s_waitcnt vmcnt(0)
	ds_store_b64 v3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB90_3:                               ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB90_7
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB90_3 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB90_6
; %bb.5:                                ;   in Loop: Header=BB90_3 Depth=1
	v_lshl_add_u32 v1, s0, 3, v3
	ds_load_b64 v[1:2], v1
	ds_load_b64 v[4:5], v3
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v3, v[1:2]
.LBB90_6:                               ;   in Loop: Header=BB90_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB90_3
.LBB90_7:                               ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB90_9
; %bb.8:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB90_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce2IdEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce2IdEvPT_S1_j,"axG",@progbits,_Z7reduce2IdEvPT_S1_j,comdat
.Lfunc_end90:
	.size	_Z7reduce2IdEvPT_S1_j, .Lfunc_end90-_Z7reduce2IdEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce3IdEvPT_S1_j,"axG",@progbits,_Z7reduce3IdEvPT_S1_j,comdat
	.protected	_Z7reduce3IdEvPT_S1_j   ; -- Begin function _Z7reduce3IdEvPT_S1_j
	.globl	_Z7reduce3IdEvPT_S1_j
	.p2align	8
	.type	_Z7reduce3IdEvPT_S1_j,@function
_Z7reduce3IdEvPT_S1_j:                  ; @_Z7reduce3IdEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s6, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s15, s5
	v_lshl_add_u32 v3, s7, 1, v0
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s6, v3
	s_cbranch_execz .LBB91_2
; %bb.1:
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[3:4]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB91_2:
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v4, s5, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s6, v4
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB91_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB91_4:
	s_or_b32 exec_lo, exec_lo, s6
	v_mov_b32_e32 v5, 0
	s_cmp_lt_u32 s5, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v4, v5
	v_lshlrev_b64 v[6:7], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[1:2], off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB91_9
.LBB91_5:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB91_7
; %bb.6:                                ;   in Loop: Header=BB91_5 Depth=1
	v_add_nc_u32_e32 v4, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_add_co_u32 v8, vcc_lo, s2, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	global_store_b64 v[6:7], v[1:2], off
.LBB91_7:                               ;   in Loop: Header=BB91_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_lt_u32 s5, 4
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB91_9
; %bb.8:                                ;   in Loop: Header=BB91_5 Depth=1
	s_mov_b32 s5, s0
	s_branch .LBB91_5
.LBB91_9:                               ; %Flow43
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB91_11
; %bb.10:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB91_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce3IdEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce3IdEvPT_S1_j,"axG",@progbits,_Z7reduce3IdEvPT_S1_j,comdat
.Lfunc_end91:
	.size	_Z7reduce3IdEvPT_S1_j, .Lfunc_end91-_Z7reduce3IdEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 448
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7reduce4IdLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj512EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj512EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj512EEvPT_S1_j
	.globl	_Z7reduce4IdLj512EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj512EEvPT_S1_j,@function
_Z7reduce4IdLj512EEvPT_S1_j:            ; @_Z7reduce4IdLj512EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB92_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB92_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 0x200, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB92_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB92_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v6, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB92_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB92_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB92_8
; %bb.7:                                ;   in Loop: Header=BB92_6 Depth=1
	v_lshl_add_u32 v4, s1, 3, v6
	ds_load_b64 v[4:5], v4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB92_8:                               ;   in Loop: Header=BB92_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB92_10
; %bb.9:                                ;   in Loop: Header=BB92_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB92_6
.LBB92_10:                              ; %Flow99
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB92_13
; %bb.11:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB92_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB92_12
.LBB92_13:                              ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB92_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB92_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj512EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj512EEvPT_S1_j,comdat
.Lfunc_end92:
	.size	_Z7reduce4IdLj512EEvPT_S1_j, .Lfunc_end92-_Z7reduce4IdLj512EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IdLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj256EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj256EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj256EEvPT_S1_j
	.globl	_Z7reduce4IdLj256EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj256EEvPT_S1_j,@function
_Z7reduce4IdLj256EEvPT_S1_j:            ; @_Z7reduce4IdLj256EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB93_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB93_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 0x100, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB93_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB93_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v6, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB93_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB93_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB93_8
; %bb.7:                                ;   in Loop: Header=BB93_6 Depth=1
	v_lshl_add_u32 v4, s1, 3, v6
	ds_load_b64 v[4:5], v4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB93_8:                               ;   in Loop: Header=BB93_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB93_10
; %bb.9:                                ;   in Loop: Header=BB93_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB93_6
.LBB93_10:                              ; %Flow99
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB93_13
; %bb.11:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB93_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB93_12
.LBB93_13:                              ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB93_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB93_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj256EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj256EEvPT_S1_j,comdat
.Lfunc_end93:
	.size	_Z7reduce4IdLj256EEvPT_S1_j, .Lfunc_end93-_Z7reduce4IdLj256EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IdLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj128EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj128EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj128EEvPT_S1_j
	.globl	_Z7reduce4IdLj128EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj128EEvPT_S1_j,@function
_Z7reduce4IdLj128EEvPT_S1_j:            ; @_Z7reduce4IdLj128EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB94_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB94_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 0x80, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB94_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB94_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v6, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB94_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB94_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB94_8
; %bb.7:                                ;   in Loop: Header=BB94_6 Depth=1
	v_lshl_add_u32 v4, s1, 3, v6
	ds_load_b64 v[4:5], v4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB94_8:                               ;   in Loop: Header=BB94_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB94_10
; %bb.9:                                ;   in Loop: Header=BB94_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB94_6
.LBB94_10:                              ; %Flow99
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB94_13
; %bb.11:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB94_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB94_12
.LBB94_13:                              ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB94_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB94_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj128EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj128EEvPT_S1_j,comdat
.Lfunc_end94:
	.size	_Z7reduce4IdLj128EEvPT_S1_j, .Lfunc_end94-_Z7reduce4IdLj128EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IdLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj64EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj64EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj64EEvPT_S1_j
	.globl	_Z7reduce4IdLj64EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj64EEvPT_S1_j,@function
_Z7reduce4IdLj64EEvPT_S1_j:             ; @_Z7reduce4IdLj64EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB95_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB95_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 64, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB95_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB95_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v6, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB95_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB95_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB95_8
; %bb.7:                                ;   in Loop: Header=BB95_6 Depth=1
	v_lshl_add_u32 v4, s1, 3, v6
	ds_load_b64 v[4:5], v4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB95_8:                               ;   in Loop: Header=BB95_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB95_10
; %bb.9:                                ;   in Loop: Header=BB95_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB95_6
.LBB95_10:                              ; %Flow99
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB95_13
; %bb.11:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB95_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB95_12
.LBB95_13:                              ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB95_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB95_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj64EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj64EEvPT_S1_j,comdat
.Lfunc_end95:
	.size	_Z7reduce4IdLj64EEvPT_S1_j, .Lfunc_end95-_Z7reduce4IdLj64EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IdLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj32EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj32EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj32EEvPT_S1_j
	.globl	_Z7reduce4IdLj32EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj32EEvPT_S1_j,@function
_Z7reduce4IdLj32EEvPT_S1_j:             ; @_Z7reduce4IdLj32EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB96_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB96_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 32, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB96_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB96_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v4, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v4, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB96_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB96_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB96_8
; %bb.7:                                ;   in Loop: Header=BB96_6 Depth=1
	v_lshl_add_u32 v5, s1, 3, v4
	ds_load_b64 v[5:6], v5
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	ds_store_b64 v4, v[1:2]
.LBB96_8:                               ;   in Loop: Header=BB96_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB96_10
; %bb.9:                                ;   in Loop: Header=BB96_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB96_6
.LBB96_10:                              ; %._crit_edge
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB96_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB96_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB96_12
.LBB96_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB96_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB96_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj32EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj32EEvPT_S1_j,comdat
.Lfunc_end96:
	.size	_Z7reduce4IdLj32EEvPT_S1_j, .Lfunc_end96-_Z7reduce4IdLj32EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IdLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj16EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj16EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj16EEvPT_S1_j
	.globl	_Z7reduce4IdLj16EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj16EEvPT_S1_j,@function
_Z7reduce4IdLj16EEvPT_S1_j:             ; @_Z7reduce4IdLj16EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB97_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB97_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 16, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB97_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB97_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v4, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v4, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB97_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB97_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB97_8
; %bb.7:                                ;   in Loop: Header=BB97_6 Depth=1
	v_lshl_add_u32 v5, s1, 3, v4
	ds_load_b64 v[5:6], v5
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	ds_store_b64 v4, v[1:2]
.LBB97_8:                               ;   in Loop: Header=BB97_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB97_10
; %bb.9:                                ;   in Loop: Header=BB97_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB97_6
.LBB97_10:                              ; %._crit_edge
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB97_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB97_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB97_12
.LBB97_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB97_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB97_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj16EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj16EEvPT_S1_j,comdat
.Lfunc_end97:
	.size	_Z7reduce4IdLj16EEvPT_S1_j, .Lfunc_end97-_Z7reduce4IdLj16EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IdLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj8EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj8EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj8EEvPT_S1_j
	.globl	_Z7reduce4IdLj8EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj8EEvPT_S1_j,@function
_Z7reduce4IdLj8EEvPT_S1_j:              ; @_Z7reduce4IdLj8EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB98_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB98_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 8, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB98_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB98_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v4, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v4, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB98_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB98_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB98_8
; %bb.7:                                ;   in Loop: Header=BB98_6 Depth=1
	v_lshl_add_u32 v5, s1, 3, v4
	ds_load_b64 v[5:6], v5
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	ds_store_b64 v4, v[1:2]
.LBB98_8:                               ;   in Loop: Header=BB98_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB98_10
; %bb.9:                                ;   in Loop: Header=BB98_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB98_6
.LBB98_10:                              ; %._crit_edge
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB98_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB98_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB98_12
.LBB98_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB98_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB98_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj8EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj8EEvPT_S1_j,comdat
.Lfunc_end98:
	.size	_Z7reduce4IdLj8EEvPT_S1_j, .Lfunc_end98-_Z7reduce4IdLj8EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IdLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj4EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj4EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj4EEvPT_S1_j
	.globl	_Z7reduce4IdLj4EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj4EEvPT_S1_j,@function
_Z7reduce4IdLj4EEvPT_S1_j:              ; @_Z7reduce4IdLj4EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB99_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB99_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 4, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB99_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB99_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v4, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v4, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB99_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB99_6:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB99_8
; %bb.7:                                ;   in Loop: Header=BB99_6 Depth=1
	v_lshl_add_u32 v5, s1, 3, v4
	ds_load_b64 v[5:6], v5
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	ds_store_b64 v4, v[1:2]
.LBB99_8:                               ;   in Loop: Header=BB99_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB99_10
; %bb.9:                                ;   in Loop: Header=BB99_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB99_6
.LBB99_10:                              ; %._crit_edge
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB99_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB99_12:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB99_12
.LBB99_13:                              ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB99_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB99_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj4EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj4EEvPT_S1_j,comdat
.Lfunc_end99:
	.size	_Z7reduce4IdLj4EEvPT_S1_j, .Lfunc_end99-_Z7reduce4IdLj4EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IdLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj2EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj2EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj2EEvPT_S1_j
	.globl	_Z7reduce4IdLj2EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj2EEvPT_S1_j,@function
_Z7reduce4IdLj2EEvPT_S1_j:              ; @_Z7reduce4IdLj2EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB100_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB100_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB100_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB100_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v4, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v4, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB100_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB100_6:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB100_8
; %bb.7:                                ;   in Loop: Header=BB100_6 Depth=1
	v_lshl_add_u32 v5, s1, 3, v4
	ds_load_b64 v[5:6], v5
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	ds_store_b64 v4, v[1:2]
.LBB100_8:                              ;   in Loop: Header=BB100_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB100_10
; %bb.9:                                ;   in Loop: Header=BB100_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB100_6
.LBB100_10:                             ; %._crit_edge
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB100_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB100_12:                             ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB100_12
.LBB100_13:                             ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB100_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB100_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj2EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj2EEvPT_S1_j,comdat
.Lfunc_end100:
	.size	_Z7reduce4IdLj2EEvPT_S1_j, .Lfunc_end100-_Z7reduce4IdLj2EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce4IdLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj1EEvPT_S1_j,comdat
	.protected	_Z7reduce4IdLj1EEvPT_S1_j ; -- Begin function _Z7reduce4IdLj1EEvPT_S1_j
	.globl	_Z7reduce4IdLj1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce4IdLj1EEvPT_S1_j,@function
_Z7reduce4IdLj1EEvPT_S1_j:              ; @_Z7reduce4IdLj1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s5, s[0:1], 0x24
	s_load_b32 s7, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s15, s6
	v_lshl_add_u32 v4, s8, 1, v3
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s7, v4
	s_cbranch_execz .LBB101_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB101_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 1, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s7, v4
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB101_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB101_4:
	s_or_b32 exec_lo, exec_lo, s7
	v_lshl_add_u32 v4, v3, 3, 0
	s_cmpk_lt_u32 s6, 0x42
	s_waitcnt vmcnt(0)
	ds_store_b64 v4, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB101_10
; %bb.5:
	s_mov_b32 s0, s6
.LBB101_6:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s1, s0, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_u32_e64 s1, v3
	s_cbranch_execz .LBB101_8
; %bb.7:                                ;   in Loop: Header=BB101_6 Depth=1
	v_lshl_add_u32 v5, s1, 3, v4
	ds_load_b64 v[5:6], v5
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	ds_store_b64 v4, v[1:2]
.LBB101_8:                              ;   in Loop: Header=BB101_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_cmpk_lt_u32 s0, 0x84
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB101_10
; %bb.9:                                ;   in Loop: Header=BB101_6 Depth=1
	s_mov_b32 s0, s1
	s_branch .LBB101_6
.LBB101_10:                             ; %._crit_edge
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s5, 16
	s_mov_b32 s1, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v0, s0, v4
	s_mov_b32 s0, exec_lo
	v_mad_u64_u32 v[4:5], null, v0, s6, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB101_13
; %bb.11:                               ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB101_12:                             ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s5, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB101_12
.LBB101_13:                             ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB101_15
; %bb.14:
	s_lshl_b64 s[0:1], s[4:5], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB101_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce4IdLj1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce4IdLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce4IdLj1EEvPT_S1_j,comdat
.Lfunc_end101:
	.size	_Z7reduce4IdLj1EEvPT_S1_j, .Lfunc_end101-_Z7reduce4IdLj1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj512EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj512EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj512EEvPT_S1_j
	.globl	_Z7reduce5IdLj512EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj512EEvPT_S1_j,@function
_Z7reduce5IdLj512EEvPT_S1_j:            ; @_Z7reduce5IdLj512EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_or_b32 v4, s2, 10, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB102_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB102_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 0x200, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v4
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB102_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB102_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s0, s[0:1], 0x24
	v_lshl_add_u32 v6, v3, 3, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v3
	s_cbranch_execz .LBB102_6
; %bb.5:
	ds_load_b64 v[4:5], v6 offset:2048
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB102_6:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v3
	s_cbranch_execz .LBB102_8
; %bb.7:
	ds_load_b64 v[4:5], v6 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB102_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v3
	s_cbranch_execz .LBB102_10
; %bb.9:
	ds_load_b64 v[4:5], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB102_10:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s1, v4
	s_mov_b32 s1, 16
	buffer_gl0_inv
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB102_13
; %bb.11:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB102_12:                             ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB102_12
.LBB102_13:                             ; %Flow102
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB102_15
; %bb.14:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB102_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj512EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj512EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj512EEvPT_S1_j,comdat
.Lfunc_end102:
	.size	_Z7reduce5IdLj512EEvPT_S1_j, .Lfunc_end102-_Z7reduce5IdLj512EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 660
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj256EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj256EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj256EEvPT_S1_j
	.globl	_Z7reduce5IdLj256EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj256EEvPT_S1_j,@function
_Z7reduce5IdLj256EEvPT_S1_j:            ; @_Z7reduce5IdLj256EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_add_u32 v4, s2, 9, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB103_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB103_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 0x100, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v4
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB103_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB103_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s0, s[0:1], 0x24
	v_lshl_add_u32 v6, v3, 3, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v3
	s_cbranch_execz .LBB103_6
; %bb.5:
	ds_load_b64 v[4:5], v6 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB103_6:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v3
	s_cbranch_execz .LBB103_8
; %bb.7:
	ds_load_b64 v[4:5], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB103_8:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s1, v4
	s_mov_b32 s1, 16
	buffer_gl0_inv
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB103_11
; %bb.9:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB103_10:                             ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB103_10
.LBB103_11:                             ; %Flow95
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB103_13
; %bb.12:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB103_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj256EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj256EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj256EEvPT_S1_j,comdat
.Lfunc_end103:
	.size	_Z7reduce5IdLj256EEvPT_S1_j, .Lfunc_end103-_Z7reduce5IdLj256EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 604
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj128EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj128EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj128EEvPT_S1_j
	.globl	_Z7reduce5IdLj128EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj128EEvPT_S1_j,@function
_Z7reduce5IdLj128EEvPT_S1_j:            ; @_Z7reduce5IdLj128EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_add_u32 v4, s2, 8, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB104_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB104_2:
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v4, 0x80, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v4
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB104_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB104_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b32 s0, s[0:1], 0x24
	v_lshl_add_u32 v6, v3, 3, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v3
	s_cbranch_execz .LBB104_6
; %bb.5:
	ds_load_b64 v[4:5], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB104_6:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s1, v4
	s_mov_b32 s1, 16
	buffer_gl0_inv
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB104_9
; %bb.7:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB104_8:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB104_8
.LBB104_9:                              ; %Flow88
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB104_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB104_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj128EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj128EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj128EEvPT_S1_j,comdat
.Lfunc_end104:
	.size	_Z7reduce5IdLj128EEvPT_S1_j, .Lfunc_end104-_Z7reduce5IdLj128EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 548
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj64EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj64EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj64EEvPT_S1_j
	.globl	_Z7reduce5IdLj64EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj64EEvPT_S1_j,@function
_Z7reduce5IdLj64EEvPT_S1_j:             ; @_Z7reduce5IdLj64EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_add_u32 v4, s2, 7, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB105_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB105_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s1, s[0:1], 0x24
	v_add_nc_u32_e32 v4, 64, v4
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB105_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB105_4:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v5, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s1, 16
	s_and_b32 s1, s1, 0xffff
	v_lshl_add_u32 v0, v3, 3, 0
	s_mov_b32 s0, 16
	v_mad_u32_u24 v6, v5, s3, v4
	s_waitcnt vmcnt(0)
	ds_store_b64 v0, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[4:5], null, v6, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB105_7
; %bb.5:
	ds_load_b64 v[5:6], v0 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB105_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB105_6
.LBB105_7:                              ; %Flow81
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB105_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB105_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj64EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj64EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj64EEvPT_S1_j,comdat
.Lfunc_end105:
	.size	_Z7reduce5IdLj64EEvPT_S1_j, .Lfunc_end105-_Z7reduce5IdLj64EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj32EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj32EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj32EEvPT_S1_j
	.globl	_Z7reduce5IdLj32EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj32EEvPT_S1_j,@function
_Z7reduce5IdLj32EEvPT_S1_j:             ; @_Z7reduce5IdLj32EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_add_u32 v4, s2, 6, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB106_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB106_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v4, 32, v4
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB106_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB106_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v4
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB106_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB106_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB106_6
.LBB106_7:                              ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB106_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB106_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj32EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj32EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj32EEvPT_S1_j,comdat
.Lfunc_end106:
	.size	_Z7reduce5IdLj32EEvPT_S1_j, .Lfunc_end106-_Z7reduce5IdLj32EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 480
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj16EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj16EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj16EEvPT_S1_j
	.globl	_Z7reduce5IdLj16EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj16EEvPT_S1_j,@function
_Z7reduce5IdLj16EEvPT_S1_j:             ; @_Z7reduce5IdLj16EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_add_u32 v4, s2, 5, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB107_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB107_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v4, 16, v4
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB107_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB107_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_and_b32 s0, s0, 0xffff
	v_mad_u32_u24 v0, v0, s1, v4
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB107_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_mov_b32 s1, 16
.LBB107_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB107_6
.LBB107_7:                              ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB107_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB107_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj16EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj16EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj16EEvPT_S1_j,comdat
.Lfunc_end107:
	.size	_Z7reduce5IdLj16EEvPT_S1_j, .Lfunc_end107-_Z7reduce5IdLj16EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 480
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj8EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj8EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj8EEvPT_S1_j
	.globl	_Z7reduce5IdLj8EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj8EEvPT_S1_j,@function
_Z7reduce5IdLj8EEvPT_S1_j:              ; @_Z7reduce5IdLj8EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_add_u32 v4, s2, 4, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB108_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB108_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v4, 8, v4
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB108_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB108_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v4
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB108_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB108_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB108_6
.LBB108_7:                              ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB108_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB108_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj8EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj8EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj8EEvPT_S1_j,comdat
.Lfunc_end108:
	.size	_Z7reduce5IdLj8EEvPT_S1_j, .Lfunc_end108-_Z7reduce5IdLj8EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 480
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj4EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj4EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj4EEvPT_S1_j
	.globl	_Z7reduce5IdLj4EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj4EEvPT_S1_j,@function
_Z7reduce5IdLj4EEvPT_S1_j:              ; @_Z7reduce5IdLj4EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_add_u32 v4, s2, 3, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB109_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB109_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v4, 4, v4
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB109_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB109_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v4
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB109_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB109_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB109_6
.LBB109_7:                              ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB109_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB109_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj4EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj4EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj4EEvPT_S1_j,comdat
.Lfunc_end109:
	.size	_Z7reduce5IdLj4EEvPT_S1_j, .Lfunc_end109-_Z7reduce5IdLj4EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 480
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj2EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj2EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj2EEvPT_S1_j
	.globl	_Z7reduce5IdLj2EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj2EEvPT_S1_j,@function
_Z7reduce5IdLj2EEvPT_S1_j:              ; @_Z7reduce5IdLj2EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_add_u32 v4, s2, 2, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB110_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB110_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v4, 2, v4
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB110_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB110_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v4
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB110_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB110_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB110_6
.LBB110_7:                              ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB110_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB110_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj2EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj2EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj2EEvPT_S1_j,comdat
.Lfunc_end110:
	.size	_Z7reduce5IdLj2EEvPT_S1_j, .Lfunc_end110-_Z7reduce5IdLj2EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 480
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce5IdLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj1EEvPT_S1_j,comdat
	.protected	_Z7reduce5IdLj1EEvPT_S1_j ; -- Begin function _Z7reduce5IdLj1EEvPT_S1_j
	.globl	_Z7reduce5IdLj1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce5IdLj1EEvPT_S1_j,@function
_Z7reduce5IdLj1EEvPT_S1_j:              ; @_Z7reduce5IdLj1EEvPT_S1_j
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s8, exec_lo
	v_lshl_add_u32 v4, s2, 1, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB111_2
; %bb.1:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[4:5]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
.LBB111_2:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b32 s0, s[0:1], 0x24
	v_add_nc_u32_e32 v4, 1, v4
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s3, v4
	s_cbranch_execz .LBB111_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
.LBB111_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s0, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 16
	v_mad_u32_u24 v0, v0, s3, v4
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB111_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB111_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB111_6
.LBB111_7:                              ; %Flow78
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB111_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB111_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce5IdLj1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce5IdLj1EEvPT_S1_j,"axG",@progbits,_Z7reduce5IdLj1EEvPT_S1_j,comdat
.Lfunc_end111:
	.size	_Z7reduce5IdLj1EEvPT_S1_j, .Lfunc_end111-_Z7reduce5IdLj1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 480
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj512ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj512ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj512ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj512ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj512ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj512ELb1EEvPT_S1_j:        ; @_Z7reduce6IdLj512ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_or_b32 v4, s2, 10, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB112_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 10
	s_mov_b32 s0, 0
.LBB112_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v8, 0x200, v4
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b64 v[8:9], v[8:9], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB112_2
; %bb.3:                                ; %Flow111
	s_or_b32 exec_lo, exec_lo, s0
.LBB112_4:                              ; %Flow112
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v6, v3, 3, 0
	s_mov_b32 s0, exec_lo
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v3
	s_cbranch_execz .LBB112_6
; %bb.5:
	ds_load_b64 v[4:5], v6 offset:2048
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB112_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v3
	s_cbranch_execz .LBB112_8
; %bb.7:
	ds_load_b64 v[4:5], v6 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB112_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v3
	s_cbranch_execz .LBB112_10
; %bb.9:
	ds_load_b64 v[4:5], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB112_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v4
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB112_13
; %bb.11:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB112_12:                             ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB112_12
.LBB112_13:                             ; %Flow110
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB112_15
; %bb.14:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB112_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj512ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj512ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj512ELb1EEvPT_S1_j,comdat
.Lfunc_end112:
	.size	_Z7reduce6IdLj512ELb1EEvPT_S1_j, .Lfunc_end112-_Z7reduce6IdLj512ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 708
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj256ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj256ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj256ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj256ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj256ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj256ELb1EEvPT_S1_j:        ; @_Z7reduce6IdLj256ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 9, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB113_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 9
	s_mov_b32 s0, 0
.LBB113_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v8, 0x100, v4
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b64 v[8:9], v[8:9], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB113_2
; %bb.3:                                ; %Flow104
	s_or_b32 exec_lo, exec_lo, s0
.LBB113_4:                              ; %Flow105
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v6, v3, 3, 0
	s_mov_b32 s0, exec_lo
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v3
	s_cbranch_execz .LBB113_6
; %bb.5:
	ds_load_b64 v[4:5], v6 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB113_6:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v3
	s_cbranch_execz .LBB113_8
; %bb.7:
	ds_load_b64 v[4:5], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB113_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v4
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB113_11
; %bb.9:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB113_10:                             ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB113_10
.LBB113_11:                             ; %Flow103
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB113_13
; %bb.12:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB113_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj256ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj256ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj256ELb1EEvPT_S1_j,comdat
.Lfunc_end113:
	.size	_Z7reduce6IdLj256ELb1EEvPT_S1_j, .Lfunc_end113-_Z7reduce6IdLj256ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 652
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj128ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj128ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj128ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj128ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj128ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj128ELb1EEvPT_S1_j:        ; @_Z7reduce6IdLj128ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 8, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB114_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 8
	s_mov_b32 s0, 0
.LBB114_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v8, 0x80, v4
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b64 v[8:9], v[8:9], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB114_2
; %bb.3:                                ; %Flow97
	s_or_b32 exec_lo, exec_lo, s0
.LBB114_4:                              ; %Flow98
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v6, v3, 3, 0
	s_mov_b32 s0, exec_lo
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v3
	s_cbranch_execz .LBB114_6
; %bb.5:
	ds_load_b64 v[4:5], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB114_6:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v4
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB114_9
; %bb.7:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB114_8:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB114_8
.LBB114_9:                              ; %Flow96
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB114_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB114_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj128ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj128ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj128ELb1EEvPT_S1_j,comdat
.Lfunc_end114:
	.size	_Z7reduce6IdLj128ELb1EEvPT_S1_j, .Lfunc_end114-_Z7reduce6IdLj128ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 596
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj64ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj64ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj64ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj64ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj64ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj64ELb1EEvPT_S1_j:         ; @_Z7reduce6IdLj64ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 7, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB115_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 7
	s_mov_b32 s0, 0
.LBB115_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v8, 64, v4
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b64 v[8:9], v[8:9], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB115_2
; %bb.3:                                ; %Flow90
	s_or_b32 exec_lo, exec_lo, s0
.LBB115_4:                              ; %Flow91
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v5, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v0, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v6, v5, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v0, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v6, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB115_7
; %bb.5:
	ds_load_b64 v[5:6], v0 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB115_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB115_6
.LBB115_7:                              ; %Flow89
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB115_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB115_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj64ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj64ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj64ELb1EEvPT_S1_j,comdat
.Lfunc_end115:
	.size	_Z7reduce6IdLj64ELb1EEvPT_S1_j, .Lfunc_end115-_Z7reduce6IdLj64ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 544
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj32ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj32ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj32ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj32ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj32ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj32ELb1EEvPT_S1_j:         ; @_Z7reduce6IdLj32ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 6, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB116_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 6
	s_mov_b32 s0, 0
.LBB116_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v8, 32, v4
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b64 v[8:9], v[8:9], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB116_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB116_4:                              ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB116_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB116_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB116_6
.LBB116_7:                              ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB116_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB116_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj32ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj32ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj32ELb1EEvPT_S1_j,comdat
.Lfunc_end116:
	.size	_Z7reduce6IdLj32ELb1EEvPT_S1_j, .Lfunc_end116-_Z7reduce6IdLj32ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj16ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj16ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj16ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj16ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj16ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj16ELb1EEvPT_S1_j:         ; @_Z7reduce6IdLj16ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 5, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB117_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 5
	s_mov_b32 s0, 0
.LBB117_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v8, 16, v4
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b64 v[8:9], v[8:9], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB117_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB117_4:                              ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB117_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB117_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB117_6
.LBB117_7:                              ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB117_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB117_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj16ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj16ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj16ELb1EEvPT_S1_j,comdat
.Lfunc_end117:
	.size	_Z7reduce6IdLj16ELb1EEvPT_S1_j, .Lfunc_end117-_Z7reduce6IdLj16ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj8ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj8ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj8ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj8ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj8ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj8ELb1EEvPT_S1_j:          ; @_Z7reduce6IdLj8ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 4, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB118_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 4
	s_mov_b32 s0, 0
.LBB118_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v8, 8, v4
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b64 v[8:9], v[8:9], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB118_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB118_4:                              ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB118_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB118_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB118_6
.LBB118_7:                              ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB118_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB118_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj8ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj8ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj8ELb1EEvPT_S1_j,comdat
.Lfunc_end118:
	.size	_Z7reduce6IdLj8ELb1EEvPT_S1_j, .Lfunc_end118-_Z7reduce6IdLj8ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj4ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj4ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj4ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj4ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj4ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj4ELb1EEvPT_S1_j:          ; @_Z7reduce6IdLj4ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 3, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB119_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 3
	s_mov_b32 s0, 0
.LBB119_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v8, 4, v4
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b64 v[8:9], v[8:9], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB119_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB119_4:                              ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB119_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB119_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB119_6
.LBB119_7:                              ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB119_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB119_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj4ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj4ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj4ELb1EEvPT_S1_j,comdat
.Lfunc_end119:
	.size	_Z7reduce6IdLj4ELb1EEvPT_S1_j, .Lfunc_end119-_Z7reduce6IdLj4ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj2ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj2ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj2ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj2ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj2ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj2ELb1EEvPT_S1_j:          ; @_Z7reduce6IdLj2ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 2, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB120_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 2
	s_mov_b32 s0, 0
.LBB120_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v8, 2, v4
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v8, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b64 v[8:9], v[8:9], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB120_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB120_4:                              ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB120_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB120_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB120_6
.LBB120_7:                              ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB120_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB120_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj2ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj2ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj2ELb1EEvPT_S1_j,comdat
.Lfunc_end120:
	.size	_Z7reduce6IdLj2ELb1EEvPT_S1_j, .Lfunc_end120-_Z7reduce6IdLj2ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj1ELb1EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj1ELb1EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj1ELb1EEvPT_S1_j
	.globl	_Z7reduce6IdLj1ELb1EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj1ELb1EEvPT_S1_j,@function
_Z7reduce6IdLj1ELb1EEvPT_S1_j:          ; @_Z7reduce6IdLj1ELb1EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 1, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB121_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 1
	s_mov_b32 s0, 0
.LBB121_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	global_load_b128 v[6:9], v[6:7], off
	s_or_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB121_2
; %bb.3:                                ; %Flow87
	s_or_b32 exec_lo, exec_lo, s0
.LBB121_4:                              ; %Flow88
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB121_7
; %bb.5:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB121_6:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB121_6
.LBB121_7:                              ; %Flow86
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB121_9
; %bb.8:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB121_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj1ELb1EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj1ELb1EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj1ELb1EEvPT_S1_j,comdat
.Lfunc_end121:
	.size	_Z7reduce6IdLj1ELb1EEvPT_S1_j, .Lfunc_end121-_Z7reduce6IdLj1ELb1EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 484
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj512ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj512ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj512ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj512ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj512ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj512ELb0EEvPT_S1_j:        ; @_Z7reduce6IdLj512ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_or_b32 v4, s2, 10, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB122_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 10
	s_mov_b32 s0, 0
.LBB122_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	v_add_nc_u32_e32 v6, 0x200, v4
	v_cmpx_gt_u32_e64 s8, v6
	s_cbranch_execz .LBB122_4
; %bb.3:                                ;   in Loop: Header=BB122_2 Depth=1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB122_4:                              ;   in Loop: Header=BB122_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB122_2
; %bb.5:                                ; %Flow109
	s_or_b32 exec_lo, exec_lo, s0
.LBB122_6:                              ; %Flow110
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v6, v3, 3, 0
	s_mov_b32 s0, exec_lo
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x100, v3
	s_cbranch_execz .LBB122_8
; %bb.7:
	ds_load_b64 v[4:5], v6 offset:2048
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB122_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v3
	s_cbranch_execz .LBB122_10
; %bb.9:
	ds_load_b64 v[4:5], v6 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB122_10:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v3
	s_cbranch_execz .LBB122_12
; %bb.11:
	ds_load_b64 v[4:5], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB122_12:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v4
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB122_15
; %bb.13:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB122_14:                             ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB122_14
.LBB122_15:                             ; %Flow108
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB122_17
; %bb.16:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB122_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj512ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj512ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj512ELb0EEvPT_S1_j,comdat
.Lfunc_end122:
	.size	_Z7reduce6IdLj512ELb0EEvPT_S1_j, .Lfunc_end122-_Z7reduce6IdLj512ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 736
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj256ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj256ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj256ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj256ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj256ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj256ELb0EEvPT_S1_j:        ; @_Z7reduce6IdLj256ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 9, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB123_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 9
	s_mov_b32 s0, 0
.LBB123_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	v_add_nc_u32_e32 v6, 0x100, v4
	v_cmpx_gt_u32_e64 s8, v6
	s_cbranch_execz .LBB123_4
; %bb.3:                                ;   in Loop: Header=BB123_2 Depth=1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB123_4:                              ;   in Loop: Header=BB123_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB123_2
; %bb.5:                                ; %Flow102
	s_or_b32 exec_lo, exec_lo, s0
.LBB123_6:                              ; %Flow103
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v6, v3, 3, 0
	s_mov_b32 s0, exec_lo
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 0x80, v3
	s_cbranch_execz .LBB123_8
; %bb.7:
	ds_load_b64 v[4:5], v6 offset:1024
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB123_8:
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v3
	s_cbranch_execz .LBB123_10
; %bb.9:
	ds_load_b64 v[4:5], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB123_10:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v4
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB123_13
; %bb.11:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB123_12:                             ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB123_12
.LBB123_13:                             ; %Flow101
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB123_15
; %bb.14:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB123_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj256ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj256ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj256ELb0EEvPT_S1_j,comdat
.Lfunc_end123:
	.size	_Z7reduce6IdLj256ELb0EEvPT_S1_j, .Lfunc_end123-_Z7reduce6IdLj256ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 680
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj128ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj128ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj128ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj128ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj128ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj128ELb0EEvPT_S1_j:        ; @_Z7reduce6IdLj128ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 8, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB124_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 8
	s_mov_b32 s0, 0
.LBB124_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	v_add_nc_u32_e32 v6, 0x80, v4
	v_cmpx_gt_u32_e64 s8, v6
	s_cbranch_execz .LBB124_4
; %bb.3:                                ;   in Loop: Header=BB124_2 Depth=1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB124_4:                              ;   in Loop: Header=BB124_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB124_2
; %bb.5:                                ; %Flow95
	s_or_b32 exec_lo, exec_lo, s0
.LBB124_6:                              ; %Flow96
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v6, v3, 3, 0
	s_mov_b32 s0, exec_lo
	ds_store_b64 v6, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 64, v3
	s_cbranch_execz .LBB124_8
; %bb.7:
	ds_load_b64 v[4:5], v6 offset:512
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[4:5]
	ds_store_b64 v6, v[1:2]
.LBB124_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s0, s3, 16
	s_mov_b32 s1, 16
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u32_u24 v0, v0, s0, v4
	s_and_b32 s0, s3, 0xffff
	buffer_gl0_inv
	v_mad_u64_u32 v[4:5], null, v0, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB124_11
; %bb.9:
	ds_load_b64 v[5:6], v6 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB124_10:                             ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v0
	s_lshr_b32 s3, s1, 1
	s_cmp_gt_u32 s1, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s1, vcc_lo
	s_mov_b32 s1, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB124_10
.LBB124_11:                             ; %Flow94
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB124_13
; %bb.12:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB124_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj128ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj128ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj128ELb0EEvPT_S1_j,comdat
.Lfunc_end124:
	.size	_Z7reduce6IdLj128ELb0EEvPT_S1_j, .Lfunc_end124-_Z7reduce6IdLj128ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 624
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj64ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj64ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj64ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj64ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj64ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj64ELb0EEvPT_S1_j:         ; @_Z7reduce6IdLj64ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 7, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB125_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 7
	s_mov_b32 s0, 0
.LBB125_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	v_add_nc_u32_e32 v6, 64, v4
	v_cmpx_gt_u32_e64 s8, v6
	s_cbranch_execz .LBB125_4
; %bb.3:                                ;   in Loop: Header=BB125_2 Depth=1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB125_4:                              ;   in Loop: Header=BB125_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB125_2
; %bb.5:                                ; %Flow88
	s_or_b32 exec_lo, exec_lo, s0
.LBB125_6:                              ; %Flow89
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v5, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v0, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v6, v5, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v0, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v6, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB125_9
; %bb.7:
	ds_load_b64 v[5:6], v0 offset:256
	v_mbcnt_lo_u32_b32 v0, -1, 0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB125_8:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB125_8
.LBB125_9:                              ; %Flow87
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB125_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB125_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj64ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj64ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj64ELb0EEvPT_S1_j,comdat
.Lfunc_end125:
	.size	_Z7reduce6IdLj64ELb0EEvPT_S1_j, .Lfunc_end125-_Z7reduce6IdLj64ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 572
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj32ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj32ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj32ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj32ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj32ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj32ELb0EEvPT_S1_j:         ; @_Z7reduce6IdLj32ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 6, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB126_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 6
	s_mov_b32 s0, 0
.LBB126_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	v_add_nc_u32_e32 v6, 32, v4
	v_cmpx_gt_u32_e64 s8, v6
	s_cbranch_execz .LBB126_4
; %bb.3:                                ;   in Loop: Header=BB126_2 Depth=1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB126_4:                              ;   in Loop: Header=BB126_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB126_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB126_6:                              ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB126_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB126_8:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB126_8
.LBB126_9:                              ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB126_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB126_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj32ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj32ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj32ELb0EEvPT_S1_j,comdat
.Lfunc_end126:
	.size	_Z7reduce6IdLj32ELb0EEvPT_S1_j, .Lfunc_end126-_Z7reduce6IdLj32ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 552
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj16ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj16ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj16ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj16ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj16ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj16ELb0EEvPT_S1_j:         ; @_Z7reduce6IdLj16ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 5, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB127_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 5
	s_mov_b32 s0, 0
.LBB127_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	v_add_nc_u32_e32 v6, 16, v4
	v_cmpx_gt_u32_e64 s8, v6
	s_cbranch_execz .LBB127_4
; %bb.3:                                ;   in Loop: Header=BB127_2 Depth=1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB127_4:                              ;   in Loop: Header=BB127_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB127_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB127_6:                              ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB127_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB127_8:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB127_8
.LBB127_9:                              ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB127_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB127_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj16ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj16ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj16ELb0EEvPT_S1_j,comdat
.Lfunc_end127:
	.size	_Z7reduce6IdLj16ELb0EEvPT_S1_j, .Lfunc_end127-_Z7reduce6IdLj16ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 552
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj8ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj8ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj8ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj8ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj8ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj8ELb0EEvPT_S1_j:          ; @_Z7reduce6IdLj8ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 4, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB128_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 4
	s_mov_b32 s0, 0
.LBB128_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	v_add_nc_u32_e32 v6, 8, v4
	v_cmpx_gt_u32_e64 s8, v6
	s_cbranch_execz .LBB128_4
; %bb.3:                                ;   in Loop: Header=BB128_2 Depth=1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB128_4:                              ;   in Loop: Header=BB128_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB128_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB128_6:                              ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB128_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB128_8:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB128_8
.LBB128_9:                              ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB128_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB128_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj8ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj8ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj8ELb0EEvPT_S1_j,comdat
.Lfunc_end128:
	.size	_Z7reduce6IdLj8ELb0EEvPT_S1_j, .Lfunc_end128-_Z7reduce6IdLj8ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 552
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj4ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj4ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj4ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj4ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj4ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj4ELb0EEvPT_S1_j:          ; @_Z7reduce6IdLj4ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 3, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB129_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 3
	s_mov_b32 s0, 0
.LBB129_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	v_add_nc_u32_e32 v6, 4, v4
	v_cmpx_gt_u32_e64 s8, v6
	s_cbranch_execz .LBB129_4
; %bb.3:                                ;   in Loop: Header=BB129_2 Depth=1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB129_4:                              ;   in Loop: Header=BB129_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB129_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB129_6:                              ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB129_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB129_8:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB129_8
.LBB129_9:                              ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB129_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB129_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj4ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj4ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj4ELb0EEvPT_S1_j,comdat
.Lfunc_end129:
	.size	_Z7reduce6IdLj4ELb0EEvPT_S1_j, .Lfunc_end129-_Z7reduce6IdLj4ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 552
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj2ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj2ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj2ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj2ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj2ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj2ELb0EEvPT_S1_j:          ; @_Z7reduce6IdLj2ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 2, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB130_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 2
	s_mov_b32 s0, 0
.LBB130_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
	v_add_nc_u32_e32 v6, 2, v4
	v_cmpx_gt_u32_e64 s8, v6
	s_cbranch_execz .LBB130_4
; %bb.3:                                ;   in Loop: Header=BB130_2 Depth=1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB130_4:                              ;   in Loop: Header=BB130_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB130_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB130_6:                              ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB130_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB130_8:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB130_8
.LBB130_9:                              ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB130_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB130_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj2ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj2ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj2ELb0EEvPT_S1_j,comdat
.Lfunc_end130:
	.size	_Z7reduce6IdLj2ELb0EEvPT_S1_j, .Lfunc_end130-_Z7reduce6IdLj2ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 552
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.section	.text._Z7reduce6IdLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj1ELb0EEvPT_S1_j,comdat
	.protected	_Z7reduce6IdLj1ELb0EEvPT_S1_j ; -- Begin function _Z7reduce6IdLj1ELb0EEvPT_S1_j
	.globl	_Z7reduce6IdLj1ELb0EEvPT_S1_j
	.p2align	8
	.type	_Z7reduce6IdLj1ELb0EEvPT_S1_j,@function
_Z7reduce6IdLj1ELb0EEvPT_S1_j:          ; @_Z7reduce6IdLj1ELb0EEvPT_S1_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v3, 0x3ff, v0
	s_mov_b32 s2, s15
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s0, 24
	v_lshl_add_u32 v4, s2, 1, v3
	s_addc_u32 s1, s1, 0
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s8, v4
	s_cbranch_execz .LBB131_6
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s1, s0, 1
	s_mov_b32 s0, 0
.LBB131_2:                              ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	s_mov_b32 s10, exec_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[8:9], v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[8:9]
	v_add_nc_u32_e32 v8, 1, v4
	v_cmpx_gt_u32_e64 s8, v8
	s_cbranch_execz .LBB131_4
; %bb.3:                                ;   in Loop: Header=BB131_2 Depth=1
	global_load_b64 v[6:7], v[6:7], off offset:8
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[6:7]
.LBB131_4:                              ;   in Loop: Header=BB131_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, s1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s8, v4
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB131_2
; %bb.5:                                ; %Flow85
	s_or_b32 exec_lo, exec_lo, s0
.LBB131_6:                              ; %Flow86
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_lshr_b32 s1, s3, 16
	v_lshl_add_u32 v5, v3, 3, 0
	s_mov_b32 s0, 16
	s_delay_alu instid0(VALU_DEP_2)
	v_mad_u32_u24 v0, v0, s1, v4
	s_and_b32 s1, s3, 0xffff
	ds_store_b64 v5, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mad_u64_u32 v[4:5], null, v0, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v4
	s_cbranch_execz .LBB131_9
; %bb.7:                                ; %.preheader
	v_mbcnt_lo_u32_b32 v0, -1, 0
.LBB131_8:                              ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s0, v0
	s_lshr_b32 s3, s0, 1
	s_cmp_gt_u32 s0, 1
	v_cmp_gt_u32_e32 vcc_lo, 32, v3
	v_cndmask_b32_e64 v3, 0, s0, vcc_lo
	s_mov_b32 s0, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v3, v3, v0, 2
	ds_bpermute_b32 v5, v3, v1
	ds_bpermute_b32 v6, v3, v2
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[5:6]
	s_cbranch_scc1 .LBB131_8
.LBB131_9:                              ; %Flow84
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB131_11
; %bb.10:
	s_lshl_b64 s[0:1], s[2:3], 3
	v_mov_b32_e32 v0, 0
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b64 v0, v[1:2], s[0:1]
.LBB131_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce6IdLj1ELb0EEvPT_S1_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7reduce6IdLj1ELb0EEvPT_S1_j,"axG",@progbits,_Z7reduce6IdLj1ELb0EEvPT_S1_j,comdat
.Lfunc_end131:
	.size	_Z7reduce6IdLj1ELb0EEvPT_S1_j, .Lfunc_end131-_Z7reduce6IdLj1ELb0EEvPT_S1_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 520
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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        .offset:         0
        .size:           8
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      - .address_space:  global
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        .value_kind:     hidden_block_count_z
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        .size:           2
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        .size:           2
        .value_kind:     hidden_remainder_z
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        .size:           8
        .value_kind:     hidden_global_offset_x
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        .size:           8
        .value_kind:     hidden_global_offset_y
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        .value_kind:     hidden_global_offset_z
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        .size:           2
        .value_kind:     hidden_grid_dims
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        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7reduce0IiEvPT_S1_j
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7reduce0IiEvPT_S1_j.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
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    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7reduce1IiEvPT_S1_j
    .private_segment_fixed_size: 0
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    .sgpr_spill_count: 0
    .symbol:         _Z7reduce1IiEvPT_S1_j.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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    .language_version:
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    .vgpr_count:     4
    .vgpr_spill_count: 0
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    .language_version:
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    .vgpr_count:     9
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amdhsa.version:
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...

	.end_amdgpu_metadata
