/*
 * Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <thrust/complex.h>

///////////////////////////////////////////////////////////////////////////////
//                              UPFIRDN1D                                    //
///////////////////////////////////////////////////////////////////////////////

template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
                                 const T *__restrict__ h_trans_flip,
                                 const int up,
                                 const int down,
                                 const int axis,
                                 const int x_shape_a,
                                 const int h_per_phase,
                                 const int padded_len,
                                 T *__restrict__ out,
                                 const int outW ) {

    const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
    const int stride { static_cast<int>( blockDim.x * gridDim.x ) };

    for ( size_t tid = t; tid < outW; tid += stride ) {

#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
        __builtin_assume( padded_len > 0 );
        __builtin_assume( up > 0 );
        __builtin_assume( down > 0 );
        __builtin_assume( tid > 0 );
#endif

        const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
        int       h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
        int       x_conv_idx { x_idx - h_per_phase + 1 };

        if ( x_conv_idx < 0 ) {
            h_idx -= x_conv_idx;
            x_conv_idx = 0;
        }

        T temp {};

        int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );

        for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
            temp += inp[x_c] * h_trans_flip[h_idx];
            h_idx += 1;
        }
        out[tid] = temp;
    }
}

extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
                                                                             const float *__restrict__ h_trans_flip,
                                                                             const int up,
                                                                             const int down,
                                                                             const int axis,
                                                                             const int x_shape_a,
                                                                             const int h_per_phase,
                                                                             const int padded_len,
                                                                             float *__restrict__ out,
                                                                             const int outW ) {
    _cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}

extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
                                                                             const double *__restrict__ h_trans_flip,
                                                                             const int up,
                                                                             const int down,
                                                                             const int axis,
                                                                             const int x_shape_a,
                                                                             const int h_per_phase,
                                                                             const int padded_len,
                                                                             double *__restrict__ out,
                                                                             const int outW ) {
    _cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}

extern "C" __global__ void __launch_bounds__( 512 )
    _cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
                               const thrust::complex<float> *__restrict__ h_trans_flip,
                               const int up,
                               const int down,
                               const int axis,
                               const int x_shape_a,
                               const int h_per_phase,
                               const int padded_len,
                               thrust::complex<float> *__restrict__ out,
                               const int outW ) {
    _cupy_upfirdn1D<thrust::complex<float>>(
        inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}

extern "C" __global__ void __launch_bounds__( 512 )
    _cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
                                const thrust::complex<double> *__restrict__ h_trans_flip,
                                const int up,
                                const int down,
                                const int axis,
                                const int x_shape_a,
                                const int h_per_phase,
                                const int padded_len,
                                thrust::complex<double> *__restrict__ out,
                                const int outW ) {
    _cupy_upfirdn1D<thrust::complex<double>>(
        inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}

///////////////////////////////////////////////////////////////////////////////
//                              UPFIRDN2D                                    //
///////////////////////////////////////////////////////////////////////////////

template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
                                 const int inpH,
                                 const T *__restrict__ h_trans_flip,
                                 const int up,
                                 const int down,
                                 const int axis,
                                 const int x_shape_a,
                                 const int h_per_phase,
                                 const int padded_len,
                                 T *__restrict__ out,
                                 const int outW,
                                 const int outH ) {

    const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
    const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };

    const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
    const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };

    for ( int x = tx; x < outH; x += stride_x ) {
        for ( int y = ty; y < outW; y += stride_y ) {
            int x_idx {};
            int h_idx {};

#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
            __builtin_assume( padded_len > 0 );
            __builtin_assume( up > 0 );
            __builtin_assume( down > 0 );
#endif

            if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
                __builtin_assume( x > 0 );
#endif
                x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
                h_idx = ( x * down ) % up * h_per_phase;
            } else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
                __builtin_assume( y > 0 );
#endif
                x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
                h_idx = ( y * down ) % up * h_per_phase;
            }

            int x_conv_idx { x_idx - h_per_phase + 1 };
            if ( x_conv_idx < 0 ) {
                h_idx -= x_conv_idx;
                x_conv_idx = 0;
            }

            T temp {};

            int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );

            for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
                if ( axis == 1 ) {
                    temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
                } else {
                    temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
                }
                h_idx += 1;
            }
            out[y * outH + x] = temp;
        }
    }
}

extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
                                                                            const int inpH,
                                                                            const float *__restrict__ h_trans_flip,
                                                                            const int up,
                                                                            const int down,
                                                                            const int axis,
                                                                            const int x_shape_a,
                                                                            const int h_per_phase,
                                                                            const int padded_len,
                                                                            float *__restrict__ out,
                                                                            const int outW,
                                                                            const int outH ) {
    _cupy_upfirdn2D<float>(
        inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}

extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
                                                                            const int inpH,
                                                                            const double *__restrict__ h_trans_flip,
                                                                            const int up,
                                                                            const int down,
                                                                            const int axis,
                                                                            const int x_shape_a,
                                                                            const int h_per_phase,
                                                                            const int padded_len,
                                                                            double *__restrict__ out,
                                                                            const int outW,
                                                                            const int outH ) {
    _cupy_upfirdn2D<double>(
        inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}

extern "C" __global__ void __launch_bounds__( 64 )
    _cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
                               const int inpH,
                               const thrust::complex<float> *__restrict__ h_trans_flip,
                               const int up,
                               const int down,
                               const int axis,
                               const int x_shape_a,
                               const int h_per_phase,
                               const int padded_len,
                               thrust::complex<float> *__restrict__ out,
                               const int outW,
                               const int outH ) {
    _cupy_upfirdn2D<thrust::complex<float>>(
        inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}

extern "C" __global__ void __launch_bounds__( 64 )
    _cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
                                const int inpH,
                                const thrust::complex<double> *__restrict__ h_trans_flip,
                                const int up,
                                const int down,
                                const int axis,
                                const int x_shape_a,
                                const int h_per_phase,
                                const int padded_len,
                                thrust::complex<double> *__restrict__ out,
                                const int outW,
                                const int outH ) {
    _cupy_upfirdn2D<thrust::complex<double>>(
        inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}

	.file	"tmpxft_002ae731_00000000-6__upfirdn.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5944:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE5944:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi
	.type	_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi, @function
_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi:
.LFB5966:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	224(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 32(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_cupy_upfirdn1D_float32(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 224
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5966:
	.size	_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi, .-_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi
	.globl	_cupy_upfirdn1D_float32
	.type	_cupy_upfirdn1D_float32, @function
_cupy_upfirdn1D_float32:
.LFB5967:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi
	.cfi_endproc
.LFE5967:
	.size	_cupy_upfirdn1D_float32, .-_cupy_upfirdn1D_float32
	.globl	_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi
	.type	_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi, @function
_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi:
.LFB5968:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	224(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 32(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_cupy_upfirdn1D_float64(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 224
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L8:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5968:
	.size	_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi, .-_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi
	.globl	_cupy_upfirdn1D_float64
	.type	_cupy_upfirdn1D_float64, @function
_cupy_upfirdn1D_float64:
.LFB5969:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi
	.cfi_endproc
.LFE5969:
	.size	_cupy_upfirdn1D_float64, .-_cupy_upfirdn1D_float64
	.globl	_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_i
	.type	_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_i, @function
_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_i:
.LFB5970:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	224(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 32(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_cupy_upfirdn1D_complex64(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 224
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L13:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5970:
	.size	_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_i, .-_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_i
	.globl	_cupy_upfirdn1D_complex64
	.type	_cupy_upfirdn1D_complex64, @function
_cupy_upfirdn1D_complex64:
.LFB5971:
	.cfi_startproc
	endbr64
	jmp	_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIfEES4_iiiiiiPS2_i
	.cfi_endproc
.LFE5971:
	.size	_cupy_upfirdn1D_complex64, .-_cupy_upfirdn1D_complex64
	.globl	_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_i
	.type	_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_i, @function
_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_i:
.LFB5972:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	224(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 32(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_cupy_upfirdn1D_complex128(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 224
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L18:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5972:
	.size	_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_i, .-_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_i
	.globl	_cupy_upfirdn1D_complex128
	.type	_cupy_upfirdn1D_complex128, @function
_cupy_upfirdn1D_complex128:
.LFB5973:
	.cfi_startproc
	endbr64
	jmp	_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_890_NS7complexIdEES4_iiiiiiPS2_i
	.cfi_endproc
.LFE5973:
	.size	_cupy_upfirdn1D_complex128, .-_cupy_upfirdn1D_complex128
	.globl	_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii
	.type	_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii, @function
_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii:
.LFB5974:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	%esi, 12(%rsp)
	leaq	68(%rsp), %rsi
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rax, 32(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	48(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_cupy_upfirdn2D_float32(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 240
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L23:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5974:
	.size	_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii, .-_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii
	.globl	_cupy_upfirdn2D_float32
	.type	_cupy_upfirdn2D_float32, @function
_cupy_upfirdn2D_float32:
.LFB5975:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii
	.cfi_endproc
.LFE5975:
	.size	_cupy_upfirdn2D_float32, .-_cupy_upfirdn2D_float32
	.globl	_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii
	.type	_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii, @function
_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii:
.LFB5976:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	%esi, 12(%rsp)
	leaq	68(%rsp), %rsi
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rax, 32(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	48(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_cupy_upfirdn2D_float64(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 240
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L28:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5976:
	.size	_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii, .-_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii
	.globl	_cupy_upfirdn2D_float64
	.type	_cupy_upfirdn2D_float64, @function
_cupy_upfirdn2D_float64:
.LFB5977:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii
	.cfi_endproc
.LFE5977:
	.size	_cupy_upfirdn2D_float64, .-_cupy_upfirdn2D_float64
	.globl	_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_ii
	.type	_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_ii, @function
_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_ii:
.LFB5978:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	%esi, 12(%rsp)
	leaq	68(%rsp), %rsi
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rax, 32(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	48(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_cupy_upfirdn2D_complex64(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 240
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L33:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5978:
	.size	_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_ii, .-_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_ii
	.globl	_cupy_upfirdn2D_complex64
	.type	_cupy_upfirdn2D_complex64, @function
_cupy_upfirdn2D_complex64:
.LFB5979:
	.cfi_startproc
	endbr64
	jmp	_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIfEEiS4_iiiiiiPS2_ii
	.cfi_endproc
.LFE5979:
	.size	_cupy_upfirdn2D_complex64, .-_cupy_upfirdn2D_complex64
	.globl	_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_ii
	.type	_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_ii, @function
_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_ii:
.LFB5980:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	%esi, 12(%rsp)
	leaq	68(%rsp), %rsi
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rax, 32(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	48(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_cupy_upfirdn2D_complex128(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 240
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L38:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5980:
	.size	_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_ii, .-_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_ii
	.globl	_cupy_upfirdn2D_complex128
	.type	_cupy_upfirdn2D_complex128, @function
_cupy_upfirdn2D_complex128:
.LFB5981:
	.cfi_startproc
	endbr64
	jmp	_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_890_NS7complexIdEEiS4_iiiiiiPS2_ii
	.cfi_endproc
.LFE5981:
	.size	_cupy_upfirdn2D_complex128, .-_cupy_upfirdn2D_complex128
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_cupy_upfirdn2D_complex128"
.LC1:
	.string	"_cupy_upfirdn2D_complex64"
.LC2:
	.string	"_cupy_upfirdn2D_float64"
.LC3:
	.string	"_cupy_upfirdn2D_float32"
.LC4:
	.string	"_cupy_upfirdn1D_complex128"
.LC5:
	.string	"_cupy_upfirdn1D_complex64"
.LC6:
	.string	"_cupy_upfirdn1D_float64"
.LC7:
	.string	"_cupy_upfirdn1D_float32"
.LC8:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__45__cpo5beginE"
.LC9:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__45__cpo3endE"
.LC10:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__45__cpo6cbeginE"
.LC11:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__45__cpo4cendE"
.LC12:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE"
.LC13:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__419piecewise_constructE"
.LC14:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std3__48in_placeE"
.LC15:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std6ranges3__45__cpo4swapE"
.LC16:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std6ranges3__45__cpo9iter_moveE"
.LC17:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955904cuda3std6ranges3__45__cpo7advanceE"
.LC18:
	.string	"_ZN42_INTERNAL_bbb21a88_11__upfirdn_cu_c38955906thrust20THRUST_200700_890_NS6system6detail10sequential3seqE"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5983:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_cupy_upfirdn2D_complex128(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_cupy_upfirdn2D_complex64(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_cupy_upfirdn2D_float64(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_cupy_upfirdn2D_float32(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_cupy_upfirdn1D_complex128(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_cupy_upfirdn1D_complex64(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_cupy_upfirdn1D_float64(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_cupy_upfirdn1D_float32(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	movl	$1, %r9d
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__48in_placeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE5983:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata
	.type	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo7advanceE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
	.zero	1
	.hidden	_ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE
	.weak	_ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE
	.section	.rodata._ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE,"aG",@progbits,_ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE,comdat
	.type	_ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE, @gnu_unique_object
	.size	_ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE, 1
_ZN4cuda3std3__444_GLOBAL__N__bbb21a88_11__upfirdn_cu_c38955906ignoreE:
	.zero	1
	.weak	_ZN4cuda3std3__48in_placeE
	.section	.rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
	.type	_ZN4cuda3std3__48in_placeE, @gnu_unique_object
	.size	_ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo4cendE
	.section	.rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
	.type	_ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo6cbeginE
	.section	.rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
	.type	_ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo3endE
	.section	.rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
	.type	_ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo5beginE
	.section	.rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
	.type	_ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
	.zero	1
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */


#include <hip/hip_runtime.h>
#include <thrust/complex.h>

///////////////////////////////////////////////////////////////////////////////
//                              UPFIRDN1D                                    //
///////////////////////////////////////////////////////////////////////////////

template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
                                 const T *__restrict__ h_trans_flip,
                                 const int up,
                                 const int down,
                                 const int axis,
                                 const int x_shape_a,
                                 const int h_per_phase,
                                 const int padded_len,
                                 T *__restrict__ out,
                                 const int outW ) {

    const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
    const int stride { static_cast<int>( blockDim.x * gridDim.x ) };

    for ( size_t tid = t; tid < outW; tid += stride ) {

#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
        __builtin_assume( padded_len > 0 );
        __builtin_assume( up > 0 );
        __builtin_assume( down > 0 );
        __builtin_assume( tid > 0 );
#endif

        const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
        int       h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
        int       x_conv_idx { x_idx - h_per_phase + 1 };

        if ( x_conv_idx < 0 ) {
            h_idx -= x_conv_idx;
            x_conv_idx = 0;
        }

        T temp {};

        int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );

        for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
            temp += inp[x_c] * h_trans_flip[h_idx];
            h_idx += 1;
        }
        out[tid] = temp;
    }
}

extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
                                                                             const float *__restrict__ h_trans_flip,
                                                                             const int up,
                                                                             const int down,
                                                                             const int axis,
                                                                             const int x_shape_a,
                                                                             const int h_per_phase,
                                                                             const int padded_len,
                                                                             float *__restrict__ out,
                                                                             const int outW ) {
    _cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}

extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
                                                                             const double *__restrict__ h_trans_flip,
                                                                             const int up,
                                                                             const int down,
                                                                             const int axis,
                                                                             const int x_shape_a,
                                                                             const int h_per_phase,
                                                                             const int padded_len,
                                                                             double *__restrict__ out,
                                                                             const int outW ) {
    _cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}

extern "C" __global__ void __launch_bounds__( 512 )
    _cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
                               const thrust::complex<float> *__restrict__ h_trans_flip,
                               const int up,
                               const int down,
                               const int axis,
                               const int x_shape_a,
                               const int h_per_phase,
                               const int padded_len,
                               thrust::complex<float> *__restrict__ out,
                               const int outW ) {
    _cupy_upfirdn1D<thrust::complex<float>>(
        inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}

extern "C" __global__ void __launch_bounds__( 512 )
    _cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
                                const thrust::complex<double> *__restrict__ h_trans_flip,
                                const int up,
                                const int down,
                                const int axis,
                                const int x_shape_a,
                                const int h_per_phase,
                                const int padded_len,
                                thrust::complex<double> *__restrict__ out,
                                const int outW ) {
    _cupy_upfirdn1D<thrust::complex<double>>(
        inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}

///////////////////////////////////////////////////////////////////////////////
//                              UPFIRDN2D                                    //
///////////////////////////////////////////////////////////////////////////////

template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
                                 const int inpH,
                                 const T *__restrict__ h_trans_flip,
                                 const int up,
                                 const int down,
                                 const int axis,
                                 const int x_shape_a,
                                 const int h_per_phase,
                                 const int padded_len,
                                 T *__restrict__ out,
                                 const int outW,
                                 const int outH ) {

    const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
    const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };

    const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
    const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };

    for ( int x = tx; x < outH; x += stride_x ) {
        for ( int y = ty; y < outW; y += stride_y ) {
            int x_idx {};
            int h_idx {};

#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
            __builtin_assume( padded_len > 0 );
            __builtin_assume( up > 0 );
            __builtin_assume( down > 0 );
#endif

            if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
                __builtin_assume( x > 0 );
#endif
                x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
                h_idx = ( x * down ) % up * h_per_phase;
            } else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
                __builtin_assume( y > 0 );
#endif
                x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
                h_idx = ( y * down ) % up * h_per_phase;
            }

            int x_conv_idx { x_idx - h_per_phase + 1 };
            if ( x_conv_idx < 0 ) {
                h_idx -= x_conv_idx;
                x_conv_idx = 0;
            }

            T temp {};

            int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );

            for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
                if ( axis == 1 ) {
                    temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
                } else {
                    temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
                }
                h_idx += 1;
            }
            out[y * outH + x] = temp;
        }
    }
}

extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
                                                                            const int inpH,
                                                                            const float *__restrict__ h_trans_flip,
                                                                            const int up,
                                                                            const int down,
                                                                            const int axis,
                                                                            const int x_shape_a,
                                                                            const int h_per_phase,
                                                                            const int padded_len,
                                                                            float *__restrict__ out,
                                                                            const int outW,
                                                                            const int outH ) {
    _cupy_upfirdn2D<float>(
        inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}

extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
                                                                            const int inpH,
                                                                            const double *__restrict__ h_trans_flip,
                                                                            const int up,
                                                                            const int down,
                                                                            const int axis,
                                                                            const int x_shape_a,
                                                                            const int h_per_phase,
                                                                            const int padded_len,
                                                                            double *__restrict__ out,
                                                                            const int outW,
                                                                            const int outH ) {
    _cupy_upfirdn2D<double>(
        inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}

extern "C" __global__ void __launch_bounds__( 64 )
    _cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
                               const int inpH,
                               const thrust::complex<float> *__restrict__ h_trans_flip,
                               const int up,
                               const int down,
                               const int axis,
                               const int x_shape_a,
                               const int h_per_phase,
                               const int padded_len,
                               thrust::complex<float> *__restrict__ out,
                               const int outW,
                               const int outH ) {
    _cupy_upfirdn2D<thrust::complex<float>>(
        inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}

extern "C" __global__ void __launch_bounds__( 64 )
    _cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
                                const int inpH,
                                const thrust::complex<double> *__restrict__ h_trans_flip,
                                const int up,
                                const int down,
                                const int axis,
                                const int x_shape_a,
                                const int h_per_phase,
                                const int padded_len,
                                thrust::complex<double> *__restrict__ out,
                                const int outW,
                                const int outH ) {
    _cupy_upfirdn2D<thrust::complex<double>>(
        inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}

	.text
	.file	"_upfirdn.hip"
	.globl	__device_stub___cupy_upfirdn1D_float32 # -- Begin function __device_stub___cupy_upfirdn1D_float32
	.type	__device_stub___cupy_upfirdn1D_float32,@function
__device_stub___cupy_upfirdn1D_float32: # @__device_stub___cupy_upfirdn1D_float32
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_cupy_upfirdn1D_float32, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub___cupy_upfirdn1D_float32, .Lfunc_end0-__device_stub___cupy_upfirdn1D_float32
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub___cupy_upfirdn1D_float64 # -- Begin function __device_stub___cupy_upfirdn1D_float64
	.type	__device_stub___cupy_upfirdn1D_float64,@function
__device_stub___cupy_upfirdn1D_float64: # @__device_stub___cupy_upfirdn1D_float64
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_cupy_upfirdn1D_float64, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub___cupy_upfirdn1D_float64, .Lfunc_end1-__device_stub___cupy_upfirdn1D_float64
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub___cupy_upfirdn1D_complex64 # -- Begin function __device_stub___cupy_upfirdn1D_complex64
	.type	__device_stub___cupy_upfirdn1D_complex64,@function
__device_stub___cupy_upfirdn1D_complex64: # @__device_stub___cupy_upfirdn1D_complex64
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_cupy_upfirdn1D_complex64, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub___cupy_upfirdn1D_complex64, .Lfunc_end2-__device_stub___cupy_upfirdn1D_complex64
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub___cupy_upfirdn1D_complex128 # -- Begin function __device_stub___cupy_upfirdn1D_complex128
	.type	__device_stub___cupy_upfirdn1D_complex128,@function
__device_stub___cupy_upfirdn1D_complex128: # @__device_stub___cupy_upfirdn1D_complex128
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_cupy_upfirdn1D_complex128, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub___cupy_upfirdn1D_complex128, .Lfunc_end3-__device_stub___cupy_upfirdn1D_complex128
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub___cupy_upfirdn2D_float32 # -- Begin function __device_stub___cupy_upfirdn2D_float32
	.type	__device_stub___cupy_upfirdn2D_float32,@function
__device_stub___cupy_upfirdn2D_float32: # @__device_stub___cupy_upfirdn2D_float32
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_cupy_upfirdn2D_float32, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	__device_stub___cupy_upfirdn2D_float32, .Lfunc_end4-__device_stub___cupy_upfirdn2D_float32
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub___cupy_upfirdn2D_float64 # -- Begin function __device_stub___cupy_upfirdn2D_float64
	.type	__device_stub___cupy_upfirdn2D_float64,@function
__device_stub___cupy_upfirdn2D_float64: # @__device_stub___cupy_upfirdn2D_float64
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_cupy_upfirdn2D_float64, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	__device_stub___cupy_upfirdn2D_float64, .Lfunc_end5-__device_stub___cupy_upfirdn2D_float64
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub___cupy_upfirdn2D_complex64 # -- Begin function __device_stub___cupy_upfirdn2D_complex64
	.type	__device_stub___cupy_upfirdn2D_complex64,@function
__device_stub___cupy_upfirdn2D_complex64: # @__device_stub___cupy_upfirdn2D_complex64
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_cupy_upfirdn2D_complex64, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	__device_stub___cupy_upfirdn2D_complex64, .Lfunc_end6-__device_stub___cupy_upfirdn2D_complex64
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub___cupy_upfirdn2D_complex128 # -- Begin function __device_stub___cupy_upfirdn2D_complex128
	.type	__device_stub___cupy_upfirdn2D_complex128,@function
__device_stub___cupy_upfirdn2D_complex128: # @__device_stub___cupy_upfirdn2D_complex128
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_cupy_upfirdn2D_complex128, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	__device_stub___cupy_upfirdn2D_complex128, .Lfunc_end7-__device_stub___cupy_upfirdn2D_complex128
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_cupy_upfirdn1D_float32, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_cupy_upfirdn1D_float64, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_cupy_upfirdn1D_complex64, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_cupy_upfirdn1D_complex128, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_cupy_upfirdn2D_float32, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_cupy_upfirdn2D_float64, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_cupy_upfirdn2D_complex64, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_cupy_upfirdn2D_complex128, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_cupy_upfirdn1D_float32,@object # @_cupy_upfirdn1D_float32
	.section	.rodata,"a",@progbits
	.globl	_cupy_upfirdn1D_float32
	.p2align	3, 0x0
_cupy_upfirdn1D_float32:
	.quad	__device_stub___cupy_upfirdn1D_float32
	.size	_cupy_upfirdn1D_float32, 8

	.type	_cupy_upfirdn1D_float64,@object # @_cupy_upfirdn1D_float64
	.globl	_cupy_upfirdn1D_float64
	.p2align	3, 0x0
_cupy_upfirdn1D_float64:
	.quad	__device_stub___cupy_upfirdn1D_float64
	.size	_cupy_upfirdn1D_float64, 8

	.type	_cupy_upfirdn1D_complex64,@object # @_cupy_upfirdn1D_complex64
	.globl	_cupy_upfirdn1D_complex64
	.p2align	3, 0x0
_cupy_upfirdn1D_complex64:
	.quad	__device_stub___cupy_upfirdn1D_complex64
	.size	_cupy_upfirdn1D_complex64, 8

	.type	_cupy_upfirdn1D_complex128,@object # @_cupy_upfirdn1D_complex128
	.globl	_cupy_upfirdn1D_complex128
	.p2align	3, 0x0
_cupy_upfirdn1D_complex128:
	.quad	__device_stub___cupy_upfirdn1D_complex128
	.size	_cupy_upfirdn1D_complex128, 8

	.type	_cupy_upfirdn2D_float32,@object # @_cupy_upfirdn2D_float32
	.globl	_cupy_upfirdn2D_float32
	.p2align	3, 0x0
_cupy_upfirdn2D_float32:
	.quad	__device_stub___cupy_upfirdn2D_float32
	.size	_cupy_upfirdn2D_float32, 8

	.type	_cupy_upfirdn2D_float64,@object # @_cupy_upfirdn2D_float64
	.globl	_cupy_upfirdn2D_float64
	.p2align	3, 0x0
_cupy_upfirdn2D_float64:
	.quad	__device_stub___cupy_upfirdn2D_float64
	.size	_cupy_upfirdn2D_float64, 8

	.type	_cupy_upfirdn2D_complex64,@object # @_cupy_upfirdn2D_complex64
	.globl	_cupy_upfirdn2D_complex64
	.p2align	3, 0x0
_cupy_upfirdn2D_complex64:
	.quad	__device_stub___cupy_upfirdn2D_complex64
	.size	_cupy_upfirdn2D_complex64, 8

	.type	_cupy_upfirdn2D_complex128,@object # @_cupy_upfirdn2D_complex128
	.globl	_cupy_upfirdn2D_complex128
	.p2align	3, 0x0
_cupy_upfirdn2D_complex128:
	.quad	__device_stub___cupy_upfirdn2D_complex128
	.size	_cupy_upfirdn2D_complex128, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_cupy_upfirdn1D_float32"
	.size	.L__unnamed_1, 24

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_cupy_upfirdn1D_float64"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_cupy_upfirdn1D_complex64"
	.size	.L__unnamed_3, 26

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_cupy_upfirdn1D_complex128"
	.size	.L__unnamed_4, 27

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_cupy_upfirdn2D_float32"
	.size	.L__unnamed_5, 24

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_cupy_upfirdn2D_float64"
	.size	.L__unnamed_6, 24

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_cupy_upfirdn2D_complex64"
	.size	.L__unnamed_7, 26

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_cupy_upfirdn2D_complex128"
	.size	.L__unnamed_8, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub___cupy_upfirdn1D_float32
	.addrsig_sym __device_stub___cupy_upfirdn1D_float64
	.addrsig_sym __device_stub___cupy_upfirdn1D_complex64
	.addrsig_sym __device_stub___cupy_upfirdn1D_complex128
	.addrsig_sym __device_stub___cupy_upfirdn2D_float32
	.addrsig_sym __device_stub___cupy_upfirdn2D_float64
	.addrsig_sym __device_stub___cupy_upfirdn2D_complex64
	.addrsig_sym __device_stub___cupy_upfirdn2D_complex128
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _cupy_upfirdn1D_float32
	.addrsig_sym _cupy_upfirdn1D_float64
	.addrsig_sym _cupy_upfirdn1D_complex64
	.addrsig_sym _cupy_upfirdn1D_complex128
	.addrsig_sym _cupy_upfirdn2D_float32
	.addrsig_sym _cupy_upfirdn2D_float64
	.addrsig_sym _cupy_upfirdn2D_complex64
	.addrsig_sym _cupy_upfirdn2D_complex128
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_cupy_upfirdn1D_float32 ; -- Begin function _cupy_upfirdn1D_float32
	.globl	_cupy_upfirdn1D_float32
	.p2align	8
	.type	_cupy_upfirdn1D_float32,@function
_cupy_upfirdn1D_float32:                ; @_cupy_upfirdn1D_float32
; %bb.0:
	s_load_b32 s3, s[0:1], 0x38
	s_add_u32 s4, s0, 56
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s15, s3
	s_cselect_b32 s2, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s2
	s_load_b32 s2, s[0:1], 0x30
	global_load_u16 v3, v1, s[4:5]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s2, v1
	s_cbranch_execz .LBB0_7
; %bb.1:                                ; %.lr.ph47.i
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x1c
	s_load_b64 s[12:13], s[0:1], 0x10
	s_mov_b32 s16, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s7, s6, 31
	s_ashr_i32 s14, s12, 31
	s_add_i32 s6, s6, s7
	v_cvt_f32_u32_e32 v0, s12
	s_xor_b32 s15, s6, s7
	v_cvt_f32_u32_e32 v2, s14
	v_cvt_f32_u32_e32 v4, s15
	s_sub_i32 s6, 0, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v2, 0x4f800000, v0
	v_rcp_iflag_f32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_mul_f32_e32 v4, 0x5f7ffffc, v0
	v_cvt_u32_f32_e32 v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, 0x2f800000, v4
	v_mul_lo_u32 v2, s6, v5
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x0
	s_ashr_i32 s1, s13, 31
	v_trunc_f32_e32 v6, v0
	v_mul_lo_u32 v0, s3, v3
	s_ashr_i32 s3, s2, 31
	v_mul_hi_u32 v3, v5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmamk_f32 v4, v6, 0xcf800000, v4
	v_ashrrev_i32_e32 v2, 31, v1
	v_cvt_u32_f32_e32 v12, v6
	v_ashrrev_i32_e32 v9, 31, v0
	v_cvt_u32_f32_e32 v10, v4
	v_add_nc_u32_e32 v11, v5, v3
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_sub_u32 s0, 0, s12
	s_subb_u32 s17, 0, s14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s0, v10
	v_mul_lo_u32 v4, s0, v12
	v_mul_lo_u32 v5, s17, v10
	v_mul_lo_u32 v15, v1, s1
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v5
	v_mul_hi_u32 v5, v10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v6, v10, v3
	v_mul_hi_u32 v7, v10, v3
	v_mul_hi_u32 v8, v12, v4
	v_mul_lo_u32 v4, v12, v4
	v_mul_hi_u32 v13, v12, v3
	v_mul_lo_u32 v3, v12, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v13, vcc_lo
	v_mul_lo_u32 v13, v2, s13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v10, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, v12, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s0, v5
	v_mul_lo_u32 v7, s17, v5
	v_mul_lo_u32 v4, s0, v6
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s0, v5
	v_add_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v5, v4
	v_mul_lo_u32 v8, v5, v3
	v_mul_hi_u32 v14, v5, v3
	v_mul_hi_u32 v16, v6, v4
	v_mul_lo_u32 v4, v6, v4
	v_mul_hi_u32 v17, v6, v3
	v_add_co_u32 v7, vcc_lo, v7, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v14, vcc_lo
	v_mul_lo_u32 v14, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v7, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, v8, v16, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v17, vcc_lo
	v_mad_u64_u32 v[3:4], null, v1, s13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v14
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, v6, v8, vcc_lo
	v_add3_u32 v15, v4, v15, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v16, v3, v14
	v_mad_u64_u32 v[4:5], null, v3, v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[6:7], null, v15, v14, 0
	v_mad_u64_u32 v[13:14], null, v15, v8, 0
	v_add_co_u32 v4, vcc_lo, v16, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v7, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v6, vcc_lo, v4, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
	v_mul_lo_u32 v8, s14, v6
	v_mad_u64_u32 v[4:5], null, s12, v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, s12, v7
	v_sub_co_u32 v4, vcc_lo, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v5, v5, v7, v8
	v_add_co_u32 v8, null, v6, 2
	v_sub_nc_u32_e32 v7, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v7, s0, s14, v7, vcc_lo
	v_sub_co_u32 v13, s0, v4, s12
	v_sub_co_ci_u32_e32 v5, vcc_lo, v15, v5, vcc_lo
	v_subrev_co_ci_u32_e64 v7, s0, 0, v7, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s12, v13
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v7
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s12, v4
	v_cndmask_b32_e64 v4, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v5
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s14, v7
	v_cndmask_b32_e32 v7, v14, v13, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s14, v5
	v_add_co_u32 v13, null, v6, 1
	v_mov_b32_e32 v14, 0
	v_cndmask_b32_e32 v4, v15, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v13, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v6, v5, vcc_lo
	v_ashrrev_i32_e32 v4, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v5, v4
	v_xor_b32_e32 v6, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v11
	v_mul_lo_u32 v7, v7, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v6, v7
	v_subrev_nc_u32_e32 v7, s15, v6
	v_cmp_le_u32_e32 vcc_lo, s15, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_subrev_nc_u32_e32 v7, s15, v6
	v_cmp_le_u32_e32 vcc_lo, s15, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_xor_b32_e32 v6, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v6, v4
	v_subrev_nc_u32_e32 v7, s5, v4
	v_add_nc_u32_e32 v4, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, 1, v7
	v_cmp_gt_i32_e32 vcc_lo, -1, v7
	v_min_i32_e32 v13, s4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v6, 0, vcc_lo
	v_cmpx_lt_i32_e64 v4, v13
	s_cbranch_execz .LBB0_6
; %bb.3:                                ; %.lr.ph.preheader.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mul_lo_u32 v7, v5, s12
	v_ashrrev_i32_e32 v5, 31, v4
	v_cndmask_b32_e32 v14, 0, v6, vcc_lo
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, v3, v7
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, s5
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v8, vcc_lo
	v_sub_nc_u32_e32 v7, v3, v14
	v_mov_b32_e32 v14, 0
.LBB0_4:                                ; %.lr.ph.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_nc_u32_e32 v4, 1, v4
	v_lshlrev_b64 v[15:16], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, v4, v13
	s_or_b32 s18, s0, s18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, s10, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v16, vcc_lo
	global_load_b32 v3, v[5:6], off
	global_load_b32 v8, v[15:16], off
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v14, v3, v8 :: v_dual_add_nc_u32 v7, 1, v7
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
.LBB0_6:                                ; %Flow28
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s17
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, v1, v0
	v_add_co_ci_u32_e32 v2, vcc_lo, v2, v9, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, s0, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
	v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
	s_or_b32 s16, vcc_lo, s16
	global_store_b32 v[3:4], v14, off
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_2
.LBB0_7:                                ; %_Z15_cupy_upfirdn1DIfEvPKT_S2_iiiiiiPS0_i.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _cupy_upfirdn1D_float32
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_cupy_upfirdn1D_float32, .Lfunc_end0-_cupy_upfirdn1D_float32
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1376
; NumSgprs: 21
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_cupy_upfirdn1D_float64 ; -- Begin function _cupy_upfirdn1D_float64
	.globl	_cupy_upfirdn1D_float64
	.p2align	8
	.type	_cupy_upfirdn1D_float64,@function
_cupy_upfirdn1D_float64:                ; @_cupy_upfirdn1D_float64
; %bb.0:
	s_load_b32 s3, s[0:1], 0x38
	s_add_u32 s4, s0, 56
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s15, s3
	s_cselect_b32 s2, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s2
	s_load_b32 s2, s[0:1], 0x30
	global_load_u16 v3, v1, s[4:5]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s2, v1
	s_cbranch_execz .LBB1_7
; %bb.1:                                ; %.lr.ph47.i
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x1c
	s_load_b64 s[12:13], s[0:1], 0x10
	s_mov_b32 s16, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s7, s6, 31
	s_ashr_i32 s14, s12, 31
	s_add_i32 s6, s6, s7
	v_cvt_f32_u32_e32 v0, s12
	s_xor_b32 s15, s6, s7
	v_cvt_f32_u32_e32 v2, s14
	v_cvt_f32_u32_e32 v4, s15
	s_sub_i32 s6, 0, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v2, 0x4f800000, v0
	v_rcp_iflag_f32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_mul_f32_e32 v4, 0x5f7ffffc, v0
	v_cvt_u32_f32_e32 v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, 0x2f800000, v4
	v_mul_lo_u32 v2, s6, v5
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x0
	s_ashr_i32 s1, s13, 31
	v_trunc_f32_e32 v6, v0
	v_mul_lo_u32 v0, s3, v3
	s_ashr_i32 s3, s2, 31
	v_mul_hi_u32 v3, v5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmamk_f32 v4, v6, 0xcf800000, v4
	v_ashrrev_i32_e32 v2, 31, v1
	v_cvt_u32_f32_e32 v14, v6
	v_ashrrev_i32_e32 v11, 31, v0
	v_cvt_u32_f32_e32 v12, v4
	v_add_nc_u32_e32 v13, v5, v3
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
	s_sub_u32 s0, 0, s12
	s_subb_u32 s17, 0, s14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s0, v12
	v_mul_lo_u32 v4, s0, v14
	v_mul_lo_u32 v5, s17, v12
	v_mul_lo_u32 v15, v1, s1
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s0, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v5
	v_mul_hi_u32 v5, v12, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v6, v12, v3
	v_mul_hi_u32 v7, v12, v3
	v_mul_hi_u32 v8, v14, v4
	v_mul_lo_u32 v4, v14, v4
	v_mul_hi_u32 v9, v14, v3
	v_mul_lo_u32 v3, v14, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	v_mul_lo_u32 v9, v2, s13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v12, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, v14, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s0, v5
	v_mul_lo_u32 v7, s17, v5
	v_mul_lo_u32 v4, s0, v6
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s0, v5
	v_add_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v5, v4
	v_mul_lo_u32 v8, v5, v3
	v_mul_hi_u32 v10, v5, v3
	v_mul_hi_u32 v16, v6, v4
	v_mul_lo_u32 v4, v6, v4
	v_mul_hi_u32 v17, v6, v3
	v_add_co_u32 v7, vcc_lo, v7, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v10, vcc_lo
	v_mul_lo_u32 v10, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v7, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, v8, v16, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v17, vcc_lo
	v_mad_u64_u32 v[3:4], null, v1, s13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v16, vcc_lo, v6, v8, vcc_lo
	v_add3_u32 v15, v4, v15, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v17, v3, v10
	v_mad_u64_u32 v[4:5], null, v3, v16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[6:7], null, v15, v10, 0
	v_mad_u64_u32 v[8:9], null, v15, v16, 0
	v_add_co_u32 v4, vcc_lo, v17, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v7, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, v4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
	v_mul_lo_u32 v8, s14, v6
	v_mad_u64_u32 v[4:5], null, s12, v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, s12, v7
	v_sub_co_u32 v4, vcc_lo, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v5, v5, v7, v8
	v_add_co_u32 v8, null, v6, 2
	v_sub_nc_u32_e32 v7, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v7, s0, s14, v7, vcc_lo
	v_sub_co_u32 v9, s0, v4, s12
	v_sub_co_ci_u32_e32 v5, vcc_lo, v15, v5, vcc_lo
	v_subrev_co_ci_u32_e64 v7, s0, 0, v7, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s12, v9
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v7
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s12, v4
	v_cndmask_b32_e64 v4, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v5
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s14, v7
	v_cndmask_b32_e32 v7, v10, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s14, v5
	v_add_co_u32 v9, null, v6, 1
	v_cndmask_b32_e32 v4, v15, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e32 v5, v9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e32 v7, v6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v7
	v_add_nc_u32_e32 v5, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v4
	v_mul_hi_u32 v6, v5, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, s15
	v_sub_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s15, v5
	v_cmp_le_u32_e32 vcc_lo, s15, v5
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s15, v5
	v_cmp_le_u32_e32 vcc_lo, s15, v5
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v4
	v_sub_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s5, v4
	v_add_nc_u32_e32 v4, 1, v4
	v_add_nc_u32_e32 v8, 1, v5
	v_cmp_gt_i32_e32 vcc_lo, -1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_min_i32_e32 v15, s4, v4
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	v_cndmask_b32_e64 v6, v8, 0, vcc_lo
	v_cmpx_lt_i32_e64 v6, v15
	s_cbranch_execz .LBB1_6
; %bb.3:                                ; %.lr.ph.preheader.i
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mul_lo_u32 v4, v7, s12
	v_ashrrev_i32_e32 v7, 31, v6
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[9:10], 3, v[6:7]
	v_sub_nc_u32_e32 v3, v3, v4
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s8, v9
	v_mul_lo_u32 v3, v3, s5
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	v_sub_nc_u32_e32 v7, v3, v8
.LBB1_4:                                ; %.lr.ph.i
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_nc_u32_e32 v6, 1, v6
	v_lshlrev_b64 v[16:17], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_ge_i32_e64 s0, v6, v15
	v_add_nc_u32_e32 v7, 1, v7
	s_or_b32 s18, s0, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v16, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
	global_load_b64 v[18:19], v[9:10], off
	global_load_b64 v[16:17], v[16:17], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[4:5], v[18:19], v[16:17], v[4:5]
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB1_4
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
.LBB1_6:                                ; %Flow28
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s17
	v_lshlrev_b64 v[6:7], 3, v[1:2]
	v_add_co_u32 v1, vcc_lo, v1, v0
	v_add_co_ci_u32_e32 v2, vcc_lo, v2, v11, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s0, s6, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
	v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
	s_or_b32 s16, vcc_lo, s16
	global_store_b64 v[6:7], v[4:5], off
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_2
.LBB1_7:                                ; %_Z15_cupy_upfirdn1DIdEvPKT_S2_iiiiiiPS0_i.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _cupy_upfirdn1D_float64
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_cupy_upfirdn1D_float64, .Lfunc_end1-_cupy_upfirdn1D_float64
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1384
; NumSgprs: 21
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_cupy_upfirdn1D_complex64 ; -- Begin function _cupy_upfirdn1D_complex64
	.globl	_cupy_upfirdn1D_complex64
	.p2align	8
	.type	_cupy_upfirdn1D_complex64,@function
_cupy_upfirdn1D_complex64:              ; @_cupy_upfirdn1D_complex64
; %bb.0:
	s_load_b32 s3, s[0:1], 0x38
	s_add_u32 s4, s0, 56
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s15, s3
	s_cselect_b32 s2, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s2
	s_load_b32 s2, s[0:1], 0x30
	global_load_u16 v3, v1, s[4:5]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s2, v1
	s_cbranch_execz .LBB2_7
; %bb.1:                                ; %.lr.ph50.i
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x1c
	s_load_b64 s[12:13], s[0:1], 0x10
	s_load_b128 s[8:11], s[0:1], 0x0
	s_mov_b32 s16, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s7, s6, 31
	s_ashr_i32 s14, s12, 31
	s_add_i32 s6, s6, s7
	v_cvt_f32_u32_e32 v0, s12
	s_xor_b32 s15, s6, s7
	v_cvt_f32_u32_e32 v2, s14
	v_cvt_f32_u32_e32 v4, s15
	s_sub_i32 s6, 0, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v2, 0x4f800000, v0
	v_rcp_iflag_f32_e32 v2, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v5, v2
	v_mul_lo_u32 v6, s6, v5
	s_load_b64 s[6:7], s[0:1], 0x28
	s_ashr_i32 s1, s13, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v5, v6
	v_add_nc_u32_e32 v13, v5, v6
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x5f7ffffc, v0
	v_mul_lo_u32 v0, s3, v3
	s_ashr_i32 s3, s2, 31
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	v_mul_f32_e32 v2, 0x2f800000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v11, 31, v0
	v_trunc_f32_e32 v3, v2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v4, v3, 0xcf800000, v4
	v_cvt_u32_f32_e32 v14, v3
	v_cvt_u32_f32_e32 v12, v4
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
	s_sub_u32 s0, 0, s12
	s_subb_u32 s17, 0, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s0, v12
	v_mul_lo_u32 v4, s0, v14
	v_mul_lo_u32 v5, s17, v12
	v_mul_lo_u32 v15, v1, s1
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s0, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v5
	v_mul_hi_u32 v5, v12, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v6, v12, v3
	v_mul_hi_u32 v7, v12, v3
	v_mul_hi_u32 v8, v14, v4
	v_mul_lo_u32 v4, v14, v4
	v_mul_hi_u32 v9, v14, v3
	v_mul_lo_u32 v3, v14, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	v_mul_lo_u32 v9, v2, s13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v12, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, v14, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s0, v5
	v_mul_lo_u32 v7, s17, v5
	v_mul_lo_u32 v4, s0, v6
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s0, v5
	v_add_nc_u32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v5, v4
	v_mul_lo_u32 v8, v5, v3
	v_mul_hi_u32 v10, v5, v3
	v_mul_hi_u32 v16, v6, v4
	v_mul_lo_u32 v4, v6, v4
	v_mul_hi_u32 v17, v6, v3
	v_add_co_u32 v7, vcc_lo, v7, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v10, vcc_lo
	v_mul_lo_u32 v10, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v7, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, v8, v16, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v17, vcc_lo
	v_mad_u64_u32 v[3:4], null, v1, s13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v16, vcc_lo, v6, v8, vcc_lo
	v_add3_u32 v15, v4, v15, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v17, v3, v10
	v_mad_u64_u32 v[4:5], null, v3, v16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[6:7], null, v15, v10, 0
	v_mad_u64_u32 v[8:9], null, v15, v16, 0
	v_add_co_u32 v4, vcc_lo, v17, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v7, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, v4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
	v_mul_lo_u32 v8, s14, v6
	v_mad_u64_u32 v[4:5], null, s12, v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, s12, v7
	v_sub_co_u32 v4, vcc_lo, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v5, v5, v7, v8
	v_add_co_u32 v8, null, v6, 2
	v_sub_nc_u32_e32 v7, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v7, s0, s14, v7, vcc_lo
	v_sub_co_u32 v9, s0, v4, s12
	v_sub_co_ci_u32_e32 v5, vcc_lo, v15, v5, vcc_lo
	v_subrev_co_ci_u32_e64 v7, s0, 0, v7, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s12, v9
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v7
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s12, v4
	v_cndmask_b32_e64 v4, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v5
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s14, v7
	v_cndmask_b32_e32 v7, v10, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s14, v5
	v_add_co_u32 v9, null, v6, 1
	v_cndmask_b32_e32 v4, v15, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e32 v5, v9, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e32 v7, v6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v7
	v_add_nc_u32_e32 v5, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v4
	v_mul_hi_u32 v6, v5, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, s15
	v_sub_nc_u32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s15, v5
	v_cmp_le_u32_e32 vcc_lo, s15, v5
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s15, v5
	v_cmp_le_u32_e32 vcc_lo, s15, v5
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v4
	v_sub_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s5, v4
	v_add_nc_u32_e32 v4, 1, v4
	v_add_nc_u32_e32 v8, 1, v5
	v_cmp_gt_i32_e32 vcc_lo, -1, v5
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_min_i32_e32 v15, s4, v4
	v_mov_b32_e32 v4, 0
	v_cndmask_b32_e64 v6, v8, 0, vcc_lo
	v_cmpx_lt_i32_e64 v6, v15
	s_cbranch_execz .LBB2_6
; %bb.3:                                ; %.lr.ph.preheader.i
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_mul_lo_u32 v4, v7, s12
	v_ashrrev_i32_e32 v7, 31, v6
	v_cndmask_b32_e32 v10, 0, v8, vcc_lo
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v3, v4
	v_lshlrev_b64 v[3:4], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, v5, s5
	v_mov_b32_e32 v5, 0
	v_add_co_u32 v7, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
	v_mov_b32_e32 v4, v5
	v_sub_nc_u32_e32 v9, v9, v10
.LBB2_4:                                ; %.lr.ph.i
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[16:17], 3, v[9:10]
	v_add_nc_u32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
	global_load_b64 v[18:19], v[7:8], off offset:-4
	global_load_b64 v[16:17], v[16:17], off
	v_add_nc_u32_e32 v6, 1, v6
	v_add_co_u32 v7, vcc_lo, v7, 8
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v3, v19, v17
	v_mul_f32_e32 v10, v18, v17
	v_cmp_ge_i32_e32 vcc_lo, v6, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v3, v18, v16, -v3
	v_fmac_f32_e32 v10, v16, v19
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v4, v4, v3 :: v_dual_add_f32 v5, v5, v10
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_4
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB2_6:                                ; %Flow37
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s17
	v_lshlrev_b64 v[6:7], 3, v[1:2]
	v_add_co_u32 v1, vcc_lo, v1, v0
	v_add_co_ci_u32_e32 v2, vcc_lo, v2, v11, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s0, s6, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
	v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
	s_or_b32 s16, vcc_lo, s16
	global_store_b64 v[6:7], v[4:5], off
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB2_2
.LBB2_7:                                ; %_Z15_cupy_upfirdn1DIN6thrust7complexIfEEEvPKT_S5_iiiiiiPS3_i.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _cupy_upfirdn1D_complex64
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_cupy_upfirdn1D_complex64, .Lfunc_end2-_cupy_upfirdn1D_complex64
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1416
; NumSgprs: 20
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_cupy_upfirdn1D_complex128 ; -- Begin function _cupy_upfirdn1D_complex128
	.globl	_cupy_upfirdn1D_complex128
	.p2align	8
	.type	_cupy_upfirdn1D_complex128,@function
_cupy_upfirdn1D_complex128:             ; @_cupy_upfirdn1D_complex128
; %bb.0:
	s_load_b32 s3, s[0:1], 0x38
	s_add_u32 s4, s0, 56
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s15, s3
	s_cselect_b32 s2, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s2
	s_load_b32 s2, s[0:1], 0x30
	global_load_u16 v1, v1, s[4:5]
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, s15, v1, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s2, v4
	s_cbranch_execz .LBB3_7
; %bb.1:                                ; %.lr.ph47.i
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x1c
	s_load_b64 s[12:13], s[0:1], 0x10
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mul_lo_u32 v12, s3, v1
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s7, s6, 31
	s_ashr_i32 s14, s12, 31
	s_add_i32 s6, s6, s7
	v_cvt_f32_u32_e32 v0, s12
	s_xor_b32 s15, s6, s7
	v_cvt_f32_u32_e32 v2, s14
	v_cvt_f32_u32_e32 v3, s15
	s_sub_i32 s6, 0, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v2, 0x4f800000, v0
	v_rcp_iflag_f32_e32 v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, s6, v2
	v_mul_f32_e32 v3, 0x2f800000, v0
	s_load_b64 s[6:7], s[0:1], 0x28
	s_ashr_i32 s1, s13, 31
	s_add_u32 s8, s8, 8
	s_addc_u32 s9, s9, 0
	v_trunc_f32_e32 v1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, v2, v5
	v_ashrrev_i32_e32 v5, 31, v4
	v_cvt_u32_f32_e32 v16, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v0, v1, 0xcf800000, v0 :: v_dual_add_nc_u32 v15, v2, v3
	v_cvt_u32_f32_e32 v14, v0
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_4 Depth 2
	s_sub_u32 s0, 0, s12
	s_subb_u32 s17, 0, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v0, s0, v14
	v_mul_lo_u32 v1, s0, v16
	v_mul_lo_u32 v2, s17, v14
	v_mul_lo_u32 v10, v4, s1
	v_add_nc_u32_e32 v0, v0, v1
	v_mul_lo_u32 v1, s0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_hi_u32 v2, v14, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v3, v14, v0
	v_mul_hi_u32 v6, v14, v0
	v_mul_hi_u32 v7, v16, v1
	v_mul_lo_u32 v1, v16, v1
	v_mul_hi_u32 v8, v16, v0
	v_mul_lo_u32 v0, v16, v0
	v_add_co_u32 v2, vcc_lo, v2, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v2, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v7, vcc_lo
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v8, vcc_lo
	v_mul_lo_u32 v8, v5, s13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v1, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v14, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v16, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v2, s0, v0
	v_mul_lo_u32 v6, s17, v0
	v_mul_lo_u32 v3, s0, v1
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_lo_u32 v3, s0, v0
	v_add_nc_u32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v0, v3
	v_mul_lo_u32 v7, v0, v2
	v_mul_hi_u32 v9, v0, v2
	v_mul_hi_u32 v11, v1, v3
	v_mul_lo_u32 v3, v1, v3
	v_mul_hi_u32 v17, v1, v2
	v_mul_lo_u32 v2, v1, v2
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v11, vcc_lo
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v17, vcc_lo
	v_mad_u64_u32 v[6:7], null, v4, s13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v3, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v11, vcc_lo, v1, v3, vcc_lo
	v_add3_u32 v10, v7, v10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v17, v6, v9
	v_mad_u64_u32 v[0:1], null, v6, v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, v10, v9, 0
	v_mad_u64_u32 v[7:8], null, v10, v11, 0
	v_add_co_u32 v0, vcc_lo, v17, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v0, vcc_lo, v1, v3, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v2, vcc_lo, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
	v_mul_lo_u32 v7, s14, v2
	v_mad_u64_u32 v[0:1], null, s12, v2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, s12, v3
	v_sub_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, v1, v3, v7
	v_add_co_u32 v7, null, v2, 2
	v_sub_nc_u32_e32 v3, v10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v3, s0, s14, v3, vcc_lo
	v_sub_co_u32 v8, s0, v0, s12
	v_sub_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
	v_subrev_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s12, v8
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v3
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s12, v0
	v_cndmask_b32_e64 v0, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v1
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s14, v3
	v_cndmask_b32_e32 v3, v9, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s14, v1
	v_add_co_u32 v8, null, v2, 1
	v_cndmask_b32_e32 v0, v10, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v1, v8, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v8, v2, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 31, v8
	v_add_nc_u32_e32 v1, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_mul_hi_u32 v2, v1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s15
	v_sub_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s15, v1
	v_cmp_le_u32_e32 vcc_lo, s15, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s15, v1
	v_cmp_le_u32_e32 vcc_lo, s15, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v2, s5, v0
	v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, 1, v0
	v_mov_b32_e32 v1, 0
	v_add_nc_u32_e32 v9, 1, v2
	v_cmp_gt_i32_e32 vcc_lo, -1, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min_i32_e32 v17, s4, v3
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v9, 0, vcc_lo
	v_cmpx_lt_i32_e64 v7, v17
	s_cbranch_execz .LBB3_6
; %bb.3:                                ; %.lr.ph.preheader.i
                                        ;   in Loop: Header=BB3_2 Depth=1
	v_mul_lo_u32 v0, v8, s12
	v_ashrrev_i32_e32 v8, 31, v7
	v_cndmask_b32_e32 v10, 0, v9, vcc_lo
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 4, v[7:8]
	v_sub_nc_u32_e32 v0, v6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s8, v2
	v_mul_lo_u32 v6, v0, s5
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	v_sub_nc_u32_e32 v10, v6, v10
.LBB3_4:                                ; %.lr.ph.i
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_nc_u32_e32 v7, 1, v7
	v_lshlrev_b64 v[18:19], 4, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_ge_i32_e64 s0, v7, v17
	v_add_nc_u32_e32 v10, 1, v10
	s_or_b32 s18, s0, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v22, vcc_lo, s10, v18
	v_add_co_ci_u32_e32 v23, vcc_lo, s11, v19, vcc_lo
	global_load_b128 v[18:21], v[8:9], off offset:-8
	global_load_b128 v[22:25], v[22:23], off
	v_add_co_u32 v8, vcc_lo, v8, 16
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[26:27], v[20:21], v[24:25]
	v_mul_f64 v[24:25], v[18:19], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[18:19], v[22:23], -v[26:27]
	v_fma_f64 v[20:21], v[22:23], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[0:1], v[0:1], v[18:19]
	v_add_f64 v[2:3], v[2:3], v[20:21]
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB3_4
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
.LBB3_6:                                ; %Flow37
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s17
	v_lshlrev_b64 v[6:7], 4, v[4:5]
	v_add_co_u32 v4, vcc_lo, v4, v12
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v13, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, s0, s6, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u64_e32 vcc_lo, s[2:3], v[4:5]
	v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
	s_or_b32 s16, vcc_lo, s16
	global_store_b128 v[6:7], v[0:3], off
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB3_2
.LBB3_7:                                ; %_Z15_cupy_upfirdn1DIN6thrust7complexIdEEEvPKT_S5_iiiiiiPS3_i.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _cupy_upfirdn1D_complex128
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_cupy_upfirdn1D_complex128, .Lfunc_end3-_cupy_upfirdn1D_complex128
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1464
; NumSgprs: 21
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_cupy_upfirdn2D_float32 ; -- Begin function _cupy_upfirdn2D_float32
	.globl	_cupy_upfirdn2D_float32
	.p2align	8
	.type	_cupy_upfirdn2D_float32,@function
_cupy_upfirdn2D_float32:                ; @_cupy_upfirdn2D_float32
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x4c
	s_load_b64 s[12:13], s[0:1], 0x38
	v_bfe_u32 v3, v0, 10, 10
	s_add_u32 s2, s0, 64
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s21, s4, 16
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s21, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s13, v1
	s_cbranch_execz .LBB4_15
; %bb.1:                                ; %.preheader.lr.ph.i
	s_load_b64 s[22:23], s[2:3], 0x0
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s14, s22
	s_cselect_b32 s4, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s4
	s_load_b256 s[4:11], s[0:1], 0x18
	global_load_u16 v4, v2, s[2:3]
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s6, 1
	s_cselect_b32 s3, -1, 0
	s_ashr_i32 s6, s4, 31
	s_ashr_i32 s15, s9, 31
	s_add_i32 s16, s4, s6
	s_add_i32 s17, s9, s15
	s_xor_b32 s9, s16, s6
	s_xor_b32 s15, s17, s15
	v_cvt_f32_u32_e32 v2, s9
	v_cvt_f32_u32_e32 v3, s15
	s_clause 0x1
	s_load_b32 s20, s[0:1], 0x8
	s_load_b64 s[16:17], s[0:1], 0x0
	s_sub_i32 s18, 0, s9
	s_sub_i32 s19, 0, s15
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v5, v2
	v_cvt_u32_f32_e32 v6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, s18, v5
	v_mul_lo_u32 v8, s19, v6
	s_load_b64 s[18:19], s[0:1], 0x10
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, s14, v4, v[0:1]
	v_mul_lo_u32 v0, s22, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v3, v5, v7
	v_mul_hi_u32 v4, v6, v8
	s_mul_i32 s14, s23, s21
	s_mov_b32 s21, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v7, s20, v2
	v_cmp_gt_i32_e64 s0, s12, v2
	v_mul_lo_u32 v8, v0, s20
	v_add_nc_u32_e32 v9, v5, v3
	v_add_nc_u32_e32 v10, v6, v4
.LBB4_2:                                ; %.preheader.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_4 Depth 2
                                        ;       Child Loop BB4_6 Depth 3
	s_delay_alu instid0(VALU_DEP_4)
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB4_14
; %bb.3:                                ; %.lr.ph83.i.preheader
                                        ;   in Loop: Header=BB4_2 Depth=1
	v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v12, v2
	s_mov_b32 s23, 0
.LBB4_4:                                ; %.lr.ph83.i
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB4_6 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v12, v1, s2
	s_mov_b32 s24, exec_lo
	v_mul_lo_u32 v3, v3, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_nc_u32_e32 v5, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v5, v4
	v_xor_b32_e32 v4, s6, v4
	v_mul_hi_u32 v6, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v13, v6, s9
	v_sub_nc_u32_e32 v5, v5, v13
	v_add_nc_u32_e32 v13, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v14, s9, v5
	v_cmp_le_u32_e32 vcc_lo, s9, v5
	v_dual_cndmask_b32 v6, v6, v13 :: v_dual_cndmask_b32 v5, v5, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, 1, v6
	v_cmp_le_u32_e32 vcc_lo, s9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v6, v13, vcc_lo
	v_xor_b32_e32 v5, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v5, v4
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v4, v5
	v_xor_b32_e32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v13, v6, v10
	v_mul_lo_u32 v13, v13, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v6, v13
	v_subrev_nc_u32_e32 v13, s15, v6
	v_cmp_le_u32_e32 vcc_lo, s15, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v13, vcc_lo
	v_subrev_nc_u32_e32 v13, s15, v6
	v_cmp_le_u32_e32 vcc_lo, s15, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v6, v13, vcc_lo
	v_xor_b32_e32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v6, v5
	v_subrev_nc_u32_e32 v6, s8, v5
	v_add_nc_u32_e32 v13, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, 1, v6
	v_cmp_gt_i32_e32 vcc_lo, -1, v6
	v_min_i32_e32 v14, s7, v13
	v_mov_b32_e32 v13, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, v5, 0, vcc_lo
	v_cmpx_lt_i32_e64 v15, v14
	s_cbranch_execz .LBB4_13
; %bb.5:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB4_4 Depth=2
	v_mul_lo_u32 v4, v4, s4
	s_mov_b32 s25, 0
	v_mov_b32_e32 v13, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v4
	v_cndmask_b32_e32 v4, 0, v5, vcc_lo
	v_mul_lo_u32 v3, v3, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s18, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
.LBB4_6:                                ;   Parent Loop BB4_2 Depth=1
                                        ;     Parent Loop BB4_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB4_8
; %bb.7:                                ;   in Loop: Header=BB4_6 Depth=3
	v_mad_u64_u32 v[5:6], null, v15, s20, v[1:2]
	s_mov_b32 s1, 0
	s_branch .LBB4_9
.LBB4_8:                                ;   in Loop: Header=BB4_6 Depth=3
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr5
.LBB4_9:                                ; %Flow
                                        ;   in Loop: Header=BB4_6 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB4_11
; %bb.10:                               ;   in Loop: Header=BB4_6 Depth=3
	v_add_nc_u32_e32 v5, v11, v15
.LBB4_11:                               ;   in Loop: Header=BB4_6 Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_nc_u32_e32 v15, 1, v15
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v15, v14
	global_load_b32 v16, v[3:4], off
	global_load_b32 v5, v[5:6], off
	v_add_co_u32 v3, s1, v3, 4
	v_add_co_ci_u32_e64 v4, s1, 0, v4, s1
	s_or_b32 s25, vcc_lo, s25
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v13, v5, v16
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB4_6
; %bb.12:                               ; %Flow41
                                        ;   in Loop: Header=BB4_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
.LBB4_13:                               ; %Flow42
                                        ;   in Loop: Header=BB4_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s24
	v_mad_u64_u32 v[3:4], null, v12, s13, v[1:2]
	v_add_nc_u32_e32 v12, v12, v0
	v_add_nc_u32_e32 v11, v11, v8
	v_cmp_le_i32_e32 vcc_lo, s12, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_or_b32 s23, vcc_lo, s23
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s1, s10, v3
	v_add_co_ci_u32_e64 v4, s1, s11, v4, s1
	global_store_b32 v[3:4], v13, off
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB4_4
.LBB4_14:                               ; %Flow45
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e32 v1, s14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s13, v1
	s_or_b32 s21, vcc_lo, s21
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB4_2
.LBB4_15:                               ; %_Z15_cupy_upfirdn2DIfEvPKT_iS2_iiiiiiPS0_ii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _cupy_upfirdn2D_float32
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_cupy_upfirdn2D_float32, .Lfunc_end4-_cupy_upfirdn2D_float32
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 992
; NumSgprs: 28
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_cupy_upfirdn2D_float64 ; -- Begin function _cupy_upfirdn2D_float64
	.globl	_cupy_upfirdn2D_float64
	.p2align	8
	.type	_cupy_upfirdn2D_float64,@function
_cupy_upfirdn2D_float64:                ; @_cupy_upfirdn2D_float64
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x4c
	s_load_b64 s[12:13], s[0:1], 0x38
	v_bfe_u32 v3, v0, 10, 10
	s_add_u32 s2, s0, 64
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s21, s4, 16
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s21, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s13, v1
	s_cbranch_execz .LBB5_15
; %bb.1:                                ; %.preheader.lr.ph.i
	s_load_b64 s[22:23], s[2:3], 0x0
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s14, s22
	s_cselect_b32 s4, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s4
	s_load_b256 s[4:11], s[0:1], 0x18
	global_load_u16 v4, v2, s[2:3]
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s6, 1
	s_cselect_b32 s3, -1, 0
	s_ashr_i32 s6, s4, 31
	s_ashr_i32 s15, s9, 31
	s_add_i32 s16, s4, s6
	s_add_i32 s17, s9, s15
	s_xor_b32 s9, s16, s6
	s_xor_b32 s15, s17, s15
	v_cvt_f32_u32_e32 v2, s9
	v_cvt_f32_u32_e32 v3, s15
	s_clause 0x1
	s_load_b32 s20, s[0:1], 0x8
	s_load_b64 s[16:17], s[0:1], 0x0
	s_sub_i32 s18, 0, s9
	s_sub_i32 s19, 0, s15
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v5, v2
	v_cvt_u32_f32_e32 v6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, s18, v5
	v_mul_lo_u32 v8, s19, v6
	s_load_b64 s[18:19], s[0:1], 0x10
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, s14, v4, v[0:1]
	v_mul_lo_u32 v0, s22, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v3, v5, v7
	v_mul_hi_u32 v4, v6, v8
	s_mul_i32 s14, s23, s21
	s_mov_b32 s21, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v9, s20, v2
	v_cmp_gt_i32_e64 s0, s12, v2
	v_mul_lo_u32 v10, v0, s20
	v_add_nc_u32_e32 v11, v5, v3
	v_add_nc_u32_e32 v12, v6, v4
.LBB5_2:                                ; %.preheader.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB5_4 Depth 2
                                        ;       Child Loop BB5_6 Depth 3
	s_delay_alu instid0(VALU_DEP_4)
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB5_14
; %bb.3:                                ; %.lr.ph83.i.preheader
                                        ;   in Loop: Header=BB5_2 Depth=1
	v_dual_mov_b32 v13, v9 :: v_dual_mov_b32 v14, v2
	s_mov_b32 s23, 0
.LBB5_4:                                ; %.lr.ph83.i
                                        ;   Parent Loop BB5_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB5_6 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v14, v1, s2
	s_mov_b32 s24, exec_lo
	v_mul_lo_u32 v5, v3, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v5
	v_add_nc_u32_e32 v4, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v3
	v_xor_b32_e32 v3, s6, v3
	v_mul_hi_u32 v6, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v6, s9
	v_sub_nc_u32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s9, v4
	v_cmp_le_u32_e32 vcc_lo, s9, v4
	v_dual_cndmask_b32 v4, v4, v8 :: v_dual_add_nc_u32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, 1, v6
	v_cndmask_b32_e32 v4, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v3
	v_sub_nc_u32_e32 v6, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v6
	v_add_nc_u32_e32 v4, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v3
	v_mul_hi_u32 v7, v4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v7, s15
	v_sub_nc_u32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s15, v4
	v_cmp_le_u32_e32 vcc_lo, s15, v4
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s15, v4
	v_cmp_le_u32_e32 vcc_lo, s15, v4
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v3
	v_sub_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s8, v3
	v_add_nc_u32_e32 v3, 1, v3
	v_add_nc_u32_e32 v7, 1, v4
	v_cmp_gt_i32_e32 vcc_lo, -1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_min_i32_e32 v16, s7, v3
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	v_cndmask_b32_e64 v15, v7, 0, vcc_lo
	v_cmpx_lt_i32_e64 v15, v16
	s_cbranch_execz .LBB5_13
; %bb.5:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB5_4 Depth=2
	v_mul_lo_u32 v3, v6, s4
	v_cndmask_b32_e32 v4, 0, v7, vcc_lo
	s_mov_b32 s25, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v5, v3
	v_mul_lo_u32 v3, v3, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 3, v[3:4]
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	v_add_co_u32 v5, vcc_lo, s18, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s19, v6, vcc_lo
.LBB5_6:                                ;   Parent Loop BB5_2 Depth=1
                                        ;     Parent Loop BB5_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB5_8
; %bb.7:                                ;   in Loop: Header=BB5_6 Depth=3
	v_mad_u64_u32 v[7:8], null, v15, s20, v[1:2]
	s_mov_b32 s1, 0
	s_branch .LBB5_9
.LBB5_8:                                ;   in Loop: Header=BB5_6 Depth=3
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr7
.LBB5_9:                                ; %Flow
                                        ;   in Loop: Header=BB5_6 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB5_11
; %bb.10:                               ;   in Loop: Header=BB5_6 Depth=3
	v_add_nc_u32_e32 v7, v13, v15
.LBB5_11:                               ;   in Loop: Header=BB5_6 Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_nc_u32_e32 v15, 1, v15
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s16, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v15, v16
	global_load_b64 v[7:8], v[7:8], off
	global_load_b64 v[17:18], v[5:6], off
	v_add_co_u32 v5, s1, v5, 8
	v_add_co_ci_u32_e64 v6, s1, 0, v6, s1
	s_or_b32 s25, vcc_lo, s25
	s_waitcnt vmcnt(0)
	v_fma_f64 v[3:4], v[7:8], v[17:18], v[3:4]
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB5_6
; %bb.12:                               ; %Flow41
                                        ;   in Loop: Header=BB5_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
.LBB5_13:                               ; %Flow42
                                        ;   in Loop: Header=BB5_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s24
	v_mad_u64_u32 v[5:6], null, v14, s13, v[1:2]
	v_add_nc_u32_e32 v14, v14, v0
	v_add_nc_u32_e32 v13, v13, v10
	v_cmp_le_i32_e32 vcc_lo, s12, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_or_b32 s23, vcc_lo, s23
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s10, v5
	v_add_co_ci_u32_e64 v6, s1, s11, v6, s1
	global_store_b64 v[5:6], v[3:4], off
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB5_4
.LBB5_14:                               ; %Flow45
                                        ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e32 v1, s14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s13, v1
	s_or_b32 s21, vcc_lo, s21
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB5_2
.LBB5_15:                               ; %_Z15_cupy_upfirdn2DIdEvPKT_iS2_iiiiiiPS0_ii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _cupy_upfirdn2D_float64
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_cupy_upfirdn2D_float64, .Lfunc_end5-_cupy_upfirdn2D_float64
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1004
; NumSgprs: 28
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_cupy_upfirdn2D_complex64 ; -- Begin function _cupy_upfirdn2D_complex64
	.globl	_cupy_upfirdn2D_complex64
	.p2align	8
	.type	_cupy_upfirdn2D_complex64,@function
_cupy_upfirdn2D_complex64:              ; @_cupy_upfirdn2D_complex64
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x4c
	s_load_b64 s[12:13], s[0:1], 0x38
	v_bfe_u32 v3, v0, 10, 10
	s_add_u32 s2, s0, 64
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s19, s4, 16
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s19, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s13, v1
	s_cbranch_execz .LBB6_15
; %bb.1:                                ; %.preheader.lr.ph.i
	s_load_b64 s[20:21], s[2:3], 0x0
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s14, s20
	s_cselect_b32 s4, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s4
	s_load_b256 s[4:11], s[0:1], 0x18
	global_load_u16 v4, v2, s[2:3]
	s_clause 0x1
	s_load_b32 s18, s[0:1], 0x8
	s_load_b64 s[22:23], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s6, 1
	s_cselect_b32 s3, -1, 0
	s_ashr_i32 s6, s4, 31
	s_ashr_i32 s15, s9, 31
	s_add_i32 s16, s4, s6
	s_add_i32 s17, s9, s15
	s_xor_b32 s9, s16, s6
	s_xor_b32 s15, s17, s15
	v_cvt_f32_u32_e32 v2, s9
	v_cvt_f32_u32_e32 v3, s15
	s_sub_i32 s16, 0, s9
	s_sub_i32 s17, 0, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v5, v2
	v_cvt_u32_f32_e32 v6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, s16, v5
	v_mul_lo_u32 v8, s17, v6
	s_load_b64 s[16:17], s[0:1], 0x0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, s14, v4, v[0:1]
	v_mul_lo_u32 v0, s20, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v3, v5, v7
	v_mul_hi_u32 v4, v6, v8
	s_add_u32 s20, s22, 4
	s_mul_i32 s14, s21, s19
	s_mov_b32 s19, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v9, s18, v2
	v_cmp_gt_i32_e64 s0, s12, v2
	v_mul_lo_u32 v10, v0, s18
	v_add_nc_u32_e32 v11, v5, v3
	v_add_nc_u32_e32 v12, v6, v4
	s_addc_u32 s21, s23, 0
.LBB6_2:                                ; %.preheader.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB6_4 Depth 2
                                        ;       Child Loop BB6_6 Depth 3
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB6_14
; %bb.3:                                ; %.lr.ph95.i.preheader
                                        ;   in Loop: Header=BB6_2 Depth=1
	v_dual_mov_b32 v13, v9 :: v_dual_mov_b32 v14, v2
	s_mov_b32 s23, 0
.LBB6_4:                                ; %.lr.ph95.i
                                        ;   Parent Loop BB6_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB6_6 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v14, v1, s2
	s_mov_b32 s24, exec_lo
	v_mul_lo_u32 v5, v3, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v5
	v_add_nc_u32_e32 v4, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v3
	v_xor_b32_e32 v3, s6, v3
	v_mul_hi_u32 v6, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v6, s9
	v_sub_nc_u32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s9, v4
	v_cmp_le_u32_e32 vcc_lo, s9, v4
	v_dual_cndmask_b32 v4, v4, v8 :: v_dual_add_nc_u32 v7, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, 1, v6
	v_cndmask_b32_e32 v4, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v3
	v_sub_nc_u32_e32 v6, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v6
	v_add_nc_u32_e32 v4, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v3
	v_mul_hi_u32 v7, v4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v7, s15
	v_sub_nc_u32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s15, v4
	v_cmp_le_u32_e32 vcc_lo, s15, v4
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s15, v4
	v_cmp_le_u32_e32 vcc_lo, s15, v4
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v3
	v_sub_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s8, v3
	v_add_nc_u32_e32 v3, 1, v3
	v_add_nc_u32_e32 v7, 1, v4
	v_cmp_gt_i32_e32 vcc_lo, -1, v4
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_min_i32_e32 v15, s7, v3
	v_mov_b32_e32 v3, 0
	v_cndmask_b32_e64 v16, v7, 0, vcc_lo
	v_cmpx_lt_i32_e64 v16, v15
	s_cbranch_execz .LBB6_13
; %bb.5:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB6_4 Depth=2
	v_mul_lo_u32 v3, v6, s4
	v_cndmask_b32_e32 v4, 0, v7, vcc_lo
	s_mov_b32 s25, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v5, v3
	v_mad_u64_u32 v[5:6], null, s18, v16, v[1:2]
	v_mul_lo_u32 v3, v3, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 3, v[3:4]
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s20, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s21, v8, vcc_lo
.LBB6_6:                                ;   Parent Loop BB6_2 Depth=1
                                        ;     Parent Loop BB6_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB6_8
; %bb.7:                                ;   in Loop: Header=BB6_6 Depth=3
	v_ashrrev_i32_e32 v6, 31, v5
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 3, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v17, vcc_lo, s16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v18, vcc_lo, s17, v18, vcc_lo
	global_load_b64 v[19:20], v[7:8], off offset:-4
	global_load_b64 v[17:18], v[17:18], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v6, v17, v20
	v_dual_mul_f32 v21, v18, v20 :: v_dual_fmac_f32 v6, v19, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v17, v17, v19, -v21
	s_branch .LBB6_9
.LBB6_8:                                ;   in Loop: Header=BB6_6 Depth=3
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr17
.LBB6_9:                                ; %Flow
                                        ;   in Loop: Header=BB6_6 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB6_11
; %bb.10:                               ;   in Loop: Header=BB6_6 Depth=3
	v_add_nc_u32_e32 v17, v13, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[17:18], 3, v[17:18]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, s16, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s17, v18, vcc_lo
	global_load_b64 v[19:20], v[7:8], off offset:-4
	global_load_b64 v[17:18], v[17:18], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v21, v18, v20
	v_mul_f32_e32 v6, v17, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, v17, v19, -v21
	v_fmac_f32_e32 v6, v19, v18
.LBB6_11:                               ;   in Loop: Header=BB6_6 Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v3, v3, v17 :: v_dual_add_nc_u32 v16, 1, v16
	v_add_co_u32 v7, s1, v7, 8
	v_dual_add_f32 v4, v4, v6 :: v_dual_add_nc_u32 v5, s18, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v16, v15
	v_add_co_ci_u32_e64 v8, s1, 0, v8, s1
	s_or_b32 s25, vcc_lo, s25
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB6_6
; %bb.12:                               ; %Flow46
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
.LBB6_13:                               ; %Flow47
                                        ;   in Loop: Header=BB6_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s24
	v_mad_u64_u32 v[5:6], null, v14, s13, v[1:2]
	v_add_nc_u32_e32 v14, v14, v0
	v_add_nc_u32_e32 v13, v13, v10
	v_cmp_le_i32_e32 vcc_lo, s12, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	s_or_b32 s23, vcc_lo, s23
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s10, v5
	v_add_co_ci_u32_e64 v6, s1, s11, v6, s1
	global_store_b64 v[5:6], v[3:4], off
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB6_4
.LBB6_14:                               ; %Flow50
                                        ;   in Loop: Header=BB6_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e32 v1, s14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s13, v1
	s_or_b32 s19, vcc_lo, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB6_2
.LBB6_15:                               ; %_Z15_cupy_upfirdn2DIN6thrust7complexIfEEEvPKT_iS5_iiiiiiPS3_ii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _cupy_upfirdn2D_complex64
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_cupy_upfirdn2D_complex64, .Lfunc_end6-_cupy_upfirdn2D_complex64
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1124
; NumSgprs: 28
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_cupy_upfirdn2D_complex128 ; -- Begin function _cupy_upfirdn2D_complex128
	.globl	_cupy_upfirdn2D_complex128
	.p2align	8
	.type	_cupy_upfirdn2D_complex128,@function
_cupy_upfirdn2D_complex128:             ; @_cupy_upfirdn2D_complex128
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x4c
	s_load_b64 s[12:13], s[0:1], 0x38
	v_bfe_u32 v1, v0, 10, 10
	s_add_u32 s2, s0, 64
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s19, s4, 16
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[4:5], null, s15, s19, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s13, v4
	s_cbranch_execz .LBB7_15
; %bb.1:                                ; %.preheader.lr.ph.i
	s_load_b64 s[20:21], s[2:3], 0x0
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s14, s20
	s_cselect_b32 s4, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s4
	s_load_b256 s[4:11], s[0:1], 0x18
	global_load_u16 v1, v1, s[2:3]
	s_clause 0x1
	s_load_b32 s18, s[0:1], 0x8
	s_load_b64 s[22:23], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s6, 1
	s_cselect_b32 s3, -1, 0
	s_ashr_i32 s6, s4, 31
	s_ashr_i32 s15, s9, 31
	s_add_i32 s16, s4, s6
	s_add_i32 s17, s9, s15
	s_xor_b32 s9, s16, s6
	s_xor_b32 s15, s17, s15
	v_cvt_f32_u32_e32 v2, s9
	v_cvt_f32_u32_e32 v3, s15
	s_sub_i32 s16, 0, s9
	s_sub_i32 s17, 0, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, s16, v2
	v_mul_lo_u32 v8, s17, v3
	s_load_b64 s[16:17], s[0:1], 0x0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, s14, v1, v[0:1]
	v_mul_lo_u32 v14, s20, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v0, v2, v7
	v_mul_hi_u32 v1, v3, v8
	s_add_u32 s20, s22, 8
	s_mul_i32 s14, s21, s19
	s_mov_b32 s19, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v15, s18, v5
	v_cmp_gt_i32_e64 s0, s12, v5
	v_mul_lo_u32 v16, v14, s18
	v_add_nc_u32_e32 v17, v2, v0
	v_add_nc_u32_e32 v18, v3, v1
	s_addc_u32 s21, s23, 0
.LBB7_2:                                ; %.preheader.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB7_4 Depth 2
                                        ;       Child Loop BB7_6 Depth 3
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB7_14
; %bb.3:                                ; %.lr.ph92.i.preheader
                                        ;   in Loop: Header=BB7_2 Depth=1
	v_dual_mov_b32 v19, v15 :: v_dual_mov_b32 v20, v5
	s_mov_b32 s23, 0
.LBB7_4:                                ; %.lr.ph92.i
                                        ;   Parent Loop BB7_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB7_6 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v20, v4, s2
	s_mov_b32 s24, exec_lo
	v_mul_lo_u32 v6, v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 31, v6
	v_add_nc_u32_e32 v1, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v1, v0
	v_xor_b32_e32 v0, s6, v0
	v_mul_hi_u32 v2, v1, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v2, s9
	v_sub_nc_u32_e32 v1, v1, v3
	v_add_nc_u32_e32 v3, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v7, s9, v1
	v_cmp_le_u32_e32 vcc_lo, s9, v1
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v7, vcc_lo
	v_add_nc_u32_e32 v3, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s9, v1
	v_cndmask_b32_e32 v1, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_sub_nc_u32_e32 v7, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v0, 31, v7
	v_add_nc_u32_e32 v1, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_mul_hi_u32 v2, v1, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s15
	v_sub_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s15, v1
	v_cmp_le_u32_e32 vcc_lo, s15, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s15, v1
	v_cmp_le_u32_e32 vcc_lo, s15, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s8, v0
	v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, 1, v0
	v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v8, 1, v2
	v_cmp_gt_i32_e32 vcc_lo, -1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_i32_e32 v21, s7, v3
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v22, v8, 0, vcc_lo
	v_cmpx_lt_i32_e64 v22, v21
	s_cbranch_execz .LBB7_13
; %bb.5:                                ; %.lr.ph.i
                                        ;   in Loop: Header=BB7_4 Depth=2
	v_mul_lo_u32 v0, v7, s4
	v_cndmask_b32_e32 v1, 0, v8, vcc_lo
	s_mov_b32 s25, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v6, v0
	v_mad_u64_u32 v[6:7], null, s18, v22, v[4:5]
	v_mul_lo_u32 v0, v0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 4, v[0:1]
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_add_co_u32 v8, vcc_lo, s20, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v3, vcc_lo
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
.LBB7_6:                                ;   Parent Loop BB7_2 Depth=1
                                        ;     Parent Loop BB7_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB7_8
; %bb.7:                                ;   in Loop: Header=BB7_6 Depth=3
	v_ashrrev_i32_e32 v7, 31, v6
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 4, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, vcc_lo, s16, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s17, v11, vcc_lo
	global_load_b128 v[23:26], v[8:9], off offset:-8
	global_load_b128 v[10:13], v[10:11], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[27:28], v[12:13], v[25:26]
	v_mul_f64 v[25:26], v[10:11], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[10:11], v[23:24], -v[27:28]
	v_fma_f64 v[12:13], v[23:24], v[12:13], v[25:26]
	s_branch .LBB7_9
.LBB7_8:                                ;   in Loop: Header=BB7_6 Depth=3
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr12_vgpr13
.LBB7_9:                                ; %Flow
                                        ;   in Loop: Header=BB7_6 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB7_11
; %bb.10:                               ;   in Loop: Header=BB7_6 Depth=3
	v_add_nc_u32_e32 v10, v19, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 4, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s16, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s17, v11, vcc_lo
	global_load_b128 v[23:26], v[8:9], off offset:-8
	global_load_b128 v[10:13], v[10:11], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[27:28], v[12:13], v[25:26]
	v_mul_f64 v[25:26], v[10:11], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[10:11], v[23:24], -v[27:28]
	v_fma_f64 v[12:13], v[23:24], v[12:13], v[25:26]
.LBB7_11:                               ;   in Loop: Header=BB7_6 Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[0:1], v[0:1], v[10:11]
	v_add_f64 v[2:3], v[2:3], v[12:13]
	v_add_nc_u32_e32 v22, 1, v22
	v_add_co_u32 v8, s1, v8, 16
	v_add_nc_u32_e32 v6, s18, v6
	v_add_co_ci_u32_e64 v9, s1, 0, v9, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v22, v21
	s_or_b32 s25, vcc_lo, s25
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB7_6
; %bb.12:                               ; %Flow46
                                        ;   in Loop: Header=BB7_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
.LBB7_13:                               ; %Flow47
                                        ;   in Loop: Header=BB7_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s24
	v_mad_u64_u32 v[6:7], null, v20, s13, v[4:5]
	v_add_nc_u32_e32 v20, v20, v14
	v_add_nc_u32_e32 v19, v19, v16
	v_cmp_le_i32_e32 vcc_lo, s12, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	s_or_b32 s23, vcc_lo, s23
	v_lshlrev_b64 v[6:7], 4, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s1, s10, v6
	v_add_co_ci_u32_e64 v7, s1, s11, v7, s1
	global_store_b128 v[6:7], v[0:3], off
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB7_4
.LBB7_14:                               ; %Flow50
                                        ;   in Loop: Header=BB7_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e32 v4, s14, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s13, v4
	s_or_b32 s19, vcc_lo, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB7_2
.LBB7_15:                               ; %_Z15_cupy_upfirdn2DIN6thrust7complexIdEEEvPKT_iS5_iiiiiiPS3_ii.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _cupy_upfirdn2D_complex128
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_cupy_upfirdn2D_complex128, .Lfunc_end7-_cupy_upfirdn2D_complex128
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1176
; NumSgprs: 28
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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        .address_space:  global
        .offset:         0
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        .size:           8
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        .size:           4
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        .size:           4
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        .size:           4
        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .size:           2
        .value_kind:     hidden_group_size_x
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        .size:           2
        .value_kind:     hidden_group_size_z
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        .value_kind:     hidden_remainder_x
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        .size:           2
        .value_kind:     hidden_remainder_y
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        .size:           2
        .value_kind:     hidden_remainder_z
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        .size:           8
        .value_kind:     hidden_global_offset_x
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        .size:           8
        .value_kind:     hidden_global_offset_y
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        .size:           8
        .value_kind:     hidden_global_offset_z
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        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 512
    .name:           _cupy_upfirdn1D_float32
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _cupy_upfirdn1D_float32.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .address_space:  global
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        .size:           8
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        .size:           4
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        .value_kind:     hidden_group_size_x
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        .size:           2
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    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 512
    .name:           _cupy_upfirdn1D_float64
    .private_segment_fixed_size: 0
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _cupy_upfirdn1D_float64.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
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    .language:       OpenCL C
    .language_version:
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    .private_segment_fixed_size: 0
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    .sgpr_spill_count: 0
    .symbol:         _cupy_upfirdn1D_complex64.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
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amdhsa.version:
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...

	.end_amdgpu_metadata
