#include "includes.h"
__global__ void GaussianBlur(unsigned int *B,unsigned int *G,unsigned int *R, int numberOfPixels, unsigned int width, int *B_new, int *G_new, int *R_new)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;

if (index >= numberOfPixels){
//printf("%d\n",index);
return;
}

int mask[] = { 1, 2, 1, 2, 4, 2, 1, 2, 1 };
int s = mask[0] + mask[1] + mask[2] + mask[3] + mask[4] + mask[5] + mask[6] + mask[7] + mask[8];

if (index < width){ // dolny rzad pikseli
if (index == 0){ //lewy dolny rog
s = mask[4] + mask[1] + mask[2] + mask[5];
B_new[index] = (int)((B[index] * mask[4] + B[index + width] * mask[1] + B[index + width + 1] * mask[2] + B[index + 1] * mask[5]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + width] * mask[1] + G[index + width + 1] * mask[2] + G[index + 1] * mask[5]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + width] * mask[1] + R[index + width + 1] * mask[2] + R[index + 1] * mask[5]) / s);
return;
}

if (index == width - 1){//prawy dolny rog
s = mask[4] + mask[0] + mask[1] + mask[3];
B_new[index] = (B[index] * mask[4] + B[index + width - 1] * mask[0] + B[index + width] * mask[1] + B[index - 1] * mask[3]);
G_new[index] = (G[index] * mask[4] + G[index + width - 1] * mask[0] + G[index + width] * mask[1] + G[index - 1] * mask[3]);
R_new[index] = (R[index] * mask[4] + R[index + width - 1] * mask[0] + R[index + width] * mask[1] + R[index - 1] * mask[3]);
return;
}
//reszta pikseli w dolnym rzedzie
s = mask[4] + mask[1] + mask[2] + mask[5] + mask[0] + mask[3];
B_new[index] = (int)((B[index] * mask[4] + B[index + width] * mask[1] + B[index + width + 1] * mask[2] + B[index + 1] * mask[5] + B[index + width - 1] * mask[0] + B[index - 1] * mask[3]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + width] * mask[1] + R[index + width + 1] * mask[2] + R[index + 1] * mask[5] + R[index + width - 1] * mask[0] + R[index - 1] * mask[3]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + width] * mask[1] + G[index + width + 1] * mask[2] + G[index + 1] * mask[5] + G[index + width - 1] * mask[0] + G[index - 1] * mask[3]) / s);

return;
}
if (index >= numberOfPixels - width){ //gorny rzad pikseli

if (index == numberOfPixels - width){ //lewy gorny rog
s = mask[4] + mask[5] + mask[7] + mask[8];
B_new[index] = (int)((B[index] * mask[4] + B[index + 1] * mask[5] + B[index - width] * mask[7] + B[index - width + 1] * mask[8]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + 1] * mask[5] + G[index - width] * mask[7] + G[index - width + 1] * mask[8]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + 1] * mask[5] + R[index - width] * mask[7] + R[index - width + 1] * mask[8]) / s);
return;
}

if (index == numberOfPixels - 1){ //prawy gorny rog
s = mask[4] + mask[3] + mask[6] + mask[7];
B_new[index] = (int)((B[index] * mask[4] + B[index - 1] * mask[3] + B[index - width - 1] * mask[6] + B[index - width] * mask[7]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index - 1] * mask[3] + G[index - width - 1] * mask[6] + G[index - width] * mask[7]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index - 1] * mask[3] + R[index - width - 1] * mask[6] + R[index - width] * mask[7]) / s);
return;
}

s = mask[4] + mask[3] + mask[5] + mask[6] + mask[7] + mask[8];
B_new[index] = (int)((B[index] * mask[4] + B[index - 1] * mask[3] + B[index - width - 1] * mask[6] + B[index - width] * mask[7] + B[index + 1] * mask[5] + B[index - width] * mask[8]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index - 1] * mask[3] + R[index - width - 1] * mask[6] + R[index - width] * mask[7] + R[index + 1] * mask[5] + R[index - width] * mask[8]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index - 1] * mask[3] + G[index - width - 1] * mask[6] + G[index - width] * mask[7] + G[index + 1] * mask[5] + G[index - width] * mask[8]) / s);
return;
}
if (index % width == 0){ //lewa sciana
s = mask[4] + mask[1] + mask[2] + mask[5] + mask[8] + mask[7];
B_new[index] = (int)((B[index] * mask[4] + B[index + width] * mask[1] + B[index + width + 1] * mask[2] + B[index + 1] * mask[5] + B[index - width + 1] * mask[8] + B[index - width]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + width] * mask[1] + G[index + width + 1] * mask[2] + G[index + 1] * mask[5] + G[index - width + 1] * mask[8] + G[index - width]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + width] * mask[1] + R[index + width + 1] * mask[2] + R[index + 1] * mask[5] + R[index - width + 1] * mask[8] + R[index - width]) / s);
return;
}
if (index % width == width - 1){ //prawa sciana
s = mask[4] + mask[1] + mask[0] + mask[3] + mask[6] + mask[7];
B_new[index] = (int)((B[index] * mask[4] + B[index + width] * mask[1] + B[index + width - 1] * mask[0] + B[index - 1] * mask[3] + B[index - width - 1] * mask[6] + B[index - width] * mask[7]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + width] * mask[1] + R[index + width - 1] * mask[0] + R[index - 1] * mask[3] + R[index - width - 1] * mask[6] + R[index - width] * mask[7]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + width] * mask[1] + G[index + width - 1] * mask[0] + G[index - 1] * mask[3] + G[index - width - 1] * mask[6] + G[index - width] * mask[7]) / s);
return;
}


int poz_1 = index - width - 1;
int poz_2 = index - width;
int poz_3 = index - width + 1;
int poz_4 = index - 1;
int poz_5 = index;
int poz_6 = index + 1;
int poz_7 = index + width - 1;
int poz_8 = index + width;
int poz_9 = index + width + 1;

B_new[index] = (int)(((B[poz_1] * mask[0]) + (B[poz_2] * mask[1]) + (B[poz_3] * mask[2]) + (B[poz_4] * mask[3]) + (B[poz_5] * mask[4]) + (B[poz_6] * mask[5]) + (B[poz_7] * mask[6]) + (B[poz_8] * mask[7]) + (B[poz_9] * mask[8])) / s);
G_new[index] = (int)(((G[poz_1] * mask[0]) + (G[poz_2] * mask[1]) + (G[poz_3] * mask[2]) + (G[poz_4] * mask[3]) + (G[poz_5] * mask[4]) + (G[poz_6] * mask[5]) + (G[poz_7] * mask[6]) + (G[poz_8] * mask[7]) + (G[poz_9] * mask[8])) / s);
R_new[index] = (int)(((R[poz_1] * mask[0]) + (R[poz_2] * mask[1]) + (R[poz_3] * mask[2]) + (R[poz_4] * mask[3]) + (R[poz_5] * mask[4]) + (R[poz_6] * mask[5]) + (R[poz_7] * mask[6]) + (R[poz_8] * mask[7]) + (R[poz_9] * mask[8])) / s);


}
	.file	"tmpxft_00253bf7_00000000-6_GaussianBlur.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z12GaussianBlurPjS_S_ijPiS0_S0_PjS_S_ijPiS0_S0_
	.type	_Z46__device_stub__Z12GaussianBlurPjS_S_ijPiS0_S0_PjS_S_ijPiS0_S0_, @function
_Z46__device_stub__Z12GaussianBlurPjS_S_ijPiS0_S0_PjS_S_ijPiS0_S0_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 36(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z12GaussianBlurPjS_S_ijPiS0_S0_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z46__device_stub__Z12GaussianBlurPjS_S_ijPiS0_S0_PjS_S_ijPiS0_S0_, .-_Z46__device_stub__Z12GaussianBlurPjS_S_ijPiS0_S0_PjS_S_ijPiS0_S0_
	.globl	_Z12GaussianBlurPjS_S_ijPiS0_S0_
	.type	_Z12GaussianBlurPjS_S_ijPiS0_S0_, @function
_Z12GaussianBlurPjS_S_ijPiS0_S0_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z12GaussianBlurPjS_S_ijPiS0_S0_PjS_S_ijPiS0_S0_
	.cfi_endproc
.LFE2033:
	.size	_Z12GaussianBlurPjS_S_ijPiS0_S0_, .-_Z12GaussianBlurPjS_S_ijPiS0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12GaussianBlurPjS_S_ijPiS0_S0_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12GaussianBlurPjS_S_ijPiS0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void GaussianBlur(unsigned int *B,unsigned int *G,unsigned int *R, int numberOfPixels, unsigned int width, int *B_new, int *G_new, int *R_new)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;

if (index >= numberOfPixels){
//printf("%d\n",index);
return;
}

int mask[] = { 1, 2, 1, 2, 4, 2, 1, 2, 1 };
int s = mask[0] + mask[1] + mask[2] + mask[3] + mask[4] + mask[5] + mask[6] + mask[7] + mask[8];

if (index < width){ // dolny rzad pikseli
if (index == 0){ //lewy dolny rog
s = mask[4] + mask[1] + mask[2] + mask[5];
B_new[index] = (int)((B[index] * mask[4] + B[index + width] * mask[1] + B[index + width + 1] * mask[2] + B[index + 1] * mask[5]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + width] * mask[1] + G[index + width + 1] * mask[2] + G[index + 1] * mask[5]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + width] * mask[1] + R[index + width + 1] * mask[2] + R[index + 1] * mask[5]) / s);
return;
}

if (index == width - 1){//prawy dolny rog
s = mask[4] + mask[0] + mask[1] + mask[3];
B_new[index] = (B[index] * mask[4] + B[index + width - 1] * mask[0] + B[index + width] * mask[1] + B[index - 1] * mask[3]);
G_new[index] = (G[index] * mask[4] + G[index + width - 1] * mask[0] + G[index + width] * mask[1] + G[index - 1] * mask[3]);
R_new[index] = (R[index] * mask[4] + R[index + width - 1] * mask[0] + R[index + width] * mask[1] + R[index - 1] * mask[3]);
return;
}
//reszta pikseli w dolnym rzedzie
s = mask[4] + mask[1] + mask[2] + mask[5] + mask[0] + mask[3];
B_new[index] = (int)((B[index] * mask[4] + B[index + width] * mask[1] + B[index + width + 1] * mask[2] + B[index + 1] * mask[5] + B[index + width - 1] * mask[0] + B[index - 1] * mask[3]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + width] * mask[1] + R[index + width + 1] * mask[2] + R[index + 1] * mask[5] + R[index + width - 1] * mask[0] + R[index - 1] * mask[3]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + width] * mask[1] + G[index + width + 1] * mask[2] + G[index + 1] * mask[5] + G[index + width - 1] * mask[0] + G[index - 1] * mask[3]) / s);

return;
}
if (index >= numberOfPixels - width){ //gorny rzad pikseli

if (index == numberOfPixels - width){ //lewy gorny rog
s = mask[4] + mask[5] + mask[7] + mask[8];
B_new[index] = (int)((B[index] * mask[4] + B[index + 1] * mask[5] + B[index - width] * mask[7] + B[index - width + 1] * mask[8]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + 1] * mask[5] + G[index - width] * mask[7] + G[index - width + 1] * mask[8]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + 1] * mask[5] + R[index - width] * mask[7] + R[index - width + 1] * mask[8]) / s);
return;
}

if (index == numberOfPixels - 1){ //prawy gorny rog
s = mask[4] + mask[3] + mask[6] + mask[7];
B_new[index] = (int)((B[index] * mask[4] + B[index - 1] * mask[3] + B[index - width - 1] * mask[6] + B[index - width] * mask[7]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index - 1] * mask[3] + G[index - width - 1] * mask[6] + G[index - width] * mask[7]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index - 1] * mask[3] + R[index - width - 1] * mask[6] + R[index - width] * mask[7]) / s);
return;
}

s = mask[4] + mask[3] + mask[5] + mask[6] + mask[7] + mask[8];
B_new[index] = (int)((B[index] * mask[4] + B[index - 1] * mask[3] + B[index - width - 1] * mask[6] + B[index - width] * mask[7] + B[index + 1] * mask[5] + B[index - width] * mask[8]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index - 1] * mask[3] + R[index - width - 1] * mask[6] + R[index - width] * mask[7] + R[index + 1] * mask[5] + R[index - width] * mask[8]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index - 1] * mask[3] + G[index - width - 1] * mask[6] + G[index - width] * mask[7] + G[index + 1] * mask[5] + G[index - width] * mask[8]) / s);
return;
}
if (index % width == 0){ //lewa sciana
s = mask[4] + mask[1] + mask[2] + mask[5] + mask[8] + mask[7];
B_new[index] = (int)((B[index] * mask[4] + B[index + width] * mask[1] + B[index + width + 1] * mask[2] + B[index + 1] * mask[5] + B[index - width + 1] * mask[8] + B[index - width]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + width] * mask[1] + G[index + width + 1] * mask[2] + G[index + 1] * mask[5] + G[index - width + 1] * mask[8] + G[index - width]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + width] * mask[1] + R[index + width + 1] * mask[2] + R[index + 1] * mask[5] + R[index - width + 1] * mask[8] + R[index - width]) / s);
return;
}
if (index % width == width - 1){ //prawa sciana
s = mask[4] + mask[1] + mask[0] + mask[3] + mask[6] + mask[7];
B_new[index] = (int)((B[index] * mask[4] + B[index + width] * mask[1] + B[index + width - 1] * mask[0] + B[index - 1] * mask[3] + B[index - width - 1] * mask[6] + B[index - width] * mask[7]) / s);
R_new[index] = (int)((R[index] * mask[4] + R[index + width] * mask[1] + R[index + width - 1] * mask[0] + R[index - 1] * mask[3] + R[index - width - 1] * mask[6] + R[index - width] * mask[7]) / s);
G_new[index] = (int)((G[index] * mask[4] + G[index + width] * mask[1] + G[index + width - 1] * mask[0] + G[index - 1] * mask[3] + G[index - width - 1] * mask[6] + G[index - width] * mask[7]) / s);
return;
}


int poz_1 = index - width - 1;
int poz_2 = index - width;
int poz_3 = index - width + 1;
int poz_4 = index - 1;
int poz_5 = index;
int poz_6 = index + 1;
int poz_7 = index + width - 1;
int poz_8 = index + width;
int poz_9 = index + width + 1;

B_new[index] = (int)(((B[poz_1] * mask[0]) + (B[poz_2] * mask[1]) + (B[poz_3] * mask[2]) + (B[poz_4] * mask[3]) + (B[poz_5] * mask[4]) + (B[poz_6] * mask[5]) + (B[poz_7] * mask[6]) + (B[poz_8] * mask[7]) + (B[poz_9] * mask[8])) / s);
G_new[index] = (int)(((G[poz_1] * mask[0]) + (G[poz_2] * mask[1]) + (G[poz_3] * mask[2]) + (G[poz_4] * mask[3]) + (G[poz_5] * mask[4]) + (G[poz_6] * mask[5]) + (G[poz_7] * mask[6]) + (G[poz_8] * mask[7]) + (G[poz_9] * mask[8])) / s);
R_new[index] = (int)(((R[poz_1] * mask[0]) + (R[poz_2] * mask[1]) + (R[poz_3] * mask[2]) + (R[poz_4] * mask[3]) + (R[poz_5] * mask[4]) + (R[poz_6] * mask[5]) + (R[poz_7] * mask[6]) + (R[poz_8] * mask[7]) + (R[poz_9] * mask[8])) / s);


}
	.text
	.file	"GaussianBlur.hip"
	.globl	_Z27__device_stub__GaussianBlurPjS_S_ijPiS0_S0_ # -- Begin function _Z27__device_stub__GaussianBlurPjS_S_ijPiS0_S0_
	.type	_Z27__device_stub__GaussianBlurPjS_S_ijPiS0_S0_,@function
_Z27__device_stub__GaussianBlurPjS_S_ijPiS0_S0_: # @_Z27__device_stub__GaussianBlurPjS_S_ijPiS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12GaussianBlurPjS_S_ijPiS0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__GaussianBlurPjS_S_ijPiS0_S0_, .Lfunc_end0-_Z27__device_stub__GaussianBlurPjS_S_ijPiS0_S0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12GaussianBlurPjS_S_ijPiS0_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12GaussianBlurPjS_S_ijPiS0_S0_,@object # @_Z12GaussianBlurPjS_S_ijPiS0_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z12GaussianBlurPjS_S_ijPiS0_S0_
	.p2align	3, 0x0
_Z12GaussianBlurPjS_S_ijPiS0_S0_:
	.quad	_Z27__device_stub__GaussianBlurPjS_S_ijPiS0_S0_
	.size	_Z12GaussianBlurPjS_S_ijPiS0_S0_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12GaussianBlurPjS_S_ijPiS0_S0_"
	.size	.L__unnamed_1, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__GaussianBlurPjS_S_ijPiS0_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12GaussianBlurPjS_S_ijPiS0_S0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12GaussianBlurPjS_S_ijPiS0_S0_ ; -- Begin function _Z12GaussianBlurPjS_S_ijPiS0_S0_
	.globl	_Z12GaussianBlurPjS_S_ijPiS0_S0_
	.p2align	8
	.type	_Z12GaussianBlurPjS_S_ijPiS0_S0_,@function
_Z12GaussianBlurPjS_S_ijPiS0_S0_:       ; @_Z12GaussianBlurPjS_S_ijPiS0_S0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b64 s[12:13], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s12, v1
	s_cbranch_execz .LBB0_32
; %bb.1:
	s_clause 0x3
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x20
	s_load_b64 s[0:1], s[0:1], 0x30
	s_mov_b32 s14, exec_lo
	v_cmpx_le_u32_e64 s13, v1
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB0_23
; %bb.2:
	s_sub_i32 s16, s12, s13
	s_mov_b32 s15, exec_lo
	v_cmpx_le_u32_e64 s16, v1
	s_xor_b32 s15, exec_lo, s15
	s_cbranch_execz .LBB0_12
; %bb.3:
	v_cmp_ne_u32_e32 vcc_lo, s16, v1
	s_and_saveexec_b32 s16, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s16, exec_lo, s16
	s_cbranch_execz .LBB0_9
; %bb.4:
	v_subrev_nc_u32_e32 v6, s13, v1
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v5, 0
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, -1, v6
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v7, v5
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v14, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v7, vcc_lo
	s_clause 0x2
	global_load_b64 v[8:9], v[10:11], off offset:-4
	global_load_b32 v12, v[12:13], off
	global_load_b32 v0, v[14:15], off
	v_cmp_ne_u32_e32 vcc_lo, s12, v1
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v1, 2, v9
	s_and_saveexec_b32 s12, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s12
	s_cbranch_execz .LBB0_6
; %bb.5:
	global_load_b32 v9, v[10:11], off offset:4
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v8, v0, v8
	v_add_nc_u32_e32 v1, v12, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v8, v8, v9, 1
	v_add3_u32 v8, v1, v0, v8
	v_add_co_u32 v0, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v12, 0xaaaaaaab, v8
	v_add_co_u32 v8, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v7, vcc_lo
	v_lshrrev_b32_e32 v14, 3, v12
	v_add_co_u32 v12, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v5, vcc_lo
	global_store_b32 v[0:1], v14, off
	s_clause 0x2
	global_load_b32 v0, v[10:11], off
	global_load_b96 v[8:10], v[8:9], off offset:-4
	global_load_b32 v1, v[12:13], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v8, v0, v8
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v1, v9, 2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v8, v8, v10, 1
	v_add3_u32 v8, v1, v0, v8
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v10, 0xaaaaaaab, v8
	v_add_co_u32 v8, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	v_lshrrev_b32_e32 v12, 3, v10
	v_add_co_u32 v10, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v5, vcc_lo
	global_store_b32 v[0:1], v12, off
	s_clause 0x2
	global_load_b32 v0, v[6:7], off
	global_load_b96 v[4:6], v[8:9], off offset:-4
	global_load_b32 v1, v[10:11], off
                                        ; implicit-def: $vgpr8_vgpr9
                                        ; implicit-def: $vgpr12
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v4, v0, v4
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v1, v5, 2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v4, v4, v6, 1
                                        ; implicit-def: $vgpr6_vgpr7
	v_add3_u32 v0, v1, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, 0xaaaaaaab, v0
	v_lshrrev_b32_e32 v4, 3, v0
	v_add_co_u32 v0, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
                                        ; implicit-def: $vgpr2_vgpr3
	global_store_b32 v[0:1], v4, off
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_6:                                ; %Flow
	s_and_not1_saveexec_b32 s12, s12
	s_cbranch_execz .LBB0_8
; %bb.7:
	s_waitcnt vmcnt(0)
	v_add_lshl_u32 v0, v0, v8, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v8, v12, v1, v0
	v_add_co_u32 v0, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
	v_mul_hi_u32 v12, 0x38e38e39, v8
	v_add_co_u32 v8, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v7, vcc_lo
	v_lshrrev_b32_e32 v14, 1, v12
	v_add_co_u32 v12, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v5, vcc_lo
	global_store_b32 v[0:1], v14, off
	s_clause 0x2
	global_load_b64 v[0:1], v[8:9], off offset:-4
	global_load_b32 v8, v[10:11], off
	global_load_b32 v9, v[12:13], off
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v1, 2, v1
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v0, v8, v0, 1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v8, v9, v1, v0
	v_add_co_u32 v0, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
	v_mul_hi_u32 v10, 0x38e38e39, v8
	v_add_co_u32 v8, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	v_lshrrev_b32_e32 v10, 1, v10
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_store_b32 v[0:1], v10, off
	s_clause 0x2
	global_load_b64 v[0:1], v[8:9], off offset:-4
	global_load_b32 v6, v[6:7], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v1, 2, v1
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v0, v6, v0, 1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v4, v1, v0
	v_mul_hi_u32 v0, 0x38e38e39, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshrrev_b32_e32 v4, 1, v0
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_8:                                ; %Flow757
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_9:                                ; %Flow758
	s_and_not1_saveexec_b32 s12, s16
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_ashrrev_i32_e32 v2, 31, v1
	v_subrev_nc_u32_e32 v3, s13, v1
	v_mov_b32_e32 v4, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	v_add_nc_u32_e32 v3, 1, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s8, v0
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v3, vcc_lo
	s_clause 0x2
	global_load_b64 v[7:8], v[7:8], off
	global_load_b32 v4, v[9:10], off
	global_load_b32 v9, v[11:12], off
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v7, 2, v7
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v4, v4, v8, 1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v4, v9, v7, v4
	v_add_co_u32 v7, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v1, vcc_lo
	v_mul_hi_u32 v4, 0x38e38e39, v4
	v_add_co_u32 v9, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v11, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v6, vcc_lo
	v_lshrrev_b32_e32 v4, 1, v4
	v_add_co_u32 v13, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v3, vcc_lo
	global_store_b32 v[7:8], v4, off
	s_clause 0x2
	global_load_b64 v[7:8], v[9:10], off
	global_load_b32 v4, v[11:12], off
	global_load_b32 v9, v[13:14], off
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v7, 2, v7
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v4, v4, v8, 1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v4, v9, v7, v4
	v_add_co_u32 v7, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
	v_mul_hi_u32 v11, 0x38e38e39, v4
	v_add_co_u32 v9, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
	v_lshrrev_b32_e32 v6, 1, v11
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_store_b32 v[7:8], v6, off
	s_clause 0x2
	global_load_b64 v[6:7], v[9:10], off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v3, 2, v6
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v4, v4, v7, 1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v2, v3, v4
	v_mul_hi_u32 v2, 0x38e38e39, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 1, v2
	global_store_b32 v[0:1], v2, off
.LBB0_11:                               ; %Flow759
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_12:                               ; %Flow764
	s_and_not1_saveexec_b32 s12, s15
	s_cbranch_execz .LBB0_22
; %bb.13:
	s_waitcnt vmcnt(0)
	v_cvt_f32_u32_e32 v0, s13
	s_sub_i32 s15, 0, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s15, v0
	s_mov_b32 s15, exec_lo
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v2
	v_mul_hi_u32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s13
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s13, v0
	v_cmp_le_u32_e32 vcc_lo, s13, v0
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v2, s13, v0
	v_cmp_le_u32_e32 vcc_lo, s13, v0
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v0
	s_xor_b32 s15, exec_lo, s15
	s_cbranch_execz .LBB0_19
; %bb.14:
	s_add_i32 s16, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, s16, v0
	s_and_saveexec_b32 s16, vcc_lo
	s_xor_b32 s16, exec_lo, s16
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_subrev_nc_u32_e32 v3, s13, v1
	v_add_nc_u32_e32 v0, s13, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, -1, v3
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_nc_u32_e32 v7, -1, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[9:10], 2, v[1:2]
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[17:18], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v11, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v6, vcc_lo
	v_add_co_u32 v15, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v10, vcc_lo
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_clause 0x2
	global_load_b32 v19, v[13:14], off
	global_load_b64 v[11:12], v[11:12], off
	global_load_b96 v[0:2], v[15:16], off offset:-4
	v_add_co_u32 v13, vcc_lo, s8, v17
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v18, vcc_lo
	v_add_co_u32 v15, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v8, vcc_lo
	s_clause 0x1
	global_load_b64 v[13:14], v[13:14], off
	global_load_b32 v20, v[15:16], off
	v_add_co_u32 v15, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v10, vcc_lo
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v21, 2, v1
	v_add3_u32 v2, v0, v11, v2
	v_add_nc_u32_e32 v11, v12, v19
	v_add_co_u32 v0, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v10, vcc_lo
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v2, v2, v13, 1
	s_waitcnt vmcnt(0)
	v_add3_u32 v13, v11, v21, v20
	v_add_co_u32 v11, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v2, v13, v14, v2
	v_add_co_u32 v13, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v6, vcc_lo
	v_lshrrev_b32_e32 v2, 4, v2
	v_add_co_u32 v19, vcc_lo, s10, v17
	v_add_co_ci_u32_e32 v20, vcc_lo, s11, v18, vcc_lo
	global_store_b32 v[15:16], v2, off
	s_clause 0x2
	global_load_b32 v21, v[13:14], off
	global_load_b64 v[11:12], v[11:12], off
	global_load_b96 v[0:2], v[0:1], off offset:-4
	v_add_co_u32 v13, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v8, vcc_lo
	s_clause 0x1
	global_load_b64 v[15:16], v[19:20], off
	global_load_b32 v19, v[13:14], off
	v_add_co_u32 v13, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v14, vcc_lo, s7, v10, vcc_lo
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v20, 2, v1
	v_add3_u32 v2, v0, v11, v2
	v_add_nc_u32_e32 v11, v12, v21
	v_add_co_u32 v0, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v12, v2, v15, 1
	s_waitcnt vmcnt(0)
	v_add3_u32 v11, v11, v20, v19
	v_add_co_u32 v2, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v11, v11, v16, v12
	v_add_co_u32 v4, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
	v_lshrrev_b32_e32 v6, 4, v11
	v_add_co_u32 v11, vcc_lo, s2, v17
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v18, vcc_lo
	global_store_b32 v[13:14], v6, off
	s_clause 0x2
	global_load_b32 v13, v[4:5], off
	global_load_b64 v[3:4], v[2:3], off
	global_load_b96 v[0:2], v[0:1], off offset:-4
	v_add_co_u32 v5, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
	s_clause 0x1
	global_load_b64 v[7:8], v[11:12], off
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v1, 2, v1
	v_add3_u32 v0, v0, v3, v2
	v_add_nc_u32_e32 v2, v4, v13
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_lshl_u32 v0, v0, v7, 1
	s_waitcnt vmcnt(0)
	v_add3_u32 v1, v2, v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v8, v0
	v_lshrrev_b32_e32 v2, 4, v0
	v_add_co_u32 v0, vcc_lo, s0, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v10, vcc_lo
	global_store_b32 v[0:1], v2, off
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_16:                               ; %Flow760
	s_and_not1_saveexec_b32 s16, s16
	s_cbranch_execz .LBB0_18
; %bb.17:
	v_ashrrev_i32_e32 v2, 31, v1
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s13, v1
	v_subrev_nc_u32_e32 v0, s13, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	v_add_nc_u32_e32 v3, -1, v3
	v_mov_b32_e32 v1, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s8, v7
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
	v_add_co_u32 v13, vcc_lo, s8, v5
	v_add_nc_u32_e32 v3, -1, v0
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v6, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v15, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v10, vcc_lo
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_clause 0x2
	global_load_b64 v[11:12], v[11:12], off offset:-4
	global_load_b32 v17, v[13:14], off
	global_load_b32 v18, v[15:16], off
	v_add_co_u32 v13, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v15, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[13:14], off
	global_load_b32 v13, v[15:16], off
	s_waitcnt vmcnt(3)
	v_add_nc_u32_e32 v11, v11, v17
	s_waitcnt vmcnt(2)
	v_lshl_add_u32 v14, v12, 2, v18
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_lshl_u32 v4, v11, v4, 1
	v_add_co_u32 v11, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v8, vcc_lo
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v14, v13, v4
	v_add_co_u32 v13, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v4, 0xaaaaaaab, v4
	v_add_co_u32 v15, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v16, vcc_lo, s3, v6, vcc_lo
	v_add_co_u32 v17, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v18, vcc_lo, s3, v10, vcc_lo
	v_lshrrev_b32_e32 v4, 3, v4
	v_add_co_u32 v19, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v20, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[11:12], v4, off
	s_clause 0x1
	global_load_b64 v[11:12], v[13:14], off offset:-4
	global_load_b32 v4, v[15:16], off
	v_add_co_u32 v13, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v3, vcc_lo
	s_clause 0x2
	global_load_b32 v15, v[17:18], off
	global_load_b32 v16, v[19:20], off
	global_load_b32 v13, v[13:14], off
	s_waitcnt vmcnt(3)
	v_add_nc_u32_e32 v4, v11, v4
	v_add_co_u32 v11, vcc_lo, s0, v7
	s_waitcnt vmcnt(2)
	v_lshl_add_u32 v14, v12, 2, v15
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v4, v4, v16, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v8, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v4, v14, v13, v4
	v_add_co_u32 v13, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v8, vcc_lo
	v_mul_hi_u32 v15, 0xaaaaaaab, v4
	v_add_co_u32 v4, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v9, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
	v_lshrrev_b32_e32 v6, 3, v15
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_store_b32 v[11:12], v6, off
	s_clause 0x1
	global_load_b64 v[11:12], v[13:14], off offset:-4
	global_load_b32 v4, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_clause 0x2
	global_load_b32 v5, v[9:10], off
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[2:3], off
	s_waitcnt vmcnt(3)
	v_add_nc_u32_e32 v2, v11, v4
	s_waitcnt vmcnt(2)
	v_lshl_add_u32 v3, v12, 2, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v0, v2, v0, 1
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v3, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, 0xaaaaaaab, v0
	v_lshrrev_b32_e32 v2, 3, v0
	v_add_co_u32 v0, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v8, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_18:                               ; %Flow761
	s_or_b32 exec_lo, exec_lo, s16
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_19:                               ; %Flow762
	s_and_not1_saveexec_b32 s15, s15
	s_cbranch_execz .LBB0_21
; %bb.20:
	v_ashrrev_i32_e32 v2, 31, v1
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s13, v1
	v_subrev_nc_u32_e32 v0, s13, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_nc_u32_e32 v3, 1, v3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_add_nc_u32_e32 v3, 1, v0
	v_add_co_u32 v13, vcc_lo, s8, v7
	global_load_b64 v[11:12], v[1:2], off
	v_mov_b32_e32 v1, v4
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v8, vcc_lo
	v_add_co_u32 v15, vcc_lo, s8, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v10, vcc_lo
	v_add_co_u32 v17, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v18, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v19, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v20, vcc_lo, s9, v1, vcc_lo
	s_clause 0x3
	global_load_b32 v4, v[13:14], off
	global_load_b32 v13, v[15:16], off
	global_load_b32 v14, v[17:18], off
	global_load_b32 v15, v[19:20], off
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v11, 2, v11
	s_waitcnt vmcnt(3)
	v_add_lshl_u32 v4, v12, v4, 1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add3_u32 v13, v13, v11, v14
	v_add_co_u32 v11, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v6, vcc_lo
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v13, v15, v4
	v_add_co_u32 v13, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v4, 0xaaaaaaab, v4
	v_add_co_u32 v15, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v8, vcc_lo
	v_add_co_u32 v17, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v18, vcc_lo, s11, v10, vcc_lo
	v_lshrrev_b32_e32 v4, 3, v4
	v_add_co_u32 v19, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v20, vcc_lo, s11, v3, vcc_lo
	global_store_b32 v[11:12], v4, off
	global_load_b64 v[11:12], v[13:14], off
	v_add_co_u32 v13, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v1, vcc_lo
	s_clause 0x3
	global_load_b32 v4, v[15:16], off
	global_load_b32 v15, v[17:18], off
	global_load_b32 v16, v[19:20], off
	global_load_b32 v13, v[13:14], off
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v11, 2, v11
	s_waitcnt vmcnt(3)
	v_add_lshl_u32 v4, v12, v4, 1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add3_u32 v14, v15, v11, v16
	v_add_co_u32 v11, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v6, vcc_lo
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v14, v13, v4
	v_add_co_u32 v13, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v4, 0xaaaaaaab, v4
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	v_lshrrev_b32_e32 v4, 3, v4
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_store_b32 v[11:12], v4, off
	global_load_b64 v[11:12], v[13:14], off
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_clause 0x3
	global_load_b32 v4, v[7:8], off
	global_load_b32 v7, v[9:10], off
	global_load_b32 v2, v[2:3], off
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(4)
	v_lshlrev_b32_e32 v1, 2, v11
	s_waitcnt vmcnt(3)
	v_add_lshl_u32 v3, v12, v4, 1
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v7, v1, v2
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v1, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, 0xaaaaaaab, v0
	v_lshrrev_b32_e32 v2, 3, v0
	v_add_co_u32 v0, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v6, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_21:                               ; %Flow763
	s_or_b32 exec_lo, exec_lo, s15
.LBB0_22:                               ; %Flow765
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
                                        ; implicit-def: $vgpr1_vgpr2
.LBB0_23:                               ; %Flow770
	s_and_not1_saveexec_b32 s12, s14
	s_cbranch_execz .LBB0_32
; %bb.24:
	s_mov_b32 s12, exec_lo
	v_cmpx_ne_u32_e32 0, v1
	s_xor_b32 s12, exec_lo, s12
	s_cbranch_execz .LBB0_30
; %bb.25:
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_nc_u32_e32 v6, s13, v1
	s_add_i32 s14, s13, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s14, v1
	global_load_b32 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v8, 2, v0
	v_add_nc_u32_e32 v0, -1, v6
	s_and_saveexec_b32 s14, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB0_27
; %bb.26:
	v_mov_b32_e32 v7, 0
	global_load_b32 v15, v[4:5], off offset:4
	v_lshlrev_b64 v[9:10], 2, v[6:7]
	v_dual_mov_b32 v1, v7 :: v_dual_add_nc_u32 v6, 1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[13:14], 2, v[6:7]
	v_add_co_u32 v11, vcc_lo, s8, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v10, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s8, v13
	global_load_b32 v16, v[11:12], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v14, vcc_lo
	v_add_co_u32 v11, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v1, vcc_lo
	s_clause 0x2
	global_load_b32 v4, v[4:5], off offset:-4
	global_load_b32 v5, v[6:7], off
	global_load_b32 v6, v[11:12], off
	s_waitcnt vmcnt(3)
	v_add_nc_u32_e32 v7, v15, v16
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v4, v7, v4, 1
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v5, v5, v8
	s_waitcnt vmcnt(0)
	v_add3_u32 v6, v5, v6, v4
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v8, 0xaaaaaaab, v6
	v_add_co_u32 v6, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v11, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v10, vcc_lo
	v_lshrrev_b32_e32 v8, 3, v8
	v_add_co_u32 v15, vcc_lo, s2, v13
	v_add_co_ci_u32_e32 v16, vcc_lo, s3, v14, vcc_lo
	global_store_b32 v[4:5], v8, off
	s_clause 0x2
	global_load_b96 v[4:6], v[6:7], off offset:-4
	global_load_b32 v11, v[11:12], off
	global_load_b32 v12, v[15:16], off
	v_add_co_u32 v7, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v6, v6, v11
	s_waitcnt vmcnt(1)
	v_lshl_add_u32 v5, v5, 2, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v4, v6, v4, 1
	s_waitcnt vmcnt(0)
	v_add3_u32 v6, v5, v7, v4
	v_add_co_u32 v4, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v11, 0xaaaaaaab, v6
	v_add_co_u32 v6, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v10, vcc_lo
	v_lshrrev_b32_e32 v12, 3, v11
	v_add_co_u32 v10, vcc_lo, s10, v13
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v14, vcc_lo
	global_store_b32 v[4:5], v12, off
	s_clause 0x2
	global_load_b96 v[4:6], v[6:7], off offset:-4
	global_load_b32 v7, v[8:9], off
	global_load_b32 v8, v[10:11], off
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v1, v6, v7
	s_waitcnt vmcnt(1)
	v_lshl_add_u32 v5, v5, 2, v8
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v1, v1, v4, 1
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v5, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, 0xaaaaaaab, v0
	v_lshrrev_b32_e32 v4, 3, v0
	v_add_co_u32 v0, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
                                        ; implicit-def: $vgpr2_vgpr3
	global_store_b32 v[0:1], v4, off
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_27:                               ; %Flow766
	s_and_not1_saveexec_b32 s14, s14
	s_cbranch_execz .LBB0_29
; %bb.28:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v7, v1
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v1, vcc_lo
	s_clause 0x2
	global_load_b32 v13, v[9:10], off
	global_load_b32 v14, v[4:5], off offset:-4
	global_load_b32 v15, v[11:12], off
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v9, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v11, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v7, vcc_lo
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v13, v14, v13, 1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v8, v8, v15, v13
	v_add_co_u32 v13, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v1, vcc_lo
	global_store_b32 v[4:5], v8, off
	s_clause 0x2
	global_load_b64 v[4:5], v[9:10], off offset:-4
	global_load_b32 v12, v[11:12], off
	global_load_b32 v13, v[13:14], off
	v_add_co_u32 v8, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v10, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v3, vcc_lo
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v14, 2, v5
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v12, v4, v12, 1
	v_add_co_u32 v4, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v7, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v6, v14, v13, v12
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[8:9], v6, off
	s_clause 0x2
	global_load_b64 v[6:7], v[10:11], off offset:-4
	global_load_b32 v4, v[4:5], off
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v1, 2, v7
	s_waitcnt vmcnt(1)
	v_add_lshl_u32 v4, v6, v4, 1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v1, v0, v4
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_29:                               ; %Flow767
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_30:                               ; %Flow768
	s_and_not1_saveexec_b32 s12, s12
	s_cbranch_execz .LBB0_32
; %bb.31:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s15, 0
	s_mov_b32 s14, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[14:15], 2
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[0:1], v2, s[8:9]
	s_add_u32 s18, s8, s16
	s_addc_u32 s19, s9, s17
	s_add_i32 s14, s13, 1
	s_load_b32 s18, s[18:19], 0x0
	s_lshl_b64 s[12:13], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s8, s8, s12
	s_addc_u32 s9, s9, s13
	s_load_b32 s8, s[8:9], 0x0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v1, s18, v1
	v_lshlrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v1, 1, v1
	v_add_nc_u32_e32 v0, s8, v0
	s_add_u32 s8, s10, s16
	s_addc_u32 s9, s11, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v1
	v_mul_hi_u32 v0, 0x38e38e39, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 1, v0
	global_store_b32 v2, v0, s[4:5]
	s_clause 0x1
	global_load_b64 v[0:1], v2, s[10:11]
	global_load_b32 v3, v2, s[8:9]
	s_add_u32 s4, s10, s12
	s_addc_u32 s5, s11, s13
	global_load_b32 v4, v2, s[4:5]
	s_add_u32 s4, s2, s16
	s_addc_u32 s5, s3, s17
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v0, 2, v0
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v4, v0
	v_lshlrev_b32_e32 v1, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v1
	v_mul_hi_u32 v0, 0x38e38e39, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 1, v0
	global_store_b32 v2, v0, s[6:7]
	s_clause 0x1
	global_load_b64 v[0:1], v2, s[2:3]
	global_load_b32 v3, v2, s[4:5]
	s_add_u32 s2, s2, s12
	s_addc_u32 s3, s3, s13
	global_load_b32 v4, v2, s[2:3]
	s_waitcnt vmcnt(2)
	v_lshlrev_b32_e32 v0, 2, v0
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v1, v1, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v4, v0
	v_lshlrev_b32_e32 v1, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v1
	v_mul_hi_u32 v0, 0x38e38e39, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 1, v0
	global_store_b32 v2, v0, s[0:1]
.LBB0_32:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12GaussianBlurPjS_S_ijPiS0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12GaussianBlurPjS_S_ijPiS0_S0_, .Lfunc_end0-_Z12GaussianBlurPjS_S_ijPiS0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5144
; NumSgprs: 22
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12GaussianBlurPjS_S_ijPiS0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z12GaussianBlurPjS_S_ijPiS0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
