#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>


// Your job is to implemment a bitonic sort. A description of the bitonic sort
// can be see at:
// http://en.wikipedia.org/wiki/Bitonic_sort
    
__device__
    void compare(float *data, int pos1, int pos2){
    if(data[pos1] > data[pos2]){
        float temp = data[pos1];
        data[pos1] = data[pos2];
        data[pos2] = temp;
    }
}
__global__ void batcherBitonicMergesort64(float * d_out, const float * d_in)
{
    // you are guaranteed this is called with <<<1, 64, 64*4>>>
    extern __shared__ float sdata[];
    int tid  = threadIdx.x;
    sdata[tid] = d_in[tid];
    __syncthreads();
    if(tid < 32)
    for (int stage = 1; stage <= 6; stage++)
    {
        //MERGE
        int n = (int) pow((float)2,(float)stage);
        int group = (2*tid)/n;
        int i = tid%(n/2);
        compare(sdata,n*group+i, n*group+n-i-1);
        __syncthreads();
        for (int substage = stage -1; substage > 0; substage--)
        {
            int n = (int) pow((float)2,(float)substage);
            int group = (2*tid)/n;
            int i = tid%(n/2);
            compare(sdata,n*group+i, n*group+i+n/2);
                
        }
        
    }
    __syncthreads();
    d_out[tid] = sdata[tid];
}

int compareFloat (const void * a, const void * b)
{
  if ( *(float*)a <  *(float*)b ) return -1;
  if ( *(float*)a == *(float*)b ) return 0;
  if ( *(float*)a >  *(float*)b ) return 1;
  return 0;                     // should never reach this
}

void printArray(float* in, float* out, int n){
	printf("\n");
	for(int i = 0; i < n; i++){
		printf("%d - (%f - %f) \n",i, in[i],out[i]);
	}
}


int main(int argc, char **argv)
{
    const int ARRAY_SIZE = 64;
    const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);

    // generate the input array on the host
    float h_in[ARRAY_SIZE];
    float h_sorted[ARRAY_SIZE];
    float h_out[ARRAY_SIZE];
    for(int i = 0; i < ARRAY_SIZE; i++) {
        // generate random float in [0, 1]
        h_in[i] = (float)random()/(float)RAND_MAX;
        h_sorted[i] = h_in[i];
    }
    qsort(h_sorted, ARRAY_SIZE, sizeof(float), compareFloat);

    // declare GPU memory pointers
    float * d_in, * d_out;

    // allocate GPU memory
    cudaMalloc((void **) &d_in, ARRAY_BYTES);
    cudaMalloc((void **) &d_out, ARRAY_BYTES);

    // transfer the input array to the GPU
    cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice); 
    batcherBitonicMergesort64<<<1, ARRAY_SIZE, ARRAY_SIZE * sizeof(float)>>>(d_out, d_in);
    
    // copy back the sum from GPU
    cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
    printArray(h_in, h_out, ARRAY_SIZE);
    
    // free GPU memory allocation
    cudaFree(d_in);
    cudaFree(d_out);
}

	.file	"tmpxft_002cba08_00000000-6_bitonic.cudafe1.cpp"
	.text
#APP

#NO_APP
	.globl	_Z12compareFloatPKvS0_
	.type	_Z12compareFloatPKvS0_, @function
_Z12compareFloatPKvS0_:
.LFB2028:
	.cfi_startproc
	endbr64
	movss	(%rdi), %xmm1
	movss	(%rsi), %xmm0
	orl	$-1, %eax
	comiss	%xmm1, %xmm0
	ja	.L1
	ucomiss	%xmm0, %xmm1
	jp	.L6
	movl	$0, %eax
	je	.L1
.L6:
	xorl	%eax, %eax
	comiss	%xmm0, %xmm1
	seta	%al
.L1:
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z12compareFloatPKvS0_, .-_Z12compareFloatPKvS0_
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7comparePfii
	.type	_Z7comparePfii, @function
_Z7comparePfii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z7comparePfii, .-_Z7comparePfii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n"
.LC1:
	.string	"%d - (%f - %f) \n"
	.text
	.globl	_Z10printArrayPfS_i
	.type	_Z10printArrayPfS_i, @function
_Z10printArrayPfS_i:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	xorl	%eax, %eax
	leaq	.LC1(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rsi, %r13
	leaq	.LC0(%rip), %rsi
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdi, %r12
	movl	$2, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
.L12:
	movl	%ebx, %edx
	cmpl	%ebx, %ebp
	jle	.L15
	movq	%r14, %rsi
	movl	$2, %edi
	movb	$2, %al
	cvtss2sd	(%r12,%rbx,4), %xmm0
	cvtss2sd	0(%r13,%rbx,4), %xmm1
	call	__printf_chk@PLT
	incq	%rbx
	jmp	.L12
.L15:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z10printArrayPfS_i, .-_Z10printArrayPfS_i
	.globl	_Z48__device_stub__Z25batcherBitonicMergesort64PfPKfPfPKf
	.type	_Z48__device_stub__Z25batcherBitonicMergesort64PfPKfPfPKf, @function
_Z48__device_stub__Z25batcherBitonicMergesort64PfPKfPfPKf:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z25batcherBitonicMergesort64PfPKf(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L16:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z48__device_stub__Z25batcherBitonicMergesort64PfPKfPfPKf, .-_Z48__device_stub__Z25batcherBitonicMergesort64PfPKfPfPKf
	.globl	_Z25batcherBitonicMergesort64PfPKf
	.type	_Z25batcherBitonicMergesort64PfPKf, @function
_Z25batcherBitonicMergesort64PfPKf:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z25batcherBitonicMergesort64PfPKfPfPKf
	.cfi_endproc
.LFE2056:
	.size	_Z25batcherBitonicMergesort64PfPKf, .-_Z25batcherBitonicMergesort64PfPKf
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%ebx, %ebx
	subq	$824, %rsp
	.cfi_def_cfa_offset 848
	movq	%fs:40, %rax
	movq	%rax, 808(%rsp)
	xorl	%eax, %eax
.L22:
	call	random@PLT
	leaq	40(%rsp), %rbp
	leaq	296(%rsp), %rdi
	cvtsi2ssq	%rax, %xmm0
	mulss	.LC2(%rip), %xmm0
	movss	%xmm0, 40(%rsp,%rbx)
	movss	%xmm0, 296(%rsp,%rbx)
	addq	$4, %rbx
	cmpq	$256, %rbx
	jne	.L22
	leaq	_Z12compareFloatPKvS0_(%rip), %rcx
	movl	$4, %edx
	movl	$64, %esi
	call	qsort@PLT
	movq	%rsp, %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	movl	$256, %r8d
	salq	$6, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z48__device_stub__Z25batcherBitonicMergesort64PfPKfPfPKf
.L23:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$256, %edx
	leaq	552(%rsp), %rbx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movl	$64, %edx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	call	_Z10printArrayPfS_i
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	808(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$824, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z25batcherBitonicMergesort64PfPKf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z25batcherBitonicMergesort64PfPKf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC2:
	.long	805306368
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>


// Your job is to implemment a bitonic sort. A description of the bitonic sort
// can be see at:
// http://en.wikipedia.org/wiki/Bitonic_sort
    
__device__
    void compare(float *data, int pos1, int pos2){
    if(data[pos1] > data[pos2]){
        float temp = data[pos1];
        data[pos1] = data[pos2];
        data[pos2] = temp;
    }
}
__global__ void batcherBitonicMergesort64(float * d_out, const float * d_in)
{
    // you are guaranteed this is called with <<<1, 64, 64*4>>>
    extern __shared__ float sdata[];
    int tid  = threadIdx.x;
    sdata[tid] = d_in[tid];
    __syncthreads();
    if(tid < 32)
    for (int stage = 1; stage <= 6; stage++)
    {
        //MERGE
        int n = (int) pow((float)2,(float)stage);
        int group = (2*tid)/n;
        int i = tid%(n/2);
        compare(sdata,n*group+i, n*group+n-i-1);
        __syncthreads();
        for (int substage = stage -1; substage > 0; substage--)
        {
            int n = (int) pow((float)2,(float)substage);
            int group = (2*tid)/n;
            int i = tid%(n/2);
            compare(sdata,n*group+i, n*group+i+n/2);
                
        }
        
    }
    __syncthreads();
    d_out[tid] = sdata[tid];
}

int compareFloat (const void * a, const void * b)
{
  if ( *(float*)a <  *(float*)b ) return -1;
  if ( *(float*)a == *(float*)b ) return 0;
  if ( *(float*)a >  *(float*)b ) return 1;
  return 0;                     // should never reach this
}

void printArray(float* in, float* out, int n){
	printf("\n");
	for(int i = 0; i < n; i++){
		printf("%d - (%f - %f) \n",i, in[i],out[i]);
	}
}


int main(int argc, char **argv)
{
    const int ARRAY_SIZE = 64;
    const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);

    // generate the input array on the host
    float h_in[ARRAY_SIZE];
    float h_sorted[ARRAY_SIZE];
    float h_out[ARRAY_SIZE];
    for(int i = 0; i < ARRAY_SIZE; i++) {
        // generate random float in [0, 1]
        h_in[i] = (float)random()/(float)RAND_MAX;
        h_sorted[i] = h_in[i];
    }
    qsort(h_sorted, ARRAY_SIZE, sizeof(float), compareFloat);

    // declare GPU memory pointers
    float * d_in, * d_out;

    // allocate GPU memory
    hipMalloc((void **) &d_in, ARRAY_BYTES);
    hipMalloc((void **) &d_out, ARRAY_BYTES);

    // transfer the input array to the GPU
    hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice); 
    batcherBitonicMergesort64<<<1, ARRAY_SIZE, ARRAY_SIZE * sizeof(float)>>>(d_out, d_in);
    
    // copy back the sum from GPU
    hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
    printArray(h_in, h_out, ARRAY_SIZE);
    
    // free GPU memory allocation
    hipFree(d_in);
    hipFree(d_out);
}

	.text
	.file	"bitonic.hip"
	.globl	_Z40__device_stub__batcherBitonicMergesort64PfPKf # -- Begin function _Z40__device_stub__batcherBitonicMergesort64PfPKf
	.type	_Z40__device_stub__batcherBitonicMergesort64PfPKf,@function
_Z40__device_stub__batcherBitonicMergesort64PfPKf: # @_Z40__device_stub__batcherBitonicMergesort64PfPKf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25batcherBitonicMergesort64PfPKf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z40__device_stub__batcherBitonicMergesort64PfPKf, .Lfunc_end0-_Z40__device_stub__batcherBitonicMergesort64PfPKf
	.cfi_endproc
                                        # -- End function
	.globl	_Z12compareFloatPKvS0_          # -- Begin function _Z12compareFloatPKvS0_
	.type	_Z12compareFloatPKvS0_,@function
_Z12compareFloatPKvS0_:                 # @_Z12compareFloatPKvS0_
	.cfi_startproc
# %bb.0:
	movss	(%rdi), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	(%rsi), %xmm1                   # xmm1 = mem[0],zero,zero,zero
	movl	$-1, %eax
	ucomiss	%xmm0, %xmm1
	ja	.LBB1_3
# %bb.1:
	xorl	%eax, %eax
	ucomiss	%xmm1, %xmm0
	jne	.LBB1_2
	jp	.LBB1_2
.LBB1_3:
	retq
.LBB1_2:
	seta	%al
	movzbl	%al, %eax
	retq
.Lfunc_end1:
	.size	_Z12compareFloatPKvS0_, .Lfunc_end1-_Z12compareFloatPKvS0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z10printArrayPfS_i             # -- Begin function _Z10printArrayPfS_i
	.type	_Z10printArrayPfS_i,@function
_Z10printArrayPfS_i:                    # @_Z10printArrayPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movl	$10, %edi
	callq	putchar@PLT
	testl	%ebp, %ebp
	jle	.LBB2_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r12d
	xorl	%r15d, %r15d
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r15,4), %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	(%rbx,%r15,4), %xmm1
	movl	$.L.str.1, %edi
	movl	%r15d, %esi
	movb	$2, %al
	callq	printf
	incq	%r15
	cmpq	%r15, %r12
	jne	.LBB2_2
.LBB2_3:                                # %._crit_edge
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z10printArrayPfS_i, .Lfunc_end2-_Z10printArrayPfS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x30000000                      # float 4.65661287E-10
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$784, %rsp                      # imm = 0x310
	.cfi_def_cfa_offset 800
	.cfi_offset %rbx, -16
	xorl	%ebx, %ebx
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	callq	random
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	mulss	.LCPI3_0(%rip), %xmm0
	movss	%xmm0, 16(%rsp,%rbx,4)
	movss	%xmm0, 272(%rsp,%rbx,4)
	incq	%rbx
	cmpq	$64, %rbx
	jne	.LBB3_1
# %bb.2:
	leaq	272(%rsp), %rdi
	movl	$64, %esi
	movl	$4, %edx
	movl	$_Z12compareFloatPKvS0_, %ecx
	callq	qsort
	leaq	8(%rsp), %rbx
	movl	$256, %esi                      # imm = 0x100
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	16(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	63(%rdi), %rdx
	movl	$256, %r8d                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z40__device_stub__batcherBitonicMergesort64PfPKf
.LBB3_4:
	movq	(%rsp), %rsi
	leaq	528(%rsp), %rbx
	movl	$256, %edx                      # imm = 0x100
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$64, %edx
	callq	_Z10printArrayPfS_i
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$784, %rsp                      # imm = 0x310
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25batcherBitonicMergesort64PfPKf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z25batcherBitonicMergesort64PfPKf,@object # @_Z25batcherBitonicMergesort64PfPKf
	.section	.rodata,"a",@progbits
	.globl	_Z25batcherBitonicMergesort64PfPKf
	.p2align	3, 0x0
_Z25batcherBitonicMergesort64PfPKf:
	.quad	_Z40__device_stub__batcherBitonicMergesort64PfPKf
	.size	_Z25batcherBitonicMergesort64PfPKf, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d - (%f - %f) \n"
	.size	.L.str.1, 17

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z25batcherBitonicMergesort64PfPKf"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__batcherBitonicMergesort64PfPKf
	.addrsig_sym _Z12compareFloatPKvS0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z25batcherBitonicMergesort64PfPKf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z25batcherBitonicMergesort64PfPKf ; -- Begin function _Z25batcherBitonicMergesort64PfPKf
	.globl	_Z25batcherBitonicMergesort64PfPKf
	.p2align	8
	.type	_Z25batcherBitonicMergesort64PfPKf,@function
_Z25batcherBitonicMergesort64PfPKf:     ; @_Z25batcherBitonicMergesort64PfPKf
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v1, 2, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v2, 0, v1
	s_waitcnt lgkmcnt(0)
	global_load_b32 v3, v1, s[2:3]
	s_mov_b32 s2, 2
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_9
; %bb.1:                                ; %.preheader
	v_lshlrev_b32_e32 v3, 1, v0
	s_mov_b32 s4, 1
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v4, s4
	v_mul_f32_e32 v5, 0x3f317218, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, 0x3f317218, v4, -v5
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	v_fmac_f32_e32 v6, 0xb102e308, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v6
	v_cndmask_b32_e32 v7, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7
	v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7|
	v_sub_f32_e32 v9, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, 0x3fb8aa3b, v9
	v_fma_f32 v11, 0x3fb8aa3b, v9, -v10
	v_rndne_f32_e32 v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v11, 0x32a5705f, v9 :: v_dual_sub_f32 v10, v10, v12
	v_add_f32_e32 v10, v10, v11
	v_sub_f32_e32 v4, v4, v5
	v_cvt_i32_f32_e32 v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v5, v10, v5
	v_sub_f32_e32 v4, v6, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
	v_dual_add_f32 v4, v8, v4 :: v_dual_cndmask_b32 v5, 0x7f800000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v5, v4, v5
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v5
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e64 v4, |v4|
	v_readfirstlane_b32 s5, v4
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshr_b32 s6, s5, 31
	v_add_nc_u32_e32 v6, v4, v5
	s_add_i32 s5, s5, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_ashr_i32 s6, s5, 1
	s_ashr_i32 s5, s5, 31
	v_xor_b32_e32 v5, v6, v5
	s_add_i32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s6, s5
	v_cvt_f32_u32_e32 v7, s5
	s_sub_i32 s6, 0, s5
	v_cvt_f32_u32_e32 v6, v5
	v_sub_nc_u32_e32 v8, 0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v7, v7
	v_rcp_iflag_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x4f7ffffe, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v7, v7
	v_mul_lo_u32 v9, s6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v9, v7, v9
	v_add_nc_u32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v0, v7
	v_mul_lo_u32 v7, v7, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v0, v7
	v_subrev_nc_u32_e32 v9, s5, v7
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v6, v6
	v_mul_lo_u32 v8, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v8, v6, v8
	v_add_nc_u32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, v3, v6
	v_mul_lo_u32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v3, v6
	v_sub_nc_u32_e32 v8, v6, v5
	v_cmp_ge_u32_e32 vcc_lo, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v7
	v_sub_nc_u32_e32 v8, v6, v5
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v9, s5, v7
	v_cndmask_b32_e32 v5, v6, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v7
	v_lshlrev_b32_e32 v8, 2, v4
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v3, v5
	v_cndmask_b32_e32 v6, v7, v9, vcc_lo
	v_lshl_add_u32 v5, v5, 2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_not_b32_e32 v7, v6
	v_lshl_add_u32 v4, v6, 2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v7, 2, v7
	v_add3_u32 v5, v5, v8, v7
	ds_load_b32 v6, v4
	ds_load_b32 v7, v5
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v7
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ds_store_b32 v4, v7
	ds_store_b32 v5, v6
.LBB0_4:                                ; %_Z7comparePfii.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_cmp_lt_u32 s4, 2
	s_mov_b32 s5, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_8
.LBB0_5:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s6, s5, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v4, s6
	v_mul_f32_e32 v5, 0x3f317218, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, 0x3f317218, v4, -v5
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	v_fmac_f32_e32 v6, 0xb102e308, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v5, v6
	v_cndmask_b32_e32 v7, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7
	v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7|
	v_sub_f32_e32 v9, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, 0x3fb8aa3b, v9
	v_fma_f32 v11, 0x3fb8aa3b, v9, -v10
	v_rndne_f32_e32 v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v11, 0x32a5705f, v9 :: v_dual_sub_f32 v10, v10, v12
	v_add_f32_e32 v10, v10, v11
	v_sub_f32_e32 v4, v4, v5
	v_cvt_i32_f32_e32 v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v10, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v5, v10, v5
	v_sub_f32_e32 v4, v6, v4
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
	v_dual_add_f32 v4, v8, v4 :: v_dual_cndmask_b32 v5, 0x7f800000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v5, v4, v5
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v5
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e64 v4, |v4|
	v_ashrrev_i32_e32 v5, 31, v4
	v_readfirstlane_b32 s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v5
	s_lshr_b32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s6, s6, s7
	v_xor_b32_e32 v4, v4, v5
	s_ashr_i32 s7, s6, 1
	s_ashr_i32 s6, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s8, s7, s6
	v_cvt_f32_u32_e32 v5, v4
	s_xor_b32 s6, s8, s6
	v_sub_nc_u32_e32 v7, 0, v4
	v_cvt_f32_u32_e32 v6, s6
	s_sub_i32 s8, 0, s6
	v_rcp_iflag_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_mul_f32 v6, 0x4f7ffffe, v6
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v6, v6
	v_mul_lo_u32 v7, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, s8, v6
	v_mul_hi_u32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v6, v8
	v_add_nc_u32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v6, v8
	v_mul_hi_u32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v0, v6
	v_mul_lo_u32 v5, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, s6
	v_sub_nc_u32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v0, v6
	v_sub_nc_u32_e32 v7, v5, v4
	v_cmp_ge_u32_e32 vcc_lo, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v5, v5, v7, vcc_lo
	v_subrev_nc_u32_e32 v7, s6, v6
	v_cmp_le_u32_e32 vcc_lo, s6, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v8, v5, v4
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v5, v8, vcc_lo
	v_subrev_nc_u32_e32 v5, s6, v6
	v_cmp_le_u32_e32 vcc_lo, s6, v6
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v6, v5, vcc_lo
	v_sub_nc_u32_e32 v4, v3, v4
	v_lshlrev_b32_e32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v4, 2, v4
	v_add3_u32 v4, 0, v4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v5, s7, 2, v4
	ds_load_b32 v6, v4
	ds_load_b32 v7, v5
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_f32_e32 v6, v7
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
	ds_store_b32 v4, v7
	ds_store_b32 v5, v6
.LBB0_7:                                ; %_Z7comparePfii.exit39
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s5, 3
	s_cbranch_scc0 .LBB0_5
.LBB0_8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s4, s4, 1
	s_add_i32 s2, s2, 1
	s_cmp_eq_u32 s4, 7
	s_cbranch_scc0 .LBB0_2
.LBB0_9:                                ; %Flow51
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v0, v2
	s_waitcnt lgkmcnt(0)
	global_store_b32 v1, v0, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25batcherBitonicMergesort64PfPKf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 9
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z25batcherBitonicMergesort64PfPKf, .Lfunc_end0-_Z25batcherBitonicMergesort64PfPKf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1464
; NumSgprs: 11
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 11
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25batcherBitonicMergesort64PfPKf
    .private_segment_fixed_size: 0
    .sgpr_count:     11
    .sgpr_spill_count: 0
    .symbol:         _Z25batcherBitonicMergesort64PfPKf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
