#define VERTICES 600

__constant__ float2 d_Vertices[VERTICES];

//tuning parameters
//block_size_x any sensible thread block size
//tile_size any sensible tile size value
//prefetch 0 or 1 for reusing constant memory from previous iteration

//#ifndef prefetch
//#define prefetch 0
//#endif

#ifndef use_bitmap
#define use_bitmap 0
#define coalesce_bitmap 0
#endif

#ifndef block_size_x
#define block_size_x 256
#endif

#ifndef tile_size
#define tile_size 1
#endif


__global__ void cn_PnPoly(int* bitmap, float2* points, int n) {
    int ti = blockIdx.x * block_size_x * tile_size + threadIdx.x;

    if (ti < n) {

        // the crossing number counter
        int cn[tile_size];
        float2 p[tile_size];
        #pragma unroll
        for (int k=0; k<tile_size; k++) {
            cn[k] = 0;
            p[k] = points[ti+k*block_size_x];
        }

        int k = VERTICES-1;
//        #if prefetch == 1
//        float2 vj; // = d_Vertices[k];
//        float2 vk;
//        #endif

        // loop through all edges of the polygon
        for (int j=0; j<VERTICES; k = j++) {    // edge from v to vp

//            #if prefetch == 1
//            float2 vj = d_Vertices[j]; 
//            float2 vk = d_Vertices[k]; 
//            #else
            float2 vj = d_Vertices[j]; 
            float2 vk = d_Vertices[k]; 
//            #endif

            #if method == 1
            float vb = (vj.x - vk.x) / (vj.y - vk.y);
            #endif

            #pragma unroll
            for (int i=0; i<tile_size; i++) {

                #if method == 0
                if ( ((vj.y>p[i].y) != (vk.y>p[i].y)) &&
                        (p[i].x < (vk.x-vj.x) * (p[i].y-vj.y) / (vk.y-vj.y) + vj.x) ) {
                    cn[i] = !cn[i];
                }
                #elif method == 1
                int b = ((vk.y <= p[k].y) && (vj.y > p[k].y)) || ((vk.y > p[k].y) && (vj.y <= p[k].y));
                cn[k] += b && (p[k].x < vk.x + vb * (p[k].y - vj.y));

                #endif


            }
        }


        #if use_bitmap == 1
        int lane_index = threadIdx.x & (32 - 1);
        unsigned int bitstring[tile_size];
        #if coalesce_bitmap == 1
        __shared__ unsigned int block_output[tile_size*block_size_x/32];
        int warp_id = threadIdx.x/32;
        #endif

        #pragma unroll
        for (int k=0; k<tile_size; k++) {
            //write at my position in bitstring
            bitstring[k] = (cn[k] & 1) << (32-lane_index);
            //compute sum of bitstring within warp
            #pragma unroll
            for (unsigned int s=16; s>0; s>>=1) {
                bitstring[k] += __shfl_xor(bitstring[k], s);
            }

            #if coalesce_bitmap == 1
            //store bitstring for this warp in shared buffer
            if (lane_index == 0) {
                block_output[warp_id+k*block_size_x/32] = bitstring[k];
            }
            #endif
        }
        __syncthreads();

        #endif

        #pragma unroll
        for (int k=0; k<tile_size; k++) {

            #if use_bitmap == 0
            bitmap[ti+k*block_size_x] = (cn[k] & 1); // 0 if even (out), and 1 if odd (in)

            #elif use_bitmap == 1
                #if coalesce_bitmap == 0
                if (lane_index == 0) {
                    bitmap[ti/32+k*block_size_x/32] = bitstring[k];
                }
                #elif coalesce_bitmap == 1
                //write back results in coalesced manner
                if (threadIdx.x < block_size_x/32) {
                    bitmap[ti/32+k*block_size_x/32] = block_output[warp_id];
                }
                #endif

            #elif use_bitmap == 2
            if (cn[k] & 1 == 1) {
                bitmap[ti+k*block_size_x] = 1; // 0 if even (out), and 1 if odd (in)
            }

            #endif
        }
    }
}




__global__ void cn_PnPoly_naive(int* bitmap, float2* points, int n) {
    int ti = blockIdx.x * blockDim.x + threadIdx.x;
//    int ti = blockIdx.y * gridDim.x * blockDim.x + blockIdx.x * blockDim.x + threadIdx.x;

    if (ti < n) {

        // the crossing number counter
        int c = 0;
        float2 p = points[ti];

        int k = VERTICES-1;

        for (int j=0; j<VERTICES; k = j++) {    // edge from v to vp

            float2 vj = d_Vertices[j]; 
            float2 vk = d_Vertices[k]; 

            if ( ((vj.y>p.y) != (vk.y>p.y)) &&
                    (p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
                c = !c;

        }

        bitmap[ti] = c; // 0 if even (out), and 1 if odd (in)

    }
}


/*CPU version*/
float pnpoly_cn(int *bitmap, float2 *v, float2 *p) {
    int nvert = VERTICES;
    int npoint = 20000;

    int i = 0;

    for (i = 0; i < npoint; i++) {
        int j, k, c = 0;
        for (j = 0, k = nvert-1; j < nvert; k = j++) {
            if ( ((v[j].y>p[i].y) != (v[k].y>p[i].y)) &&
                    (p[i].x < (v[k].x-v[j].x) * (p[i].y-v[j].y) / (v[k].y-v[j].y) + v[j].x) )
                c = !c;
        }
        bitmap[i] = c & 1;
    }

    return 0.0;
}

/*GPU version*/
__global__ void pnpoly_cn_gpu(int *bitmap, float2 *points, int n) {
    int i = blockIdx.x * block_size_x + threadIdx.x;

    if (i < n) {

        float2 p = points[i];
        int c = 0;
        int k = VERTICES-1;
        int j = 0;

        for (j = 0; j < VERTICES; k = j++) {
            float2 vj = d_Vertices[j]; 
            float2 vk = d_Vertices[k]; 

            if ( ((vj.y>p.y) != (vk.y>p.y)) &&
                    (p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
                c = !c;

        }

        bitmap[i] = c;

    }
}

	.file	"tmpxft_0030c87d_00000000-6_pnpoly.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9pnpoly_cnPiP6float2S1_
	.type	_Z9pnpoly_cnPiP6float2S1_, @function
_Z9pnpoly_cnPiP6float2S1_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rsi, %rcx
	movq	%rdi, %r8
	movq	%rdx, %rsi
	xorl	%edx, %edx
.L3:
	movss	4(%rsi,%rdx,8), %xmm2
	xorl	%eax, %eax
	xorl	%edi, %edi
	movl	$599, %r10d
.L6:
	movss	4(%rcx,%rax,8), %xmm3
	movslq	%r10d, %r9
	movl	%eax, %r10d
	leaq	(%rcx,%r9,8), %r9
	comiss	%xmm2, %xmm3
	movss	4(%r9), %xmm1
	seta	%bl
	comiss	%xmm2, %xmm1
	seta	%r11b
	cmpb	%r11b, %bl
	je	.L4
	movss	(%rcx,%rax,8), %xmm4
	movss	(%r9), %xmm0
	movaps	%xmm2, %xmm5
	subss	%xmm3, %xmm1
	subss	%xmm3, %xmm5
	subss	%xmm4, %xmm0
	mulss	%xmm5, %xmm0
	divss	%xmm1, %xmm0
	addss	%xmm4, %xmm0
	comiss	(%rsi,%rdx,8), %xmm0
	jbe	.L4
	xorl	$1, %edi
.L4:
	incq	%rax
	cmpq	$600, %rax
	jne	.L6
	movl	%edi, (%r8,%rdx,4)
	incq	%rdx
	cmpq	$20000, %rdx
	jne	.L3
	xorps	%xmm0, %xmm0
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z9pnpoly_cnPiP6float2S1_, .-_Z9pnpoly_cnPiP6float2S1_
	.globl	_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i
	.type	_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i, @function
_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9cn_PnPolyPiP6float2i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L12:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i, .-_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i
	.globl	_Z9cn_PnPolyPiP6float2i
	.type	_Z9cn_PnPolyPiP6float2i, @function
_Z9cn_PnPolyPiP6float2i:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z9cn_PnPolyPiP6float2iPiP6float2i
	.cfi_endproc
.LFE2034:
	.size	_Z9cn_PnPolyPiP6float2i, .-_Z9cn_PnPolyPiP6float2i
	.globl	_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i
	.type	_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i, @function
_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15cn_PnPoly_naivePiP6float2i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L17:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i, .-_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i
	.globl	_Z15cn_PnPoly_naivePiP6float2i
	.type	_Z15cn_PnPoly_naivePiP6float2i, @function
_Z15cn_PnPoly_naivePiP6float2i:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z15cn_PnPoly_naivePiP6float2iPiP6float2i
	.cfi_endproc
.LFE2036:
	.size	_Z15cn_PnPoly_naivePiP6float2i, .-_Z15cn_PnPoly_naivePiP6float2i
	.globl	_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i
	.type	_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i, @function
_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z13pnpoly_cn_gpuPiP6float2i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L22:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i, .-_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i
	.globl	_Z13pnpoly_cn_gpuPiP6float2i
	.type	_Z13pnpoly_cn_gpuPiP6float2i, @function
_Z13pnpoly_cn_gpuPiP6float2i:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z13pnpoly_cn_gpuPiP6float2iPiP6float2i
	.cfi_endproc
.LFE2038:
	.size	_Z13pnpoly_cn_gpuPiP6float2i, .-_Z13pnpoly_cn_gpuPiP6float2i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z13pnpoly_cn_gpuPiP6float2i"
.LC2:
	.string	"_Z15cn_PnPoly_naivePiP6float2i"
.LC3:
	.string	"_Z9cn_PnPolyPiP6float2i"
.LC4:
	.string	"d_Vertices"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13pnpoly_cn_gpuPiP6float2i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15cn_PnPoly_naivePiP6float2i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9cn_PnPolyPiP6float2i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movl	$4800, %r9d
	leaq	_ZL10d_Vertices(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2040:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL10d_Vertices
	.comm	_ZL10d_Vertices,4800,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define VERTICES 600

__constant__ float2 d_Vertices[VERTICES];

//tuning parameters
//block_size_x any sensible thread block size
//tile_size any sensible tile size value
//prefetch 0 or 1 for reusing constant memory from previous iteration

//#ifndef prefetch
//#define prefetch 0
//#endif

#ifndef use_bitmap
#define use_bitmap 0
#define coalesce_bitmap 0
#endif

#ifndef block_size_x
#define block_size_x 256
#endif

#ifndef tile_size
#define tile_size 1
#endif


__global__ void cn_PnPoly(int* bitmap, float2* points, int n) {
    int ti = blockIdx.x * block_size_x * tile_size + threadIdx.x;

    if (ti < n) {

        // the crossing number counter
        int cn[tile_size];
        float2 p[tile_size];
        #pragma unroll
        for (int k=0; k<tile_size; k++) {
            cn[k] = 0;
            p[k] = points[ti+k*block_size_x];
        }

        int k = VERTICES-1;
//        #if prefetch == 1
//        float2 vj; // = d_Vertices[k];
//        float2 vk;
//        #endif

        // loop through all edges of the polygon
        for (int j=0; j<VERTICES; k = j++) {    // edge from v to vp

//            #if prefetch == 1
//            float2 vj = d_Vertices[j]; 
//            float2 vk = d_Vertices[k]; 
//            #else
            float2 vj = d_Vertices[j]; 
            float2 vk = d_Vertices[k]; 
//            #endif

            #if method == 1
            float vb = (vj.x - vk.x) / (vj.y - vk.y);
            #endif

            #pragma unroll
            for (int i=0; i<tile_size; i++) {

                #if method == 0
                if ( ((vj.y>p[i].y) != (vk.y>p[i].y)) &&
                        (p[i].x < (vk.x-vj.x) * (p[i].y-vj.y) / (vk.y-vj.y) + vj.x) ) {
                    cn[i] = !cn[i];
                }
                #elif method == 1
                int b = ((vk.y <= p[k].y) && (vj.y > p[k].y)) || ((vk.y > p[k].y) && (vj.y <= p[k].y));
                cn[k] += b && (p[k].x < vk.x + vb * (p[k].y - vj.y));

                #endif


            }
        }


        #if use_bitmap == 1
        int lane_index = threadIdx.x & (32 - 1);
        unsigned int bitstring[tile_size];
        #if coalesce_bitmap == 1
        __shared__ unsigned int block_output[tile_size*block_size_x/32];
        int warp_id = threadIdx.x/32;
        #endif

        #pragma unroll
        for (int k=0; k<tile_size; k++) {
            //write at my position in bitstring
            bitstring[k] = (cn[k] & 1) << (32-lane_index);
            //compute sum of bitstring within warp
            #pragma unroll
            for (unsigned int s=16; s>0; s>>=1) {
                bitstring[k] += __shfl_xor(bitstring[k], s);
            }

            #if coalesce_bitmap == 1
            //store bitstring for this warp in shared buffer
            if (lane_index == 0) {
                block_output[warp_id+k*block_size_x/32] = bitstring[k];
            }
            #endif
        }
        __syncthreads();

        #endif

        #pragma unroll
        for (int k=0; k<tile_size; k++) {

            #if use_bitmap == 0
            bitmap[ti+k*block_size_x] = (cn[k] & 1); // 0 if even (out), and 1 if odd (in)

            #elif use_bitmap == 1
                #if coalesce_bitmap == 0
                if (lane_index == 0) {
                    bitmap[ti/32+k*block_size_x/32] = bitstring[k];
                }
                #elif coalesce_bitmap == 1
                //write back results in coalesced manner
                if (threadIdx.x < block_size_x/32) {
                    bitmap[ti/32+k*block_size_x/32] = block_output[warp_id];
                }
                #endif

            #elif use_bitmap == 2
            if (cn[k] & 1 == 1) {
                bitmap[ti+k*block_size_x] = 1; // 0 if even (out), and 1 if odd (in)
            }

            #endif
        }
    }
}




__global__ void cn_PnPoly_naive(int* bitmap, float2* points, int n) {
    int ti = blockIdx.x * blockDim.x + threadIdx.x;
//    int ti = blockIdx.y * gridDim.x * blockDim.x + blockIdx.x * blockDim.x + threadIdx.x;

    if (ti < n) {

        // the crossing number counter
        int c = 0;
        float2 p = points[ti];

        int k = VERTICES-1;

        for (int j=0; j<VERTICES; k = j++) {    // edge from v to vp

            float2 vj = d_Vertices[j]; 
            float2 vk = d_Vertices[k]; 

            if ( ((vj.y>p.y) != (vk.y>p.y)) &&
                    (p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
                c = !c;

        }

        bitmap[ti] = c; // 0 if even (out), and 1 if odd (in)

    }
}


/*CPU version*/
float pnpoly_cn(int *bitmap, float2 *v, float2 *p) {
    int nvert = VERTICES;
    int npoint = 20000;

    int i = 0;

    for (i = 0; i < npoint; i++) {
        int j, k, c = 0;
        for (j = 0, k = nvert-1; j < nvert; k = j++) {
            if ( ((v[j].y>p[i].y) != (v[k].y>p[i].y)) &&
                    (p[i].x < (v[k].x-v[j].x) * (p[i].y-v[j].y) / (v[k].y-v[j].y) + v[j].x) )
                c = !c;
        }
        bitmap[i] = c & 1;
    }

    return 0.0;
}

/*GPU version*/
__global__ void pnpoly_cn_gpu(int *bitmap, float2 *points, int n) {
    int i = blockIdx.x * block_size_x + threadIdx.x;

    if (i < n) {

        float2 p = points[i];
        int c = 0;
        int k = VERTICES-1;
        int j = 0;

        for (j = 0; j < VERTICES; k = j++) {
            float2 vj = d_Vertices[j]; 
            float2 vk = d_Vertices[k]; 

            if ( ((vj.y>p.y) != (vk.y>p.y)) &&
                    (p.x < (vk.x-vj.x) * (p.y-vj.y) / (vk.y-vj.y) + vj.x) )
                c = !c;

        }

        bitmap[i] = c;

    }
}

	.text
	.file	"pnpoly.hip"
	.globl	_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi # -- Begin function _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.type	_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi,@function
_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi: # @_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end0-_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi # -- Begin function _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.type	_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi,@function
_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi: # @_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, .Lfunc_end1-_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.cfi_endproc
                                        # -- End function
	.globl	_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_ # -- Begin function _Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_
	.type	_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_,@function
_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_: # @_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
.LBB2_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	movss	4(%rdx,%rax,8), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	$599, %r8d                      # imm = 0x257
	xorl	%r9d, %r9d
	xorl	%ecx, %ecx
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r8d, %r10d
	movq	%r9, %r8
	movss	4(%rsi,%r9,8), %xmm1            # xmm1 = mem[0],zero,zero,zero
	movss	4(%rsi,%r10,8), %xmm2           # xmm2 = mem[0],zero,zero,zero
	movaps	%xmm0, %xmm3
	cmpltps	%xmm1, %xmm3
	movaps	%xmm0, %xmm4
	cmpnltps	%xmm2, %xmm4
	xorps	%xmm3, %xmm4
	movd	%xmm4, %r9d
	testb	$1, %r9b
	jne	.LBB2_5
# %bb.3:                                #   in Loop: Header=BB2_2 Depth=2
	movss	(%rsi,%r10,8), %xmm3            # xmm3 = mem[0],zero,zero,zero
	movss	(%rsi,%r8,8), %xmm4             # xmm4 = mem[0],zero,zero,zero
	subss	%xmm4, %xmm3
	movaps	%xmm0, %xmm5
	subss	%xmm1, %xmm5
	mulss	%xmm3, %xmm5
	subss	%xmm1, %xmm2
	divss	%xmm2, %xmm5
	addss	%xmm4, %xmm5
	ucomiss	(%rdx,%rax,8), %xmm5
	jbe	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_2 Depth=2
	xorl	%r9d, %r9d
	testl	%ecx, %ecx
	sete	%r9b
	movl	%r9d, %ecx
.LBB2_5:                                #   in Loop: Header=BB2_2 Depth=2
	leaq	1(%r8), %r9
	cmpq	$600, %r9                       # imm = 0x258
	jne	.LBB2_2
# %bb.6:                                #   in Loop: Header=BB2_1 Depth=1
	andl	$1, %ecx
	movl	%ecx, (%rdi,%rax,4)
	incq	%rax
	cmpq	$20000, %rax                    # imm = 0x4E20
	jne	.LBB2_1
# %bb.7:
	xorps	%xmm0, %xmm0
	retq
.Lfunc_end2:
	.size	_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_, .Lfunc_end2-_Z9pnpoly_cnPiP15HIP_vector_typeIfLj2EES2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi # -- Begin function _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.type	_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi,@function
_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi: # @_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end3-_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$d_Vertices, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$4800, %r9d                     # imm = 0x12C0
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_Vertices,@object              # @d_Vertices
	.local	d_Vertices
	.comm	d_Vertices,4800,16
	.type	_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi,@object # @_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.section	.rodata,"a",@progbits
	.globl	_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.p2align	3, 0x0
_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi:
	.quad	_Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.size	_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, 8

	.type	_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi,@object # @_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.globl	_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.p2align	3, 0x0
_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi:
	.quad	_Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.size	_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, 8

	.type	_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi,@object # @_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.globl	_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.p2align	3, 0x0
_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi:
	.quad	_Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.size	_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi"
	.size	.L__unnamed_1, 41

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi"
	.size	.L__unnamed_2, 48

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi"
	.size	.L__unnamed_3, 46

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"d_Vertices"
	.size	.L__unnamed_4, 11

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.addrsig_sym _Z30__device_stub__cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.addrsig_sym _Z28__device_stub__pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_Vertices
	.addrsig_sym _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.addrsig_sym _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.addrsig_sym _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi ; -- Begin function _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.globl	_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
	.p2align	8
	.type	_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi,@function
_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi: ; @_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
; %bb.0:
	s_load_b32 s2, s[0:1], 0x10
	v_lshl_add_u32 v0, s15, 8, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.1:                                ; %.critedge
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_Vertices@rel32@lo+4800
	s_addc_u32 s1, s1, d_Vertices@rel32@hi+4808
	v_mov_b32_e32 v4, 0
	s_load_b32 s11, s[0:1], 0x0
	s_mov_b32 s3, 0
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	s_movk_i32 s2, 0x257
	s_mov_b32 s1, s3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b64 s[6:7], 4
	global_load_b64 v[2:3], v[2:3], off
.LBB0_2:                                ; %.critedge40
                                        ; =>This Inner Loop Header: Depth=1
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, d_Vertices@rel32@lo+4
	s_addc_u32 s9, s9, d_Vertices@rel32@hi+12
	s_add_u32 s12, s6, s8
	s_addc_u32 s13, s7, s9
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s0, s11, v3
	s_load_b32 s10, s[12:13], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, vcc_lo, s0
	s_xor_b32 s12, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s12
	s_cbranch_execz .LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_lshl_b64 s[12:13], s[2:3], 3
	v_subrev_f32_e32 v5, s10, v3
	s_add_u32 s8, s12, s8
	s_addc_u32 s9, s13, s9
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, d_Vertices@rel32@lo
	s_addc_u32 s13, s13, d_Vertices@rel32@hi+8
	s_add_u32 s12, s6, s12
	s_addc_u32 s13, s7, s13
	s_clause 0x1
	s_load_b32 s2, s[8:9], 0x0
	s_load_b32 s8, s[12:13], 0x0
	v_sub_f32_e64 v7, s11, s10
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e64 v6, s2, s8
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v5, v6
	v_div_scale_f32 v6, null, v7, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v6, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	v_div_scale_f32 v9, vcc_lo, v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v9, v8
	v_fma_f32 v11, -v6, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v8
	v_fma_f32 v6, -v6, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v8, v10
	v_div_fixup_f32 v5, v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, s8, v5
	v_cmpx_lt_f32_e32 v2, v5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s1, 1
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmpk_lg_i32 s6, 0x12c4
	s_cbranch_scc0 .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s11, s10
	s_mov_b32 s2, s1
	s_mov_b32 s1, s0
	s_branch .LBB0_2
.LBB0_8:                                ; %.critedge42
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_and_b32_e32 v2, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end0-_Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 520
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi ; -- Begin function _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.globl	_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
	.p2align	8
	.type	_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi,@function
_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi: ; @_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_9
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_Vertices@rel32@lo+4800
	s_addc_u32 s1, s1, d_Vertices@rel32@hi+4808
	v_mov_b32_e32 v0, 0
	s_load_b32 s11, s[0:1], 0x0
	s_mov_b32 s3, 0
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_movk_i32 s2, 0x257
	s_mov_b32 s1, s3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_mov_b64 s[6:7], 4
	global_load_b64 v[3:4], v[3:4], off
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, d_Vertices@rel32@lo+4
	s_addc_u32 s9, s9, d_Vertices@rel32@hi+12
	s_add_u32 s12, s6, s8
	s_addc_u32 s13, s7, s9
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s0, s11, v4
	s_load_b32 s10, s[12:13], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, vcc_lo, s0
	s_xor_b32 s12, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s12
	s_cbranch_execz .LBB1_6
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	s_lshl_b64 s[12:13], s[2:3], 3
	v_subrev_f32_e32 v5, s10, v4
	s_add_u32 s8, s12, s8
	s_addc_u32 s9, s13, s9
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, d_Vertices@rel32@lo
	s_addc_u32 s13, s13, d_Vertices@rel32@hi+8
	s_add_u32 s12, s6, s12
	s_addc_u32 s13, s7, s13
	s_clause 0x1
	s_load_b32 s2, s[8:9], 0x0
	s_load_b32 s8, s[12:13], 0x0
	v_sub_f32_e64 v7, s11, s10
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e64 v6, s2, s8
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v5, v6
	v_div_scale_f32 v6, null, v7, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v6, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	v_div_scale_f32 v9, vcc_lo, v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v9, v8
	v_fma_f32 v11, -v6, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v8
	v_fma_f32 v6, -v6, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v8, v10
	v_div_fixup_f32 v5, v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, s8, v5
	v_cmpx_lt_f32_e32 v3, v5
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s1, 1
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmpk_eq_i32 s6, 0x12c4
	s_cbranch_scc1 .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s11, s10
	s_mov_b32 s2, s1
	s_mov_b32 s1, s0
	s_branch .LBB1_2
.LBB1_8:
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB1_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi, .Lfunc_end1-_Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 540
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi ; -- Begin function _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.globl	_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
	.p2align	8
	.type	_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi,@function
_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi: ; @_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
; %bb.0:
	s_load_b32 s2, s[0:1], 0x10
	v_lshl_add_u32 v0, s15, 8, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB2_9
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_Vertices@rel32@lo+4800
	s_addc_u32 s1, s1, d_Vertices@rel32@hi+4808
	v_mov_b32_e32 v4, 0
	s_load_b32 s11, s[0:1], 0x0
	s_mov_b32 s3, 0
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	s_movk_i32 s2, 0x257
	s_mov_b32 s1, s3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b64 s[6:7], 4
	global_load_b64 v[2:3], v[2:3], off
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, d_Vertices@rel32@lo+4
	s_addc_u32 s9, s9, d_Vertices@rel32@hi+12
	s_add_u32 s12, s6, s8
	s_addc_u32 s13, s7, s9
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f32_e64 s0, s11, v3
	s_load_b32 s10, s[12:13], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, vcc_lo, s0
	s_xor_b32 s12, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s12
	s_cbranch_execz .LBB2_6
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	s_lshl_b64 s[12:13], s[2:3], 3
	v_subrev_f32_e32 v5, s10, v3
	s_add_u32 s8, s12, s8
	s_addc_u32 s9, s13, s9
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, d_Vertices@rel32@lo
	s_addc_u32 s13, s13, d_Vertices@rel32@hi+8
	s_add_u32 s12, s6, s12
	s_addc_u32 s13, s7, s13
	s_clause 0x1
	s_load_b32 s2, s[8:9], 0x0
	s_load_b32 s8, s[12:13], 0x0
	v_sub_f32_e64 v7, s11, s10
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e64 v6, s2, s8
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v5, v6
	v_div_scale_f32 v6, null, v7, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v6, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	v_div_scale_f32 v9, vcc_lo, v5, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v9, v8
	v_fma_f32 v11, -v6, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v8
	v_fma_f32 v6, -v6, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v8, v10
	v_div_fixup_f32 v5, v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, s8, v5
	v_cmpx_lt_f32_e32 v2, v5
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_6:                                ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s0, s1, 1
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmpk_lg_i32 s6, 0x12c4
	s_cbranch_scc0 .LBB2_8
; %bb.7:                                ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s11, s10
	s_mov_b32 s2, s1
	s_mov_b32 s1, s0
	s_branch .LBB2_2
.LBB2_8:
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB2_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi, .Lfunc_end2-_Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 516
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_Vertices              ; @d_Vertices
	.type	d_Vertices,@object
	.section	.bss,"aw",@nobits
	.globl	d_Vertices
	.p2align	4, 0x0
d_Vertices:
	.zero	4800
	.size	d_Vertices, 4800

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_Vertices
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9cn_PnPolyPiP15HIP_vector_typeIfLj2EEi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15cn_PnPoly_naivePiP15HIP_vector_typeIfLj2EEi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13pnpoly_cn_gpuPiP15HIP_vector_typeIfLj2EEi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
