#include<iostream>
#include<cstdlib>
#include<fstream>
#include<string>
#include<sys/time.h>

typedef unsigned long long int UINT;
const int MAXTHREADSPERBLOCK = 512;

using namespace std;


__global__ void GPU(const int tilesize, const int paddsize, const int maxThreads, 
			int *dev_table, const int rowsize, const int maxlevel, int tileX, int lenY, int *dev_arr1, int *dev_arr2){
	//This code has to ensure n2 size is the multiple of 128. And n2 is no smaller than n1, where n2 is row array size, n1 is colum array size
	//on K40, tile size is max to 48K, which is 128*96; on pascal and volta, tile size is max to 64K which is 128*128
	//For running on K40, we reserve the shared memory space for a 64*64 tile. Because of the dependency, the actual shared memory size is 96 * 96. 96 is picked for ensuring memory coalscing.
//	__shared__ int table[9216];

	int thread = threadIdx.x;
	int curjobs = 0;
	int curlevel = 1;
	int startIdx, startx, starty;
	int tableX = tileX + paddsize;
	int x,y;
	
	while (curlevel <= maxlevel){
		if (curlevel <= lenY){
			curjobs++;
//			printf("curlevel: %d, lenY: %d, curjobs: %d, thread: %d\n", curlevel, lenY, curjobs, thread);
		}

		startx = paddsize + curlevel - 1;
		starty = paddsize;

		if (curlevel > tileX){
			curjobs--;	
			startx = tableX -1;
			starty = paddsize + curlevel - tileX;

//			printf("curlevel: %d, curjobs: %d, thread: %d\n", curlevel,  curjobs, thread);
		}
	
		if (thread < curjobs){
			startx -= thread;
			starty += thread;
			startIdx = startx + starty * rowsize;
			dev_table[startIdx] = max(dev_table[startIdx - 1], dev_table[startIdx - rowsize]);
			x = startx - paddsize;
			y = starty - paddsize;
			if (dev_arr1[x] == dev_arr2[y])
				dev_table[startIdx] = dev_table[startIdx - rowsize - 1] + 1;				
		}

		curlevel++;
		
	
		__syncthreads();	
	}
	
}

void checkGPUError(cudaError err){
	if (cudaSuccess != err){
		printf("CUDA error in file %s, in line %i: %s\n", __FILE__, __LINE__, cudaGetErrorString(err));
		exit(EXIT_FAILURE);
	}
}

int LCS(int n1, int n2, int *arr1, int *arr2){
	int lcslength;
	int paddsize = 1;
	int tileX = 256;
	int tileY = 256;
	int rowsize = paddsize + n2;
	int colsize = paddsize + n1;

	int *dev_table, *dev_arr1, *dev_arr2;

	int *table;

	table = new int[colsize * rowsize];

	size_t freeMem, totalMem;

	cudaMemGetInfo(&freeMem, &totalMem);
	int tablesize = colsize * rowsize;
	cout << "current GPU memory info FREE: " << freeMem << " Bytes, Total: " << totalMem << " Bytes.";
	cout << "colsize: " << colsize << ", rowsize: " << rowsize << ", allocates: " << tablesize * sizeof(int)<< " Bytes." << endl;
	cudaError err = cudaMalloc(&dev_table, tablesize * sizeof(int));
	checkGPUError(err);
	
	cudaMalloc(&dev_arr1, n1*sizeof(int));
	cudaMalloc(&dev_arr2, n2*sizeof(int));

	cudaMemset(dev_table, 0, tablesize * sizeof(int));
	cudaMemcpy(dev_arr1, arr1, n1*sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_arr2, arr2, n2*sizeof(int), cudaMemcpyHostToDevice);

	int maxthreads;
	int maxlevel;
	int threadPerBlock = tileY + paddsize;
	int blockPerGrid = (threadPerBlock + MAXTHREADSPERBLOCK -1)/MAXTHREADSPERBLOCK;
	int numStream = 32;

	cudaDeviceSetCacheConfig(cudaFuncCachePreferShared);

	int xseg = (n1+tileX-1) / tileX;
	int yseg = (n2+tileY-1) / tileY;
	int maxSegThreads = min(xseg, yseg);		//max number of segs at either of the seg levels.
	int maxSegLevel = xseg + yseg - 1;
	int curSegLevel = 1;
//	int curSegJobs = 1;
	int startSegX, startSegY;	

	cudaStream_t stream[numStream];
	for (int s=0; s<numStream; s++)
		cudaStreamCreate(&stream[s]);

	while(curSegLevel <= maxSegLevel){
		int segIdx = 0;
		if (curSegLevel <= xseg){
			//curSegJobs = curSegLevel;
			startSegX = curSegLevel - 1;
			startSegY = 0;
		}	
		else{
			//startSegIdx = xseg - 1 + xseg * (curSegLevel - xseg);
			//curSegJobs = 2 * xseg - curSegLevel;
			startSegX = xseg - 1;
			startSegY = curSegLevel - xseg;
		}
		
//		cout << "curSegLevel: " << curSegLevel << ", maxSegLevel: " << maxSegLevel << endl;	
		
		while ( startSegX >= 0 && startSegY <= yseg - 1){
			//suppose n2 is the row size and the longer array
			//int i = paddsize + startSegX * tileX;
			//int j = paddsize + startSegY * tileY;
			int i = startSegX * tileX;
			int j = startSegY * tileY;
			int startSegAdd = j * rowsize + i;
			int s = segIdx % numStream;
			//resY is used to determine the rest size of Y. This is used to check if the rest size of Y is smaller than tileY.
			int resY = n1 - startSegY * tileY;
			int lenY = min(resY, tileY);
			maxlevel = tileX + lenY - 1;
			maxthreads = min(tileX, lenY);
			int tilesize = (tileX+paddsize) * (lenY+paddsize);

			GPU<<<blockPerGrid, threadPerBlock, 0, stream[s]>>>(tilesize, paddsize, maxthreads, &dev_table[startSegAdd], rowsize, 
										maxlevel, tileX, lenY, &dev_arr1[i], &dev_arr2[j]);
		
//			cout << "startSegX: " << startSegX << ", startSegY: " << startSegY << ", segIdx: " << segIdx << endl;
			startSegX--;
			startSegY++;
			segIdx++;
		}
		//this synchronization is might removable
		cudaDeviceSynchronize();

		curSegLevel++;
	}
	
	cudaMemcpy(&lcslength, &dev_table[tablesize-1], sizeof(int), cudaMemcpyDeviceToHost);
	cudaMemcpy(table, dev_table, (n1+paddsize)*rowsize*sizeof(int), cudaMemcpyDeviceToHost);
/*
	//display table
	cout << "full table: " << endl;
	for (int i=0; i<n1+paddsize; i++){
		for (int j=0; j<n2+paddsize; j++){
			cout << table[i * rowsize + j] << " ";
		}
		cout << endl;
	}
*/	

	for (int s=0; s<numStream; s++)
		cudaStreamDestroy(stream[s]);
	
	cudaFree(dev_arr1);
	cudaFree(dev_arr2);
	cudaFree(dev_table);

	delete[] table;

	return lcslength;
}


	.file	"tmpxft_003716aa_00000000-6_GPU_TILE_NOSHARE.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3770:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3770:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/zzzhe1990/GPUMemEfficient/master/LCS-SHFL/GPU_TILE_NOSHARE.cu"
.LC1:
	.string	"CUDA error in file %s, in line %i: %s\n"
	.text
	.globl	_Z13checkGPUError9cudaError
	.type	_Z13checkGPUError9cudaError, @function
_Z13checkGPUError9cudaError:
.LFB3766:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movl	$65, %ecx
	leaq	.LC0(%rip), %rdx
	movq	%rax, %r8
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3766:
	.size	_Z13checkGPUError9cudaError, .-_Z13checkGPUError9cudaError
	.globl	_Z33__device_stub__Z3GPUiiiPiiiiiS_S_iiiPiiiiiS_S_
	.type	_Z33__device_stub__Z3GPUiiiPiiiiiS_S_iiiPiiiiiS_S_, @function
_Z33__device_stub__Z3GPUiiiPiiiiiS_S_iiiPiiiiiS_S_:
.LFB3792:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	240(%rsp), %rax
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	248(%rsp), %rax
	movl	%edx, 36(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 32(%rsp)
	movl	%r9d, 20(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z3GPUiiiPiiiiiS_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3792:
	.size	_Z33__device_stub__Z3GPUiiiPiiiiiS_S_iiiPiiiiiS_S_, .-_Z33__device_stub__Z3GPUiiiPiiiiiS_S_iiiPiiiiiS_S_
	.globl	_Z3GPUiiiPiiiiiS_S_
	.type	_Z3GPUiiiPiiiiiS_S_, @function
_Z3GPUiiiPiiiiiS_S_:
.LFB3793:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z3GPUiiiPiiiiiS_S_iiiPiiiiiS_S_
	.cfi_endproc
.LFE3793:
	.size	_Z3GPUiiiPiiiiiS_S_, .-_Z3GPUiiiPiiiiiS_S_
	.section	.rodata.str1.1
.LC2:
	.string	"current GPU memory info FREE: "
.LC3:
	.string	" Bytes, Total: "
.LC4:
	.string	" Bytes."
.LC5:
	.string	"colsize: "
.LC6:
	.string	", rowsize: "
.LC7:
	.string	", allocates: "
	.text
	.globl	_Z3LCSiiPiS_
	.type	_Z3LCSiiPiS_, @function
_Z3LCSiiPiS_:
.LFB3767:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	movabsq	$2305843009213693950, %rcx
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	leal	1(%rdi), %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$392, %rsp
	.cfi_def_cfa_offset 448
	movq	%fs:40, %rax
	movq	%rax, 376(%rsp)
	xorl	%eax, %eax
	leal	1(%rsi), %eax
	movl	%eax, 20(%rsp)
	imull	%r12d, %eax
	cltq
	cmpq	%rax, %rcx
	jb	.L14
	salq	$2, %rax
	movl	%edi, %ebx
	movq	%rdx, %r15
	movl	%esi, %ebp
	movq	%rax, %rdi
	leaq	_ZSt4cout(%rip), %r13
	movq	%rax, 8(%rsp)
	call	_Znam@PLT
	leaq	88(%rsp), %rsi
	leaq	80(%rsp), %rdi
	movq	%rax, 24(%rsp)
	call	cudaMemGetInfo@PLT
	movq	%r13, %rdi
	leaq	.LC2(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	80(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	88(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r13, %rdi
	leaq	.LC5(%rip), %rsi
	movslq	%ebx, %r13
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	salq	$2, %r13
	movslq	%ebp, %r12
	movq	%rax, %rdi
	salq	$2, %r12
	call	_ZNSolsEi@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	20(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	8(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	8(%rsp), %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	call	_Z13checkGPUError9cudaError
	movq	%r13, %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%r12, %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	64(%rsp), %rdi
	movq	%r13, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	leaq	120(%rsp), %r13
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	movq	%r12, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	leaq	376(%rsp), %r14
	call	cudaMemcpy@PLT
	movl	$1, %edi
	call	cudaDeviceSetCacheConfig@PLT
	leal	255(%rbx), %eax
	movl	$256, %ecx
	cltd
	idivl	%ecx
	movl	%eax, %r12d
	leal	255(%rbp), %eax
	cltd
	idivl	%ecx
	movl	%eax, 32(%rsp)
	addl	%r12d, %eax
	movl	%eax, 36(%rsp)
	jmp	.L15
.L14:
	movq	376(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L31
	call	__cxa_throw_bad_array_new_length@PLT
.L15:
	movq	%r13, %rdi
	addq	$8, %r13
	call	cudaStreamCreate@PLT
	cmpq	%r14, %r13
	jne	.L15
	sall	$8, %ebp
	movl	$1, %r13d
	movl	%ebp, 40(%rsp)
.L17:
	cmpl	%r13d, 36(%rsp)
	jle	.L32
	cmpl	%r12d, %r13d
	jg	.L18
	leal	-1(%r13), %r15d
	xorl	%r14d, %r14d
	jmp	.L19
.L18:
	movl	%r13d, %r14d
	leal	-1(%r12), %r15d
	subl	%r12d, %r14d
.L19:
	movl	20(%rsp), %ebp
	movl	%r15d, 44(%rsp)
	imull	%r14d, %ebp
	addl	%r15d, %ebp
	sall	$8, %ebp
.L20:
	movl	44(%rsp), %eax
	subl	%r15d, %eax
	testl	%r15d, %r15d
	js	.L27
	movl	32(%rsp), %ecx
	cmpl	%ecx, %r14d
	jge	.L27
	andl	$31, %eax
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	120(%rsp,%rax,8), %r9
	movl	$1, 116(%rsp)
	movabsq	$4294967553, %rdx
	movabsq	$4294967297, %rdi
	movq	%rdx, 108(%rsp)
	movq	%rdi, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movl	%r14d, %eax
	movl	%ebx, %edx
	movl	$256, %ecx
	movq	56(%rsp), %rsi
	sall	$8, %eax
	subl	%eax, %edx
	cmpl	%ecx, %edx
	cmovg	%ecx, %edx
	movslq	%ebp, %rcx
	leaq	(%rsi,%rcx,4), %rcx
	movq	72(%rsp), %rsi
	leal	1(%rdx), %edi
	leal	255(%rdx), %r9d
	imull	$257, %edi, %edi
	leaq	(%rsi,%rax,4), %rax
	pushq	%rax
	.cfi_def_cfa_offset 456
	movl	%r15d, %eax
	movq	72(%rsp), %rsi
	sall	$8, %eax
	leaq	(%rsi,%rax,4), %rax
	movl	$1, %esi
	pushq	%rax
	.cfi_def_cfa_offset 464
	pushq	%rdx
	.cfi_def_cfa_offset 472
	pushq	$256
	.cfi_def_cfa_offset 480
	movl	52(%rsp), %r8d
	call	_Z33__device_stub__Z3GPUiiiPiiiiiS_S_iiiPiiiiiS_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 448
.L21:
	movl	40(%rsp), %eax
	decl	%r15d
	incl	%r14d
	addl	%eax, %ebp
	jmp	.L20
.L27:
	call	cudaDeviceSynchronize@PLT
	incl	%r13d
	jmp	.L17
.L32:
	movq	8(%rsp), %rbx
	movq	56(%rsp), %rax
	leaq	108(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	leaq	-4(%rax,%rbx), %rsi
	xorl	%ebx, %ebx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	24(%rsp), %rdi
	call	cudaMemcpy@PLT
.L25:
	movq	120(%rsp,%rbx,8), %rdi
	incq	%rbx
	call	cudaStreamDestroy@PLT
	cmpq	$32, %rbx
	jne	.L25
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	_ZdaPv@PLT
	movl	108(%rsp), %eax
	movq	376(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L26
.L31:
	call	__stack_chk_fail@PLT
.L26:
	addq	$392, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3767:
	.size	_Z3LCSiiPiS_, .-_Z3LCSiiPiS_
	.section	.rodata.str1.1
.LC8:
	.string	"_Z3GPUiiiPiiiiiS_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3795:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3GPUiiiPiiiiiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3795:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<iostream>
#include<cstdlib>
#include<fstream>
#include<string>
#include<sys/time.h>

typedef unsigned long long int UINT;
const int MAXTHREADSPERBLOCK = 512;

using namespace std;


__global__ void GPU(const int tilesize, const int paddsize, const int maxThreads, 
			int *dev_table, const int rowsize, const int maxlevel, int tileX, int lenY, int *dev_arr1, int *dev_arr2){
	//This code has to ensure n2 size is the multiple of 128. And n2 is no smaller than n1, where n2 is row array size, n1 is colum array size
	//on K40, tile size is max to 48K, which is 128*96; on pascal and volta, tile size is max to 64K which is 128*128
	//For running on K40, we reserve the shared memory space for a 64*64 tile. Because of the dependency, the actual shared memory size is 96 * 96. 96 is picked for ensuring memory coalscing.
//	__shared__ int table[9216];

	int thread = threadIdx.x;
	int curjobs = 0;
	int curlevel = 1;
	int startIdx, startx, starty;
	int tableX = tileX + paddsize;
	int x,y;
	
	while (curlevel <= maxlevel){
		if (curlevel <= lenY){
			curjobs++;
//			printf("curlevel: %d, lenY: %d, curjobs: %d, thread: %d\n", curlevel, lenY, curjobs, thread);
		}

		startx = paddsize + curlevel - 1;
		starty = paddsize;

		if (curlevel > tileX){
			curjobs--;	
			startx = tableX -1;
			starty = paddsize + curlevel - tileX;

//			printf("curlevel: %d, curjobs: %d, thread: %d\n", curlevel,  curjobs, thread);
		}
	
		if (thread < curjobs){
			startx -= thread;
			starty += thread;
			startIdx = startx + starty * rowsize;
			dev_table[startIdx] = max(dev_table[startIdx - 1], dev_table[startIdx - rowsize]);
			x = startx - paddsize;
			y = starty - paddsize;
			if (dev_arr1[x] == dev_arr2[y])
				dev_table[startIdx] = dev_table[startIdx - rowsize - 1] + 1;				
		}

		curlevel++;
		
	
		__syncthreads();	
	}
	
}

void checkGPUError(hipError_t err){
	if (hipSuccess != err){
		printf("CUDA error in file %s, in line %i: %s\n", __FILE__, __LINE__, hipGetErrorString(err));
		exit(EXIT_FAILURE);
	}
}

int LCS(int n1, int n2, int *arr1, int *arr2){
	int lcslength;
	int paddsize = 1;
	int tileX = 256;
	int tileY = 256;
	int rowsize = paddsize + n2;
	int colsize = paddsize + n1;

	int *dev_table, *dev_arr1, *dev_arr2;

	int *table;

	table = new int[colsize * rowsize];

	size_t freeMem, totalMem;

	hipMemGetInfo(&freeMem, &totalMem);
	int tablesize = colsize * rowsize;
	cout << "current GPU memory info FREE: " << freeMem << " Bytes, Total: " << totalMem << " Bytes.";
	cout << "colsize: " << colsize << ", rowsize: " << rowsize << ", allocates: " << tablesize * sizeof(int)<< " Bytes." << endl;
	hipError_t err = hipMalloc(&dev_table, tablesize * sizeof(int));
	checkGPUError(err);
	
	hipMalloc(&dev_arr1, n1*sizeof(int));
	hipMalloc(&dev_arr2, n2*sizeof(int));

	hipMemset(dev_table, 0, tablesize * sizeof(int));
	hipMemcpy(dev_arr1, arr1, n1*sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(dev_arr2, arr2, n2*sizeof(int), hipMemcpyHostToDevice);

	int maxthreads;
	int maxlevel;
	int threadPerBlock = tileY + paddsize;
	int blockPerGrid = (threadPerBlock + MAXTHREADSPERBLOCK -1)/MAXTHREADSPERBLOCK;
	int numStream = 32;

	hipDeviceSetCacheConfig(hipFuncCachePreferShared);

	int xseg = (n1+tileX-1) / tileX;
	int yseg = (n2+tileY-1) / tileY;
	int maxSegThreads = min(xseg, yseg);		//max number of segs at either of the seg levels.
	int maxSegLevel = xseg + yseg - 1;
	int curSegLevel = 1;
//	int curSegJobs = 1;
	int startSegX, startSegY;	

	hipStream_t stream[numStream];
	for (int s=0; s<numStream; s++)
		hipStreamCreate(&stream[s]);

	while(curSegLevel <= maxSegLevel){
		int segIdx = 0;
		if (curSegLevel <= xseg){
			//curSegJobs = curSegLevel;
			startSegX = curSegLevel - 1;
			startSegY = 0;
		}	
		else{
			//startSegIdx = xseg - 1 + xseg * (curSegLevel - xseg);
			//curSegJobs = 2 * xseg - curSegLevel;
			startSegX = xseg - 1;
			startSegY = curSegLevel - xseg;
		}
		
//		cout << "curSegLevel: " << curSegLevel << ", maxSegLevel: " << maxSegLevel << endl;	
		
		while ( startSegX >= 0 && startSegY <= yseg - 1){
			//suppose n2 is the row size and the longer array
			//int i = paddsize + startSegX * tileX;
			//int j = paddsize + startSegY * tileY;
			int i = startSegX * tileX;
			int j = startSegY * tileY;
			int startSegAdd = j * rowsize + i;
			int s = segIdx % numStream;
			//resY is used to determine the rest size of Y. This is used to check if the rest size of Y is smaller than tileY.
			int resY = n1 - startSegY * tileY;
			int lenY = min(resY, tileY);
			maxlevel = tileX + lenY - 1;
			maxthreads = min(tileX, lenY);
			int tilesize = (tileX+paddsize) * (lenY+paddsize);

			GPU<<<blockPerGrid, threadPerBlock, 0, stream[s]>>>(tilesize, paddsize, maxthreads, &dev_table[startSegAdd], rowsize, 
										maxlevel, tileX, lenY, &dev_arr1[i], &dev_arr2[j]);
		
//			cout << "startSegX: " << startSegX << ", startSegY: " << startSegY << ", segIdx: " << segIdx << endl;
			startSegX--;
			startSegY++;
			segIdx++;
		}
		//this synchronization is might removable
		hipDeviceSynchronize();

		curSegLevel++;
	}
	
	hipMemcpy(&lcslength, &dev_table[tablesize-1], sizeof(int), hipMemcpyDeviceToHost);
	hipMemcpy(table, dev_table, (n1+paddsize)*rowsize*sizeof(int), hipMemcpyDeviceToHost);
/*
	//display table
	cout << "full table: " << endl;
	for (int i=0; i<n1+paddsize; i++){
		for (int j=0; j<n2+paddsize; j++){
			cout << table[i * rowsize + j] << " ";
		}
		cout << endl;
	}
*/	

	for (int s=0; s<numStream; s++)
		hipStreamDestroy(stream[s]);
	
	hipFree(dev_arr1);
	hipFree(dev_arr2);
	hipFree(dev_table);

	delete[] table;

	return lcslength;
}


	.text
	.file	"GPU_TILE_NOSHARE.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z18__device_stub__GPUiiiPiiiiiS_S_ # -- Begin function _Z18__device_stub__GPUiiiPiiiiiS_S_
	.type	_Z18__device_stub__GPUiiiPiiiiiS_S_,@function
_Z18__device_stub__GPUiiiPiiiiiS_S_:    # @_Z18__device_stub__GPUiiiPiiiiiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3GPUiiiPiiiiiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__GPUiiiPiiiiiS_S_, .Lfunc_end0-_Z18__device_stub__GPUiiiPiiiiiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z13checkGPUError10hipError_t   # -- Begin function _Z13checkGPUError10hipError_t
	.type	_Z13checkGPUError10hipError_t,@function
_Z13checkGPUError10hipError_t:          # @_Z13checkGPUError10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB1_2
# %bb.1:
	retq
.LBB1_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	movl	$67, %edx
	movq	%rax, %rcx
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z13checkGPUError10hipError_t, .Lfunc_end1-_Z13checkGPUError10hipError_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z3LCSiiPiS_                    # -- Begin function _Z3LCSiiPiS_
	.type	_Z3LCSiiPiS_,@function
_Z3LCSiiPiS_:                           # @_Z3LCSiiPiS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$456, %rsp                      # imm = 0x1C8
	.cfi_def_cfa_offset 512
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
                                        # kill: def $esi killed $esi def $rsi
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
                                        # kill: def $edi killed $edi def $rdi
	leal	1(%rsi), %r15d
	leal	1(%rdi), %r13d
	movq	%rdi, %r12
	movq	%rdi, 40(%rsp)                  # 8-byte Spill
	movl	%r15d, %eax
	imull	%r13d, %eax
	cltq
	leaq	(,%rax,4), %rbp
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	testl	%eax, %eax
	movq	$-1, %rdi
	cmovnsq	%rbp, %rdi
	callq	_Znam
	movq	%rax, 136(%rsp)                 # 8-byte Spill
	leaq	184(%rsp), %rbx
	leaq	176(%rsp), %r14
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMemGetInfo
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$30, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rsi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.3, %esi
	movl	$15, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rsi
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertImEERSoT_
	movl	$.L.str.4, %esi
	movl	$7, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%r13d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$11, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	movl	%r15d, 12(%rsp)                 # 4-byte Spill
	movl	%r15d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.7, %esi
	movl	$13, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	movq	%rbp, %r13
	movq	%rbp, %rsi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.4, %esi
	movl	$7, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	leaq	24(%rsp), %r15
	movq	%r15, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	%eax, %edi
	callq	_Z13checkGPUError10hipError_t
	movslq	%r12d, %r14
	shlq	$2, %r14
	leaq	72(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	16(%rsp), %r12                  # 8-byte Reload
	movslq	%r12d, %rbp
	leaq	(,%rbp,4), %rbx
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	movq	%r13, 128(%rsp)                 # 8-byte Spill
	movq	%r13, %rdx
	callq	hipMemset
	leaq	72(%rsp), %rax
	movq	(%rax), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %rax
	movq	(%rax), %rdi
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$1, %edi
	callq	hipDeviceSetCacheConfig
	movq	%rsp, 112(%rsp)                 # 8-byte Spill
	movl	$255, %eax
	movq	40(%rsp), %rcx                  # 8-byte Reload
	leal	(%rcx,%rax), %ebx
	addl	%r12d, %eax
	addl	$510, %ebp                      # imm = 0x1FE
	testl	%eax, %eax
	cmovnsl	%eax, %ebp
	sarl	$8, %ebp
	movq	%rbp, 32(%rsp)                  # 8-byte Spill
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	leaq	(%rsp,%r15), %rdi
	addq	$192, %rdi
	callq	hipStreamCreate
	addq	$8, %r15
	cmpq	$256, %r15                      # imm = 0x100
	jne	.LBB2_1
# %bb.2:                                # %.preheader
	leal	255(%rbx), %ecx
	testl	%ebx, %ebx
	cmovnsl	%ebx, %ecx
	sarl	$8, %ecx
	movq	32(%rsp), %rax                  # 8-byte Reload
	movq	%rcx, 88(%rsp)                  # 8-byte Spill
	addl	%ecx, %eax
	cmpl	$2, %eax
	jl	.LBB2_12
# %bb.3:                                # %.lr.ph118.preheader
	movabsq	$4294967297, %rcx               # imm = 0x100000001
	movslq	88(%rsp), %rdx                  # 4-byte Folded Reload
	movslq	32(%rsp), %rsi                  # 4-byte Folded Reload
	movq	%rsi, 168(%rsp)                 # 8-byte Spill
	movl	%eax, %eax
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	movl	%edx, %esi
	shll	$8, %esi
	movq	16(%rsp), %rax                  # 8-byte Reload
	shll	$8, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	40(%rsp), %rax                  # 8-byte Reload
	addl	%esi, %eax
	movl	%eax, 80(%rsp)                  # 4-byte Spill
	negl	%esi
	movq	%rsi, 152(%rsp)                 # 8-byte Spill
	movq	%rdx, 96(%rsp)                  # 8-byte Spill
                                        # kill: def $edx killed $edx killed $rdx def $rdx
	negl	%edx
	movq	%rdx, 144(%rsp)                 # 8-byte Spill
	movl	$1, %edi
	leaq	256(%rcx), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
.LBB2_4:                                # %.lr.ph118
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_7 Depth 2
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movl	%esi, %edx
	subl	%edi, %edx
	movl	%edi, %ecx
	cmovgl	88(%rsp), %ecx                  # 4-byte Folded Reload
	negl	%edx
	cmpq	%rsi, %rdi
	movq	%rsi, %rax
	cmovlq	%rdi, %rax
	movq	%rdi, 104(%rsp)                 # 8-byte Spill
	cmpl	%esi, %edi
	movl	$0, %esi
	cmovlel	%esi, %edx
	cmpl	$0, 40(%rsp)                    # 4-byte Folded Reload
	jle	.LBB2_11
# %bb.5:                                # %.lr.ph118
                                        #   in Loop: Header=BB2_4 Depth=1
	cmpl	32(%rsp), %edx                  # 4-byte Folded Reload
	jge	.LBB2_11
# %bb.6:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB2_4 Depth=1
	movq	144(%rsp), %rdx                 # 8-byte Reload
	addl	%ecx, %edx
	shll	$8, %ecx
	movq	152(%rsp), %rsi                 # 8-byte Reload
	leal	(%rsi,%rcx), %r15d
	movl	12(%rsp), %esi                  # 4-byte Reload
                                        # kill: def $esi killed $esi def $rsi
	imull	%r15d, %esi
	shll	$8, %eax
	movl	80(%rsp), %r13d                 # 4-byte Reload
	subl	%ecx, %r13d
	movslq	%edx, %rcx
	incq	%rcx
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	movl	%eax, %r14d
	addl	$-256, %r14d
	leal	(%rax,%rsi), %r12d
	addl	$-256, %r12d
	movq	96(%rsp), %rbx                  # 8-byte Reload
	movq	104(%rsp), %rax                 # 8-byte Reload
	cmpq	%rbx, %rax
	cmovlq	%rax, %rbx
	xorl	%ebp, %ebp
.LBB2_7:                                # %.lr.ph
                                        #   Parent Loop BB2_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%ebp, %eax
	andl	$31, %eax
	movq	192(%rsp,%rax,8), %r9
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_9
# %bb.8:                                #   in Loop: Header=BB2_7 Depth=2
	movl	$256, %r11d                     # imm = 0x100
	cmpl	%r11d, %r13d
	movl	$256, %edx                      # imm = 0x100
	cmovll	%r13d, %edx
	movl	%edx, %eax
	shll	$8, %eax
	leal	(%rdx,%rax), %edi
	addl	$257, %edi                      # imm = 0x101
	leal	255(%rdx), %r9d
	movslq	%r12d, %rcx
	shlq	$2, %rcx
	addq	24(%rsp), %rcx
	movslq	%r14d, %rax
	shlq	$2, %rax
	addq	72(%rsp), %rax
	movslq	%r15d, %r10
	shlq	$2, %r10
	addq	64(%rsp), %r10
	movl	$1, %esi
	movl	12(%rsp), %r8d                  # 4-byte Reload
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rdx
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	callq	_Z18__device_stub__GPUiiiPiiiiiS_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB2_9:                                #   in Loop: Header=BB2_7 Depth=2
	cmpq	$2, %rbx
	jl	.LBB2_11
# %bb.10:                               #   in Loop: Header=BB2_7 Depth=2
	movq	56(%rsp), %rax                  # 8-byte Reload
	addq	%rbp, %rax
	addl	$256, %r15d                     # imm = 0x100
	addl	16(%rsp), %r12d                 # 4-byte Folded Reload
	movl	$-256, %ecx
	addl	%ecx, %r13d
	incq	%rbp
	addl	%ecx, %r14d
	decq	%rbx
	cmpq	168(%rsp), %rax                 # 8-byte Folded Reload
	jl	.LBB2_7
.LBB2_11:                               # %._crit_edge
                                        #   in Loop: Header=BB2_4 Depth=1
	callq	hipDeviceSynchronize
	movq	104(%rsp), %rdi                 # 8-byte Reload
	incq	%rdi
	cmpq	160(%rsp), %rdi                 # 8-byte Folded Reload
	jne	.LBB2_4
.LBB2_12:                               # %._crit_edge119
	movq	24(%rsp), %rax
	movq	120(%rsp), %rcx                 # 8-byte Reload
	leaq	(%rax,%rcx,4), %rsi
	addq	$-4, %rsi
	leaq	84(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rsi
	movq	136(%rsp), %r14                 # 8-byte Reload
	movq	%r14, %rdi
	movq	128(%rsp), %rdx                 # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
.LBB2_13:                               # =>This Inner Loop Header: Depth=1
	movq	192(%rsp,%rbx,8), %rdi
	callq	hipStreamDestroy
	incq	%rbx
	cmpq	$32, %rbx
	jne	.LBB2_13
# %bb.14:
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	_ZdaPv
	movl	84(%rsp), %eax
	movq	112(%rsp), %rsp                 # 8-byte Reload
	addq	$456, %rsp                      # imm = 0x1C8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z3LCSiiPiS_, .Lfunc_end2-_Z3LCSiiPiS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3GPUiiiPiiiiiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3GPUiiiPiiiiiS_S_,@object     # @_Z3GPUiiiPiiiiiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z3GPUiiiPiiiiiS_S_
	.p2align	3, 0x0
_Z3GPUiiiPiiiiiS_S_:
	.quad	_Z18__device_stub__GPUiiiPiiiiiS_S_
	.size	_Z3GPUiiiPiiiiiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error in file %s, in line %i: %s\n"
	.size	.L.str, 39

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/zzzhe1990/GPUMemEfficient/master/LCS-SHFL/GPU_TILE_NOSHARE.hip"
	.size	.L.str.1, 125

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"current GPU memory info FREE: "
	.size	.L.str.2, 31

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" Bytes, Total: "
	.size	.L.str.3, 16

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	" Bytes."
	.size	.L.str.4, 8

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"colsize: "
	.size	.L.str.5, 10

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	", rowsize: "
	.size	.L.str.6, 12

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	", allocates: "
	.size	.L.str.7, 14

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3GPUiiiPiiiiiS_S_"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__GPUiiiPiiiiiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3GPUiiiPiiiiiS_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3GPUiiiPiiiiiS_S_     ; -- Begin function _Z3GPUiiiPiiiiiS_S_
	.globl	_Z3GPUiiiPiiiiiS_S_
	.p2align	8
	.type	_Z3GPUiiiPiiiiiS_S_,@function
_Z3GPUiiiPiiiiiS_S_:                    ; @_Z3GPUiiiPiiiiiS_S_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_6
; %bb.1:                                ; %.lr.ph
	s_clause 0x2
	s_load_b32 s10, s[0:1], 0x4
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x28
	v_not_b32_e32 v5, v0
	s_mov_b32 s12, 0
	s_mov_b32 s15, 0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s11, s10, 1
	s_add_i32 s13, s6, s10
	s_sub_i32 s14, s11, s6
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s17, s12
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_le_i32 s12, s7
	s_cselect_b32 s16, -1, 0
	s_cmp_lg_u32 s16, 0
	s_mov_b32 s16, exec_lo
	s_addc_u32 s15, s15, 0
	s_cmp_gt_i32 s12, s6
	s_cselect_b32 s18, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lg_u32 s18, 0
	s_subb_u32 s15, s15, 0
	v_cmpx_gt_i32_e64 s15, v0
	s_cbranch_execz .LBB0_5
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s19, s11, s17
	s_and_b32 s20, s18, exec_lo
	s_cselect_b32 s19, s13, s19
	s_add_i32 s17, s14, s17
	s_and_b32 s18, s18, exec_lo
	s_cselect_b32 s17, s17, s10
	v_add_nc_u32_e32 v6, s19, v5
	v_add_nc_u32_e32 v7, s17, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, v7, s4, v[6:7]
	v_subrev_nc_u32_e32 v6, s10, v6
	v_subrev_nc_u32_e32 v8, s10, v7
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v3, s4, v1
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v6
	s_clause 0x1
	global_load_b32 v10, v[1:2], off offset:-4
	global_load_b32 v11, v[3:4], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	s_waitcnt vmcnt(0)
	v_max_i32_e32 v10, v10, v11
	global_store_b32 v[1:2], v10, off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[8:9], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v6, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v3, v[3:4], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 1, v3
	global_store_b32 v[1:2], v3, off
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_cmp_lg_u32 s5, s12
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_2
.LBB0_6:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3GPUiiiPiiiiiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3GPUiiiPiiiiiS_S_, .Lfunc_end0-_Z3GPUiiiPiiiiiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 440
; NumSgprs: 23
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3GPUiiiPiiiiiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z3GPUiiiPiiiiiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
