#include <iostream>
#include <math.h>
#include <cstdio>
#include <cstdint>
#include <cuda_profiler_api.h>

#define MIN(X,Y) ((X) < (Y) ? (X) : (Y))

#define ull unsigned long long

__global__
void mandelbrot(ull x, ull y, int steps, uint8_t *res)
{
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    ull size = y * x/8;
    for (ull i = index; i < size; i += stride) {
        for (int bytepos = 0; bytepos < 8; bytepos++) {
            float r0 = 3.0f * ((i*8+bytepos) % x) / x - 2.0f;
            float c0 = 2.0f * ((i*8+bytepos) / x) / y - 1.0f;
            float r = r0, c = c0;
            for (int step = 0; step < steps && r < 2 && r > -3 && c < 2 && c > -2; step++) {
                float r2 = r * r - c * c + r0;
                float c2 = 2 * r * c + c0;
                r = r2;
                c = c2;
            }
            if (r > 2 || r < -3 || c > 2 || c < -2) {
                res[i] |= 0x80 >> bytepos;
            }
        }
    }
}

int main(int argc, char **args)
{
    if (argc != 4) {
        std::cerr << "Bad params" << std::endl;
        return 1;
    }
    cudaError_t error;
    int SCALE = atoi(args[1]);
    int STEPS = atoi(args[2]);
    char *OUT = args[3];
    ull X = 3 * SCALE, Y = 2*SCALE;
    if (X % 8 != 0) {
        std::cerr << "Scale has to be divisible by 8\n";
        return 1;
    }
    std::cerr << "Scale: " << SCALE << " (X = " << X << ", Y = " << Y << ")\nSteps: " << STEPS << "\nOutput file: " << OUT << std::endl;

    uint8_t *res;
    error = cudaMalloc(&res, X*Y*sizeof(uint8_t) / 8);
    if (!res || error == cudaErrorMemoryAllocation) {
        std::cerr << "Unable to allocate " << X*Y*sizeof(uint8_t)/8 << " bytes of GPU memory" << std::endl;
        return 1;
    }
    
    uint8_t *dataHost = (uint8_t *)malloc(X * Y * sizeof(uint8_t)/8);
    if (!dataHost) {
        std::cerr << "Not enough RAM" << std::endl;
        return 1;
    }

    FILE *output = fopen(OUT, "wb");

    std::cerr << "Writing" << sizeof(uint8_t) * X * Y /8 << " bytes "<< std::endl;
    cudaMemset(res, 0x0, X * Y * sizeof(uint8_t)/8);
    int blockSize = 256;
    int numBlocks = (X*Y + blockSize - 1) / blockSize;
    mandelbrot<<<numBlocks, blockSize>>>(X, Y, STEPS, res);
    cudaDeviceSynchronize();
    cudaMemcpy(dataHost, res, X * Y * sizeof(uint8_t)/8, cudaMemcpyDeviceToHost);
    fwrite(dataHost, sizeof(uint8_t), X*Y/8, output);
    
    
    cudaFree(res);
    std::cerr << "Closing" << std::endl;
    std::cout << "convert -size " << X << "x" << Y << " -depth 1 -define png:compression-strategy=3 gray:" << OUT << " res.png" << std::endl;
    fclose(output);
    cudaProfilerStop(); 
    return 0;
}

	.file	"tmpxft_0037a298_00000000-6_Mandelbrot.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4294:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4294:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z33__device_stub__Z10mandelbrotyyiPhyyiPh
	.type	_Z33__device_stub__Z10mandelbrotyyiPhyyiPh, @function
_Z33__device_stub__Z10mandelbrotyyiPhyyiPh:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10mandelbrotyyiPh(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L3:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z33__device_stub__Z10mandelbrotyyiPhyyiPh, .-_Z33__device_stub__Z10mandelbrotyyiPhyyiPh
	.globl	_Z10mandelbrotyyiPh
	.type	_Z10mandelbrotyyiPh, @function
_Z10mandelbrotyyiPh:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z10mandelbrotyyiPhyyiPh
	.cfi_endproc
.LFE3661:
	.size	_Z10mandelbrotyyiPh, .-_Z10mandelbrotyyiPh
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Bad params"
.LC1:
	.string	"Scale has to be divisible by 8\n"
.LC2:
	.string	"Scale: "
.LC3:
	.string	" (X = "
.LC4:
	.string	", Y = "
.LC5:
	.string	")\nSteps: "
.LC6:
	.string	"\nOutput file: "
.LC7:
	.string	"Unable to allocate "
.LC8:
	.string	" bytes of GPU memory"
.LC9:
	.string	"Not enough RAM"
.LC10:
	.string	"wb"
.LC11:
	.string	"Writing"
.LC12:
	.string	" bytes "
.LC13:
	.string	"Closing"
.LC14:
	.string	"convert -size "
.LC15:
	.string	"x"
.LC16:
	.string	" -depth 1 -define png:compression-strategy=3 gray:"
.LC17:
	.string	" res.png"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	cmpl	$4, %edi
	je	.L10
	leaq	.LC0(%rip), %rsi
	jmp	.L22
.L10:
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, %r12d
	call	atoi@PLT
	movl	%eax, %r14d
	movq	24(%rbx), %rax
	leal	(%r12,%r12,2), %ebx
	movl	%ebx, %r15d
	movq	%rax, 16(%rsp)
	andl	$7, %r15d
	je	.L12
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L11:
	movl	$1, %r15d
	jmp	.L9
.L12:
	leaq	.LC2(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	movslq	%ebx, %rbx
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	leal	(%r12,%r12), %ebp
	movq	%rbx, %r12
	movq	%rax, %rdi
	movslq	%ebp, %rbp
	call	_ZNSolsEi@PLT
	imulq	%rbp, %r12
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbx, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIyEERSoT_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIyEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	16(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%r12, %rax
	leaq	40(%rsp), %rdi
	shrq	$3, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	cmpq	$0, 40(%rsp)
	je	.L19
	cmpl	$2, %eax
	jne	.L14
.L19:
	leaq	.LC7(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	8(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIyEERSoT_@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
.L21:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	jmp	.L11
.L14:
	movq	8(%rsp), %rdi
	call	malloc@PLT
	movq	%rax, %r13
	testq	%rax, %rax
	jne	.L16
	leaq	.LC9(%rip), %rsi
.L22:
	leaq	_ZSt4cerr(%rip), %rdi
	jmp	.L21
.L16:
	movq	16(%rsp), %rdi
	leaq	.LC10(%rip), %rsi
	addq	$255, %r12
	shrq	$8, %r12
	call	fopen@PLT
	leaq	.LC11(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	movq	%rax, 24(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	8(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIyEERSoT_@PLT
	leaq	.LC12(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	8(%rsp), %rdx
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movl	%r12d, 48(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$16777217, %edx
	movl	$1, %ecx
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	salq	$8, %rdx
	movl	56(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	40(%rsp), %rcx
	movl	%r14d, %edx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	call	_Z33__device_stub__Z10mandelbrotyyiPhyyiPh
.L17:
	call	cudaDeviceSynchronize@PLT
	movq	8(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rcx
	movq	8(%rsp), %rdx
	movq	%r13, %rdi
	movl	$1, %esi
	call	fwrite@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC13(%rip), %rsi
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC14(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbx, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIyEERSoT_@PLT
	leaq	.LC15(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIyEERSoT_@PLT
	leaq	.LC16(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	16(%rsp), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC17(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	24(%rsp), %rdi
	call	fclose@PLT
	call	cudaProfilerStop@PLT
.L9:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	movl	%r15d, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC18:
	.string	"_Z10mandelbrotyyiPh"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10mandelbrotyyiPh(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <cstdio>
#include <cstdint>
#include <hip/hip_runtime_api.h>

#define MIN(X,Y) ((X) < (Y) ? (X) : (Y))

#define ull unsigned long long

__global__
void mandelbrot(ull x, ull y, int steps, uint8_t *res)
{
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    ull size = y * x/8;
    for (ull i = index; i < size; i += stride) {
        for (int bytepos = 0; bytepos < 8; bytepos++) {
            float r0 = 3.0f * ((i*8+bytepos) % x) / x - 2.0f;
            float c0 = 2.0f * ((i*8+bytepos) / x) / y - 1.0f;
            float r = r0, c = c0;
            for (int step = 0; step < steps && r < 2 && r > -3 && c < 2 && c > -2; step++) {
                float r2 = r * r - c * c + r0;
                float c2 = 2 * r * c + c0;
                r = r2;
                c = c2;
            }
            if (r > 2 || r < -3 || c > 2 || c < -2) {
                res[i] |= 0x80 >> bytepos;
            }
        }
    }
}

int main(int argc, char **args)
{
    if (argc != 4) {
        std::cerr << "Bad params" << std::endl;
        return 1;
    }
    hipError_t error;
    int SCALE = atoi(args[1]);
    int STEPS = atoi(args[2]);
    char *OUT = args[3];
    ull X = 3 * SCALE, Y = 2*SCALE;
    if (X % 8 != 0) {
        std::cerr << "Scale has to be divisible by 8\n";
        return 1;
    }
    std::cerr << "Scale: " << SCALE << " (X = " << X << ", Y = " << Y << ")\nSteps: " << STEPS << "\nOutput file: " << OUT << std::endl;

    uint8_t *res;
    error = hipMalloc(&res, X*Y*sizeof(uint8_t) / 8);
    if (!res || error == hipErrorOutOfMemory) {
        std::cerr << "Unable to allocate " << X*Y*sizeof(uint8_t)/8 << " bytes of GPU memory" << std::endl;
        return 1;
    }
    
    uint8_t *dataHost = (uint8_t *)malloc(X * Y * sizeof(uint8_t)/8);
    if (!dataHost) {
        std::cerr << "Not enough RAM" << std::endl;
        return 1;
    }

    FILE *output = fopen(OUT, "wb");

    std::cerr << "Writing" << sizeof(uint8_t) * X * Y /8 << " bytes "<< std::endl;
    hipMemset(res, 0x0, X * Y * sizeof(uint8_t)/8);
    int blockSize = 256;
    int numBlocks = (X*Y + blockSize - 1) / blockSize;
    mandelbrot<<<numBlocks, blockSize>>>(X, Y, STEPS, res);
    hipDeviceSynchronize();
    hipMemcpy(dataHost, res, X * Y * sizeof(uint8_t)/8, hipMemcpyDeviceToHost);
    fwrite(dataHost, sizeof(uint8_t), X*Y/8, output);
    
    
    hipFree(res);
    std::cerr << "Closing" << std::endl;
    std::cout << "convert -size " << X << "x" << Y << " -depth 1 -define png:compression-strategy=3 gray:" << OUT << " res.png" << std::endl;
    fclose(output);
    hipProfilerStop(); 
    return 0;
}

	.text
	.file	"Mandelbrot.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z25__device_stub__mandelbrotyyiPh # -- Begin function _Z25__device_stub__mandelbrotyyiPh
	.type	_Z25__device_stub__mandelbrotyyiPh,@function
_Z25__device_stub__mandelbrotyyiPh:     # @_Z25__device_stub__mandelbrotyyiPh
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10mandelbrotyyiPh, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__mandelbrotyyiPh, .Lfunc_end0-_Z25__device_stub__mandelbrotyyiPh
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$4, %edi
	jne	.LBB1_3
# %bb.1:
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r12d
	movq	16(%rbx), %rdi
	callq	atoi
	movl	%eax, %r15d
	leal	(%r12,%r12,2), %eax
	movslq	%eax, %rbp
	testb	$7, %bpl
	je	.LBB1_8
# %bb.2:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
	movl	$31, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_6
.LBB1_3:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	movl	$10, %edx
.LBB1_4:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
.LBB1_5:
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB1_6:
	movl	$1, %eax
.LBB1_7:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_8:
	.cfi_def_cfa_offset 96
	movq	24(%rbx), %rbx
	movl	%r12d, %eax
	addl	%r12d, %eax
	movslq	%eax, %r14
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.2, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movl	$.L.str.3, %esi
	movl	$6, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rdi
	movq	%rbp, %rsi
	callq	_ZNSo9_M_insertIyEERSoT_
	movq	%rax, %r12
	movl	$.L.str.4, %esi
	movl	$6, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	_ZNSo9_M_insertIyEERSoT_
	movq	%rax, %r12
	movl	$.L.str.5, %esi
	movl	$9, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movl	$.L.str.6, %esi
	movl	$14, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	testq	%rbx, %rbx
	movl	%r15d, 20(%rsp)                 # 4-byte Spill
	je	.LBB1_10
# %bb.9:
	movq	%rbx, %rdi
	callq	strlen
	movq	%r12, %rdi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_11
.LBB1_10:
	movq	(%r12), %rax
	movq	-24(%rax), %rax
	movq	%r12, %rdi
	addq	%rax, %rdi
	movl	32(%r12,%rax), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_11:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	(%r12), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rbp, %r15
	imulq	%r14, %r15
	movq	%r15, %r13
	shrq	$3, %r13
	leaq	8(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	cmpl	$2, %eax
	je	.LBB1_18
# %bb.12:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	cmpq	$0, 8(%rsp)
	je	.LBB1_18
# %bb.13:
	movq	%r13, %rdi
	callq	malloc
	testq	%rax, %rax
	je	.LBB1_19
# %bb.14:
	movq	%rax, %r12
	movq	%r14, 24(%rsp)                  # 8-byte Spill
	movl	$.L.str.10, %esi
	movq	%rbx, %rdi
	callq	fopen
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.11, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movq	%r13, %rsi
	callq	_ZNSo9_M_insertIyEERSoT_
	movq	%rax, %r14
	movl	$.L.str.12, %esi
	movl	$7, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	movq	%r13, %rdx
	callq	hipMemset
	addq	$255, %r15
	shrq	$8, %r15
	movl	%r15d, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_16
# %bb.15:
	movq	8(%rsp), %rcx
	movq	%rbp, %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movl	20(%rsp), %edx                  # 4-byte Reload
	callq	_Z25__device_stub__mandelbrotyyiPh
.LBB1_16:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movq	%r12, %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$1, %esi
	movq	%r12, %rdi
	movq	%r13, %rdx
	movq	32(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rcx
	callq	fwrite
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.13, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cerr(%rip), %rax
	movq	-24(%rax), %rdi
	movl	$_ZSt4cerr, %eax
	addq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cerr, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.14, %esi
	movl	$14, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movq	%rbp, %rsi
	callq	_ZNSo9_M_insertIyEERSoT_
	movq	%rax, %r14
	movl	$.L.str.15, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	callq	_ZNSo9_M_insertIyEERSoT_
	movq	%rax, %r14
	movl	$.L.str.16, %esi
	movl	$50, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	testq	%rbx, %rbx
	je	.LBB1_20
# %bb.17:
	movq	%rbx, %rdi
	callq	strlen
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_21
.LBB1_18:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.7, %esi
	movl	$19, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cerr, %edi
	movq	%r13, %rsi
	callq	_ZNSo9_M_insertIyEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.8, %esi
	movl	$20, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	jmp	.LBB1_5
.LBB1_19:
	movl	$_ZSt4cerr, %ebx
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.9, %esi
	movl	$14, %edx
	jmp	.LBB1_4
.LBB1_20:
	movq	(%r14), %rax
	movq	-24(%rax), %rax
	movq	%r14, %rdi
	addq	%rax, %rdi
	movl	32(%r14,%rax), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_21:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit53
	movl	$.L.str.17, %esi
	movl	$8, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%r15, %rdi
	callq	fclose
	callq	hipProfilerStop
	xorl	%eax, %eax
	jmp	.LBB1_7
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10mandelbrotyyiPh, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10mandelbrotyyiPh,@object     # @_Z10mandelbrotyyiPh
	.section	.rodata,"a",@progbits
	.globl	_Z10mandelbrotyyiPh
	.p2align	3, 0x0
_Z10mandelbrotyyiPh:
	.quad	_Z25__device_stub__mandelbrotyyiPh
	.size	_Z10mandelbrotyyiPh, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Bad params"
	.size	.L.str, 11

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Scale has to be divisible by 8\n"
	.size	.L.str.1, 32

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Scale: "
	.size	.L.str.2, 8

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" (X = "
	.size	.L.str.3, 7

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	", Y = "
	.size	.L.str.4, 7

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	")\nSteps: "
	.size	.L.str.5, 10

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\nOutput file: "
	.size	.L.str.6, 15

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Unable to allocate "
	.size	.L.str.7, 20

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	" bytes of GPU memory"
	.size	.L.str.8, 21

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Not enough RAM"
	.size	.L.str.9, 15

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"wb"
	.size	.L.str.10, 3

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Writing"
	.size	.L.str.11, 8

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	" bytes "
	.size	.L.str.12, 8

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Closing"
	.size	.L.str.13, 8

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"convert -size "
	.size	.L.str.14, 15

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"x"
	.size	.L.str.15, 2

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	" -depth 1 -define png:compression-strategy=3 gray:"
	.size	.L.str.16, 51

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	" res.png"
	.size	.L.str.17, 9

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10mandelbrotyyiPh"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__mandelbrotyyiPh
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10mandelbrotyyiPh
	.addrsig_sym _ZSt4cerr
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10mandelbrotyyiPh     ; -- Begin function _Z10mandelbrotyyiPh
	.globl	_Z10mandelbrotyyiPh
	.p2align	8
	.type	_Z10mandelbrotyyiPh,@function
_Z10mandelbrotyyiPh:                    ; @_Z10mandelbrotyyiPh
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s10, s0, 32
	s_addc_u32 s11, s1, 0
	s_mov_b32 s8, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s13, s2, 0xffff
	s_mul_i32 s2, s6, s5
	v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
	s_mul_hi_u32 s3, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s3, s2
	s_mul_i32 s3, s7, s4
	s_add_i32 s3, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s6, s4
	s_lshr_b64 s[2:3], s[2:3], 3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_gt_u64_e64 s[2:3], v[1:2]
	s_cbranch_execz .LBB0_11
; %bb.1:                                ; %.preheader.lr.ph
	v_cvt_f32_u32_e32 v0, s4
	v_cvt_f32_u32_e32 v3, s5
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x10
	s_load_b64 s[8:9], s[0:1], 0x18
	s_load_b32 s10, s[10:11], 0x0
	s_clz_i32_u32 s0, s5
	s_clz_i32_u32 s1, s7
	s_min_u32 s11, s0, 32
	v_fmamk_f32 v0, v3, 0x4f800000, v0
	s_min_u32 s14, s1, 32
	s_lshl_b64 s[0:1], s[4:5], s11
	s_lshl_b64 s[6:7], s[6:7], s14
	s_min_u32 s0, s0, 1
	v_rcp_f32_e32 v0, v0
	s_min_u32 s6, s6, 1
	s_or_b32 s0, s1, s0
	s_or_b32 s1, s7, s6
	v_cvt_f32_u32_e32 v4, s0
	v_cvt_f32_u32_e32 v5, s1
	s_sub_i32 s0, 32, s11
	s_sub_i32 s1, 32, s14
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s12, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	v_ldexp_f32 v7, v5, s1
	s_mul_i32 s6, s10, s13
	s_cselect_b32 s10, -1, 0
	s_ashr_i32 s11, s6, 31
	v_mul_f32_e32 v3, 0x2f800000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v3, v3
	v_fmamk_f32 v6, v3, 0xcf800000, v0
	v_ldexp_f32 v0, v4, s0
	v_cvt_u32_f32_e32 v9, v3
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_u32_f32_e32 v8, v6
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;       Child Loop BB0_5 Depth 3
	v_add_co_u32 v5, vcc_lo, s8, v1
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
	s_mov_b32 s13, 0
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_5 Depth 3
	s_sub_u32 s0, 0, s4
	s_subb_u32 s1, 0, s5
	v_mul_hi_u32 v10, s0, v8
	v_mul_lo_u32 v11, s0, v9
	v_mul_lo_u32 v12, s1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v10, v11
	v_mul_lo_u32 v11, s0, v8
	v_add_nc_u32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v8, v11
	v_mul_lo_u32 v13, v8, v10
	v_mul_hi_u32 v14, v8, v10
	v_mul_hi_u32 v15, v9, v11
	v_mul_lo_u32 v11, v9, v11
	v_mul_hi_u32 v16, v9, v10
	v_mul_lo_u32 v10, v9, v10
	v_add_co_u32 v12, vcc_lo, v12, v13
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v12, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, v13, v15, vcc_lo
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v11, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, v9, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v12, s0, v10
	v_mul_lo_u32 v14, s1, v10
	v_mul_lo_u32 v13, s0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v12, v13
	v_mul_lo_u32 v13, s0, v10
	v_add_nc_u32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v14, v10, v13
	v_mul_lo_u32 v15, v10, v12
	v_mul_hi_u32 v16, v10, v12
	v_mul_hi_u32 v17, v11, v13
	v_mul_lo_u32 v13, v11, v13
	v_mul_hi_u32 v18, v11, v12
	v_mul_lo_u32 v12, v11, v12
	v_add_co_u32 v14, vcc_lo, v14, v15
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v14, v13
	v_add_co_ci_u32_e32 v13, vcc_lo, v15, v17, vcc_lo
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v13, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v16, vcc_lo, v3, s13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s0, v10, v12
	v_add_co_ci_u32_e64 v17, s0, v11, v13, s0
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v19, v16, v14
	v_mad_u64_u32 v[10:11], null, v16, v17, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[12:13], null, v18, v14, 0
	v_mad_u64_u32 v[14:15], null, v18, v17, 0
	v_add_co_u32 v10, vcc_lo, v19, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v12, vcc_lo, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v11, vcc_lo
	v_mul_lo_u32 v14, s5, v12
	v_mad_u64_u32 v[10:11], null, s4, v12, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v15, s4, v13
	v_sub_co_u32 v10, vcc_lo, v16, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v11, v11, v15, v14
	v_sub_nc_u32_e32 v14, v18, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v14, s0, s5, v14, vcc_lo
	v_add_co_u32 v15, s0, v12, 2
	v_add_co_ci_u32_e64 v17, s0, 0, v13, s0
	v_sub_co_u32 v19, s0, v10, s4
	v_sub_co_ci_u32_e32 v11, vcc_lo, v18, v11, vcc_lo
	v_subrev_co_ci_u32_e64 v14, s0, 0, v14, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s4, v19
	v_cmp_eq_u32_e64 s0, s5, v11
	v_cndmask_b32_e64 v19, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s5, v14
	v_cndmask_b32_e64 v20, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v10
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v11
	v_cndmask_b32_e64 v21, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s5, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v21, v10, s0
	v_cndmask_b32_e32 v14, v20, v19, vcc_lo
	v_add_co_u32 v19, vcc_lo, v12, 1
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v13, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v11, v20, v17 :: v_dual_cndmask_b32 v14, v19, v15
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v14, v11, s4
	v_mul_lo_u32 v15, v10, s5
	v_mad_u64_u32 v[12:13], null, v10, s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v13, v13, v15, v14
	v_sub_co_u32 v12, vcc_lo, v16, v12
	v_clz_i32_u32_e32 v15, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e32 v13, vcc_lo, v18, v13, vcc_lo
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v14, v13
	v_lshlrev_b64 v[10:11], v15, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v14, 32, v14
	v_min_u32_e32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], v14, v[12:13]
	v_or_b32_e32 v10, v11, v10
	v_sub_nc_u32_e32 v11, 32, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_u32_e32 v12, 1, v12
	v_cvt_f32_u32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v12, v13, v12
	v_sub_nc_u32_e32 v13, 32, v15
	v_cvt_f32_u32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v10, v10, v13
	v_ldexp_f32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v10, v10, v10 :: v_dual_mul_f32 v11, 0x40400000, v11
	v_div_scale_f32 v13, null, v7, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v12, null, v0, v0, v11
	v_rcp_f32_e32 v15, v13
	v_div_scale_f32 v18, vcc_lo, v11, v0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v13, v15, 1.0
	v_fma_f32 v16, -v12, v14, 1.0
	v_dual_fmac_f32 v15, v17, v15 :: v_dual_fmac_f32 v14, v16, v14
	v_div_scale_f32 v16, s0, v10, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, v18, v14
	v_mul_f32_e32 v19, v16, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -v12, v17, v18
	v_fma_f32 v21, -v13, v19, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v20, v14
	v_fmac_f32_e32 v19, v21, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, -v12, v17, v18
	v_fma_f32 v13, -v13, v19, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v12, v12, v14, v17
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v13, v13, v15, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v11, v12, v0, v11
	v_div_fixup_f32 v10, v13, v7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, -2.0, v11 :: v_dual_add_f32 v10, -1.0, v10
	v_cmp_gt_f32_e32 vcc_lo, 2.0, v11
	v_cmp_lt_f32_e64 s0, 0xc0400000, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e64 s1, 2.0, v10
	s_and_b32 s14, s10, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, -2.0, v10
	s_and_b32 s0, s14, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v13, v11
	s_mov_b32 s16, 1
	s_mov_b32 s15, 0
.LBB0_5:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, v12, v12 :: v_dual_add_f32 v15, v13, v13
	s_cmp_ge_i32 s16, s12
	s_cselect_b32 s17, -1, 0
	v_fma_f32 v14, v13, v13, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v12, v15, v12, v10
	s_add_i32 s16, s16, 1
	v_add_f32_e32 v13, v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ngt_f32_e64 s1, 2.0, v12
	v_cmp_ngt_f32_e32 vcc_lo, 2.0, v13
	v_cmp_nlt_f32_e64 s0, 0xc0400000, v13
	s_or_b32 s17, s17, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, -2.0, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s17, s0
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, vcc_lo
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s15, s0, s15
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
.LBB0_7:                                ; %Flow85
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_max_f32 v12, v10, v10 :: v_dual_max_f32 v13, v11, v11
	v_cmp_gt_f32_e32 vcc_lo, 0xc0400000, v11
	v_cmp_gt_f32_e64 s0, -2.0, v10
	v_max_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s0, vcc_lo, s0
	v_cmp_lt_f32_e64 s1, 2.0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s0, s1
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_3 Depth=2
	global_load_u8 v10, v[5:6], off
	s_lshr_b32 s1, 0x80, s13
	s_waitcnt vmcnt(0)
	v_or_b32_e32 v10, s1, v10
	global_store_b8 v[5:6], v10, off
.LBB0_9:                                ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s13, s13, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s13, 8
	s_cbranch_scc0 .LBB0_3
; %bb.10:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v1, vcc_lo, v1, s6
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
	s_or_b32 s7, vcc_lo, s7
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_2
.LBB0_11:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10mandelbrotyyiPh
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10mandelbrotyyiPh, .Lfunc_end0-_Z10mandelbrotyyiPh
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1756
; NumSgprs: 20
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10mandelbrotyyiPh
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z10mandelbrotyyiPh.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
