#include "includes.h"
__global__ void normal_eqs_disparity_multicam_GPU( float *d_CD, float *d_disparity_compact, float4 *d_Zbuffer_normals_compact, int *d_ind_disparity_Zbuffer, const float *d_focal_length, const float *d_nodal_point_x, const float *d_nodal_point_y, const float *d_baseline, const int *d_n_cols, const int *d_n_values_disparity, const int *d_start_ind_disparity, const int *d_pixel_ind_offset) {
int n_val_accum = gridDim.x * blockDim.x; // _MAX_N_VAL_ACCUM may not be
// multiple of blocksize

int n_disparity = d_n_values_disparity[blockIdx.y];
int n_accum = (int)ceilf((float)n_disparity / (float)n_val_accum);
int start_ind = d_start_ind_disparity[blockIdx.y];

float f = d_focal_length[blockIdx.y];
float ox = d_nodal_point_x[blockIdx.y];
float oy = d_nodal_point_y[blockIdx.y];
float b = d_baseline[blockIdx.y];
int n_cols = d_n_cols[blockIdx.y];
int pixel_ind_offset = d_pixel_ind_offset[blockIdx.y];

// initialize accumulators

float A0 = 0.0f, A1 = 0.0f, A2 = 0.0f, A3 = 0.0f, A4 = 0.0f, A5 = 0.0f,
A6 = 0.0f, A7 = 0.0f, A8 = 0.0f, A9 = 0.0f, A10 = 0.0f, A11 = 0.0f,
A12 = 0.0f, A13 = 0.0f, A14 = 0.0f, A15 = 0.0f, A16 = 0.0f, A17 = 0.0f,
A18 = 0.0f, A19 = 0.0f, A20 = 0.0f, A21 = 0.0f, A22 = 0.0f, A23 = 0.0f,
A24 = 0.0f, A25 = 0.0f, A26 = 0.0f;

for (int in_ind = blockDim.x * blockIdx.x * n_accum + threadIdx.x;
in_ind < blockDim.x * (blockIdx.x + 1) * n_accum; in_ind += blockDim.x) {

if (in_ind < n_disparity) { // is this a valid sample?

// fetch disparity, Zbuffer and normal from global memory
float disp = d_disparity_compact[in_ind + start_ind];
float4 tmp = d_Zbuffer_normals_compact[in_ind + start_ind];
float Zbuffer = tmp.x;
float nx = tmp.y;
float ny = tmp.z;
float nz = tmp.w;

// compute coordinates
int pixel_ind =
d_ind_disparity_Zbuffer[in_ind + start_ind] - pixel_ind_offset;

float y = floorf(__fdividef((float)pixel_ind, n_cols));
float x = (float)pixel_ind - y * n_cols;

x = __fdividef((x - ox), f);
y = -__fdividef((y - oy), f);

// reconstruct 3D point from disparity

float Zd = -(f * b) / disp;
float Xd = x * Zd;
float Yd = y * Zd;

// reconstruct 3D point from model

float Zm = Zbuffer;
float Xm = x * Zm;
float Ym = y * Zm;

/************************/
/* evaluate constraints */
/************************/

// unique values A-matrix

A0 += nx * nx;
A1 += nx * ny;
A2 += nx * nz;
A3 += Ym * nx * nz - Zm * nx * ny;
A4 += Zm * (nx * nx) - Xm * nx * nz;
A5 += -Ym * (nx * nx) + Xm * nx * ny;

A6 += ny * ny;
A7 += ny * nz;
A8 += -Zm * (ny * ny) + Ym * ny * nz;
A9 += -Xm * ny * nz + Zm * nx * ny;
A10 += Xm * (ny * ny) - Ym * nx * ny;

A11 += nz * nz;
A12 += Ym * (nz * nz) - Zm * ny * nz;
A13 += -Xm * (nz * nz) + Zm * nx * nz;
A14 += Xm * ny * nz - Ym * nx * nz;

A15 += (Ym * Ym) * (nz * nz) + (Zm * Zm) * (ny * ny) -
Ym * Zm * ny * nz * 2.0f;
A16 += -Xm * Ym * (nz * nz) - (Zm * Zm) * nx * ny + Xm * Zm * ny * nz +
Ym * Zm * nx * nz;
A17 += -Xm * Zm * (ny * ny) - (Ym * Ym) * nx * nz + Xm * Ym * ny * nz +
Ym * Zm * nx * ny;

A18 += (Xm * Xm) * (nz * nz) + (Zm * Zm) * (nx * nx) -
Xm * Zm * nx * nz * 2.0f;
A19 += -Ym * Zm * (nx * nx) - (Xm * Xm) * ny * nz + Xm * Ym * nx * nz +
Xm * Zm * nx * ny;

A20 += (Xm * Xm) * (ny * ny) + (Ym * Ym) * (nx * nx) -
Xm * Ym * nx * ny * 2.0f;

// B-vector

A21 += Xd * (nx * nx) - Xm * (nx * nx) + Yd * nx * ny - Ym * nx * ny +
Zd * nx * nz - Zm * nx * nz;
A22 += Yd * (ny * ny) - Ym * (ny * ny) + Xd * nx * ny - Xm * nx * ny +
Zd * ny * nz - Zm * ny * nz;
A23 += Zd * (nz * nz) - Zm * (nz * nz) + Xd * nx * nz - Xm * nx * nz +
Yd * ny * nz - Ym * ny * nz;
A24 += -Yd * Zm * (ny * ny) + Ym * Zd * (nz * nz) + Ym * Zm * (ny * ny) -
Ym * Zm * (nz * nz) - (Ym * Ym) * ny * nz + (Zm * Zm) * ny * nz +
Xd * Ym * nx * nz - Xm * Ym * nx * nz - Xd * Zm * nx * ny +
Yd * Ym * ny * nz + Xm * Zm * nx * ny - Zd * Zm * ny * nz;
A25 += Xd * Zm * (nx * nx) - Xm * Zd * (nz * nz) - Xm * Zm * (nx * nx) +
Xm * Zm * (nz * nz) + (Xm * Xm) * nx * nz - (Zm * Zm) * nx * nz -
Xd * Xm * nx * nz - Xm * Yd * ny * nz + Xm * Ym * ny * nz +
Yd * Zm * nx * ny - Ym * Zm * nx * ny + Zd * Zm * nx * nz;
A26 += -Xd * Ym * (nx * nx) + Xm * Yd * (ny * ny) + Xm * Ym * (nx * nx) -
Xm * Ym * (ny * ny) - (Xm * Xm) * nx * ny + (Ym * Ym) * nx * ny +
Xd * Xm * nx * ny - Yd * Ym * nx * ny + Xm * Zd * ny * nz -
Xm * Zm * ny * nz - Ym * Zd * nx * nz + Ym * Zm * nx * nz;
}
}

/**************************/
/* write out accumulators */
/**************************/

int out_ind =
27 * n_val_accum * blockIdx.y + blockDim.x * blockIdx.x + threadIdx.x;

d_CD[out_ind] = A0;
d_CD[out_ind + n_val_accum] = A1;
d_CD[out_ind + 2 * n_val_accum] = A2;
d_CD[out_ind + 3 * n_val_accum] = A3;
d_CD[out_ind + 4 * n_val_accum] = A4;
d_CD[out_ind + 5 * n_val_accum] = A5;
d_CD[out_ind + 6 * n_val_accum] = A6;
d_CD[out_ind + 7 * n_val_accum] = A7;
d_CD[out_ind + 8 * n_val_accum] = A8;
d_CD[out_ind + 9 * n_val_accum] = A9;
d_CD[out_ind + 10 * n_val_accum] = A10;
d_CD[out_ind + 11 * n_val_accum] = A11;
d_CD[out_ind + 12 * n_val_accum] = A12;
d_CD[out_ind + 13 * n_val_accum] = A13;
d_CD[out_ind + 14 * n_val_accum] = A14;
d_CD[out_ind + 15 * n_val_accum] = A15;
d_CD[out_ind + 16 * n_val_accum] = A16;
d_CD[out_ind + 17 * n_val_accum] = A17;
d_CD[out_ind + 18 * n_val_accum] = A18;
d_CD[out_ind + 19 * n_val_accum] = A19;
d_CD[out_ind + 20 * n_val_accum] = A20;
d_CD[out_ind + 21 * n_val_accum] = A21;
d_CD[out_ind + 22 * n_val_accum] = A22;
d_CD[out_ind + 23 * n_val_accum] = A23;
d_CD[out_ind + 24 * n_val_accum] = A24;
d_CD[out_ind + 25 * n_val_accum] = A25;
d_CD[out_ind + 26 * n_val_accum] = A26;
}
	.file	"tmpxft_0029e5d3_00000000-6_normal_eqs_disparity_multicam_GPU.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z89__device_stub__Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_PfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_
	.type	_Z89__device_stub__Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_PfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_, @function
_Z89__device_stub__Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_PfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	120(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 40(%rsp)
	movq	296(%rsp), %rax
	movq	%rdx, 72(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 32(%rsp)
	movq	304(%rsp), %rax
	movq	%rcx, 64(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 24(%rsp)
	movq	312(%rsp), %rax
	movq	%r8, 56(%rsp)
	movq	%rax, 16(%rsp)
	movq	320(%rsp), %rax
	movq	%r9, 48(%rsp)
	movq	%rax, 8(%rsp)
	movq	328(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	%rsp, %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	112(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 304
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L2:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z89__device_stub__Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_PfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_, .-_Z89__device_stub__Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_PfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_
	.globl	_Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_
	.type	_Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_, @function
_Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z89__device_stub__Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_PfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_
	.cfi_endproc
.LFE2033:
	.size	_Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_, .-_Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z33normal_eqs_disparity_multicam_GPUPfS_P6float4PiPKfS4_S4_S4_PKiS6_S6_S6_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void normal_eqs_disparity_multicam_GPU( float *d_CD, float *d_disparity_compact, float4 *d_Zbuffer_normals_compact, int *d_ind_disparity_Zbuffer, const float *d_focal_length, const float *d_nodal_point_x, const float *d_nodal_point_y, const float *d_baseline, const int *d_n_cols, const int *d_n_values_disparity, const int *d_start_ind_disparity, const int *d_pixel_ind_offset) {
int n_val_accum = gridDim.x * blockDim.x; // _MAX_N_VAL_ACCUM may not be
// multiple of blocksize

int n_disparity = d_n_values_disparity[blockIdx.y];
int n_accum = (int)ceilf((float)n_disparity / (float)n_val_accum);
int start_ind = d_start_ind_disparity[blockIdx.y];

float f = d_focal_length[blockIdx.y];
float ox = d_nodal_point_x[blockIdx.y];
float oy = d_nodal_point_y[blockIdx.y];
float b = d_baseline[blockIdx.y];
int n_cols = d_n_cols[blockIdx.y];
int pixel_ind_offset = d_pixel_ind_offset[blockIdx.y];

// initialize accumulators

float A0 = 0.0f, A1 = 0.0f, A2 = 0.0f, A3 = 0.0f, A4 = 0.0f, A5 = 0.0f,
A6 = 0.0f, A7 = 0.0f, A8 = 0.0f, A9 = 0.0f, A10 = 0.0f, A11 = 0.0f,
A12 = 0.0f, A13 = 0.0f, A14 = 0.0f, A15 = 0.0f, A16 = 0.0f, A17 = 0.0f,
A18 = 0.0f, A19 = 0.0f, A20 = 0.0f, A21 = 0.0f, A22 = 0.0f, A23 = 0.0f,
A24 = 0.0f, A25 = 0.0f, A26 = 0.0f;

for (int in_ind = blockDim.x * blockIdx.x * n_accum + threadIdx.x;
in_ind < blockDim.x * (blockIdx.x + 1) * n_accum; in_ind += blockDim.x) {

if (in_ind < n_disparity) { // is this a valid sample?

// fetch disparity, Zbuffer and normal from global memory
float disp = d_disparity_compact[in_ind + start_ind];
float4 tmp = d_Zbuffer_normals_compact[in_ind + start_ind];
float Zbuffer = tmp.x;
float nx = tmp.y;
float ny = tmp.z;
float nz = tmp.w;

// compute coordinates
int pixel_ind =
d_ind_disparity_Zbuffer[in_ind + start_ind] - pixel_ind_offset;

float y = floorf(__fdividef((float)pixel_ind, n_cols));
float x = (float)pixel_ind - y * n_cols;

x = __fdividef((x - ox), f);
y = -__fdividef((y - oy), f);

// reconstruct 3D point from disparity

float Zd = -(f * b) / disp;
float Xd = x * Zd;
float Yd = y * Zd;

// reconstruct 3D point from model

float Zm = Zbuffer;
float Xm = x * Zm;
float Ym = y * Zm;

/************************/
/* evaluate constraints */
/************************/

// unique values A-matrix

A0 += nx * nx;
A1 += nx * ny;
A2 += nx * nz;
A3 += Ym * nx * nz - Zm * nx * ny;
A4 += Zm * (nx * nx) - Xm * nx * nz;
A5 += -Ym * (nx * nx) + Xm * nx * ny;

A6 += ny * ny;
A7 += ny * nz;
A8 += -Zm * (ny * ny) + Ym * ny * nz;
A9 += -Xm * ny * nz + Zm * nx * ny;
A10 += Xm * (ny * ny) - Ym * nx * ny;

A11 += nz * nz;
A12 += Ym * (nz * nz) - Zm * ny * nz;
A13 += -Xm * (nz * nz) + Zm * nx * nz;
A14 += Xm * ny * nz - Ym * nx * nz;

A15 += (Ym * Ym) * (nz * nz) + (Zm * Zm) * (ny * ny) -
Ym * Zm * ny * nz * 2.0f;
A16 += -Xm * Ym * (nz * nz) - (Zm * Zm) * nx * ny + Xm * Zm * ny * nz +
Ym * Zm * nx * nz;
A17 += -Xm * Zm * (ny * ny) - (Ym * Ym) * nx * nz + Xm * Ym * ny * nz +
Ym * Zm * nx * ny;

A18 += (Xm * Xm) * (nz * nz) + (Zm * Zm) * (nx * nx) -
Xm * Zm * nx * nz * 2.0f;
A19 += -Ym * Zm * (nx * nx) - (Xm * Xm) * ny * nz + Xm * Ym * nx * nz +
Xm * Zm * nx * ny;

A20 += (Xm * Xm) * (ny * ny) + (Ym * Ym) * (nx * nx) -
Xm * Ym * nx * ny * 2.0f;

// B-vector

A21 += Xd * (nx * nx) - Xm * (nx * nx) + Yd * nx * ny - Ym * nx * ny +
Zd * nx * nz - Zm * nx * nz;
A22 += Yd * (ny * ny) - Ym * (ny * ny) + Xd * nx * ny - Xm * nx * ny +
Zd * ny * nz - Zm * ny * nz;
A23 += Zd * (nz * nz) - Zm * (nz * nz) + Xd * nx * nz - Xm * nx * nz +
Yd * ny * nz - Ym * ny * nz;
A24 += -Yd * Zm * (ny * ny) + Ym * Zd * (nz * nz) + Ym * Zm * (ny * ny) -
Ym * Zm * (nz * nz) - (Ym * Ym) * ny * nz + (Zm * Zm) * ny * nz +
Xd * Ym * nx * nz - Xm * Ym * nx * nz - Xd * Zm * nx * ny +
Yd * Ym * ny * nz + Xm * Zm * nx * ny - Zd * Zm * ny * nz;
A25 += Xd * Zm * (nx * nx) - Xm * Zd * (nz * nz) - Xm * Zm * (nx * nx) +
Xm * Zm * (nz * nz) + (Xm * Xm) * nx * nz - (Zm * Zm) * nx * nz -
Xd * Xm * nx * nz - Xm * Yd * ny * nz + Xm * Ym * ny * nz +
Yd * Zm * nx * ny - Ym * Zm * nx * ny + Zd * Zm * nx * nz;
A26 += -Xd * Ym * (nx * nx) + Xm * Yd * (ny * ny) + Xm * Ym * (nx * nx) -
Xm * Ym * (ny * ny) - (Xm * Xm) * nx * ny + (Ym * Ym) * nx * ny +
Xd * Xm * nx * ny - Yd * Ym * nx * ny + Xm * Zd * ny * nz -
Xm * Zm * ny * nz - Ym * Zd * nx * nz + Ym * Zm * nx * nz;
}
}

/**************************/
/* write out accumulators */
/**************************/

int out_ind =
27 * n_val_accum * blockIdx.y + blockDim.x * blockIdx.x + threadIdx.x;

d_CD[out_ind] = A0;
d_CD[out_ind + n_val_accum] = A1;
d_CD[out_ind + 2 * n_val_accum] = A2;
d_CD[out_ind + 3 * n_val_accum] = A3;
d_CD[out_ind + 4 * n_val_accum] = A4;
d_CD[out_ind + 5 * n_val_accum] = A5;
d_CD[out_ind + 6 * n_val_accum] = A6;
d_CD[out_ind + 7 * n_val_accum] = A7;
d_CD[out_ind + 8 * n_val_accum] = A8;
d_CD[out_ind + 9 * n_val_accum] = A9;
d_CD[out_ind + 10 * n_val_accum] = A10;
d_CD[out_ind + 11 * n_val_accum] = A11;
d_CD[out_ind + 12 * n_val_accum] = A12;
d_CD[out_ind + 13 * n_val_accum] = A13;
d_CD[out_ind + 14 * n_val_accum] = A14;
d_CD[out_ind + 15 * n_val_accum] = A15;
d_CD[out_ind + 16 * n_val_accum] = A16;
d_CD[out_ind + 17 * n_val_accum] = A17;
d_CD[out_ind + 18 * n_val_accum] = A18;
d_CD[out_ind + 19 * n_val_accum] = A19;
d_CD[out_ind + 20 * n_val_accum] = A20;
d_CD[out_ind + 21 * n_val_accum] = A21;
d_CD[out_ind + 22 * n_val_accum] = A22;
d_CD[out_ind + 23 * n_val_accum] = A23;
d_CD[out_ind + 24 * n_val_accum] = A24;
d_CD[out_ind + 25 * n_val_accum] = A25;
d_CD[out_ind + 26 * n_val_accum] = A26;
}
	.text
	.file	"normal_eqs_disparity_multicam_GPU.hip"
	.globl	_Z48__device_stub__normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_ # -- Begin function _Z48__device_stub__normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.type	_Z48__device_stub__normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_,@function
_Z48__device_stub__normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_: # @_Z48__device_stub__normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z48__device_stub__normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_, .Lfunc_end0-_Z48__device_stub__normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_,@object # @_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.section	.rodata,"a",@progbits
	.globl	_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.p2align	3, 0x0
_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_:
	.quad	_Z48__device_stub__normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.size	_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_"
	.size	.L__unnamed_1, 93

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z48__device_stub__normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_ ; -- Begin function _Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.globl	_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
	.p2align	8
	.type	_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_,@function
_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_: ; @_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x6c
	s_load_b256 s[4:11], s[0:1], 0x40
	s_mov_b32 s12, s15
	s_mov_b32 s13, 0
	s_load_b32 s16, s[0:1], 0x60
	s_lshl_b64 s[34:35], s[12:13], 2
	v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v30, 0
	v_dual_mov_b32 v26, 0 :: v_dual_mov_b32 v27, 0
	v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v23, 0
	v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v22, 0
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v18, 0
	v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v20, 0
	v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v17, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s15, s2, 0xffff
	s_add_u32 s2, s6, s34
	s_addc_u32 s3, s7, s35
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v14, 0
	s_load_b32 s6, s[2:3], 0x0
	s_mul_i32 s2, s16, s15
	s_load_b512 s[16:31], s[0:1], 0x0
	v_cvt_f32_i32_e32 v1, s2
	s_mul_i32 s3, s14, s15
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
	s_add_i32 s0, s3, s15
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v15, 0
	s_mov_b32 s7, exec_lo
	v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v32, 0
	v_mov_b32_e32 v28, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v1, v1, v2
	v_div_scale_f32 v6, vcc_lo, v2, v1, v2
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_mul_f32_e32 v5, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v5, v6
	v_fmac_f32_e32 v5, v7, v4
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v5, v6
	v_div_fmas_f32 v3, v3, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v3, v1, v2
	v_ceil_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v1, v1
	v_mad_u64_u32 v[5:6], null, s3, v1, v[0:1]
	v_mul_lo_u32 v33, s0, v1
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_u32_e64 v5, v33
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.lr.ph
	s_add_u32 s0, s8, s34
	s_addc_u32 s1, s9, s35
	s_add_u32 s8, s24, s34
	s_addc_u32 s9, s25, s35
	s_add_u32 s24, s26, s34
	s_addc_u32 s25, s27, s35
	s_add_u32 s26, s28, s34
	s_addc_u32 s27, s29, s35
	s_add_u32 s10, s10, s34
	s_addc_u32 s11, s11, s35
	s_add_u32 s4, s4, s34
	s_addc_u32 s5, s5, s35
	s_add_u32 s28, s30, s34
	s_addc_u32 s29, s31, s35
	s_load_b32 s8, s[8:9], 0x0
	s_load_b32 s14, s[4:5], 0x0
	s_load_b32 s28, s[28:29], 0x0
	s_load_b32 s4, s[0:1], 0x0
	s_load_b32 s5, s[24:25], 0x0
	s_load_b32 s9, s[26:27], 0x0
	s_load_b32 s10, s[10:11], 0x0
	v_dual_mov_b32 v32, 0 :: v_dual_mov_b32 v31, 0
	v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v28, 0
	v_dual_mov_b32 v30, 0 :: v_dual_mov_b32 v27, 0
	v_dual_mov_b32 v26, 0 :: v_dual_mov_b32 v23, 0
	v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v25, 0
	v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v22, 0
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v19, 0
	v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v17, 0
	v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v13, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v34, s14
	v_mul_f32_e64 v35, s28, -s8
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v7, 0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, 0
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v11, 0
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v15, 0
	v_mov_b32_e32 v12, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s11, exec_lo
	v_cmpx_gt_i32_e64 s6, v5
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v1, s4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_lshlrev_b64 v[1:2], 4, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v36, vcc_lo, s22, v3
	v_add_co_ci_u32_e32 v37, vcc_lo, s23, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v36, v[36:37], off
	v_add_co_u32 v1, vcc_lo, s20, v1
	global_load_b32 v37, v[3:4], off
	v_add_co_ci_u32_e32 v2, vcc_lo, s21, v2, vcc_lo
	global_load_b128 v[1:4], v[1:2], off
	s_waitcnt vmcnt(2)
	v_subrev_nc_u32_e32 v36, s10, v36
	s_waitcnt vmcnt(1)
	v_div_scale_f32 v43, s0, v35, v37, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v36, v36
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v29, v2, v4 :: v_dual_mul_f32 v48, v1, v2
	v_div_scale_f32 v38, null, v34, v34, v36
	v_div_scale_f32 v41, vcc_lo, v36, v34, v36
	v_dual_fmac_f32 v24, v3, v4 :: v_dual_mul_f32 v59, v1, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_f32_e32 v39, v38
	v_dual_fmac_f32 v32, v2, v2 :: v_dual_mul_f32 v49, v3, v3
	v_dual_fmac_f32 v22, v4, v4 :: v_dual_fmac_f32 v31, v2, v3
	v_mul_f32_e32 v55, v1, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v40, -v38, v39, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v39, v40, v39
	v_mul_f32_e32 v40, v41, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v42, -v38, v40, v41
	v_fmac_f32_e32 v40, v42, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v38, -v38, v40, v41
	v_div_fmas_f32 v38, v38, v39, v40
	v_div_scale_f32 v39, null, v37, v37, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v38, v38, v34, v36
	v_rcp_f32_e32 v40, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v38, v38
	v_fma_f32 v36, -v38, v34, v36
	v_subrev_f32_e32 v38, s9, v38
	s_waitcnt_depctr 0xfff
	v_fma_f32 v47, -v39, v40, 1.0
	v_dual_mul_f32 v45, v2, v2 :: v_dual_subrev_f32 v36, s5, v36
	v_div_scale_f32 v42, null, s8, s8, -v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v40, v47, v40
	v_div_scale_f32 v41, null, s8, s8, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v46, v42
	v_div_scale_f32 v51, vcc_lo, v36, s8, v36
	v_rcp_f32_e32 v44, v41
	s_waitcnt_depctr 0xfff
	v_fma_f32 v47, -v42, v46, 1.0
	v_fma_f32 v50, -v41, v44, 1.0
	v_fmac_f32_e32 v27, v3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v46, v47, v46 :: v_dual_mul_f32 v47, v4, v4
	v_fmac_f32_e32 v44, v50, v44
	v_div_scale_f32 v50, s1, -v38, s8, -v38
	v_mul_f32_e32 v53, v43, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v52, v51, v44
	v_mul_f32_e32 v54, v50, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v57, -v39, v53, v43
	v_mul_f32_e32 v60, v48, v3
	v_fma_f32 v58, -v42, v54, v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v53, v57, v40
	v_dual_mul_f32 v57, v55, v4 :: v_dual_fmac_f32 v54, v58, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v39, -v39, v53, v43
	v_mul_f32_e32 v43, v1, v47
	v_fma_f32 v56, -v41, v52, v51
	v_fma_f32 v42, -v42, v54, v50
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v52, v56, v44
	v_fma_f32 v41, -v41, v52, v51
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v41, v41, v44, v52
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f32 v42, v42, v46, v54
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v36, v41, s8, v36
	v_div_fmas_f32 v39, v39, v40, v53
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v38, v42, s8, -v38
	v_div_fixup_f32 v37, v39, v37, v35
	v_mul_f32_e32 v39, v59, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v51, v37, v1
	v_mul_f32_e32 v42, v1, v36
	v_fma_f32 v43, v37, v47, -v43
	v_mul_f32_e32 v80, v51, v3
	v_dual_mul_f32 v51, v51, v2 :: v_dual_mul_f32 v36, v37, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v53, v3, v42
	v_mul_f32_e32 v44, v1, v38
	v_mul_f32_e64 v61, v1, -v42
	v_dual_mul_f32 v75, v2, v36 :: v_dual_mul_f32 v40, v59, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mul_f32 v65, v2, v44 :: v_dual_mul_f32 v38, v37, v38
	v_dual_mul_f32 v67, v3, v44 :: v_dual_mul_f32 v52, v2, v42
	v_dual_mul_f32 v69, v1, v44 :: v_dual_mul_f32 v54, v47, v42
	v_dual_mul_f32 v73, v49, v44 :: v_dual_mul_f32 v62, v42, v42
	v_dual_mul_f32 v63, v45, v42 :: v_dual_mul_f32 v68, v44, v44
	v_dual_mul_f32 v64, v37, v42 :: v_dual_mul_f32 v91, v3, v65
	v_dual_mul_f32 v56, v1, v49 :: v_dual_mul_f32 v41, v40, v3
	v_dual_mul_f32 v46, v37, v2 :: v_dual_mul_f32 v83, v4, v52
	v_dual_mul_f32 v50, v37, v3 :: v_dual_mul_f32 v71, v44, v42
	v_mul_f32_e32 v58, v1, v42
	v_dual_mul_f32 v66, v45, v44 :: v_dual_mul_f32 v81, v36, v42
	v_fma_f32 v57, v47, v44, -v57
	v_mul_f32_e64 v70, v44, -v42
	v_dual_mul_f32 v37, v37, v44 :: v_dual_mul_f32 v74, v2, v38
	v_mul_f32_e32 v79, v1, v36
	v_dual_mul_f32 v77, v1, v38 :: v_dual_mul_f32 v78, v44, v36
	v_fma_f32 v84, -v4, v53, v60
	v_fma_f32 v54, v48, v4, -v54
	v_mul_f32_e32 v89, v49, v62
	v_fma_f32 v36, v45, v36, -v63
	v_mul_f32_e32 v63, v47, v64
	v_mul_f32_e32 v64, v3, v64
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mul_f32 v88, v3, v62 :: v_dual_fmac_f32 v89, v45, v68
	v_fma_f32 v60, v4, v65, -v60
	v_mul_f32_e64 v72, v1, -v44
	v_mul_f32_e32 v76, v3, v38
	v_dual_mul_f32 v44, v38, v44 :: v_dual_mul_f32 v85, v3, v58
	v_mul_f32_e32 v82, v38, v42
	v_dual_mul_f32 v86, v47, v62 :: v_dual_add_f32 v25, v25, v84
	v_mul_f32_e32 v87, v2, v58
	v_dual_mul_f32 v62, v2, v62 :: v_dual_fmac_f32 v43, v4, v75
	v_dual_mul_f32 v90, v4, v65 :: v_dual_add_f32 v19, v19, v54
	v_fma_f32 v66, v3, v52, -v66
	v_fma_f32 v56, v4, v67, -v56
	v_dual_add_f32 v18, v18, v57 :: v_dual_mul_f32 v57, v47, v68
	v_mul_f32_e32 v92, v3, v69
	v_fma_f32 v41, v47, v70, -v41
	v_fma_f32 v38, v49, v38, -v73
	v_mul_f32_e32 v54, v2, v71
	v_dual_add_f32 v28, v28, v60 :: v_dual_fmac_f32 v57, v59, v49
	v_fma_f32 v1, v1, v45, -v83
	v_dual_mul_f32 v83, v4, v88 :: v_dual_mul_f32 v60, v49, v77
	v_mul_f32_e32 v70, v2, v69
	v_dual_mul_f32 v73, v2, v68 :: v_dual_mul_f32 v84, v3, v71
	v_dual_mul_f32 v81, v2, v81 :: v_dual_mul_f32 v68, v3, v68
	v_dual_mul_f32 v77, v2, v77 :: v_dual_fmac_f32 v36, v3, v74
	v_dual_add_f32 v26, v26, v66 :: v_dual_fmac_f32 v41, v4, v85
	v_fma_f32 v63, v45, v79, -v63
	v_mul_f32_e32 v79, v2, v79
	v_dual_mul_f32 v74, v2, v37 :: v_dual_add_f32 v23, v23, v56
	v_fma_f32 v42, v49, v42, -v91
	v_mul_f32_e32 v56, v3, v44
	v_mul_f32_e32 v91, v3, v82
	v_fmac_f32_e32 v38, v3, v75
	v_mul_f32_e32 v75, v3, v54
	v_fma_f32 v43, -v4, v52, v43
	v_dual_fmac_f32 v86, v59, v45 :: v_dual_mul_f32 v59, v4, v92
	v_mul_f32_e32 v66, v2, v78
	v_dual_mul_f32 v2, v2, v44 :: v_dual_fmac_f32 v41, v4, v70
	v_fma_f32 v44, v4, v53, -v90
	v_mul_f32_e32 v53, v4, v87
	v_fma_f32 v37, v47, v37, -v60
	v_dual_mul_f32 v78, v45, v78 :: v_dual_fmac_f32 v89, -2.0, v75
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v43, v4, v76 :: v_dual_fmac_f32 v86, -2.0, v53
	v_fma_f32 v53, -v45, v58, v63
	v_fmac_f32_e32 v37, v49, v69
	v_mul_f32_e32 v88, v4, v73
	v_fma_f32 v60, v49, v82, -v78
	v_fma_f32 v36, -v3, v65, v36
	v_fmac_f32_e32 v53, v47, v58
	v_fma_f32 v37, -v47, v69, v37
	v_dual_add_f32 v20, v20, v44 :: v_dual_add_f32 v17, v17, v41
	v_fmac_f32_e32 v57, -2.0, v59
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v53, v4, v62
	v_fma_f32 v37, -v4, v68, v37
	v_fmac_f32_e32 v60, v45, v71
	v_add_f32_e32 v21, v21, v42
	v_fma_f32 v42, v49, v61, -v88
	v_fma_f32 v40, -v40, v4, v53
	v_fmac_f32_e32 v37, v39, v4
	v_fma_f32 v44, -v49, v71, v60
	v_fmac_f32_e32 v36, v46, v4
	v_add_f32_e32 v30, v30, v1
	v_fma_f32 v39, -v4, v81, v40
	v_fmac_f32_e32 v37, v4, v66
	v_fma_f32 v44, -v3, v62, v44
	v_fma_f32 v1, v45, v72, -v83
	v_fma_f32 v38, -v3, v52, v38
	v_fma_f32 v39, -v4, v91, v39
	v_fma_f32 v37, -v4, v54, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v44, v3, v73 :: v_dual_fmac_f32 v1, v4, v54
	v_dual_add_f32 v14, v14, v86 :: v_dual_fmac_f32 v39, v4, v84
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v37, -v3, v79, v37
	v_fmac_f32_e32 v44, v3, v81
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v42, v4, v84 :: v_dual_fmac_f32 v1, v3, v87
	v_fmac_f32_e32 v39, v3, v77
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v37, v4, v56
	v_fma_f32 v2, -v3, v2, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v42, v3, v70
	v_add_f32_e32 v12, v12, v89
	v_dual_fmac_f32 v38, v50, v4 :: v_dual_add_f32 v15, v15, v1
	v_dual_fmac_f32 v2, v4, v64 :: v_dual_add_f32 v13, v13, v42
	v_fma_f32 v36, -v48, v4, v36
	v_fma_f32 v39, -v3, v70, v39
	v_fmac_f32_e32 v37, v3, v87
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v2, -v4, v85, v2
	v_fma_f32 v40, -v4, v67, v43
	v_fma_f32 v38, -v55, v4, v38
	v_fmac_f32_e32 v39, v51, v4
	v_fma_f32 v1, -v80, v4, v37
	v_fma_f32 v2, -v4, v74, v2
	v_dual_add_f32 v11, v11, v36 :: v_dual_add_f32 v16, v16, v57
	v_dual_add_f32 v9, v9, v40 :: v_dual_add_f32 v10, v10, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v2, v4, v70 :: v_dual_add_f32 v7, v7, v39
	v_add_f32_e32 v8, v8, v1
	v_add_f32_e32 v6, v6, v2
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v5, s15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, v5, v33
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_2
; %bb.5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_6:                                ; %Flow689
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s7
	s_mul_i32 s0, s12, s2
	s_mul_i32 s0, s0, 27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s0, s3, v0
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add3_u32 v2, s2, s2, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s2, v2
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v33, s2, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_ashrrev_i32_e32 v34, 31, v33
	global_store_b32 v[0:1], v32, off
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_nc_u32_e32 v35, s2, v33
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_lshlrev_b64 v[32:33], 2, v[33:34]
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	global_store_b32 v[0:1], v31, off
	v_add_co_u32 v0, vcc_lo, s16, v4
	v_add_nc_u32_e32 v4, s2, v35
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v5, vcc_lo
	v_add_co_u32 v31, vcc_lo, s16, v32
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e32 v32, vcc_lo, s17, v33, vcc_lo
	v_ashrrev_i32_e32 v36, 31, v35
	s_clause 0x2
	global_store_b32 v[2:3], v29, off
	global_store_b32 v[0:1], v28, off
	global_store_b32 v[31:32], v30, off
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	v_add_nc_u32_e32 v4, s2, v4
	v_lshlrev_b64 v[2:3], 2, v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v28, s2, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v2, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	v_add_nc_u32_e32 v30, s2, v28
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_ashrrev_i32_e32 v29, 31, v28
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_ashrrev_i32_e32 v31, 31, v30
	s_clause 0x1
	global_store_b32 v[2:3], v26, off
	global_store_b32 v[0:1], v27, off
	v_lshlrev_b64 v[0:1], 2, v[28:29]
	v_add_co_u32 v2, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v5, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[30:31]
	v_add_nc_u32_e32 v26, s2, v30
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_nc_u32_e32 v28, s2, v26
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	v_ashrrev_i32_e32 v27, 31, v26
	global_store_b32 v[2:3], v24, off
	v_ashrrev_i32_e32 v29, 31, v28
	s_clause 0x1
	global_store_b32 v[0:1], v23, off
	global_store_b32 v[4:5], v25, off
	v_add_nc_u32_e32 v4, s2, v28
	v_lshlrev_b64 v[2:3], 2, v[26:27]
	v_lshlrev_b64 v[0:1], 2, v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v23, s2, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v25, s2, v23
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_ashrrev_i32_e32 v26, 31, v25
	s_clause 0x1
	global_store_b32 v[2:3], v21, off
	global_store_b32 v[0:1], v22, off
	v_lshlrev_b64 v[0:1], 2, v[23:24]
	v_add_co_u32 v2, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v5, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[25:26]
	v_add_nc_u32_e32 v21, s2, v25
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_nc_u32_e32 v23, s2, v21
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	v_ashrrev_i32_e32 v22, 31, v21
	global_store_b32 v[2:3], v18, off
	v_ashrrev_i32_e32 v24, 31, v23
	s_clause 0x1
	global_store_b32 v[0:1], v19, off
	global_store_b32 v[4:5], v20, off
	v_add_nc_u32_e32 v4, s2, v23
	v_lshlrev_b64 v[2:3], 2, v[21:22]
	v_lshlrev_b64 v[0:1], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v18, s2, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v20, s2, v18
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_ashrrev_i32_e32 v21, 31, v20
	s_clause 0x1
	global_store_b32 v[2:3], v16, off
	global_store_b32 v[0:1], v17, off
	v_lshlrev_b64 v[0:1], 2, v[18:19]
	v_add_co_u32 v2, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v5, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[20:21]
	v_add_nc_u32_e32 v16, s2, v20
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_nc_u32_e32 v18, s2, v16
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	v_ashrrev_i32_e32 v17, 31, v16
	s_clause 0x2
	global_store_b32 v[2:3], v13, off
	global_store_b32 v[0:1], v14, off
	global_store_b32 v[4:5], v15, off
	v_add_nc_u32_e32 v4, s2, v18
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[2:3], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v13, s2, v4
	v_lshlrev_b64 v[0:1], 2, v[18:19]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	v_add_nc_u32_e32 v15, s2, v13
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_ashrrev_i32_e32 v14, 31, v13
	global_store_b32 v[2:3], v12, off
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_nc_u32_e32 v4, s2, v15
	v_ashrrev_i32_e32 v16, 31, v15
	global_store_b32 v[0:1], v11, off
	v_lshlrev_b64 v[0:1], 2, v[13:14]
	v_add_nc_u32_e32 v13, s2, v4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v2, vcc_lo, s16, v2
	v_lshlrev_b64 v[11:12], 2, v[15:16]
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v14, 31, v13
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v11, vcc_lo, s16, v11
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v12, vcc_lo
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s16, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s17, v14, vcc_lo
	s_clause 0x4
	global_store_b32 v[2:3], v10, off
	global_store_b32 v[0:1], v9, off
	global_store_b32 v[11:12], v8, off
	global_store_b32 v[4:5], v7, off
	global_store_b32 v[13:14], v6, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 93
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_, .Lfunc_end0-_Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3192
; NumSgprs: 38
; NumVgprs: 93
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 93
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_
    .private_segment_fixed_size: 0
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z33normal_eqs_disparity_multicam_GPUPfS_P15HIP_vector_typeIfLj4EEPiPKfS5_S5_S5_PKiS7_S7_S7_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     93
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
