#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>

__global__ void kernel(int** arr)
{
	for (int i=0; i<3; i++)
		printf("%d\n", arr[i][0]);
}

int main()
{
	int arr[][3] = {{1},{2},{3}}; // 3 arrays, 1 element each
	char x = 0b100000100;
	printf("Bin: %d\n", x);

	int **d_arr;

	cudaMalloc((void***)(&d_arr), sizeof(int*)*3); // allocate for 3 int pointers

	for (int i=0; i<3; i++)
	{
		int* temp;
		cudaMalloc( (void**)  &(temp), sizeof(int) * 1 ); // allocate for 1 int in each int pointer
		cudaMemcpy(temp, arr[i], sizeof(int) * 1, cudaMemcpyHostToDevice); // copy data
		cudaMemcpy(d_arr+i, &temp, sizeof(int*), cudaMemcpyHostToDevice);
	}

	kernel<<<1,1>>>(d_arr);
	cudaDeviceSynchronize();
	cudaDeviceReset();
}

	.file	"tmpxft_00215b3c_00000000-6_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z26__device_stub__Z6kernelPPiPPi
	.type	_Z26__device_stub__Z6kernelPPiPPi, @function
_Z26__device_stub__Z6kernelPPiPPi:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z6kernelPPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L2:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z26__device_stub__Z6kernelPPiPPi, .-_Z26__device_stub__Z6kernelPPiPPi
	.globl	_Z6kernelPPi
	.type	_Z6kernelPPi, @function
_Z6kernelPPi:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z6kernelPPiPPi
	.cfi_endproc
.LFE2053:
	.size	_Z6kernelPPi, .-_Z6kernelPPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Bin: %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$8, %ecx
	movl	$4, %edx
	leaq	.LC0(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
	subq	$80, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rdi
	leaq	36(%rsp), %rbp
	movl	$1, 36(%rsp)
	leaq	24(%rsp), %r12
	rep stosl
	movl	$2, %edi
	movl	$2, 48(%rsp)
	movl	$3, 60(%rsp)
	call	__printf_chk@PLT
	movq	%rsp, %rdi
	movl	$24, %esi
	call	cudaMalloc@PLT
.L9:
	movl	$4, %esi
	movq	%r12, %rdi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	movl	$4, %edx
	addq	$12, %rbp
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$8, %edx
	addq	%rbx, %rdi
	addq	$8, %rbx
	call	cudaMemcpy@PLT
	cmpq	$24, %rbx
	jne	.L9
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 32(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	(%rsp), %rdi
	call	_Z26__device_stub__Z6kernelPPiPPi
.L10:
	call	cudaDeviceSynchronize@PLT
	call	cudaDeviceReset@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$80, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z6kernelPPi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kernelPPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

__global__ void kernel(int** arr)
{
	for (int i=0; i<3; i++)
		printf("%d\n", arr[i][0]);
}

int main()
{
	int arr[][3] = {{1},{2},{3}}; // 3 arrays, 1 element each
	char x = 0b100000100;
	printf("Bin: %d\n", x);

	int **d_arr;

	hipMalloc((void***)(&d_arr), sizeof(int*)*3); // allocate for 3 int pointers

	for (int i=0; i<3; i++)
	{
		int* temp;
		hipMalloc( (void**)  &(temp), sizeof(int) * 1 ); // allocate for 1 int in each int pointer
		hipMemcpy(temp, arr[i], sizeof(int) * 1, hipMemcpyHostToDevice); // copy data
		hipMemcpy(d_arr+i, &temp, sizeof(int*), hipMemcpyHostToDevice);
	}

	kernel<<<1,1>>>(d_arr);
	hipDeviceSynchronize();
	hipDeviceReset();
}

	.text
	.file	"test.hip"
	.globl	_Z21__device_stub__kernelPPi    # -- Begin function _Z21__device_stub__kernelPPi
	.type	_Z21__device_stub__kernelPPi,@function
_Z21__device_stub__kernelPPi:           # @_Z21__device_stub__kernelPPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelPPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelPPi, .Lfunc_end0-_Z21__device_stub__kernelPPi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorps	%xmm0, %xmm0
	leaq	16(%rsp), %rbx
	movaps	%xmm0, (%rbx)
	movaps	%xmm0, 16(%rbx)
	movl	$0, 32(%rbx)
	movl	$1, (%rbx)
	movl	$2, 12(%rbx)
	movl	$3, 24(%rbx)
	xorl	%r15d, %r15d
	movl	$.L.str, %edi
	movl	$4, %esi
	xorl	%eax, %eax
	callq	printf
	movq	%rsp, %rdi
	movl	$24, %esi
	callq	hipMalloc
	leaq	8(%rsp), %r14
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$4, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	8(%rsp), %rdi
	movl	$4, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	addq	%r15, %rdi
	movl	$8, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	addq	$8, %r15
	addq	$12, %rbx
	cmpq	$24, %r15
	jne	.LBB1_1
# %bb.2:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	(%rsp), %rdi
	callq	_Z21__device_stub__kernelPPi
.LBB1_4:
	callq	hipDeviceSynchronize
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelPPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kernelPPi,@object            # @_Z6kernelPPi
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelPPi
	.p2align	3, 0x0
_Z6kernelPPi:
	.quad	_Z21__device_stub__kernelPPi
	.size	_Z6kernelPPi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Bin: %d\n"
	.size	.L.str, 9

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kernelPPi"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelPPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kernelPPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kernelPPi            ; -- Begin function _Z6kernelPPi
	.globl	_Z6kernelPPi
	.p2align	8
	.type	_Z6kernelPPi,@function
_Z6kernelPPi:                           ; @_Z6kernelPPi
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x58
	v_mbcnt_lo_u32_b32 v29, -1, 0
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 2
	v_mov_b32_e32 v0, 33
	v_mov_b32_e32 v6, 1
	s_mov_b32 s7, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s6, s7
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_12 Depth 2
                                        ;     Child Loop BB0_18 Depth 2
                                        ;     Child Loop BB0_27 Depth 2
                                        ;     Child Loop BB0_30 Depth 2
                                        ;       Child Loop BB0_33 Depth 3
                                        ;       Child Loop BB0_41 Depth 3
                                        ;       Child Loop BB0_49 Depth 3
                                        ;       Child Loop BB0_57 Depth 3
                                        ;       Child Loop BB0_65 Depth 3
                                        ;       Child Loop BB0_73 Depth 3
                                        ;       Child Loop BB0_81 Depth 3
                                        ;       Child Loop BB0_89 Depth 3
                                        ;       Child Loop BB0_97 Depth 3
                                        ;       Child Loop BB0_103 Depth 3
                                        ;       Child Loop BB0_112 Depth 3
                                        ;     Child Loop BB0_120 Depth 2
                                        ;     Child Loop BB0_128 Depth 2
                                        ;     Child Loop BB0_134 Depth 2
                                        ;     Child Loop BB0_143 Depth 2
                                        ;     Child Loop BB0_148 Depth 2
                                        ;     Child Loop BB0_156 Depth 2
                                        ;     Child Loop BB0_162 Depth 2
                                        ;     Child Loop BB0_171 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[6:7], 3
	v_mov_b32_e32 v1, v29
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_load_b64 v[3:4], v2, s[0:1]
	s_waitcnt vmcnt(0)
	flat_load_b32 v30, v[3:4]
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_7
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[9:10], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5]
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[9:10]
	s_cbranch_execz .LBB0_6
; %bb.3:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s9, 0
.LBB0_4:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b64 v[11:12], v2, s[4:5]
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v9
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[7:8], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[9:10]
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %Flow350
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_6:                                ; %Flow352
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_7:                                ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[4:5] offset:40
	global_load_b128 v[7:10], v2, s[4:5]
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v11
	v_readfirstlane_b32 s11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, v2
	s_add_i32 s14, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v7, s13
	v_add_co_ci_u32_e32 v12, vcc_lo, s14, v8, vcc_lo
	global_store_b128 v[11:12], v[3:6], off offset:8
.LBB0_9:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v9, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v10, vcc_lo
	s_mov_b32 s16, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v1, v3
	s_mov_b32 s17, s7
	s_mov_b32 s18, s7
	s_mov_b32 s19, s7
	v_add_co_ci_u32_e32 v14, vcc_lo, v9, v4, vcc_lo
	v_mov_b32_e32 v1, v2
	v_mov_b32_e32 v3, v2
	v_dual_mov_b32 v9, s16 :: v_dual_mov_b32 v12, s19
	v_dual_mov_b32 v10, s17 :: v_dual_mov_b32 v11, s18
	s_clause 0x3
	global_store_b128 v[13:14], v[0:3], off
	global_store_b128 v[13:14], v[9:12], off offset:16
	global_store_b128 v[13:14], v[9:12], off offset:32
	global_store_b128 v[13:14], v[9:12], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_17
; %bb.10:                               ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	v_dual_mov_b32 v15, s8 :: v_dual_mov_b32 v16, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v3, vcc_lo, v7, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v8, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[3:4], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_13
; %bb.11:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s14, 0
.LBB0_12:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v9, s8 :: v_dual_mov_b32 v10, s9
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_12
.LBB0_13:                               ; %Flow348
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	global_load_b64 v[3:4], v2, s[4:5] offset:16
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v1, s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_1 Depth=1
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_15:                               ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_17:                               ; %Flow349
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s1
	v_add_co_u32 v1, vcc_lo, v7, s13
	v_add_co_ci_u32_e32 v4, vcc_lo, s12, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_18:                               ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_18 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_20:                               ;   in Loop: Header=BB0_18 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_18 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_23
.LBB0_22:                               ;   in Loop: Header=BB0_18 Depth=2
	s_mov_b32 s1, -1
.LBB0_23:                               ; %Flow343
                                        ;   in Loop: Header=BB0_18 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_18
; %bb.24:                               ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[7:8], v[13:14], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_28
; %bb.25:                               ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[13:14], v2, s[4:5] offset:24 glc
	global_load_b64 v[11:12], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_cndmask_b32 v9, v9, v1
	v_and_b32_e32 v1, v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v9, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_mov_b32_e32 v11, v13
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v1, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_28
; %bb.26:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
.LBB0_27:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_27
.LBB0_28:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, .str@rel32@lo+4
	s_addc_u32 s9, s9, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc0 .LBB0_115
; %bb.29:                               ;   in Loop: Header=BB0_1 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v10, v8 :: v_dual_and_b32 v31, 2, v7
	v_and_b32_e32 v9, -3, v7
	s_mov_b64 s[10:11], 4
.LBB0_30:                               ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_33 Depth 3
                                        ;       Child Loop BB0_41 Depth 3
                                        ;       Child Loop BB0_49 Depth 3
                                        ;       Child Loop BB0_57 Depth 3
                                        ;       Child Loop BB0_65 Depth 3
                                        ;       Child Loop BB0_73 Depth 3
                                        ;       Child Loop BB0_81 Depth 3
                                        ;       Child Loop BB0_89 Depth 3
                                        ;       Child Loop BB0_97 Depth 3
                                        ;       Child Loop BB0_103 Depth 3
                                        ;       Child Loop BB0_112 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[10:11], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s12, s10, 56
	s_cselect_b32 s13, s11, 0
	s_cmp_gt_u32 s12, 7
	s_cbranch_scc1 .LBB0_35
; %bb.31:                               ;   in Loop: Header=BB0_30 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc1 .LBB0_34
; %bb.32:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_lshl_b64 s[0:1], s[12:13], 3
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[8:9]
.LBB0_33:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s0, s14
	v_or_b32_e32 v11, v3, v11
	v_or_b32_e32 v12, v4, v12
	s_cbranch_scc1 .LBB0_33
.LBB0_34:                               ; %Flow319
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_36
.LBB0_35:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr18
.LBB0_36:                               ; %Flow321
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[8:9]
	s_cbranch_vccnz .LBB0_38
; %bb.37:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[11:12], v2, s[8:9]
	s_add_i32 s18, s12, -8
	s_add_u32 s0, s8, 8
	s_addc_u32 s1, s9, 0
.LBB0_38:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_43
; %bb.39:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_42
; %bb.40:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_41:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v13, v3, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v4, v14
	s_cbranch_scc1 .LBB0_41
.LBB0_42:                               ; %Flow314
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_44
.LBB0_43:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $sgpr19
.LBB0_44:                               ; %Flow316
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_46
; %bb.45:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[13:14], v2, s[0:1]
	s_add_i32 s19, s18, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_46:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_51
; %bb.47:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_50
; %bb.48:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_49:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v15, v3, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v4, v16
	s_cbranch_scc1 .LBB0_49
.LBB0_50:                               ; %Flow309
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_52
.LBB0_51:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr18
.LBB0_52:                               ; %Flow311
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_54
; %bb.53:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[15:16], v2, s[0:1]
	s_add_i32 s18, s19, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_54:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_59
; %bb.55:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_58
; %bb.56:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_57:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v17, v3, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v4, v18
	s_cbranch_scc1 .LBB0_57
.LBB0_58:                               ; %Flow304
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_60
.LBB0_59:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr19
.LBB0_60:                               ; %Flow306
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_62
; %bb.61:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[17:18], v2, s[0:1]
	s_add_i32 s19, s18, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_62:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_67
; %bb.63:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_66
; %bb.64:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_65:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s19, s16
	v_or_b32_e32 v19, v3, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v4, v20
	s_cbranch_scc1 .LBB0_65
.LBB0_66:                               ; %Flow299
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s18, 0
	s_branch .LBB0_68
.LBB0_67:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $sgpr18
.LBB0_68:                               ; %Flow301
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_70
; %bb.69:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[19:20], v2, s[0:1]
	s_add_i32 s18, s19, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_70:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s18, 7
	s_cbranch_scc1 .LBB0_75
; %bb.71:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s18, 0
	s_cbranch_scc1 .LBB0_74
; %bb.72:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], 0
.LBB0_73:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s0, s16
	s_addc_u32 s21, s1, s17
	s_add_u32 s16, s16, 1
	global_load_u8 v1, v2, s[20:21]
	s_addc_u32 s17, s17, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s18, s16
	v_or_b32_e32 v21, v3, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v4, v22
	s_cbranch_scc1 .LBB0_73
.LBB0_74:                               ; %Flow294
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, 0
	s_mov_b32 s19, 0
	s_branch .LBB0_76
.LBB0_75:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr19
.LBB0_76:                               ; %Flow296
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_78
; %bb.77:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[21:22], v2, s[0:1]
	s_add_i32 s19, s18, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_78:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s19, 7
	s_cbranch_scc1 .LBB0_83
; %bb.79:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s19, 0
	s_cbranch_scc1 .LBB0_82
; %bb.80:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[14:15], 0
	s_mov_b64 s[16:17], s[0:1]
.LBB0_81:                               ; %.preheader.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[16:17]
	s_add_i32 s19, s19, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s14, v[1:2]
	s_add_u32 s14, s14, 8
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 1
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s19, 0
	v_or_b32_e32 v23, v3, v23
	v_or_b32_e32 v24, v4, v24
	s_cbranch_scc1 .LBB0_81
.LBB0_82:                               ; %Flow289
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, 0
	s_branch .LBB0_84
.LBB0_83:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s14, -1
.LBB0_84:                               ; %Flow291
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_86
; %bb.85:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[23:24], v2, s[0:1]
.LBB0_86:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v1, v29
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_92
; %bb.87:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[27:28], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[25:26], v2, s[4:5]
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v28
	v_and_b32_e32 v3, v3, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v32, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v32, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v25, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v26, v4, vcc_lo
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[27:28]
	s_cbranch_execz .LBB0_91
; %bb.88:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s15, 0
.LBB0_89:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[25:26], v2, s[4:5] offset:40
	global_load_b64 v[32:33], v2, s[4:5]
	v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v27, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v25, v25, v27
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v25, 24, v[32:33]
	v_and_b32_e32 v32, v26, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, v32, 24, v[4:5]
	v_mov_b32_e32 v4, v25
	global_load_b64 v[25:26], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[25:28], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[27:28]
	s_or_b32 s15, vcc_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_89
; %bb.90:                               ; %Flow284
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
.LBB0_91:                               ; %Flow286
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_92:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[32:33], v2, s[4:5] offset:40
	global_load_b128 v[25:28], v2, s[4:5]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s20, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s16, v32
	v_readfirstlane_b32 s17, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[14:15], s[16:17]
	s_mul_i32 s1, s17, 24
	s_mul_hi_u32 s18, s16, 24
	s_mul_i32 s19, s16, 24
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB0_94
; %bb.93:                               ;   in Loop: Header=BB0_30 Depth=2
	v_dual_mov_b32 v3, s20 :: v_dual_mov_b32 v4, v2
	s_add_i32 s20, s18, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v32, vcc_lo, v25, s19
	v_add_co_ci_u32_e32 v33, vcc_lo, s20, v26, vcc_lo
	global_store_b128 v[32:33], v[3:6], off offset:8
.LBB0_94:                               ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	v_cmp_gt_u64_e64 vcc_lo, s[10:11], 56
	v_or_b32_e32 v3, 0, v10
	v_or_b32_e32 v4, v9, v31
	s_lshl_b64 s[16:17], s[16:17], 12
	s_lshl_b32 s20, s12, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s20, s20, 28
	v_dual_cndmask_b32 v10, v3, v10 :: v_dual_cndmask_b32 v9, v4, v9
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v27, s16
	v_add_co_ci_u32_e32 v27, vcc_lo, s17, v28, vcc_lo
	s_and_b32 s20, s20, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v9, 0xffffff1f, v9, s20
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[17:20], off offset:32
	global_store_b128 v[3:4], v[21:24], off offset:48
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_102
; %bb.95:                               ;   in Loop: Header=BB0_30 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[4:5] offset:32 glc
	global_load_b64 v[9:10], v2, s[4:5] offset:40
	v_dual_mov_b32 v15, s14 :: v_dual_mov_b32 v16, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v9
	v_readfirstlane_b32 s21, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[20:21], s[14:15]
	s_mul_i32 s17, s21, 24
	s_mul_hi_u32 s21, s20, 24
	s_mul_i32 s20, s20, 24
	s_add_i32 s21, s21, s17
	v_add_co_u32 v13, vcc_lo, v25, s20
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v26, vcc_lo
	s_mov_b32 s17, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[15:18], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[11:12], v[17:18]
	s_cbranch_execz .LBB0_98
; %bb.96:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s20, 0
.LBB0_97:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, s15
	s_sleep 1
	global_store_b64 v[13:14], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[11:12]
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_or_b32 s20, vcc_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_97
.LBB0_98:                               ; %Flow282
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b64 v[9:10], v2, s[4:5] offset:16
	s_mov_b32 s20, exec_lo
	s_mov_b32 s17, exec_lo
	v_mbcnt_lo_u32_b32 v1, s20, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_100
; %bb.99:                               ;   in Loop: Header=BB0_30 Depth=2
	s_bcnt1_i32_b32 s20, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s20
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[9:10], v[1:2], off offset:8
.LBB0_100:                              ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[9:10], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_102
; %bb.101:                              ;   in Loop: Header=BB0_30 Depth=2
	global_load_b32 v1, v[9:10], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s17, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[1:2], off
	s_and_b32 m0, s17, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_102:                              ; %Flow283
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_add_i32 s18, s18, s1
	v_add_co_u32 v1, vcc_lo, v25, s19
	v_add_co_ci_u32_e32 v10, vcc_lo, s18, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
.LBB0_103:                              ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_105
; %bb.104:                              ;   in Loop: Header=BB0_103 Depth=3
	global_load_b32 v1, v[9:10], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_105:                              ;   in Loop: Header=BB0_103 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_103 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_108
.LBB0_107:                              ;   in Loop: Header=BB0_103 Depth=3
	s_mov_b32 s1, -1
.LBB0_108:                              ; %Flow277
                                        ;   in Loop: Header=BB0_103 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_103
; %bb.109:                              ;   in Loop: Header=BB0_30 Depth=2
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_113
; %bb.110:                              ;   in Loop: Header=BB0_30 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[15:16], v2, s[4:5] offset:24 glc
	global_load_b64 v[13:14], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v12, vcc_lo, s15, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_cndmask_b32_e32 v11, v11, v1, vcc_lo
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_and_b32 v3, v11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v12, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_113
; %bb.111:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s0, 0
.LBB0_112:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v2, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_112
.LBB0_113:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s10, s10, s12
	s_subb_u32 s11, s11, s13
	s_add_u32 s8, s8, s12
	s_addc_u32 s9, s9, s13
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_30
; %bb.114:                              ; %Flow322
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB0_116
.LBB0_115:                              ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_116:                              ; %Flow337
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_145
; %bb.117:                              ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v1, v29
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_123
; %bb.118:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[11:12], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[9:10], v2, s[4:5]
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v12
	v_and_b32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v13, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v13, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v9, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[11:12]
	s_cbranch_execz .LBB0_122
; %bb.119:                              ; %.preheader3.i.i.i9.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s9, 0
.LBB0_120:                              ; %.preheader3.i.i.i9
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[4:5] offset:40
	global_load_b64 v[13:14], v2, s[4:5]
	v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v9, 24, v[13:14]
	v_and_b32_e32 v13, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v13, 24, v[4:5]
	v_mov_b32_e32 v4, v9
	global_load_b64 v[9:10], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[9:12], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_120
; %bb.121:                              ; %Flow334
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_122:                              ; %Flow336
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_123:                              ; %.loopexit4.i.i.i4
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[9:10], v2, s[4:5] offset:40
	global_load_b128 v[11:14], v2, s[4:5]
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v9
	v_readfirstlane_b32 s11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_125
; %bb.124:                              ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, v2
	s_add_i32 s14, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v9, vcc_lo, v11, s13
	v_add_co_ci_u32_e32 v10, vcc_lo, s14, v12, vcc_lo
	global_store_b128 v[9:10], v[3:6], off offset:8
.LBB0_125:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s16, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s17, s7
	s_mov_b32 s18, s7
	s_mov_b32 s19, s7
	v_and_or_b32 v7, 0xffffff1f, v7, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v9, v4, vcc_lo
	v_mov_b32_e32 v9, v2
	v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v13, s16
	v_dual_mov_b32 v14, s17 :: v_dual_mov_b32 v15, s18
	v_mov_b32_e32 v16, s19
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_133
; %bb.126:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v2, s[4:5] offset:32 glc
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	v_dual_mov_b32 v15, s8 :: v_dual_mov_b32 v16, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v13, vcc_lo, v11, s14
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v12, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[13:14], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[15:18], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[17:18]
	s_cbranch_execz .LBB0_129
; %bb.127:                              ; %.preheader1.i.i.i7.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s14, 0
.LBB0_128:                              ; %.preheader1.i.i.i7
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, s9
	s_sleep 1
	global_store_b64 v[13:14], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_128
.LBB0_129:                              ; %Flow332
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	global_load_b64 v[7:8], v2, s[4:5] offset:16
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v1, s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_131
; %bb.130:                              ;   in Loop: Header=BB0_1 Depth=1
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB0_131:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_133
; %bb.132:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[1:2], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_133:                              ; %Flow333
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s1
	v_add_co_u32 v1, vcc_lo, v11, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_134:                              ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_136
; %bb.135:                              ;   in Loop: Header=BB0_134 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_136:                              ;   in Loop: Header=BB0_134 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_138
; %bb.137:                              ;   in Loop: Header=BB0_134 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_139
.LBB0_138:                              ;   in Loop: Header=BB0_134 Depth=2
	s_mov_b32 s1, -1
.LBB0_139:                              ; %Flow327
                                        ;   in Loop: Header=BB0_134 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_134
; %bb.140:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b128 v[9:12], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_144
; %bb.141:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5] offset:24 glc
	global_load_b64 v[13:14], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v1
	v_and_b32_e32 v1, v12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v11, v3
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v13, v3
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[3:4], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v2, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_144
; %bb.142:                              ; %.preheader.i.i.i6.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
.LBB0_143:                              ; %.preheader.i.i.i6
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_143
.LBB0_144:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_145:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v1, v29
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_151
; %bb.146:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[13:14], v2, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[7:8], v2, s[4:5]
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v14
	v_and_b32_e32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v11, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v11, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v7, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[13:14]
	s_cbranch_execz .LBB0_150
; %bb.147:                              ; %.preheader3.i.i.i16.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s9, 0
.LBB0_148:                              ; %.preheader3.i.i.i16
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b64 v[11:12], v2, s[4:5]
	v_dual_mov_b32 v14, v4 :: v_dual_mov_b32 v13, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[4:5]
	v_mov_b32_e32 v4, v7
	global_load_b64 v[11:12], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[11:14], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[13:14]
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_148
; %bb.149:                              ; %Flow270
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_150:                              ; %Flow272
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
.LBB0_151:                              ; %.loopexit4.i.i.i10
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v2, s[4:5] offset:40
	global_load_b128 v[13:16], v2, s[4:5]
	v_readfirstlane_b32 s8, v3
	v_readfirstlane_b32 s9, v4
	s_mov_b32 s14, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[8:9], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s12, s10, 24
	s_mul_i32 s13, s10, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_153
; %bb.152:                              ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, v2
	s_add_i32 s14, s12, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v13, s13
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v14, vcc_lo
	global_store_b128 v[7:8], v[3:6], off offset:8
.LBB0_153:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v16, vcc_lo
	s_mov_b32 s16, s7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s17, s7
	s_mov_b32 s18, s7
	s_mov_b32 s19, s7
	v_and_or_b32 v9, 0xffffff1d, v9, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v11, v30
	v_dual_mov_b32 v12, v2 :: v_dual_mov_b32 v15, s16
	v_dual_mov_b32 v16, s17 :: v_dual_mov_b32 v17, s18
	v_mov_b32_e32 v18, s19
	s_clause 0x3
	global_store_b128 v[3:4], v[9:12], off
	global_store_b128 v[3:4], v[15:18], off offset:16
	global_store_b128 v[3:4], v[15:18], off offset:32
	global_store_b128 v[3:4], v[15:18], off offset:48
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_161
; %bb.154:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	global_load_b64 v[11:12], v2, s[4:5] offset:32 glc
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	v_dual_mov_b32 v9, s8 :: v_dual_mov_b32 v10, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[14:15], s[8:9]
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s15, s14, 24
	s_mul_i32 s14, s14, 24
	s_add_i32 s15, s15, s11
	v_add_co_u32 v3, vcc_lo, v13, s14
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v14, vcc_lo
	s_mov_b32 s11, exec_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[9:12], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[11:12]
	s_cbranch_execz .LBB0_157
; %bb.155:                              ; %.preheader1.i.i.i14.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s14, 0
.LBB0_156:                              ; %.preheader1.i.i.i14
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, s9
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_156
.LBB0_157:                              ; %Flow268
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	global_load_b64 v[3:4], v2, s[4:5] offset:16
	s_mov_b32 s14, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v1, s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_159
; %bb.158:                              ;   in Loop: Header=BB0_1 Depth=1
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_159:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_161
; %bb.160:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s11, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_161:                              ; %Flow269
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_add_i32 s12, s12, s1
	v_add_co_u32 v1, vcc_lo, v13, s13
	v_add_co_ci_u32_e32 v4, vcc_lo, s12, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_162:                              ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_164
; %bb.163:                              ;   in Loop: Header=BB0_162 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_164:                              ;   in Loop: Header=BB0_162 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_166
; %bb.165:                              ;   in Loop: Header=BB0_162 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_167
.LBB0_166:                              ;   in Loop: Header=BB0_162 Depth=2
	s_mov_b32 s1, -1
.LBB0_167:                              ; %Flow263
                                        ;   in Loop: Header=BB0_162 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_162
; %bb.168:                              ;   in Loop: Header=BB0_1 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_172
; %bb.169:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[4:5] offset:40
	global_load_b64 v[11:12], v2, s[4:5] offset:24 glc
	global_load_b64 v[9:10], v2, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, s8
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v1, vcc_lo
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_and_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_172
; %bb.170:                              ; %.preheader.i.i.i13.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
.LBB0_171:                              ; %.preheader.i.i.i13
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[7:10], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_171
.LBB0_172:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, 3
	s_cbranch_scc0 .LBB0_1
; %bb.173:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelPPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 34
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kernelPPi, .Lfunc_end0-_Z6kernelPPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6648
; NumSgprs: 24
; NumVgprs: 34
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 34
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%d\n"
	.size	.str, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         88
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelPPi
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelPPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     34
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
