/* -*- mode: C; tab-width: 2; indent-tabs-mode: nil; -*- */

/*
 * This code has been contributed by the DARPA HPCS program.  Contact
 * David Koester <dkoester@mitre.org> or Bob Lucas <rflucas@isi.edu>
 * if you have questions.
 *
 *
 * GUPS (Giga UPdates per Second) is a measurement that profiles the memory
 * architecture of a system and is a measure of performance similar to MFLOPS.
 * The HPCS HPCchallenge RandomAccess benchmark is intended to exercise the
 * GUPS capability of a system, much like the LINPACK benchmark is intended to
 * exercise the MFLOPS capability of a computer.  In each case, we would
 * expect these benchmarks to achieve close to the "peak" capability of the
 * memory system. The extent of the similarities between RandomAccess and
 * LINPACK are limited to both benchmarks attempting to calculate a peak system
 * capability.
 *
 * GUPS is calculated by identifying the number of memory locations that can be
 * randomly updated in one second, divided by 1 billion (1e9). The term "randomly"
 * means that there is little relationship between one address to be updated and
 * the next, except that they occur in the space of one half the total system
 * memory.  An update is a read-modify-write operation on a table of 64-bit words.
 * An address is generated, the value at that address read from memory, modified
 * by an integer operation (add, and, or, xor) with a literal value, and that
 * new value is written back to memory.
 *
 * We are interested in knowing the GUPS performance of both entire systems and
 * system subcomponents --- e.g., the GUPS rating of a distributed memory
 * multiprocessor the GUPS rating of an SMP node, and the GUPS rating of a
 * single processor.  While there is typically a scaling of FLOPS with processor
 * count, a similar phenomenon may not always occur for GUPS.
 *
 * Select the memory size to be the power of two such that 2^n <= 1/2 of the
 * total memory.  Each CPU operates on its own address stream, and the single
 * table may be distributed among nodes. The distribution of memory to nodes
 * is left to the implementer.  A uniform data distribution may help balance
 * the workload, while non-uniform data distributions may simplify the
 * calculations that identify processor location by eliminating the requirement
 * for integer divides. A small (less than 1%) percentage of missed updates
 * are permitted.
 *
 * When implementing a benchmark that measures GUPS on a distributed memory
 * multiprocessor system, it may be required to define constraints as to how
 * far in the random address stream each node is permitted to "look ahead".
 * Likewise, it may be required to define a constraint as to the number of
 * update messages that can be stored before processing to permit multi-level
 * parallelism for those systems that support such a paradigm.  The limits on
 * "look ahead" and "stored updates" are being implemented to assure that the
 * benchmark meets the intent to profile memory architecture and not induce
 * significant artificial data locality. For the purpose of measuring GUPS,
 * we will stipulate that each thread is permitted to look ahead no more than
 * 1024 random address stream samples with the same number of update messages
 * stored before processing.
 *
 * The supplied MPI-1 code generates the input stream {A} on all processors
 * and the global table has been distributed as uniformly as possible to
 * balance the workload and minimize any Amdahl fraction.  This code does not
 * exploit "look-ahead".  Addresses are sent to the appropriate processor
 * where the table entry resides as soon as each address is calculated.
 * Updates are performed as addresses are received.  Each message is limited
 * to a single 64 bit long integer containing element ai from {A}.
 * Local offsets for T[ ] are extracted by the destination processor.
 *
 * If the number of processors is equal to a power of two, then the global
 * table can be distributed equally over the processors.  In addition, the
 * processor number can be determined from that portion of the input stream
 * that identifies the address into the global table by masking off log2(p)
 * bits in the address.
 *
 * If the number of processors is not equal to a power of two, then the global
 * table cannot be equally distributed between processors.  In the MPI-1
 * implementation provided, there has been an attempt to minimize the differences
 * in workloads and the largest difference in elements of T[ ] is one.  The
 * number of values in the input stream generated by each processor will be
 * related to the number of global table entries on each processor.
 *
 * The MPI-1 version of RandomAccess treats the potential instance where the
 * number of processors is a power of two as a special case, because of the
 * significant simplifications possible because processor location and local
 * offset can be determined by applying masks to the input stream values.
 * The non power of two case uses an integer division to determine the processor
 * location.  The integer division will be more costly in terms of machine
 * cycles to perform than the bit masking operations
 *
 * For additional information on the GUPS metric, the HPCchallenge RandomAccess
 * Benchmark,and the rules to run RandomAccess or modify it to optimize
 * performance -- see http://icl.cs.utk.edu/hpcc/
 *
 */

#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>

#define DEFAULT_LOGN 20
#define POLY 0x0000000000000007ULL

union benchtype {
  uint64_t u64;
  uint2 u32;
};

static __constant__ uint64_t c_m2[64];
static __device__ uint32_t d_error[1];

static __global__ void
d_init(size_t n, benchtype *t)
{
  for (ptrdiff_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
       i += gridDim.x * blockDim.x) {
    t[i].u64 = i;
  }
}

static __device__ uint64_t
d_starts(size_t n)
{
  if (n == 0) {
    return 1;
  }

  int i = 63 - __clzll(n);

  uint64_t ran = 2;
  while (i > 0) {
    uint64_t temp = 0;
    for (int j = 0; j < 64; j++) {
      if ((ran >> j) & 1) {
        temp ^= c_m2[j];
      }
    }
    ran = temp;
    i -= 1;
    if ((n >> i) & 1) {
      ran = (ran << 1) ^ ((int64_t) ran < 0 ? POLY : 0);
    }
  }

  return ran;
}

enum atomictype_t {
  ATOMICTYPE_CAS,
  ATOMICTYPE_XOR,
};

template<atomictype_t ATOMICTYPE>
__global__ void
d_bench(size_t n, benchtype *t)
{
  size_t num_threads = gridDim.x * blockDim.x;
  size_t thread_num = blockIdx.x * blockDim.x + threadIdx.x;
  size_t start = thread_num * 4 * n / num_threads;
  size_t end = (thread_num + 1) * 4 * n / num_threads;
  benchtype ran;
  ran.u64 = d_starts(start);
  for (ptrdiff_t i = start; i < end; ++i) {
    ran.u64 = (ran.u64 << 1) ^ ((int64_t) ran.u64 < 0 ? POLY : 0);
    switch (ATOMICTYPE) {
    case ATOMICTYPE_CAS:
      unsigned long long int *address, old, assumed;
      address = (unsigned long long int *)&t[ran.u64 & (n - 1)].u64;
      old = *address;
      do {
        assumed = old;
        old = atomicCAS(address, assumed, assumed ^ ran.u64);
      } while  (assumed != old);
      break;
    case ATOMICTYPE_XOR:
      atomicXor(&t[ran.u64 & (n - 1)].u32.x, ran.u32.x);
      atomicXor(&t[ran.u64 & (n - 1)].u32.y, ran.u32.y);
      break;
    }
  }
}

static __global__ void
d_check(size_t n, benchtype *t)
{
  for (ptrdiff_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
       i += gridDim.x * blockDim.x) {
    if (t[i].u64 != i) {
      atomicAdd(d_error, 1);
    }
  }
}

static void
starts()
{
  uint64_t m2[64];
  uint64_t temp = 1;
  for (ptrdiff_t i = 0; i < 64; i++) {
    m2[i] = temp;
    temp = (temp << 1) ^ ((int64_t) temp < 0 ? POLY : 0);
    temp = (temp << 1) ^ ((int64_t) temp < 0 ? POLY : 0);
  }
  cudaMemcpyToSymbol(c_m2, m2, sizeof(m2));
}

int
main(int argc, char *argv[])
{
  size_t n = 0;
  if (argc > 1) {
    int logn = atoi(argv[1]);
    if (logn >= 0) {
      n = (size_t) 1 << logn;
    }
  }
  if (n <= 0) {
    n = (size_t) 1 << DEFAULT_LOGN;
  }
  printf("Total table size = %llu (%llu bytes.)\n",
         n, n * sizeof(uint64_t));

  starts();

  int ndev;
  cudaGetDeviceCount(&ndev);
  int dev = 0;
  if (argc > 2) {
    dev = atoi(argv[2]);
  }
  if (dev < 0 || dev >= ndev) {
    dev = 0;
  }
  cudaDeviceProp prop;
  cudaGetDeviceProperties(&prop, dev);
  cudaSetDevice(dev);
  printf("Using GPU %d of %d GPUs.\n", dev, ndev);
  printf("Warp size = %d.\n", prop.warpSize);
  printf("Multi-processor count = %d.\n", prop.multiProcessorCount);
  printf("Max threads per multi-processor = %d.\n",
         prop.maxThreadsPerMultiProcessor);

  benchtype *d_t;
  if (cudaMalloc((void **)&d_t, n * sizeof(benchtype)) != cudaSuccess) {
    fprintf(stderr, "Memory allocation failed!\n");
    exit(-1);
  }

  dim3 grid(prop.multiProcessorCount *
            (prop.maxThreadsPerMultiProcessor / prop.warpSize));
  dim3 thread(prop.warpSize);
  cudaEvent_t begin, end;
  cudaEventCreate(&begin);
  cudaEventCreate(&end);
  d_init<<<grid, thread>>>(n, d_t);
  cudaEventRecord(begin);
  cudaEventSynchronize(begin);
  d_bench<ATOMICTYPE_CAS><<<grid, thread>>>(n, d_t);
  cudaEventRecord(end);
  cudaEventSynchronize(end);

  float ms;
  cudaEventElapsedTime(&ms, begin, end);
  cudaEventDestroy(end);
  cudaEventDestroy(begin);
  double time = ms * 1.0e-3;
  printf("Elapsed time = %.6f seconds.\n", time);
  double gups = 4 * n / (double) ms * 1.0e-6;
  printf("Giga Updates per second = %.6f GUP/s.\n", gups);
  d_bench<ATOMICTYPE_CAS><<<grid, thread>>>(n, d_t);
  void *p_error;
  cudaGetSymbolAddress(&p_error, d_error);
  cudaMemset(d_error, 0, sizeof(uint32_t));
  d_check<<<grid, thread>>>(n, d_t);
  uint32_t h_error;
  cudaMemcpy(&h_error, p_error, sizeof(uint32_t), cudaMemcpyDeviceToHost);
  printf("Verification: Found %u errors.\n", h_error);

  cudaFree(d_t);
  return 0;
}

	.file	"tmpxft_002128a6_00000000-6_randomaccess.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL36__device_stub__Z7d_checkmP9benchtypemP9benchtype, @function
_ZL36__device_stub__Z7d_checkmP9benchtypemP9benchtype:
.LFB2058:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL7d_checkmP9benchtype(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_ZL36__device_stub__Z7d_checkmP9benchtypemP9benchtype, .-_ZL36__device_stub__Z7d_checkmP9benchtypemP9benchtype
	.type	_ZL7d_checkmP9benchtype, @function
_ZL7d_checkmP9benchtype:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_ZL36__device_stub__Z7d_checkmP9benchtypemP9benchtype
	.cfi_endproc
.LFE2059:
	.size	_ZL7d_checkmP9benchtype, .-_ZL7d_checkmP9benchtype
	.type	_ZL35__device_stub__Z6d_initmP9benchtypemP9benchtype, @function
_ZL35__device_stub__Z6d_initmP9benchtypemP9benchtype:
.LFB2056:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL6d_initmP9benchtype(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_ZL35__device_stub__Z6d_initmP9benchtypemP9benchtype, .-_ZL35__device_stub__Z6d_initmP9benchtypemP9benchtype
	.type	_ZL6d_initmP9benchtype, @function
_ZL6d_initmP9benchtype:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z6d_initmP9benchtypemP9benchtype
	.cfi_endproc
.LFE2057:
	.size	_ZL6d_initmP9benchtype, .-_ZL6d_initmP9benchtype
	.type	_Z30__wrapper__device_stub_d_benchIL12atomictype_t0EEvRmRP9benchtype.isra.0, @function
_Z30__wrapper__device_stub_d_benchIL12atomictype_t0EEvRmRP9benchtype.isra.0:
.LFB2183:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	leaq	24(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7d_benchIL12atomictype_t0EEvmP9benchtype(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L13:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2183:
	.size	_Z30__wrapper__device_stub_d_benchIL12atomictype_t0EEvRmRP9benchtype.isra.0, .-_Z30__wrapper__device_stub_d_benchIL12atomictype_t0EEvRmRP9benchtype.isra.0
	.section	.text._Z7d_benchIL12atomictype_t0EEvmP9benchtype,"axG",@progbits,_Z7d_benchIL12atomictype_t0EEvmP9benchtype,comdat
	.weak	_Z7d_benchIL12atomictype_t0EEvmP9benchtype
	.type	_Z7d_benchIL12atomictype_t0EEvmP9benchtype, @function
_Z7d_benchIL12atomictype_t0EEvmP9benchtype:
.LFB2110:
	.cfi_startproc
	endbr64
	jmp	_Z30__wrapper__device_stub_d_benchIL12atomictype_t0EEvRmRP9benchtype.isra.0
	.cfi_endproc
.LFE2110:
	.size	_Z7d_benchIL12atomictype_t0EEvmP9benchtype, .-_Z7d_benchIL12atomictype_t0EEvmP9benchtype
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Total table size = %llu (%llu bytes.)\n"
.LC1:
	.string	"Using GPU %d of %d GPUs.\n"
.LC2:
	.string	"Warp size = %d.\n"
.LC3:
	.string	"Multi-processor count = %d.\n"
.LC4:
	.string	"Max threads per multi-processor = %d.\n"
.LC5:
	.string	"Memory allocation failed!\n"
.LC7:
	.string	"Elapsed time = %.6f seconds.\n"
.LC9:
	.string	"Giga Updates per second = %.6f GUP/s.\n"
.LC10:
	.string	"Verification: Found %u errors.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%edi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	$1048576, %ebx
	subq	$1120, %rsp
	.cfi_def_cfa_offset 1168
	movq	%fs:40, %rax
	movq	%rax, 1112(%rsp)
	xorl	%eax, %eax
	decl	%edi
	jle	.L19
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movl	%eax, %ecx
	testl	%eax, %eax
	js	.L19
	movl	$1, %ebx
	salq	%cl, %rbx
.L19:
	movq	%rbx, %rdx
	movl	$2, %edi
	leaq	80(%rsp), %r13
	xorl	%eax, %eax
	leaq	0(,%rbx,8), %r14
	leaq	.LC0(%rip), %rsi
	movq	%r14, %rcx
	call	__printf_chk@PLT
	xorl	%ecx, %ecx
	movl	$1, %eax
.L22:
	movq	%rax, 0(%r13,%rcx,8)
	leaq	(%rax,%rax), %rdx
	sarq	$63, %rax
	incq	%rcx
	andl	$7, %eax
	xorq	%rax, %rdx
	leaq	(%rdx,%rdx), %rax
	sarq	$63, %rdx
	andl	$7, %edx
	xorq	%rdx, %rax
	cmpq	$64, %rcx
	jne	.L22
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movl	$512, %edx
	movq	%r13, %rsi
	leaq	_ZL4c_m2(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	leaq	12(%rsp), %rdi
	call	cudaGetDeviceCount@PLT
	cmpl	$2, %r12d
	jle	.L37
	movq	16(%rbp), %rdi
	call	atoi@PLT
	movl	%eax, %ebp
	testl	%eax, %eax
	jns	.L23
	jmp	.L39
.L37:
	xorl	%ebp, %ebp
.L23:
	cmpl	%ebp, 12(%rsp)
	jg	.L24
.L39:
	xorl	%ebp, %ebp
.L24:
	movl	%ebp, %esi
	movq	%r13, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	movl	%ebp, %edi
	call	cudaSetDevice@PLT
	movl	12(%rsp), %ecx
	movl	%ebp, %edx
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	388(%rsp), %edx
	leaq	.LC2(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	468(%rsp), %edx
	leaq	.LC3(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	704(%rsp), %edx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	24(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L25
	movq	stderr(%rip), %rdi
	leaq	.LC5(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L25:
	movl	704(%rsp), %eax
	movl	388(%rsp), %ecx
	leaq	32(%rsp), %rdi
	cltd
	movl	%ecx, 68(%rsp)
	idivl	%ecx
	imull	468(%rsp), %eax
	movl	%eax, 56(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 60(%rsp)
	movq	%rax, 72(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	76(%rsp), %ecx
	movl	64(%rsp), %esi
	xorl	%r9d, %r9d
	movq	68(%rsp), %rdx
	movq	56(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	24(%rsp), %rsi
	movq	%rbx, %rdi
	call	_ZL35__device_stub__Z6d_initmP9benchtypemP9benchtype
.L26:
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	76(%rsp), %ecx
	movl	64(%rsp), %esi
	xorl	%r9d, %r9d
	movq	68(%rsp), %rdx
	movq	56(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	24(%rsp), %rsi
	movq	%rbx, %rdi
	call	_Z30__wrapper__device_stub_d_benchIL12atomictype_t0EEvRmRP9benchtype.isra.0
.L27:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	cvtss2sd	16(%rsp), %xmm0
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	mulsd	.LC6(%rip), %xmm0
	movb	$1, %al
	call	__printf_chk@PLT
	movq	%rbx, %rax
	salq	$2, %rax
	js	.L28
	cvtsi2sdq	%rax, %xmm0
	jmp	.L29
.L28:
	shrq	%rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L29:
	cvtss2sd	16(%rsp), %xmm1
	divsd	%xmm1, %xmm0
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	mulsd	.LC8(%rip), %xmm0
	call	__printf_chk@PLT
	movl	76(%rsp), %ecx
	movl	64(%rsp), %esi
	xorl	%r9d, %r9d
	movq	68(%rsp), %rdx
	movq	56(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	24(%rsp), %rsi
	movq	%rbx, %rdi
	call	_Z30__wrapper__device_stub_d_benchIL12atomictype_t0EEvRmRP9benchtype.isra.0
.L30:
	leaq	_ZL7d_error(%rip), %rbp
	leaq	48(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaGetSymbolAddress@PLT
	xorl	%esi, %esi
	movl	$4, %edx
	movq	%rbp, %rdi
	call	cudaMemset@PLT
	movl	76(%rsp), %ecx
	movl	64(%rsp), %esi
	xorl	%r9d, %r9d
	movq	68(%rsp), %rdx
	movq	56(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	movq	24(%rsp), %rsi
	movq	%rbx, %rdi
	call	_ZL36__device_stub__Z7d_checkmP9benchtypemP9benchtype
.L31:
	movq	48(%rsp), %rsi
	leaq	20(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	20(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC10(%rip), %rsi
	call	__printf_chk@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	1112(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$1120, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z7d_benchIL12atomictype_t0EEvmP9benchtype"
.LC12:
	.string	"_Z7d_checkmP9benchtype"
.LC13:
	.string	"_Z6d_initmP9benchtype"
.LC14:
	.string	"c_m2"
.LC15:
	.string	"d_error"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7d_benchIL12atomictype_t0EEvmP9benchtype(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL7d_checkmP9benchtype(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL6d_initmP9benchtype(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movl	$512, %r9d
	leaq	_ZL4c_m2(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL7d_error(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2063:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL7d_error
	.comm	_ZL7d_error,4,4
	.local	_ZL4c_m2
	.comm	_ZL4c_m2,512,32
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC6:
	.long	-755914244
	.long	1062232653
	.align 8
.LC8:
	.long	-1598689907
	.long	1051772663
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* -*- mode: C; tab-width: 2; indent-tabs-mode: nil; -*- */

/*
 * This code has been contributed by the DARPA HPCS program.  Contact
 * David Koester <dkoester@mitre.org> or Bob Lucas <rflucas@isi.edu>
 * if you have questions.
 *
 *
 * GUPS (Giga UPdates per Second) is a measurement that profiles the memory
 * architecture of a system and is a measure of performance similar to MFLOPS.
 * The HPCS HPCchallenge RandomAccess benchmark is intended to exercise the
 * GUPS capability of a system, much like the LINPACK benchmark is intended to
 * exercise the MFLOPS capability of a computer.  In each case, we would
 * expect these benchmarks to achieve close to the "peak" capability of the
 * memory system. The extent of the similarities between RandomAccess and
 * LINPACK are limited to both benchmarks attempting to calculate a peak system
 * capability.
 *
 * GUPS is calculated by identifying the number of memory locations that can be
 * randomly updated in one second, divided by 1 billion (1e9). The term "randomly"
 * means that there is little relationship between one address to be updated and
 * the next, except that they occur in the space of one half the total system
 * memory.  An update is a read-modify-write operation on a table of 64-bit words.
 * An address is generated, the value at that address read from memory, modified
 * by an integer operation (add, and, or, xor) with a literal value, and that
 * new value is written back to memory.
 *
 * We are interested in knowing the GUPS performance of both entire systems and
 * system subcomponents --- e.g., the GUPS rating of a distributed memory
 * multiprocessor the GUPS rating of an SMP node, and the GUPS rating of a
 * single processor.  While there is typically a scaling of FLOPS with processor
 * count, a similar phenomenon may not always occur for GUPS.
 *
 * Select the memory size to be the power of two such that 2^n <= 1/2 of the
 * total memory.  Each CPU operates on its own address stream, and the single
 * table may be distributed among nodes. The distribution of memory to nodes
 * is left to the implementer.  A uniform data distribution may help balance
 * the workload, while non-uniform data distributions may simplify the
 * calculations that identify processor location by eliminating the requirement
 * for integer divides. A small (less than 1%) percentage of missed updates
 * are permitted.
 *
 * When implementing a benchmark that measures GUPS on a distributed memory
 * multiprocessor system, it may be required to define constraints as to how
 * far in the random address stream each node is permitted to "look ahead".
 * Likewise, it may be required to define a constraint as to the number of
 * update messages that can be stored before processing to permit multi-level
 * parallelism for those systems that support such a paradigm.  The limits on
 * "look ahead" and "stored updates" are being implemented to assure that the
 * benchmark meets the intent to profile memory architecture and not induce
 * significant artificial data locality. For the purpose of measuring GUPS,
 * we will stipulate that each thread is permitted to look ahead no more than
 * 1024 random address stream samples with the same number of update messages
 * stored before processing.
 *
 * The supplied MPI-1 code generates the input stream {A} on all processors
 * and the global table has been distributed as uniformly as possible to
 * balance the workload and minimize any Amdahl fraction.  This code does not
 * exploit "look-ahead".  Addresses are sent to the appropriate processor
 * where the table entry resides as soon as each address is calculated.
 * Updates are performed as addresses are received.  Each message is limited
 * to a single 64 bit long integer containing element ai from {A}.
 * Local offsets for T[ ] are extracted by the destination processor.
 *
 * If the number of processors is equal to a power of two, then the global
 * table can be distributed equally over the processors.  In addition, the
 * processor number can be determined from that portion of the input stream
 * that identifies the address into the global table by masking off log2(p)
 * bits in the address.
 *
 * If the number of processors is not equal to a power of two, then the global
 * table cannot be equally distributed between processors.  In the MPI-1
 * implementation provided, there has been an attempt to minimize the differences
 * in workloads and the largest difference in elements of T[ ] is one.  The
 * number of values in the input stream generated by each processor will be
 * related to the number of global table entries on each processor.
 *
 * The MPI-1 version of RandomAccess treats the potential instance where the
 * number of processors is a power of two as a special case, because of the
 * significant simplifications possible because processor location and local
 * offset can be determined by applying masks to the input stream values.
 * The non power of two case uses an integer division to determine the processor
 * location.  The integer division will be more costly in terms of machine
 * cycles to perform than the bit masking operations
 *
 * For additional information on the GUPS metric, the HPCchallenge RandomAccess
 * Benchmark,and the rules to run RandomAccess or modify it to optimize
 * performance -- see http://icl.cs.utk.edu/hpcc/
 *
 */


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>

#define DEFAULT_LOGN 20
#define POLY 0x0000000000000007ULL

union benchtype {
  uint64_t u64;
  uint2 u32;
};

static __constant__ uint64_t c_m2[64];
static __device__ uint32_t d_error[1];

static __global__ void
d_init(size_t n, benchtype *t)
{
  for (ptrdiff_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
       i += gridDim.x * blockDim.x) {
    t[i].u64 = i;
  }
}

static __device__ uint64_t
d_starts(size_t n)
{
  if (n == 0) {
    return 1;
  }

  int i = 63 - __clzll(n);

  uint64_t ran = 2;
  while (i > 0) {
    uint64_t temp = 0;
    for (int j = 0; j < 64; j++) {
      if ((ran >> j) & 1) {
        temp ^= c_m2[j];
      }
    }
    ran = temp;
    i -= 1;
    if ((n >> i) & 1) {
      ran = (ran << 1) ^ ((int64_t) ran < 0 ? POLY : 0);
    }
  }

  return ran;
}

enum atomictype_t {
  ATOMICTYPE_CAS,
  ATOMICTYPE_XOR,
};

template<atomictype_t ATOMICTYPE>
__global__ void
d_bench(size_t n, benchtype *t)
{
  size_t num_threads = gridDim.x * blockDim.x;
  size_t thread_num = blockIdx.x * blockDim.x + threadIdx.x;
  size_t start = thread_num * 4 * n / num_threads;
  size_t end = (thread_num + 1) * 4 * n / num_threads;
  benchtype ran;
  ran.u64 = d_starts(start);
  for (ptrdiff_t i = start; i < end; ++i) {
    ran.u64 = (ran.u64 << 1) ^ ((int64_t) ran.u64 < 0 ? POLY : 0);
    switch (ATOMICTYPE) {
    case ATOMICTYPE_CAS:
      unsigned long long int *address, old, assumed;
      address = (unsigned long long int *)&t[ran.u64 & (n - 1)].u64;
      old = *address;
      do {
        assumed = old;
        old = atomicCAS(address, assumed, assumed ^ ran.u64);
      } while  (assumed != old);
      break;
    case ATOMICTYPE_XOR:
      atomicXor(&t[ran.u64 & (n - 1)].u32.x, ran.u32.x);
      atomicXor(&t[ran.u64 & (n - 1)].u32.y, ran.u32.y);
      break;
    }
  }
}

static __global__ void
d_check(size_t n, benchtype *t)
{
  for (ptrdiff_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
       i += gridDim.x * blockDim.x) {
    if (t[i].u64 != i) {
      atomicAdd(d_error, 1);
    }
  }
}

static void
starts()
{
  uint64_t m2[64];
  uint64_t temp = 1;
  for (ptrdiff_t i = 0; i < 64; i++) {
    m2[i] = temp;
    temp = (temp << 1) ^ ((int64_t) temp < 0 ? POLY : 0);
    temp = (temp << 1) ^ ((int64_t) temp < 0 ? POLY : 0);
  }
  hipMemcpyToSymbol(HIP_SYMBOL(c_m2), m2, sizeof(m2));
}

int
main(int argc, char *argv[])
{
  size_t n = 0;
  if (argc > 1) {
    int logn = atoi(argv[1]);
    if (logn >= 0) {
      n = (size_t) 1 << logn;
    }
  }
  if (n <= 0) {
    n = (size_t) 1 << DEFAULT_LOGN;
  }
  printf("Total table size = %llu (%llu bytes.)\n",
         n, n * sizeof(uint64_t));

  starts();

  int ndev;
  hipGetDeviceCount(&ndev);
  int dev = 0;
  if (argc > 2) {
    dev = atoi(argv[2]);
  }
  if (dev < 0 || dev >= ndev) {
    dev = 0;
  }
  hipDeviceProp_t prop;
  hipGetDeviceProperties(&prop, dev);
  hipSetDevice(dev);
  printf("Using GPU %d of %d GPUs.\n", dev, ndev);
  printf("Warp size = %d.\n", prop.warpSize);
  printf("Multi-processor count = %d.\n", prop.multiProcessorCount);
  printf("Max threads per multi-processor = %d.\n",
         prop.maxThreadsPerMultiProcessor);

  benchtype *d_t;
  if (hipMalloc((void **)&d_t, n * sizeof(benchtype)) != hipSuccess) {
    fprintf(stderr, "Memory allocation failed!\n");
    exit(-1);
  }

  dim3 grid(prop.multiProcessorCount *
            (prop.maxThreadsPerMultiProcessor / prop.warpSize));
  dim3 thread(prop.warpSize);
  hipEvent_t begin, end;
  hipEventCreate(&begin);
  hipEventCreate(&end);
  d_init<<<grid, thread>>>(n, d_t);
  hipEventRecord(begin);
  hipEventSynchronize(begin);
  d_bench<ATOMICTYPE_CAS><<<grid, thread>>>(n, d_t);
  hipEventRecord(end);
  hipEventSynchronize(end);

  float ms;
  hipEventElapsedTime(&ms, begin, end);
  hipEventDestroy(end);
  hipEventDestroy(begin);
  double time = ms * 1.0e-3;
  printf("Elapsed time = %.6f seconds.\n", time);
  double gups = 4 * n / (double) ms * 1.0e-6;
  printf("Giga Updates per second = %.6f GUP/s.\n", gups);
  d_bench<ATOMICTYPE_CAS><<<grid, thread>>>(n, d_t);
  void *p_error;
  hipGetSymbolAddress(&p_error, HIP_SYMBOL(d_error));
  hipMemset(d_error, 0, sizeof(uint32_t));
  d_check<<<grid, thread>>>(n, d_t);
  uint32_t h_error;
  hipMemcpy(&h_error, p_error, sizeof(uint32_t), hipMemcpyDeviceToHost);
  printf("Verification: Found %u errors.\n", h_error);

  hipFree(d_t);
  return 0;
}

	.text
	.file	"randomaccess.hip"
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI0_0:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
.LCPI0_3:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI0_1:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI0_2:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$1520, %rsp                     # imm = 0x5F0
	.cfi_def_cfa_offset 1568
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r15
	movl	%edi, %ebp
	movl	$1048576, %ebx                  # imm = 0x100000
	cmpl	$2, %edi
	jl	.LBB0_3
# %bb.1:
	movq	8(%r15), %rdi
	callq	atoi
	testl	%eax, %eax
	js	.LBB0_3
# %bb.2:
	movl	$1, %ebx
	movl	%eax, %ecx
	shlq	%cl, %rbx
.LBB0_3:                                # %.thread
	leaq	(,%rbx,8), %r14
	xorl	%r12d, %r12d
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$1, %eax
.LBB0_4:                                # =>This Inner Loop Header: Depth=1
	movq	%rax, 48(%rsp,%r12,8)
	leaq	(%rax,%rax), %rcx
	sarq	$63, %rax
	andl	$7, %eax
	xorq	%rcx, %rax
	addq	%rax, %rax
	sarq	$63, %rcx
	andl	$7, %ecx
	xorq	%rcx, %rax
	incq	%r12
	cmpq	$64, %r12
	jne	.LBB0_4
# %bb.5:                                # %_ZL6startsv.exit
	xorl	%r12d, %r12d
	leaq	48(%rsp), %rsi
	movl	$_ZL4c_m2, %edi
	movl	$512, %edx                      # imm = 0x200
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	leaq	12(%rsp), %rdi
	callq	hipGetDeviceCount
	movl	$0, %eax
	cmpl	$3, %ebp
	jl	.LBB0_7
# %bb.6:
	movq	16(%r15), %rdi
	callq	atoi
.LBB0_7:
	cmpl	12(%rsp), %eax
	movl	$0, %ebp
	cmovll	%eax, %ebp
	testl	%eax, %eax
	cmovsl	%r12d, %ebp
	leaq	48(%rsp), %r15
	movq	%r15, %rdi
	movl	%ebp, %esi
	callq	hipGetDevicePropertiesR0600
	movl	%ebp, %edi
	callq	hipSetDevice
	movl	12(%rsp), %edx
	movl	$.L.str.1, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	movl	308(%r15), %esi
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movl	388(%r15), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movl	624(%r15), %esi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movq	%rsp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB0_17
# %bb.8:
	movl	356(%rsp), %r14d
	movl	672(%rsp), %eax
	cltd
	idivl	%r14d
	movl	%eax, %r15d
	imull	436(%rsp), %r15d
	btsq	$32, %r15
	btsq	$32, %r14
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_10
# %bb.9:
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	callq	_ZL21__device_stub__d_initmP9benchtype
.LBB0_10:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_12
# %bb.11:
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	callq	_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype
.LBB0_12:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	44(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	cvtss2sd	(%r12), %xmm0
	mulsd	.LCPI0_0(%rip), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	leaq	(,%rbx,4), %rax
	movq	%rax, %xmm1
	punpckldq	.LCPI0_1(%rip), %xmm1   # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	subpd	.LCPI0_2(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	cvtss2sd	(%r12), %xmm2
	addsd	%xmm1, %xmm0
	divsd	%xmm2, %xmm0
	mulsd	.LCPI0_3(%rip), %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_14
# %bb.13:
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	callq	_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype
.LBB0_14:
	leaq	32(%rsp), %rdi
	movl	$_ZL7d_error, %esi
	callq	hipGetSymbolAddress
	movl	$_ZL7d_error, %edi
	movl	$4, %edx
	xorl	%esi, %esi
	callq	hipMemset
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_16
# %bb.15:
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	callq	_ZL22__device_stub__d_checkmP9benchtype
.LBB0_16:
	movq	32(%rsp), %rsi
	leaq	40(%rsp), %rbx
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	(%rbx), %esi
	movl	$.L.str.8, %edi
	xorl	%eax, %eax
	callq	printf
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$1520, %rsp                     # imm = 0x5F0
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_17:
	.cfi_def_cfa_offset 1568
	movq	stderr(%rip), %rcx
	movl	$.L.str.5, %edi
	movl	$26, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.type	_ZL21__device_stub__d_initmP9benchtype,@function # -- Begin function _ZL21__device_stub__d_initmP9benchtype
_ZL21__device_stub__d_initmP9benchtype: # @_ZL21__device_stub__d_initmP9benchtype
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL6d_initmP9benchtype, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZL21__device_stub__d_initmP9benchtype, .Lfunc_end1-_ZL21__device_stub__d_initmP9benchtype
	.cfi_endproc
                                        # -- End function
	.section	.text._Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype,"axG",@progbits,_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype,comdat
	.weak	_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype # -- Begin function _Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype
	.type	_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype,@function
_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype: # @_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7d_benchIL12atomictype_t0EEvmP9benchtype, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype, .Lfunc_end2-_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype
	.cfi_endproc
                                        # -- End function
	.text
	.type	_ZL22__device_stub__d_checkmP9benchtype,@function # -- Begin function _ZL22__device_stub__d_checkmP9benchtype
_ZL22__device_stub__d_checkmP9benchtype: # @_ZL22__device_stub__d_checkmP9benchtype
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL7d_checkmP9benchtype, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZL22__device_stub__d_checkmP9benchtype, .Lfunc_end3-_ZL22__device_stub__d_checkmP9benchtype
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL6d_initmP9benchtype, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL7d_checkmP9benchtype, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7d_benchIL12atomictype_t0EEvmP9benchtype, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$_ZL4c_m2, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$512, %r9d                      # imm = 0x200
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$_ZL7d_error, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Total table size = %llu (%llu bytes.)\n"
	.size	.L.str, 39

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Using GPU %d of %d GPUs.\n"
	.size	.L.str.1, 26

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Warp size = %d.\n"
	.size	.L.str.2, 17

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Multi-processor count = %d.\n"
	.size	.L.str.3, 29

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Max threads per multi-processor = %d.\n"
	.size	.L.str.4, 39

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Memory allocation failed!\n"
	.size	.L.str.5, 27

	.type	_ZL6d_initmP9benchtype,@object  # @_ZL6d_initmP9benchtype
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL6d_initmP9benchtype:
	.quad	_ZL21__device_stub__d_initmP9benchtype
	.size	_ZL6d_initmP9benchtype, 8

	.type	_Z7d_benchIL12atomictype_t0EEvmP9benchtype,@object # @_Z7d_benchIL12atomictype_t0EEvmP9benchtype
	.section	.rodata._Z7d_benchIL12atomictype_t0EEvmP9benchtype,"aG",@progbits,_Z7d_benchIL12atomictype_t0EEvmP9benchtype,comdat
	.weak	_Z7d_benchIL12atomictype_t0EEvmP9benchtype
	.p2align	3, 0x0
_Z7d_benchIL12atomictype_t0EEvmP9benchtype:
	.quad	_Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype
	.size	_Z7d_benchIL12atomictype_t0EEvmP9benchtype, 8

	.type	.L.str.6,@object                # @.str.6
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.6:
	.asciz	"Elapsed time = %.6f seconds.\n"
	.size	.L.str.6, 30

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Giga Updates per second = %.6f GUP/s.\n"
	.size	.L.str.7, 39

	.type	_ZL7d_error,@object             # @_ZL7d_error
	.local	_ZL7d_error
	.comm	_ZL7d_error,4,4
	.type	_ZL7d_checkmP9benchtype,@object # @_ZL7d_checkmP9benchtype
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL7d_checkmP9benchtype:
	.quad	_ZL22__device_stub__d_checkmP9benchtype
	.size	_ZL7d_checkmP9benchtype, 8

	.type	.L.str.8,@object                # @.str.8
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.8:
	.asciz	"Verification: Found %u errors.\n"
	.size	.L.str.8, 32

	.type	_ZL4c_m2,@object                # @_ZL4c_m2
	.local	_ZL4c_m2
	.comm	_ZL4c_m2,512,16
	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_ZL6d_initmP9benchtype"
	.size	.L__unnamed_1, 23

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZL7d_checkmP9benchtype"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7d_benchIL12atomictype_t0EEvmP9benchtype"
	.size	.L__unnamed_3, 43

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZL4c_m2"
	.size	.L__unnamed_4, 9

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_ZL7d_error"
	.size	.L__unnamed_5, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZL21__device_stub__d_initmP9benchtype
	.addrsig_sym _Z22__device_stub__d_benchIL12atomictype_t0EEvmP9benchtype
	.addrsig_sym _ZL22__device_stub__d_checkmP9benchtype
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZL6d_initmP9benchtype
	.addrsig_sym _Z7d_benchIL12atomictype_t0EEvmP9benchtype
	.addrsig_sym _ZL7d_error
	.addrsig_sym _ZL7d_checkmP9benchtype
	.addrsig_sym _ZL4c_m2
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL6d_initmP9benchtype,"axG",@progbits,_ZL6d_initmP9benchtype,comdat
	.globl	_ZL6d_initmP9benchtype          ; -- Begin function _ZL6d_initmP9benchtype
	.p2align	8
	.type	_ZL6d_initmP9benchtype,@function
_ZL6d_initmP9benchtype:                 ; @_ZL6d_initmP9benchtype
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s0, s0, 16
	s_addc_u32 s1, s1, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s0, s[0:1], 0x0
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[2:3], 3
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	global_store_b64 v[3:4], v[1:2], off
	v_add_co_u32 v1, vcc_lo, v1, s2
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	v_add_co_u32 v3, s0, v3, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[1:2]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow13
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL6d_initmP9benchtype
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL6d_initmP9benchtype,"axG",@progbits,_ZL6d_initmP9benchtype,comdat
.Lfunc_end0:
	.size	_ZL6d_initmP9benchtype, .Lfunc_end0-_ZL6d_initmP9benchtype
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL7d_checkmP9benchtype,"axG",@progbits,_ZL7d_checkmP9benchtype,comdat
	.globl	_ZL7d_checkmP9benchtype         ; -- Begin function _ZL7d_checkmP9benchtype
	.p2align	8
	.type	_ZL7d_checkmP9benchtype,@function
_ZL7d_checkmP9benchtype:                ; @_ZL7d_checkmP9benchtype
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s0, s0, 16
	s_addc_u32 s1, s1, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB1_6
; %bb.1:                                ; %.lr.ph
	s_load_b32 s0, s[0:1], 0x0
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_mov_b32_e32 v0, v1
	v_mov_b32_e32 v1, v2
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[2:3], 3
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[5:6], v[3:4], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[0:1], v[5:6]
	s_cbranch_execz .LBB1_5
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v5, s1, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_and_b32 s8, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s8
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, _ZL7d_error@gotpcrel32@lo+4
	s_addc_u32 s9, s9, _ZL7d_error@gotpcrel32@hi+12
	s_bcnt1_i32_b32 s1, s1
	s_load_b64 s[8:9], s[8:9], 0x0
	v_mov_b32_e32 v5, s1
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u32 v2, v5, s[8:9]
.LBB1_5:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v0, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v3, s0, v3, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[0:1]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_2
.LBB1_6:                                ; %Flow14
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL7d_checkmP9benchtype
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL7d_checkmP9benchtype,"axG",@progbits,_ZL7d_checkmP9benchtype,comdat
.Lfunc_end1:
	.size	_ZL7d_checkmP9benchtype, .Lfunc_end1-_ZL7d_checkmP9benchtype
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._Z7d_benchIL12atomictype_t0EEvmP9benchtype,"axG",@progbits,_Z7d_benchIL12atomictype_t0EEvmP9benchtype,comdat
	.protected	_Z7d_benchIL12atomictype_t0EEvmP9benchtype ; -- Begin function _Z7d_benchIL12atomictype_t0EEvmP9benchtype
	.globl	_Z7d_benchIL12atomictype_t0EEvmP9benchtype
	.p2align	8
	.type	_Z7d_benchIL12atomictype_t0EEvmP9benchtype,@function
_Z7d_benchIL12atomictype_t0EEvmP9benchtype: ; @_Z7d_benchIL12atomictype_t0EEvmP9benchtype
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s3, s8
	v_cvt_f32_u32_e32 v1, s2
	s_sub_u32 s3, 0, s2
	s_subb_u32 s9, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e64 v1, 0, 0x4f800000
	v_rcp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, 0xcf800000, v2
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, s3, v2
	v_mul_hi_u32 v4, s3, v1
	v_mul_lo_u32 v5, s9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_mul_lo_u32 v4, s3, v1
	v_add_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v1, v4
	v_mul_lo_u32 v6, v1, v3
	v_mul_hi_u32 v7, v1, v3
	v_mul_hi_u32 v8, v2, v4
	v_mul_lo_u32 v4, v2, v4
	v_mul_hi_u32 v9, v2, v3
	v_mul_lo_u32 v3, v2, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v1, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, v2, v4, vcc_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v0, s3, v5
	v_mul_lo_u32 v4, s3, v6
	v_mul_lo_u32 v7, s9, v5
	v_mul_lo_u32 v8, s3, v5
	s_mov_b32 s3, 0
	v_mad_u64_u32 v[2:3], null, v1, s4, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v0, v0, v4
	v_mul_hi_u32 v9, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v0, v3 :: v_dual_add_nc_u32 v7, v0, v7
	v_mul_lo_u32 v10, v5, v7
	v_mul_hi_u32 v11, v5, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v1, s5, v[0:1]
	v_mul_lo_u32 v1, v6, v8
	v_mul_hi_u32 v0, v6, v8
	v_mul_hi_u32 v4, v6, v7
	v_mul_lo_u32 v7, v6, v7
	v_add_co_u32 v8, vcc_lo, v9, v10
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo
	v_alignbit_b32 v10, v3, v2, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, v8, v1
	v_add_co_ci_u32_e32 v0, vcc_lo, v9, v0, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v0, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v11, v0, v8
	v_mad_u64_u32 v[4:5], null, v10, v8, 0
	v_mad_u64_u32 v[2:3], null, v0, v9, 0
	v_mad_u64_u32 v[6:7], null, v10, v9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v11, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v2, vcc_lo, v3, v5, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s2, v8, 0
	v_mad_u64_u32 v[4:5], null, s2, v6, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v2, vcc_lo, v0, v2
	v_sub_co_ci_u32_e32 v3, vcc_lo, v10, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v4, vcc_lo, v2, s2
	v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s2, v4
	v_cmp_eq_u32_e64 s0, 0, v3
	v_cndmask_b32_e64 v4, 0, -1, vcc_lo
	v_add_co_u32 v7, vcc_lo, v8, 2
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, -1, v2, s0
	v_cndmask_b32_e32 v4, -1, v4, vcc_lo
	v_add_co_u32 v5, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v10, v9 :: v_dual_cndmask_b32 v4, v5, v7
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_dual_cndmask_b32 v5, v6, v3 :: v_dual_mov_b32 v6, 1
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v7, 0 :: v_dual_cndmask_b32 v4, v8, v4
	v_cmpx_le_u64_e64 s[2:3], v[0:1]
	s_cbranch_execz .LBB2_12
; %bb.1:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v2, v4
	v_clz_i32_u32_e32 v3, v5
	v_mov_b32_e32 v6, 2
	s_mov_b32 s11, exec_lo
	v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v2, 32, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v2, v2, v3
	v_xor_b32_e32 v9, 63, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v9
	s_cbranch_execz .LBB2_11
; %bb.2:                                ; %.preheader.i.preheader
	v_mov_b32_e32 v6, 2
	v_mov_b32_e32 v7, 0
	s_mov_b32 s12, 0
.LBB2_3:                                ; %.preheader.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _ZL4c_m2@gotpcrel32@lo+4
	s_addc_u32 s1, s1, _ZL4c_m2@gotpcrel32@hi+12
	v_mov_b32_e32 v2, 0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v8, v9
	s_mov_b64 s[8:9], 0
.LBB2_4:                                ;   Parent Loop BB2_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[9:10], s8, v[6:7]
	s_mov_b32 s13, exec_lo
	v_and_b32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 1, v9
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_4 Depth=2
	s_waitcnt lgkmcnt(0)
	s_load_b64 s[14:15], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_xor_b32_e32 v3, s15, v3
	v_xor_b32_e32 v2, s14, v2
.LBB2_6:                                ;   in Loop: Header=BB2_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s8, 64
	s_cbranch_scc0 .LBB2_4
; %bb.7:                                ;   in Loop: Header=BB2_3 Depth=1
	v_add_nc_u32_e32 v9, -1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[6:7], v9, v[4:5]
	v_and_b32_e32 v6, 1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v6
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
	s_and_saveexec_b32 s0, vcc_lo
; %bb.8:                                ;   in Loop: Header=BB2_3 Depth=1
	v_ashrrev_i32_e32 v10, 31, v3
	v_lshlrev_b64 v[6:7], 1, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 7, v10
	v_xor_b32_e32 v6, v2, v6
; %bb.9:                                ;   in Loop: Header=BB2_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, 2, v8
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB2_3
; %bb.10:                               ; %Flow33
	s_or_b32 exec_lo, exec_lo, s12
.LBB2_11:                               ; %Flow34
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s11
.LBB2_12:                               ; %_ZL8d_startsm.exit
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s10
	v_cvt_f32_u32_e32 v2, s2
	s_lshl_b64 s[0:1], s[4:5], 2
	s_sub_u32 s8, 0, s2
	s_subb_u32 s9, 0, 0
	v_fmac_f32_e64 v2, 0, 0x4f800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x5f7ffffc, v2
	v_mul_f32_e32 v3, 0x2f800000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v3, v3
	v_fmac_f32_e32 v2, 0xcf800000, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v8, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, s8, v2
	v_mul_lo_u32 v10, s9, v2
	v_add_nc_u32_e32 v8, v9, v8
	v_mul_lo_u32 v9, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v10
	v_mul_hi_u32 v10, v2, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v11, v2, v8
	v_mul_hi_u32 v12, v2, v8
	v_mul_hi_u32 v13, v3, v9
	v_mul_lo_u32 v9, v3, v9
	v_mul_hi_u32 v14, v3, v8
	v_mul_lo_u32 v8, v3, v8
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v8, s8, v2
	v_mul_lo_u32 v10, s9, v2
	v_mul_lo_u32 v9, s8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v9
	v_mul_lo_u32 v9, s8, v2
	v_add_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v2, v9
	v_mul_lo_u32 v11, v2, v8
	v_mul_hi_u32 v12, v2, v8
	v_mul_hi_u32 v13, v3, v9
	v_mul_lo_u32 v9, v3, v9
	v_mul_hi_u32 v14, v3, v8
	v_mul_lo_u32 v8, v3, v8
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v10, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s0, v2, v8
	v_add_co_ci_u32_e64 v11, s0, v3, v9, s0
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v13, v10, v8
	v_mad_u64_u32 v[0:1], null, v10, v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, v12, v8, 0
	v_mad_u64_u32 v[8:9], null, v12, v11, 0
	v_add_co_u32 v0, vcc_lo, v13, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v0, vcc_lo, v1, v3, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, v0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
	v_mad_u64_u32 v[0:1], null, s2, v8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, s2, v9, v[1:2]
	v_sub_co_u32 v0, vcc_lo, v10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e32 v1, vcc_lo, v12, v2, vcc_lo
	v_sub_co_u32 v2, vcc_lo, v0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_cmp_eq_u32_e64 s0, 0, v1
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_add_co_u32 v10, vcc_lo, v8, 2
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v0
	v_cndmask_b32_e64 v0, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v0, -1, v0, s0
	v_cndmask_b32_e32 v2, -1, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v12, v11 :: v_dual_cndmask_b32 v2, v3, v10
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_dual_cndmask_b32 v9, v9, v1 :: v_dual_cndmask_b32 v8, v8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u64_e64 v[4:5], v[8:9]
	s_cbranch_execz .LBB2_17
; %bb.13:                               ; %.lr.ph
	s_add_u32 s0, s4, -1
	s_addc_u32 s1, s5, -1
.LBB2_14:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_15 Depth 2
	v_ashrrev_i32_e32 v0, 31, v7
	v_lshlrev_b64 v[6:7], 1, v[6:7]
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, 7, v0
	v_and_b32_e32 v1, s1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v0, v6
	v_and_b32_e32 v0, s0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v10, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
	global_load_b64 v[2:3], v[10:11], off
.LBB2_15:                               ;   Parent Loop BB2_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v1, v3, v7
	v_xor_b32_e32 v0, v2, v6
	global_atomic_cmpswap_b64 v[0:1], v[10:11], v[0:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[0:1]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB2_15
; %bb.16:                               ;   in Loop: Header=BB2_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_add_co_u32 v4, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u64_e32 vcc_lo, v[4:5], v[8:9]
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_14
.LBB2_17:                               ; %Flow32
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7d_benchIL12atomictype_t0EEvmP9benchtype
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z7d_benchIL12atomictype_t0EEvmP9benchtype,"axG",@progbits,_Z7d_benchIL12atomictype_t0EEvmP9benchtype,comdat
.Lfunc_end2:
	.size	_Z7d_benchIL12atomictype_t0EEvmP9benchtype, .Lfunc_end2-_Z7d_benchIL12atomictype_t0EEvmP9benchtype
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1992
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	_ZL7d_error,@object             ; @_ZL7d_error
	.section	.bss,"aw",@nobits
	.globl	_ZL7d_error
	.p2align	2, 0x0
_ZL7d_error:
	.zero	4
	.size	_ZL7d_error, 4

	.type	_ZL4c_m2,@object                ; @_ZL4c_m2
	.globl	_ZL4c_m2
	.p2align	4, 0x0
_ZL4c_m2:
	.zero	512
	.size	_ZL4c_m2, 512

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZL7d_error
	.addrsig_sym _ZL4c_m2
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL6d_initmP9benchtype
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL6d_initmP9benchtype.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL7d_checkmP9benchtype
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL7d_checkmP9benchtype.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7d_benchIL12atomictype_t0EEvmP9benchtype
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7d_benchIL12atomictype_t0EEvmP9benchtype.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
