#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <float.h>
#include "cuComplex.h"
#include "time.h"
#include "cuda_runtime.h"
#include <iostream>

using namespace std;

struct test
    {
        float vu[2];
        float w;
        float visibility_x;
        float visibility_y;
        float empt[3];
    } ;


__global__ void test(struct test * vis, int vis_entries, int vis_per_block, cuComplex *convFunc, 
                     int support, int sampling, int wplanes, float wpow2increment, cuComplex *output, 
                     int dim_row, int dim_col, float inc_row, float inc_col)
{
    __shared__ struct test2
    {
        struct test testing;
    } tt;

    support = support / 2;

    // Let's first see which visibility data shall be taken care of
    __shared__ float pos_y,pos_x;
    __shared__ int loc_y, loc_x;
    __shared__ int off_y, off_x;
    __shared__ int wplane;

    float tmp;
    cuComplex add;
    
     int begin = (blockIdx.y*vis_per_block);
     int end = begin + vis_per_block - 5;
     if (begin>=vis_entries) return;  //This block is useless
     if (end>=vis_entries) end = vis_entries - 1;
     
    for (int vis_no = begin; vis_no <= end; vis_no++)
    {
        __syncthreads();
        
        if ((threadIdx.x == 0) && (threadIdx.y == 0))
        {
            tt= *(struct test2*) (vis + vis_no);

        // We first find in which wplane point is
        wplane = (int) round(sqrtf(fabs(wpow2increment * tt.testing.w))); //still need to understand the +1 abd offset.. I beleive it is 0
        
        if ( wplane > (wplanes -1) ) wplane = wplanes - 1;

           pos_y=(tt.testing.vu[0] / inc_row) + __int2float_rz(dim_row / 2);
           pos_x=(tt.testing.vu[1] / inc_col) + __int2float_rz(dim_col / 2);
           loc_y = __float2int_rz(pos_y); 
           loc_x = __float2int_rz(pos_x); 
           off_y = __float2int_rz(__int2float_rz(loc_y-pos_y)* __int2float_rz(sampling));
           off_x = __float2int_rz(__int2float_rz(loc_x-pos_x)* __int2float_rz(sampling));
        }

        __syncthreads();

        if (((loc_y-support)<0) || ((loc_y+support)>(dim_row-1)) || ((loc_x-support)<0) || ((loc_x+support)>(dim_col-1)))
            continue;  /// out of grid 
       
        //continue;
        for (int iy = (-support + threadIdx.y); //*17
                      iy <= support;
                      iy += blockDim.y)
        {   
//            int ix_orig=(-support+threadIdx.x);
//            int ix=ix_orig;
//            ix -= (loc_x + ix - threadIdx.x) % 64; //Important 
            
            for (int  ix = (-support + threadIdx.x); //*17
                           ix <= support;
                           ix += blockDim.x)
            {
//                if (ix < ix_orig) continue;
               int newloc_y=loc_y+iy;
               int newloc_x=loc_x+ix;
                
                //newloc[0]=loc[0]+iy;
                //newloc[1]=loc[1]+ix;
                //loc_y+=iy;
                //loc_x+=ix;
                
                int poss=(newloc_y)*dim_col+newloc_x;
                // poss=0;
                //int iloc_y=(sampling*(iy+support))+(sampling-1)+off[0];
               // int iloc_x=(sampling*(ix+support/)+(sampling-1)+off[1];
                 int iloc_y=(off_y+(support))*sampling+(iy+support);
                 int iloc_x=(off_x+(support))*sampling+(ix+support);
                
                //REVIEW above.... worthed to do an interesting note
                //if ((iloc_x<0)||(iloc_y<0)) continue;
                
                int convplaneside=(support*2+1)*sampling-1;
                //if ((iloc_x>convplaneside)||(iloc_y>convplaneside)) continue;
                cuComplex addvalue;
                int pss2=wplane*convplaneside*convplaneside+(iloc_y*convplaneside+iloc_x);
             //   if (threadIdx.x>100000) printf("%d",pss2);
                //pss2-=(pss2-threadIdx.x)%32; // no real big difference
                //cuComplex wt=*(convFunc+ pss2);   //To change for convFunc //To CHECK... Do we expect complex values
                cuComplex wt; 
                wt.x=1.0f;
                wt.y=1.0f;
                addvalue.x = tt.testing.visibility_x * wt.x-tt.testing.visibility_y* wt.y;
                addvalue.y = tt.testing.visibility_y * wt.x+tt.testing.visibility_x* wt.y;  //can be improved
                add.x+=addvalue.x;
                add.y+=addvalue.y;
                (output+poss)->x=addvalue.x;
                (output+poss)->y=addvalue.y;
////                output[threadIdx.y * blockDim.x + threadIdx.x] = addvalue;
//                tmp+=addvalue.x+addvalue.y;
                
                
//               atomicAdd(&((output+poss)->x),addvalue.x);
//               atomicAdd(&((output+poss)->y),addvalue.y);
//                
//                
            }
        }
               
        //atomicAdd(&(output)->x,tmp);
    }

//     __syncthreads();
        if(threadIdx.x == 0 && threadIdx.y == 0)
     output[blockIdx.y].x=tmp; 
//           atomicAdd(&((output)->x),tmp);
//            atomicAdd(&((output)->y),add.y);
     
}


int main(int argc, char *argv[])
{
    float timestamp;
    float  *data;
    cuComplex* grid;
    cudaEvent_t event_start,event_stop;
        // Initialise
        cudaSetDevice(0);
	cudaThreadSetCacheConfig(cudaFuncCachePreferShared);        
        // Allocate and generate buffers
    cudaMalloc((void **) &data, 240000 * 8 * sizeof(float));
    cudaMalloc((void **) &grid, 2016* 2016 * sizeof(cuComplex));

    cudaMemset(data, 0, 240000 * 8 * sizeof(float));

    cudaEventCreate(&event_start);
        cudaEventCreate(&event_stop);
        cout <<"Allocation ready"<<endl;
    cudaEventRecord(event_start, 0);
    dim3 threadsPerBlock;
    dim3 blocks;
    int b=1000; 
     threadsPerBlock.x=32;
     threadsPerBlock.y=32;
     threadsPerBlock.z=1;
     blocks.x=1;
     blocks.y=24000;
     blocks.z=1;
    
   test<<<blocks,threadsPerBlock>>>
             ((struct test*)data, 
             240000,
             240000 / blocks.y,
          //   b_x, b_y,
             NULL,
             529,
             4,
             128,
             1.2,
             grid, 
             2016,2016,
             6.56984f,6.56984f
             );
  
        cudaEventRecord(event_stop, 0);
        cout << "Now waiting"<<endl;
        cout.flush();
        cudaEventSynchronize(event_stop);
  
        cudaEventElapsedTime(&timestamp, event_start, event_stop);
        printf("Calculated in %f\n", timestamp);
}

	.file	"tmpxft_00348987_00000000-6_imager.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3661:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3661:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z4testP4testiiP6float2iiifS2_iiffP4testiiP6float2iiifS2_iiff
	.type	_Z48__device_stub__Z4testP4testiiP6float2iiifS2_iiffP4testiiP6float2iiifS2_iiff, @function
_Z48__device_stub__Z4testP4testiiP6float2iiifS2_iiffP4testiiP6float2iiifS2_iiff:
.LFB3683:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	264(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 52(%rsp)
	leaq	92(%rsp), %rsi
	movl	%edx, 48(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	72(%rsp), %rcx
	movl	%r8d, 36(%rsp)
	movl	%r9d, 32(%rsp)
	movq	%rax, 16(%rsp)
	movss	%xmm0, 28(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z4testP4testiiP6float2iiifS2_iiff(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 272
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3683:
	.size	_Z48__device_stub__Z4testP4testiiP6float2iiifS2_iiffP4testiiP6float2iiifS2_iiff, .-_Z48__device_stub__Z4testP4testiiP6float2iiifS2_iiffP4testiiP6float2iiifS2_iiff
	.globl	_Z4testP4testiiP6float2iiifS2_iiff
	.type	_Z4testP4testiiP6float2iiifS2_iiff, @function
_Z4testP4testiiP6float2iiifS2_iiff:
.LFB3684:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z4testP4testiiP6float2iiifS2_iiffP4testiiP6float2iiifS2_iiff
	.cfi_endproc
.LFE3684:
	.size	_Z4testP4testiiP6float2iiifS2_iiff, .-_Z4testP4testiiP6float2iiifS2_iiff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Allocation ready"
.LC3:
	.string	"Now waiting"
.LC4:
	.string	"Calculated in %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3658:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	xorl	%edi, %edi
	leaq	_ZSt4cout(%rip), %rbx
	subq	$80, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	movl	$1, %edi
	call	cudaThreadSetCacheConfig@PLT
	leaq	16(%rsp), %rdi
	movl	$7680000, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$32514048, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$7680000, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	.LC0(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdx
	movl	$1, %esi
	movabsq	$103079215104001, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	$2016
	.cfi_def_cfa_offset 104
	movss	.LC1(%rip), %xmm2
	xorl	%ecx, %ecx
	movl	$4, %r9d
	pushq	$2016
	.cfi_def_cfa_offset 112
	movl	$529, %r8d
	movl	$10, %edx
	movss	.LC2(%rip), %xmm0
	pushq	40(%rsp)
	.cfi_def_cfa_offset 120
	movaps	%xmm2, %xmm1
	movl	$240000, %esi
	pushq	$128
	.cfi_def_cfa_offset 128
	movq	48(%rsp), %rdi
	call	_Z48__device_stub__Z4testP4testiiP6float2iiifS2_iiffP4testiiP6float2iiifS2_iiff
	addq	$32, %rsp
	.cfi_def_cfa_offset 96
.L9:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	%rbx, %rdi
	call	_ZNSo5flushEv@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rsi
	movq	40(%rsp), %rdx
	leaq	12(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$80, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3658:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z4testP4testiiP6float2iiifS2_iiff"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3686:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4testP4testiiP6float2iiifS2_iiff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3686:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1087519777
	.align 4
.LC2:
	.long	1067030938
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <float.h>
#include "hip/hip_complex.h"
#include "time.h"
#include "hip/hip_runtime.h"
#include <iostream>

using namespace std;

struct test
    {
        float vu[2];
        float w;
        float visibility_x;
        float visibility_y;
        float empt[3];
    } ;


__global__ void test(struct test * vis, int vis_entries, int vis_per_block, hipComplex *convFunc, 
                     int support, int sampling, int wplanes, float wpow2increment, hipComplex *output, 
                     int dim_row, int dim_col, float inc_row, float inc_col)
{
    __shared__ struct test2
    {
        struct test testing;
    } tt;

    support = support / 2;

    // Let's first see which visibility data shall be taken care of
    __shared__ float pos_y,pos_x;
    __shared__ int loc_y, loc_x;
    __shared__ int off_y, off_x;
    __shared__ int wplane;

    float tmp;
    hipComplex add;
    
     int begin = (blockIdx.y*vis_per_block);
     int end = begin + vis_per_block - 5;
     if (begin>=vis_entries) return;  //This block is useless
     if (end>=vis_entries) end = vis_entries - 1;
     
    for (int vis_no = begin; vis_no <= end; vis_no++)
    {
        __syncthreads();
        
        if ((threadIdx.x == 0) && (threadIdx.y == 0))
        {
            tt= *(struct test2*) (vis + vis_no);

        // We first find in which wplane point is
        wplane = (int) round(sqrtf(fabs(wpow2increment * tt.testing.w))); //still need to understand the +1 abd offset.. I beleive it is 0
        
        if ( wplane > (wplanes -1) ) wplane = wplanes - 1;

           pos_y=(tt.testing.vu[0] / inc_row) + __int2float_rz(dim_row / 2);
           pos_x=(tt.testing.vu[1] / inc_col) + __int2float_rz(dim_col / 2);
           loc_y = __float2int_rz(pos_y); 
           loc_x = __float2int_rz(pos_x); 
           off_y = __float2int_rz(__int2float_rz(loc_y-pos_y)* __int2float_rz(sampling));
           off_x = __float2int_rz(__int2float_rz(loc_x-pos_x)* __int2float_rz(sampling));
        }

        __syncthreads();

        if (((loc_y-support)<0) || ((loc_y+support)>(dim_row-1)) || ((loc_x-support)<0) || ((loc_x+support)>(dim_col-1)))
            continue;  /// out of grid 
       
        //continue;
        for (int iy = (-support + threadIdx.y); //*17
                      iy <= support;
                      iy += blockDim.y)
        {   
//            int ix_orig=(-support+threadIdx.x);
//            int ix=ix_orig;
//            ix -= (loc_x + ix - threadIdx.x) % 64; //Important 
            
            for (int  ix = (-support + threadIdx.x); //*17
                           ix <= support;
                           ix += blockDim.x)
            {
//                if (ix < ix_orig) continue;
               int newloc_y=loc_y+iy;
               int newloc_x=loc_x+ix;
                
                //newloc[0]=loc[0]+iy;
                //newloc[1]=loc[1]+ix;
                //loc_y+=iy;
                //loc_x+=ix;
                
                int poss=(newloc_y)*dim_col+newloc_x;
                // poss=0;
                //int iloc_y=(sampling*(iy+support))+(sampling-1)+off[0];
               // int iloc_x=(sampling*(ix+support/)+(sampling-1)+off[1];
                 int iloc_y=(off_y+(support))*sampling+(iy+support);
                 int iloc_x=(off_x+(support))*sampling+(ix+support);
                
                //REVIEW above.... worthed to do an interesting note
                //if ((iloc_x<0)||(iloc_y<0)) continue;
                
                int convplaneside=(support*2+1)*sampling-1;
                //if ((iloc_x>convplaneside)||(iloc_y>convplaneside)) continue;
                hipComplex addvalue;
                int pss2=wplane*convplaneside*convplaneside+(iloc_y*convplaneside+iloc_x);
             //   if (threadIdx.x>100000) printf("%d",pss2);
                //pss2-=(pss2-threadIdx.x)%32; // no real big difference
                //cuComplex wt=*(convFunc+ pss2);   //To change for convFunc //To CHECK... Do we expect complex values
                hipComplex wt; 
                wt.x=1.0f;
                wt.y=1.0f;
                addvalue.x = tt.testing.visibility_x * wt.x-tt.testing.visibility_y* wt.y;
                addvalue.y = tt.testing.visibility_y * wt.x+tt.testing.visibility_x* wt.y;  //can be improved
                add.x+=addvalue.x;
                add.y+=addvalue.y;
                (output+poss)->x=addvalue.x;
                (output+poss)->y=addvalue.y;
////                output[threadIdx.y * blockDim.x + threadIdx.x] = addvalue;
//                tmp+=addvalue.x+addvalue.y;
                
                
//               atomicAdd(&((output+poss)->x),addvalue.x);
//               atomicAdd(&((output+poss)->y),addvalue.y);
//                
//                
            }
        }
               
        //atomicAdd(&(output)->x,tmp);
    }

//     __syncthreads();
        if(threadIdx.x == 0 && threadIdx.y == 0)
     output[blockIdx.y].x=tmp; 
//           atomicAdd(&((output)->x),tmp);
//            atomicAdd(&((output)->y),add.y);
     
}


int main(int argc, char *argv[])
{
    float timestamp;
    float  *data;
    hipComplex* grid;
    hipEvent_t event_start,event_stop;
        // Initialise
        hipSetDevice(0);
	hipDeviceSetCacheConfig(hipFuncCachePreferShared);        
        // Allocate and generate buffers
    hipMalloc((void **) &data, 240000 * 8 * sizeof(float));
    hipMalloc((void **) &grid, 2016* 2016 * sizeof(hipComplex));

    hipMemset(data, 0, 240000 * 8 * sizeof(float));

    hipEventCreate(&event_start);
        hipEventCreate(&event_stop);
        cout <<"Allocation ready"<<endl;
    hipEventRecord(event_start, 0);
    dim3 threadsPerBlock;
    dim3 blocks;
    int b=1000; 
     threadsPerBlock.x=32;
     threadsPerBlock.y=32;
     threadsPerBlock.z=1;
     blocks.x=1;
     blocks.y=24000;
     blocks.z=1;
    
   test<<<blocks,threadsPerBlock>>>
             ((struct test*)data, 
             240000,
             240000 / blocks.y,
          //   b_x, b_y,
             NULL,
             529,
             4,
             128,
             1.2,
             grid, 
             2016,2016,
             6.56984f,6.56984f
             );
  
        hipEventRecord(event_stop, 0);
        cout << "Now waiting"<<endl;
        cout.flush();
        hipEventSynchronize(event_stop);
  
        hipEventElapsedTime(&timestamp, event_start, event_stop);
        printf("Calculated in %f\n", timestamp);
}

	.text
	.file	"imager.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff # -- Begin function _Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.type	_Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff,@function
_Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff: # @_Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	28(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	24(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	20(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	16(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r10, 88(%rbx)
	movq	%r11, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff, .Lfunc_end0-_Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x3f99999a                      # float 1.20000005
.LCPI1_1:
	.long	0x40d23c21                      # float 6.56983995
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	xorl	%edi, %edi
	callq	hipSetDevice
	movl	$1, %edi
	callq	hipDeviceSetCacheConfig
	leaq	24(%rsp), %rbx
	movl	$7680000, %esi                  # imm = 0x753000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$32514048, %esi                 # imm = 0x1F02000
	callq	hipMalloc
	movq	(%rbx), %rdi
	movl	$7680000, %edx                  # imm = 0x753000
	xorl	%esi, %esi
	callq	hipMemset
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movl	$_ZSt4cout, %r14d
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$16, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$103079215104001, %rdi          # imm = 0x5DC000000001
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	24(%rsp), %rdi
	movl	$2016, %eax                     # imm = 0x7E0
	movss	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movl	$240000, %esi                   # imm = 0x3A980
	movl	$10, %edx
	xorl	%ecx, %ecx
	movl	$529, %r8d                      # imm = 0x211
	movl	$4, %r9d
	movaps	%xmm1, %xmm2
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	$128
	.cfi_adjust_cfa_offset 8
	callq	_Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB1_2:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	callq	_ZNSo5flushEv
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff,@object # @_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.section	.rodata,"a",@progbits
	.globl	_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.p2align	3, 0x0
_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff:
	.quad	_Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.size	_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Allocation ready"
	.size	.L.str, 17

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Now waiting"
	.size	.L.str.1, 12

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Calculated in %f\n"
	.size	.L.str.2, 18

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff"
	.size	.L__unnamed_1, 52

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff ; -- Begin function _Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.globl	_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
	.p2align	8
	.type	_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff,@function
_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff: ; @_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s6, s15, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s6, s2
	s_cbranch_scc1 .LBB0_14
; %bb.1:
	s_add_i32 s3, s3, s6
	s_add_i32 s4, s2, -1
	s_add_i32 s3, s3, -5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s3, s2
	s_cselect_b32 s5, s3, s4
	s_cmp_gt_i32 s6, s5
	s_cbranch_scc1 .LBB0_14
; %bb.2:                                ; %.lr.ph115
	s_clause 0x2
	s_load_b128 s[8:11], s[0:1], 0x30
	s_load_b32 s2, s[0:1], 0x18
	s_load_b64 s[12:13], s[0:1], 0x28
	v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v2, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_load_b64 s[14:15], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v3, v2, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s8, 31
	s_lshr_b32 s4, s2, 31
	s_add_i32 s3, s8, s3
	s_add_i32 s2, s2, s4
	s_ashr_i32 s3, s3, 1
	s_ashr_i32 s18, s2, 1
	s_sub_i32 s2, 0, s3
	s_cmp_lt_i32 s8, -1
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v1, 0, 1, s4
	s_and_b32 s4, s4, exec_lo
	s_cselect_b32 s2, s2, s3
	s_clz_i32_u32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_min_u32 s3, s3, 32
	s_lshl_b32 s4, s3, 23
	s_lshl_b32 s3, s2, s3
	s_sub_i32 s4, 0x4f000000, s4
	s_cmp_lg_u32 s2, 0
	s_cselect_b32 s4, s4, 0
	s_lshr_b32 s2, s9, 31
	s_bfe_u32 s16, s3, 0x170008
	s_add_i32 s2, s9, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s7, s2, 1
	v_cmp_eq_u32_e64 s2, 0, v3
	s_sub_i32 s3, 0, s7
	s_cmp_lt_i32 s9, -1
	v_subrev_nc_u32_e32 v3, s18, v0
	s_cselect_b32 s17, -1, 0
	v_lshlrev_b32_e32 v0, 31, v1
	v_cndmask_b32_e64 v4, 0, 1, s17
	s_and_b32 s17, s17, exec_lo
	s_cselect_b32 s3, s3, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_clz_i32_u32 s7, s3
	v_lshlrev_b32_e32 v1, 31, v4
	s_min_u32 s7, s7, 32
	v_subrev_nc_u32_e32 v4, s18, v2
	s_lshl_b32 s17, s7, 23
	s_lshl_b32 s7, s3, s7
	s_sub_i32 s17, 0x4f000000, s17
	s_cmp_lg_u32 s3, 0
	v_or_b32_e32 v0, s4, v0
	s_cselect_b32 s3, s17, 0
	s_bfe_u32 s7, s7, 0x170008
	v_or_b32_e32 v1, s3, v1
	v_cmp_lt_i32_e64 s3, s18, v3
	v_cmp_ge_i32_e64 s4, s18, v4
	v_or_b32_e32 v5, s16, v0
	s_add_u32 s16, s0, 64
	v_or_b32_e32 v6, s7, v1
	s_addc_u32 s17, s1, 0
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
                                        ;       Child Loop BB0_10 Depth 3
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[20:21], s[6:7], 5
	s_add_u32 s20, s14, s20
	s_addc_u32 s21, s15, s21
	s_clause 0x1
	global_load_b128 v[8:11], v7, s[20:21]
	global_load_b128 v[12:15], v7, s[20:21] offset:16
	s_waitcnt vmcnt(1)
	ds_store_b128 v7, v[8:11]
	ds_load_b64 v[0:1], v7
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v2, null, s10, s10, v0
	v_div_scale_f32 v8, null, s11, s11, v1
	v_div_scale_f32 v17, vcc_lo, v0, s10, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v9, v2
	v_rcp_f32_e32 v10, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v2, v9, 1.0
	v_fma_f32 v16, -v8, v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v9, v11, v9 :: v_dual_fmac_f32 v10, v16, v10
	v_div_scale_f32 v11, s0, v1, s11, v1
	v_mul_f32_e32 v16, v17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v11, v10
	v_fma_f32 v19, -v2, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -v8, v18, v11
	v_fmac_f32_e32 v16, v19, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v20, v10
	v_fma_f32 v2, -v2, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v8, v18, v11
	v_div_fmas_f32 v2, v2, v9, v16
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v8, v8, v10, v18
	v_div_fixup_f32 v0, v2, s10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v8, s11, v1
	v_dual_add_f32 v0, v0, v5 :: v_dual_add_f32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v0, v0
	v_trunc_f32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v1, v0
	v_cvt_i32_f32_e32 v0, v2
	s_waitcnt vmcnt(0)
	ds_store_b128 v7, v[12:15] offset:16
	ds_store_b64 v7, v[0:1] offset:32
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v0, v7 offset:36
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v1, s18, v0
	v_cmp_le_i32_e32 vcc_lo, s18, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s8, v1
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_13
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	ds_load_b32 v2, v7 offset:32
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s0, s18
	s_cselect_b32 s1, -1, 0
	s_add_i32 s0, s0, s18
	s_cmp_ge_i32 s0, s9
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	s_or_b32 s0, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, -1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_12
; %bb.7:                                ; %.lr.ph107
                                        ;   in Loop: Header=BB0_3 Depth=1
	ds_load_2addr_b32 v[8:9], v7 offset0:3 offset1:4
	s_load_b32 s0, s[16:17], 0xc
	v_add_nc_u32_e32 v10, v3, v0
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s9, v10, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v1, v8, v9
	v_add_f32_e32 v2, v8, v9
	v_mov_b32_e32 v8, v3
	s_lshr_b32 s7, s0, 16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s19, s9, s7
.LBB0_8:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_10 Depth 3
	s_and_saveexec_b32 s21, s4
	s_cbranch_execz .LBB0_11
; %bb.9:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_load_b32 s0, s[16:17], 0xc
	v_mov_b32_e32 v9, v4
	s_mov_b32 s23, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s22, s0, 0xffff
.LBB0_10:                               ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_8 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v0, v9
	v_add_nc_u32_e32 v9, s22, v9
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e32 vcc_lo, s18, v9
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, s12, v10
	v_add_co_ci_u32_e64 v11, s0, s13, v11, s0
	global_store_b64 v[10:11], v[1:2], off
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_10
.LBB0_11:                               ; %Flow143
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	v_add_nc_u32_e32 v8, s7, v8
	v_add_nc_u32_e32 v0, s19, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, s18, v8
	s_or_b32 s20, vcc_lo, s20
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_8
.LBB0_12:                               ; %Flow145
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_13:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s0, s6, 1
	s_cmp_lt_i32 s6, s5
	s_mov_b32 s6, s0
	s_cbranch_scc1 .LBB0_3
.LBB0_14:                               ; %.loopexit96
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
		.amdhsa_group_segment_fixed_size 40
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff, .Lfunc_end0-_Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1076
; NumSgprs: 26
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 40 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 40
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z4testP4testiiP15HIP_vector_typeIfLj2EEiiifS3_iiff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
