#include<cuda_runtime.h>
#include<iostream>
#include<stdio.h>
#include<sys/time.h>
#include<assert.h>
using namespace std;

#define REAL double

#define BX 128
#define BY 2
#define BZ 1
#define GZ 1

const REAL cc = 0.4;
const REAL ce = 0.1;
const REAL cw = 0.1;
const REAL cs = 0.1;
const REAL cn = 0.1;
const REAL ct = 0.1;
const REAL cb = 0.1;

//Must be re-written, including all the parameters
int stencil(REAL *A, REAL *B, int nx, int ny, int nz, int steps)
{
  int i, j, k, s;
#define IDX(i,j,k) ((i)*ny*nz+(j)*nz+(k))
  for(s = 0; s < steps; s ++) {
    for(i = 0; i < nx; i ++) {
      for(j = 0; j < ny; j ++) {
        for(k = 0; k < nz; k ++) {
          REAL r = 0.4*A[IDX(i,j,k)];
          if(k !=  0)   r += 0.1*A[IDX(i,j,k-1)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(k != nz-1) r += 0.1*A[IDX(i,j,k+1)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(j !=  0)   r += 0.1*A[IDX(i,j-1,k)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(j != ny-1) r += 0.1*A[IDX(i,j+1,k)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(i !=  0)   r += 0.1*A[IDX(i-1,j,k)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(i != nx-1) r += 0.1*A[IDX(i+1,j,k)];
          else          r += 0.1*A[IDX(i,j,k)];
          B[IDX(i,j,k)] = r;
        }
      }
    }
     REAL *tmp = NULL;
    tmp = A, A = B, B = tmp;
  }
  return 0;
}
void check(REAL *a, REAL *b, int nx, int ny, int nz) {
    int slice = nx * ny;
    for (int z = 1; z < nz-1; ++z) {
        for (int y = 1; y < ny-1; ++y) {
            for (int x = 1; x < nz-1; ++x) {
                int idx = z * slice + y * nx + x;
                if (abs(a[idx]-b[idx]) > 1e-5) {
                    cout << a[idx] << " " << b[idx] << endl;
                    printf("%d\n", idx);
                    printf("Wrong!!!!!!!!\n");
                    return;
                }
            }
        }
    }
    printf("Right!!!!!!\n");
    return;
}
__global__ void baseline(REAL* A, REAL* B, int nx, int ny, int nz)
{
	int i = threadIdx.x + blockDim.x*blockIdx.x;
	int j = threadIdx.y + blockDim.y*blockIdx.y;
	int kb = nz/gridDim.z*blockIdx.z;
	int slice = nx*ny;

    int k = kb;
	//int k = kb > 0? kb: 1;
	int ke = (kb+nz/gridDim.z<nz)? kb+nz/gridDim.z : nz;
	int c = i + j*nx + k*slice;
    if(i>=0 && i<nx && j>=0 && j<ny){
    //#pragma unroll
	for (; k < ke; k++){
        int w = (i==0)?c:c-1;
        int e = (i==nx-1)?c:c+1;
        int n = (j==0)?c:c-nx;
        int s = (j==ny-1)?c:c+nx;
        int b = (k==0)?c:c-slice;
        int t = (k==nz-1)?c:c+slice;
        B[c] = ce*A[e] + cw*A[w] + cs*A[s] + cn*A[n]
            +ct*A[t] + cb*A[b] + cc*A[c];
        c += slice;
		//if (k > 0 && k < nz-1 && i > 0 && i < nx-1 && j > 0 && j < ny-1){
		//	B[idx] = ce*A[idx+1] + cw*A[idx-1] + cs*A[idx+nx] + cn*A[idx-nx]
		//			+ct*A[idx+slice] + cb*A[idx-slice] + cc*A[idx];
		//	idx += slice;
	}
   }
}

__global__ void baseopt(REAL* A, REAL* B, int nx, int ny, int nz)
{
	int i = threadIdx.x + blockDim.x*blockIdx.x;
	int j = threadIdx.y + blockDim.y*blockIdx.y;
	int kb = nz/gridDim.z*blockIdx.z;
	int slice = nx*ny;

	//int k = kb > 0? kb: 1;
    int k = kb;
	int ke = (kb+nz/gridDim.z<nz)? kb+nz/gridDim.z : nz;
	int c = i + j*nx + k*slice;
    int b = (k==0)?c:c-slice;
    int w = (i==0)?c:c-1;
    int e = (i==nx-1)?c:c+1;
    int n = (j==0)?c:c-nx;
    int s = (j==ny-1)?c:c+nx;
    int t;
    double b_b = A[b];
    double b_c = A[c];
    double b_t;
    if(i>=0 && i<nx && j>=0 && j<ny){
    #pragma unroll
    for (; k < ke; k++){
        t = (k==nz-1)?c:c+slice;
        b_t = A[t];
        B[c] = ce*A[e] + cw*A[w] + cs*A[s] + cn*A[n]
            +ct*b_t + cb*b_b + cc*b_c;
        b_b = b_c;
        b_c = b_t;
        c += slice;
        //b_t = B[idx+slice];
        ////A[idx] = ce*B[idx+1] + cw*B[idx-1] + cs*B[idx+nx] + cn*B[idx-nx]
        ////		+ct*B[idx+slice] + cb*B[idx-slice] + cc*B[idx];
        //A[idx] = ce*B[idx+1] + cw*B[idx-1] + cs*B[idx+nx] + cn*B[idx-nx]
        //		+ct*b_t + cb*b_b + cc*b_c;
        //b_b = b_c;
        //b_c = b_t;
        //idx += slice;
    }
  }
	return;
}

__global__ void roc(const REAL* __restrict__ A, REAL* B, int nx, int ny, int nz)
{
	int i = threadIdx.x + blockDim.x*blockIdx.x;
	int j = threadIdx.y + blockDim.y*blockIdx.y;
	int kb = nz/gridDim.z*blockIdx.z;
	int slice = nx*ny;

	//int k = kb > 0? kb: 1;
    int k = kb;
	int ke = (kb+nz/gridDim.z<nz)? kb+nz/gridDim.z : nz;
	int c = i + j*nx + k*slice;
    int b = (k==0)?c:c-slice;
    int w = (i==0)?c:c-1;
    int e = (i==nx-1)?c:c+1;
    int n = (j==0)?c:c-nx;
    int s = (j==ny-1)?c:c+nx;
    int t;
    double b_b = A[b];
    double b_c = A[c];
    double b_t;
    if(i>=0 && i<nx && j>=0 && j<ny){
    #pragma unroll
    for (; k < ke; k++){
        t = (k==nz-1)?c:c+slice;
        b_t = A[t];
        B[c] = ce*A[e] + cw*A[w] + cs*A[s] + cn*A[n]
            +ct*b_t + cb*b_b + cc*b_c;
        b_b = b_c;
        b_c = b_t;
        c += slice;
    }
   }
	return;
}

int main(int argc, char **argv){

    int NX = atoi(argv[2]);
    int NY = atoi(argv[3]);
    int NZ = atoi(argv[4]);
    int T = atoi(argv[5]);
    int num = 8;
    int NZ_ = NZ/num+2;
    if (NX*NY*NZ <= 600*600*600) {
        num = 1;
        NZ_ = NZ;
    }
    int p1, p2;
    if (NZ % num == 0) {
        p1 = p2 = NZ/num;
    } else {
        p1 = NZ / (num-1);
        p2 = NZ - p1*(num-1);
    }
	//int size = sizeof(REAL)*NX*NY*NZ;
	int partsize1 = NX*NY*p1;
    int partsize2 = NX*NY*p2;
    REAL *host_A, *host_B;
    int totalsize;
    if (num == 1) {
        totalsize = NX*NY*NZ;
        host_A = new REAL[totalsize];
        host_B = new REAL[totalsize];
    } else {
        totalsize = (partsize1+2*NX*NY)*(num-1)+partsize2;
        host_A = new REAL[totalsize];
        host_B = new REAL[totalsize];
    }
    int size_ = NZ_*NY*NX;
	REAL *cpu_A = new REAL[NX*NY*NZ];
    REAL *result_A = new REAL[NX*NY*NZ];
	REAL *cpu_B = new REAL[NX*NY*NZ];

    for (int i = 0; i < totalsize; ++i) {
        host_A[i] = 1.0;
        host_B[i] = 1.0;
    }
    //for (int k = 0; k < NZ; k++)
    //    for (int j = 0; j < NY; j++)
    //        for (int i = 0; i < NX; i++) {
    //            host_A[k*NY*NX+j*NX+i] = 1.0;
    //            host_B[k*NY*NX+j*NX+i] = 1.0;
    //        }

    for (int k = 0; k < NZ; k++)
		for (int j = 0; j < NY; j++)
			for (int i = 0; i < NX; i++) {
                //cout << k*NY*NX + j*NX + i << endl;
				cpu_A[k*NY*NX+j*NX+i] = 1.0;	
				cpu_B[k*NY*NX+j*NX+i] = 1.0;
				result_A[k*NY*NX+j*NX+i] = 1.0;
            }

    cudaEvent_t start, stop;
    cudaEventCreate(&start);
    cudaEventCreate(&stop);
    cudaEventRecord(start, 0);
    float elapsed_time;
    float elapsed_timecopy;
    double flops;
    int index = 0;
    int partsize;
    cout << "start gpu computing..." << endl;
    for (int i = 0; i < num; ++i) {
        REAL *dev_A, *dev_B;
        if (i == 0) {
            partsize = partsize1+NX*NY;
            NZ_ = p1+1;
        } else if (i < num-1) {
            partsize = partsize1+2*NX*NY;
            NZ_ = p1+2;
        } else {
            partsize = partsize2+NX*NY;
            NZ_ = p2+1;
        }
        if (num == 1) {
            partsize = NX*NY*NZ;
            NZ_ = NZ;
        }

        cudaMalloc(&dev_A, sizeof(REAL)*partsize);
        cudaMalloc(&dev_B, sizeof(REAL)*partsize);
        
       // cudaEvent_t startcopy,stopcopy;
       // cudaEventCreate(&startcopy);
       // cudaEventCreate(&stopcopy);
       // cudaEventRecord(startcopy, 0);

        cudaMemcpy(dev_A, host_A+index, sizeof(REAL)*partsize, cudaMemcpyHostToDevice);
        cudaMemcpy(dev_B, host_B+index, sizeof(REAL)*partsize, cudaMemcpyHostToDevice);
        
       // cudaEventRecord(stopcopy,0);
       // cudaEventSynchronize(stopcopy);
       // cudaEventElapsedTime(&elapsed_timecopy, startcopy, stopcopy);

        dim3 threadPerBlock(BX, BY, BZ); //128,1,1
        dim3 blockPerGrid((NX+BX-1)/BX, (NY+BY-1)/BY, GZ); //512/128,512/1,1 = 4,512,1

        ///////////////////////////////////////////////////////////////
        //baseline
        for (int t = 0; t < T; t++){
            roc<<<blockPerGrid, threadPerBlock>>>(dev_A, dev_B, NX, NY, NZ_);
            REAL* tmp = dev_A;
            dev_A = dev_B;
            dev_B = tmp;
        }
        ///////////////////////////////////////////////////////////////
        if (cudaGetLastError() != cudaSuccess)
            printf("cudawrong!!!\n");

        cudaMemcpy(host_A+index, dev_A, sizeof(REAL)*partsize, cudaMemcpyDeviceToHost);
        index += partsize;
        cudaFree(dev_A);
        cudaFree(dev_B);
    }
    cudaEventRecord(stop, 0);
    cudaEventSynchronize(stop);
    cudaEventElapsedTime(&elapsed_time, start, stop);

    struct timeval t1, t2;
    gettimeofday(&t1, NULL);
   // stencil(cpu_A, cpu_B, NX, NY, NZ, T);
    gettimeofday(&t2, NULL);
    float cpubaseline_time = (t2.tv_sec-t1.tv_sec)*1e3 + (t2.tv_usec-t1.tv_usec)*1e-3;
    cout << "CPU time:" << cpubaseline_time/T << " ms" << endl;

/*
    if (num == 1) {
        check(cpu_A, host_A, NX, NY, NZ);
    } else {
        int index=0, partsize=0, idx=0;
        for (int i = 0; i < num; ++i) {
            if (i < num-1) partsize = partsize1;
            else partsize = partsize2;

            for (int j = 0; j < partsize; ++j) {
                result_A[idx] = host_A[index+j];
                idx++;
            }

            index += partsize+2*NX*NY;
        }
        check(cpu_A, result_A, NX, NY, NZ);
    }*/
    //printf("baseline: Gflops = %lf\n", flops);

    printf("baseline: elapsed time = %f ms\n", elapsed_time);
    
   // printf("baseline: elapsed timecopy = %f ms\n", elapsed_timecopy*num);
    flops = 1.0*13*(NX-2)*(NY-2)*(NZ-2)*T/1.e+6;
    flops /= elapsed_time;

/*
	///////////////////////////////////////////////////////////////
	//baseopt
	cudaEventRecord(start, 0);
	for (int t = 0; t < T; t++){
		baseopt<<<blockPerGrid, threadPerBlock>>>(dev_A, dev_B, NX, NY, NZ);		
		REAL* tmp = dev_A;
		dev_A = dev_B;
		dev_B = tmp;
	}
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);
	if (cudaGetLastError() != cudaSuccess)
		printf("baseopt: wrong!!!\n");
	cudaEventElapsedTime(&elapsed_time, start, stop);

	printf("baseopt: elapsed time = %f ms\n", elapsed_time/T);
	flops = 1.0*13*(NX-2)*(NY-2)*(NZ-2)*T/1.e+6;
	flops /= elapsed_time;
	//printf("baseopt: Gflops = %lf\n", flops);
	///////////////////////////////////////////////////////////////

	///////////////////////////////////////////////////////////////
	//read-only data cache
	cudaEventRecord(start, 0);
	for (int t = 0; t < T; t++){
		roc<<<blockPerGrid, threadPerBlock>>>(dev_A, dev_B, NX, NY, NZ);		
		REAL* tmp = dev_A;
		dev_A = dev_B;
		dev_B = tmp;
	}
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);
	if (cudaGetLastError() != cudaSuccess)
		printf("read-only data cache: wrong!!!\n");
	cudaEventElapsedTime(&elapsed_time, start, stop);

	printf("read-only data cache: elapsed time = %f ms\n", elapsed_time);
	flops = 1.0*13*(NX-2)*(NY-2)*(NZ-2)*T/1.e+6;
	flops /= elapsed_time;
    //printf("read-only data cache: Gflops = %lf\n", flops);
	///////////////////////////////////////////////////////////////

	///////////////////////////////////////////////////////////////
	//share memory raw
	cudaEventRecord(start, 0);
	for (int t = 0; t < T; t++){
		shm_raw<<<blockPerGrid, threadPerBlock>>>(dev_A, dev_B, NX, NY, NZ);		
		REAL* tmp = dev_A;
		dev_A = dev_B;
		dev_B = tmp;
	}
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);
	if (cudaGetLastError() != cudaSuccess)
		printf("share memory raw: wrong!!!\n");
	cudaEventElapsedTime(&elapsed_time, start, stop);

	printf("share memory raw: elapsed time = %f ms\n", elapsed_time/T);
	flops = 1.0*13*(NX-2)*(NY-2)*(NZ-2)*T/1.e+6;
	flops /= elapsed_time;
	//printf("share memory raw: Gflops = %lf\n", flops);
	///////////////////////////////////////////////////////////////

	cudaEventDestroy(start);
	cudaEventDestroy(stop);
*/
	return 0;
}

	.file	"tmpxft_003571ff_00000000-6_stencilparallel_last.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3640:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3640:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7stencilPdS_iiii
	.type	_Z7stencilPdS_iiii, @function
_Z7stencilPdS_iiii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movsd	.LC0(%rip), %xmm3
	movl	%edx, %r11d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movsd	.LC1(%rip), %xmm1
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	imull	%r8d, %r12d
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r9d, -16(%rsp)
.L3:
	movl	-16(%rsp), %eax
	cmpl	%eax, %ebp
	jge	.L31
	movsd	.LC1(%rip), %xmm5
	xorl	%eax, %eax
	xorl	%r10d, %r10d
.L21:
	cmpl	%r11d, %r10d
	jge	.L19
	leal	(%rax,%r12), %edx
	movsd	.LC1(%rip), %xmm4
	xorl	%r9d, %r9d
	movl	%edx, -28(%rsp)
.L20:
	cmpl	%ecx, %r9d
	jge	.L17
	movl	%eax, %ebx
	leal	-1(%r8), %r15d
	movsd	.LC1(%rip), %xmm6
	xorl	%edx, %edx
	subl	%r8d, %ebx
	movl	%r15d, -12(%rsp)
	leal	-1(%rcx), %r15d
	leal	(%rax,%r8), %r14d
	movl	%ebx, -32(%rsp)
	movl	%eax, %ebx
	movl	%r15d, -8(%rsp)
	leal	-1(%r11), %r15d
	subl	%r12d, %ebx
	movl	%r15d, -4(%rsp)
	movl	%ebx, -20(%rsp)
	leal	(%rax,%r12), %ebx
	movl	%ebx, -24(%rsp)
	leal	1(%rax), %ebx
	salq	$3, %rax
.L18:
	movl	%edx, %r15d
	cmpl	%edx, %r8d
	jle	.L32
	movsd	(%rdi,%rax), %xmm2
	movaps	%xmm2, %xmm0
	mulsd	%xmm3, %xmm0
	testq	%rdx, %rdx
	je	.L4
	leal	-2(%rbx), %r13d
	movslq	%r13d, %r13
	movsd	(%rdi,%r13,8), %xmm7
	mulsd	%xmm1, %xmm7
	jmp	.L24
.L4:
	movaps	%xmm2, %xmm7
	mulsd	%xmm1, %xmm7
.L24:
	addsd	%xmm7, %xmm0
	cmpl	%r15d, -12(%rsp)
	je	.L6
	movslq	%ebx, %r13
	movsd	(%rdi,%r13,8), %xmm7
	mulsd	%xmm1, %xmm7
	jmp	.L25
.L6:
	movaps	%xmm2, %xmm7
	mulsd	%xmm6, %xmm7
.L25:
	addsd	%xmm7, %xmm0
	testl	%r9d, %r9d
	je	.L8
	movl	-32(%rsp), %r15d
	leal	(%r15,%rdx), %r13d
	movslq	%r13d, %r13
	movsd	(%rdi,%r13,8), %xmm7
	mulsd	%xmm1, %xmm7
	jmp	.L26
.L8:
	movaps	%xmm2, %xmm7
	mulsd	%xmm5, %xmm7
.L26:
	addsd	%xmm7, %xmm0
	cmpl	%r9d, -8(%rsp)
	je	.L10
	leal	(%r14,%rdx), %r13d
	movslq	%r13d, %r13
	movsd	(%rdi,%r13,8), %xmm7
	mulsd	%xmm1, %xmm7
	jmp	.L27
.L10:
	movaps	%xmm2, %xmm7
	mulsd	%xmm4, %xmm7
.L27:
	addsd	%xmm7, %xmm0
	testl	%r10d, %r10d
	je	.L12
	movl	-20(%rsp), %r15d
	leal	(%r15,%rdx), %r13d
	movslq	%r13d, %r13
	movsd	(%rdi,%r13,8), %xmm7
	mulsd	%xmm1, %xmm7
	jmp	.L28
.L12:
	movaps	%xmm2, %xmm7
	mulsd	%xmm1, %xmm7
.L28:
	addsd	%xmm7, %xmm0
	cmpl	%r10d, -4(%rsp)
	je	.L14
	movl	-24(%rsp), %r15d
	leal	(%r15,%rdx), %r13d
	movslq	%r13d, %r13
	movsd	(%rdi,%r13,8), %xmm2
	mulsd	%xmm1, %xmm2
	jmp	.L29
.L14:
	mulsd	%xmm1, %xmm2
.L29:
	addsd	%xmm2, %xmm0
	incq	%rdx
	incl	%ebx
	movsd	%xmm0, (%rsi,%rax)
	addq	$8, %rax
	jmp	.L18
.L32:
	incl	%r9d
	movslq	%r14d, %rax
	jmp	.L20
.L17:
	movslq	-28(%rsp), %rax
	incl	%r10d
	jmp	.L21
.L19:
	incl	%ebp
	xchgq	%rsi, %rdi
	jmp	.L3
.L31:
	popq	%rbx
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z7stencilPdS_iiii, .-_Z7stencilPdS_iiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	" "
.LC5:
	.string	"%d\n"
.LC6:
	.string	"Wrong!!!!!!!!\n"
.LC7:
	.string	"Right!!!!!!\n"
	.text
	.globl	_Z5checkPdS_iii
	.type	_Z5checkPdS_iii, @function
_Z5checkPdS_iii:
.LFB3636:
	.cfi_startproc
	endbr64
	movl	%edx, %r11d
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1, %r10d
	decl	%r8d
	imull	%ecx, %r11d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	decl	%ecx
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r11d, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	pushq	%r9
	.cfi_def_cfa_offset 64
	movq	%rdi, %r9
	movslq	%edx, %rdi
	movq	.LC2(%rip), %xmm2
	movsd	.LC3(%rip), %xmm3
	leaq	0(,%rdi,8), %r14
	incq	%rdi
.L34:
	cmpl	%r10d, %r8d
	jle	.L38
	movslq	%esi, %rax
	leal	(%rsi,%rdx), %ebx
	movl	$1, %r15d
	addq	%rdi, %rax
	salq	$3, %rax
.L39:
	cmpl	%r15d, %ecx
	jle	.L46
	movq	%rax, %rbp
	movl	$1, %r13d
.L37:
	movsd	(%r9,%rbp), %xmm1
	movaps	%xmm1, %xmm0
	subsd	(%r12,%rbp), %xmm0
	andps	%xmm2, %xmm0
	comisd	%xmm3, %xmm0
	jbe	.L43
	movaps	%xmm1, %xmm0
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	(%r12,%rbp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC5(%rip), %rsi
	leal	0(%r13,%rbx), %edx
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %rsi
	jmp	.L45
.L43:
	incl	%r13d
	addq	$8, %rbp
	cmpl	%r13d, %r8d
	jg	.L37
	incl	%r15d
	addq	%r14, %rax
	addl	%edx, %ebx
	jmp	.L39
.L46:
	incl	%r10d
	addl	%r11d, %esi
	jmp	.L34
.L38:
	leaq	.LC7(%rip), %rsi
.L45:
	popq	%rdx
	.cfi_def_cfa_offset 56
	movl	$2, %edi
	popq	%rbx
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE3636:
	.size	_Z5checkPdS_iii, .-_Z5checkPdS_iii
	.globl	_Z32__device_stub__Z8baselinePdS_iiiPdS_iii
	.type	_Z32__device_stub__Z8baselinePdS_iiiPdS_iii, @function
_Z32__device_stub__Z8baselinePdS_iiiPdS_iii:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8baselinePdS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L47:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L49
	call	__stack_chk_fail@PLT
.L49:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z32__device_stub__Z8baselinePdS_iiiPdS_iii, .-_Z32__device_stub__Z8baselinePdS_iiiPdS_iii
	.globl	_Z8baselinePdS_iii
	.type	_Z8baselinePdS_iii, @function
_Z8baselinePdS_iii:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z8baselinePdS_iiiPdS_iii
	.cfi_endproc
.LFE3663:
	.size	_Z8baselinePdS_iii, .-_Z8baselinePdS_iii
	.globl	_Z31__device_stub__Z7baseoptPdS_iiiPdS_iii
	.type	_Z31__device_stub__Z7baseoptPdS_iiiPdS_iii, @function
_Z31__device_stub__Z7baseoptPdS_iiiPdS_iii:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7baseoptPdS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L52:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L54
	call	__stack_chk_fail@PLT
.L54:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z31__device_stub__Z7baseoptPdS_iiiPdS_iii, .-_Z31__device_stub__Z7baseoptPdS_iiiPdS_iii
	.globl	_Z7baseoptPdS_iii
	.type	_Z7baseoptPdS_iii, @function
_Z7baseoptPdS_iii:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z7baseoptPdS_iiiPdS_iii
	.cfi_endproc
.LFE3665:
	.size	_Z7baseoptPdS_iii, .-_Z7baseoptPdS_iii
	.globl	_Z28__device_stub__Z3rocPKdPdiiiPKdPdiii
	.type	_Z28__device_stub__Z3rocPKdPdiiiPKdPdiii, @function
_Z28__device_stub__Z3rocPKdPdiiiPKdPdiii:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rsi, 24(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L57
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z3rocPKdPdiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L57:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L59
	call	__stack_chk_fail@PLT
.L59:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z28__device_stub__Z3rocPKdPdiiiPKdPdiii, .-_Z28__device_stub__Z3rocPKdPdiiiPKdPdiii
	.globl	_Z3rocPKdPdiii
	.type	_Z3rocPKdPdiii, @function
_Z3rocPKdPdiii:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z3rocPKdPdiiiPKdPdiii
	.cfi_endproc
.LFE3667:
	.size	_Z3rocPKdPdiii, .-_Z3rocPKdPdiii
	.section	.rodata.str1.1
.LC9:
	.string	"start gpu computing..."
.LC10:
	.string	"cudawrong!!!\n"
.LC13:
	.string	"CPU time:"
.LC14:
	.string	" ms"
.LC15:
	.string	"baseline: elapsed time = %f ms\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	subq	$184, %rsp
	.cfi_def_cfa_offset 240
	movq	16(%rsi), %rdi
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	call	atoi@PLT
	movq	24(%rbx), %rdi
	movl	%eax, 8(%rsp)
	call	atoi@PLT
	movq	32(%rbx), %rdi
	movl	%eax, 28(%rsp)
	call	atoi@PLT
	movq	40(%rbx), %rdi
	movl	%eax, 12(%rsp)
	call	atoi@PLT
	movl	8(%rsp), %r12d
	movl	%eax, 68(%rsp)
	movl	28(%rsp), %eax
	imull	%eax, %r12d
	movl	12(%rsp), %eax
	imull	%r12d, %eax
	movl	%eax, 32(%rsp)
	cmpl	$216000000, %eax
	jle	.L88
	movl	$8, %ebp
	testb	$7, 12(%rsp)
	jne	.L97
	jmp	.L63
.L88:
	movl	$1, %ebp
.L63:
	movl	12(%rsp), %eax
	cltd
	idivl	%ebp
	movl	%eax, 24(%rsp)
	movl	%eax, 36(%rsp)
	jmp	.L65
.L97:
	movl	12(%rsp), %eax
	movl	$7, %ecx
	movl	$8, %ebp
	cltd
	idivl	%ecx
	movl	%edx, 36(%rsp)
	movl	%eax, 24(%rsp)
.L65:
	movl	36(%rsp), %eax
	movl	24(%rsp), %ebx
	movslq	32(%rsp), %r13
	imull	%r12d, %eax
	imull	%r12d, %ebx
	cmpl	$1, %ebp
	movl	%eax, 80(%rsp)
	jne	.L66
	movabsq	$1152921504606846975, %rax
	cmpq	%r13, %rax
	jb	.L67
	leaq	0(,%r13,8), %r14
	movq	%r14, %rdi
	call	_Znam@PLT
	movq	%r14, %rdi
	movq	%rax, 40(%rsp)
	call	_Znam@PLT
	movl	32(%rsp), %r14d
	movq	%rax, 48(%rsp)
	jmp	.L68
.L67:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L96
	call	__cxa_throw_bad_array_new_length@PLT
.L66:
	leal	(%rbx,%r12,2), %r14d
	movl	80(%rsp), %eax
	imull	$7, %r14d, %r14d
	addl	%eax, %r14d
	movabsq	$1152921504606846975, %rax
	movslq	%r14d, %r15
	cmpq	%r15, %rax
	jb	.L67
	salq	$3, %r15
	movq	%r15, %rdi
	call	_Znam@PLT
	movq	%r15, %rdi
	movq	%rax, 40(%rsp)
	call	_Znam@PLT
	movq	%rax, 48(%rsp)
.L68:
	movabsq	$1152921504606846975, %rax
	cmpq	%r13, %rax
	jb	.L67
	salq	$3, %r13
	movq	%r13, %rdi
	call	_Znam@PLT
	movq	%r13, %rdi
	movq	%rax, %r15
	call	_Znam@PLT
	movq	%r13, %rdi
	movq	%rax, 16(%rsp)
	call	_Znam@PLT
	movsd	.LC8(%rip), %xmm0
	movq	16(%rsp), %rcx
	movq	%rax, %rsi
	xorl	%eax, %eax
.L70:
	cmpl	%eax, %r14d
	jle	.L98
	movq	40(%rsp), %rdx
	movsd	%xmm0, (%rdx,%rax,8)
	movq	48(%rsp), %rdx
	movsd	%xmm0, (%rdx,%rax,8)
	incq	%rax
	jmp	.L70
.L98:
	movl	28(%rsp), %r13d
	movl	8(%rsp), %eax
	xorl	%edi, %edi
	xorl	%edx, %edx
	movsd	.LC8(%rip), %xmm0
	imull	%eax, %r13d
.L72:
	movl	12(%rsp), %eax
	cmpl	%eax, %edx
	jge	.L99
	movl	%edi, %r9d
	xorl	%r10d, %r10d
.L76:
	movl	28(%rsp), %eax
	cmpl	%eax, %r10d
	jge	.L74
	movslq	%r9d, %rax
	xorl	%r8d, %r8d
	salq	$3, %rax
.L75:
	movl	8(%rsp), %r11d
	cmpl	%r11d, %r8d
	jge	.L100
	movsd	%xmm0, (%r15,%rax)
	incl	%r8d
	movsd	%xmm0, (%rsi,%rax)
	movsd	%xmm0, (%rcx,%rax)
	addq	$8, %rax
	jmp	.L75
.L100:
	incl	%r10d
	addl	%r11d, %r9d
	jmp	.L76
.L74:
	incl	%edx
	addl	%r13d, %edi
	jmp	.L72
.L99:
	leaq	104(%rsp), %rdi
	xorl	%r14d, %r14d
	call	cudaEventCreate@PLT
	leaq	112(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	104(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	.LC9(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leal	(%rbx,%r13,2), %eax
	movl	$2, %ecx
	addl	%r12d, %ebx
	movl	%eax, 84(%rsp)
	movl	28(%rsp), %eax
	incl	%eax
	cltd
	idivl	%ecx
	movl	$128, %ecx
	movl	%eax, 88(%rsp)
	movl	8(%rsp), %eax
	addl	$127, %eax
	cltd
	idivl	%ecx
	movl	%eax, 92(%rsp)
	movl	24(%rsp), %eax
	leal	1(%rax), %r13d
	xorl	%eax, %eax
	movl	%eax, 64(%rsp)
.L77:
	cmpl	$1, %ebp
	cmove	32(%rsp), %ebx
	cmove	12(%rsp), %r13d
.L78:
	leaq	120(%rsp), %rdi
	movslq	%ebx, %rax
	salq	$3, %rax
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMalloc@PLT
	leaq	128(%rsp), %rax
	movq	16(%rsp), %rsi
	movq	%rax, %rdi
	movq	%rax, 72(%rsp)
	call	cudaMalloc@PLT
	movslq	64(%rsp), %r15
	movq	40(%rsp), %rax
	movl	$1, %ecx
	movq	16(%rsp), %rdx
	movq	120(%rsp), %rdi
	salq	$3, %r15
	addq	%r15, %rax
	movq	%rax, %rsi
	movq	%rax, 56(%rsp)
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rax
	movq	16(%rsp), %rdx
	movl	$1, %ecx
	movq	128(%rsp), %rdi
	leaq	(%rax,%r15), %rsi
	xorl	%r15d, %r15d
	call	cudaMemcpy@PLT
	movl	$67108865, %eax
	movl	$1, 144(%rsp)
	movl	$1, 160(%rsp)
	salq	$7, %rax
	movq	%rax, 136(%rsp)
	movl	92(%rsp), %eax
	movl	%eax, 152(%rsp)
	movl	88(%rsp), %eax
	movl	%eax, 156(%rsp)
.L80:
	movl	68(%rsp), %eax
	cmpl	%eax, %r15d
	jge	.L101
	movl	144(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	136(%rsp), %rdx
	movq	152(%rsp), %rdi
	movl	160(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L81
	movl	28(%rsp), %ecx
	movl	8(%rsp), %edx
	movl	%r13d, %r8d
	movq	128(%rsp), %rsi
	movq	120(%rsp), %rdi
	call	_Z28__device_stub__Z3rocPKdPdiiiPKdPdiii
.L81:
	movq	120(%rsp), %rax
	movq	128(%rsp), %rdx
	incl	%r15d
	movq	%rdx, 120(%rsp)
	movq	%rax, 128(%rsp)
	jmp	.L80
.L101:
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L83
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L83:
	movq	16(%rsp), %rdx
	movq	120(%rsp), %rsi
	movl	$2, %ecx
	incl	%r14d
	movq	56(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	120(%rsp), %rdi
	addl	%ebx, 64(%rsp)
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	cmpl	%r14d, %ebp
	je	.L84
	leal	-1(%rbp), %eax
	cmpl	%r14d, %eax
	jle	.L102
	movl	24(%rsp), %eax
	movl	84(%rsp), %ebx
	leal	2(%rax), %r13d
	jmp	.L78
.L102:
	movl	80(%rsp), %eax
	leal	(%r12,%rax), %ebx
	movl	36(%rsp), %eax
	leal	1(%rax), %r13d
	jmp	.L77
.L84:
	movq	112(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	112(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	112(%rsp), %rdx
	movq	104(%rsp), %rsi
	movq	72(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	xorl	%esi, %esi
	leaq	136(%rsp), %rdi
	call	gettimeofday@PLT
	xorl	%esi, %esi
	leaq	152(%rsp), %rdi
	call	gettimeofday@PLT
	movq	152(%rsp), %rax
	subq	136(%rsp), %rax
	leaq	.LC13(%rip), %rsi
	cvtsi2sdq	%rax, %xmm0
	movq	160(%rsp), %rax
	subq	144(%rsp), %rax
	leaq	_ZSt4cout(%rip), %rdi
	mulsd	.LC11(%rip), %xmm0
	cvtsi2sdq	%rax, %xmm1
	mulsd	.LC12(%rip), %xmm1
	addsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 8(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtsi2ssl	68(%rsp), %xmm1
	movss	8(%rsp), %xmm0
	movq	%rax, %rdi
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC14(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	128(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L87
.L96:
	call	__stack_chk_fail@PLT
.L87:
	addq	$184, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	main, .-main
	.section	.rodata.str1.1
.LC16:
	.string	"_Z3rocPKdPdiii"
.LC17:
	.string	"_Z7baseoptPdS_iii"
.LC18:
	.string	"_Z8baselinePdS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3669:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z3rocPKdPdiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7baseoptPdS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8baselinePdS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3669:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	-1717986918
	.long	1071225241
	.align 8
.LC1:
	.long	-1717986918
	.long	1069128089
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC2:
	.long	-1
	.long	2147483647
	.long	0
	.long	0
	.section	.rodata.cst8
	.align 8
.LC3:
	.long	-1998362383
	.long	1055193269
	.align 8
.LC8:
	.long	0
	.long	1072693248
	.align 8
.LC11:
	.long	0
	.long	1083129856
	.align 8
.LC12:
	.long	-755914244
	.long	1062232653
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<hip/hip_runtime.h>
#include<iostream>
#include<stdio.h>
#include<sys/time.h>
#include<assert.h>
using namespace std;

#define REAL double

#define BX 128
#define BY 2
#define BZ 1
#define GZ 1

const REAL cc = 0.4;
const REAL ce = 0.1;
const REAL cw = 0.1;
const REAL cs = 0.1;
const REAL cn = 0.1;
const REAL ct = 0.1;
const REAL cb = 0.1;

//Must be re-written, including all the parameters
int stencil(REAL *A, REAL *B, int nx, int ny, int nz, int steps)
{
  int i, j, k, s;
#define IDX(i,j,k) ((i)*ny*nz+(j)*nz+(k))
  for(s = 0; s < steps; s ++) {
    for(i = 0; i < nx; i ++) {
      for(j = 0; j < ny; j ++) {
        for(k = 0; k < nz; k ++) {
          REAL r = 0.4*A[IDX(i,j,k)];
          if(k !=  0)   r += 0.1*A[IDX(i,j,k-1)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(k != nz-1) r += 0.1*A[IDX(i,j,k+1)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(j !=  0)   r += 0.1*A[IDX(i,j-1,k)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(j != ny-1) r += 0.1*A[IDX(i,j+1,k)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(i !=  0)   r += 0.1*A[IDX(i-1,j,k)];
          else          r += 0.1*A[IDX(i,j,k)];
          if(i != nx-1) r += 0.1*A[IDX(i+1,j,k)];
          else          r += 0.1*A[IDX(i,j,k)];
          B[IDX(i,j,k)] = r;
        }
      }
    }
     REAL *tmp = NULL;
    tmp = A, A = B, B = tmp;
  }
  return 0;
}
void check(REAL *a, REAL *b, int nx, int ny, int nz) {
    int slice = nx * ny;
    for (int z = 1; z < nz-1; ++z) {
        for (int y = 1; y < ny-1; ++y) {
            for (int x = 1; x < nz-1; ++x) {
                int idx = z * slice + y * nx + x;
                if (abs(a[idx]-b[idx]) > 1e-5) {
                    cout << a[idx] << " " << b[idx] << endl;
                    printf("%d\n", idx);
                    printf("Wrong!!!!!!!!\n");
                    return;
                }
            }
        }
    }
    printf("Right!!!!!!\n");
    return;
}
__global__ void baseline(REAL* A, REAL* B, int nx, int ny, int nz)
{
	int i = threadIdx.x + blockDim.x*blockIdx.x;
	int j = threadIdx.y + blockDim.y*blockIdx.y;
	int kb = nz/gridDim.z*blockIdx.z;
	int slice = nx*ny;

    int k = kb;
	//int k = kb > 0? kb: 1;
	int ke = (kb+nz/gridDim.z<nz)? kb+nz/gridDim.z : nz;
	int c = i + j*nx + k*slice;
    if(i>=0 && i<nx && j>=0 && j<ny){
    //#pragma unroll
	for (; k < ke; k++){
        int w = (i==0)?c:c-1;
        int e = (i==nx-1)?c:c+1;
        int n = (j==0)?c:c-nx;
        int s = (j==ny-1)?c:c+nx;
        int b = (k==0)?c:c-slice;
        int t = (k==nz-1)?c:c+slice;
        B[c] = ce*A[e] + cw*A[w] + cs*A[s] + cn*A[n]
            +ct*A[t] + cb*A[b] + cc*A[c];
        c += slice;
		//if (k > 0 && k < nz-1 && i > 0 && i < nx-1 && j > 0 && j < ny-1){
		//	B[idx] = ce*A[idx+1] + cw*A[idx-1] + cs*A[idx+nx] + cn*A[idx-nx]
		//			+ct*A[idx+slice] + cb*A[idx-slice] + cc*A[idx];
		//	idx += slice;
	}
   }
}

__global__ void baseopt(REAL* A, REAL* B, int nx, int ny, int nz)
{
	int i = threadIdx.x + blockDim.x*blockIdx.x;
	int j = threadIdx.y + blockDim.y*blockIdx.y;
	int kb = nz/gridDim.z*blockIdx.z;
	int slice = nx*ny;

	//int k = kb > 0? kb: 1;
    int k = kb;
	int ke = (kb+nz/gridDim.z<nz)? kb+nz/gridDim.z : nz;
	int c = i + j*nx + k*slice;
    int b = (k==0)?c:c-slice;
    int w = (i==0)?c:c-1;
    int e = (i==nx-1)?c:c+1;
    int n = (j==0)?c:c-nx;
    int s = (j==ny-1)?c:c+nx;
    int t;
    double b_b = A[b];
    double b_c = A[c];
    double b_t;
    if(i>=0 && i<nx && j>=0 && j<ny){
    #pragma unroll
    for (; k < ke; k++){
        t = (k==nz-1)?c:c+slice;
        b_t = A[t];
        B[c] = ce*A[e] + cw*A[w] + cs*A[s] + cn*A[n]
            +ct*b_t + cb*b_b + cc*b_c;
        b_b = b_c;
        b_c = b_t;
        c += slice;
        //b_t = B[idx+slice];
        ////A[idx] = ce*B[idx+1] + cw*B[idx-1] + cs*B[idx+nx] + cn*B[idx-nx]
        ////		+ct*B[idx+slice] + cb*B[idx-slice] + cc*B[idx];
        //A[idx] = ce*B[idx+1] + cw*B[idx-1] + cs*B[idx+nx] + cn*B[idx-nx]
        //		+ct*b_t + cb*b_b + cc*b_c;
        //b_b = b_c;
        //b_c = b_t;
        //idx += slice;
    }
  }
	return;
}

__global__ void roc(const REAL* __restrict__ A, REAL* B, int nx, int ny, int nz)
{
	int i = threadIdx.x + blockDim.x*blockIdx.x;
	int j = threadIdx.y + blockDim.y*blockIdx.y;
	int kb = nz/gridDim.z*blockIdx.z;
	int slice = nx*ny;

	//int k = kb > 0? kb: 1;
    int k = kb;
	int ke = (kb+nz/gridDim.z<nz)? kb+nz/gridDim.z : nz;
	int c = i + j*nx + k*slice;
    int b = (k==0)?c:c-slice;
    int w = (i==0)?c:c-1;
    int e = (i==nx-1)?c:c+1;
    int n = (j==0)?c:c-nx;
    int s = (j==ny-1)?c:c+nx;
    int t;
    double b_b = A[b];
    double b_c = A[c];
    double b_t;
    if(i>=0 && i<nx && j>=0 && j<ny){
    #pragma unroll
    for (; k < ke; k++){
        t = (k==nz-1)?c:c+slice;
        b_t = A[t];
        B[c] = ce*A[e] + cw*A[w] + cs*A[s] + cn*A[n]
            +ct*b_t + cb*b_b + cc*b_c;
        b_b = b_c;
        b_c = b_t;
        c += slice;
    }
   }
	return;
}

int main(int argc, char **argv){

    int NX = atoi(argv[2]);
    int NY = atoi(argv[3]);
    int NZ = atoi(argv[4]);
    int T = atoi(argv[5]);
    int num = 8;
    int NZ_ = NZ/num+2;
    if (NX*NY*NZ <= 600*600*600) {
        num = 1;
        NZ_ = NZ;
    }
    int p1, p2;
    if (NZ % num == 0) {
        p1 = p2 = NZ/num;
    } else {
        p1 = NZ / (num-1);
        p2 = NZ - p1*(num-1);
    }
	//int size = sizeof(REAL)*NX*NY*NZ;
	int partsize1 = NX*NY*p1;
    int partsize2 = NX*NY*p2;
    REAL *host_A, *host_B;
    int totalsize;
    if (num == 1) {
        totalsize = NX*NY*NZ;
        host_A = new REAL[totalsize];
        host_B = new REAL[totalsize];
    } else {
        totalsize = (partsize1+2*NX*NY)*(num-1)+partsize2;
        host_A = new REAL[totalsize];
        host_B = new REAL[totalsize];
    }
    int size_ = NZ_*NY*NX;
	REAL *cpu_A = new REAL[NX*NY*NZ];
    REAL *result_A = new REAL[NX*NY*NZ];
	REAL *cpu_B = new REAL[NX*NY*NZ];

    for (int i = 0; i < totalsize; ++i) {
        host_A[i] = 1.0;
        host_B[i] = 1.0;
    }
    //for (int k = 0; k < NZ; k++)
    //    for (int j = 0; j < NY; j++)
    //        for (int i = 0; i < NX; i++) {
    //            host_A[k*NY*NX+j*NX+i] = 1.0;
    //            host_B[k*NY*NX+j*NX+i] = 1.0;
    //        }

    for (int k = 0; k < NZ; k++)
		for (int j = 0; j < NY; j++)
			for (int i = 0; i < NX; i++) {
                //cout << k*NY*NX + j*NX + i << endl;
				cpu_A[k*NY*NX+j*NX+i] = 1.0;	
				cpu_B[k*NY*NX+j*NX+i] = 1.0;
				result_A[k*NY*NX+j*NX+i] = 1.0;
            }

    hipEvent_t start, stop;
    hipEventCreate(&start);
    hipEventCreate(&stop);
    hipEventRecord(start, 0);
    float elapsed_time;
    float elapsed_timecopy;
    double flops;
    int index = 0;
    int partsize;
    cout << "start gpu computing..." << endl;
    for (int i = 0; i < num; ++i) {
        REAL *dev_A, *dev_B;
        if (i == 0) {
            partsize = partsize1+NX*NY;
            NZ_ = p1+1;
        } else if (i < num-1) {
            partsize = partsize1+2*NX*NY;
            NZ_ = p1+2;
        } else {
            partsize = partsize2+NX*NY;
            NZ_ = p2+1;
        }
        if (num == 1) {
            partsize = NX*NY*NZ;
            NZ_ = NZ;
        }

        hipMalloc(&dev_A, sizeof(REAL)*partsize);
        hipMalloc(&dev_B, sizeof(REAL)*partsize);
        
       // cudaEvent_t startcopy,stopcopy;
       // cudaEventCreate(&startcopy);
       // cudaEventCreate(&stopcopy);
       // cudaEventRecord(startcopy, 0);

        hipMemcpy(dev_A, host_A+index, sizeof(REAL)*partsize, hipMemcpyHostToDevice);
        hipMemcpy(dev_B, host_B+index, sizeof(REAL)*partsize, hipMemcpyHostToDevice);
        
       // cudaEventRecord(stopcopy,0);
       // cudaEventSynchronize(stopcopy);
       // cudaEventElapsedTime(&elapsed_timecopy, startcopy, stopcopy);

        dim3 threadPerBlock(BX, BY, BZ); //128,1,1
        dim3 blockPerGrid((NX+BX-1)/BX, (NY+BY-1)/BY, GZ); //512/128,512/1,1 = 4,512,1

        ///////////////////////////////////////////////////////////////
        //baseline
        for (int t = 0; t < T; t++){
            roc<<<blockPerGrid, threadPerBlock>>>(dev_A, dev_B, NX, NY, NZ_);
            REAL* tmp = dev_A;
            dev_A = dev_B;
            dev_B = tmp;
        }
        ///////////////////////////////////////////////////////////////
        if (hipGetLastError() != hipSuccess)
            printf("cudawrong!!!\n");

        hipMemcpy(host_A+index, dev_A, sizeof(REAL)*partsize, hipMemcpyDeviceToHost);
        index += partsize;
        hipFree(dev_A);
        hipFree(dev_B);
    }
    hipEventRecord(stop, 0);
    hipEventSynchronize(stop);
    hipEventElapsedTime(&elapsed_time, start, stop);

    struct timeval t1, t2;
    gettimeofday(&t1, NULL);
   // stencil(cpu_A, cpu_B, NX, NY, NZ, T);
    gettimeofday(&t2, NULL);
    float cpubaseline_time = (t2.tv_sec-t1.tv_sec)*1e3 + (t2.tv_usec-t1.tv_usec)*1e-3;
    cout << "CPU time:" << cpubaseline_time/T << " ms" << endl;

/*
    if (num == 1) {
        check(cpu_A, host_A, NX, NY, NZ);
    } else {
        int index=0, partsize=0, idx=0;
        for (int i = 0; i < num; ++i) {
            if (i < num-1) partsize = partsize1;
            else partsize = partsize2;

            for (int j = 0; j < partsize; ++j) {
                result_A[idx] = host_A[index+j];
                idx++;
            }

            index += partsize+2*NX*NY;
        }
        check(cpu_A, result_A, NX, NY, NZ);
    }*/
    //printf("baseline: Gflops = %lf\n", flops);

    printf("baseline: elapsed time = %f ms\n", elapsed_time);
    
   // printf("baseline: elapsed timecopy = %f ms\n", elapsed_timecopy*num);
    flops = 1.0*13*(NX-2)*(NY-2)*(NZ-2)*T/1.e+6;
    flops /= elapsed_time;

/*
	///////////////////////////////////////////////////////////////
	//baseopt
	cudaEventRecord(start, 0);
	for (int t = 0; t < T; t++){
		baseopt<<<blockPerGrid, threadPerBlock>>>(dev_A, dev_B, NX, NY, NZ);		
		REAL* tmp = dev_A;
		dev_A = dev_B;
		dev_B = tmp;
	}
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);
	if (cudaGetLastError() != cudaSuccess)
		printf("baseopt: wrong!!!\n");
	cudaEventElapsedTime(&elapsed_time, start, stop);

	printf("baseopt: elapsed time = %f ms\n", elapsed_time/T);
	flops = 1.0*13*(NX-2)*(NY-2)*(NZ-2)*T/1.e+6;
	flops /= elapsed_time;
	//printf("baseopt: Gflops = %lf\n", flops);
	///////////////////////////////////////////////////////////////

	///////////////////////////////////////////////////////////////
	//read-only data cache
	cudaEventRecord(start, 0);
	for (int t = 0; t < T; t++){
		roc<<<blockPerGrid, threadPerBlock>>>(dev_A, dev_B, NX, NY, NZ);		
		REAL* tmp = dev_A;
		dev_A = dev_B;
		dev_B = tmp;
	}
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);
	if (cudaGetLastError() != cudaSuccess)
		printf("read-only data cache: wrong!!!\n");
	cudaEventElapsedTime(&elapsed_time, start, stop);

	printf("read-only data cache: elapsed time = %f ms\n", elapsed_time);
	flops = 1.0*13*(NX-2)*(NY-2)*(NZ-2)*T/1.e+6;
	flops /= elapsed_time;
    //printf("read-only data cache: Gflops = %lf\n", flops);
	///////////////////////////////////////////////////////////////

	///////////////////////////////////////////////////////////////
	//share memory raw
	cudaEventRecord(start, 0);
	for (int t = 0; t < T; t++){
		shm_raw<<<blockPerGrid, threadPerBlock>>>(dev_A, dev_B, NX, NY, NZ);		
		REAL* tmp = dev_A;
		dev_A = dev_B;
		dev_B = tmp;
	}
	cudaEventRecord(stop, 0);
	cudaEventSynchronize(stop);
	if (cudaGetLastError() != cudaSuccess)
		printf("share memory raw: wrong!!!\n");
	cudaEventElapsedTime(&elapsed_time, start, stop);

	printf("share memory raw: elapsed time = %f ms\n", elapsed_time/T);
	flops = 1.0*13*(NX-2)*(NY-2)*(NZ-2)*T/1.e+6;
	flops /= elapsed_time;
	//printf("share memory raw: Gflops = %lf\n", flops);
	///////////////////////////////////////////////////////////////

	cudaEventDestroy(start);
	cudaEventDestroy(stop);
*/
	return 0;
}

	.text
	.file	"stencilparallel_last.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z7stencilPdS_iiii
.LCPI0_0:
	.quad	0x3fd999999999999a              # double 0.40000000000000002
.LCPI0_1:
	.quad	0x3fb999999999999a              # double 0.10000000000000001
	.text
	.globl	_Z7stencilPdS_iiii
	.type	_Z7stencilPdS_iiii,@function
_Z7stencilPdS_iiii:                     # @_Z7stencilPdS_iiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $r8d killed $r8d def $r8
                                        # kill: def $ecx killed $ecx def $rcx
	movq	%rcx, -56(%rsp)                 # 8-byte Spill
                                        # kill: def $edx killed $edx def $rdx
	movq	%rdx, -72(%rsp)                 # 8-byte Spill
	movq	%rsi, -112(%rsp)                # 8-byte Spill
	movl	%r9d, -80(%rsp)                 # 4-byte Spill
	testl	%r9d, %r9d
	jle	.LBB0_16
# %bb.1:                                # %.preheader154.lr.ph
	leal	-1(%r8), %r11d
	movq	-56(%rsp), %rax                 # 8-byte Reload
	leal	-1(%rax), %ecx
	movq	%rcx, -8(%rsp)                  # 8-byte Spill
	movq	-72(%rsp), %rcx                 # 8-byte Reload
	leal	-1(%rcx), %edx
	movq	%rdx, -16(%rsp)                 # 8-byte Spill
	movl	%eax, %edx
	movq	%rdx, -48(%rsp)                 # 8-byte Spill
	movl	%ecx, %ecx
	movq	%rcx, -40(%rsp)                 # 8-byte Spill
	movl	%r8d, %r15d
	movl	%r8d, %ecx
	imull	%eax, %ecx
	movl	%ecx, -76(%rsp)                 # 4-byte Spill
	shlq	$3, %r11
	shlq	$3, %r15
	xorl	%eax, %eax
	movq	%rax, -64(%rsp)                 # 8-byte Spill
	movsd	.LCPI0_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	.LCPI0_1(%rip), %xmm1           # xmm1 = mem[0],zero
	movq	%r8, -24(%rsp)                  # 8-byte Spill
.LBB0_2:                                # %.preheader154
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
                                        #       Child Loop BB0_7 Depth 3
                                        #         Child Loop BB0_9 Depth 4
	movq	%rdi, -88(%rsp)                 # 8-byte Spill
	cmpl	$0, -72(%rsp)                   # 4-byte Folded Reload
	jle	.LBB0_15
# %bb.3:                                # %.preheader153.preheader
                                        #   in Loop: Header=BB0_2 Depth=1
	xorl	%edi, %edi
.LBB0_4:                                # %.preheader153
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_7 Depth 3
                                        #         Child Loop BB0_9 Depth 4
	cmpl	$0, -56(%rsp)                   # 4-byte Folded Reload
	jle	.LBB0_5
# %bb.6:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB0_4 Depth=2
	movl	%edi, %edx
	imull	-48(%rsp), %edx                 # 4-byte Folded Reload
	leaq	1(%rdi), %rcx
	leal	-1(%rdi), %esi
	movl	-76(%rsp), %eax                 # 4-byte Reload
	movl	%eax, %r9d
	movq	%rcx, -32(%rsp)                 # 8-byte Spill
	imull	%ecx, %r9d
	movl	%r9d, -120(%rsp)                # 4-byte Spill
	imull	%eax, %esi
	movl	%esi, -116(%rsp)                # 4-byte Spill
	leal	1(%rdx), %ecx
	imull	%r8d, %ecx
	movl	%ecx, -124(%rsp)                # 4-byte Spill
	decl	%edx
	imull	%r8d, %edx
	movq	%rdx, -96(%rsp)                 # 8-byte Spill
                                        # kill: def $eax killed $eax def $rax
	imull	%edi, %eax
	movq	%rax, -104(%rsp)                # 8-byte Spill
	decl	%eax
	movl	%eax, -128(%rsp)                # 4-byte Spill
	xorl	%ebx, %ebx
.LBB0_7:                                # %.preheader
                                        #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB0_9 Depth 4
	testl	%r8d, %r8d
	jle	.LBB0_12
# %bb.8:                                # %.lr.ph
                                        #   in Loop: Header=BB0_7 Depth=3
	movslq	-120(%rsp), %rcx                # 4-byte Folded Reload
	movq	-88(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%rcx,8), %rsi
	movslq	-116(%rsp), %rcx                # 4-byte Folded Reload
	leaq	(%rax,%rcx,8), %rdx
	movslq	-124(%rsp), %rcx                # 4-byte Folded Reload
	leaq	(%rax,%rcx,8), %r8
	movslq	-96(%rsp), %rcx                 # 4-byte Folded Reload
	leaq	(%rax,%rcx,8), %r9
	movslq	-104(%rsp), %rcx                # 4-byte Folded Reload
	leaq	(%rax,%rcx,8), %rbp
	movq	-112(%rsp), %rax                # 8-byte Reload
	leaq	(%rax,%rcx,8), %rcx
	movl	-128(%rsp), %r12d               # 4-byte Reload
	xorl	%r14d, %r14d
.LBB0_9:                                #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        #       Parent Loop BB0_7 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	movsd	(%rbp,%r14), %xmm3              # xmm3 = mem[0],zero
	movapd	%xmm3, %xmm2
	mulsd	%xmm0, %xmm2
	testq	%r14, %r14
	je	.LBB0_11
# %bb.10:                               #   in Loop: Header=BB0_9 Depth=4
	movslq	%r12d, %r13
	movq	-88(%rsp), %rax                 # 8-byte Reload
	movsd	(%rax,%r13,8), %xmm3            # xmm3 = mem[0],zero
.LBB0_11:                               #   in Loop: Header=BB0_9 Depth=4
	leaq	(%r14,%rbp), %r13
	cmpq	%r14, %r11
	leaq	8(%r14,%rbp), %rax
	cmoveq	%r13, %rax
	leaq	(%r9,%r14), %r10
	testq	%rbx, %rbx
	cmoveq	%r13, %r10
	movsd	(%rax), %xmm4                   # xmm4 = mem[0],zero
	leaq	(%r8,%r14), %rax
	cmpq	-8(%rsp), %rbx                  # 8-byte Folded Reload
	cmoveq	%r13, %rax
	movsd	(%r10), %xmm5                   # xmm5 = mem[0],zero
	movsd	(%rax), %xmm6                   # xmm6 = mem[0],zero
	leaq	(%rdx,%r14), %rax
	testq	%rdi, %rdi
	cmoveq	%r13, %rax
	movsd	(%rax), %xmm7                   # xmm7 = mem[0],zero
	leaq	(%rsi,%r14), %rax
	cmpq	-16(%rsp), %rdi                 # 8-byte Folded Reload
	cmoveq	%r13, %rax
	movsd	(%rax), %xmm8                   # xmm8 = mem[0],zero
	mulsd	%xmm1, %xmm3
	addsd	%xmm3, %xmm2
	mulsd	%xmm1, %xmm4
	addsd	%xmm2, %xmm4
	mulsd	%xmm1, %xmm5
	addsd	%xmm4, %xmm5
	mulsd	%xmm1, %xmm6
	addsd	%xmm5, %xmm6
	mulsd	%xmm1, %xmm7
	addsd	%xmm6, %xmm7
	mulsd	%xmm1, %xmm8
	addsd	%xmm7, %xmm8
	movsd	%xmm8, (%rcx,%r14)
	addq	$8, %r14
	incl	%r12d
	cmpq	%r14, %r15
	jne	.LBB0_9
.LBB0_12:                               # %._crit_edge
                                        #   in Loop: Header=BB0_7 Depth=3
	incq	%rbx
	movq	-24(%rsp), %r8                  # 8-byte Reload
	addl	%r8d, -120(%rsp)                # 4-byte Folded Spill
	addl	%r8d, -116(%rsp)                # 4-byte Folded Spill
	addl	%r8d, -124(%rsp)                # 4-byte Folded Spill
	movq	-96(%rsp), %rax                 # 8-byte Reload
	addl	%r8d, %eax
	movq	%rax, -96(%rsp)                 # 8-byte Spill
	movq	-104(%rsp), %rax                # 8-byte Reload
	addl	%r8d, %eax
	movq	%rax, -104(%rsp)                # 8-byte Spill
	addl	%r8d, -128(%rsp)                # 4-byte Folded Spill
	cmpq	-48(%rsp), %rbx                 # 8-byte Folded Reload
	jne	.LBB0_7
# %bb.13:                               #   in Loop: Header=BB0_4 Depth=2
	movq	-32(%rsp), %rax                 # 8-byte Reload
	movq	%rax, %rdi
	jmp	.LBB0_14
.LBB0_5:                                # %.preheader153.._crit_edge157_crit_edge
                                        #   in Loop: Header=BB0_4 Depth=2
	incq	%rdi
	movq	%rdi, %rax
.LBB0_14:                               # %._crit_edge157
                                        #   in Loop: Header=BB0_4 Depth=2
	cmpq	-40(%rsp), %rax                 # 8-byte Folded Reload
	jne	.LBB0_4
.LBB0_15:                               # %._crit_edge159
                                        #   in Loop: Header=BB0_2 Depth=1
	movq	-64(%rsp), %rax                 # 8-byte Reload
	incl	%eax
	movq	-112(%rsp), %rdi                # 8-byte Reload
	movq	-88(%rsp), %rcx                 # 8-byte Reload
	movq	%rcx, -112(%rsp)                # 8-byte Spill
	movq	%rax, -64(%rsp)                 # 8-byte Spill
	cmpl	-80(%rsp), %eax                 # 4-byte Folded Reload
	jne	.LBB0_2
.LBB0_16:                               # %._crit_edge163
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z7stencilPdS_iiii, .Lfunc_end0-_Z7stencilPdS_iiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z5checkPdS_iii
.LCPI1_0:
	.quad	0x7fffffffffffffff              # double NaN
	.quad	0x7fffffffffffffff              # double NaN
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_1:
	.quad	0x3ee4f8b588e368f1              # double 1.0000000000000001E-5
	.text
	.globl	_Z5checkPdS_iii
	.type	_Z5checkPdS_iii,@function
_Z5checkPdS_iii:                        # @_Z5checkPdS_iii
	.cfi_startproc
# %bb.0:
                                        # kill: def $ecx killed $ecx def $rcx
	movq	%rdi, %rax
	movl	$.Lstr.1, %edi
	cmpl	$3, %r8d
	jl	puts@PLT                        # TAILCALL
# %bb.1:                                # %.preheader44.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	decl	%r8d
	movl	%r8d, %esi
	leal	-2(%rcx), %r9d
	movl	%r9d, 4(%rsp)                   # 4-byte Spill
	leal	1(%rcx), %r9d
	imull	%edx, %r9d
	incl	%r9d
	movl	%ecx, %r11d
	imull	%edx, %r11d
	decq	%rsi
	movl	$1, %ebp
	movapd	.LCPI1_0(%rip), %xmm1           # xmm1 = [NaN,NaN]
	movsd	.LCPI1_1(%rip), %xmm2           # xmm2 = mem[0],zero
.LBB1_2:                                # %.preheader44
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
                                        #       Child Loop BB1_6 Depth 3
	cmpl	$3, %ecx
	jl	.LBB1_10
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	$1, %r12d
	movl	%r9d, %r10d
.LBB1_4:                                # %.critedge.lr.ph
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_6 Depth 3
	movq	%rsi, %r13
	movl	%r10d, %r15d
.LBB1_6:                                # %.critedge
                                        #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movslq	%r15d, %r14
	movsd	(%rax,%r14,8), %xmm0            # xmm0 = mem[0],zero
	movapd	%xmm0, %xmm3
	subsd	(%rbx,%r14,8), %xmm3
	andpd	%xmm1, %xmm3
	ucomisd	%xmm2, %xmm3
	ja	.LBB1_7
# %bb.5:                                #   in Loop: Header=BB1_6 Depth=3
	incl	%r15d
	decq	%r13
	jne	.LBB1_6
# %bb.9:                                # %.critedge39
                                        #   in Loop: Header=BB1_4 Depth=2
	leal	1(%r12), %r14d
	addl	%edx, %r10d
	cmpl	4(%rsp), %r12d                  # 4-byte Folded Reload
	movl	%r14d, %r12d
	jne	.LBB1_4
.LBB1_10:                               # %.critedge41
                                        #   in Loop: Header=BB1_2 Depth=1
	incl	%ebp
	addl	%r11d, %r9d
	cmpl	%r8d, %ebp
	jne	.LBB1_2
	jmp	.LBB1_8
.LBB1_7:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	(%rbx,%r14,8), %xmm0            # xmm0 = mem[0],zero
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.1, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr, %edi
.LBB1_8:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end1:
	.size	_Z5checkPdS_iii, .Lfunc_end1-_Z5checkPdS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__baselinePdS_iii # -- Begin function _Z23__device_stub__baselinePdS_iii
	.type	_Z23__device_stub__baselinePdS_iii,@function
_Z23__device_stub__baselinePdS_iii:     # @_Z23__device_stub__baselinePdS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8baselinePdS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z23__device_stub__baselinePdS_iii, .Lfunc_end2-_Z23__device_stub__baselinePdS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__baseoptPdS_iii # -- Begin function _Z22__device_stub__baseoptPdS_iii
	.type	_Z22__device_stub__baseoptPdS_iii,@function
_Z22__device_stub__baseoptPdS_iii:      # @_Z22__device_stub__baseoptPdS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7baseoptPdS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__baseoptPdS_iii, .Lfunc_end3-_Z22__device_stub__baseoptPdS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__rocPKdPdiii  # -- Begin function _Z18__device_stub__rocPKdPdiii
	.type	_Z18__device_stub__rocPKdPdiii,@function
_Z18__device_stub__rocPKdPdiii:         # @_Z18__device_stub__rocPKdPdiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3rocPKdPdiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z18__device_stub__rocPKdPdiii, .Lfunc_end4-_Z18__device_stub__rocPKdPdiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI5_0:
	.quad	0x408f400000000000              # double 1000
.LCPI5_1:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$168, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movq	16(%rsi), %rdi
	callq	atoi
	movl	%eax, %r15d
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	32(%rbx), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	40(%rbx), %rdi
	callq	atoi
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	movq	%r14, 104(%rsp)                 # 8-byte Spill
                                        # kill: def $r14d killed $r14d killed $r14 def $r14
	movq	%r15, 24(%rsp)                  # 8-byte Spill
	imull	%r15d, %r14d
	movl	%ebp, %eax
	imull	%r14d, %eax
	movl	%eax, 8(%rsp)                   # 4-byte Spill
	cmpl	$216000001, %eax                # imm = 0xCDFE601
	movl	$1, %eax
	movl	$8, %r12d
	cmovll	%eax, %r12d
	leal	-1(%r12), %ecx
	testl	%ebp, %ecx
	movl	%ebp, 80(%rsp)                  # 4-byte Spill
	movl	%ebp, %eax
	cltd
	je	.LBB5_1
# %bb.2:
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	jmp	.LBB5_3
.LBB5_1:
	idivl	%r12d
	movl	%eax, %edx
.LBB5_3:
	movq	%rax, 32(%rsp)                  # 8-byte Spill
                                        # kill: def $eax killed $eax killed $rax def $rax
	imull	%r14d, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%edx, 4(%rsp)                   # 4-byte Spill
	movl	%edx, %eax
	imull	%r14d, %eax
	movl	%eax, (%rsp)                    # 4-byte Spill
	movl	8(%rsp), %eax                   # 4-byte Reload
	movl	%eax, %ebp
	cmpl	$216000001, %eax                # imm = 0xCDFE601
	jl	.LBB5_5
# %bb.4:
	movq	16(%rsp), %rax                  # 8-byte Reload
	leal	(%rax,%r14,2), %ebp
	imull	%ecx, %ebp
	addl	(%rsp), %ebp                    # 4-byte Folded Reload
.LBB5_5:
	movl	%ecx, 76(%rsp)                  # 4-byte Spill
	movslq	%ebp, %r15
	leaq	(,%r15,8), %rax
	testl	%r15d, %r15d
	movq	$-1, %rbx
	cmovnsq	%rax, %rbx
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, %r13
	movq	%rbx, %rdi
	callq	_Znam
	testl	%r15d, %r15d
	jle	.LBB5_8
# %bb.6:                                # %.lr.ph.preheader
	movl	%ebp, %esi
	xorl	%ecx, %ecx
	movabsq	$4607182418800017408, %rdx      # imm = 0x3FF0000000000000
.LBB5_7:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%rdx, (%r13,%rcx,8)
	movq	%rdx, (%rax,%rcx,8)
	incq	%rcx
	cmpq	%rcx, %rsi
	jne	.LBB5_7
.LBB5_8:                                # %._crit_edge173
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	movq	%r13, 120(%rsp)                 # 8-byte Spill
	leaq	152(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	56(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%ebp, %ebp
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$22, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	addl	%r14d, (%rsp)                   # 4-byte Folded Spill
	incl	4(%rsp)                         # 4-byte Folded Spill
	movq	16(%rsp), %rax                  # 8-byte Reload
	leal	(%rax,%r14,2), %ecx
	movl	%ecx, 72(%rsp)                  # 4-byte Spill
	movq	32(%rsp), %rsi                  # 8-byte Reload
	leal	2(%rsi), %ecx
	movl	%ecx, 68(%rsp)                  # 4-byte Spill
	addl	%r14d, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	incl	%esi
	movq	24(%rsp), %rcx                  # 8-byte Reload
	leal	127(%rcx), %eax
                                        # kill: def $ecx killed $ecx killed $rcx def $rcx
	addl	$254, %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$7, %ecx
	movq	104(%rsp), %rdx                 # 8-byte Reload
	movl	%edx, %eax
	incl	%eax
	shrl	$31, %eax
	leal	(%rdx,%rax), %r13d
	incl	%r13d
	sarl	%r13d
	shlq	$32, %r13
	orq	%rcx, %r13
	movabsq	$8589934720, %rbx               # imm = 0x200000080
	xorl	%r14d, %r14d
	movq	%r12, 128(%rsp)                 # 8-byte Spill
	movq	%rsi, 32(%rsp)                  # 8-byte Spill
.LBB5_9:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_14 Depth 2
	cmpl	76(%rsp), %ebp                  # 4-byte Folded Reload
	movl	(%rsp), %r15d                   # 4-byte Reload
	cmovll	72(%rsp), %r15d                 # 4-byte Folded Reload
	movl	4(%rsp), %r12d                  # 4-byte Reload
	cmovll	68(%rsp), %r12d                 # 4-byte Folded Reload
	movq	%rbp, 144(%rsp)                 # 8-byte Spill
	testl	%ebp, %ebp
	cmovel	16(%rsp), %r15d                 # 4-byte Folded Reload
	cmovel	%esi, %r12d
	movl	8(%rsp), %eax                   # 4-byte Reload
	cmpl	$216000001, %eax                # imm = 0xCDFE601
	cmovll	%eax, %r15d
	cmovll	80(%rsp), %r12d                 # 4-byte Folded Reload
	movslq	%r15d, %rbp
	shlq	$3, %rbp
	leaq	40(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	88(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movq	40(%rsp), %rdi
	movl	%r14d, 84(%rsp)                 # 4-byte Spill
	movslq	%r14d, %r14
	movq	120(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%r14,8), %rsi
	movq	%rsi, 136(%rsp)                 # 8-byte Spill
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	88(%rsp), %rdi
	movq	112(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%r14,8), %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	12(%rsp), %eax                  # 4-byte Reload
	movl	%eax, %r14d
	testl	%eax, %eax
	jle	.LBB5_10
.LBB5_14:                               # %.lr.ph176
                                        #   Parent Loop BB5_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_16
# %bb.15:                               #   in Loop: Header=BB5_14 Depth=2
	movq	40(%rsp), %rdi
	movq	88(%rsp), %rsi
	movq	24(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movq	104(%rsp), %rcx                 # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	%r12d, %r8d
	callq	_Z18__device_stub__rocPKdPdiii
.LBB5_16:                               #   in Loop: Header=BB5_14 Depth=2
	movq	40(%rsp), %rax
	movq	88(%rsp), %rcx
	movq	%rcx, 40(%rsp)
	movq	%rax, 88(%rsp)
	decl	%r14d
	jne	.LBB5_14
.LBB5_10:                               # %._crit_edge177
                                        #   in Loop: Header=BB5_9 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB5_12
# %bb.11:                               #   in Loop: Header=BB5_9 Depth=1
	movl	$.Lstr.2, %edi
	callq	puts@PLT
.LBB5_12:                               #   in Loop: Header=BB5_9 Depth=1
	movq	40(%rsp), %rsi
	movq	136(%rsp), %rdi                 # 8-byte Reload
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	84(%rsp), %r14d                 # 4-byte Reload
	addl	%r15d, %r14d
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	144(%rsp), %rbp                 # 8-byte Reload
	incl	%ebp
	movq	128(%rsp), %r12                 # 8-byte Reload
	cmpl	%r12d, %ebp
	movq	32(%rsp), %rsi                  # 8-byte Reload
	jne	.LBB5_9
# %bb.13:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	56(%rsp), %rdi
	callq	hipEventSynchronize
	movq	152(%rsp), %rsi
	movq	56(%rsp), %rdx
	leaq	164(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	leaq	40(%rsp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	leaq	88(%rsp), %r15
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r15), %rax
	movq	8(%r15), %rcx
	subq	(%r14), %rax
	cvtsi2sd	%rax, %xmm0
	mulsd	.LCPI5_0(%rip), %xmm0
	subq	8(%r14), %rcx
	cvtsi2sd	%rcx, %xmm1
	mulsd	.LCPI5_1(%rip), %xmm1
	addsd	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	cvtsd2ss	%xmm1, %xmm0
	movss	%xmm0, 24(%rsp)                 # 4-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtsi2ssl	12(%rsp), %xmm0         # 4-byte Folded Reload
	movss	24(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movl	$.L.str.7, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.8, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$168, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8baselinePdS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7baseoptPdS_iii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3rocPKdPdiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" "
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d\n"
	.size	.L.str.1, 4

	.type	_Z8baselinePdS_iii,@object      # @_Z8baselinePdS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z8baselinePdS_iii
	.p2align	3, 0x0
_Z8baselinePdS_iii:
	.quad	_Z23__device_stub__baselinePdS_iii
	.size	_Z8baselinePdS_iii, 8

	.type	_Z7baseoptPdS_iii,@object       # @_Z7baseoptPdS_iii
	.globl	_Z7baseoptPdS_iii
	.p2align	3, 0x0
_Z7baseoptPdS_iii:
	.quad	_Z22__device_stub__baseoptPdS_iii
	.size	_Z7baseoptPdS_iii, 8

	.type	_Z3rocPKdPdiii,@object          # @_Z3rocPKdPdiii
	.globl	_Z3rocPKdPdiii
	.p2align	3, 0x0
_Z3rocPKdPdiii:
	.quad	_Z18__device_stub__rocPKdPdiii
	.size	_Z3rocPKdPdiii, 8

	.type	.L.str.4,@object                # @.str.4
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.4:
	.asciz	"start gpu computing..."
	.size	.L.str.4, 23

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"CPU time:"
	.size	.L.str.6, 10

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	" ms"
	.size	.L.str.7, 4

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"baseline: elapsed time = %f ms\n"
	.size	.L.str.8, 32

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8baselinePdS_iii"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7baseoptPdS_iii"
	.size	.L__unnamed_2, 18

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z3rocPKdPdiii"
	.size	.L__unnamed_3, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Wrong!!!!!!!!"
	.size	.Lstr, 14

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Right!!!!!!"
	.size	.Lstr.1, 12

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"cudawrong!!!"
	.size	.Lstr.2, 13

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__baselinePdS_iii
	.addrsig_sym _Z22__device_stub__baseoptPdS_iii
	.addrsig_sym _Z18__device_stub__rocPKdPdiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZSt4cout
	.addrsig_sym _Z8baselinePdS_iii
	.addrsig_sym _Z7baseoptPdS_iii
	.addrsig_sym _Z3rocPKdPdiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8baselinePdS_iii      ; -- Begin function _Z8baselinePdS_iii
	.globl	_Z8baselinePdS_iii
	.p2align	8
	.type	_Z8baselinePdS_iii,@function
_Z8baselinePdS_iii:                     ; @_Z8baselinePdS_iii
; %bb.0:
	s_load_b32 s8, s[0:1], 0x2c
	v_and_b32_e32 v2, 0x3ff, v0
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s9, s13, s4
	s_mov_b32 s4, exec_lo
	v_add_nc_u32_e32 v1, s9, v2
	v_cmpx_lt_i32_e32 -1, v1
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_load_b32 s2, s[2:3], 0x8
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v3, s2
	s_sub_i32 s7, 0, s2
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v3
	v_bfe_u32 v3, v0, 10, 10
	s_mul_i32 s7, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s3, s7
	s_add_i32 s3, s3, s7
	s_lshr_b32 s7, s8, 16
	s_mul_hi_u32 s3, s6, s3
	s_mul_i32 s7, s14, s7
	s_mul_i32 s8, s3, s2
	s_add_i32 s10, s3, 1
	s_sub_i32 s8, s6, s8
	v_add_nc_u32_e32 v4, s7, v3
	s_sub_i32 s11, s8, s2
	s_cmp_ge_u32 s8, s2
	s_cselect_b32 s3, s10, s3
	s_cselect_b32 s8, s11, s8
	s_add_i32 s10, s3, 1
	s_cmp_ge_u32 s8, s2
	v_cmp_gt_i32_e64 s2, s5, v4
	s_cselect_b32 s8, s10, s3
	v_cmp_lt_i32_e64 s3, -1, v4
	s_mul_i32 s12, s8, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_and_b32 s2, vcc_lo, s2
	s_add_i32 s8, s12, s8
	s_and_b32 s2, s2, s3
	s_min_u32 s13, s8, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s12, s13
	s_cselect_b32 s3, -1, 0
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_4
; %bb.2:                                ; %.lr.ph
	s_mul_i32 s2, s12, s5
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_add3_u32 v0, s7, s2, v3
	s_add_i32 s11, s5, -1
	s_add_i32 s10, s4, -1
	s_load_b128 s[0:3], s[0:1], 0x0
	v_cndmask_b32_e64 v9, 0, s4, vcc_lo
	v_mul_lo_u32 v0, s4, v0
	v_cmp_ne_u32_e32 vcc_lo, s11, v4
	s_add_i32 s14, s6, -1
	s_add_i32 s6, s12, 1
	s_mul_i32 s8, s5, s4
	s_mul_i32 s5, s5, s6
	v_cndmask_b32_e64 v18, 0, s4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s10, v1
	v_add_nc_u32_e32 v2, v2, v0
	v_ashrrev_i32_e32 v10, 31, v9
	s_mov_b32 s11, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v11, s9, v2
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_add3_u32 v2, s7, s5, v3
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v18, v11, v18
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo
	v_lshlrev_b64 v[12:13], 3, v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 3, v[4:5]
	v_lshlrev_b64 v[16:17], 3, v[9:10]
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v19, 31, v18
	v_mul_lo_u32 v2, s4, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s0, v12
	v_lshlrev_b64 v[7:8], 3, v[6:7]
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v13, vcc_lo
	v_add_co_u32 v5, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s0, v14
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v15, vcc_lo
	v_sub_co_u32 v11, vcc_lo, v12, v16
	v_sub_co_ci_u32_e32 v12, vcc_lo, v13, v17, vcc_lo
	v_lshlrev_b64 v[13:14], 3, v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s0, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s0, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
	s_mov_b32 s2, 0x9999999a
	s_mov_b32 s3, 0x3fb99999
	s_lshl_b64 s[4:5], s[8:9], 3
	s_mov_b64 s[6:7], 0
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v15, vcc_lo, v7, s6
	v_add_co_ci_u32_e32 v16, vcc_lo, s7, v8, vcc_lo
	v_add_co_u32 v17, vcc_lo, v9, s6
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v19, vcc_lo, v13, s6
	s_clause 0x1
	global_load_b64 v[15:16], v[15:16], off
	global_load_b64 v[17:18], v[17:18], off
	v_add_co_ci_u32_e32 v20, vcc_lo, s7, v14, vcc_lo
	v_add_co_u32 v21, vcc_lo, v11, s6
	v_add_co_ci_u32_e32 v22, vcc_lo, s7, v12, vcc_lo
	global_load_b64 v[19:20], v[19:20], off
	s_cmp_lg_u32 s12, 0
	global_load_b64 v[21:22], v[21:22], off
	s_cselect_b32 s16, s8, 0
	s_cmp_eq_u32 s14, s12
	s_cselect_b32 vcc_lo, -1, 0
	s_ashr_i32 s17, s16, 31
	v_cndmask_b32_e32 v23, v2, v0, vcc_lo
	s_lshl_b64 s[16:17], s[16:17], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_sub_u32 s9, s6, s16
	s_subb_u32 s10, s7, s17
	v_add_nc_u32_e32 v23, v23, v1
	s_add_i32 s12, s12, 1
	v_add_nc_u32_e32 v1, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 3, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s0, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s1, v24, vcc_lo
	v_add_co_u32 v25, vcc_lo, v3, s9
	v_add_co_ci_u32_e32 v26, vcc_lo, s10, v4, vcc_lo
	global_load_b64 v[23:24], v[23:24], off
	v_add_co_u32 v27, vcc_lo, v3, s6
	global_load_b64 v[25:26], v[25:26], off
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v4, vcc_lo
	s_mov_b32 s10, s2
	global_load_b64 v[27:28], v[27:28], off
	s_waitcnt vmcnt(6)
	v_mul_f64 v[15:16], v[15:16], s[2:3]
	s_waitcnt vmcnt(5)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[15:16], v[17:18], s[2:3], v[15:16]
	v_add_co_u32 v17, vcc_lo, v5, s6
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v6, vcc_lo
	s_add_u32 s6, s6, s4
	s_addc_u32 s7, s7, s5
	s_cmp_lt_i32 s12, s13
	s_waitcnt vmcnt(4)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[19:20], s[2:3], v[15:16]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[15:16], v[21:22], s[2:3], v[15:16]
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[23:24], s[2:3], v[15:16]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[15:16], v[25:26], s[2:3], v[15:16]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[15:16], v[27:28], s[10:11], v[15:16]
	global_store_b64 v[17:18], v[15:16], off
	s_cbranch_scc1 .LBB0_3
.LBB0_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8baselinePdS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8baselinePdS_iii, .Lfunc_end0-_Z8baselinePdS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 972
; NumSgprs: 20
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7baseoptPdS_iii       ; -- Begin function _Z7baseoptPdS_iii
	.globl	_Z7baseoptPdS_iii
	.p2align	8
	.type	_Z7baseoptPdS_iii,@function
_Z7baseoptPdS_iii:                      ; @_Z7baseoptPdS_iii
; %bb.0:
	s_load_b32 s8, s[0:1], 0x2c
	v_and_b32_e32 v10, 0x3ff, v0
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s13, s13, s4
	s_mov_b32 s4, exec_lo
	v_add_nc_u32_e32 v1, s13, v10
	v_cmpx_lt_i32_e32 -1, v1
	s_cbranch_execz .LBB1_4
; %bb.1:
	s_load_b32 s2, s[2:3], 0x8
	s_load_b128 s[4:7], s[0:1], 0x10
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v2, s2
	s_sub_i32 s7, 0, s2
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v2
	s_mul_i32 s7, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s3, s7
	s_add_i32 s3, s3, s7
	s_lshr_b32 s7, s8, 16
	s_mul_hi_u32 s3, s6, s3
	s_mul_i32 s14, s14, s7
	s_mul_i32 s8, s3, s2
	v_add_nc_u32_e32 v6, s14, v0
	s_sub_i32 s7, s6, s8
	s_add_i32 s8, s3, 1
	s_sub_i32 s9, s7, s2
	s_cmp_ge_u32 s7, s2
	s_cselect_b32 s3, s8, s3
	s_cselect_b32 s7, s9, s7
	s_add_i32 s8, s3, 1
	s_cmp_ge_u32 s7, s2
	v_cmp_gt_i32_e64 s2, s5, v6
	s_cselect_b32 s7, s8, s3
	v_cmp_lt_i32_e64 s3, -1, v6
	s_mul_i32 s10, s7, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_and_b32 s2, vcc_lo, s2
	s_add_i32 s7, s10, s7
	s_and_b32 s2, s2, s3
	s_min_u32 s11, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s10, s11
	s_cselect_b32 s3, -1, 0
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_4
; %bb.2:                                ; %.lr.ph
	v_mad_u64_u32 v[2:3], null, v6, s4, v[1:2]
	s_mul_i32 s8, s5, s4
	s_add_i32 s7, s4, -1
	s_add_i32 s9, s5, -1
	s_load_b128 s[0:3], s[0:1], 0x0
	s_cmp_eq_u32 s10, 0
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, s10, s8, v[2:3]
	s_add_i32 s12, s6, -1
	v_subrev_nc_u32_e32 v3, s8, v7
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v3, v2, vcc_lo
	v_lshlrev_b64 v[4:5], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v11, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[4:5], v[2:3], off
	global_load_b64 v[2:3], v[11:12], off
	v_cmp_ne_u32_e32 vcc_lo, 0, v6
	v_cndmask_b32_e64 v9, 0, s4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_sub_nc_u32_e32 v13, v7, v9
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s7, v1
	s_mul_i32 s7, s10, s5
	v_add3_u32 v7, s14, s7, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v9, v8
	v_cndmask_b32_e64 v14, 0, 1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s9, v6
	s_add_i32 s7, s10, 1
	v_mul_lo_u32 v16, s4, v7
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_lshlrev_b32_e32 v14, 3, v14
	v_cndmask_b32_e64 v17, 0, s4, vcc_lo
	s_mul_i32 s5, s5, s7
	s_ashr_i32 s9, s8, 31
	v_add3_u32 v0, s14, s5, v0
	v_add_co_u32 v6, vcc_lo, v11, v14
	v_ashrrev_i32_e32 v18, 31, v17
	v_add3_u32 v19, v10, v16, s13
	v_ashrrev_i32_e32 v14, 31, v13
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[17:18], 3, v[17:18]
	v_add_co_u32 v8, vcc_lo, v11, v8
	v_ashrrev_i32_e32 v20, 31, v19
	v_add_co_ci_u32_e32 v9, vcc_lo, v12, v9, vcc_lo
	v_lshlrev_b64 v[13:14], 3, v[13:14]
	v_add_co_u32 v10, vcc_lo, v11, v17
	v_add_co_ci_u32_e32 v11, vcc_lo, v12, v18, vcc_lo
	v_lshlrev_b64 v[17:18], 3, v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s0, v13
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v14, vcc_lo
	v_mul_lo_u32 v0, s4, v0
	v_add_co_u32 v14, vcc_lo, s2, v17
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v18, vcc_lo
	s_mov_b32 s2, 0x9999999a
	s_mov_b32 s3, 0x3fb99999
	s_lshl_b64 s[4:5], s[8:9], 3
	s_mov_b32 s7, 0x3fd99999
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	s_clause 0x3
	global_load_b64 v[17:18], v[8:9], off
	global_load_b64 v[19:20], v[6:7], off
	global_load_b64 v[21:22], v[10:11], off
	global_load_b64 v[23:24], v[12:13], off
	s_cmp_eq_u32 s12, s10
	s_waitcnt vmcnt(4)
	v_dual_mov_b32 v26, v3 :: v_dual_mov_b32 v25, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_mov_b32 s6, s2
	v_cndmask_b32_e32 v2, v0, v16, vcc_lo
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lt_i32 s10, s11
	v_add_nc_u32_e32 v2, v2, v1
	v_add_nc_u32_e32 v1, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(4)
	v_mul_f64 v[17:18], v[17:18], s[2:3]
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[19:20], s[2:3], v[17:18]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[17:18], v[21:22], s[2:3], v[17:18]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[23:24], s[2:3], v[17:18]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[17:18], v[2:3], s[2:3], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], s[2:3], v[17:18]
	v_fma_f64 v[17:18], v[25:26], s[6:7], v[4:5]
	v_dual_mov_b32 v4, v25 :: v_dual_mov_b32 v5, v26
	global_store_b64 v[14:15], v[17:18], off
	v_add_co_u32 v14, vcc_lo, v14, s4
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	s_cbranch_scc1 .LBB1_3
.LBB1_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7baseoptPdS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7baseoptPdS_iii, .Lfunc_end1-_Z7baseoptPdS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 936
; NumSgprs: 18
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3rocPKdPdiii          ; -- Begin function _Z3rocPKdPdiii
	.globl	_Z3rocPKdPdiii
	.p2align	8
	.type	_Z3rocPKdPdiii,@function
_Z3rocPKdPdiii:                         ; @_Z3rocPKdPdiii
; %bb.0:
	s_load_b32 s8, s[0:1], 0x2c
	v_and_b32_e32 v8, 0x3ff, v0
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s13, s13, s4
	s_mov_b32 s4, exec_lo
	v_add_nc_u32_e32 v1, s13, v8
	v_cmpx_lt_i32_e32 -1, v1
	s_cbranch_execz .LBB2_4
; %bb.1:
	s_load_b32 s2, s[2:3], 0x8
	s_load_b128 s[4:7], s[0:1], 0x10
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v2, s2
	s_sub_i32 s7, 0, s2
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v2
	s_mul_i32 s7, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s3, s7
	s_add_i32 s3, s3, s7
	s_lshr_b32 s7, s8, 16
	s_mul_hi_u32 s3, s6, s3
	s_mul_i32 s9, s14, s7
	s_mul_i32 s8, s3, s2
	v_add_nc_u32_e32 v2, s9, v0
	s_sub_i32 s7, s6, s8
	s_add_i32 s8, s3, 1
	s_sub_i32 s10, s7, s2
	s_cmp_ge_u32 s7, s2
	s_cselect_b32 s3, s8, s3
	s_cselect_b32 s7, s10, s7
	s_add_i32 s8, s3, 1
	s_cmp_ge_u32 s7, s2
	v_cmp_gt_i32_e64 s2, s5, v2
	s_cselect_b32 s8, s8, s3
	v_cmp_lt_i32_e64 s3, -1, v2
	s_mul_i32 s7, s8, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_and_b32 s2, vcc_lo, s2
	s_add_i32 s8, s7, s8
	s_and_b32 s2, s2, s3
	s_min_u32 s14, s8, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s7, s14
	s_cselect_b32 s3, -1, 0
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_4
; %bb.2:                                ; %.lr.ph
	v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
	s_mul_i32 s8, s5, s4
	s_load_b128 s[0:3], s[0:1], 0x0
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_add_i32 s10, s4, -1
	s_mul_i32 s12, s7, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s7, s8, v[3:4]
	v_cndmask_b32_e64 v6, 0, -1, vcc_lo
	v_mov_b32_e32 v7, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[9:10], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[6:7]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
	v_add_co_u32 v5, vcc_lo, v9, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s10, v1
	s_add_i32 s10, s5, -1
	s_cmp_eq_u32 s7, 0
	global_load_b64 v[11:12], v[5:6], off
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v5, 3, v5
	v_add_co_u32 v5, vcc_lo, v9, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, s10, v2
	s_mov_b32 s10, 0x9999999a
	s_mov_b32 s11, 0x3fb99999
	global_load_b64 v[13:14], v[5:6], off
	v_cndmask_b32_e64 v5, 0, s4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v9, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	global_load_b64 v[15:16], v[5:6], off
	v_cndmask_b32_e64 v2, 0, s4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v4, v2
	v_subrev_nc_u32_e32 v2, s8, v4
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	global_load_b64 v[17:18], v[5:6], off
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[2:3], off
	global_load_b64 v[4:5], v[9:10], off
	v_add3_u32 v9, s9, s12, v0
	s_add_i32 s12, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s5, s5, s12
	v_mul_lo_u32 v10, s4, v9
	v_add3_u32 v0, s9, s5, v0
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, s4, v0
	s_add_i32 s4, s6, -1
	v_add3_u32 v8, v8, v10, s13
	s_mov_b32 s12, 0x9999999a
	s_mov_b32 s13, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	s_lshl_b64 s[2:3], s[8:9], 3
	s_waitcnt vmcnt(5)
	v_mul_f64 v[2:3], v[11:12], s[10:11]
	s_waitcnt vmcnt(4)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[13:14], s[10:11], v[2:3]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[2:3], v[15:16], s[10:11], v[2:3]
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[17:18], s[10:11], v[2:3]
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s4, s7
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v12, v5 :: v_dual_mov_b32 v11, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_add_i32 s7, s7, 1
	v_cndmask_b32_e32 v4, v0, v10, vcc_lo
	s_cmp_lt_i32 s7, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v1
	v_add_nc_u32_e32 v1, s8, v1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[13:14], v[4:5], s[10:11], v[2:3]
	v_fma_f64 v[6:7], v[6:7], s[10:11], v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], s[12:13], v[6:7]
	v_dual_mov_b32 v6, v11 :: v_dual_mov_b32 v7, v12
	global_store_b64 v[8:9], v[13:14], off
	v_add_co_u32 v8, vcc_lo, v8, s2
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	s_cbranch_scc1 .LBB2_3
.LBB2_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3rocPKdPdiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z3rocPKdPdiii, .Lfunc_end2-_Z3rocPKdPdiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 968
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8baselinePdS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z8baselinePdS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7baseoptPdS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7baseoptPdS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3rocPKdPdiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3rocPKdPdiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
