/*
 * Compute beta parameters.
 *
 * The so-called beta parameters were developed in SNO as a measure of event
 * isotropy:
 *
 *     The lth beta parameter, beta_l, is defined as the average value of the
 *     Legendre polynomial, P_l, of the cosine of the angle between each pair
 *     PMT hits in the event.
 *
 *         beta_l = <P_l(cos(theta_ik)> where i != k
 *
 *     Again, the angle is taken with respect to the fitted vertex position.
 *     The combination beta_14 = beta_1 + 4 * beta_4 was selected by the SNO
 *     collaboration for use in signal extraction due to the good separability
 *     it provides and the ease of parameterisation of the Gaussian-like
 *     distribution.
 *
 *     - Measurement of the 8B Solar Neutrino Energy Spectrum at the Sudbury
 *       Neutrino Observatory, Jeanne R. Wilson, p. 179 (Ph.D. Thesis)
*/

#include <map>
#include <string>
#include <cuda.h>
#include <stdio.h>

__global__ void get_coeffs(int2* pairs, float3* hit_pos, float3* fit_pos, float* p1, float* p4, int n) {
    int i = threadIdx.x + blockIdx.x * blockDim.x;

    if (i < n) {
        int2 pair = pairs[i];

        float3 A = hit_pos[pair.x];
        float3 B = hit_pos[pair.y];
        float3 C = *fit_pos;

        float c = sqrtf((A.x-B.x)*(A.x-B.x) + (A.y-B.y)*(A.y-B.y) + (A.z-B.z)*(A.z-B.z));
        float a = sqrtf((C.x-B.x)*(C.x-B.x) + (C.y-B.y)*(C.y-B.y) + (C.z-B.z)*(C.z-B.z));
        float b = sqrtf((C.x-A.x)*(C.x-A.x) + (C.y-A.y)*(C.y-A.y) + (C.z-A.z)*(C.z-A.z));

        // dust off that trig!
        p1[i] = (float)(-0.5) * (c*c - a*a - b*b) / (a*b);

        // Legendre P4(x) = (1/8) (25x**4 - 30x**2 + 3)
        p4[i] = (float)(0.125) * (25*p1[i]*p1[i]*p1[i]*p1[i] - 30*p1[i]*p1[i] + 3);
    }
}

float get_beta14(float3 &fit_pos, float3* hit_pos, int nhits) {
    // compute list of pmt pairs (this isn't really necessary)
    const int npairs = nhits * (nhits - 1) / 2;
    int2* pairs = (int2*) malloc(npairs * sizeof(int2));
    unsigned pidx = 0;
    for (unsigned i=0; i<nhits-1; i++) {
        for (unsigned j=i+1; j<nhits; j++) {
            pairs[pidx] = make_int2(i, j);
            pidx++;
        }
    }

    // allocate device memory and copy over
    int2* pairs_device;
    float* p1_device;
    float* p4_device;
    float3* hit_pos_device;
    float3* fit_pos_device;

    cudaMalloc(&pairs_device, npairs * sizeof(int2));
    cudaMalloc(&p1_device, npairs * sizeof(float));
    cudaMalloc(&p4_device, npairs * sizeof(float));
    cudaMalloc(&hit_pos_device, nhits * sizeof(float3));
    cudaMalloc(&fit_pos_device, sizeof(float3));

    cudaMemcpy(pairs_device, pairs, npairs * sizeof(int2), cudaMemcpyHostToDevice);
    cudaMemcpy(hit_pos_device, hit_pos, nhits * sizeof(float3), cudaMemcpyHostToDevice);
    cudaMemcpy(fit_pos_device, &fit_pos, sizeof(float3), cudaMemcpyHostToDevice);

    // execute kernel and retreive results
    int blocksize = 512;
    int nblocks = npairs / blocksize + 1;
    get_coeffs<<<nblocks, blocksize>>>(pairs_device, hit_pos_device, fit_pos_device, p1_device, p4_device, npairs);

    float* p1 = (float*) malloc(npairs * sizeof(float));
    float* p4 = (float*) malloc(npairs * sizeof(float));
    cudaMemcpy(p1, p1_device, npairs * sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(p4, p4_device, npairs * sizeof(float), cudaMemcpyDeviceToHost);

    // compute average
    float p1ave = 0.0;
    float p4ave = 0.0;
    for (unsigned i=0; i<npairs; i++) {
        p1ave += p1[i];
        p4ave += p4[i];
    }

    p1ave /= npairs;
    p4ave /= npairs;

    float beta14 = p1ave + 4.0 * p4ave;

    free(pairs);
    free(p1);
    free(p4);
    cudaFree(pairs_device);
    cudaFree(hit_pos_device);
    cudaFree(fit_pos_device);
    cudaFree(p1_device);
    cudaFree(p4_device);

    return beta14;
}


	.file	"tmpxft_0031ae41_00000000-6_beta14.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3431:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3431:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z51__device_stub__Z10get_coeffsP4int2P6float3S2_PfS3_iP4int2P6float3S2_PfS3_i
	.type	_Z51__device_stub__Z10get_coeffsP4int2P6float3S2_PfS3_iP4int2P6float3S2_PfS3_i, @function
_Z51__device_stub__Z10get_coeffsP4int2P6float3S2_PfS3_iP4int2P6float3S2_PfS3_i:
.LFB3453:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z10get_coeffsP4int2P6float3S2_PfS3_i(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3453:
	.size	_Z51__device_stub__Z10get_coeffsP4int2P6float3S2_PfS3_iP4int2P6float3S2_PfS3_i, .-_Z51__device_stub__Z10get_coeffsP4int2P6float3S2_PfS3_iP4int2P6float3S2_PfS3_i
	.globl	_Z10get_coeffsP4int2P6float3S2_PfS3_i
	.type	_Z10get_coeffsP4int2P6float3S2_PfS3_i, @function
_Z10get_coeffsP4int2P6float3S2_PfS3_i:
.LFB3454:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z10get_coeffsP4int2P6float3S2_PfS3_iP4int2P6float3S2_PfS3_i
	.cfi_endproc
.LFE3454:
	.size	_Z10get_coeffsP4int2P6float3S2_PfS3_i, .-_Z10get_coeffsP4int2P6float3S2_PfS3_i
	.globl	_Z10get_beta14R6float3PS_i
	.type	_Z10get_beta14R6float3PS_i, @function
_Z10get_beta14R6float3PS_i:
.LFB3428:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$2, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%edx, %rbx
	leal	-1(%rbx), %r14d
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 16(%rsp)
	movq	%rsi, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	movl	%r14d, %eax
	imull	%ebx, %eax
	cltd
	movl	%eax, 12(%rsp)
	idivl	%ecx
	movslq	%eax, %rbp
	leaq	0(,%rbp,8), %r15
	movq	%rbp, %r13
	movq	%r15, %rdi
	call	malloc@PLT
	xorl	%esi, %esi
	xorl	%r9d, %r9d
	movq	%rax, %r12
	xorl	%eax, %eax
.L9:
	cmpl	%r14d, %eax
	jnb	.L18
	leal	1(%rax), %edx
	movl	%esi, %edi
	movl	%edx, %ecx
.L10:
	cmpl	%ebx, %ecx
	jnb	.L19
	movl	%edi, %r10d
	incl	%edi
	leaq	(%r12,%r10,8), %r10
	movl	%ecx, 4(%r10)
	incl	%ecx
	movl	%eax, (%r10)
	jmp	.L10
.L19:
	movl	%ebx, %eax
	subl	%edx, %eax
	cmpl	%edx, %ebx
	cmovb	%r9d, %eax
	addl	%eax, %esi
	movl	%edx, %eax
	jmp	.L9
.L18:
	imulq	$12, %rbx, %rbx
	salq	$2, %rbp
	leaq	40(%rsp), %rdi
	movq	%r15, %rsi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$12, %esi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	movq	%r15, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	64(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rsi
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movl	$12, %edx
	call	cudaMemcpy@PLT
	movl	12(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1024, %ecx
	cltd
	idivl	%ecx
	movl	$8388609, %edx
	movl	$1, %ecx
	salq	$9, %rdx
	incl	%eax
	movl	%eax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 84(%rsp)
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	56(%rsp), %r8
	movq	48(%rsp), %rcx
	movl	%r13d, %r9d
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z51__device_stub__Z10get_coeffsP4int2P6float3S2_PfS3_iP4int2P6float3S2_PfS3_i
.L13:
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r14
	call	malloc@PLT
	movq	48(%rsp), %rsi
	movq	%rbp, %rdx
	movq	%r14, %rdi
	movl	$2, %ecx
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rsi
	movq	%rbp, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
	movaps	%xmm0, %xmm1
.L14:
	cmpl	%r13d, %eax
	jnb	.L20
	addss	(%r14,%rax,4), %xmm1
	addss	(%rbx,%rax,4), %xmm0
	incq	%rax
	jmp	.L14
.L20:
	cvtsi2ssl	%r13d, %xmm2
	movq	%r12, %rdi
	divss	%xmm2, %xmm0
	divss	%xmm2, %xmm1
	cvtss2sd	%xmm0, %xmm0
	mulsd	.LC1(%rip), %xmm0
	cvtss2sd	%xmm1, %xmm1
	addsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 12(%rsp)
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movss	12(%rsp), %xmm0
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3428:
	.size	_Z10get_beta14R6float3PS_i, .-_Z10get_beta14R6float3PS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_Z10get_coeffsP4int2P6float3S2_PfS3_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3456:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10get_coeffsP4int2P6float3S2_PfS3_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3456:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1074790400
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * Compute beta parameters.
 *
 * The so-called beta parameters were developed in SNO as a measure of event
 * isotropy:
 *
 *     The lth beta parameter, beta_l, is defined as the average value of the
 *     Legendre polynomial, P_l, of the cosine of the angle between each pair
 *     PMT hits in the event.
 *
 *         beta_l = <P_l(cos(theta_ik)> where i != k
 *
 *     Again, the angle is taken with respect to the fitted vertex position.
 *     The combination beta_14 = beta_1 + 4 * beta_4 was selected by the SNO
 *     collaboration for use in signal extraction due to the good separability
 *     it provides and the ease of parameterisation of the Gaussian-like
 *     distribution.
 *
 *     - Measurement of the 8B Solar Neutrino Energy Spectrum at the Sudbury
 *       Neutrino Observatory, Jeanne R. Wilson, p. 179 (Ph.D. Thesis)
*/

#include <map>
#include <string>
#include <hip/hip_runtime.h>
#include <stdio.h>

__global__ void get_coeffs(int2* pairs, float3* hit_pos, float3* fit_pos, float* p1, float* p4, int n) {
    int i = threadIdx.x + blockIdx.x * blockDim.x;

    if (i < n) {
        int2 pair = pairs[i];

        float3 A = hit_pos[pair.x];
        float3 B = hit_pos[pair.y];
        float3 C = *fit_pos;

        float c = sqrtf((A.x-B.x)*(A.x-B.x) + (A.y-B.y)*(A.y-B.y) + (A.z-B.z)*(A.z-B.z));
        float a = sqrtf((C.x-B.x)*(C.x-B.x) + (C.y-B.y)*(C.y-B.y) + (C.z-B.z)*(C.z-B.z));
        float b = sqrtf((C.x-A.x)*(C.x-A.x) + (C.y-A.y)*(C.y-A.y) + (C.z-A.z)*(C.z-A.z));

        // dust off that trig!
        p1[i] = (float)(-0.5) * (c*c - a*a - b*b) / (a*b);

        // Legendre P4(x) = (1/8) (25x**4 - 30x**2 + 3)
        p4[i] = (float)(0.125) * (25*p1[i]*p1[i]*p1[i]*p1[i] - 30*p1[i]*p1[i] + 3);
    }
}

float get_beta14(float3 &fit_pos, float3* hit_pos, int nhits) {
    // compute list of pmt pairs (this isn't really necessary)
    const int npairs = nhits * (nhits - 1) / 2;
    int2* pairs = (int2*) malloc(npairs * sizeof(int2));
    unsigned pidx = 0;
    for (unsigned i=0; i<nhits-1; i++) {
        for (unsigned j=i+1; j<nhits; j++) {
            pairs[pidx] = make_int2(i, j);
            pidx++;
        }
    }

    // allocate device memory and copy over
    int2* pairs_device;
    float* p1_device;
    float* p4_device;
    float3* hit_pos_device;
    float3* fit_pos_device;

    hipMalloc(&pairs_device, npairs * sizeof(int2));
    hipMalloc(&p1_device, npairs * sizeof(float));
    hipMalloc(&p4_device, npairs * sizeof(float));
    hipMalloc(&hit_pos_device, nhits * sizeof(float3));
    hipMalloc(&fit_pos_device, sizeof(float3));

    hipMemcpy(pairs_device, pairs, npairs * sizeof(int2), hipMemcpyHostToDevice);
    hipMemcpy(hit_pos_device, hit_pos, nhits * sizeof(float3), hipMemcpyHostToDevice);
    hipMemcpy(fit_pos_device, &fit_pos, sizeof(float3), hipMemcpyHostToDevice);

    // execute kernel and retreive results
    int blocksize = 512;
    int nblocks = npairs / blocksize + 1;
    get_coeffs<<<nblocks, blocksize>>>(pairs_device, hit_pos_device, fit_pos_device, p1_device, p4_device, npairs);

    float* p1 = (float*) malloc(npairs * sizeof(float));
    float* p4 = (float*) malloc(npairs * sizeof(float));
    hipMemcpy(p1, p1_device, npairs * sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(p4, p4_device, npairs * sizeof(float), hipMemcpyDeviceToHost);

    // compute average
    float p1ave = 0.0;
    float p4ave = 0.0;
    for (unsigned i=0; i<npairs; i++) {
        p1ave += p1[i];
        p4ave += p4[i];
    }

    p1ave /= npairs;
    p4ave /= npairs;

    float beta14 = p1ave + 4.0 * p4ave;

    free(pairs);
    free(p1);
    free(p4);
    hipFree(pairs_device);
    hipFree(hit_pos_device);
    hipFree(fit_pos_device);
    hipFree(p1_device);
    hipFree(p4_device);

    return beta14;
}


	.text
	.file	"beta14.hip"
	.globl	_Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i # -- Begin function _Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.type	_Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i,@function
_Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i: # @_Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i, .Lfunc_end0-_Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z10get_beta14R15HIP_vector_typeIfLj3EEPS0_i
.LCPI1_0:
	.quad	0x4010000000000000              # double 4
	.text
	.globl	_Z10get_beta14R15HIP_vector_typeIfLj3EEPS0_i
	.type	_Z10get_beta14R15HIP_vector_typeIfLj3EEPS0_i,@function
_Z10get_beta14R15HIP_vector_typeIfLj3EEPS0_i: # @_Z10get_beta14R15HIP_vector_typeIfLj3EEPS0_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %r15d
	movq	%rsi, 64(%rsp)                  # 8-byte Spill
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	leal	-1(%r15), %r12d
	movl	%r12d, %r13d
	imull	%edx, %r13d
	movl	%r13d, %ebp
	shrl	$31, %ebp
	addl	%r13d, %ebp
	sarl	%ebp
	movslq	%ebp, %r14
	leaq	(,%r14,8), %rdi
	movq	%rdi, 56(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, %rbx
	testl	%r12d, %r12d
	je	.LBB1_4
# %bb.1:                                # %.lr.ph69.preheader
	xorl	%ecx, %ecx
	movl	%r12d, %eax
	xorl	%edx, %edx
.LBB1_2:                                # %.lr.ph69
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_11 Depth 2
	movl	%edx, %esi
	leal	1(%rsi), %edx
	cmpl	%r15d, %edx
	jae	.LBB1_3
# %bb.10:                               # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movd	%esi, %xmm0
	leal	(%rcx,%rax), %esi
	movl	%edx, %edi
.LBB1_11:                               #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movd	%edi, %xmm1
	movdqa	%xmm0, %xmm2
	punpckldq	%xmm1, %xmm2            # xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
	movl	%ecx, %r8d
	movq	%xmm2, (%rbx,%r8,8)
	incl	%ecx
	incl	%edi
	cmpl	%edi, %r15d
	jne	.LBB1_11
# %bb.12:                               #   in Loop: Header=BB1_2 Depth=1
	movl	%esi, %ecx
.LBB1_3:                                # %.loopexit
                                        #   in Loop: Header=BB1_2 Depth=1
	decl	%eax
	cmpl	%r12d, %edx
	jne	.LBB1_2
.LBB1_4:                                # %._crit_edge
	leaq	48(%rsp), %rdi
	movq	56(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rsi
	callq	hipMalloc
	shlq	$2, %r14
	leaq	40(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movslq	%r15d, %rax
	shlq	$2, %rax
	leaq	(%rax,%rax,2), %r15
	leaq	24(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$12, %esi
	callq	hipMalloc
	leaq	48(%rsp), %rax
	movq	(%rax), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movl	$12, %edx
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leal	1023(%r13), %edi
	testl	%r13d, %r13d
	cmovnsl	%r13d, %edi
	sarl	$10, %edi
	incl	%edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	48(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	32(%rsp), %r8
	movl	%ebp, %r9d
	callq	_Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
.LBB1_6:
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %r12
	movq	40(%rsp), %rsi
	movq	%r15, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rsi
	movq	%r12, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	incl	%r13d
	pxor	%xmm0, %xmm0
	pxor	%xmm1, %xmm1
	cmpl	$3, %r13d
	jb	.LBB1_9
# %bb.7:                                # %.lr.ph74.preheader
	cmpl	$2, %ebp
	movl	$1, %eax
	cmovael	%ebp, %eax
	xorl	%ecx, %ecx
.LBB1_8:                                # %.lr.ph74
                                        # =>This Inner Loop Header: Depth=1
	addss	(%r15,%rcx,4), %xmm0
	addss	(%r12,%rcx,4), %xmm1
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB1_8
.LBB1_9:                                # %._crit_edge75
	cvtsi2ss	%ebp, %xmm2
	divss	%xmm2, %xmm0
	divss	%xmm2, %xmm1
	cvtss2sd	%xmm1, %xmm1
	mulsd	.LCPI1_0(%rip), %xmm1
	cvtss2sd	%xmm0, %xmm0
	addsd	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	cvtsd2ss	%xmm1, %xmm0
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movq	%rbx, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z10get_beta14R15HIP_vector_typeIfLj3EEPS0_i, .Lfunc_end1-_Z10get_beta14R15HIP_vector_typeIfLj3EEPS0_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i,@object # @_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.section	.rodata,"a",@progbits
	.globl	_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.p2align	3, 0x0
_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i:
	.quad	_Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.size	_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i"
	.size	.L__unnamed_1, 59

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i ; -- Begin function _Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.globl	_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
	.p2align	8
	.type	_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i,@function
_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i: ; @_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b32 s3, s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_mad_i64_i32 v[5:6], null, v3, 12, s[6:7]
	v_mad_i64_i32 v[7:8], null, v4, 12, s[6:7]
	s_clause 0x1
	global_load_b96 v[3:5], v[5:6], off
	global_load_b96 v[6:8], v[7:8], off
	s_clause 0x1
	s_load_b64 s[2:3], s[8:9], 0x0
	s_load_b32 s4, s[8:9], 0x8
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v0, v3, v6 :: v_dual_sub_f32 v9, v4, v7
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v10, v5, v8 :: v_dual_sub_f32 v7, s3, v7
	v_sub_f32_e32 v4, s3, v4
	v_dual_sub_f32 v6, s2, v6 :: v_dual_sub_f32 v3, s2, v3
	v_mul_f32_e32 v9, v9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v7, v7, v7 :: v_dual_mul_f32 v4, v4, v4
	v_sub_f32_e32 v8, s4, v8
	v_dual_fmac_f32 v9, v0, v0 :: v_dual_sub_f32 v0, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v7, v6, v6 :: v_dual_fmac_f32 v4, v3, v3
	v_fmac_f32_e32 v9, v10, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v7, v8, v8
	v_fmac_f32_e32 v4, v0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v0, 0x4f800000, v9
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
	v_mul_f32_e32 v3, 0x4f800000, v7
	v_cmp_gt_f32_e64 s2, 0xf800000, v7
	v_mul_f32_e32 v5, 0x4f800000, v4
	v_cmp_gt_f32_e64 s3, 0xf800000, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v7, v3, s2
	v_cndmask_b32_e64 v4, v4, v5, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v6, v3
	v_cndmask_b32_e32 v0, v9, v0, vcc_lo
	v_sqrt_f32_e32 v7, v4
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v9, -1, v6
	v_sqrt_f32_e32 v5, v0
	v_add_nc_u32_e32 v11, 1, v6
	v_add_nc_u32_e32 v12, -1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, -v9, v6, v3
	v_fma_f32 v17, -v11, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v18, -v12, v7, v4
	v_cmp_ge_f32_e64 s4, 0, v14
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, -1, v5
	v_add_nc_u32_e32 v10, 1, v5
	v_cndmask_b32_e64 v6, v6, v9, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v15, -v8, v5, v0
	v_fma_f32 v16, -v10, v5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s4, 0, v15
	v_cndmask_b32_e64 v5, v5, v8, s4
	v_cmp_lt_f32_e64 s4, 0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v6, v11, s4
	v_add_nc_u32_e32 v13, 1, v7
	v_cmp_ge_f32_e64 s4, 0, v18
	v_mul_f32_e32 v8, 0x37800000, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v9, -v13, v7, v4
	v_cndmask_b32_e64 v7, v7, v12, s4
	v_cmp_lt_f32_e64 s4, 0, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v6, v8, s2
	v_cndmask_b32_e64 v5, v5, v10, s4
	v_cmp_lt_f32_e64 s4, 0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, 0x37800000, v5
	v_cndmask_b32_e64 v7, v7, v13, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v9, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v3, 0x260
	v_mul_f32_e32 v8, 0x37800000, v7
	v_cndmask_b32_e32 v3, v6, v3, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v7, v8, s3
	v_dual_cndmask_b32 v0, v5, v0 :: v_dual_mul_f32 v5, v3, v3
	v_cmp_class_f32_e64 vcc_lo, v4, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v0, v0, v0, -v5
	v_cndmask_b32_e32 v4, v6, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v0, -v4, v4, v0
	v_mul_f32_e32 v3, v3, v4
	v_mul_f32_e32 v0, -0.5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v4, null, v3, v3, v0
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v7, vcc_lo, v0, v3, v0
	v_mul_f32_e32 v6, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v6, v7
	v_fmac_f32_e32 v6, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v6, v7
	v_div_fmas_f32 v4, v4, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v4, v4, v3, v0
	v_mul_f32_e32 v3, 0xc1f00000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v0, 0x41c80000, v4 :: v_dual_mul_f32 v3, v4, v3
	v_mul_f32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v4, v0
	v_fmac_f32_e32 v3, v4, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, 0x40400000, v3
	v_add_co_u32 v2, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	v_mul_f32_e32 v5, 0x3e000000, v5
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[0:1], v5, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i, .Lfunc_end0-_Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 936
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10get_coeffsP15HIP_vector_typeIiLj2EEPS_IfLj3EES3_PfS4_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
