#include "cooktorrance_implement.h"

#include "brdf_common.h"

__global__ void 
cooktorrance_kernel(float3* pos, unsigned int width, float3 V, float3 N, float m, float f0)
{
    unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
    unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;

    float3 L = calculateL(pos, width, x, y);
    float3 H = normalize(add(L, V));
    float NdotH = dot(N, H);
    float VdotH = dot(V, H);
    float NdotL = dot(N, L);
    float NdotV = dot(N, V);

    float D = beckmann(m, NdotH);
    float F = fresnel(f0, VdotH);

    NdotH = NdotH + NdotH;
    
    float G = min(2.f * NdotH * NdotL / VdotH, 2.f * NdotH * NdotV / VdotH);
    G = min(1.f, G);
    
    float val = D * G * F / NdotL / NdotV / 3.1415927f;
    
    pos[y*width+x] = scale(L, val);
}

extern "C" void cooktorrance_brdf(float3 *pos, unsigned numVertices, unsigned width, float3 V, float3 N, float m, float f0)
{
    dim3 block(8, 8, 1);
    unsigned height = numVertices / width;
    dim3 grid(width / block.x, height / block.y, 1);
    cooktorrance_kernel<<< grid, block>>>(pos, width, V, N, m, f0);
}

	.file	"tmpxft_002747b5_00000000-6_cooktorrance.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2022:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2022:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z19cooktorrance_kernelP6float3jS_S_ffP6float3jRS_S1_ff
	.type	_Z52__device_stub__Z19cooktorrance_kernelP6float3jS_S_ffP6float3jRS_S1_ff, @function
_Z52__device_stub__Z19cooktorrance_kernelP6float3jS_S_ffP6float3jRS_S1_ff:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movss	%xmm0, 16(%rsp)
	movss	%xmm1, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdx, 120(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rcx, 128(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z19cooktorrance_kernelP6float3jS_S_ff(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z52__device_stub__Z19cooktorrance_kernelP6float3jS_S_ffP6float3jRS_S1_ff, .-_Z52__device_stub__Z19cooktorrance_kernelP6float3jS_S_ffP6float3jRS_S1_ff
	.globl	_Z19cooktorrance_kernelP6float3jS_S_ff
	.type	_Z19cooktorrance_kernelP6float3jS_S_ff, @function
_Z19cooktorrance_kernelP6float3jS_S_ff:
.LFB2045:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movaps	%xmm0, %xmm6
	movaps	%xmm4, %xmm0
	movss	%xmm1, 24(%rsp)
	movq	%rsp, %rcx
	leaq	16(%rsp), %rdx
	movaps	%xmm5, %xmm1
	movq	%xmm6, 16(%rsp)
	movq	%xmm2, (%rsp)
	movss	%xmm3, 8(%rsp)
	call	_Z52__device_stub__Z19cooktorrance_kernelP6float3jS_S_ffP6float3jRS_S1_ff
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2045:
	.size	_Z19cooktorrance_kernelP6float3jS_S_ff, .-_Z19cooktorrance_kernelP6float3jS_S_ff
	.globl	cooktorrance_brdf
	.type	cooktorrance_brdf, @function
cooktorrance_brdf:
.LFB2019:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%esi, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	$1, %ecx
	movl	$1, %esi
	movd	%xmm4, %r14d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	movd	%xmm5, %r15d
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edx, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 144
	movq	%xmm0, 16(%rsp)
	movss	%xmm1, 24(%rsp)
	movq	%xmm2, (%rsp)
	movss	%xmm3, 8(%rsp)
	movq	%fs:40, %rdx
	movq	%rdx, 88(%rsp)
	movl	%ebx, %edx
	shrl	$3, %edx
	movl	%edx, 52(%rsp)
	xorl	%edx, %edx
	divl	%ebx
	movabsq	$34359738376, %rdx
	shrl	$3, %eax
	movl	%eax, 56(%rsp)
	movq	52(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	16(%rsp), %rax
	leaq	76(%rsp), %rcx
	movl	%ebx, %esi
	movq	%rbp, %rdi
	leaq	64(%rsp), %rdx
	movd	%r15d, %xmm1
	movd	%r14d, %xmm0
	movq	%rax, 64(%rsp)
	movl	24(%rsp), %eax
	movl	%eax, 72(%rsp)
	movq	(%rsp), %rax
	movq	%rax, 76(%rsp)
	movl	8(%rsp), %eax
	movl	%eax, 84(%rsp)
	call	_Z52__device_stub__Z19cooktorrance_kernelP6float3jS_S_ffP6float3jRS_S1_ff
.L9:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$104, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2019:
	.size	cooktorrance_brdf, .-cooktorrance_brdf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z19cooktorrance_kernelP6float3jS_S_ff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2047:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19cooktorrance_kernelP6float3jS_S_ff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2047:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "cooktorrance_implement.h"

#include "brdf_common.h"

__global__ void 
cooktorrance_kernel(float3* pos, unsigned int width, float3 V, float3 N, float m, float f0)
{
    unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
    unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;

    float3 L = calculateL(pos, width, x, y);
    float3 H = normalize(add(L, V));
    float NdotH = dot(N, H);
    float VdotH = dot(V, H);
    float NdotL = dot(N, L);
    float NdotV = dot(N, V);

    float D = beckmann(m, NdotH);
    float F = fresnel(f0, VdotH);

    NdotH = NdotH + NdotH;
    
    float G = min(2.f * NdotH * NdotL / VdotH, 2.f * NdotH * NdotV / VdotH);
    G = min(1.f, G);
    
    float val = D * G * F / NdotL / NdotV / 3.1415927f;
    
    pos[y*width+x] = scale(L, val);
}

extern "C" void cooktorrance_brdf(float3 *pos, unsigned numVertices, unsigned width, float3 V, float3 N, float m, float f0)
{
    dim3 block(8, 8, 1);
    unsigned height = numVertices / width;
    dim3 grid(width / block.x, height / block.y, 1);
    cooktorrance_kernel<<< grid, block>>>(pos, width, V, N, m, f0);
}

	.text
	.file	"cooktorrance.hip"
	.globl	_Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff # -- Begin function _Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.type	_Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff,@function
_Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff: # @_Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	96(%rsp), %rax
	movlps	%xmm0, (%rax)
	movss	%xmm1, 8(%rax)
	leaq	80(%rsp), %rcx
	movlps	%xmm2, (%rcx)
	movss	%xmm3, 8(%rcx)
	leaq	40(%rsp), %rdx
	movq	%rdi, (%rdx)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movss	%xmm4, (%rsi)
	leaq	12(%rsp), %r8
	movss	%xmm5, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rdx, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rax, 16(%rbx)
	movq	%rcx, 24(%rbx)
	movq	%rsi, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff, .Lfunc_end0-_Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.cfi_endproc
                                        # -- End function
	.globl	cooktorrance_brdf               # -- Begin function cooktorrance_brdf
	.type	cooktorrance_brdf,@function
cooktorrance_brdf:                      # @cooktorrance_brdf
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movss	%xmm5, 12(%rsp)                 # 4-byte Spill
	movss	%xmm4, 8(%rsp)                  # 4-byte Spill
	movss	%xmm3, 4(%rsp)                  # 4-byte Spill
	movaps	%xmm2, 32(%rsp)                 # 16-byte Spill
	movss	%xmm1, (%rsp)                   # 4-byte Spill
	movaps	%xmm0, 16(%rsp)                 # 16-byte Spill
	movl	%edx, %ebx
	movl	%esi, %eax
	movq	%rdi, %r14
	xorl	%edx, %edx
	divl	%ebx
                                        # kill: def $eax killed $eax def $rax
	movl	%ebx, %edi
	shrl	$3, %edi
	shrl	$3, %eax
	shlq	$32, %rax
	orq	%rax, %rdi
	movabsq	$34359738376, %rdx              # imm = 0x800000008
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 80
	movq	%r14, %rdi
	movl	%ebx, %esi
	movaps	16(%rsp), %xmm0                 # 16-byte Reload
	movss	(%rsp), %xmm1                   # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movaps	32(%rsp), %xmm2                 # 16-byte Reload
	movss	4(%rsp), %xmm3                  # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	8(%rsp), %xmm4                  # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm5                 # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff # TAILCALL
.Lfunc_end1:
	.size	cooktorrance_brdf, .Lfunc_end1-cooktorrance_brdf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff,@object # @_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.section	.rodata,"a",@progbits
	.globl	_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.p2align	3, 0x0
_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff:
	.quad	_Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.size	_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff"
	.size	.L__unnamed_1, 58

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff ; -- Begin function _Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.globl	_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
	.p2align	8
	.type	_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff,@function
_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff: ; @_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x8
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s12, 16
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
	s_load_b64 s[2:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v1, v2, s4
	s_and_b32 s4, s12, 0xffff
	s_mul_i32 s14, s14, s4
	s_load_b32 s4, s[0:1], 0x28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s14, v0, v1
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, v0, 12, s[2:3]
	global_load_b96 v[0:2], v[3:4], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v0, v0
	v_fmac_f32_e32 v5, v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v6, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v6, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v7, -1, v6
	v_add_nc_u32_e32 v8, 1, v6
	v_fma_f32 v9, -v7, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -v8, v6, v5
	v_cmp_ge_f32_e64 s2, 0, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v6, v7, s2
	v_cmp_lt_f32_e64 s2, 0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v6, v8, s2
	s_mov_b32 s2, 0x88e368f1
	s_mov_b32 s3, 0x3ee4f8b5
	v_mov_b32_e32 v8, 0x3f13cd36
	v_mul_f32_e32 v7, 0x37800000, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	v_mov_b32_e32 v7, 0x3f13cd36
	v_cndmask_b32_e32 v9, v6, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[5:6], v9
	v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[5:6]
	v_dual_mov_b32 v6, 0x3f13cd36 :: v_dual_mov_b32 v5, 0x3f13cd36
	s_and_saveexec_b32 s12, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_div_scale_f32 v5, null, v9, v9, v0
	v_div_scale_f32 v6, null, v9, v9, v1
	v_div_scale_f32 v7, null, v9, v9, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v10, v5
	v_rcp_f32_e32 v11, v6
	v_div_scale_f32 v13, vcc_lo, v0, v9, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v12, v7
	v_div_scale_f32 v14, s0, v1, v9, v1
	v_div_scale_f32 v18, s1, v2, v9, v2
	v_fma_f32 v15, -v5, v10, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v6, v11, 1.0
	v_fma_f32 v17, -v7, v12, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v10, v15, v10 :: v_dual_fmac_f32 v11, v16, v11
	v_dual_mul_f32 v15, v13, v10 :: v_dual_mul_f32 v16, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v19, -v5, v15, v13
	v_fmac_f32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v20, -v6, v16, v14
	v_fmac_f32_e32 v15, v19, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v17, v18, v12 :: v_dual_fmac_f32 v16, v20, v11
	v_fma_f32 v5, -v5, v15, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v21, -v7, v17, v18
	v_fma_f32 v6, -v6, v16, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v5, v5, v10, v15
	v_fmac_f32_e32 v17, v21, v12
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v6, v6, v11, v16
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v7, -v7, v17, v18
	v_div_fixup_f32 v5, v5, v9, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v6, v6, v9, v1
	v_div_fmas_f32 v7, v7, v12, v17
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v7, v7, v9, v2
.LBB0_2:                                ; %_Z10calculateLP15HIP_vector_typeIfLj3EEjjj.exit
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v2, s6, v6 :: v_dual_add_f32 v9, s5, v5
	v_add_f32_e32 v10, s7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v2, v2
	v_fmac_f32_e32 v0, v9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v10, v10
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v11, -1, v1
	v_add_nc_u32_e32 v12, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v11, v1, v0
	v_fma_f32 v14, -v12, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v13
	v_cndmask_b32_e64 v1, v1, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v14
	v_cndmask_b32_e64 v1, v1, v12, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0x37800000, v1
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, v1, v0, vcc_lo
	v_cvt_f64_f32_e32 v[0:1], v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[0:1]
	v_dual_mov_b32 v1, 0x3f13cd36 :: v_dual_mov_b32 v0, 0x3f13cd36
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_div_scale_f32 v0, null, v11, v11, v9
	v_div_scale_f32 v1, null, v11, v11, v2
	v_div_scale_f32 v8, null, v11, v11, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v12, v0
	v_rcp_f32_e32 v13, v1
	v_div_scale_f32 v15, vcc_lo, v9, v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v14, v8
	v_div_scale_f32 v16, s0, v2, v11, v2
	v_div_scale_f32 v20, s1, v10, v11, v10
	v_fma_f32 v17, -v0, v12, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v1, v13, 1.0
	v_fma_f32 v19, -v8, v14, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, v17, v12 :: v_dual_fmac_f32 v13, v18, v13
	v_dual_mul_f32 v17, v15, v12 :: v_dual_mul_f32 v18, v16, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v21, -v0, v17, v15
	v_fmac_f32_e32 v14, v19, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v22, -v1, v18, v16
	v_fmac_f32_e32 v17, v21, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v19, v20, v14 :: v_dual_fmac_f32 v18, v22, v13
	v_fma_f32 v0, -v0, v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v23, -v8, v19, v20
	v_fma_f32 v1, -v1, v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v0, v0, v12, v17
	v_fmac_f32_e32 v19, v23, v14
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v1, v1, v13, v18
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v8, -v8, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v1, v1, v11, v2
	v_div_fmas_f32 v12, v8, v14, v19
	v_div_fixup_f32 v8, v0, v11, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v0, v12, v11, v10
.LBB0_4:                                ; %_Z9normalize15HIP_vector_typeIfLj3EE.exit
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, s6, v1
	s_mov_b32 s0, 0x3e76c4e1
	v_fmac_f32_e32 v2, s5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, s7, v0
	v_sub_f32_e32 v9, 1.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f32_e64 v10, |v9|
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v10
	v_cndmask_b32_e64 v11, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v10, v10, v11
	v_add_f32_e32 v11, 1.0, v10
	v_add_f32_e32 v13, -1.0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v11
	v_add_f32_e32 v15, -1.0, v11
	v_sub_f32_e32 v10, v10, v15
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v14, v13, v12
	v_cmp_eq_f32_e64 s2, 0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, v11, v14
	v_fma_f32 v11, v14, v11, -v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v14, v10
	v_add_f32_e32 v10, v16, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v13, v10
	v_dual_sub_f32 v13, v13, v15 :: v_dual_sub_f32 v16, v10, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v13, v10 :: v_dual_sub_f32 v11, v16, v11
	v_add_f32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v15, v10
	v_mul_f32_e32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v14, v10
	v_sub_f32_e32 v12, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v13, v11, v11 :: v_dual_sub_f32 v10, v10, v12
	v_fma_f32 v12, v11, v11, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v10, v10
	v_fmac_f32_e32 v12, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v13, v12
	v_fmaak_f32 v15, s0, v14, 0x3e91f4c4
	v_sub_f32_e32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v15, v14, v15, 0x3ecccdef :: v_dual_sub_f32 v12, v12, v13
	v_mul_f32_e32 v18, v11, v14
	v_mul_f32_e32 v16, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, v14, v11, -v18
	v_fma_f32 v13, v14, v15, -v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v12, v15
	v_add_f32_e32 v15, v16, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v17, 0x3f2aaaaa, v15 :: v_dual_sub_f32 v16, v15, v16
	v_fmac_f32_e32 v19, v14, v10
	v_ldexp_f32 v10, v10, 1
	v_dual_sub_f32 v13, v13, v16 :: v_dual_add_f32 v16, 0xbf2aaaaa, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v19, v12, v11
	v_ldexp_f32 v11, v11, 1
	v_add_f32_e32 v13, 0x31739010, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v15, v16
	v_add_f32_e32 v13, v13, v15
	v_add_f32_e32 v14, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v17, v13
	v_sub_f32_e32 v15, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v14, v18
	v_add_f32_e32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v19, v17 :: v_dual_mul_f32 v16, v14, v12
	v_fma_f32 v15, v14, v12, -v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v14, v13
	v_frexp_exp_i32_f32_e32 v13, v9
	v_fmac_f32_e32 v15, v17, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v16, v15
	v_dual_sub_f32 v14, v12, v16 :: v_dual_mul_f32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v14, v15, v14 :: v_dual_fmac_f32 v1, s8, v8
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v13, vcc_lo
	v_dual_add_f32 v13, v11, v12 :: v_dual_add_f32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v13, v11
	v_sub_f32_e32 v11, v12, v11
	v_fmac_f32_e32 v1, s10, v0
	v_cvt_f32_i32_e32 v0, v8
	v_mul_f32_e64 v8, s11, s11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v10, v11
	v_dual_mul_f32 v16, v1, v1 :: v_dual_mul_f32 v17, 0x3f317218, v0
	v_fma_f32 v15, v1, v1, -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v8, v8, v16
	v_fma_f32 v18, 0x3f317218, v0, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v12, null, v8, v8, v15
	v_fmamk_f32 v0, v0, 0xb102e308, v18
	v_add_f32_e32 v18, v13, v10
	v_div_scale_f32 v22, vcc_lo, v15, v8, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v11, v12
	v_add_f32_e32 v14, v17, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v17, v14, v17
	v_add_f32_e32 v19, v14, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v12, v11, 1.0
	v_sub_f32_e32 v0, v0, v17
	v_sub_f32_e32 v13, v18, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v21, v19, v14 :: v_dual_sub_f32 v10, v10, v13
	v_dual_sub_f32 v13, v18, v21 :: v_dual_add_f32 v18, v0, v10
	v_sub_f32_e32 v23, v19, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v11, v20, v11 :: v_dual_sub_f32 v20, v18, v0
	v_sub_f32_e32 v14, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v20 :: v_dual_add_f32 v13, v13, v14
	v_add_f32_e32 v13, v18, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v22, v11
	v_fma_f32 v14, -v12, v17, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v14, v11
	v_sub_f32_e32 v14, v18, v20
	v_add_f32_e32 v18, v19, v13
	v_sub_f32_e32 v0, v0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v18, v19
	v_add_f32_e32 v0, v10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v13, v14
	v_fma_f32 v12, -v12, v17, v22
	v_add_f32_e32 v0, v0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v11, v12, v11, v17
	v_mul_f32_e32 v12, s9, v6
	v_mul_f32_e64 v17, s6, s9
	v_add_f32_e32 v13, v18, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v11, v11, v8, v15
	v_mul_f32_e32 v8, v16, v8
	v_fmac_f32_e64 v17, s5, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v18, v13, v18
	v_mul_f32_e32 v10, 0x3fb8aa3b, v11
	v_mul_f32_e32 v19, 0x40a00000, v13
	v_mul_f32_e32 v20, 0, v13
	v_fmac_f32_e64 v17, s7, s10
	v_sub_f32_e32 v0, v0, v18
	v_fma_f32 v14, 0x3fb8aa3b, v11, -v10
	v_rndne_f32_e32 v15, v10
	v_add_f32_e32 v18, v1, v1
	v_fma_f32 v13, 0x40a00000, v13, -v19
	v_fmac_f32_e32 v20, 0x40a00000, v0
	v_fmac_f32_e32 v14, 0x32a5705f, v11
	v_sub_f32_e32 v10, v10, v15
	v_fmac_f32_e32 v18, 2.0, v1
	v_cmp_class_f32_e64 vcc_lo, v19, 0x204
	v_add_f32_e32 v1, v13, v20
	v_cvt_i32_f32_e32 v13, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v10, v10, v14 :: v_dual_add_f32 v15, v19, v1
	v_fmac_f32_e32 v12, s8, v5
	v_exp_f32_e32 v0, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v0, v13
	v_cndmask_b32_e32 v13, v15, v19, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
	v_sub_f32_e32 v15, v15, v19
	v_fmac_f32_e32 v12, s10, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v13|
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v13
	v_sub_f32_e32 v1, v1, v15
	v_mul_f32_e32 v14, v17, v18
	v_cndmask_b32_e64 v22, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v1, 0, v1, s3
	v_mul_f32_e32 v10, v12, v18
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
	v_div_scale_f32 v20, null, v2, v2, v14
	v_add_f32_e32 v1, v22, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_scale_f32 v18, null, v2, v2, v10
	v_dual_cndmask_b32 v0, 0x7f800000, v0 :: v_dual_sub_f32 v11, v13, v22
	v_rcp_f32_e32 v16, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v21, v18
	v_div_scale_f32 v26, s0, v10, v2, v10
	v_div_scale_f32 v24, null, v8, v8, v0
	v_mul_f32_e32 v25, 0x3fb8aa3b, v11
	v_div_scale_f32 v33, vcc_lo, v0, v8, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v28, v24
	v_fma_f32 v27, -v20, v16, 1.0
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v23, -v18, v21, 1.0
	v_rndne_f32_e32 v29, v25
	v_div_scale_f32 v30, s1, v14, v2, v14
	v_fmac_f32_e32 v16, v27, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
	v_fmac_f32_e32 v21, v23, v21
	v_fma_f32 v23, 0x3fb8aa3b, v11, -v25
	v_sub_f32_e32 v25, v25, v29
	v_fma_f32 v31, -v24, v28, 1.0
	v_mul_f32_e32 v32, v30, v16
	v_mul_f32_e32 v27, v26, v21
	v_fmac_f32_e32 v23, 0x32a5705f, v11
	v_cvt_i32_f32_e32 v19, v29
	v_fmac_f32_e32 v28, v31, v28
	v_fma_f32 v35, -v20, v32, v30
	v_fma_f32 v31, -v18, v27, v26
	v_add_f32_e32 v23, v25, v23
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v11
	v_mul_f32_e32 v34, v33, v28
	v_fmac_f32_e32 v32, v35, v16
	v_fmac_f32_e32 v27, v31, v21
	v_exp_f32_e32 v23, v23
	v_cndmask_b32_e64 v25, 0x7f800000, 0, s2
	v_fma_f32 v29, -v24, v34, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, -v18, v27, v26
	v_fmac_f32_e32 v34, v29, v28
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v18, v23, v19
	v_fma_f32 v19, -v24, v34, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, 0, v18, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v11
	v_fma_f32 v18, -v20, v32, v30
	v_cndmask_b32_e64 v11, 0x7f800000, v13, s3
	v_div_fmas_f32 v13, v19, v28, v34
	s_mov_b32 vcc_lo, s0
	v_cmp_class_f32_e64 s0, v9, 0x204
	v_div_fmas_f32 v15, v15, v21, v27
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v1, v11, v1, v11
	v_div_fmas_f32 v16, v18, v16, v32
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v11
	v_div_fixup_f32 v10, v15, v2, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v2, v16, v2, v14
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_bfi_b32 v11, 0x7fffffff, v25, v9
	s_or_b32 vcc_lo, s2, s0
	v_min3_f32 v2, v10, v2, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_bfi_b32 v1, 0x7fffffff, v1, v9
	v_sub_f32_e64 v9, 1.0, s4
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_div_fixup_f32 v0, v13, v8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v1, v9, v1, s4
	v_mul_f32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v1
	v_div_scale_f32 v1, null, v12, v12, v0
	v_div_scale_f32 v9, vcc_lo, v0, v12, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v1, v2, 1.0
	v_fmac_f32_e32 v2, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v9, v2
	v_fma_f32 v10, -v1, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v10, v2
	v_fma_f32 v1, -v1, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v2, v8
	v_div_fixup_f32 v0, v1, v12, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v1, null, v17, v17, v0
	v_div_scale_f32 v9, vcc_lo, v0, v17, v0
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v1, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v8, v2
	v_mul_f32_e32 v8, v9, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v1, v8, v9
	v_fmac_f32_e32 v8, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v8, v9
	v_div_fmas_f32 v1, v1, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v1, v17, v0
	v_div_scale_f32 v1, null, 0x40490fdb, 0x40490fdb, v0
	v_div_scale_f32 v9, vcc_lo, v0, 0x40490fdb, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v1, v2, 1.0
	v_fmac_f32_e32 v2, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v9, v2
	v_fma_f32 v10, -v1, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v10, v2
	v_fma_f32 v1, -v1, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v1, v1, v2, v8
	v_div_fixup_f32 v2, v1, 0x40490fdb, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v1, v6, v2
	v_mul_f32_e32 v0, v5, v2
	v_mul_f32_e32 v2, v7, v2
	global_store_b96 v[3:4], v[0:2], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff, .Lfunc_end0-_Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2980
; NumSgprs: 18
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           12
        .value_kind:     by_value
      - .offset:         24
        .size:           12
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z19cooktorrance_kernelP15HIP_vector_typeIfLj3EEjS0_S0_ff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     36
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
