#include <vector>
#include <random>
#include <cuda.h>

__global__ void atomic_add_test(float* ptc_w, int* ptc_cell, float* grid_w, int n_ptc, int n_grid) {
  int tid = threadIdx.x + blockIdx.x * blockDim.x;

  for (int n = tid; n < n_ptc; n += blockDim.x * gridDim.x) {
    atomicAdd(&grid_w[ptc_cell[n]], ptc_w[n]);
  }
}

int main(int argc, char** argv) {
  // Declare and allocate memory
  int N = 10000000;
  int N_grid = 100000;
  int ptc_per_cell = N / N_grid;
  float* p_ptc_w;
  int* p_ptc_cell;
  float* p_grid_w;

  cudaMalloc(&p_ptc_w, N * sizeof(float));
  cudaMalloc(&p_ptc_cell, N * sizeof(int));
  cudaMalloc(&p_grid_w, N_grid * sizeof(float));


  // Host pointers and initialization
  std::vector<float> v_ptc_w(N), v_grid_w(N_grid), v_grid_compare(N_grid);
  std::vector<int> v_ptc_cell(N);

  std::default_random_engine gen;
  std::uniform_real_distribution<float> dist_f(0.0f, 1.0f);
  for (int i = 0; i < N_grid; i++) {
    for (int j = 0; j < ptc_per_cell; j++) {
      int n = i * ptc_per_cell + j;
      v_ptc_w[n] = dist_f(gen);
      v_ptc_cell[n] = i;
    }
    v_grid_w[i] = 0.0f;
  }

  cudaMemcpy(p_ptc_w, v_ptc_w.data(), N * sizeof(float), cudaMemcpyHostToDevice);
  cudaMemcpy(p_ptc_cell, v_ptc_cell.data(), N * sizeof(int), cudaMemcpyHostToDevice);
  cudaMemcpy(p_grid_w, v_grid_w.data(), N_grid * sizeof(float), cudaMemcpyHostToDevice);

  // Run the atomicAdd kernel
  atomic_add_test<<<512, 512>>>(p_ptc_w, p_ptc_cell, p_grid_w, N, N_grid);
  cudaDeviceSynchronize();

  cudaMemcpy(v_grid_w.data(), p_grid_w, N_grid * sizeof(float), cudaMemcpyDeviceToHost);

  // Free memory
  cudaFree(p_ptc_w);
  cudaFree(p_ptc_cell);
  cudaFree(p_grid_w);

  return 0;
}

	.file	"tmpxft_0037ab08_00000000-6_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4111:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4111:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z15atomic_add_testPfPiS_iiPfPiS_ii
	.type	_Z41__device_stub__Z15atomic_add_testPfPiS_iiPfPiS_ii, @function
_Z41__device_stub__Z15atomic_add_testPfPiS_iiPfPiS_ii:
.LFB4133:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15atomic_add_testPfPiS_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4133:
	.size	_Z41__device_stub__Z15atomic_add_testPfPiS_iiPfPiS_ii, .-_Z41__device_stub__Z15atomic_add_testPfPiS_iiPfPiS_ii
	.globl	_Z15atomic_add_testPfPiS_ii
	.type	_Z15atomic_add_testPfPiS_ii, @function
_Z15atomic_add_testPfPiS_ii:
.LFB4134:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z15atomic_add_testPfPiS_iiPfPiS_ii
	.cfi_endproc
.LFE4134:
	.size	_Z15atomic_add_testPfPiS_ii, .-_Z15atomic_add_testPfPiS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15atomic_add_testPfPiS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4136:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15atomic_add_testPfPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4136:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata._ZNSt6vectorIfSaIfEEC2EmRKS0_.str1.1,"aMS",@progbits,1
.LC1:
	.string	"cannot create std::vector larger than max_size()"
	.section	.text._ZNSt6vectorIfSaIfEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKS0_,comdat
	.align 2
	.weak	_ZNSt6vectorIfSaIfEEC2EmRKS0_
	.type	_ZNSt6vectorIfSaIfEEC2EmRKS0_, @function
_ZNSt6vectorIfSaIfEEC2EmRKS0_:
.LFB4456:
	.cfi_startproc
	endbr64
	movabsq	$2305843009213693951, %rax
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	cmpq	%rsi, %rax
	jnb	.L11
	leaq	.LC1(%rip), %rdi
	call	_ZSt20__throw_length_errorPKc@PLT
.L11:
	xorl	%eax, %eax
	movq	%rdi, %rbx
	leaq	0(,%rsi,4), %r12
	movq	%rsi, %rbp
	movq	%rax, (%rdi)
	movq	%rax, 8(%rdi)
	movq	%rax, 16(%rdi)
	xorl	%eax, %eax
	testq	%rsi, %rsi
	je	.L12
	movq	%r12, %rdi
	call	_Znwm@PLT
.L12:
	addq	%rax, %r12
	movq	%rax, (%rbx)
	movq	%rax, 8(%rbx)
	movq	%r12, 16(%rbx)
	testq	%rbp, %rbp
	je	.L13
	movl	$0x00000000, (%rax)
	addq	$4, %rax
	decq	%rbp
	je	.L13
.L14:
	cmpq	%rax, %r12
	je	.L13
	movl	$0x00000000, (%rax)
	addq	$4, %rax
	jmp	.L14
.L13:
	movq	%rax, 8(%rbx)
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4456:
	.size	_ZNSt6vectorIfSaIfEEC2EmRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKS0_
	.weak	_ZNSt6vectorIfSaIfEEC1EmRKS0_
	.set	_ZNSt6vectorIfSaIfEEC1EmRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKS0_
	.section	.text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorIfSaIfEED2Ev
	.type	_ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4459:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L25
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L25:
	ret
	.cfi_endproc
.LFE4459:
	.size	_ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
	.weak	_ZNSt6vectorIfSaIfEED1Ev
	.set	_ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
	.section	.text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorIiSaIiEED2Ev
	.type	_ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4471:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L27
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L27:
	ret
	.cfi_endproc
.LFE4471:
	.size	_ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
	.weak	_ZNSt6vectorIiSaIiEED1Ev
	.set	_ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB4108:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA4108
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$40000000, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$168, %rsp
	.cfi_def_cfa_offset 224
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	leaq	56(%rsp), %rbp
.LEHB0:
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$40000000, %esi
	leaq	128(%rsp), %r14
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$400000, %esi
	leaq	80(%rsp), %r12
	call	cudaMalloc@PLT
	movq	%r14, %rdx
	movl	$10000000, %esi
	movq	%rbp, %rdi
	call	_ZNSt6vectorIfSaIfEEC1EmRKS0_
.LEHE0:
	movq	%r14, %rdx
	movl	$100000, %esi
	movq	%r12, %rdi
.LEHB1:
	call	_ZNSt6vectorIfSaIfEEC1EmRKS0_
.LEHE1:
	leaq	104(%rsp), %r13
	movq	%r14, %rdx
	movl	$100000, %esi
	movq	%r13, %rdi
.LEHB2:
	call	_ZNSt6vectorIfSaIfEEC1EmRKS0_
.LEHE2:
	xorl	%edi, %edi
	movq	%rdi, 136(%rsp)
	movq	%rdi, 144(%rsp)
	movl	$40000000, %edi
.LEHB3:
	call	_Znwm@PLT
.LEHE3:
	leaq	40000000(%rax), %rdx
	xorl	%esi, %esi
	movq	%rax, 128(%rsp)
	movq	%rax, %rbx
	movq	%rdx, 144(%rsp)
	movl	%esi, (%rax)
	xorl	%eax, %eax
.L30:
	addq	$4, %rax
	cmpq	$40000000, %rax
	je	.L56
	xorl	%ecx, %ecx
	movl	%ecx, (%rbx,%rax)
	jmp	.L30
.L56:
	movq	56(%rsp), %r8
	movq	80(%rsp), %r15
	xorl	%ecx, %ecx
	xorps	%xmm1, %xmm1
	movss	.LC4(%rip), %xmm2
	movss	.LC5(%rip), %xmm3
	movq	%rdx, 136(%rsp)
	movl	$2147483647, %r9d
	movl	$1, %edx
.L32:
	imulq	$400, %rcx, %rsi
	movl	%ecx, %r10d
	xorl	%edi, %edi
.L36:
	imulq	$16807, %rdx, %rax
	xorl	%edx, %edx
	divq	%r9
	movq	%rdx, %rax
	decq	%rax
	js	.L33
	cvtsi2ssq	%rax, %xmm0
	jmp	.L34
.L33:
	movq	%rax, %r11
	andl	$1, %eax
	shrq	%r11
	orq	%rax, %r11
	cvtsi2ssq	%r11, %xmm0
	addss	%xmm0, %xmm0
.L34:
	addss	%xmm1, %xmm0
	mulss	%xmm2, %xmm0
	comiss	%xmm3, %xmm0
	jb	.L35
	movss	.LC3(%rip), %xmm0
.L35:
	addss	%xmm1, %xmm0
	incl	%edi
	movss	%xmm0, (%r8,%rsi)
	movl	%r10d, (%rbx,%rsi)
	addq	$4, %rsi
	cmpl	$100, %edi
	jne	.L36
	movl	$0x00000000, (%r15,%rcx,4)
	incq	%rcx
	cmpq	$100000, %rcx
	jne	.L32
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$40000000, %edx
	movq	%r8, %rsi
.LEHB4:
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$40000000, %edx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$400000, %edx
	movq	%r15, %rsi
	call	cudaMemcpy@PLT
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$9, %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	je	.L38
.L40:
	call	cudaDeviceSynchronize@PLT
	jmp	.L57
.L38:
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$10000000, %ecx
	movl	$100000, %r8d
	movq	8(%rsp), %rdi
	call	_Z41__device_stub__Z15atomic_add_testPfPiS_iiPfPiS_ii
	jmp	.L40
.L57:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$400000, %edx
	movq	%r15, %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
.LEHE4:
	movq	%r14, %rdi
	call	_ZNSt6vectorIiSaIiEED1Ev
	movq	%r13, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	%r12, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	%rbp, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	jmp	.L54
.L51:
	endbr64
	movq	%rax, %rbx
.L41:
	movq	%r14, %rdi
	call	_ZNSt6vectorIiSaIiEED1Ev
	jmp	.L42
.L50:
	endbr64
	movq	%rax, %rbx
.L42:
	movq	%r13, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L43
.L49:
	endbr64
	movq	%rax, %rbx
.L43:
	movq	%r12, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L44
.L48:
	endbr64
	movq	%rax, %rbx
.L44:
	movq	%rbp, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L54
	movq	%rbx, %rdi
.LEHB5:
	call	_Unwind_Resume@PLT
.LEHE5:
.L54:
	call	__stack_chk_fail@PLT
.L46:
	addq	$168, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4108:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA4108:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE4108-.LLSDACSB4108
.LLSDACSB4108:
	.uleb128 .LEHB0-.LFB4108
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB4108
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L48-.LFB4108
	.uleb128 0
	.uleb128 .LEHB2-.LFB4108
	.uleb128 .LEHE2-.LEHB2
	.uleb128 .L49-.LFB4108
	.uleb128 0
	.uleb128 .LEHB3-.LFB4108
	.uleb128 .LEHE3-.LEHB3
	.uleb128 .L50-.LFB4108
	.uleb128 0
	.uleb128 .LEHB4-.LFB4108
	.uleb128 .LEHE4-.LEHB4
	.uleb128 .L51-.LFB4108
	.uleb128 0
	.uleb128 .LEHB5-.LFB4108
	.uleb128 .LEHE5-.LEHB5
	.uleb128 0
	.uleb128 0
.LLSDACSE4108:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1065353215
	.align 4
.LC4:
	.long	805306368
	.align 4
.LC5:
	.long	1065353216
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <vector>
#include <random>
#include <hip/hip_runtime.h>

__global__ void atomic_add_test(float* ptc_w, int* ptc_cell, float* grid_w, int n_ptc, int n_grid) {
  int tid = threadIdx.x + blockIdx.x * blockDim.x;

  for (int n = tid; n < n_ptc; n += blockDim.x * gridDim.x) {
    atomicAdd(&grid_w[ptc_cell[n]], ptc_w[n]);
  }
}

int main(int argc, char** argv) {
  // Declare and allocate memory
  int N = 10000000;
  int N_grid = 100000;
  int ptc_per_cell = N / N_grid;
  float* p_ptc_w;
  int* p_ptc_cell;
  float* p_grid_w;

  hipMalloc(&p_ptc_w, N * sizeof(float));
  hipMalloc(&p_ptc_cell, N * sizeof(int));
  hipMalloc(&p_grid_w, N_grid * sizeof(float));


  // Host pointers and initialization
  std::vector<float> v_ptc_w(N), v_grid_w(N_grid), v_grid_compare(N_grid);
  std::vector<int> v_ptc_cell(N);

  std::default_random_engine gen;
  std::uniform_real_distribution<float> dist_f(0.0f, 1.0f);
  for (int i = 0; i < N_grid; i++) {
    for (int j = 0; j < ptc_per_cell; j++) {
      int n = i * ptc_per_cell + j;
      v_ptc_w[n] = dist_f(gen);
      v_ptc_cell[n] = i;
    }
    v_grid_w[i] = 0.0f;
  }

  hipMemcpy(p_ptc_w, v_ptc_w.data(), N * sizeof(float), hipMemcpyHostToDevice);
  hipMemcpy(p_ptc_cell, v_ptc_cell.data(), N * sizeof(int), hipMemcpyHostToDevice);
  hipMemcpy(p_grid_w, v_grid_w.data(), N_grid * sizeof(float), hipMemcpyHostToDevice);

  // Run the atomicAdd kernel
  atomic_add_test<<<512, 512>>>(p_ptc_w, p_ptc_cell, p_grid_w, N, N_grid);
  hipDeviceSynchronize();

  hipMemcpy(v_grid_w.data(), p_grid_w, N_grid * sizeof(float), hipMemcpyDeviceToHost);

  // Free memory
  hipFree(p_ptc_w);
  hipFree(p_ptc_cell);
  hipFree(p_grid_w);

  return 0;
}

	.text
	.file	"test.hip"
	.globl	_Z30__device_stub__atomic_add_testPfPiS_ii # -- Begin function _Z30__device_stub__atomic_add_testPfPiS_ii
	.type	_Z30__device_stub__atomic_add_testPfPiS_ii,@function
_Z30__device_stub__atomic_add_testPfPiS_ii: # @_Z30__device_stub__atomic_add_testPfPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15atomic_add_testPfPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__atomic_add_testPfPiS_ii, .Lfunc_end0-_Z30__device_stub__atomic_add_testPfPiS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x00000000                      # float 0
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	40(%rsp), %rdi
	movl	$40000000, %esi                 # imm = 0x2625A00
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$40000000, %esi                 # imm = 0x2625A00
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$400000, %esi                   # imm = 0x61A80
	callq	hipMalloc
	movl	$40000000, %edi                 # imm = 0x2625A00
	callq	_Znwm
	movl	$40000000, %edx                 # imm = 0x2625A00
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp0:
	movl	$400000, %edi                   # imm = 0x61A80
	callq	_Znwm
.Ltmp1:
# %bb.1:
	movl	$400000, %edx                   # imm = 0x61A80
	movq	%rax, (%rsp)                    # 8-byte Spill
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.Ltmp3:
	movl	$40000000, %edi                 # imm = 0x2625A00
	callq	_Znwm
.Ltmp4:
# %bb.2:
	movq	%rax, %r15
	xorl	%r13d, %r13d
	movl	$40000000, %edx                 # imm = 0x2625A00
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	48(%rsp), %r12
	movq	$1, (%r12)
	movl	$400, %ebp                      # imm = 0x190
	movq	%r15, 24(%rsp)                  # 8-byte Spill
	movq	8(%rsp), %rbx                   # 8-byte Reload
.LBB1_3:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	xorl	%r14d, %r14d
.LBB1_4:                                #   Parent Loop BB1_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
.Ltmp6:
	movq	%r12, %rdi
	callq	_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
.Ltmp7:
# %bb.5:                                #   in Loop: Header=BB1_4 Depth=2
	addss	.LCPI1_0(%rip), %xmm0
	movss	%xmm0, (%rbx,%r14,4)
	movl	%r13d, (%r15,%r14,4)
	incq	%r14
	cmpq	$100, %r14
	jne	.LBB1_4
# %bb.6:                                #   in Loop: Header=BB1_3 Depth=1
	movq	(%rsp), %rax                    # 8-byte Reload
	movl	$0, (%rax,%r13,4)
	incq	%r13
	addq	%rbp, %rbx
	addq	%rbp, %r15
	cmpq	$100000, %r13                   # imm = 0x186A0
	jne	.LBB1_3
# %bb.7:
	movq	40(%rsp), %rdi
.Ltmp9:
	movl	$40000000, %edx                 # imm = 0x2625A00
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp10:
# %bb.8:
	movq	32(%rsp), %rdi
.Ltmp11:
	movl	$40000000, %edx                 # imm = 0x2625A00
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp12:
# %bb.9:
	movq	16(%rsp), %rdi
.Ltmp13:
	movl	$400000, %edx                   # imm = 0x61A80
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp14:
# %bb.10:
.Ltmp15:
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp16:
# %bb.11:
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.12:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
.Ltmp17:
	movl	$10000000, %ecx                 # imm = 0x989680
	movl	$100000, %r8d                   # imm = 0x186A0
	callq	_Z30__device_stub__atomic_add_testPfPiS_ii
.Ltmp18:
.LBB1_13:
.Ltmp19:
	callq	hipDeviceSynchronize
.Ltmp20:
# %bb.14:
	movq	16(%rsp), %rsi
.Ltmp21:
	movl	$400000, %edx                   # imm = 0x61A80
	movq	(%rsp), %rdi                    # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp22:
# %bb.15:
	movq	40(%rsp), %rdi
.Ltmp23:
	callq	hipFree
.Ltmp24:
# %bb.16:
	movq	32(%rsp), %rdi
.Ltmp25:
	callq	hipFree
.Ltmp26:
# %bb.17:
	movq	16(%rsp), %rdi
.Ltmp27:
	callq	hipFree
.Ltmp28:
# %bb.18:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit52
	movq	24(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdlPv
	movq	(%rsp), %rdi                    # 8-byte Reload
	callq	_ZdlPv
	movq	8(%rsp), %rdi                   # 8-byte Reload
	callq	_ZdlPv
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_20:
	.cfi_def_cfa_offset 112
.Ltmp5:
	movq	%rax, %r12
	jmp	.LBB1_23
.LBB1_19:
.Ltmp2:
	movq	%rax, %r12
	jmp	.LBB1_24
.LBB1_21:
.Ltmp29:
	jmp	.LBB1_22
.LBB1_25:
.Ltmp8:
.LBB1_22:                               # %_ZNSt6vectorIiSaIiEED2Ev.exit54
	movq	%rax, %r12
	movq	24(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdlPv
.LBB1_23:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit58
	movq	(%rsp), %rdi                    # 8-byte Reload
	callq	_ZdlPv
.LBB1_24:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit60
	movq	8(%rsp), %rdi                   # 8-byte Reload
	callq	_ZdlPv
	movq	%r12, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table1:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp1-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp3-.Ltmp1                  #   Call between .Ltmp1 and .Ltmp3
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp4-.Ltmp3                  #   Call between .Ltmp3 and .Ltmp4
	.uleb128 .Ltmp5-.Lfunc_begin0           #     jumps to .Ltmp5
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp4-.Lfunc_begin0           # >> Call Site 5 <<
	.uleb128 .Ltmp6-.Ltmp4                  #   Call between .Ltmp4 and .Ltmp6
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 6 <<
	.uleb128 .Ltmp7-.Ltmp6                  #   Call between .Ltmp6 and .Ltmp7
	.uleb128 .Ltmp8-.Lfunc_begin0           #     jumps to .Ltmp8
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp9-.Lfunc_begin0           # >> Call Site 7 <<
	.uleb128 .Ltmp28-.Ltmp9                 #   Call between .Ltmp9 and .Ltmp28
	.uleb128 .Ltmp29-.Lfunc_begin0          #     jumps to .Ltmp29
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp28-.Lfunc_begin0          # >> Call Site 8 <<
	.uleb128 .Lfunc_end1-.Ltmp28            #   Call between .Ltmp28 and .Lfunc_end1
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
.LCPI2_0:
	.quad	0x41dfffffff800000              # double 2147483646
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI2_1:
	.long	0x40000000                      # float 2
.LCPI2_2:
	.long	0x5f000000                      # float 9.22337203E+18
.LCPI2_3:
	.long	0x3f800000                      # float 1
	.section	.text._ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_,"axG",@progbits,_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_,comdat
	.weak	_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
	.type	_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_,@function
_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_: # @_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$64, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	fldl	.LCPI2_0(%rip)
	fstpt	(%rsp)
	callq	logl
	fstpt	52(%rsp)                        # 10-byte Folded Spill
	flds	.LCPI2_1(%rip)
	fstpt	(%rsp)
	callq	logl
	fldt	52(%rsp)                        # 10-byte Folded Reload
	fdivp	%st, %st(1)
	flds	.LCPI2_2(%rip)
	xorl	%ecx, %ecx
	fxch	%st(1)
	fucomi	%st(1), %st
	fldz
	fcmovnb	%st(2), %st
	fstp	%st(2)
	fsubp	%st, %st(1)
	setae	%cl
	fnstcw	28(%rsp)
	movzwl	28(%rsp), %eax
	orl	$3072, %eax                     # imm = 0xC00
	movw	%ax, 30(%rsp)
	fldcw	30(%rsp)
	fistpll	40(%rsp)
	fldcw	28(%rsp)
	shlq	$63, %rcx
	xorq	40(%rsp), %rcx
	leaq	23(%rcx), %rax
	xorl	%edx, %edx
	divq	%rcx
	movq	%rax, %rcx
	cmpq	$1, %rax
	adcq	$0, %rcx
	movq	(%rbx), %rsi
	xorps	%xmm0, %xmm0
	movss	.LCPI2_3(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movabsq	$8589934597, %rdi               # imm = 0x200000005
.LBB2_1:                                # %select.unfold
                                        # =>This Inner Loop Header: Depth=1
	imulq	$16807, %rsi, %rsi              # imm = 0x41A7
	movq	%rsi, %rax
	mulq	%rdi
	movq	%rsi, %rax
	subq	%rdx, %rax
	shrq	%rax
	addq	%rdx, %rax
	shrq	$30, %rax
	movq	%rax, %rdx
	shlq	$31, %rdx
	subq	%rdx, %rax
	leaq	(%rsi,%rax), %rdx
	decq	%rdx
	testq	%rdx, %rdx
	js	.LBB2_2
# %bb.3:                                # %select.unfold
                                        #   in Loop: Header=BB2_1 Depth=1
	xorps	%xmm2, %xmm2
	cvtsi2ss	%rdx, %xmm2
	jmp	.LBB2_4
.LBB2_2:                                #   in Loop: Header=BB2_1 Depth=1
	movq	%rdx, %r8
	shrq	%r8
	andl	$1, %edx
	orq	%r8, %rdx
	xorps	%xmm2, %xmm2
	cvtsi2ss	%rdx, %xmm2
	addss	%xmm2, %xmm2
.LBB2_4:                                # %select.unfold
                                        #   in Loop: Header=BB2_1 Depth=1
	addq	%rax, %rsi
	mulss	%xmm1, %xmm2
	movss	%xmm1, 36(%rsp)
	flds	36(%rsp)
	fmull	.LCPI2_0(%rip)
	addss	%xmm2, %xmm0
	fstps	32(%rsp)
	movss	32(%rsp), %xmm1                 # xmm1 = mem[0],zero,zero,zero
	decq	%rcx
	jne	.LBB2_1
# %bb.5:
	movq	%rsi, (%rbx)
	divss	%xmm1, %xmm0
	ucomiss	.LCPI2_3(%rip), %xmm0
	jae	.LBB2_7
# %bb.6:
	addq	$64, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB2_7:
	.cfi_def_cfa_offset 80
	movss	.LCPI2_3(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	xorps	%xmm1, %xmm1
	addq	$64, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	nextafterf                      # TAILCALL
.Lfunc_end2:
	.size	_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_, .Lfunc_end2-_ZSt18generate_canonicalIfLm24ESt26linear_congruential_engineImLm16807ELm0ELm2147483647EEET_RT1_
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15atomic_add_testPfPiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15atomic_add_testPfPiS_ii,@object # @_Z15atomic_add_testPfPiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z15atomic_add_testPfPiS_ii
	.p2align	3, 0x0
_Z15atomic_add_testPfPiS_ii:
	.quad	_Z30__device_stub__atomic_add_testPfPiS_ii
	.size	_Z15atomic_add_testPfPiS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15atomic_add_testPfPiS_ii"
	.size	.L__unnamed_1, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__atomic_add_testPfPiS_ii
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z15atomic_add_testPfPiS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15atomic_add_testPfPiS_ii ; -- Begin function _Z15atomic_add_testPfPiS_ii
	.globl	_Z15atomic_add_testPfPiS_ii
	.p2align	8
	.type	_Z15atomic_add_testPfPiS_ii,@function
_Z15atomic_add_testPfPiS_ii:            ; @_Z15atomic_add_testPfPiS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s8, s[0:1], 0x18
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s9, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.lr.ph
	s_load_b32 s2, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s9
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v2, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v0, v[6:7], off
	global_load_b32 v5, v[2:3], off
.LBB0_3:                                ; %atomicrmw.start
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v5, v0
	global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v4, v5
	v_mov_b32_e32 v5, v4
	s_or_b32 s9, vcc_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_3
; %bb.4:                                ; %atomicrmw.end
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s8, v1
	s_or_b32 s3, vcc_lo, s3
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_5:                                ; %Flow22
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15atomic_add_testPfPiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15atomic_add_testPfPiS_ii, .Lfunc_end0-_Z15atomic_add_testPfPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15atomic_add_testPfPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15atomic_add_testPfPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
