#include "includes.h"
__global__ void cudaSToOutput_kernel( unsigned int nbProposals, const unsigned int scoreIdx, const unsigned int nbCls, const unsigned int nbOutputs, const unsigned int maxParts, const unsigned int maxTemplates, bool generateParts, bool generateTemplates, const unsigned int* numPartsPerClass, const unsigned int* numTemplatesPerClass, const int* maxCls, const float* inputs, const int* predictionIndex, const float* partsPrediction, const float* partsVisibilityPrediction, const float* templatesPrediction, float* outputs)
{
const int batchPos = blockIdx.z*nbProposals;
const int index = (threadIdx.x & 0x1f) + blockIdx.x*blockDim.x;

if(index < nbProposals)
{
const unsigned int inputIdx = index*4*(nbCls - scoreIdx)
+ batchPos*4*(nbCls - scoreIdx);

//const unsigned int outputIdx = (nbOutputs == 4) ?
//                                index*4 + batchPos*4
//                                : index*5 + batchPos*5;
unsigned int outputIdx = 0;
unsigned offset = 0;

if((nbOutputs == 4))
outputIdx = index*4 + batchPos*4;
else if((nbOutputs == 5))
outputIdx = index*5 + batchPos*5;
else if(generateParts && generateTemplates)
outputIdx = (index + batchPos)*(5 + maxParts*3 + maxTemplates*3);
else if(generateTemplates)
outputIdx = (index + batchPos)*(5 + maxTemplates*3);
else if(generateParts)
outputIdx = (index + batchPos)*(5 + maxParts*3);


outputs[0 + outputIdx] = inputs[0 + inputIdx];
outputs[1 + outputIdx] = inputs[1 + inputIdx];
outputs[2 + outputIdx] = inputs[2 + inputIdx];
outputs[3 + outputIdx] = inputs[3 + inputIdx];

offset = 4;

if(nbOutputs > 4)
{
int cls = maxCls[index + batchPos];
outputs[4 + outputIdx] = cls > -1 ?
(float) cls
: 0.0;
offset += 1;
}

if(generateParts)
{
const int predProp = predictionIndex[(index + batchPos)*2 + 0];
const int predCls = predictionIndex[(index + batchPos)*2 + 1];
// PARTS PROCESSING
if(predCls > -1)
{
for(unsigned int part = 0; part < numPartsPerClass[predCls];
++part)
{
const unsigned int partIdx = batchPos*maxParts*2*nbCls
+ predProp*maxParts*2*nbCls
+ predCls*maxParts*2
+ part*2;
outputs[0 + offset + part*2 + outputIdx] = partsPrediction[0 + partIdx];
outputs[1 + offset + part*2 + outputIdx] = partsPrediction[1 + partIdx];

}
for(int idx = numPartsPerClass[predCls]; idx < maxParts; ++idx)
{
outputs[0 + offset + numPartsPerClass[predCls]*2 + idx*2 + outputIdx] = 0.0;
outputs[1 + offset + numPartsPerClass[predCls]*2 + idx*2 + outputIdx] = 0.0;
}
}
offset += maxParts*2;

if(predCls > -1)
{
// PARTS VISIBILITY PROCESSING
for(unsigned int part = 0; part < numPartsPerClass[predCls];
++part)
{
const unsigned int partVisibilityIdx = batchPos*maxParts*nbCls
+ predProp*maxParts*nbCls
+ predCls*maxParts
+ part;
outputs[offset + part + outputIdx] = partsVisibilityPrediction[partVisibilityIdx];

}

for(int idx = numPartsPerClass[predCls]; idx < maxParts; ++idx)
outputs[offset + numPartsPerClass[predCls] + idx + outputIdx] = -1.0;
}
offset += maxParts;
}

if(generateTemplates)
{

const int predProp = predictionIndex[(index + batchPos)*2 + 0];
const int predCls = predictionIndex[(index + batchPos)*2 + 1];

if(predCls > -1)
{
for(unsigned int tpl = 0; tpl < numTemplatesPerClass[predCls]; ++tpl)
{
unsigned int templateIdx = batchPos*maxTemplates*3*nbCls
+ predProp*maxTemplates*3*nbCls
+ predCls*maxTemplates*3
+ tpl*3;

outputs[0 + offset + tpl*3 + outputIdx] = templatesPrediction[0 + templateIdx];
outputs[1 + offset + tpl*3 + outputIdx] = templatesPrediction[1 + templateIdx];
outputs[2 + offset + tpl*3 + outputIdx] = templatesPrediction[2 + templateIdx];

}
for(int idx = numTemplatesPerClass[predCls]; idx < maxParts; ++idx)
{
outputs[0 + offset + numTemplatesPerClass[predCls]*3 + idx*3 + outputIdx] = 0.0;
outputs[1 + offset + numTemplatesPerClass[predCls]*3 + idx*3 + outputIdx] = 0.0;
outputs[2 + offset + numTemplatesPerClass[predCls]*3 + idx*3 + outputIdx] = 0.0;

}

}
}

}
}
	.file	"tmpxft_003060f9_00000000-6_cudaSToOutput_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z72__device_stub__Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_PfjjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.type	_Z72__device_stub__Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_PfjjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf, @function
_Z72__device_stub__Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_PfjjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movl	336(%rsp), %eax
	movl	%edi, 108(%rsp)
	leaq	128(%rsp), %rdi
	movl	%esi, 104(%rsp)
	leaq	140(%rsp), %rsi
	movb	%al, 84(%rsp)
	movl	344(%rsp), %eax
	movl	%edx, 100(%rsp)
	leaq	112(%rsp), %rdx
	movb	%al, 80(%rsp)
	movq	352(%rsp), %rax
	movl	%ecx, 96(%rsp)
	leaq	120(%rsp), %rcx
	movq	%rax, 72(%rsp)
	movq	360(%rsp), %rax
	movl	%r8d, 92(%rsp)
	movq	%rax, 64(%rsp)
	movq	368(%rsp), %rax
	movl	%r9d, 88(%rsp)
	movq	%rax, 56(%rsp)
	movq	376(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	384(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	392(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	400(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	408(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	416(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	108(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	100(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	92(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 128(%rsp)
	movl	$1, 136(%rsp)
	movq	%rax, 140(%rsp)
	movl	$1, 148(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	120(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf(%rip), %rdi
	pushq	120(%rsp)
	.cfi_def_cfa_offset 352
	movq	156(%rsp), %rcx
	movl	164(%rsp), %r8d
	movq	144(%rsp), %rsi
	movl	152(%rsp), %edx
	leaq	192(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L2:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z72__device_stub__Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_PfjjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf, .-_Z72__device_stub__Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_PfjjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.globl	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.type	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf, @function
_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf:
.LFB2033:
	.cfi_startproc
	endbr64
	movzbl	16(%rsp), %eax
	movl	%eax, 16(%rsp)
	movzbl	8(%rsp), %eax
	movl	%eax, 8(%rsp)
	jmp	_Z72__device_stub__Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_PfjjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.cfi_endproc
.LFE2033:
	.size	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf, .-_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaSToOutput_kernel( unsigned int nbProposals, const unsigned int scoreIdx, const unsigned int nbCls, const unsigned int nbOutputs, const unsigned int maxParts, const unsigned int maxTemplates, bool generateParts, bool generateTemplates, const unsigned int* numPartsPerClass, const unsigned int* numTemplatesPerClass, const int* maxCls, const float* inputs, const int* predictionIndex, const float* partsPrediction, const float* partsVisibilityPrediction, const float* templatesPrediction, float* outputs)
{
const int batchPos = blockIdx.z*nbProposals;
const int index = (threadIdx.x & 0x1f) + blockIdx.x*blockDim.x;

if(index < nbProposals)
{
const unsigned int inputIdx = index*4*(nbCls - scoreIdx)
+ batchPos*4*(nbCls - scoreIdx);

//const unsigned int outputIdx = (nbOutputs == 4) ?
//                                index*4 + batchPos*4
//                                : index*5 + batchPos*5;
unsigned int outputIdx = 0;
unsigned offset = 0;

if((nbOutputs == 4))
outputIdx = index*4 + batchPos*4;
else if((nbOutputs == 5))
outputIdx = index*5 + batchPos*5;
else if(generateParts && generateTemplates)
outputIdx = (index + batchPos)*(5 + maxParts*3 + maxTemplates*3);
else if(generateTemplates)
outputIdx = (index + batchPos)*(5 + maxTemplates*3);
else if(generateParts)
outputIdx = (index + batchPos)*(5 + maxParts*3);


outputs[0 + outputIdx] = inputs[0 + inputIdx];
outputs[1 + outputIdx] = inputs[1 + inputIdx];
outputs[2 + outputIdx] = inputs[2 + inputIdx];
outputs[3 + outputIdx] = inputs[3 + inputIdx];

offset = 4;

if(nbOutputs > 4)
{
int cls = maxCls[index + batchPos];
outputs[4 + outputIdx] = cls > -1 ?
(float) cls
: 0.0;
offset += 1;
}

if(generateParts)
{
const int predProp = predictionIndex[(index + batchPos)*2 + 0];
const int predCls = predictionIndex[(index + batchPos)*2 + 1];
// PARTS PROCESSING
if(predCls > -1)
{
for(unsigned int part = 0; part < numPartsPerClass[predCls];
++part)
{
const unsigned int partIdx = batchPos*maxParts*2*nbCls
+ predProp*maxParts*2*nbCls
+ predCls*maxParts*2
+ part*2;
outputs[0 + offset + part*2 + outputIdx] = partsPrediction[0 + partIdx];
outputs[1 + offset + part*2 + outputIdx] = partsPrediction[1 + partIdx];

}
for(int idx = numPartsPerClass[predCls]; idx < maxParts; ++idx)
{
outputs[0 + offset + numPartsPerClass[predCls]*2 + idx*2 + outputIdx] = 0.0;
outputs[1 + offset + numPartsPerClass[predCls]*2 + idx*2 + outputIdx] = 0.0;
}
}
offset += maxParts*2;

if(predCls > -1)
{
// PARTS VISIBILITY PROCESSING
for(unsigned int part = 0; part < numPartsPerClass[predCls];
++part)
{
const unsigned int partVisibilityIdx = batchPos*maxParts*nbCls
+ predProp*maxParts*nbCls
+ predCls*maxParts
+ part;
outputs[offset + part + outputIdx] = partsVisibilityPrediction[partVisibilityIdx];

}

for(int idx = numPartsPerClass[predCls]; idx < maxParts; ++idx)
outputs[offset + numPartsPerClass[predCls] + idx + outputIdx] = -1.0;
}
offset += maxParts;
}

if(generateTemplates)
{

const int predProp = predictionIndex[(index + batchPos)*2 + 0];
const int predCls = predictionIndex[(index + batchPos)*2 + 1];

if(predCls > -1)
{
for(unsigned int tpl = 0; tpl < numTemplatesPerClass[predCls]; ++tpl)
{
unsigned int templateIdx = batchPos*maxTemplates*3*nbCls
+ predProp*maxTemplates*3*nbCls
+ predCls*maxTemplates*3
+ tpl*3;

outputs[0 + offset + tpl*3 + outputIdx] = templatesPrediction[0 + templateIdx];
outputs[1 + offset + tpl*3 + outputIdx] = templatesPrediction[1 + templateIdx];
outputs[2 + offset + tpl*3 + outputIdx] = templatesPrediction[2 + templateIdx];

}
for(int idx = numTemplatesPerClass[predCls]; idx < maxParts; ++idx)
{
outputs[0 + offset + numTemplatesPerClass[predCls]*3 + idx*3 + outputIdx] = 0.0;
outputs[1 + offset + numTemplatesPerClass[predCls]*3 + idx*3 + outputIdx] = 0.0;
outputs[2 + offset + numTemplatesPerClass[predCls]*3 + idx*3 + outputIdx] = 0.0;

}

}
}

}
}
	.text
	.file	"cudaSToOutput_kernel.hip"
	.globl	_Z35__device_stub__cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf # -- Begin function _Z35__device_stub__cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.type	_Z35__device_stub__cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf,@function
_Z35__device_stub__cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf: # @_Z35__device_stub__cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	280(%rsp), %al
	movb	272(%rsp), %r10b
	leaq	28(%rsp), %r11
	movl	%edi, (%r11)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	7(%rsp), %r9
	movb	%r10b, (%r9)
	leaq	6(%rsp), %r10
	movb	%al, (%r10)
	leaq	80(%rsp), %rbx
	movq	%r11, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf, .Lfunc_end0-_Z35__device_stub__cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf,@object # @_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.section	.rodata,"a",@progbits
	.globl	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.p2align	3, 0x0
_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf:
	.quad	_Z35__device_stub__cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.size	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf"
	.size	.L__unnamed_1, 59

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf ; -- Begin function _Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.globl	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
	.p2align	8
	.type	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf,@function
_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf: ; @_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x74
	s_load_b128 s[24:27], s[0:1], 0x0
	v_and_b32_e32 v2, 31, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s24, v0
	s_cbranch_execz .LBB0_48
; %bb.1:
	s_clause 0x1
	s_load_b128 s[20:23], s[0:1], 0x10
	s_load_b32 s2, s[0:1], 0x18
	s_mov_b32 s3, -1
	s_waitcnt lgkmcnt(0)
	s_bitcmp1_b32 s22, 0
	s_mul_i32 s22, s15, s24
	s_cselect_b32 s24, -1, 0
	v_add_nc_u32_e32 v2, s22, v0
	s_bitcmp1_b32 s2, 8
	s_cselect_b32 s23, -1, 0
	s_cmp_lt_i32 s27, 5
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %LeafBlock327
	s_cmp_eq_u32 s27, 5
	s_cbranch_scc0 .LBB0_5
; %bb.3:
	v_lshl_add_u32 v0, v2, 2, v2
	s_mov_b32 s2, 0
	s_branch .LBB0_6
.LBB0_4:
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr0
	s_branch .LBB0_7
.LBB0_5:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr0
.LBB0_6:                                ; %Flow351
	s_mov_b32 s3, 0
.LBB0_7:                                ; %Flow350
	v_lshlrev_b32_e32 v1, 2, v2
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_9
; %bb.8:                                ; %LeafBlock
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v0, v1
	s_cmp_lg_u32 s27, 4
	s_cselect_b32 s2, -1, 0
.LBB0_9:                                ; %Flow352
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_22
; %bb.10:
	s_and_b32 s2, s24, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_15
; %bb.11:
	s_xor_b32 s2, s23, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_16
; %bb.12:
	v_mov_b32_e32 v0, 0
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB0_14
; %bb.13:
	s_mul_i32 s2, s20, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, 5
	v_mul_lo_u32 v0, v2, s2
.LBB0_14:                               ; %Flow345
	s_mov_b32 s2, 0
	s_branch .LBB0_17
.LBB0_15:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr0
	s_branch .LBB0_20
.LBB0_16:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr0
.LBB0_17:                               ; %Flow346
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_19
; %bb.18:
	s_mul_i32 s2, s21, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, 5
	v_mul_lo_u32 v0, v2, s2
.LBB0_19:                               ; %Flow347
	s_mov_b32 s2, 0
.LBB0_20:                               ; %Flow348
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_22
; %bb.21:
	s_add_i32 s2, s21, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s2, 3
	s_add_i32 s2, s2, 5
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mul_lo_u32 v0, v2, s2
.LBB0_22:
	s_load_b512 s[4:19], s[0:1], 0x20
	s_sub_i32 s2, s26, s25
	v_mov_b32_e32 v4, 0
	v_mul_lo_u32 v3, v1, s2
	s_load_b64 s[2:3], s[0:1], 0x60
	s_cmp_lt_u32 s27, 5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v1, v4
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v7, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v3, v[5:6], off
	s_mov_b32 s10, 4
	s_waitcnt vmcnt(0)
	global_store_b32 v[7:8], v3, off
	v_add_nc_u32_e32 v3, 1, v0
	global_load_b32 v1, v[5:6], off offset:4
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_nc_u32_e32 v3, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[7:8], v1, off
	global_load_b32 v1, v[5:6], off offset:8
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_nc_u32_e32 v3, 3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[7:8], v1, off
	global_load_b32 v1, v[5:6], off offset:12
	v_lshlrev_b64 v[5:6], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[5:6], v1, off
	s_cbranch_scc1 .LBB0_24
; %bb.23:
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s10, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_add_nc_u32_e32 v3, 4, v0
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v5, v1
	v_cmp_lt_i32_e32 vcc_lo, -1, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v1, 0, v5, vcc_lo
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_store_b32 v[3:4], v1, off
.LBB0_24:
	v_lshlrev_b32_e32 v1, 1, v2
	s_and_not1_b32 vcc_lo, exec_lo, s24
	s_cbranch_vccnz .LBB0_40
; %bb.25:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s12, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, -1, v3
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB0_32
; %bb.26:                               ; %.preheader241
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, v3
	s_mov_b32 s11, 0
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[4:5]
	v_add_co_u32 v6, s0, s4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
	global_load_b32 v8, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB0_29
; %bb.27:                               ; %.lr.ph
	v_dual_mov_b32 v4, v3 :: v_dual_add_nc_u32 v9, s22, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, v9, s26, v[4:5]
	v_mov_b32_e32 v9, v8
	v_mul_lo_u32 v4, s20, v6
	v_add_nc_u32_e32 v6, s10, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v4, 1, v4
.LBB0_28:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[10:11], 2, v[4:5]
	v_mov_b32_e32 v7, v5
	v_add_nc_u32_e32 v9, -1, v9
	v_add_nc_u32_e32 v4, 2, v4
	v_add_co_u32 v10, s0, s14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s0, s15, v11, s0
	v_lshlrev_b64 v[12:13], 2, v[6:7]
	global_load_b32 v14, v[10:11], off
	v_add_co_u32 v12, s0, s2, v12
	v_add_co_ci_u32_e64 v13, s0, s3, v13, s0
	v_cmp_eq_u32_e64 s0, 0, v9
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s11, s0, s11
	s_waitcnt vmcnt(0)
	global_store_b32 v[12:13], v14, off
	global_load_b32 v7, v[10:11], off offset:4
	v_dual_mov_b32 v11, v5 :: v_dual_add_nc_u32 v10, 1, v6
	v_add_nc_u32_e32 v6, 2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, s1, s2, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s1, s3, v11, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v7, off
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_28
.LBB0_29:                               ; %Flow342
	s_or_b32 exec_lo, exec_lo, s9
	v_cmp_gt_u32_e64 s0, s20, v8
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_32
; %bb.30:                               ; %.lr.ph246
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v4, 2, v8
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v0, s10, v4
.LBB0_31:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v6, 1, v4
	v_lshlrev_b64 v[9:10], 2, v[4:5]
	v_add_nc_u32_e32 v8, 1, v8
	v_add_nc_u32_e32 v4, 2, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, s1, s2, v9
	v_cmp_le_u32_e64 s0, s20, v8
	v_add_co_ci_u32_e64 v10, s1, s3, v10, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s1, s2, v6
	v_add_co_ci_u32_e64 v7, s1, s3, v7, s1
	s_delay_alu instid0(VALU_DEP_4)
	s_or_b32 s9, s0, s9
	s_clause 0x1
	global_store_b32 v[9:10], v5, off
	global_store_b32 v[6:7], v5, off
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_31
.LBB0_32:                               ; %Flow343
	s_or_b32 exec_lo, exec_lo, s8
	s_lshl_b32 s1, s20, 1
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB0_39
; %bb.33:                               ; %.preheader238
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[4:5]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_mov_b32 s5, 0
	s_mov_b32 s4, exec_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v6
	s_cbranch_execz .LBB0_36
; %bb.34:                               ; %.lr.ph248
	v_dual_mov_b32 v2, v3 :: v_dual_add_nc_u32 v7, s22, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v7, s26, v[2:3]
	v_add3_u32 v2, s1, s10, v0
	v_mov_b32_e32 v7, v6
	v_mul_lo_u32 v4, v3, s20
.LBB0_35:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	v_dual_mov_b32 v3, v5 :: v_dual_add_nc_u32 v4, 1, v4
	v_add_nc_u32_e32 v7, -1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	global_load_b32 v10, v[8:9], off
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	s_or_b32 s5, vcc_lo, s5
	v_add_co_u32 v8, s0, s2, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s0, s3, v9, s0
	s_waitcnt vmcnt(0)
	global_store_b32 v[8:9], v10, off
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_35
.LBB0_36:                               ; %Flow337
	s_or_b32 exec_lo, exec_lo, s4
	v_cmp_gt_u32_e32 vcc_lo, s20, v6
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_39
; %bb.37:                               ; %.lr.ph251
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, s10, v0
	v_lshlrev_b32_e32 v4, 1, v6
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v2, v2, v4, s1
	v_mov_b32_e32 v4, -1.0
.LBB0_38:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v6, 1, v6
	v_add_nc_u32_e32 v2, 1, v2
	v_cmp_le_u32_e32 vcc_lo, s20, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s2, v7
	v_add_co_ci_u32_e64 v8, s0, s3, v8, s0
	s_or_b32 s4, vcc_lo, s4
	global_store_b32 v[7:8], v4, off
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_38
.LBB0_39:                               ; %Flow338
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s0, s10, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s10, s0, s20
.LBB0_40:
	s_and_not1_b32 vcc_lo, exec_lo, s23
	s_cbranch_vccnz .LBB0_48
; %bb.41:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s12, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
	global_load_b64 v[3:4], v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_48
; %bb.42:                               ; %.preheader235
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, v4
	s_mov_b32 s4, 0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v5
	s_cbranch_execz .LBB0_45
; %bb.43:                               ; %.lr.ph253
	v_dual_mov_b32 v1, v4 :: v_dual_add_nc_u32 v6, s22, v3
	s_mul_i32 s0, s21, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, v6, s26, v[1:2]
	v_mov_b32_e32 v6, v5
	v_mul_lo_u32 v1, s0, v3
	v_add_nc_u32_e32 v3, s10, v0
.LBB0_44:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	v_mov_b32_e32 v4, v2
	v_add_nc_u32_e32 v6, -1, v6
	v_add_co_u32 v7, vcc_lo, s18, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v8, vcc_lo
	global_load_b32 v11, v[7:8], off
	v_dual_mov_b32 v8, v2 :: v_dual_add_nc_u32 v7, 1, v1
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s18, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v8, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[9:10], v11, off
	global_load_b32 v4, v[7:8], off
	v_dual_mov_b32 v8, v2 :: v_dual_add_nc_u32 v7, 1, v3
	v_dual_mov_b32 v10, v2 :: v_dual_add_nc_u32 v9, 2, v1
	v_add_nc_u32_e32 v1, 3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[7:8], v4, off
	v_add_nc_u32_e32 v7, 2, v3
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_dual_mov_b32 v8, v2 :: v_dual_add_nc_u32 v3, 3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v9, vcc_lo, s18, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s19, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
	v_add_co_u32 v7, s0, s2, v7
	global_load_b32 v4, v[9:10], off
	v_add_co_ci_u32_e64 v8, s0, s3, v8, s0
	s_or_b32 s4, vcc_lo, s4
	s_waitcnt vmcnt(0)
	global_store_b32 v[7:8], v4, off
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_44
.LBB0_45:                               ; %Flow331
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_gt_u32_e32 vcc_lo, s20, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_48
; %bb.46:                               ; %.lr.ph256
	v_mul_lo_u32 v1, v5, 6
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v0, s10, v1
	v_mov_b32_e32 v1, 0
.LBB0_47:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, 1, v0
	v_lshlrev_b64 v[8:9], 2, v[0:1]
	v_dual_mov_b32 v7, v1 :: v_dual_add_nc_u32 v6, 2, v0
	v_add_nc_u32_e32 v5, 1, v5
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_nc_u32_e32 v0, 3, v0
	v_add_co_u32 v8, s0, s2, v8
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e64 v9, s0, s3, v9, s0
	v_add_co_u32 v2, s0, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s20, v5
	v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
	v_add_co_u32 v6, s0, s2, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s3, v7, s0
	s_or_b32 s1, vcc_lo, s1
	s_clause 0x2
	global_store_b32 v[8:9], v1, off
	global_store_b32 v[2:3], v1, off
	global_store_b32 v[6:7], v1, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_47
.LBB0_48:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 360
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf, .Lfunc_end0-_Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2272
; NumSgprs: 30
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           1
        .value_kind:     by_value
      - .offset:         25
        .size:           1
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         108
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         116
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         118
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         120
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         122
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         124
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         126
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         168
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 360
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z20cudaSToOutput_kerneljjjjjjbbPKjS0_PKiPKfS2_S4_S4_S4_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
