#include <cuda.h>
#include <iostream>
#include <ostream>
#include <fstream>
#include <sys/time.h>
#include <time.h>

using namespace std;

#define CASENAME "test_new"

#define BLOCKSIZEX 64
#define BLOCKSIZEY 1
#define BLOCKSIZEZ 1
#define BLOCKSIZELRX 48
#define BLOCKSIZELRY 1
#define BLOCKSIZELRZ 1
#define XDIM 64
#define YDIM 64
#define ZDIM 8
#define TMAX  1000
#define STARTF 0

#define OBSTR1 4.f
#define OBSTX1 23.5f
#define OBSTY1 23.5f
#define OBSTZ1 32.5f

#define OBSTR2 32.f
#define OBSTX2 319.5f
#define OBSTY2 511.5f
#define OBSTZ2 31.5f

#define LRFACTOR 0.5f
#define LRLEVEL 2
#define LRX0 11.75f	//minimum x coord of LR
#define XLRDIM 48	//number of nodes in x
#define LRY0 11.75f
#define YLRDIM 64
#define LRZ0 -0.25f
#define ZLRDIM 8

#define RE 20.f//2000.f//100.f;
#define UMAX 0.08f
#define SmagLES 0 //YES,NO
#define MODEL "MRT" //BGK,MRT,STREAM
#define REFINEMENT 0 //1,0
#define CS 0.1f

#define VELAV 0
#define START_VELAV   400000
#define START_VELFLUC 700000

inline __device__ int ImageFcn(float x, float y, float z){
    int value = 0;
//	if(((x-OBSTX1)*(x-OBSTX1)+(y-OBSTY1)*(y-OBSTY1))<OBSTR1*OBSTR1)
//		value = 10;
//	else if(((x-OBSTX2)*(x-OBSTX2)+(y-OBSTY2)*(y-OBSTY2))<OBSTR2*OBSTR2)
//		value = 10;
    
    if(abs(x-OBSTX1) < OBSTR1 && abs(y-OBSTY1) < OBSTR1)
        value = 10;

    return value;
}

inline __device__ int ImageFcn(int x, int y, int z){
    int value = 0;
//Cylinder
//	if(((x-OBSTX1)*(x-OBSTX1)+(y-OBSTY1)*(y-OBSTY1))<OBSTR1*OBSTR1)
//		value = 10;
//	else if(((x-OBSTX2)*(x-OBSTX2)+(y-OBSTY2)*(y-OBSTY2))<OBSTR2*OBSTR2)
//		value = 10;
    if(abs(x-OBSTX1) < OBSTR1 && abs(y-OBSTY1) < OBSTR1)
        value = 10;
//Lid Driven Cavity
//	if(y == 0 || y == YDIM-1 || z == 0 || z == ZDIM-1)
//		value = 1;
//	else if(x == XDIM-2 || y == 1 || y == YDIM-2 || z == 1 || z == ZDIM-2)
//		return 1;
//	else if(x == 0)
//		return 1;
    
//	if(abs(x-OBSTX1) < OBSTR1 && abs(y-OBSTY1) < OBSTR1)
//        value = 10;
//    if(z == 1)
//		value = 1;
//    if(z == ZDIM-2)
//		value = 1;
	else if(y == 0)
		value = 200;//22;
	else if(y == YDIM-1)
		value = 100;
	else if(x == 0)
		value = 26;
	else if(x == XDIM-1)
		value = 25;
	return value;
}

inline __device__ float PoisProf (float x){
	float radius = (YDIM-1-1)*0.5f;
	float result = -1.0f*(((1.0f-(x-0.5f)/radius))*((1.0f-(x-0.5f)/radius))-1.0f);
	return (result);
}

int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
  struct timeval result0;

  /* Perform the carry for the later subtraction by updating y. */
  if (x->tv_usec < y->tv_usec) {
    int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
    y->tv_usec -= 1000000 * nsec;
    y->tv_sec += nsec;
  }
  if (x->tv_usec - y->tv_usec > 1000000) {
    int nsec = (y->tv_usec - x->tv_usec) / 1000000;
    y->tv_usec += 1000000 * nsec;
    y->tv_sec -= nsec;
  }

  /* Compute the time remaining to wait.
     tv_usec is certainly positive. */
  result0.tv_sec = x->tv_sec - y->tv_sec;
  result0.tv_usec = x->tv_usec - y->tv_usec;
  *result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;

  /* Return 1 if result is negative. */
  return x->tv_sec < y->tv_sec;
}

__device__ int dmin(int a, int b)
{
	if (a<b) return a;
	else return b-1;
}
__device__ int dmax(int a)
{
	if (a>-1) return a;
	else return 0;
}
__device__ int dmin_p(int a, int b)
{
	if (a<b) return a;
	else return 0;
}
__device__ int dmax_p(int a, int b)
{
	if (a>-1) return a;
	else return b-1;
}

inline __device__ float trilinear_interp (float v000, float v001, float v010, float v011,
                                          float v100, float v101, float v110, float v111, float x, float y, float z){
    return v000*(1.f-x)*(1.f-y)*(1.f-z)+
           v001*(    x)*(1.f-y)*(1.f-z)+
           v010*(1.f-x)*(    y)*(1.f-z)+
           v011*(    x)*(    y)*(1.f-z)+
           v100*(1.f-x)*(1.f-y)*(    z)+
           v101*(    x)*(1.f-y)*(    z)+
           v110*(1.f-x)*(    y)*(    z)+
           v111*(    x)*(    y)*(    z);
}

inline __device__ int f_mem(int f_num, int x, int y, int z, size_t pitch, int zInner)
{
	int index = (x+y*pitch+z*YDIM*pitch)+f_num*pitch*YDIM*(zInner);
	index = dmax(index);
	index = dmin(index,19*pitch*YDIM*(zInner));
	return index;
}

inline __device__ int f_memLR(int f_num, int x, int y, int z, size_t pitch, int zInner)
{
	int index = (x+y*pitch+z*YLRDIM*pitch)+f_num*pitch*YLRDIM*(zInner);
	index = dmax(index);
	index = dmin(index,19*pitch*YLRDIM*(zInner));
	return index;
}

inline __device__ int buff_mem(int f_num, int x, int y, size_t pitch)
{
	int index = (x+y*pitch)+f_num*pitch*YDIM;
	index = dmax(index);
	index = dmin(index,19*pitch*YDIM);
	return index;
}

inline __device__ int buff_memLR(int f_num, int x, int y, size_t pitch)
{
	int index = (x+y*pitch)+f_num*pitch*YLRDIM;
	index = dmax(index);
	index = dmin(index,19*pitch*YLRDIM);
	return index;
}

inline __device__ void mrt_meq(float* meq, float rho, float u, float v, float w)
{
    meq[ 0] = rho;
    meq[ 1] = -11.f*rho+19.f*(u*u+v*v+w*w);
    meq[ 2] = 7.53968254f*(u*u+v*v+w*w);;
    meq[ 3] = u;
	meq[ 4] = -0.666666667f*u;
    meq[ 5] = v;
	meq[ 6] = -0.666666667f*v;
    meq[ 7] = w;
	meq[ 8] = -0.666666667f*w;
	meq[ 9] = 2.f*u*u-(v*v+w*w);
	meq[11] = v*v-w*w;
}

inline __device__ void InvertMoments(float* f, float* m)
{
float u = m[3];
float v = m[5];
float w = m[7];
f[0 ]=(0.052631579f*m[0]                           +- 0.012531328f*(m[1])+ 0.047619048f*(m[2]));
f[1 ]=(0.052631579f*m[0]+  0.1f*u                  +-0.0045948204f*(m[1])+-0.015873016f*(m[2])+  -0.1f*(m[4])                 + 0.055555556f*((m[9])-m[10]));
f[2 ]=(0.052631579f*m[0]         +  0.1f*v         +-0.0045948204f*(m[1])+-0.015873016f*(m[2])             +   -0.1f*(m[6])   +-0.027777778f*((m[9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[3 ]=(0.052631579f*m[0]+ -0.1f*u                  +-0.0045948204f*(m[1])+-0.015873016f*(m[2])+   0.1f*(m[4])                 + 0.055555556f*((m[9])-m[10]));                                                      
f[4 ]=(0.052631579f*m[0]         + -0.1f*v         +-0.0045948204f*(m[1])+-0.015873016f*(m[2])             +    0.1f*(m[6])   +-0.027777778f*((m[9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[5 ]=(0.052631579f*m[0]+  0.1f*u+  0.1f*v         + 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+ 0.025f*(m[4]+m[6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]-m[17])+ (0.027777778f*(m[9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[6 ]=(0.052631579f*m[0]+ -0.1f*u+  0.1f*v         + 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+-0.025f*(m[4]-m[6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]-m[17])+ (0.027777778f*(m[9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[7 ]=(0.052631579f*m[0]+ -0.1f*u+ -0.1f*v         + 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+-0.025f*(m[4]+m[6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]+m[17])+ (0.027777778f*(m[9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[8 ]=(0.052631579f*m[0]+  0.1f*u+ -0.1f*v         + 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+ 0.025f*(m[4]-m[6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]+m[17])+ (0.027777778f*(m[9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[9 ]=(0.052631579f*m[0]                  +  0.1f*w+-0.0045948204f*(m[1])+-0.015873016f*(m[2])                +   -0.1f*(m[8])+-0.027777778f*((m[9])-m[10])+-0.083333333f*((m[11])-m[12]));                                       
f[10]=(0.052631579f*m[0]+  0.1f*u         +  0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+ 0.025f*(m[4]+m[8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]+m[18])+ (0.027777778f*(m[9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[11]=(0.052631579f*m[0]         +  0.1f*v+  0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])             +  0.025f*(m[6]+m[8])+0.125f*( m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[9]) +( 0.25f*(m[14]))));
f[12]=(0.052631579f*m[0]+ -0.1f*u         +  0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+-0.025f*(m[4]-m[8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]+m[18])+ (0.027777778f*(m[9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[13]=(0.052631579f*m[0]         + -0.1f*v+  0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])             + -0.025f*(m[6]-m[8])+0.125f*(-m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[9]) +(-0.25f*(m[14]))));
f[14]=(0.052631579f*m[0]                  + -0.1f*w+-0.0045948204f*(m[1])+-0.015873016f*(m[2])                +    0.1f*(m[8])+-0.027777778f*((m[9])-m[10])+-0.083333333f*((m[11])-m[12]));                                      
f[15]=(0.052631579f*m[0]+  0.1f*u         + -0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+ 0.025f*(m[4]-m[8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]-m[18])+ (0.027777778f*(m[9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[16]=(0.052631579f*m[0]         +  0.1f*v+ -0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])             +  0.025f*(m[6]-m[8])+0.125f*( m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[9]) +(-0.25f*(m[14]))));
f[17]=(0.052631579f*m[0]+ -0.1f*u         + -0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+-0.025f*(m[4]+m[8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]-m[18])+ (0.027777778f*(m[9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[18]=(0.052631579f*m[0]         + -0.1f*v+ -0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])             + -0.025f*(m[6]+m[8])+0.125f*(-m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[9]) +( 0.25f*(m[14]))));


}

inline __device__ void mrt_collide(float* f, float omega)
{
    float m[19];
	float u,v,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
	w = f[ 9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
	float rho = f[ 0]+f[ 1]+f[ 2]+f[ 3]+f[ 4]+f[ 5]+f[ 6]+f[ 7]+f[ 8]+f[ 9]+
	      f[10]+f[11]+f[12]+f[13]+f[14]+f[15]+f[16]+f[17]+f[18];

	m[ 1]  = 19.f*(-f[ 0]+ f[ 5]+f[ 6]+f[ 7]+f[ 8]+f[10]+f[11]+f[12]+f[13]+f[15]+f[16]+f[17]+f[18]   -(u*u+v*v+w*w));//+8.f*(f[ 5]+f[ 6]+f[ 7]+f[ 8]+f[10]+f[11]+f[12]+f[13]+f[15]+f[16]+f[17]+f[18]);
	m[ 2]  =  12.f*f[ 0]+ -4.f*f[ 1]+ -4.f*f[ 2]+ -4.f*f[ 3]+ -4.f*f[ 4]+      f[ 5]+      f[ 6]+      f[ 7]+      f[ 8]+ -4.f*f[ 9]+    f[10]+        f[11]+      f[12]+      f[13]+ -4.f*f[14]+      f[15]+      f[16]+      f[17]+      f[18] +7.53968254f*(u*u+v*v+w*w);
	m[ 4]  = 1.666666667f*(-3.f*f[1]+3.f*f[ 3]+u);
	m[ 6]  = 1.666666667f*(-3.f*f[2]+3.f*f[ 4]+v);
	m[ 8]  = 1.666666667f*(-3.f*f[9]+3.f*f[14]+w);
	m[ 9]  = 2.f*f[ 1]+  -  f[ 2]+  2.f*f[ 3]+  -  f[ 4]+ f[ 5]+ f[ 6]+ f[ 7]+ f[ 8]+-    f[ 9]+ f[10]+ -2.f*f[11]+ f[12]+-2.f*f[13]+-    f[14]+ f[15]+ -2.f*f[16]+ f[17]+-2.f*f[18]  -(2.f*u*u-(v*v+w*w));
	m[10] = 0.f;
	m[11] =             f[ 2]         +     f[ 4]+ f[ 5]+ f[ 6]+ f[ 7]+ f[ 8]+-    f[ 9]+-f[10]          +-f[12]         +-    f[14]+-f[15]          +-f[17]         -(v*v-w*w);
	m[12] =        -2.f*f[ 2]          -2.f*f[ 4]+ f[ 5]+ f[ 6]+ f[ 7]+ f[ 8]+ 2.f*f[ 9]+-f[10]          +-f[12]         + 2.f*f[14]+-f[15]          +-f[17]         ;
	m[13] =                                  f[ 5]+-f[ 6]+ f[ 7]+-f[ 8]                                                                             -u*v;
	m[14] =                                                                    f[11]     +-    f[13]              + -    f[16]     +     f[18]  -v*w;
	m[15] =                                                          f[10]        + - f[12]                  +-f[15]          + f[17]           -u*w;  
	m[16] =                                  f[ 5]+-f[ 6]+-f[ 7]+ f[ 8]         -f[10]        +   f[12]                  +-f[15]          + f[17]         ;  
	m[17] =                                 -f[ 5]+-f[ 6]+ f[ 7]+ f[ 8]              +     f[11]     +-    f[13]              +      f[16]     +-    f[18];  
	m[18] =                                                          f[10]+-     f[11]+ f[12]+-    f[13]         +-f[15]+      f[16]+-f[17]+     f[18];

f[ 0] -=- 0.012531328f*(m[ 1])+ 0.047619048f*(m[ 2]);
f[ 1] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+  -0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])*omega-m[10]);
f[ 2] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +   -0.1f*(m[ 6])   +-0.027777778f*((m[ 9])*omega-m[10])+ 0.083333333f*((m[11])*omega-m[12]);
f[ 3] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+   0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])*omega-m[10]);                                                                                         
f[ 4] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +    0.1f*(m[ 6])   +-0.027777778f*((m[ 9])*omega-m[10])+ 0.083333333f*((m[11])*omega-m[12]);
f[ 5] -= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]-m[17])+ omega*(0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13])));
f[ 6] -= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]-m[17])+ omega*(0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13])));
f[ 7] -= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]+m[17])+ omega*(0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13])));
f[ 8] -= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]+m[17])+ omega*(0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13])));
f[ 9] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +   -0.1f*(m[ 8])+-0.027777778f*((m[ 9])*omega-m[10])+-0.083333333f*((m[11])*omega-m[12]);                                       
f[10]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]+m[18])+ omega*(0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15])));
f[11]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]+m[ 8])+0.125f*( m[17]-m[18])-0.027777778f*(m[10])+omega*(-0.055555556f*(m[ 9]) +( 0.25f*(m[14])));
f[12]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]+m[18])+ omega*(0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15])));
f[13]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]-m[ 8])+0.125f*(-m[17]-m[18])-0.027777778f*(m[10])+omega*(-0.055555556f*(m[ 9]) +(-0.25f*(m[14])));
f[14]-=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +    0.1f*(m[ 8])+-0.027777778f*((m[ 9])*omega-m[10])+-0.083333333f*((m[11])*omega-m[12]);                                      
f[15]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]-m[18])+ omega*(0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15])));
f[16]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]-m[ 8])+0.125f*( m[17]+m[18])-0.027777778f*(m[10])+omega*(-0.055555556f*(m[ 9]) +(-0.25f*(m[14])));
f[17]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]-m[18])+ omega*(0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15])));
f[18]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]+m[ 8])+0.125f*(-m[17]+m[18])-0.027777778f*(m[10])+omega*(-0.055555556f*(m[ 9]) +( 0.25f*(m[14])));

}

inline __device__ void North_Extrap(float* f, float rho)
{
    float m[19];
	rho = 1.0f;
	float u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	float v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
	float w = f[ 9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];


	m[ 1]  = -30.f*f[ 0]+-11.f*f[ 1]+-11.f*f[ 2]+-11.f*f[ 3]+-11.f*f[ 4]+  8.f*f[ 5]+  8.f*f[ 6]+  8.f*f[ 7]+  8.f*f[ 8]+-11.f*f[ 9]+  8.f*f[10]+  8.f*f[11]+  8.f*f[12]+  8.f*f[13]+-11.f*f[14]+  8.f*f[15]+  8.f*f[16]+  8.f*f[17]+  8.f*f[18];
	m[ 2]  =  12.f*f[ 0]+ -4.f*f[ 1]+ -4.f*f[ 2]+ -4.f*f[ 3]+ -4.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -4.f*f[ 9]+    f[10]+      f[11]+    f[12]+    f[13]+ -4.f*f[14]+    f[15]+    f[16]+    f[17]+    f[18];
	m[ 4]  =           -4.f*f[ 1]         +  4.f*f[ 3]         +    f[ 5]+ -  f[ 6]+ -  f[ 7]+    f[ 8]         +    f[10]          + -  f[12]                    +    f[15]          + -  f[17]          ;
	m[ 6]  =                    -4.f*f[ 2]         +  4.f*f[ 4]+    f[ 5]+    f[ 6]+ -  f[ 7]+ -  f[ 8]                   +    f[11]          + -  f[13]                    +    f[16]          + -  f[18];
	m[ 8]  =                                                                                 + -4.f*f[ 9]+    f[10]+    f[11]+    f[12]+    f[13]+  4.f*f[14]+ -  f[15]+ -  f[16]+ -  f[17]+ -  f[18];
	m[ 9]  =            2.f*f[ 1]+ -  f[ 2]+  2.f*f[ 3]+ -  f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -  f[ 9]+    f[10]+ -2.f*f[11]+    f[12]+ -2.f*f[13]+ -  f[14]+    f[15]+ -2.f*f[16]+    f[17]+ -2.f*f[18];
	m[10] =           -4.f*f[ 1]+  2.f*f[ 2]+ -4.f*f[ 3]+  2.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+  2.f*f[ 9]+    f[10]+ -2.f*f[11]+    f[12]+ -2.f*f[13]+  2.f*f[14]+    f[15]+ -2.f*f[16]+    f[17]+ -2.f*f[18];
	m[11] =                       f[ 2]         +    f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -  f[ 9]+ -  f[10]          + -  f[12]          + -  f[14]+ -  f[15]          + -  f[17]          ;
	m[12] =                    -2.f*f[ 2]           -2.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+  2.f*f[ 9]+ -  f[10]          + -  f[12]          +  2.f*f[14]+ -  f[15]          + -  f[17]          ;
	m[13] =                                                  f[ 5]+ -  f[ 6]+    f[ 7]+ -  f[ 8]                                                                                                   ;
	m[14] =                                                                                                         f[11]          + -  f[13]                    + -  f[16]          +    f[18];
	m[15] =                                                                                               f[10]          + -  f[12]                    + -  f[15]          +    f[17]          ;  
	m[16] =                                                  f[ 5]+ -  f[ 6]+ -  f[ 7]+    f[ 8]           -  f[10]          +    f[12]                    + -  f[15]          +    f[17]          ;  
	m[17] =                                               -  f[ 5]+ -  f[ 6]+    f[ 7]+    f[ 8]                   +    f[11]          + -  f[13]                    +    f[16]          + -  f[18];  
	m[18] =                                                                                               f[10]+ -  f[11]+    f[12]+ -  f[13]          + -  f[15]+    f[16]+ -  f[17]+    f[18];

f[ 0] =(0.052631579f*rho                           +- 0.012531328f*(m[ 1])+ 0.047619048f*(m[ 2]));
f[ 1] =(0.052631579f*rho+  0.1f*u                  +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+  -0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])-m[10]));
f[ 2] =(0.052631579f*rho         +  0.1f*v         +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +   -0.1f*(m[ 6])   +-0.027777778f*((m[ 9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[ 3] =(0.052631579f*rho+ -0.1f*u                  +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+   0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])-m[10]));        
f[ 4] =(0.052631579f*rho         + -0.1f*v         +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +    0.1f*(m[ 6])   +-0.027777778f*((m[ 9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[ 5] =(0.052631579f*rho+  0.1f*u+  0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]-m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[ 6] =(0.052631579f*rho+ -0.1f*u+  0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]-m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[ 7] =(0.052631579f*rho+ -0.1f*u+ -0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]+m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[ 8] =(0.052631579f*rho+  0.1f*u+ -0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]+m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[ 9] =(0.052631579f*rho                  +  0.1f*w+-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +   -0.1f*(m[ 8])+-0.027777778f*((m[ 9])-m[10])+-0.083333333f*((m[11])-m[12]));                                       
f[10]=(0.052631579f*rho+  0.1f*u         +  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]+m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[11]=(0.052631579f*rho         +  0.1f*v+  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]+m[ 8])+0.125f*( m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +( 0.25f*(m[14]))));
f[12]=(0.052631579f*rho+ -0.1f*u         +  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]+m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[13]=(0.052631579f*rho         + -0.1f*v+  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]-m[ 8])+0.125f*(-m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +(-0.25f*(m[14]))));
f[14]=(0.052631579f*rho                  + -0.1f*w+-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +    0.1f*(m[ 8])+-0.027777778f*((m[ 9])-m[10])+-0.083333333f*((m[11])-m[12]));                                      
f[15]=(0.052631579f*rho+  0.1f*u         + -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]-m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[16]=(0.052631579f*rho         +  0.1f*v+ -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]-m[ 8])+0.125f*( m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +(-0.25f*(m[14]))));
f[17]=(0.052631579f*rho+ -0.1f*u         + -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]-m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[18]=(0.052631579f*rho         + -0.1f*v+ -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]+m[ 8])+0.125f*(-m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +( 0.25f*(m[14]))));

}

inline __device__ void South_Extrap(float* f, float v)
{
    float m[19];
	float u = 0.f;//f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	float w = 0.f;//f[ 9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
    float rho = f[0]+f[1]+f[2]+f[3]+f[4]+f[5]+f[6]+f[7]+f[8]+f[9]+f[10]+f[11]+f[12]+f[13]+f[14]+f[15]+f[16]+f[17]+f[18];

	m[ 1]  = -30.f*f[ 0]+-11.f*f[ 1]+-11.f*f[ 2]+-11.f*f[ 3]+-11.f*f[ 4]+  8.f*f[ 5]+  8.f*f[ 6]+  8.f*f[ 7]+  8.f*f[ 8]+-11.f*f[ 9]+  8.f*f[10]+  8.f*f[11]+  8.f*f[12]+  8.f*f[13]+-11.f*f[14]+  8.f*f[15]+  8.f*f[16]+  8.f*f[17]+  8.f*f[18];
	m[ 2]  =  12.f*f[ 0]+ -4.f*f[ 1]+ -4.f*f[ 2]+ -4.f*f[ 3]+ -4.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -4.f*f[ 9]+    f[10]+      f[11]+    f[12]+    f[13]+ -4.f*f[14]+    f[15]+    f[16]+    f[17]+    f[18];
	m[ 4]  =           -4.f*f[ 1]         +  4.f*f[ 3]         +    f[ 5]+ -  f[ 6]+ -  f[ 7]+    f[ 8]         +    f[10]          + -  f[12]                    +    f[15]          + -  f[17]          ;
	m[ 6]  =                    -4.f*f[ 2]         +  4.f*f[ 4]+    f[ 5]+    f[ 6]+ -  f[ 7]+ -  f[ 8]                   +    f[11]          + -  f[13]                    +    f[16]          + -  f[18];
	m[ 8]  =                                                                                 + -4.f*f[ 9]+    f[10]+    f[11]+    f[12]+    f[13]+  4.f*f[14]+ -  f[15]+ -  f[16]+ -  f[17]+ -  f[18];
	m[ 9]  =            2.f*f[ 1]+ -  f[ 2]+  2.f*f[ 3]+ -  f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -  f[ 9]+    f[10]+ -2.f*f[11]+    f[12]+ -2.f*f[13]+ -  f[14]+    f[15]+ -2.f*f[16]+    f[17]+ -2.f*f[18];
	m[10] =           -4.f*f[ 1]+  2.f*f[ 2]+ -4.f*f[ 3]+  2.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+  2.f*f[ 9]+    f[10]+ -2.f*f[11]+    f[12]+ -2.f*f[13]+  2.f*f[14]+    f[15]+ -2.f*f[16]+    f[17]+ -2.f*f[18];
	m[11] =                       f[ 2]         +    f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -  f[ 9]+ -  f[10]          + -  f[12]          + -  f[14]+ -  f[15]          + -  f[17]          ;
	m[12] =                    -2.f*f[ 2]           -2.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+  2.f*f[ 9]+ -  f[10]          + -  f[12]          +  2.f*f[14]+ -  f[15]          + -  f[17]          ;
	m[13] =                                                  f[ 5]+ -  f[ 6]+    f[ 7]+ -  f[ 8]                                                                                                   ;
	m[14] =                                                                                                         f[11]          + -  f[13]                    + -  f[16]          +    f[18];
	m[15] =                                                                                               f[10]          + -  f[12]                    + -  f[15]          +    f[17]          ;  
	m[16] =                                                  f[ 5]+ -  f[ 6]+ -  f[ 7]+    f[ 8]           -  f[10]          +    f[12]                    + -  f[15]          +    f[17]          ;  
	m[17] =                                               -  f[ 5]+ -  f[ 6]+    f[ 7]+    f[ 8]                   +    f[11]          + -  f[13]                    +    f[16]          + -  f[18];  
	m[18] =                                                                                               f[10]+ -  f[11]+    f[12]+ -  f[13]          + -  f[15]+    f[16]+ -  f[17]+    f[18];

f[ 0] =(0.052631579f*rho                           +- 0.012531328f*(m[ 1])+ 0.047619048f*(m[ 2]));
f[ 1] =(0.052631579f*rho+  0.1f*u                  +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+  -0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])-m[10]));
f[ 2] =(0.052631579f*rho         +  0.1f*v         +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +   -0.1f*(m[ 6])   +-0.027777778f*((m[ 9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[ 3] =(0.052631579f*rho+ -0.1f*u                  +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+   0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])-m[10]));        
f[ 4] =(0.052631579f*rho         + -0.1f*v         +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +    0.1f*(m[ 6])   +-0.027777778f*((m[ 9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[ 5] =(0.052631579f*rho+  0.1f*u+  0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]-m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[ 6] =(0.052631579f*rho+ -0.1f*u+  0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]-m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[ 7] =(0.052631579f*rho+ -0.1f*u+ -0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]+m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[ 8] =(0.052631579f*rho+  0.1f*u+ -0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]+m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[ 9] =(0.052631579f*rho                  +  0.1f*w+-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +   -0.1f*(m[ 8])+-0.027777778f*((m[ 9])-m[10])+-0.083333333f*((m[11])-m[12]));                                       
f[10]=(0.052631579f*rho+  0.1f*u         +  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]+m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[11]=(0.052631579f*rho         +  0.1f*v+  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]+m[ 8])+0.125f*( m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +( 0.25f*(m[14]))));
f[12]=(0.052631579f*rho+ -0.1f*u         +  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]+m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[13]=(0.052631579f*rho         + -0.1f*v+  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]-m[ 8])+0.125f*(-m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +(-0.25f*(m[14]))));
f[14]=(0.052631579f*rho                  + -0.1f*w+-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +    0.1f*(m[ 8])+-0.027777778f*((m[ 9])-m[10])+-0.083333333f*((m[11])-m[12]));                                      
f[15]=(0.052631579f*rho+  0.1f*u         + -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]-m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[16]=(0.052631579f*rho         +  0.1f*v+ -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]-m[ 8])+0.125f*( m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +(-0.25f*(m[14]))));
f[17]=(0.052631579f*rho+ -0.1f*u         + -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]-m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[18]=(0.052631579f*rho         + -0.1f*v+ -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]+m[ 8])+0.125f*(-m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +( 0.25f*(m[14]))));

}

__device__ void xsymmetry_bot(float* f, int y, int z)
{
	if(y == 0 && z == 0){
		f[ 2] = f[ 4];
        f[13]=f[18];
        f[11]=f[18];
        f[16]=f[18];
		f[ 6] =f[ 7];
        f[ 9] =f[14];
        f[12]=f[17];
	}
	else if(y == 0 && z == ZDIM-1){
		f[ 4] = f[ 2];
        f[11]=f[13];
        f[18]=f[13];
        f[16]=f[13];
		f[ 6] =f[ 7];
        f[14]=f[ 9];
        f[17]=f[12];
	}
	else if(y == YDIM-1 && z == 0){
		f[ 4] = f[ 2];
        f[11]=f[16];
        f[18]=f[16];
        f[13]=f[16];
		f[ 7] =f[ 6];
        f[ 9] =f[14];
        f[12]=f[17];
	}
	else if(y == YDIM-1 && z == ZDIM-1){
		f[ 4] = f[ 2];
        f[16]=f[11];
        f[18]=f[11];
        f[13]=f[11];
		f[ 7] =f[ 6];
        f[14]=f[ 9];
        f[17]=f[12];
	}
    else{
	if(y == 0){
        f[ 2] = f[ 4];
        f[11]=f[13];
        f[16]=f[18];
        f[ 8] = f[ 5];
    }
	else if(y == YDIM-1){
         f[ 4]=f[ 2] ;
        f[13]=f[11];
        f[18]=f[16];
         f[ 5]=f[ 8] ;
    }
    }
	f[ 1] = f[ 3] ;
	f[ 5] = f[ 6] ;
	f[ 8] = f[ 7] ;
	f[10]= f[12];
	f[15]= f[17];
}

__device__ void xsymmetry_top(float* f, int y, int z)
{
	if(y == 0 && z == 0){
		f[ 2]  = f[ 4];
		f[13] = f[18];			
		f[11] = f[18];
		f[16] = f[18];
		f[ 5]  = f[ 8];
		f[ 9]  = f[14];
		f[10] = f[15];
	}
	else if(y == 0 && z == ZDIM-1){
		f[ 2]  = f[ 4];
		f[11] = f[13];
		f[18] = f[13];
		f[16] = f[13];
		f[ 5]  = f[ 8];
		f[14] = f[ 9];
		f[15] = f[10];
	}
	else if(y == YDIM-1 && z == 0){
		f[ 4]  = f[ 2];
		f[18] = f[16];
		f[11] = f[16];
		f[13] = f[16];	
		f[ 8]  = f[ 5];
		f[ 9]  = f[14];
		f[10] = f[15];
	}
	else if(y == YDIM-1 && z == ZDIM-1){
		f[ 4]  = f[ 2];
		f[13] = f[11];
		f[16] = f[11];
		f[18] = f[11];
		f[ 8]  = f[ 5];
		f[14] = f[ 9];
		f[15] = f[10];
	}

	else{
	if(y == 0){
		f[ 2] = f[ 4];
		f[11] = f[13];
		f[16] = f[18];
		f[ 5] = f[ 8];
	}
	else if(y == YDIM-1){
		f[ 4] = f[ 2];
		f[13] = f[11];
		f[18] = f[16];
		f[ 8] = f[ 5];
	}
	}
	f[ 3] = f[ 1] ;
	f[ 6] = f[ 5] ;
	f[ 7] = f[ 8] ;
	f[12]= f[10];
	f[17]= f[15];
}

inline __device__ void vel_av(float* f, float& uAv, float& vAv, int t)
{
	float u,v;//,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
    uAv = (uAv*(t-START_VELAV)+u)/((t-START_VELAV)+1);
    vAv = (vAv*(t-START_VELAV)+v)/((t-START_VELAV)+1);
}
inline __device__ void vel_avLR(float* f, float& uAv, float& vAv, float t)
{
	float u,v;//,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
    uAv = (uAv*(t-START_VELAV)+u*LRFACTOR)/((t-START_VELAV)+LRFACTOR);
    vAv = (vAv*(t-START_VELAV)+v*LRFACTOR)/((t-START_VELAV)+LRFACTOR);
}

inline __device__ void vel_fluc(float* f, float& uAv, 
                    float& vAv, float& ufluc, float& vfluc, int t)
{
	float u,v;//,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
    u = (u-uAv)*(u-uAv);
    v = (v-vAv)*(v-vAv);
    ufluc = (ufluc*(t-START_VELFLUC)+u)/((t-START_VELFLUC)+1);
    vfluc = (vfluc*(t-START_VELFLUC)+v)/((t-START_VELFLUC)+1);
}
inline __device__ void vel_flucLR(float* f, float& uAv, 
                    float& vAv, float& ufluc, float& vfluc, float t)
{
	float u,v;//,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
    u = (u-uAv)*(u-uAv);
    v = (v-vAv)*(v-vAv);
    ufluc = (ufluc*(t-START_VELFLUC)+u*LRFACTOR)/((t-START_VELFLUC)+LRFACTOR);
    vfluc = (vfluc*(t-START_VELFLUC)+v*LRFACTOR)/((t-START_VELFLUC)+LRFACTOR);
}



__global__ void initialize(float *fout, size_t pitch, int zInner, int GPU_N, int level)
{
	int x = threadIdx.x+blockIdx.x*blockDim.x;//coord in linear mem
	int y = threadIdx.y+blockIdx.y*blockDim.y;
	int z = threadIdx.z+blockIdx.z*blockDim.z;
    float xcoord = x;
    float ycoord = y;
    float zcoord = z+1+GPU_N*ZDIM;
    if(level > 0){
        xcoord = LRX0+x*LRFACTOR;
        ycoord = LRY0+y*LRFACTOR;
        zcoord = LRZ0+z*LRFACTOR;
    }
	int j = x+y*pitch+z*YDIM*pitch;//index on padded mem (pitch in elements)
    float f[19] = {0};
    float m[19] = {0};
	
	int im = ImageFcn(xcoord,ycoord,zcoord);
	float u,v,w,rho;
	rho = 1.f;
	u = 0.01f;
	v = UMAX;
	w = 0.0;

    if(im == 10 || im == 1){
    u = 0.0f;
    v = 0.0f;
    w = 0.0f;
    }
    
    mrt_meq(m,rho,u,v,w);
    InvertMoments(f,m);
    
    for(int i = 0; i<19; i++)
    fout[j+i *pitch*YDIM*zInner]=f[ i];
}

__global__ void update_top(float* hB, float* hA, float* fA, float* temp,
							float omega, size_t pitch, int GPU, int zInner)//pitch in elements
{
	int x = threadIdx.x+blockIdx.x*blockDim.x;//coord in linear mem
	int y = threadIdx.y+blockIdx.y*blockDim.y;
	int j = x+y*pitch;//index on padded mem (pitch in elements)
	int im = ImageFcn(x,y,(GPU+1)*(zInner+2)-1);
    float f[19];

	f[0 ]= hA  [j];
	f[1 ]= hA  [buff_mem(1 ,x-1,y  ,pitch)];
	f[3 ]= hA  [buff_mem(3 ,x+1,y  ,pitch)];
	f[2 ]= hA  [buff_mem(2 ,x  ,y-1,pitch)];
	f[5 ]= hA  [buff_mem(5 ,x-1,y-1,pitch)];
	f[6 ]= hA  [buff_mem(6 ,x+1,y-1,pitch)];
	f[4 ]= hA  [buff_mem(4 ,x  ,y+1,pitch)];
	f[7 ]= hA  [buff_mem(7 ,x+1,y+1,pitch)];
	f[8 ]= hA  [buff_mem(8 ,x-1,y+1,pitch)];
	f[9 ]= fA  [f_mem   (9 ,x  ,y  ,zInner-1,pitch, zInner)];
	f[10]= fA  [f_mem   (10,x-1,y  ,zInner-1,pitch, zInner)];
	f[11]= fA  [f_mem   (11,x  ,y-1,zInner-1,pitch, zInner)];
	f[12]= fA  [f_mem   (12,x+1,y  ,zInner-1,pitch, zInner)];
	f[13]= fA  [f_mem   (13,x  ,y+1,zInner-1,pitch, zInner)];
	f[14]= temp[buff_mem(14,x  ,y  ,pitch)];
	f[15]= temp[buff_mem(15,x-1,y  ,pitch)];
	f[16]= temp[buff_mem(16,x  ,y-1,pitch)];
	f[17]= temp[buff_mem(17,x+1,y  ,pitch)];
	f[18]= temp[buff_mem(18,x  ,y+1,pitch)];

	if(im == 1 || im ==10){//BB
		hB[buff_mem(0 ,x,y,pitch)] = f[0 ];
		hB[buff_mem(1 ,x,y,pitch)] = f[3 ];
		hB[buff_mem(2 ,x,y,pitch)] = f[4 ];
		hB[buff_mem(3 ,x,y,pitch)] = f[1 ];
		hB[buff_mem(4 ,x,y,pitch)] = f[2 ];
		hB[buff_mem(5 ,x,y,pitch)] = f[7 ];
		hB[buff_mem(6 ,x,y,pitch)] = f[8 ];
		hB[buff_mem(7 ,x,y,pitch)] = f[5 ];
		hB[buff_mem(8 ,x,y,pitch)] = f[6 ];
		hB[buff_mem(9 ,x,y,pitch)] = f[14];
		hB[buff_mem(10,x,y,pitch)] = f[17];
		hB[buff_mem(11,x,y,pitch)] = f[18];
		hB[buff_mem(12,x,y,pitch)] = f[15];
		hB[buff_mem(13,x,y,pitch)] = f[16];
		hB[buff_mem(14,x,y,pitch)] = f[9 ];
		hB[buff_mem(15,x,y,pitch)] = f[12];
		hB[buff_mem(16,x,y,pitch)] = f[13];
		hB[buff_mem(17,x,y,pitch)] = f[10];
		hB[buff_mem(18,x,y,pitch)] = f[11];
	}
	else{
        if(im == 100)//north outlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= hA[buff_mem(i ,x,y-1,pitch)];
			North_Extrap(f,1.0f);
        }
        if(im == 200)//south inlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= hA[buff_mem(i ,x,y+1,pitch)];
			South_Extrap(f,UMAX);
        }
        if(im == 25)
            xsymmetry_top(f,y,(GPU+1)*(zInner+2)-1);
        if(im == 26)
            xsymmetry_bot(f,y,(GPU+1)*(zInner+2)-1);

		mrt_collide(f,omega);

        for(int i = 0; i<19; i++)
		    hB[buff_mem(i ,x,y,pitch)] = f[i ];
	}

}

__global__ void update_bot(float* gB, float* gA, float* fA, float* temp,
							float omega, size_t pitch, int GPU, int zInner)//pitch in elements
{
	int x = threadIdx.x+blockIdx.x*blockDim.x;//coord in linear mem
	int y = threadIdx.y+blockIdx.y*blockDim.y;
	int j = x+y*pitch;//index on padded mem (pitch in elements)
	int im = ImageFcn(x,y,(GPU+1)*(zInner+2)-1);
    float f[19];

	f[0 ]= gA  [j];
	f[1 ]= gA  [buff_mem(1 ,x-1,y  ,pitch)];
	f[3 ]= gA  [buff_mem(3 ,x+1,y  ,pitch)];
	f[2 ]= gA  [buff_mem(2 ,x  ,y-1,pitch)];
	f[5 ]= gA  [buff_mem(5 ,x-1,y-1,pitch)];
	f[6 ]= gA  [buff_mem(6 ,x+1,y-1,pitch)];
	f[4 ]= gA  [buff_mem(4 ,x  ,y+1,pitch)];
	f[7 ]= gA  [buff_mem(7 ,x+1,y+1,pitch)];
	f[8 ]= gA  [buff_mem(8 ,x-1,y+1,pitch)];
	f[9 ]= temp[buff_mem(9 ,x  ,y  ,pitch)];
	f[10]= temp[buff_mem(10,x-1,y  ,pitch)];
	f[11]= temp[buff_mem(11,x  ,y-1,pitch)];
	f[12]= temp[buff_mem(12,x+1,y  ,pitch)];
	f[13]= temp[buff_mem(13,x  ,y+1,pitch)];
	f[14]= fA  [f_mem   (14,x  ,y  ,0,pitch, zInner)];
	f[15]= fA  [f_mem   (15,x-1,y  ,0,pitch, zInner)];
	f[16]= fA  [f_mem   (16,x  ,y-1,0,pitch, zInner)];
	f[17]= fA  [f_mem   (17,x+1,y  ,0,pitch, zInner)];
	f[18]= fA  [f_mem   (18,x  ,y+1,0,pitch, zInner)];

	if(im == 1 || im ==10){//BB
		gB[buff_mem(0 ,x,y,pitch)] = f[0 ];
		gB[buff_mem(1 ,x,y,pitch)] = f[3 ];
		gB[buff_mem(2 ,x,y,pitch)] = f[4 ];
		gB[buff_mem(3 ,x,y,pitch)] = f[1 ];
		gB[buff_mem(4 ,x,y,pitch)] = f[2 ];
		gB[buff_mem(5 ,x,y,pitch)] = f[7 ];
		gB[buff_mem(6 ,x,y,pitch)] = f[8 ];
		gB[buff_mem(7 ,x,y,pitch)] = f[5 ];
		gB[buff_mem(8 ,x,y,pitch)] = f[6 ];
		gB[buff_mem(9 ,x,y,pitch)] = f[14];
		gB[buff_mem(10,x,y,pitch)] = f[17];
		gB[buff_mem(11,x,y,pitch)] = f[18];
		gB[buff_mem(12,x,y,pitch)] = f[15];
		gB[buff_mem(13,x,y,pitch)] = f[16];
		gB[buff_mem(14,x,y,pitch)] = f[9 ];
		gB[buff_mem(15,x,y,pitch)] = f[12];
		gB[buff_mem(16,x,y,pitch)] = f[13];
		gB[buff_mem(17,x,y,pitch)] = f[10];
		gB[buff_mem(18,x,y,pitch)] = f[11];
	}
	else{
        if(im == 100)//north outlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= gA[buff_mem(i ,x,y-1,pitch)];
			North_Extrap(f,1.0f);
        }
        if(im == 200)//south inlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= gA[buff_mem(i ,x,y+1,pitch)];
			South_Extrap(f,UMAX);
        }
        if(im == 25)
            xsymmetry_top(f,y,GPU*(zInner+2));
        if(im == 26)
            xsymmetry_bot(f,y,GPU*(zInner+2));

		mrt_collide(f,omega);

        for(int i = 0; i<19; i++)
		    gB[buff_mem(i ,x,y,pitch)] = f[i ];
	}
}

__global__ void update_inn(float* fB, float* fA, float* g, float* h, float omega, size_t pitch, int GPU, int zInner, float **velAv, float ** velFluc, int t)
{
	int x = threadIdx.x+blockIdx.x*blockDim.x;//coord in linear mem
	int y = threadIdx.y+blockIdx.y*blockDim.y;
	int z = threadIdx.z+blockIdx.z*blockDim.z;
	int j = x+y*pitch+z*YDIM*pitch;//index on padded mem (pitch in elements)
	int im = ImageFcn(x,y,GPU*(zInner+2)+1+z);
	float f[19];

    f[ 0] = fA[j];
	f[ 1] = fA[f_mem   (1 ,x-1,y  ,z  ,pitch, zInner)];
	f[ 3] = fA[f_mem   (3 ,x+1,y  ,z  ,pitch, zInner)];
	f[ 2] = fA[f_mem   (2 ,x  ,y-1,z  ,pitch, zInner)];
	f[ 5] = fA[f_mem   (5 ,x-1,y-1,z  ,pitch, zInner)];
	f[ 6] = fA[f_mem   (6 ,x+1,y-1,z  ,pitch, zInner)];
	f[ 4] = fA[f_mem   (4 ,x  ,y+1,z  ,pitch, zInner)];
	f[ 7] = fA[f_mem   (7 ,x+1,y+1,z  ,pitch, zInner)];
	f[ 8] = fA[f_mem   (8 ,x-1,y+1,z  ,pitch, zInner)];

    if(z==zInner-1){//top nodes need info from h
	f[ 9] = fA[f_mem   (9 ,x  ,y  ,z-1,pitch, zInner)];
	f[10]= fA[f_mem   (10,x-1,y  ,z-1,pitch, zInner)];
	f[11]= fA[f_mem   (11,x  ,y-1,z-1,pitch, zInner)];
	f[12]= fA[f_mem   (12,x+1,y  ,z-1,pitch, zInner)];
	f[13]= fA[f_mem   (13,x  ,y+1,z-1,pitch, zInner)];
	f[14]= h [buff_mem(14,x  ,y  ,pitch)];
	f[15]= h [buff_mem(15,x-1,y  ,pitch)];
	f[16]= h [buff_mem(16,x  ,y-1,pitch)];
	f[17]= h [buff_mem(17,x+1,y  ,pitch)];
	f[18]= h [buff_mem(18,x  ,y+1,pitch)];
    }
    else if(z==0){//bottom nodes need info from g
	f[ 9] =g [buff_mem(9 ,x  ,y  ,pitch)];
	f[10]= g [buff_mem(10,x-1,y  ,pitch)];
	f[11]= g [buff_mem(11,x  ,y-1,pitch)];
	f[12]= g [buff_mem(12,x+1,y  ,pitch)];
	f[13]= g [buff_mem(13,x  ,y+1,pitch)];
	f[14]= fA[f_mem   (14,x  ,y  ,z+1,pitch, zInner)];
	f[15]= fA[f_mem   (15,x-1,y  ,z+1,pitch, zInner)];
	f[16]= fA[f_mem   (16,x  ,y-1,z+1,pitch, zInner)];
	f[17]= fA[f_mem   (17,x+1,y  ,z+1,pitch, zInner)];
	f[18]= fA[f_mem   (18,x  ,y+1,z+1,pitch, zInner)];
    }
    else{//normal nodes
	f[ 9] = fA[f_mem(9 ,x  ,y  ,z-1,pitch,zInner)];
	f[10]= fA[f_mem(10,x-1,y  ,z-1,pitch,zInner)];
	f[11]= fA[f_mem(11,x  ,y-1,z-1,pitch,zInner)];
	f[12]= fA[f_mem(12,x+1,y  ,z-1,pitch,zInner)];
	f[13]= fA[f_mem(13,x  ,y+1,z-1,pitch,zInner)];
	f[14]= fA[f_mem(14,x  ,y  ,z+1,pitch,zInner)];
	f[15]= fA[f_mem(15,x-1,y  ,z+1,pitch,zInner)];
	f[16]= fA[f_mem(16,x  ,y-1,z+1,pitch,zInner)];
	f[17]= fA[f_mem(17,x+1,y  ,z+1,pitch,zInner)];
	f[18]= fA[f_mem(18,x  ,y+1,z+1,pitch,zInner)];

    }//end normal nodes

	if(im == 1 || im ==10){//BB
		fB[f_mem(1 ,x,y,z,pitch,zInner)] = f[ 3] ;
		fB[f_mem(2 ,x,y,z,pitch,zInner)] = f[ 4] ;
		fB[f_mem(3 ,x,y,z,pitch,zInner)] = f[ 1] ;
		fB[f_mem(4 ,x,y,z,pitch,zInner)] = f[ 2] ;
		fB[f_mem(5 ,x,y,z,pitch,zInner)] = f[ 7] ;
		fB[f_mem(6 ,x,y,z,pitch,zInner)] = f[ 8] ;
		fB[f_mem(7 ,x,y,z,pitch,zInner)] = f[ 5] ;
		fB[f_mem(8 ,x,y,z,pitch,zInner)] = f[ 6] ;
		fB[f_mem(9 ,x,y,z,pitch,zInner)] = f[14];
		fB[f_mem(10,x,y,z,pitch,zInner)] = f[17];
		fB[f_mem(11,x,y,z,pitch,zInner)] = f[18];
		fB[f_mem(12,x,y,z,pitch,zInner)] = f[15];
		fB[f_mem(13,x,y,z,pitch,zInner)] = f[16];
		fB[f_mem(14,x,y,z,pitch,zInner)] = f[ 9] ;
		fB[f_mem(15,x,y,z,pitch,zInner)] = f[12];
		fB[f_mem(16,x,y,z,pitch,zInner)] = f[13];
		fB[f_mem(17,x,y,z,pitch,zInner)] = f[10];
		fB[f_mem(18,x,y,z,pitch,zInner)] = f[11];
	}
	else{
        if(im == 100)//north outlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= fA[f_mem(i ,x,y-1,z,pitch,zInner)];
			North_Extrap(f,1.0f);
        }
        if(im == 200)//south inlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= fA[f_mem(i ,x,y+1,z,pitch,zInner)];
			South_Extrap(f,UMAX);
        }
        if(im == 25)
            xsymmetry_top(f,y,GPU*(zInner+2)+1+z);
        if(im == 26)
            xsymmetry_bot(f,y,GPU*(zInner+2)+1+z);

		mrt_collide(f,omega);

        if(VELAV == 1){
            if(t>=START_VELAV && t<START_VELFLUC){
                float u_Av = velAv[0][x+y*pitch+(z+1)*pitch*YDIM];
                float v_Av = velAv[1][x+y*pitch+(z+1)*pitch*YDIM];
        		vel_av(f,u_Av,v_Av,t);
                velAv[0][x+y*pitch+(z+1)*pitch*YDIM] = u_Av;
                velAv[1][x+y*pitch+(z+1)*pitch*YDIM] = v_Av;
            }
            else if(t>=START_VELFLUC){
                float u_Av = velAv[0][x+y*pitch+(z+1)*pitch*YDIM];
                float v_Av = velAv[1][x+y*pitch+(z+1)*pitch*YDIM];
                float u_fluc = velFluc[0][x+y*pitch+(z+1)*pitch*YDIM];
                float v_fluc = velFluc[1][x+y*pitch+(z+1)*pitch*YDIM];
        		vel_fluc(f,u_Av,v_Av,u_fluc,v_fluc,t);
                velFluc[0][x+y*pitch+(z+1)*pitch*YDIM] = u_fluc;
                velFluc[1][x+y*pitch+(z+1)*pitch*YDIM] = v_fluc;
            }
        }

        for(int i = 0; i<19; i++)
		    fB[f_mem(i ,x,y,z,pitch,zInner)] = f[ i] ;
	}
//        for(int i = 0; i<19; i++)
//		    fB[f_mem(i ,x,y,z,pitch,zInner)] = 1.f ;
}


void WriteResults(ostream &output, float *fin, float *gin, float *hin, float **velAv,  
                  float **velFluc, float omega, int GPU_N, int GPU)
{
    float f[19];
	output<<"VARIABLES = \"X\",\"Y\",\"Z\",\"u\",\"v\",\"w\",\"rho\",\"velAv[0]\",\"velAv[1]\",\"ufluc\",\"vfluc\"\n";
	output<<"ZONE F=POINT, I="<<XDIM<<", J="<<YDIM<<", K="<<ZDIM/GPU_N<<"\n";

    for(int j = 0; j<YDIM; j++){
    for(int i = 0; i<XDIM; i++){
        float rho = 0;
        for(int l = 0; l<19; l++){
            f[l] = gin[(i+j*XDIM)+l *XDIM*YDIM];
            rho += f[l];
        }
        float u = f[1]-f[3 ]+f[5 ]-f[6 ]-f[7 ]+f[8 ]+f[10]-f[12]+f[15]-f[17];
        float v = f[2]-f[4 ]+f[5 ]+f[6 ]-f[7 ]-f[8 ]+f[11]-f[13]+f[16]-f[18];
        float w = f[9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
        output<<i<<", "<<j<<", "<<(ZDIM/GPU_N*GPU)<<", "<<u<<","<<v<<","<<w<<","<<rho<<","
              <<velAv[0][i+j*XDIM]<<","<<velAv[1][i+j*XDIM]<<", "<<velFluc[0][i+j*XDIM]<<","<<velFluc[1][i+j*XDIM]<<endl;
    }}

    for(int k = 1; k<ZDIM/GPU_N-1; k++){
    for(int j = 0; j<YDIM; j++){
    for(int i = 0; i<XDIM; i++){
        float rho = 0;
        for(int l = 0; l<19; l++){
            f[l] = fin[(i+j*XDIM)+(k-1)*XDIM*YDIM+l*XDIM*YDIM*(ZDIM/GPU_N-2)];
            rho += f[l];
        }
        float u = f[1]-f[3 ]+f[5 ]-f[6 ]-f[7 ]+f[8 ]+f[10]-f[12]+f[15]-f[17];
        float v = f[2]-f[4 ]+f[5 ]+f[6 ]-f[7 ]-f[8 ]+f[11]-f[13]+f[16]-f[18];
        float w = f[9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
        int z = (ZDIM/GPU_N*GPU+k);
        output<<i<<", "<<j<<", "<<z<<", "<<u<<","<<v<<","<<w<<","<<rho<<","
              <<velAv[0][i+j*XDIM+k*XDIM*YDIM]<<","<<velAv[1][i+j*XDIM+k*XDIM*YDIM]<<", "
              <<velFluc[0][i+j*XDIM+k*XDIM*YDIM]<<","<<velFluc[1][i+j*XDIM+k*XDIM*YDIM]<<endl;
    }}}

    for(int j = 0; j<YDIM; j++){
    for(int i = 0; i<XDIM; i++){
        float rho = 0;
        for(int l = 0; l<19; l++){
            f[l] = hin[(i+j*XDIM)+l *XDIM*YDIM];
            rho += f[l];
        }
        float u = f[1]-f[3 ]+f[5 ]-f[6 ]-f[7 ]+f[8 ]+f[10]-f[12]+f[15]-f[17];
        float v = f[2]-f[4 ]+f[5 ]+f[6 ]-f[7 ]-f[8 ]+f[11]-f[13]+f[16]-f[18];
        float w = f[9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
        output<<i<<", "<<j<<", "<<(ZDIM/GPU_N*(GPU+1)-1)<<", "<<u<<","<<v<<","<<w<<","<<rho<<","
              <<velAv[0][i+j*XDIM+(ZDIM-1)*XDIM*YDIM]<<","<<velAv[1][i+j*XDIM+(ZDIM/GPU_N-1)*XDIM*YDIM]<<", "
              <<velFluc[0][i+j*XDIM+(ZDIM-1)*XDIM*YDIM]<<","<<velFluc[1][i+j*XDIM+(ZDIM/GPU_N-1)*XDIM*YDIM]<<endl;
    }}
}



void WriteInputs(ostream &output, float omega, float omegaLR, int GPU_per_node)
{
    output<<"Base domain size \t"<<XDIM<<"x"<<YDIM<<"x"<<ZDIM<<endl;
	output<<"Base blocksize: \t"<<BLOCKSIZEX<<"x"<<BLOCKSIZEY<<"x"<<BLOCKSIZEZ<<endl;
	output<<"Obst1 location: \t("<<OBSTX1<<","<<OBSTY1<<","<<OBSTZ1<<")"<<endl;
	output<<"Obst1 radius: \t"<<OBSTR1<<endl;
	output<<"Obst2 location: \t("<<OBSTX2<<","<<OBSTY2<<","<<OBSTZ2<<")"<<endl;
	output<<"Obst2 radius: \t"<<OBSTR2<<endl;
	output<<"RE: \t"<<RE<<endl;
	output<<"UMAX: \t"<<UMAX<<endl;
    output<<"omega \t: "<<omega<<endl;
	output<<"TMAX: \t"<<TMAX<<endl;
	output<<"STARTF: \t"<<STARTF<<endl;
	output<<"START_VELAV: \t"<<START_VELAV<<endl;
	output<<"START_VELFLUC: \t"<<START_VELFLUC<<endl;
	output<<"REFINEMENT: \t"<<REFINEMENT<<endl;
	output<<"MODEL: \t"<<MODEL<<endl;
	output<<"Smagorinski LES: \t"<<SmagLES<<endl;
	output<<"CS: \t"<<CS<<endl;
    output<<"LR domain size \t"<<XLRDIM<<"x"<<YLRDIM<<"x"<<ZLRDIM<<endl;
    output<<"LR factor \t"<<LRFACTOR<<endl;
    output<<"LR location \t"<<LRX0<<"x"<<LRY0<<"x"<<LRZ0<<endl;
	output<<"LR blocksize: \t"<<BLOCKSIZELRX<<"x"<<BLOCKSIZELRY<<"x"<<BLOCKSIZELRZ<<endl;   
	output<<"omega in LR \t: "<<omegaLR<<endl;
	output<<"GPUs per node \t: "<<GPU_per_node<<endl;
}





int main(int argc, char *argv[])
{
    
	int GPU_N;
	cudaGetDeviceCount(&GPU_N);
	cout<<"number of GPUs: "<<GPU_N<<endl;

	ofstream output;
	ofstream outputForce;
	ofstream outputInputs;
	string FileName = CASENAME;
	output.open ((FileName+".dat").c_str());
	outputForce.open ((FileName+".force").c_str());
	outputInputs.open ((FileName+".inputs").c_str());

	//size_t memsize, memsize2;
	size_t pitch = 2;
	while(pitch<XDIM)
		pitch=pitch*2;
	pitch *= sizeof(float);//pitch*sizeof(float);
	size_t pitch_e = pitch/sizeof(float);
	cout<<"Pitch (in elements): "<<pitch/sizeof(float)<<endl;

	float CharLength = OBSTR1*2.f;

	float omega = 1.0f/(3.0f*(UMAX*CharLength/RE)+0.5f);
	float omegaLR = 2.0f/(1.0f+2.0f*(2.0f/omega-1.0f));
	if(LRFACTOR == 0.25f){
	omegaLR = 2.0f/(1.0f+2.0f*(2.0f/omegaLR-1.0f));
	}
	float SF_cf = omega*(1.0f-omegaLR)/((1.0f-omega)*omegaLR/LRFACTOR);
	float SF_fc = 1.f/SF_cf;

    WriteInputs(outputInputs,omega,omegaLR,GPU_N);
    WriteInputs(cout,omega,omegaLR,GPU_N);

	if(abs(LRFACTOR-1.f/LRLEVEL)>0.001f && REFINEMENT == 1){
		cout<<"LRLEVEL and LRFACTOR don't match! Exiting..."<<endl;
		return 0;
	}

    int zInner = ZDIM/GPU_N-2; //excluding halo
    int ForceTime = max(0,TMAX-STARTF);

    dim3 threads(BLOCKSIZEX, BLOCKSIZEY, BLOCKSIZEZ);
	//2 halo layers per GPU (for 2 GPUs)
    dim3 grid  (((XDIM+BLOCKSIZEX-1)/BLOCKSIZEX),((YDIM+BLOCKSIZEY-1)/BLOCKSIZEY),(zInner)/BLOCKSIZEZ);
    dim3 g_grid(((XDIM+BLOCKSIZEX-1)/BLOCKSIZEX),((YDIM+BLOCKSIZEY-1)/BLOCKSIZEY),1);

    cudaStream_t stream_halo[GPU_N];
    cudaStream_t stream_inner[GPU_N];

    //data pointers as 3D array (GPUxCoord)
    float   *f_h[GPU_N],   *g_h[GPU_N],   *h_h[GPU_N];
    float *f_d[GPU_N][2], *g_d[GPU_N][2], *h_d[GPU_N][2];
    float *g_temp[GPU_N], *h_temp[GPU_N];
    float *F_h[GPU_N][3];
    float *F_d[GPU_N][3];
    float *F_total[3];
    float *velAv_h[GPU_N][3],*velFluc_h[GPU_N][3];
    float *velAv_d[GPU_N][3],*velFluc_d[GPU_N][3];

    for(int i = 0; i<3; i++)
	F_total[i] = (float *)malloc(ForceTime*sizeof(float));
	
    for(int i=0;i<3;i++)
    for(int j=0;j<(ForceTime);j++)
        F_total[i][j] = 0;

    //Malloc and Initialize for each GPU
    for(int n = 0; n<GPU_N; n++){
    	f_h    [n] = (float *)malloc(XDIM*YDIM*zInner*19*sizeof(float));
    	g_h    [n] = (float *)malloc(XDIM*YDIM*       19*sizeof(float));
    	h_h    [n] = (float *)malloc(XDIM*YDIM*       19*sizeof(float));
        for(int i = 0; i<3; i++){
    	F_h      [n][i] = (float *)malloc(ForceTime*sizeof(float));
    	velAv_h  [n][i] = (float *)malloc(XDIM*YDIM*ZDIM/GPU_N*sizeof(float));
    	velFluc_h[n][i] = (float *)malloc(XDIM*YDIM*ZDIM/GPU_N*sizeof(float));
        }
        cudaSetDevice(n);
    	cudaStreamCreate(&stream_halo[n]);
    	cudaStreamCreate(&stream_inner[n]);
        for(int m = 0; m<GPU_N; m++)
            if(m != n) cudaDeviceEnablePeerAccess(m,0);

        for(int i = 0; i<2; i++){
       	cudaMalloc((void **) &f_d[n][i], pitch_e*YDIM*zInner*19*sizeof(float));
    	cudaMalloc((void **) &g_d[n][i], pitch_e*YDIM*       19*sizeof(float));
    	cudaMalloc((void **) &h_d[n][i], pitch_e*YDIM*       19*sizeof(float));
        }
    	cudaMalloc((void **) & g_temp[n], pitch_e*YDIM*       19*sizeof(float));
    	cudaMalloc((void **) & h_temp[n], pitch_e*YDIM*       19*sizeof(float));
        for(int i = 0; i<3; i++){
    	cudaMalloc((void **) & F_d      [n][i], (ForceTime)*sizeof(float));
	    cudaMalloc((void **) & velAv_d  [n][i], pitch_e*YDIM*ZDIM/GPU_N*sizeof(float));
	    cudaMalloc((void **) & velFluc_d[n][i], pitch_e*YDIM*ZDIM/GPU_N*sizeof(float));
        }

    	//initialize host f_inner
    	for (int i = 0; i < XDIM*YDIM*zInner*19; i++)
    		f_h[n][i] = 0;
    	//initialize host g,h
    	for (int i = 0; i < XDIM*YDIM*19; i++){
    		g_h[n][i] = 0;
    		h_h[n][i] = 0;
    	}
        for(int i=0;i<3;i++){
            for(int j=0;j<(ForceTime);j++)
                F_h[n][i][j] = 0;
        	for (int j = 0; j < XDIM*YDIM*ZDIM/GPU_N; j++){
            velAv_h  [n][i][j] = 0;
            velFluc_h[n][i][j] = 0;
            }
    	}
        for(int i = 0; i<2; i++){
    	cudaMemcpy2D(f_d[n][i],pitch,f_h[n],XDIM*sizeof(float),XDIM*sizeof(float),YDIM*zInner*19,cudaMemcpyHostToDevice);
    	cudaMemcpy2D(g_d[n][i],pitch,g_h[n],XDIM*sizeof(float),XDIM*sizeof(float),YDIM       *19,cudaMemcpyHostToDevice);
    	cudaMemcpy2D(h_d[n][i],pitch,h_h[n],XDIM*sizeof(float),XDIM*sizeof(float),YDIM       *19,cudaMemcpyHostToDevice);
        }

        for(int i = 0; i<3; i++){
    	cudaMemcpy2D(velAv_d  [n][i],pitch,velAv_h  [n][i],XDIM*sizeof(float),XDIM*sizeof(float),YDIM*ZDIM/GPU_N,cudaMemcpyHostToDevice);
    	cudaMemcpy2D(velFluc_d[n][i],pitch,velFluc_h[n][i],XDIM*sizeof(float),XDIM*sizeof(float),YDIM*ZDIM/GPU_N,cudaMemcpyHostToDevice);
	    cudaMemcpy(F_d[n][i],F_h[n][i],sizeof(float)*(ForceTime),cudaMemcpyHostToDevice);
        }

        //initialization kernels
        for(int i = 0; i<2; i++){
        initialize<<<  grid,threads>>>(f_d[n][i],pitch_e,zInner,GPU_N,0);
        initialize<<<g_grid,threads>>>(g_d[n][i],pitch_e,     1,GPU_N,0);
        initialize<<<g_grid,threads>>>(h_d[n][i],pitch_e,     1,GPU_N,0);
        }
        initialize<<<g_grid,threads>>>(g_temp[n],pitch_e,     1,GPU_N,0);
        initialize<<<g_grid,threads>>>(h_temp[n],pitch_e,     1,GPU_N,0);

    }//end Malloc and Initialize
    

    //setup LR


    int A = 0;
    int B = 1;
    
	struct timeval tdr0,tdr1;
	double restime;
	cudaDeviceSynchronize();
	gettimeofday (&tdr0,NULL);

    for(int n = 0; n<GPU_N; n++){
	cudaSetDevice(n);
    size_t mem_avail, mem_total;
    cudaMemGetInfo(&mem_avail,&mem_total);
    cout<<"Device memory used for dev"<<n<<" : "<<(mem_total-mem_avail)*pow(10,-9)<<" GB\n";
    cout<<"Device memory available for dev"<<n<<" : "<<(mem_avail)*pow(10,-9)<<" GB\n";
    }
    
    //time loop
    for(int t = 0; t<TMAX; t++)
    {
        for(int n = 0; n<GPU_N; n++)
        {
      		cudaSetDevice(n);
    		update_top<<<g_grid, threads, 0, stream_halo [n]>>>(h_d[n][B],h_d[n][A],f_d[n][A],h_temp[n],omega,pitch_e,n,zInner);
    		update_bot<<<g_grid, threads, 0, stream_halo [n]>>>(g_d[n][B],g_d[n][A],f_d[n][A],g_temp[n],omega,pitch_e,n,zInner);
        }
        for(int n = 0; n<GPU_N; n++)
		cudaStreamSynchronize(stream_halo[n]);
        for(int n = 0; n<GPU_N; n++){
		    cudaSetDevice(n);
		    update_inn<<<grid,threads,0,stream_inner[n]>>>(f_d[n][B],f_d[n][A],g_d[n][A], h_d[n][A],omega,pitch_e,n,zInner,velAv_d[n],velFluc_d[n],t);
        }

        for(int n = 0; n<GPU_N; n++)
            cudaMemcpyPeerAsync(&h_temp[n][0],n,&g_d[   (n+1)%GPU_N][B][0],   (n+1)%GPU_N,pitch_e*YDIM*sizeof(float)*19,stream_halo[n]);
        for(int n = 0; n<GPU_N; n++)
            cudaMemcpyPeerAsync(&g_temp[n][0],n,&h_d[abs(n-1)%GPU_N][B][0],abs(n-1)%GPU_N,pitch_e*YDIM*sizeof(float)*19,stream_halo[n]);

	    cudaDeviceSynchronize();
        swap(A,B);




    }



	cudaDeviceSynchronize();
	gettimeofday (&tdr1,NULL);
	timeval_subtract (&restime, &tdr1, &tdr0);
	int Nodes;
	Nodes = XDIM*YDIM*ZDIM;
    if (REFINEMENT == 1)
        Nodes += XLRDIM*YLRDIM*ZLRDIM*LRLEVEL;
	cout<<"Time taken for main kernel: "<<restime<<" ("
			<<double(Nodes*double(TMAX/1000000.f))/restime<<"MLUPS)\n";

    //D2H Memcpy and write results
    for(int n = 0; n<GPU_N; n++){
        cudaSetDevice(n);
    	cudaMemcpy2D(f_h[n],XDIM*sizeof(float),f_d[n][A],pitch,XDIM*sizeof(float),YDIM*zInner*19,cudaMemcpyDeviceToHost);
    	cudaMemcpy2D(g_h[n],XDIM*sizeof(float),g_d[n][A],pitch,XDIM*sizeof(float),YDIM       *19,cudaMemcpyDeviceToHost);
    	cudaMemcpy2D(h_h[n],XDIM*sizeof(float),h_d[n][A],pitch,XDIM*sizeof(float),YDIM       *19,cudaMemcpyDeviceToHost);
        for(int i = 0; i<3; i++){
	    cudaMemcpy2D(  velAv_h[n][i],XDIM*sizeof(float),velAv_d[n][i],pitch,XDIM*sizeof(float),YDIM*ZDIM/GPU_N,cudaMemcpyDeviceToHost);
	    cudaMemcpy2D(velFluc_h[n][i],XDIM*sizeof(float),velAv_d[n][i],pitch,XDIM*sizeof(float),YDIM*ZDIM/GPU_N,cudaMemcpyDeviceToHost);
	    cudaMemcpy(F_h[n][i],F_d[n][i],sizeof(float)*ForceTime,cudaMemcpyDeviceToHost);
        }
        WriteResults(output,f_h[n],g_h[n],h_h[n],velAv_h[n],velFluc_h[n],omega,GPU_N,n);
        output<<endl;

        for(int i=0;i<3;i++)
        for(int j=0;j<ForceTime;j++)
            F_total[i][j] += F_h[n][i][j];
        
        for(int i = 0; i<2; i++){
            cudaFree(f_d[n][i]);
            cudaFree(g_d[n][i]);
            cudaFree(h_d[n][i]);
        }
        cudaFree(f_d[n]);
        cudaFree(g_d[n]);
        cudaFree(h_d[n]);
        cudaFree(g_temp[n]);
        cudaFree(h_temp[n]);
        for(int i=0;i<3;i++)
            cudaFree(F_d[n][i]);
        cudaFree(F_d[n]);




    }//end Memcpy and write results





    return 0;
}

	.file	"tmpxft_0033eac7_00000000-6_bak_LRMultiGPU4.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3797:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3797:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.isra.0.str1.1,"aMS",@progbits,1
.LC0:
	.string	"basic_string::append"
	.section	.text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.isra.0,"axG",@progbits,_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,comdat
	.align 2
	.type	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.isra.0, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.isra.0:
.LFB4536:
	.cfi_startproc
	movabsq	$4611686018427387903, %rax
	subq	8(%rdi), %rax
	cmpq	%rdx, %rax
	jnb	.L3
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	.LC0(%rip), %rdi
	call	_ZSt20__throw_length_errorPKc@PLT
.L3:
	.cfi_def_cfa_offset 8
	jmp	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
	.cfi_endproc
.LFE4536:
	.size	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.isra.0, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.isra.0
	.text
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4538:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4538:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z16timeval_subtractPdP7timevalS1_
	.type	_Z16timeval_subtractPdP7timevalS1_, @function
_Z16timeval_subtractPdP7timevalS1_:
.LFB3769:
	.cfi_startproc
	endbr64
	movq	%rdx, %rcx
	movq	8(%rsi), %rdx
	movq	8(%rcx), %r8
	cmpq	%r8, %rdx
	jge	.L10
	movq	%r8, %rax
	movl	$1000000, %r9d
	subq	%rdx, %rax
	cqto
	idivq	%r9
	incl	%eax
	imull	$1000000, %eax, %edx
	cltq
	addq	%rax, (%rcx)
	movslq	%edx, %rdx
	subq	%rdx, %r8
	movq	%r8, 8(%rcx)
.L10:
	movq	8(%rsi), %rdx
	movq	8(%rcx), %r8
	movq	%rdx, %rax
	subq	%r8, %rax
	cmpq	$1000000, %rax
	jle	.L11
	movq	%r8, %rax
	movl	$1000000, %r9d
	subq	%rdx, %rax
	cqto
	idivq	%r9
	imull	$1000000, %eax, %edx
	cltq
	subq	%rax, (%rcx)
	movslq	%edx, %rdx
	addq	%r8, %rdx
	movq	%rdx, 8(%rcx)
.L11:
	movq	(%rsi), %r8
	movq	(%rcx), %rdx
	movq	8(%rsi), %rax
	subq	8(%rcx), %rax
	cvtsi2sdq	%rax, %xmm0
	movq	%r8, %rax
	divsd	.LC1(%rip), %xmm0
	subq	%rdx, %rax
	cvtsi2sdq	%rax, %xmm1
	xorl	%eax, %eax
	cmpq	%rdx, %r8
	setl	%al
	addsd	%xmm1, %xmm0
	movsd	%xmm0, (%rdi)
	ret
	.cfi_endproc
.LFE3769:
	.size	_Z16timeval_subtractPdP7timevalS1_, .-_Z16timeval_subtractPdP7timevalS1_
	.globl	_Z4dminii
	.type	_Z4dminii, @function
_Z4dminii:
.LFB3770:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3770:
	.size	_Z4dminii, .-_Z4dminii
	.globl	_Z4dmaxi
	.type	_Z4dmaxi, @function
_Z4dmaxi:
.LFB3771:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3771:
	.size	_Z4dmaxi, .-_Z4dmaxi
	.globl	_Z6dmin_pii
	.type	_Z6dmin_pii, @function
_Z6dmin_pii:
.LFB4531:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z4dminii
	.cfi_endproc
.LFE4531:
	.size	_Z6dmin_pii, .-_Z6dmin_pii
	.globl	_Z6dmax_pii
	.type	_Z6dmax_pii, @function
_Z6dmax_pii:
.LFB4533:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z4dminii
	.cfi_endproc
.LFE4533:
	.size	_Z6dmax_pii, .-_Z6dmax_pii
	.globl	_Z13xsymmetry_botPfii
	.type	_Z13xsymmetry_botPfii, @function
_Z13xsymmetry_botPfii:
.LFB3784:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3784:
	.size	_Z13xsymmetry_botPfii, .-_Z13xsymmetry_botPfii
	.globl	_Z13xsymmetry_topPfii
	.type	_Z13xsymmetry_topPfii, @function
_Z13xsymmetry_topPfii:
.LFB4535:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4535:
	.size	_Z13xsymmetry_topPfii, .-_Z13xsymmetry_topPfii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"VARIABLES = \"X\",\"Y\",\"Z\",\"u\",\"v\",\"w\",\"rho\",\"velAv[0]\",\"velAv[1]\",\"ufluc\",\"vfluc\"\n"
.LC4:
	.string	"ZONE F=POINT, I="
.LC5:
	.string	", J="
.LC6:
	.string	", K="
.LC7:
	.string	"\n"
.LC8:
	.string	", "
.LC9:
	.string	","
	.text
	.globl	_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii
	.type	_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii, @function
_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii:
.LFB3790:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	movq	%rcx, 48(%rsp)
	movq	%rdi, 8(%rsp)
	movq	%rsi, 40(%rsp)
	leaq	.LC3(%rip), %rsi
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	8(%rsp), %rdi
	leaq	.LC4(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$64, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$64, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movl	$8, %eax
	cltd
	idivl	256(%rsp)
	movslq	%eax, %rbx
	movl	%ebx, %esi
	call	_ZNSolsEi@PLT
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	264(%rsp), %eax
	xorl	%edx, %edx
	imull	%ebx, %eax
	movl	%eax, 20(%rsp)
.L25:
	movl	%edx, 24(%rsp)
	movq	%rdx, %rbp
	xorl	%r12d, %r12d
	salq	$8, %rbp
.L29:
	leaq	0(%r13,%rbp), %rsi
	xorl	%eax, %eax
	xorps	%xmm3, %xmm3
.L26:
	movss	(%rsi), %xmm0
	addq	$16384, %rsi
	movss	%xmm0, 108(%rsp,%rax,4)
	incq	%rax
	addss	%xmm0, %xmm3
	cmpq	$19, %rax
	jne	.L26
	movss	112(%rsp), %xmm0
	subss	120(%rsp), %xmm0
	movl	%r12d, %esi
	movq	%rdx, 64(%rsp)
	movss	128(%rsp), %xmm13
	movss	116(%rsp), %xmm2
	incl	%r12d
	movss	%xmm3, 72(%rsp)
	movss	132(%rsp), %xmm12
	subss	124(%rsp), %xmm2
	addss	%xmm13, %xmm0
	movq	8(%rsp), %rdi
	movss	136(%rsp), %xmm11
	movss	140(%rsp), %xmm10
	movss	148(%rsp), %xmm1
	movss	152(%rsp), %xmm9
	addss	%xmm13, %xmm2
	movss	156(%rsp), %xmm8
	movss	160(%rsp), %xmm14
	subss	%xmm12, %xmm0
	movss	168(%rsp), %xmm7
	movss	172(%rsp), %xmm6
	movss	176(%rsp), %xmm5
	movss	180(%rsp), %xmm4
	addss	%xmm12, %xmm2
	subss	%xmm11, %xmm0
	subss	%xmm11, %xmm2
	addss	%xmm10, %xmm0
	subss	%xmm10, %xmm2
	addss	%xmm1, %xmm0
	addss	144(%rsp), %xmm1
	addss	%xmm9, %xmm2
	addss	%xmm9, %xmm1
	subss	%xmm8, %xmm0
	subss	%xmm14, %xmm2
	addss	%xmm8, %xmm1
	addss	%xmm7, %xmm0
	addss	%xmm6, %xmm2
	addss	%xmm14, %xmm1
	subss	%xmm5, %xmm0
	subss	164(%rsp), %xmm1
	subss	%xmm4, %xmm2
	movss	%xmm0, 60(%rsp)
	subss	%xmm7, %xmm1
	movss	%xmm2, 56(%rsp)
	subss	%xmm6, %xmm1
	subss	%xmm5, %xmm1
	subss	%xmm4, %xmm1
	movss	%xmm1, 32(%rsp)
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	24(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	20(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	60(%rsp), %xmm0
	movq	%rax, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	56(%rsp), %xmm2
	movq	%rax, %rdi
	cvtss2sd	%xmm2, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	32(%rsp), %xmm1
	movq	%rax, %rdi
	cvtss2sd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	72(%rsp), %xmm3
	movq	%rax, %rdi
	cvtss2sd	%xmm3, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	(%r14), %rax
	cvtss2sd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	8(%r14), %rax
	cvtss2sd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	(%r15), %rax
	cvtss2sd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	8(%r15), %rax
	cvtss2sd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	addq	$4, %rbp
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	cmpl	$64, %r12d
	movq	64(%rsp), %rdx
	jne	.L29
	incq	%rdx
	cmpq	$64, %rdx
	jne	.L25
	leal	-2(%rbx), %eax
	movl	$4096, %r9d
	movl	$1, %r12d
	sall	$12, %eax
	cltq
	salq	$2, %rax
	movq	%rax, 24(%rsp)
.L28:
	leal	-1(%rbx), %eax
	cmpl	%r12d, %eax
	jle	.L34
	leaq	0(,%r9,4), %r10
	xorl	%r13d, %r13d
.L35:
	movq	%r13, %rbp
	movl	%r13d, 32(%rsp)
	xorl	%r8d, %r8d
	salq	$8, %rbp
	addq	%r10, %rbp
.L33:
	movq	40(%rsp), %rax
	xorps	%xmm3, %xmm3
	leaq	-16384(%rax,%rbp), %rsi
	xorl	%eax, %eax
.L30:
	movss	(%rsi), %xmm0
	movq	24(%rsp), %rcx
	movss	%xmm0, 108(%rsp,%rax,4)
	incq	%rax
	addss	%xmm0, %xmm3
	addq	%rcx, %rsi
	cmpq	$19, %rax
	jne	.L30
	movss	112(%rsp), %xmm0
	subss	120(%rsp), %xmm0
	movl	%r8d, %esi
	movq	%r10, 88(%rsp)
	movss	128(%rsp), %xmm13
	movss	116(%rsp), %xmm2
	movq	%r9, 80(%rsp)
	subss	124(%rsp), %xmm2
	movq	8(%rsp), %rdi
	movl	%r8d, 56(%rsp)
	addss	%xmm13, %xmm0
	movss	%xmm3, 76(%rsp)
	movss	132(%rsp), %xmm12
	movss	136(%rsp), %xmm11
	movss	140(%rsp), %xmm10
	movss	148(%rsp), %xmm1
	movss	152(%rsp), %xmm9
	addss	%xmm13, %xmm2
	movss	156(%rsp), %xmm8
	movss	160(%rsp), %xmm14
	subss	%xmm12, %xmm0
	movss	168(%rsp), %xmm7
	movss	172(%rsp), %xmm6
	movss	176(%rsp), %xmm5
	movss	180(%rsp), %xmm4
	addss	%xmm12, %xmm2
	subss	%xmm11, %xmm0
	subss	%xmm11, %xmm2
	addss	%xmm10, %xmm0
	subss	%xmm10, %xmm2
	addss	%xmm1, %xmm0
	addss	144(%rsp), %xmm1
	addss	%xmm9, %xmm2
	addss	%xmm9, %xmm1
	subss	%xmm8, %xmm0
	subss	%xmm14, %xmm2
	addss	%xmm8, %xmm1
	addss	%xmm7, %xmm0
	addss	%xmm6, %xmm2
	addss	%xmm14, %xmm1
	subss	%xmm5, %xmm0
	subss	164(%rsp), %xmm1
	subss	%xmm4, %xmm2
	movss	%xmm0, 64(%rsp)
	subss	%xmm7, %xmm1
	movss	%xmm2, 72(%rsp)
	subss	%xmm6, %xmm1
	subss	%xmm5, %xmm1
	subss	%xmm4, %xmm1
	movss	%xmm1, 60(%rsp)
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	32(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movl	20(%rsp), %eax
	leal	(%rax,%r12), %esi
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	64(%rsp), %xmm0
	movq	%rax, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	72(%rsp), %xmm2
	movq	%rax, %rdi
	cvtss2sd	%xmm2, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	60(%rsp), %xmm1
	movq	%rax, %rdi
	cvtss2sd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	76(%rsp), %xmm3
	movq	%rax, %rdi
	cvtss2sd	%xmm3, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	(%r14), %rax
	cvtss2sd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	8(%r14), %rax
	cvtss2sd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	(%r15), %rax
	cvtss2sd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	8(%r15), %rax
	cvtss2sd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	addq	$4, %rbp
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	56(%rsp), %r8d
	movq	80(%rsp), %r9
	movq	88(%rsp), %r10
	incl	%r8d
	cmpl	$64, %r8d
	jne	.L33
	incq	%r13
	cmpq	$64, %r13
	jne	.L35
	incl	%r12d
	addq	$4096, %r9
	jmp	.L28
.L34:
	movl	20(%rsp), %eax
	xorl	%r13d, %r13d
	leal	-1(%rax,%rbx), %eax
	salq	$14, %rbx
	movl	%eax, 20(%rsp)
.L36:
	movl	%r13d, 24(%rsp)
	movq	%r13, %rbp
	xorl	%r12d, %r12d
	salq	$8, %rbp
.L40:
	movq	48(%rsp), %rax
	xorps	%xmm3, %xmm3
	leaq	(%rax,%rbp), %rsi
	xorl	%eax, %eax
.L37:
	movss	(%rsi), %xmm0
	addq	$16384, %rsi
	movss	%xmm0, 108(%rsp,%rax,4)
	incq	%rax
	addss	%xmm0, %xmm3
	cmpq	$19, %rax
	jne	.L37
	movss	112(%rsp), %xmm0
	subss	120(%rsp), %xmm0
	movl	%r12d, %esi
	movss	%xmm3, 60(%rsp)
	movss	128(%rsp), %xmm13
	movss	116(%rsp), %xmm2
	incl	%r12d
	movss	132(%rsp), %xmm12
	subss	124(%rsp), %xmm2
	addss	%xmm13, %xmm0
	movq	8(%rsp), %rdi
	movss	136(%rsp), %xmm11
	movss	140(%rsp), %xmm10
	movss	148(%rsp), %xmm1
	movss	152(%rsp), %xmm9
	addss	%xmm13, %xmm2
	movss	156(%rsp), %xmm8
	movss	160(%rsp), %xmm14
	subss	%xmm12, %xmm0
	movss	168(%rsp), %xmm7
	movss	172(%rsp), %xmm6
	movss	176(%rsp), %xmm5
	movss	180(%rsp), %xmm4
	addss	%xmm12, %xmm2
	subss	%xmm11, %xmm0
	subss	%xmm11, %xmm2
	addss	%xmm10, %xmm0
	subss	%xmm10, %xmm2
	addss	%xmm1, %xmm0
	addss	144(%rsp), %xmm1
	addss	%xmm9, %xmm2
	addss	%xmm9, %xmm1
	subss	%xmm8, %xmm0
	subss	%xmm14, %xmm2
	addss	%xmm8, %xmm1
	addss	%xmm7, %xmm0
	addss	%xmm6, %xmm2
	addss	%xmm14, %xmm1
	subss	%xmm5, %xmm0
	subss	164(%rsp), %xmm1
	subss	%xmm4, %xmm2
	movss	%xmm0, 56(%rsp)
	subss	%xmm7, %xmm1
	movss	%xmm2, 40(%rsp)
	subss	%xmm6, %xmm1
	subss	%xmm5, %xmm1
	subss	%xmm4, %xmm1
	movss	%xmm1, 32(%rsp)
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	24(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	20(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	56(%rsp), %xmm0
	movq	%rax, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	40(%rsp), %xmm2
	movq	%rax, %rdi
	cvtss2sd	%xmm2, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	32(%rsp), %xmm1
	movq	%rax, %rdi
	cvtss2sd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	60(%rsp), %xmm3
	movq	%rax, %rdi
	cvtss2sd	%xmm3, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	(%r14), %rax
	cvtss2sd	114688(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	-16384(%rbx,%rbp), %r8
	movq	%rax, %rdi
	movq	8(%r14), %rax
	movq	%r8, 32(%rsp)
	cvtss2sd	(%rax,%r8), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	(%r15), %rax
	cvtss2sd	114688(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC9(%rip), %rsi
	addq	$4, %rbp
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	32(%rsp), %r8
	movq	%rax, %rdi
	movq	8(%r15), %rax
	cvtss2sd	(%rax,%r8), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	cmpl	$64, %r12d
	jne	.L40
	incq	%r13
	cmpq	$64, %r13
	jne	.L36
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3790:
	.size	_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii, .-_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii
	.section	.rodata.str1.1
.LC10:
	.string	"Base domain size \t"
.LC11:
	.string	"x"
.LC12:
	.string	"Base blocksize: \t"
.LC13:
	.string	"Obst1 location: \t("
.LC16:
	.string	")"
.LC17:
	.string	"Obst1 radius: \t"
.LC19:
	.string	"Obst2 location: \t("
.LC23:
	.string	"Obst2 radius: \t"
.LC25:
	.string	"RE: \t"
.LC27:
	.string	"UMAX: \t"
.LC29:
	.string	"omega \t: "
.LC30:
	.string	"TMAX: \t"
.LC31:
	.string	"STARTF: \t"
.LC32:
	.string	"START_VELAV: \t"
.LC33:
	.string	"START_VELFLUC: \t"
.LC34:
	.string	"REFINEMENT: \t"
.LC35:
	.string	"MODEL: \t"
.LC36:
	.string	"MRT"
.LC37:
	.string	"Smagorinski LES: \t"
.LC38:
	.string	"CS: \t"
.LC40:
	.string	"LR domain size \t"
.LC41:
	.string	"LR factor \t"
.LC43:
	.string	"LR location \t"
.LC46:
	.string	"LR blocksize: \t"
.LC47:
	.string	"omega in LR \t: "
.LC48:
	.string	"GPUs per node \t: "
	.text
	.globl	_Z11WriteInputsRSoffi
	.type	_Z11WriteInputsRSoffi, @function
_Z11WriteInputsRSoffi:
.LFB3791:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	leaq	.LC16(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%esi, %r13d
	leaq	.LC10(%rip), %rsi
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	leaq	.LC9(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	leaq	.LC11(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rdi, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	movss	%xmm1, 8(%rsp)
	movss	%xmm0, 12(%rsp)
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$64, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$64, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$8, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC12(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$64, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC13(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC14(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC14(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC15(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r14, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC17(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC18(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC19(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC20(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC21(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC22(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%r14, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC23(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC24(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC25(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC26(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC27(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC28(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC29(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	12(%rsp), %xmm2
	movq	%rax, %rdi
	cvtss2sd	%xmm2, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC30(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1000, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC31(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	xorl	%esi, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC32(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$400000, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC33(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$700000, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC34(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	xorl	%esi, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC35(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC36(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC37(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	xorl	%esi, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC38(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC39(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC40(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$48, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$64, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$8, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC41(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC42(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC43(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC44(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC44(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	.LC45(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC46(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$48, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	.LC47(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movss	8(%rsp), %xmm1
	movq	%rax, %rdi
	cvtss2sd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC48(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	movq	%rax, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_ZNSolsEPFRSoS_E.isra.0
	.cfi_endproc
.LFE3791:
	.size	_Z11WriteInputsRSoffi, .-_Z11WriteInputsRSoffi
	.globl	_Z34__device_stub__Z10initializePfmiiiPfmiii
	.type	_Z34__device_stub__Z10initializePfmiiiPfmiii, @function
_Z34__device_stub__Z10initializePfmiiiPfmiii:
.LFB3819:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10initializePfmiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L49:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3819:
	.size	_Z34__device_stub__Z10initializePfmiiiPfmiii, .-_Z34__device_stub__Z10initializePfmiiiPfmiii
	.globl	_Z10initializePfmiii
	.type	_Z10initializePfmiii, @function
_Z10initializePfmiii:
.LFB3820:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10initializePfmiiiPfmiii
	.cfi_endproc
.LFE3820:
	.size	_Z10initializePfmiii, .-_Z10initializePfmiii
	.globl	_Z40__device_stub__Z10update_topPfS_S_S_fmiiPfS_S_S_fmii
	.type	_Z40__device_stub__Z10update_topPfS_S_S_fmiiPfS_S_S_fmii, @function
_Z40__device_stub__Z10update_topPfS_S_S_fmiiPfS_S_S_fmii:
.LFB3821:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, (%rsp)
	movl	%r9d, 8(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10update_topPfS_S_S_fmii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L54:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3821:
	.size	_Z40__device_stub__Z10update_topPfS_S_S_fmiiPfS_S_S_fmii, .-_Z40__device_stub__Z10update_topPfS_S_S_fmiiPfS_S_S_fmii
	.globl	_Z10update_topPfS_S_S_fmii
	.type	_Z10update_topPfS_S_S_fmii, @function
_Z10update_topPfS_S_S_fmii:
.LFB3822:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z10update_topPfS_S_S_fmiiPfS_S_S_fmii
	.cfi_endproc
.LFE3822:
	.size	_Z10update_topPfS_S_S_fmii, .-_Z10update_topPfS_S_S_fmii
	.globl	_Z40__device_stub__Z10update_botPfS_S_S_fmiiPfS_S_S_fmii
	.type	_Z40__device_stub__Z10update_botPfS_S_S_fmiiPfS_S_S_fmii, @function
_Z40__device_stub__Z10update_botPfS_S_S_fmiiPfS_S_S_fmii:
.LFB3823:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, (%rsp)
	movl	%r9d, 8(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10update_botPfS_S_S_fmii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L59:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3823:
	.size	_Z40__device_stub__Z10update_botPfS_S_S_fmiiPfS_S_S_fmii, .-_Z40__device_stub__Z10update_botPfS_S_S_fmiiPfS_S_S_fmii
	.globl	_Z10update_botPfS_S_S_fmii
	.type	_Z10update_botPfS_S_S_fmii, @function
_Z10update_botPfS_S_S_fmii:
.LFB3824:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z10update_botPfS_S_S_fmiiPfS_S_S_fmii
	.cfi_endproc
.LFE3824:
	.size	_Z10update_botPfS_S_S_fmii, .-_Z10update_botPfS_S_S_fmii
	.globl	_Z47__device_stub__Z10update_innPfS_S_S_fmiiPS_S0_iPfS_S_S_fmiiPS_S0_i
	.type	_Z47__device_stub__Z10update_innPfS_S_S_fmiiPS_S0_iPfS_S_S_fmiiPS_S0_i, @function
_Z47__device_stub__Z10update_innPfS_S_S_fmiiPS_S0_iPfS_S_S_fmiiPS_S0_i:
.LFB3825:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	248(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	256(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm0, 28(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	%rsp, %rax
	movq	%rax, 200(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	72(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z10update_innPfS_S_S_fmiiPS_S0_i(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 256
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L64:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3825:
	.size	_Z47__device_stub__Z10update_innPfS_S_S_fmiiPS_S0_iPfS_S_S_fmiiPS_S0_i, .-_Z47__device_stub__Z10update_innPfS_S_S_fmiiPS_S0_iPfS_S_S_fmiiPS_S0_i
	.globl	_Z10update_innPfS_S_S_fmiiPS_S0_i
	.type	_Z10update_innPfS_S_S_fmiiPS_S0_i, @function
_Z10update_innPfS_S_S_fmiiPS_S0_i:
.LFB3826:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z10update_innPfS_S_S_fmiiPS_S0_iPfS_S_S_fmiiPS_S0_i
	.cfi_endproc
.LFE3826:
	.size	_Z10update_innPfS_S_S_fmiiPS_S0_i, .-_Z10update_innPfS_S_S_fmiiPS_S0_i
	.section	.rodata.str1.1
.LC49:
	.string	"_Z10update_innPfS_S_S_fmiiPS_S0_i"
.LC50:
	.string	"_Z10update_botPfS_S_S_fmii"
.LC51:
	.string	"_Z10update_topPfS_S_S_fmii"
.LC52:
	.string	"_Z10initializePfmiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3828:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC49(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10update_innPfS_S_S_fmiiPS_S0_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC50(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10update_botPfS_S_S_fmii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC51(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10update_topPfS_S_S_fmii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC52(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10initializePfmiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3828:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,"axG",@progbits,_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,comdat
	.weak	_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_
	.type	_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_, @function
_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_:
.LFB4158:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA4158
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rdi, %rbx
	movq	%rdx, %rdi
	call	strlen@PLT
	movq	8(%r13), %r14
	movq	0(%r13), %r13
	movq	%rbx, %rdi
	movq	%rax, %r12
	leaq	16(%rbx), %rax
	movb	$0, 16(%rbx)
	movq	%rax, (%rbx)
	xorl	%eax, %eax
	leaq	(%r12,%r14), %rsi
	movq	%rax, 8(%rbx)
.LEHB0:
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm@PLT
	movq	%r14, %rdx
	movq	%r13, %rsi
	movq	%rbx, %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.isra.0
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.isra.0
.LEHE0:
	movq	%rbx, %rax
	popq	%rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
.L74:
	.cfi_restore_state
	endbr64
	movq	%rax, %rbp
.L73:
	movq	%rbx, %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	movq	%rbp, %rdi
.LEHB1:
	call	_Unwind_Resume@PLT
.LEHE1:
	.cfi_endproc
.LFE4158:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table._ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,"aG",@progbits,_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,comdat
.LLSDA4158:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE4158-.LLSDACSB4158
.LLSDACSB4158:
	.uleb128 .LEHB0-.LFB4158
	.uleb128 .LEHE0-.LEHB0
	.uleb128 .L74-.LFB4158
	.uleb128 0
	.uleb128 .LEHB1-.LFB4158
	.uleb128 .LEHE1-.LEHB1
	.uleb128 0
	.uleb128 0
.LLSDACSE4158:
	.section	.text._ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,"axG",@progbits,_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_,comdat
	.size	_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_, .-_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_
	.section	.rodata.str1.1
.LC53:
	.string	"number of GPUs: "
.LC54:
	.string	"test_new"
.LC55:
	.string	".dat"
.LC56:
	.string	".force"
.LC57:
	.string	".inputs"
.LC58:
	.string	"Pitch (in elements): "
.LC61:
	.string	"Device memory used for dev"
.LC62:
	.string	" : "
.LC64:
	.string	" GB\n"
.LC65:
	.string	"Device memory available for dev"
.LC66:
	.string	"Time taken for main kernel: "
.LC67:
	.string	" ("
.LC69:
	.string	"MLUPS)\n"
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB3792:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA3792
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	leaq	-1740(%rbp), %rdi
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	leaq	-1592(%rbp), %r15
	pushq	%r13
	leaq	-1080(%rbp), %r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	leaq	_ZSt4cout(%rip), %rbx
	subq	$1944, %rsp
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
.LEHB2:
	call	cudaGetDeviceCount@PLT
	leaq	.LC53(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	-1740(%rbp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%r15, %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE2:
	movq	%r14, %rdi
.LEHB3:
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE3:
	leaq	-568(%rbp), %r12
	movq	%r12, %rdi
.LEHB4:
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE4:
	leaq	8+.LC54(%rip), %rdx
	leaq	-1640(%rbp), %rdi
	leaq	-8(%rdx), %rsi
	movq	%rdi, -1656(%rbp)
	leaq	-1656(%rbp), %r13
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_S_copy_charsEPcPKcS7_@PLT
	movq	-1656(%rbp), %rax
	leaq	.LC55(%rip), %rdx
	movq	%r13, %rsi
	movq	$8, -1648(%rbp)
	movb	$0, 8(%rax)
	leaq	-1624(%rbp), %rax
	movq	%rax, %rdi
	movq	%rax, -1752(%rbp)
.LEHB5:
	call	_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_
.LEHE5:
	movq	-1624(%rbp), %rsi
	movl	$16, %edx
	movq	%r15, %rdi
.LEHB6:
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE6:
	movq	-1752(%rbp), %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	movq	-1752(%rbp), %rdi
	leaq	.LC56(%rip), %rdx
	movq	%r13, %rsi
.LEHB7:
	call	_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_
.LEHE7:
	movq	-1624(%rbp), %rsi
	movl	$16, %edx
	movq	%r14, %rdi
.LEHB8:
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE8:
	movq	-1752(%rbp), %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	movq	-1752(%rbp), %rdi
	leaq	.LC57(%rip), %rdx
	movq	%r13, %rsi
.LEHB9:
	call	_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_
.LEHE9:
	movq	-1624(%rbp), %rsi
	movl	$16, %edx
	movq	%r12, %rdi
.LEHB10:
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE10:
	movq	-1752(%rbp), %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	leaq	.LC58(%rip), %rsi
	movq	%rbx, %rdi
.LEHB11:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movl	$64, %esi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	-1740(%rbp), %esi
	movss	.LC59(%rip), %xmm1
	movq	%r12, %rdi
	movss	.LC60(%rip), %xmm0
	call	_Z11WriteInputsRSoffi
	movl	-1740(%rbp), %esi
	movss	.LC59(%rip), %xmm1
	movq	%rbx, %rdi
	movss	.LC60(%rip), %xmm0
	call	_Z11WriteInputsRSoffi
	movl	-1740(%rbp), %ecx
	movl	$8, %eax
	movq	%rsp, %rsi
	movl	$1, -1716(%rbp)
	movl	$1, -1692(%rbp)
	cltd
	idivl	%ecx
	subl	$2, %eax
	movl	%eax, -1768(%rbp)
	movl	$67108865, %eax
	movl	-1768(%rbp), %ebx
	salq	$6, %rax
	movq	%rax, -1724(%rbp)
	movabsq	$274877906945, %rax
	movq	%rax, -1712(%rbp)
	movq	%rax, -1700(%rbp)
	movslq	%ecx, %rax
	leaq	15(,%rax,8), %rdx
	movl	%ebx, -1704(%rbp)
	movq	%rdx, %rdi
	movq	%rdx, %rcx
	andq	$-4096, %rdi
	andq	$-16, %rcx
	subq	%rdi, %rsi
.L78:
	cmpq	%rsi, %rsp
	je	.L79
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L78
.L79:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L80
	orq	$0, -8(%rsp,%rcx)
.L80:
	movq	%rdx, %rdi
	movq	%rsp, -1792(%rbp)
	movq	%rdx, %rcx
	movq	%rsp, %rsi
	andq	$-4096, %rdi
	andq	$-16, %rcx
	subq	%rdi, %rsi
.L81:
	cmpq	%rsi, %rsp
	je	.L82
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L81
.L82:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L83
	orq	$0, -8(%rsp,%rcx)
.L83:
	movq	%rdx, %rdi
	movq	%rsp, -1928(%rbp)
	movq	%rdx, %rcx
	movq	%rsp, %rsi
	andq	$-4096, %rdi
	andq	$-16, %rcx
	subq	%rdi, %rsi
.L84:
	cmpq	%rsi, %rsp
	je	.L85
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L84
.L85:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L86
	orq	$0, -8(%rsp,%rcx)
.L86:
	movq	%rdx, %rdi
	movq	%rsp, -1936(%rbp)
	movq	%rdx, %rcx
	movq	%rsp, %rsi
	andq	$-4096, %rdi
	andq	$-16, %rcx
	subq	%rdi, %rsi
.L87:
	cmpq	%rsi, %rsp
	je	.L88
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L87
.L88:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L89
	orq	$0, -8(%rsp,%rcx)
.L89:
	movq	%rdx, %rdi
	movq	%rsp, -1944(%rbp)
	movq	%rdx, %rcx
	movq	%rsp, %rsi
	andq	$-4096, %rdi
	andq	$-16, %rcx
	subq	%rdi, %rsi
.L90:
	cmpq	%rsi, %rsp
	je	.L91
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L90
.L91:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L92
	orq	$0, -8(%rsp,%rcx)
.L92:
	movq	%rax, %rcx
	movq	%rsp, -1952(%rbp)
	movq	%rsp, %rdi
	salq	$4, %rcx
	leaq	15(%rcx), %rsi
	movq	%rsi, %r8
	andq	$-4096, %r8
	subq	%r8, %rdi
.L93:
	cmpq	%rdi, %rsp
	je	.L94
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L93
.L94:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L95
	orq	$0, -8(%rsp,%rcx)
.L95:
	movq	%rsi, %r8
	movq	%rsi, %rcx
	movq	%rsp, %rdi
	movq	%rsp, %r15
	andq	$-4096, %r8
	andq	$-16, %rcx
	subq	%r8, %rdi
.L96:
	cmpq	%rdi, %rsp
	je	.L97
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L96
.L97:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L98
	orq	$0, -8(%rsp,%rcx)
.L98:
	movq	%rsp, -1752(%rbp)
	movq	%rsi, %rcx
	movq	%rsp, %rdi
	andq	$-4096, %rsi
	andq	$-16, %rcx
	subq	%rsi, %rdi
.L99:
	cmpq	%rdi, %rsp
	je	.L100
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L99
.L100:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L101
	orq	$0, -8(%rsp,%rcx)
.L101:
	movq	%rdx, %rdi
	movq	%rsp, -1760(%rbp)
	movq	%rdx, %rcx
	movq	%rsp, %rsi
	andq	$-4096, %rdi
	andq	$-16, %rcx
	subq	%rdi, %rsi
.L102:
	cmpq	%rsi, %rsp
	je	.L103
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L102
.L103:
	andl	$4095, %ecx
	subq	%rcx, %rsp
	testq	%rcx, %rcx
	je	.L104
	orq	$0, -8(%rsp,%rcx)
.L104:
	movq	%rsp, -1808(%rbp)
	movq	%rdx, %rcx
	movq	%rsp, %rsi
	andq	$-4096, %rdx
	andq	$-16, %rcx
	subq	%rdx, %rsi
.L105:
	cmpq	%rsi, %rsp
	je	.L106
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L105
.L106:
	movq	%rcx, %rdx
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L107
	orq	$0, -8(%rsp,%rdx)
.L107:
	imulq	$24, %rax, %rax
	movq	%rsp, -1816(%rbp)
	movq	%rsp, %rsi
	leaq	15(%rax), %rcx
	movq	%rcx, %rdx
	andq	$-4096, %rcx
	andq	$-16, %rdx
	subq	%rcx, %rsi
.L108:
	cmpq	%rsi, %rsp
	je	.L109
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L108
.L109:
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L110
	orq	$0, -8(%rsp,%rdx)
.L110:
	leaq	15(%rax), %rcx
	movq	%rsp, -1824(%rbp)
	movq	%rsp, %rsi
	movq	%rcx, %rdx
	andq	$-4096, %rcx
	andq	$-16, %rdx
	subq	%rcx, %rsi
.L111:
	cmpq	%rsi, %rsp
	je	.L112
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L111
.L112:
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L113
	orq	$0, -8(%rsp,%rdx)
.L113:
	leaq	15(%rax), %rcx
	movq	%rsp, -1776(%rbp)
	movq	%rsp, %rsi
	movq	%rcx, %rdx
	andq	$-4096, %rcx
	andq	$-16, %rdx
	subq	%rcx, %rsi
.L114:
	cmpq	%rsi, %rsp
	je	.L115
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L114
.L115:
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L116
	orq	$0, -8(%rsp,%rdx)
.L116:
	leaq	15(%rax), %rcx
	movq	%rsp, -1832(%rbp)
	movq	%rsp, %rsi
	movq	%rcx, %rdx
	andq	$-4096, %rcx
	andq	$-16, %rdx
	subq	%rcx, %rsi
.L117:
	cmpq	%rsi, %rsp
	je	.L118
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L117
.L118:
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L119
	orq	$0, -8(%rsp,%rdx)
.L119:
	leaq	15(%rax), %rcx
	movq	%rsp, -1840(%rbp)
	movq	%rsp, %rsi
	movq	%rcx, %rdx
	andq	$-4096, %rcx
	andq	$-16, %rdx
	subq	%rcx, %rsi
.L120:
	cmpq	%rsi, %rsp
	je	.L121
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L120
.L121:
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L122
	orq	$0, -8(%rsp,%rdx)
.L122:
	addq	$15, %rax
	movq	%rsp, -1848(%rbp)
	movq	%rsp, %rcx
	movq	%rax, %rdx
	andq	$-4096, %rax
	andq	$-16, %rdx
	subq	%rax, %rcx
.L123:
	cmpq	%rcx, %rsp
	je	.L124
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L123
.L124:
	movq	%rdx, %rax
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L125
	orq	$0, -8(%rsp,%rax)
.L125:
	movl	$4000, %edi
	movq	%rsp, -1896(%rbp)
	call	malloc@PLT
	movl	$4000, %edi
	movq	%rax, -1624(%rbp)
	call	malloc@PLT
	movl	$4000, %edi
	movq	%rax, -1616(%rbp)
	call	malloc@PLT
	xorl	%edx, %edx
	movq	%rax, -1608(%rbp)
	xorl	%eax, %eax
.L126:
	movq	-1624(%rbp,%rdx,8), %rdi
	movl	$1000, %ecx
	incq	%rdx
	rep stosl
	cmpq	$3, %rdx
	jne	.L126
	imull	$77824, -1768(%rbp), %eax
	xorl	%r9d, %r9d
	xorl	%ebx, %ebx
	movq	$8, -1864(%rbp)
	movq	%r9, -1800(%rbp)
	movq	%r9, -1784(%rbp)
	movl	%eax, -1900(%rbp)
	cltq
	salq	$2, %rax
	movq	%r9, -1856(%rbp)
	movq	%rax, -1960(%rbp)
	movslq	-1768(%rbp), %rax
	imulq	$311296, %rax, %rax
	movq	%rax, -1912(%rbp)
	imull	$1216, -1768(%rbp), %eax
	cltq
	movq	%rax, -1920(%rbp)
.L127:
	movl	-1856(%rbp), %eax
	movl	-1740(%rbp), %r13d
	movl	%eax, -1904(%rbp)
	movl	%eax, %r14d
	cmpl	%eax, %r13d
	jle	.L256
	movq	-1960(%rbp), %rdi
	call	malloc@PLT
	movl	$311296, %edi
	movq	%rax, -1872(%rbp)
	movq	-1936(%rbp), %rax
	movq	-1872(%rbp), %rdx
	movq	%rdx, (%rax,%rbx)
	call	malloc@PLT
	movl	$311296, %edi
	movq	%rax, -1880(%rbp)
	movq	-1944(%rbp), %rax
	movq	-1880(%rbp), %rdx
	movq	%rdx, (%rax,%rbx)
	call	malloc@PLT
	movq	-1800(%rbp), %r12
	xorl	%ecx, %ecx
	movq	%rax, -1888(%rbp)
	movq	-1952(%rbp), %rax
	movq	-1888(%rbp), %rsi
	movq	%rsi, (%rax,%rbx)
.L129:
	movl	$4000, %edi
	movl	%ecx, -1972(%rbp)
	call	malloc@PLT
	movq	-1824(%rbp), %rdx
	movq	%rax, (%rdx,%r12)
	movl	$32768, %eax
	cltd
	idivl	%r13d
	cltq
	leaq	0(,%rax,4), %rdi
	movq	%rdi, -1968(%rbp)
	call	malloc@PLT
	movq	-1832(%rbp), %rsi
	movq	-1968(%rbp), %rdi
	movq	%rax, (%rsi,%r12)
	call	malloc@PLT
	movl	-1972(%rbp), %ecx
	movq	-1840(%rbp), %rdx
	incl	%ecx
	movq	%rax, (%rdx,%r12)
	addq	$8, %r12
	cmpl	$3, %ecx
	jne	.L129
	movl	-1904(%rbp), %edi
	call	cudaSetDevice@PLT
	movq	-1792(%rbp), %rax
	leaq	(%rax,%rbx), %rdi
	call	cudaStreamCreate@PLT
	movq	-1928(%rbp), %rax
	leaq	(%rax,%rbx), %rdi
	call	cudaStreamCreate@PLT
	xorl	%r12d, %r12d
.L130:
	cmpl	%r12d, -1740(%rbp)
	jle	.L257
	cmpl	%r14d, %r12d
	je	.L131
	xorl	%esi, %esi
	movl	%r12d, %edi
	call	cudaDeviceEnablePeerAccess@PLT
.L131:
	incl	%r12d
	jmp	.L130
.L257:
	movq	-1784(%rbp), %rax
	movq	-1912(%rbp), %rsi
	leaq	(%r15,%rax), %rdi
	call	cudaMalloc@PLT
	movq	-1784(%rbp), %rsi
	movq	-1752(%rbp), %rax
	leaq	(%rax,%rsi), %rdi
	movl	$311296, %esi
	call	cudaMalloc@PLT
	movq	-1760(%rbp), %rax
	movq	-1784(%rbp), %rdx
	movl	$311296, %esi
	leaq	(%rax,%rdx), %rdi
	call	cudaMalloc@PLT
	movq	-1864(%rbp), %rax
	movq	-1912(%rbp), %rsi
	leaq	(%r15,%rax), %rdi
	call	cudaMalloc@PLT
	movq	-1864(%rbp), %rsi
	movq	-1752(%rbp), %rax
	leaq	(%rax,%rsi), %rdi
	movl	$311296, %esi
	call	cudaMalloc@PLT
	movq	-1760(%rbp), %rax
	movq	-1864(%rbp), %rdx
	movl	$311296, %esi
	leaq	(%rax,%rdx), %rdi
	call	cudaMalloc@PLT
	movq	-1808(%rbp), %rax
	movl	$311296, %esi
	leaq	(%rax,%rbx), %rdi
	call	cudaMalloc@PLT
	movq	-1816(%rbp), %rax
	movl	$311296, %esi
	leaq	(%rax,%rbx), %rdi
	call	cudaMalloc@PLT
	movq	-1800(%rbp), %r12
	xorl	%r14d, %r14d
	movl	$32768, %r13d
.L133:
	movq	-1776(%rbp), %rax
	movl	$4000, %esi
	leaq	(%rax,%r12), %rdi
	call	cudaMalloc@PLT
	movslq	-1740(%rbp), %rcx
	movq	%r13, %rax
	xorl	%edx, %edx
	divq	%rcx
	leaq	0(,%rax,4), %rsi
	movq	-1848(%rbp), %rax
	leaq	(%rax,%r12), %rdi
	call	cudaMalloc@PLT
	movslq	-1740(%rbp), %rcx
	movq	%r13, %rax
	xorl	%edx, %edx
	divq	%rcx
	leaq	0(,%rax,4), %rsi
	movq	-1896(%rbp), %rax
	leaq	(%rax,%r12), %rdi
	call	cudaMalloc@PLT
	incl	%r14d
	addq	$8, %r12
	cmpl	$3, %r14d
	jne	.L133
	xorl	%eax, %eax
.L134:
	cmpl	%eax, -1900(%rbp)
	jle	.L258
	movq	-1872(%rbp), %rsi
	movl	$0x00000000, (%rsi,%rax,4)
	incq	%rax
	jmp	.L134
.L258:
	movq	-1880(%rbp), %rdi
	xorl	%eax, %eax
	movl	$77824, %ecx
	xorl	%r8d, %r8d
	movq	-1800(%rbp), %rsi
	rep stosl
	movq	-1888(%rbp), %rdi
	movl	$77824, %ecx
	rep stosl
	movl	$32768, %eax
	cltd
	idivl	-1740(%rbp)
	movl	%eax, %r9d
	xorl	%eax, %eax
.L136:
	movq	-1824(%rbp), %rdx
	movl	$1000, %ecx
	movq	(%rdx,%rsi), %rdi
	xorl	%edx, %edx
	rep stosl
.L139:
	cmpl	%edx, %r9d
	jle	.L259
	movq	-1832(%rbp), %rcx
	movq	(%rcx,%rsi), %rcx
	movl	$0x00000000, (%rcx,%rdx,4)
	movq	-1840(%rbp), %rcx
	movq	(%rcx,%rsi), %rcx
	movl	$0x00000000, (%rcx,%rdx,4)
	incq	%rdx
	jmp	.L139
.L259:
	incl	%r8d
	addq	$8, %rsi
	cmpl	$3, %r8d
	jne	.L136
	movq	-1784(%rbp), %r12
	xorl	%r13d, %r13d
.L138:
	movq	(%r15,%r12), %rdi
	pushq	%r8
	movl	$256, %ecx
	movl	$256, %esi
	pushq	$1
	movq	-1920(%rbp), %r9
	movl	$256, %r8d
	movq	-1872(%rbp), %rdx
	.cfi_escape 0x2e,0x10
	call	cudaMemcpy2D@PLT
	movl	$1216, %r9d
	movl	$256, %ecx
	movl	$256, %esi
	movq	-1752(%rbp), %rax
	movq	-1880(%rbp), %rdx
	movl	$256, %r8d
	movq	(%rax,%r12), %rdi
	movl	$1, (%rsp)
	call	cudaMemcpy2D@PLT
	movl	$1216, %r9d
	movl	$256, %ecx
	movl	$256, %esi
	movq	-1760(%rbp), %rax
	movq	-1888(%rbp), %rdx
	movl	$256, %r8d
	movq	(%rax,%r12), %rdi
	movl	$1, (%rsp)
	call	cudaMemcpy2D@PLT
	popq	%rsi
	addq	$8, %r12
	popq	%rdi
	testl	%r13d, %r13d
	jne	.L260
	movl	$1, %r13d
	jmp	.L138
.L260:
	movq	-1800(%rbp), %r12
	xorl	%r14d, %r14d
	movl	$512, %r13d
.L140:
	movl	%r13d, %eax
	movq	-1832(%rbp), %rsi
	movl	$256, %r8d
	cltd
	idivl	-1740(%rbp)
	movq	(%rsi,%r12), %rdx
	movq	-1848(%rbp), %rsi
	movq	(%rsi,%r12), %rdi
	pushq	%rcx
	pushq	$1
	movl	$256, %ecx
	movl	$256, %esi
	movslq	%eax, %r9
	call	cudaMemcpy2D@PLT
	movl	%r13d, %eax
	movl	$256, %r8d
	movl	$256, %ecx
	movq	-1840(%rbp), %rsi
	cltd
	idivl	-1740(%rbp)
	movq	(%rsi,%r12), %rdx
	movq	-1896(%rbp), %rsi
	movq	(%rsi,%r12), %rdi
	movl	$1, (%rsp)
	movl	$256, %esi
	movslq	%eax, %r9
	call	cudaMemcpy2D@PLT
	popq	%rax
	movq	-1824(%rbp), %rax
	movl	$1, %ecx
	popq	%rdx
	movl	$4000, %edx
	movq	(%rax,%r12), %rsi
	movq	-1776(%rbp), %rax
	movq	(%rax,%r12), %rdi
	.cfi_escape 0x2e,0
	call	cudaMemcpy@PLT
	incl	%r14d
	addq	$8, %r12
	cmpl	$3, %r14d
	jne	.L140
	movq	-1784(%rbp), %r12
	movl	$2, %r13d
.L144:
	movl	-1716(%rbp), %ecx
	movq	-1724(%rbp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-1712(%rbp), %rdi
	movl	-1704(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L141
	movq	(%r15,%r12), %rdi
	movl	-1740(%rbp), %ecx
	xorl	%r8d, %r8d
	movl	$64, %esi
	movl	-1768(%rbp), %edx
	call	_Z34__device_stub__Z10initializePfmiiiPfmiii
.L141:
	movl	-1716(%rbp), %ecx
	movq	-1724(%rbp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-1700(%rbp), %rdi
	movl	-1692(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L142
	movq	-1752(%rbp), %rax
	movl	-1740(%rbp), %ecx
	xorl	%r8d, %r8d
	movl	$1, %edx
	movl	$64, %esi
	movq	(%rax,%r12), %rdi
	call	_Z34__device_stub__Z10initializePfmiiiPfmiii
.L142:
	movl	-1716(%rbp), %ecx
	movq	-1724(%rbp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-1700(%rbp), %rdi
	movl	-1692(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L143
	movq	-1760(%rbp), %rax
	movl	-1740(%rbp), %ecx
	xorl	%r8d, %r8d
	movl	$1, %edx
	movl	$64, %esi
	movq	(%rax,%r12), %rdi
	call	_Z34__device_stub__Z10initializePfmiiiPfmiii
.L143:
	addq	$8, %r12
	decl	%r13d
	je	.L261
	movl	$1, %r13d
	jmp	.L144
.L261:
	movl	-1716(%rbp), %ecx
	movq	-1724(%rbp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-1700(%rbp), %rdi
	movl	-1692(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L145
	movq	-1808(%rbp), %rax
	movl	-1740(%rbp), %ecx
	xorl	%r8d, %r8d
	movl	$1, %edx
	movl	$64, %esi
	movq	(%rax,%rbx), %rdi
	call	_Z34__device_stub__Z10initializePfmiiiPfmiii
.L145:
	movl	-1716(%rbp), %ecx
	movq	-1724(%rbp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	-1700(%rbp), %rdi
	movl	-1692(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	movl	-1740(%rbp), %ecx
	testl	%eax, %eax
	jne	.L146
	movq	-1816(%rbp), %rax
	xorl	%r8d, %r8d
	movl	$1, %edx
	movl	$64, %esi
	movq	(%rax,%rbx), %rdi
	call	_Z34__device_stub__Z10initializePfmiiiPfmiii
.L146:
	incq	-1856(%rbp)
	addq	$8, %rbx
	addq	$16, -1784(%rbp)
	addq	$24, -1800(%rbp)
	addq	$16, -1864(%rbp)
	jmp	.L127
.L256:
	call	cudaDeviceSynchronize@PLT
	leaq	-1688(%rbp), %rdi
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	call	gettimeofday@PLT
	leaq	.LC61(%rip), %r12
.L148:
	cmpl	%ebx, -1740(%rbp)
	jle	.L262
	movl	%ebx, %edi
	call	cudaSetDevice@PLT
	leaq	-1672(%rbp), %rsi
	leaq	-1736(%rbp), %rdi
	call	cudaMemGetInfo@PLT
	movq	%r12, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movl	%ebx, %esi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	leaq	.LC62(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	-1672(%rbp), %rdx
	movq	%rax, %rdi
	subq	-1736(%rbp), %rdx
	js	.L149
	cvtsi2sdq	%rdx, %xmm0
	jmp	.L150
.L149:
	movq	%rdx, %rax
	andl	$1, %edx
	shrq	%rax
	orq	%rdx, %rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L150:
	mulsd	.LC63(%rip), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	leaq	.LC64(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC65(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movl	%ebx, %esi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	leaq	.LC62(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	-1736(%rbp), %rdx
	movq	%rax, %rdi
	testq	%rdx, %rdx
	js	.L151
	cvtsi2sdq	%rdx, %xmm0
	jmp	.L152
.L151:
	movq	%rdx, %rax
	andl	$1, %edx
	shrq	%rax
	orq	%rdx, %rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L152:
	mulsd	.LC63(%rip), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	leaq	.LC64(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	incl	%ebx
	jmp	.L148
.L262:
	movl	$1, -1800(%rbp)
	xorl	%ebx, %ebx
	movl	%ebx, -1872(%rbp)
	movl	%ebx, -1864(%rbp)
.L154:
	movslq	-1800(%rbp), %rax
	movslq	-1872(%rbp), %r12
	xorl	%ebx, %ebx
	salq	$3, %rax
	salq	$3, %r12
	movq	%rax, -1784(%rbp)
	movq	%rax, %r14
	movq	%r12, %r13
.L168:
	movl	%ebx, -1856(%rbp)
	cmpl	%ebx, -1740(%rbp)
	jle	.L263
	movl	-1856(%rbp), %edi
	call	cudaSetDevice@PLT
	movq	-1792(%rbp), %rax
	movl	-1716(%rbp), %ecx
	xorl	%r8d, %r8d
	movq	-1724(%rbp), %rdx
	movq	-1700(%rbp), %rdi
	movq	(%rax,%rbx,8), %r9
	movl	-1692(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L155
	movq	-1816(%rbp), %rax
	movq	(%r15,%r13), %rdx
	movl	$64, %r8d
	movss	.LC60(%rip), %xmm0
	movq	(%rax,%rbx,8), %rcx
	movq	-1760(%rbp), %rax
	movq	(%rax,%r13), %rsi
	movq	(%rax,%r14), %rdi
	pushq	%r11
	movl	-1768(%rbp), %eax
	movl	-1856(%rbp), %r9d
	pushq	%rax
	.cfi_escape 0x2e,0x10
	call	_Z40__device_stub__Z10update_topPfS_S_S_fmiiPfS_S_S_fmii
	popq	%r9
	popq	%r10
.L155:
	movq	-1792(%rbp), %rax
	movl	-1716(%rbp), %ecx
	xorl	%r8d, %r8d
	movq	-1724(%rbp), %rdx
	movq	-1700(%rbp), %rdi
	movq	(%rax,%rbx,8), %r9
	movl	-1692(%rbp), %esi
	.cfi_escape 0x2e,0
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L156
	movq	-1808(%rbp), %rax
	movq	(%r15,%r13), %rdx
	movss	.LC60(%rip), %xmm0
	movq	(%rax,%rbx,8), %rcx
	movq	-1752(%rbp), %rax
	movq	(%rax,%r13), %rsi
	movq	(%rax,%r14), %rdi
	pushq	%r8
	movl	$64, %r8d
	movl	-1768(%rbp), %eax
	movl	-1856(%rbp), %r9d
	pushq	%rax
	.cfi_escape 0x2e,0x10
	call	_Z40__device_stub__Z10update_botPfS_S_S_fmiiPfS_S_S_fmii
	popq	%rax
	popq	%rdx
.L156:
	incq	%rbx
	addq	$16, %r13
	addq	$16, %r14
	jmp	.L168
.L263:
	xorl	%ebx, %ebx
.L158:
	cmpl	%ebx, -1740(%rbp)
	jle	.L264
	movq	-1792(%rbp), %rax
	movq	(%rax,%rbx,8), %rdi
	.cfi_escape 0x2e,0
	call	cudaStreamSynchronize@PLT
	incq	%rbx
	jmp	.L158
.L264:
	movq	-1784(%rbp), %rax
	xorl	%ebx, %ebx
	leaq	(%r15,%rax), %r13
.L160:
	movl	%ebx, %r14d
	cmpl	%ebx, -1740(%rbp)
	jle	.L265
	movl	%r14d, %edi
	call	cudaSetDevice@PLT
	movq	-1928(%rbp), %rax
	movl	-1716(%rbp), %ecx
	xorl	%r8d, %r8d
	movq	-1724(%rbp), %rdx
	movq	-1712(%rbp), %rdi
	movq	(%rax,%rbx,8), %r9
	movl	-1704(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L161
	movq	-1760(%rbp), %rdx
	imulq	$24, %rbx, %rax
	movq	(%r15,%r12), %rsi
	movl	%r14d, %r9d
	movl	-1864(%rbp), %edi
	movss	.LC60(%rip), %xmm0
	movl	$64, %r8d
	movq	(%rdx,%r12), %rcx
	movq	-1752(%rbp), %rdx
	movq	(%rdx,%r12), %rdx
	pushq	%rdi
	movq	-1896(%rbp), %rdi
	addq	%rax, %rdi
	pushq	%rdi
	movq	-1848(%rbp), %rdi
	addq	%rdi, %rax
	movq	0(%r13), %rdi
	pushq	%rax
	movl	-1768(%rbp), %eax
	pushq	%rax
	.cfi_escape 0x2e,0x20
	call	_Z47__device_stub__Z10update_innPfS_S_S_fmiiPS_S0_iPfS_S_S_fmiiPS_S0_i
	addq	$32, %rsp
.L161:
	incq	%rbx
	addq	$16, %r13
	addq	$16, %r12
	jmp	.L160
.L265:
	movslq	-1800(%rbp), %r12
	xorl	%ebx, %ebx
.L163:
	movl	-1740(%rbp), %ecx
	movl	%ebx, %esi
	cmpl	%ebx, %ecx
	jle	.L266
	leal	1(%rbx), %eax
	movl	$311296, %r8d
	cltd
	idivl	%ecx
	movslq	%edx, %rax
	movq	-1752(%rbp), %rdx
	movq	%rax, %rcx
	addq	%rax, %rax
	addq	%r12, %rax
	movq	(%rdx,%rax,8), %rdx
	movq	-1816(%rbp), %rax
	movq	(%rax,%rbx,8), %rdi
	movq	-1792(%rbp), %rax
	movq	(%rax,%rbx,8), %r9
	.cfi_escape 0x2e,0
	call	cudaMemcpyPeerAsync@PLT
	incq	%rbx
	jmp	.L163
.L266:
	movslq	-1800(%rbp), %r12
	xorl	%ebx, %ebx
.L165:
	movl	-1740(%rbp), %edi
	movl	%ebx, %esi
	cmpl	%ebx, %edi
	jle	.L267
	leal	-1(%rbx), %ecx
	movl	$311296, %r8d
	movl	%ecx, %eax
	negl	%eax
	cmovs	%ecx, %eax
	cltd
	idivl	%edi
	movslq	%edx, %rax
	movq	-1760(%rbp), %rdx
	movq	%rax, %rcx
	addq	%rax, %rax
	addq	%r12, %rax
	movq	(%rdx,%rax,8), %rdx
	movq	-1808(%rbp), %rax
	movq	(%rax,%rbx,8), %rdi
	movq	-1792(%rbp), %rax
	movq	(%rax,%rbx,8), %r9
	call	cudaMemcpyPeerAsync@PLT
	incq	%rbx
	jmp	.L165
.L267:
	call	cudaDeviceSynchronize@PLT
	movl	-1872(%rbp), %ebx
	incl	-1864(%rbp)
	cmpl	$1000, -1864(%rbp)
	movl	-1800(%rbp), %eax
	movl	%ebx, -1800(%rbp)
	je	.L167
	movl	%eax, -1872(%rbp)
	jmp	.L154
.L167:
	call	cudaDeviceSynchronize@PLT
	leaq	-1672(%rbp), %rbx
	xorl	%esi, %esi
	movq	%rbx, %rdi
	call	gettimeofday@PLT
	leaq	-1736(%rbp), %rdi
	movq	%rbx, %rsi
	leaq	-1688(%rbp), %rdx
	call	_Z16timeval_subtractPdP7timevalS1_
	leaq	.LC66(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	-1736(%rbp), %xmm2
	movq	%rax, %rdi
	movaps	%xmm2, %xmm0
	movsd	%xmm2, -1768(%rbp)
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	leaq	.LC67(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movsd	.LC68(%rip), %xmm0
	divsd	-1768(%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	leaq	.LC69(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	xorl	%ebx, %ebx
	xorl	%r12d, %r12d
	xorl	%r13d, %r13d
.L169:
	movl	%r13d, -1856(%rbp)
	cmpl	%r13d, -1740(%rbp)
	jle	.L268
	movl	-1856(%rbp), %edi
	call	cudaSetDevice@PLT
	movl	$256, %r8d
	movl	$256, %ecx
	movl	$256, %esi
	movq	-1936(%rbp), %rax
	movq	(%rax,%r13,8), %rax
	movq	%rax, -1768(%rbp)
	movq	-1784(%rbp), %rax
	movq	(%r15,%rax), %rdx
	pushq	%r14
	movq	-1920(%rbp), %r9
	movq	-1768(%rbp), %rdi
	pushq	$2
	.cfi_escape 0x2e,0x10
	call	cudaMemcpy2D@PLT
	movq	-1944(%rbp), %rax
	movq	-1784(%rbp), %rsi
	movl	$256, %ecx
	movl	$1216, %r9d
	movl	$256, %r8d
	movq	(%rax,%r13,8), %rax
	movq	%rax, -1792(%rbp)
	movq	-1752(%rbp), %rax
	movq	-1792(%rbp), %rdi
	movq	(%rax,%rsi), %rdx
	movl	$2, (%rsp)
	movl	$256, %esi
	call	cudaMemcpy2D@PLT
	movq	-1952(%rbp), %rax
	movq	-1784(%rbp), %rsi
	movl	$256, %ecx
	movl	$1216, %r9d
	movl	$256, %r8d
	movq	(%rax,%r13,8), %rax
	movq	%rax, -1800(%rbp)
	movq	-1760(%rbp), %rax
	movq	-1800(%rbp), %rdi
	movq	(%rax,%rsi), %rdx
	movl	$2, (%rsp)
	movl	$256, %esi
	call	cudaMemcpy2D@PLT
	xorl	%r11d, %r11d
	popq	%r9
	popq	%r10
	movq	%r12, %r14
	movl	%r11d, -1864(%rbp)
.L170:
	movl	$512, %eax
	movq	-1848(%rbp), %rsi
	movq	-1832(%rbp), %rcx
	cltd
	idivl	-1740(%rbp)
	movq	(%rcx,%r14), %rdi
	movq	(%rsi,%r14), %rdx
	pushq	%r8
	pushq	$2
	movl	$256, %r8d
	movl	$256, %ecx
	movl	$256, %esi
	movslq	%eax, %r9
	call	cudaMemcpy2D@PLT
	movl	$512, %eax
	movl	$256, %r8d
	movl	$256, %ecx
	movq	-1840(%rbp), %rsi
	cltd
	idivl	-1740(%rbp)
	movq	-1848(%rbp), %rdx
	movq	(%rsi,%r14), %rdi
	movq	(%rdx,%r14), %rdx
	movl	$2, (%rsp)
	movl	$256, %esi
	movslq	%eax, %r9
	call	cudaMemcpy2D@PLT
	movq	-1776(%rbp), %rax
	popq	%rcx
	movl	$4000, %edx
	movl	$2, %ecx
	popq	%rsi
	movq	(%rax,%r14), %rsi
	movq	-1824(%rbp), %rax
	movq	(%rax,%r14), %rdi
	.cfi_escape 0x2e,0
	call	cudaMemcpy@PLT
	incl	-1864(%rbp)
	addq	$8, %r14
	cmpl	$3, -1864(%rbp)
	jne	.L170
	movl	-1856(%rbp), %eax
	leaq	-1592(%rbp), %r14
	movss	.LC60(%rip), %xmm0
	movq	-1800(%rbp), %rcx
	movq	-1792(%rbp), %rdx
	movq	%r14, %rdi
	pushq	%rax
	movl	-1740(%rbp), %eax
	movq	-1768(%rbp), %rsi
	pushq	%rax
	movq	-1840(%rbp), %rax
	leaq	(%rax,%r12), %r9
	movq	-1832(%rbp), %rax
	leaq	(%rax,%r12), %r8
	.cfi_escape 0x2e,0x10
	call	_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	popq	%rax
	movq	%r14, %rdi
	popq	%rdx
	.cfi_escape 0x2e,0
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	-1824(%rbp), %rax
	xorl	%edx, %edx
	leaq	(%rax,%r12), %rdi
.L171:
	movq	-1624(%rbp,%rdx), %rcx
	movq	(%rdi,%rdx), %rsi
	xorl	%eax, %eax
.L172:
	movss	(%rcx,%rax), %xmm0
	addss	(%rsi,%rax), %xmm0
	movss	%xmm0, (%rcx,%rax)
	addq	$4, %rax
	cmpq	$4000, %rax
	jne	.L172
	addq	$8, %rdx
	cmpq	$24, %rdx
	jne	.L171
	movq	(%r15,%rbx), %rdi
	call	cudaFree@PLT
	movq	-1752(%rbp), %rax
	movq	(%rax,%rbx), %rdi
	call	cudaFree@PLT
	movq	-1760(%rbp), %rax
	movq	(%rax,%rbx), %rdi
	call	cudaFree@PLT
	movq	8(%r15,%rbx), %rdi
	call	cudaFree@PLT
	movq	-1752(%rbp), %rax
	movq	8(%rax,%rbx), %rdi
	call	cudaFree@PLT
	movq	-1760(%rbp), %rax
	movq	8(%rax,%rbx), %rdi
	call	cudaFree@PLT
	leaq	(%r15,%rbx), %rdi
	call	cudaFree@PLT
	movq	-1752(%rbp), %rax
	leaq	(%rax,%rbx), %rdi
	call	cudaFree@PLT
	movq	-1760(%rbp), %rax
	leaq	(%rax,%rbx), %rdi
	call	cudaFree@PLT
	movq	-1808(%rbp), %rax
	movq	(%rax,%r13,8), %rdi
	call	cudaFree@PLT
	movq	-1816(%rbp), %rax
	movq	(%rax,%r13,8), %rdi
	call	cudaFree@PLT
	movq	-1776(%rbp), %rax
	movq	(%rax,%r12), %rdi
	call	cudaFree@PLT
	movq	-1776(%rbp), %rax
	movq	8(%rax,%r12), %rdi
	call	cudaFree@PLT
	movq	-1776(%rbp), %rax
	movq	16(%rax,%r12), %rdi
	call	cudaFree@PLT
	movq	-1776(%rbp), %rax
	leaq	(%rax,%r12), %rdi
	call	cudaFree@PLT
.LEHE11:
	addq	$16, -1784(%rbp)
	incq	%r13
	addq	$24, %r12
	addq	$16, %rbx
	jmp	.L169
.L268:
	leaq	-1656(%rbp), %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	leaq	-568(%rbp), %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	leaq	-1080(%rbp), %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	leaq	-1592(%rbp), %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L182
	jmp	.L253
.L191:
	endbr64
	jmp	.L255
.L193:
	endbr64
	jmp	.L255
.L194:
	endbr64
.L255:
	movq	%rax, %rbx
.L178:
	movq	-1752(%rbp), %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	jmp	.L176
.L192:
	endbr64
	movq	%rax, %rbx
.L176:
	leaq	-1656(%rbp), %rdi
	call	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
	leaq	-568(%rbp), %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	jmp	.L179
.L190:
	endbr64
	movq	%rax, %rbx
.L179:
	leaq	-1080(%rbp), %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	jmp	.L180
.L189:
	endbr64
	movq	%rax, %rbx
.L180:
	leaq	-1592(%rbp), %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	jne	.L253
	movq	%rbx, %rdi
.LEHB12:
	call	_Unwind_Resume@PLT
.LEHE12:
.L253:
	call	__stack_chk_fail@PLT
.L182:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3792:
	.section	.gcc_except_table,"a",@progbits
.LLSDA3792:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE3792-.LLSDACSB3792
.LLSDACSB3792:
	.uleb128 .LEHB2-.LFB3792
	.uleb128 .LEHE2-.LEHB2
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB3-.LFB3792
	.uleb128 .LEHE3-.LEHB3
	.uleb128 .L189-.LFB3792
	.uleb128 0
	.uleb128 .LEHB4-.LFB3792
	.uleb128 .LEHE4-.LEHB4
	.uleb128 .L190-.LFB3792
	.uleb128 0
	.uleb128 .LEHB5-.LFB3792
	.uleb128 .LEHE5-.LEHB5
	.uleb128 .L192-.LFB3792
	.uleb128 0
	.uleb128 .LEHB6-.LFB3792
	.uleb128 .LEHE6-.LEHB6
	.uleb128 .L191-.LFB3792
	.uleb128 0
	.uleb128 .LEHB7-.LFB3792
	.uleb128 .LEHE7-.LEHB7
	.uleb128 .L192-.LFB3792
	.uleb128 0
	.uleb128 .LEHB8-.LFB3792
	.uleb128 .LEHE8-.LEHB8
	.uleb128 .L193-.LFB3792
	.uleb128 0
	.uleb128 .LEHB9-.LFB3792
	.uleb128 .LEHE9-.LEHB9
	.uleb128 .L192-.LFB3792
	.uleb128 0
	.uleb128 .LEHB10-.LFB3792
	.uleb128 .LEHE10-.LEHB10
	.uleb128 .L194-.LFB3792
	.uleb128 0
	.uleb128 .LEHB11-.LFB3792
	.uleb128 .LEHE11-.LEHB11
	.uleb128 .L192-.LFB3792
	.uleb128 0
	.uleb128 .LEHB12-.LFB3792
	.uleb128 .LEHE12-.LEHB12
	.uleb128 0
	.uleb128 0
.LLSDACSE3792:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1093567616
	.align 8
.LC14:
	.long	0
	.long	1077379072
	.align 8
.LC15:
	.long	0
	.long	1077952512
	.align 8
.LC18:
	.long	0
	.long	1074790400
	.align 8
.LC20:
	.long	0
	.long	1081341952
	.align 8
.LC21:
	.long	0
	.long	1082128384
	.align 8
.LC22:
	.long	0
	.long	1077903360
	.align 8
.LC24:
	.long	0
	.long	1077936128
	.align 8
.LC26:
	.long	0
	.long	1077149696
	.align 8
.LC28:
	.long	1073741824
	.long	1068792545
	.align 8
.LC39:
	.long	-1610612736
	.long	1069128089
	.align 8
.LC42:
	.long	0
	.long	1071644672
	.align 8
.LC44:
	.long	0
	.long	1076330496
	.align 8
.LC45:
	.long	0
	.long	-1076887552
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC59:
	.long	1069086873
	.align 4
.LC60:
	.long	1071039453
	.section	.rodata.cst8
	.align 8
.LC63:
	.long	-400107883
	.long	1041313291
	.align 8
.LC68:
	.long	-536870912
	.long	1077961293
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <iostream>
#include <ostream>
#include <fstream>
#include <sys/time.h>
#include <time.h>

using namespace std;

#define CASENAME "test_new"

#define BLOCKSIZEX 64
#define BLOCKSIZEY 1
#define BLOCKSIZEZ 1
#define BLOCKSIZELRX 48
#define BLOCKSIZELRY 1
#define BLOCKSIZELRZ 1
#define XDIM 64
#define YDIM 64
#define ZDIM 8
#define TMAX  1000
#define STARTF 0

#define OBSTR1 4.f
#define OBSTX1 23.5f
#define OBSTY1 23.5f
#define OBSTZ1 32.5f

#define OBSTR2 32.f
#define OBSTX2 319.5f
#define OBSTY2 511.5f
#define OBSTZ2 31.5f

#define LRFACTOR 0.5f
#define LRLEVEL 2
#define LRX0 11.75f	//minimum x coord of LR
#define XLRDIM 48	//number of nodes in x
#define LRY0 11.75f
#define YLRDIM 64
#define LRZ0 -0.25f
#define ZLRDIM 8

#define RE 20.f//2000.f//100.f;
#define UMAX 0.08f
#define SmagLES 0 //YES,NO
#define MODEL "MRT" //BGK,MRT,STREAM
#define REFINEMENT 0 //1,0
#define CS 0.1f

#define VELAV 0
#define START_VELAV   400000
#define START_VELFLUC 700000

inline __device__ int ImageFcn(float x, float y, float z){
    int value = 0;
//	if(((x-OBSTX1)*(x-OBSTX1)+(y-OBSTY1)*(y-OBSTY1))<OBSTR1*OBSTR1)
//		value = 10;
//	else if(((x-OBSTX2)*(x-OBSTX2)+(y-OBSTY2)*(y-OBSTY2))<OBSTR2*OBSTR2)
//		value = 10;
    
    if(abs(x-OBSTX1) < OBSTR1 && abs(y-OBSTY1) < OBSTR1)
        value = 10;

    return value;
}

inline __device__ int ImageFcn(int x, int y, int z){
    int value = 0;
//Cylinder
//	if(((x-OBSTX1)*(x-OBSTX1)+(y-OBSTY1)*(y-OBSTY1))<OBSTR1*OBSTR1)
//		value = 10;
//	else if(((x-OBSTX2)*(x-OBSTX2)+(y-OBSTY2)*(y-OBSTY2))<OBSTR2*OBSTR2)
//		value = 10;
    if(abs(x-OBSTX1) < OBSTR1 && abs(y-OBSTY1) < OBSTR1)
        value = 10;
//Lid Driven Cavity
//	if(y == 0 || y == YDIM-1 || z == 0 || z == ZDIM-1)
//		value = 1;
//	else if(x == XDIM-2 || y == 1 || y == YDIM-2 || z == 1 || z == ZDIM-2)
//		return 1;
//	else if(x == 0)
//		return 1;
    
//	if(abs(x-OBSTX1) < OBSTR1 && abs(y-OBSTY1) < OBSTR1)
//        value = 10;
//    if(z == 1)
//		value = 1;
//    if(z == ZDIM-2)
//		value = 1;
	else if(y == 0)
		value = 200;//22;
	else if(y == YDIM-1)
		value = 100;
	else if(x == 0)
		value = 26;
	else if(x == XDIM-1)
		value = 25;
	return value;
}

inline __device__ float PoisProf (float x){
	float radius = (YDIM-1-1)*0.5f;
	float result = -1.0f*(((1.0f-(x-0.5f)/radius))*((1.0f-(x-0.5f)/radius))-1.0f);
	return (result);
}

int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
  struct timeval result0;

  /* Perform the carry for the later subtraction by updating y. */
  if (x->tv_usec < y->tv_usec) {
    int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
    y->tv_usec -= 1000000 * nsec;
    y->tv_sec += nsec;
  }
  if (x->tv_usec - y->tv_usec > 1000000) {
    int nsec = (y->tv_usec - x->tv_usec) / 1000000;
    y->tv_usec += 1000000 * nsec;
    y->tv_sec -= nsec;
  }

  /* Compute the time remaining to wait.
     tv_usec is certainly positive. */
  result0.tv_sec = x->tv_sec - y->tv_sec;
  result0.tv_usec = x->tv_usec - y->tv_usec;
  *result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;

  /* Return 1 if result is negative. */
  return x->tv_sec < y->tv_sec;
}

__device__ int dmin(int a, int b)
{
	if (a<b) return a;
	else return b-1;
}
__device__ int dmax(int a)
{
	if (a>-1) return a;
	else return 0;
}
__device__ int dmin_p(int a, int b)
{
	if (a<b) return a;
	else return 0;
}
__device__ int dmax_p(int a, int b)
{
	if (a>-1) return a;
	else return b-1;
}

inline __device__ float trilinear_interp (float v000, float v001, float v010, float v011,
                                          float v100, float v101, float v110, float v111, float x, float y, float z){
    return v000*(1.f-x)*(1.f-y)*(1.f-z)+
           v001*(    x)*(1.f-y)*(1.f-z)+
           v010*(1.f-x)*(    y)*(1.f-z)+
           v011*(    x)*(    y)*(1.f-z)+
           v100*(1.f-x)*(1.f-y)*(    z)+
           v101*(    x)*(1.f-y)*(    z)+
           v110*(1.f-x)*(    y)*(    z)+
           v111*(    x)*(    y)*(    z);
}

inline __device__ int f_mem(int f_num, int x, int y, int z, size_t pitch, int zInner)
{
	int index = (x+y*pitch+z*YDIM*pitch)+f_num*pitch*YDIM*(zInner);
	index = dmax(index);
	index = dmin(index,19*pitch*YDIM*(zInner));
	return index;
}

inline __device__ int f_memLR(int f_num, int x, int y, int z, size_t pitch, int zInner)
{
	int index = (x+y*pitch+z*YLRDIM*pitch)+f_num*pitch*YLRDIM*(zInner);
	index = dmax(index);
	index = dmin(index,19*pitch*YLRDIM*(zInner));
	return index;
}

inline __device__ int buff_mem(int f_num, int x, int y, size_t pitch)
{
	int index = (x+y*pitch)+f_num*pitch*YDIM;
	index = dmax(index);
	index = dmin(index,19*pitch*YDIM);
	return index;
}

inline __device__ int buff_memLR(int f_num, int x, int y, size_t pitch)
{
	int index = (x+y*pitch)+f_num*pitch*YLRDIM;
	index = dmax(index);
	index = dmin(index,19*pitch*YLRDIM);
	return index;
}

inline __device__ void mrt_meq(float* meq, float rho, float u, float v, float w)
{
    meq[ 0] = rho;
    meq[ 1] = -11.f*rho+19.f*(u*u+v*v+w*w);
    meq[ 2] = 7.53968254f*(u*u+v*v+w*w);;
    meq[ 3] = u;
	meq[ 4] = -0.666666667f*u;
    meq[ 5] = v;
	meq[ 6] = -0.666666667f*v;
    meq[ 7] = w;
	meq[ 8] = -0.666666667f*w;
	meq[ 9] = 2.f*u*u-(v*v+w*w);
	meq[11] = v*v-w*w;
}

inline __device__ void InvertMoments(float* f, float* m)
{
float u = m[3];
float v = m[5];
float w = m[7];
f[0 ]=(0.052631579f*m[0]                           +- 0.012531328f*(m[1])+ 0.047619048f*(m[2]));
f[1 ]=(0.052631579f*m[0]+  0.1f*u                  +-0.0045948204f*(m[1])+-0.015873016f*(m[2])+  -0.1f*(m[4])                 + 0.055555556f*((m[9])-m[10]));
f[2 ]=(0.052631579f*m[0]         +  0.1f*v         +-0.0045948204f*(m[1])+-0.015873016f*(m[2])             +   -0.1f*(m[6])   +-0.027777778f*((m[9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[3 ]=(0.052631579f*m[0]+ -0.1f*u                  +-0.0045948204f*(m[1])+-0.015873016f*(m[2])+   0.1f*(m[4])                 + 0.055555556f*((m[9])-m[10]));                                                      
f[4 ]=(0.052631579f*m[0]         + -0.1f*v         +-0.0045948204f*(m[1])+-0.015873016f*(m[2])             +    0.1f*(m[6])   +-0.027777778f*((m[9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[5 ]=(0.052631579f*m[0]+  0.1f*u+  0.1f*v         + 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+ 0.025f*(m[4]+m[6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]-m[17])+ (0.027777778f*(m[9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[6 ]=(0.052631579f*m[0]+ -0.1f*u+  0.1f*v         + 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+-0.025f*(m[4]-m[6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]-m[17])+ (0.027777778f*(m[9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[7 ]=(0.052631579f*m[0]+ -0.1f*u+ -0.1f*v         + 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+-0.025f*(m[4]+m[6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]+m[17])+ (0.027777778f*(m[9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[8 ]=(0.052631579f*m[0]+  0.1f*u+ -0.1f*v         + 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+ 0.025f*(m[4]-m[6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]+m[17])+ (0.027777778f*(m[9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[9 ]=(0.052631579f*m[0]                  +  0.1f*w+-0.0045948204f*(m[1])+-0.015873016f*(m[2])                +   -0.1f*(m[8])+-0.027777778f*((m[9])-m[10])+-0.083333333f*((m[11])-m[12]));                                       
f[10]=(0.052631579f*m[0]+  0.1f*u         +  0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+ 0.025f*(m[4]+m[8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]+m[18])+ (0.027777778f*(m[9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[11]=(0.052631579f*m[0]         +  0.1f*v+  0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])             +  0.025f*(m[6]+m[8])+0.125f*( m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[9]) +( 0.25f*(m[14]))));
f[12]=(0.052631579f*m[0]+ -0.1f*u         +  0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+-0.025f*(m[4]-m[8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]+m[18])+ (0.027777778f*(m[9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[13]=(0.052631579f*m[0]         + -0.1f*v+  0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])             + -0.025f*(m[6]-m[8])+0.125f*(-m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[9]) +(-0.25f*(m[14]))));
f[14]=(0.052631579f*m[0]                  + -0.1f*w+-0.0045948204f*(m[1])+-0.015873016f*(m[2])                +    0.1f*(m[8])+-0.027777778f*((m[9])-m[10])+-0.083333333f*((m[11])-m[12]));                                      
f[15]=(0.052631579f*m[0]+  0.1f*u         + -0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+ 0.025f*(m[4]-m[8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]-m[18])+ (0.027777778f*(m[9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[16]=(0.052631579f*m[0]         +  0.1f*v+ -0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])             +  0.025f*(m[6]-m[8])+0.125f*( m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[9]) +(-0.25f*(m[14]))));
f[17]=(0.052631579f*m[0]+ -0.1f*u         + -0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])+-0.025f*(m[4]+m[8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]-m[18])+ (0.027777778f*(m[9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[18]=(0.052631579f*m[0]         + -0.1f*v+ -0.1f*w+ 0.0033416876f*(m[1])+ 0.003968254f*(m[2])             + -0.025f*(m[6]+m[8])+0.125f*(-m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[9]) +( 0.25f*(m[14]))));


}

inline __device__ void mrt_collide(float* f, float omega)
{
    float m[19];
	float u,v,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
	w = f[ 9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
	float rho = f[ 0]+f[ 1]+f[ 2]+f[ 3]+f[ 4]+f[ 5]+f[ 6]+f[ 7]+f[ 8]+f[ 9]+
	      f[10]+f[11]+f[12]+f[13]+f[14]+f[15]+f[16]+f[17]+f[18];

	m[ 1]  = 19.f*(-f[ 0]+ f[ 5]+f[ 6]+f[ 7]+f[ 8]+f[10]+f[11]+f[12]+f[13]+f[15]+f[16]+f[17]+f[18]   -(u*u+v*v+w*w));//+8.f*(f[ 5]+f[ 6]+f[ 7]+f[ 8]+f[10]+f[11]+f[12]+f[13]+f[15]+f[16]+f[17]+f[18]);
	m[ 2]  =  12.f*f[ 0]+ -4.f*f[ 1]+ -4.f*f[ 2]+ -4.f*f[ 3]+ -4.f*f[ 4]+      f[ 5]+      f[ 6]+      f[ 7]+      f[ 8]+ -4.f*f[ 9]+    f[10]+        f[11]+      f[12]+      f[13]+ -4.f*f[14]+      f[15]+      f[16]+      f[17]+      f[18] +7.53968254f*(u*u+v*v+w*w);
	m[ 4]  = 1.666666667f*(-3.f*f[1]+3.f*f[ 3]+u);
	m[ 6]  = 1.666666667f*(-3.f*f[2]+3.f*f[ 4]+v);
	m[ 8]  = 1.666666667f*(-3.f*f[9]+3.f*f[14]+w);
	m[ 9]  = 2.f*f[ 1]+  -  f[ 2]+  2.f*f[ 3]+  -  f[ 4]+ f[ 5]+ f[ 6]+ f[ 7]+ f[ 8]+-    f[ 9]+ f[10]+ -2.f*f[11]+ f[12]+-2.f*f[13]+-    f[14]+ f[15]+ -2.f*f[16]+ f[17]+-2.f*f[18]  -(2.f*u*u-(v*v+w*w));
	m[10] = 0.f;
	m[11] =             f[ 2]         +     f[ 4]+ f[ 5]+ f[ 6]+ f[ 7]+ f[ 8]+-    f[ 9]+-f[10]          +-f[12]         +-    f[14]+-f[15]          +-f[17]         -(v*v-w*w);
	m[12] =        -2.f*f[ 2]          -2.f*f[ 4]+ f[ 5]+ f[ 6]+ f[ 7]+ f[ 8]+ 2.f*f[ 9]+-f[10]          +-f[12]         + 2.f*f[14]+-f[15]          +-f[17]         ;
	m[13] =                                  f[ 5]+-f[ 6]+ f[ 7]+-f[ 8]                                                                             -u*v;
	m[14] =                                                                    f[11]     +-    f[13]              + -    f[16]     +     f[18]  -v*w;
	m[15] =                                                          f[10]        + - f[12]                  +-f[15]          + f[17]           -u*w;  
	m[16] =                                  f[ 5]+-f[ 6]+-f[ 7]+ f[ 8]         -f[10]        +   f[12]                  +-f[15]          + f[17]         ;  
	m[17] =                                 -f[ 5]+-f[ 6]+ f[ 7]+ f[ 8]              +     f[11]     +-    f[13]              +      f[16]     +-    f[18];  
	m[18] =                                                          f[10]+-     f[11]+ f[12]+-    f[13]         +-f[15]+      f[16]+-f[17]+     f[18];

f[ 0] -=- 0.012531328f*(m[ 1])+ 0.047619048f*(m[ 2]);
f[ 1] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+  -0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])*omega-m[10]);
f[ 2] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +   -0.1f*(m[ 6])   +-0.027777778f*((m[ 9])*omega-m[10])+ 0.083333333f*((m[11])*omega-m[12]);
f[ 3] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+   0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])*omega-m[10]);                                                                                         
f[ 4] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +    0.1f*(m[ 6])   +-0.027777778f*((m[ 9])*omega-m[10])+ 0.083333333f*((m[11])*omega-m[12]);
f[ 5] -= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]-m[17])+ omega*(0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13])));
f[ 6] -= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]-m[17])+ omega*(0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13])));
f[ 7] -= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]+m[17])+ omega*(0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13])));
f[ 8] -= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]+m[17])+ omega*(0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13])));
f[ 9] -=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +   -0.1f*(m[ 8])+-0.027777778f*((m[ 9])*omega-m[10])+-0.083333333f*((m[11])*omega-m[12]);                                       
f[10]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]+m[18])+ omega*(0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15])));
f[11]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]+m[ 8])+0.125f*( m[17]-m[18])-0.027777778f*(m[10])+omega*(-0.055555556f*(m[ 9]) +( 0.25f*(m[14])));
f[12]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]+m[18])+ omega*(0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15])));
f[13]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]-m[ 8])+0.125f*(-m[17]-m[18])-0.027777778f*(m[10])+omega*(-0.055555556f*(m[ 9]) +(-0.25f*(m[14])));
f[14]-=-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +    0.1f*(m[ 8])+-0.027777778f*((m[ 9])*omega-m[10])+-0.083333333f*((m[11])*omega-m[12]);                                      
f[15]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]-m[18])+ omega*(0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15])));
f[16]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]-m[ 8])+0.125f*( m[17]+m[18])-0.027777778f*(m[10])+omega*(-0.055555556f*(m[ 9]) +(-0.25f*(m[14])));
f[17]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]-m[18])+ omega*(0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15])));
f[18]-= 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]+m[ 8])+0.125f*(-m[17]+m[18])-0.027777778f*(m[10])+omega*(-0.055555556f*(m[ 9]) +( 0.25f*(m[14])));

}

inline __device__ void North_Extrap(float* f, float rho)
{
    float m[19];
	rho = 1.0f;
	float u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	float v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
	float w = f[ 9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];


	m[ 1]  = -30.f*f[ 0]+-11.f*f[ 1]+-11.f*f[ 2]+-11.f*f[ 3]+-11.f*f[ 4]+  8.f*f[ 5]+  8.f*f[ 6]+  8.f*f[ 7]+  8.f*f[ 8]+-11.f*f[ 9]+  8.f*f[10]+  8.f*f[11]+  8.f*f[12]+  8.f*f[13]+-11.f*f[14]+  8.f*f[15]+  8.f*f[16]+  8.f*f[17]+  8.f*f[18];
	m[ 2]  =  12.f*f[ 0]+ -4.f*f[ 1]+ -4.f*f[ 2]+ -4.f*f[ 3]+ -4.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -4.f*f[ 9]+    f[10]+      f[11]+    f[12]+    f[13]+ -4.f*f[14]+    f[15]+    f[16]+    f[17]+    f[18];
	m[ 4]  =           -4.f*f[ 1]         +  4.f*f[ 3]         +    f[ 5]+ -  f[ 6]+ -  f[ 7]+    f[ 8]         +    f[10]          + -  f[12]                    +    f[15]          + -  f[17]          ;
	m[ 6]  =                    -4.f*f[ 2]         +  4.f*f[ 4]+    f[ 5]+    f[ 6]+ -  f[ 7]+ -  f[ 8]                   +    f[11]          + -  f[13]                    +    f[16]          + -  f[18];
	m[ 8]  =                                                                                 + -4.f*f[ 9]+    f[10]+    f[11]+    f[12]+    f[13]+  4.f*f[14]+ -  f[15]+ -  f[16]+ -  f[17]+ -  f[18];
	m[ 9]  =            2.f*f[ 1]+ -  f[ 2]+  2.f*f[ 3]+ -  f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -  f[ 9]+    f[10]+ -2.f*f[11]+    f[12]+ -2.f*f[13]+ -  f[14]+    f[15]+ -2.f*f[16]+    f[17]+ -2.f*f[18];
	m[10] =           -4.f*f[ 1]+  2.f*f[ 2]+ -4.f*f[ 3]+  2.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+  2.f*f[ 9]+    f[10]+ -2.f*f[11]+    f[12]+ -2.f*f[13]+  2.f*f[14]+    f[15]+ -2.f*f[16]+    f[17]+ -2.f*f[18];
	m[11] =                       f[ 2]         +    f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -  f[ 9]+ -  f[10]          + -  f[12]          + -  f[14]+ -  f[15]          + -  f[17]          ;
	m[12] =                    -2.f*f[ 2]           -2.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+  2.f*f[ 9]+ -  f[10]          + -  f[12]          +  2.f*f[14]+ -  f[15]          + -  f[17]          ;
	m[13] =                                                  f[ 5]+ -  f[ 6]+    f[ 7]+ -  f[ 8]                                                                                                   ;
	m[14] =                                                                                                         f[11]          + -  f[13]                    + -  f[16]          +    f[18];
	m[15] =                                                                                               f[10]          + -  f[12]                    + -  f[15]          +    f[17]          ;  
	m[16] =                                                  f[ 5]+ -  f[ 6]+ -  f[ 7]+    f[ 8]           -  f[10]          +    f[12]                    + -  f[15]          +    f[17]          ;  
	m[17] =                                               -  f[ 5]+ -  f[ 6]+    f[ 7]+    f[ 8]                   +    f[11]          + -  f[13]                    +    f[16]          + -  f[18];  
	m[18] =                                                                                               f[10]+ -  f[11]+    f[12]+ -  f[13]          + -  f[15]+    f[16]+ -  f[17]+    f[18];

f[ 0] =(0.052631579f*rho                           +- 0.012531328f*(m[ 1])+ 0.047619048f*(m[ 2]));
f[ 1] =(0.052631579f*rho+  0.1f*u                  +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+  -0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])-m[10]));
f[ 2] =(0.052631579f*rho         +  0.1f*v         +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +   -0.1f*(m[ 6])   +-0.027777778f*((m[ 9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[ 3] =(0.052631579f*rho+ -0.1f*u                  +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+   0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])-m[10]));        
f[ 4] =(0.052631579f*rho         + -0.1f*v         +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +    0.1f*(m[ 6])   +-0.027777778f*((m[ 9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[ 5] =(0.052631579f*rho+  0.1f*u+  0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]-m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[ 6] =(0.052631579f*rho+ -0.1f*u+  0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]-m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[ 7] =(0.052631579f*rho+ -0.1f*u+ -0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]+m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[ 8] =(0.052631579f*rho+  0.1f*u+ -0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]+m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[ 9] =(0.052631579f*rho                  +  0.1f*w+-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +   -0.1f*(m[ 8])+-0.027777778f*((m[ 9])-m[10])+-0.083333333f*((m[11])-m[12]));                                       
f[10]=(0.052631579f*rho+  0.1f*u         +  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]+m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[11]=(0.052631579f*rho         +  0.1f*v+  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]+m[ 8])+0.125f*( m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +( 0.25f*(m[14]))));
f[12]=(0.052631579f*rho+ -0.1f*u         +  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]+m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[13]=(0.052631579f*rho         + -0.1f*v+  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]-m[ 8])+0.125f*(-m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +(-0.25f*(m[14]))));
f[14]=(0.052631579f*rho                  + -0.1f*w+-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +    0.1f*(m[ 8])+-0.027777778f*((m[ 9])-m[10])+-0.083333333f*((m[11])-m[12]));                                      
f[15]=(0.052631579f*rho+  0.1f*u         + -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]-m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[16]=(0.052631579f*rho         +  0.1f*v+ -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]-m[ 8])+0.125f*( m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +(-0.25f*(m[14]))));
f[17]=(0.052631579f*rho+ -0.1f*u         + -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]-m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[18]=(0.052631579f*rho         + -0.1f*v+ -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]+m[ 8])+0.125f*(-m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +( 0.25f*(m[14]))));

}

inline __device__ void South_Extrap(float* f, float v)
{
    float m[19];
	float u = 0.f;//f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	float w = 0.f;//f[ 9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
    float rho = f[0]+f[1]+f[2]+f[3]+f[4]+f[5]+f[6]+f[7]+f[8]+f[9]+f[10]+f[11]+f[12]+f[13]+f[14]+f[15]+f[16]+f[17]+f[18];

	m[ 1]  = -30.f*f[ 0]+-11.f*f[ 1]+-11.f*f[ 2]+-11.f*f[ 3]+-11.f*f[ 4]+  8.f*f[ 5]+  8.f*f[ 6]+  8.f*f[ 7]+  8.f*f[ 8]+-11.f*f[ 9]+  8.f*f[10]+  8.f*f[11]+  8.f*f[12]+  8.f*f[13]+-11.f*f[14]+  8.f*f[15]+  8.f*f[16]+  8.f*f[17]+  8.f*f[18];
	m[ 2]  =  12.f*f[ 0]+ -4.f*f[ 1]+ -4.f*f[ 2]+ -4.f*f[ 3]+ -4.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -4.f*f[ 9]+    f[10]+      f[11]+    f[12]+    f[13]+ -4.f*f[14]+    f[15]+    f[16]+    f[17]+    f[18];
	m[ 4]  =           -4.f*f[ 1]         +  4.f*f[ 3]         +    f[ 5]+ -  f[ 6]+ -  f[ 7]+    f[ 8]         +    f[10]          + -  f[12]                    +    f[15]          + -  f[17]          ;
	m[ 6]  =                    -4.f*f[ 2]         +  4.f*f[ 4]+    f[ 5]+    f[ 6]+ -  f[ 7]+ -  f[ 8]                   +    f[11]          + -  f[13]                    +    f[16]          + -  f[18];
	m[ 8]  =                                                                                 + -4.f*f[ 9]+    f[10]+    f[11]+    f[12]+    f[13]+  4.f*f[14]+ -  f[15]+ -  f[16]+ -  f[17]+ -  f[18];
	m[ 9]  =            2.f*f[ 1]+ -  f[ 2]+  2.f*f[ 3]+ -  f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -  f[ 9]+    f[10]+ -2.f*f[11]+    f[12]+ -2.f*f[13]+ -  f[14]+    f[15]+ -2.f*f[16]+    f[17]+ -2.f*f[18];
	m[10] =           -4.f*f[ 1]+  2.f*f[ 2]+ -4.f*f[ 3]+  2.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+  2.f*f[ 9]+    f[10]+ -2.f*f[11]+    f[12]+ -2.f*f[13]+  2.f*f[14]+    f[15]+ -2.f*f[16]+    f[17]+ -2.f*f[18];
	m[11] =                       f[ 2]         +    f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+ -  f[ 9]+ -  f[10]          + -  f[12]          + -  f[14]+ -  f[15]          + -  f[17]          ;
	m[12] =                    -2.f*f[ 2]           -2.f*f[ 4]+    f[ 5]+    f[ 6]+    f[ 7]+    f[ 8]+  2.f*f[ 9]+ -  f[10]          + -  f[12]          +  2.f*f[14]+ -  f[15]          + -  f[17]          ;
	m[13] =                                                  f[ 5]+ -  f[ 6]+    f[ 7]+ -  f[ 8]                                                                                                   ;
	m[14] =                                                                                                         f[11]          + -  f[13]                    + -  f[16]          +    f[18];
	m[15] =                                                                                               f[10]          + -  f[12]                    + -  f[15]          +    f[17]          ;  
	m[16] =                                                  f[ 5]+ -  f[ 6]+ -  f[ 7]+    f[ 8]           -  f[10]          +    f[12]                    + -  f[15]          +    f[17]          ;  
	m[17] =                                               -  f[ 5]+ -  f[ 6]+    f[ 7]+    f[ 8]                   +    f[11]          + -  f[13]                    +    f[16]          + -  f[18];  
	m[18] =                                                                                               f[10]+ -  f[11]+    f[12]+ -  f[13]          + -  f[15]+    f[16]+ -  f[17]+    f[18];

f[ 0] =(0.052631579f*rho                           +- 0.012531328f*(m[ 1])+ 0.047619048f*(m[ 2]));
f[ 1] =(0.052631579f*rho+  0.1f*u                  +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+  -0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])-m[10]));
f[ 2] =(0.052631579f*rho         +  0.1f*v         +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +   -0.1f*(m[ 6])   +-0.027777778f*((m[ 9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[ 3] =(0.052631579f*rho+ -0.1f*u                  +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])+   0.1f*(m[ 4])                 + 0.055555556f*((m[ 9])-m[10]));        
f[ 4] =(0.052631579f*rho         + -0.1f*v         +-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])             +    0.1f*(m[ 6])   +-0.027777778f*((m[ 9])-m[10])+ 0.083333333f*((m[11])-m[12]));
f[ 5] =(0.052631579f*rho+  0.1f*u+  0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]-m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[ 6] =(0.052631579f*rho+ -0.1f*u+  0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]-m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[ 7] =(0.052631579f*rho+ -0.1f*u+ -0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*(-m[16]+m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+( 0.25f*(m[13]))));
f[ 8] =(0.052631579f*rho+  0.1f*u+ -0.1f*v         + 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 6])              +0.013888889f*(m[10])+0.041666667f*(m[12])+0.125f*( m[16]+m[17])+ (0.027777778f*(m[ 9]) +0.083333333f*(m[11])+(-0.25f*(m[13]))));
f[ 9] =(0.052631579f*rho                  +  0.1f*w+-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +   -0.1f*(m[ 8])+-0.027777778f*((m[ 9])-m[10])+-0.083333333f*((m[11])-m[12]));                                       
f[10]=(0.052631579f*rho+  0.1f*u         +  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]+m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[11]=(0.052631579f*rho         +  0.1f*v+  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]+m[ 8])+0.125f*( m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +( 0.25f*(m[14]))));
f[12]=(0.052631579f*rho+ -0.1f*u         +  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]+m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[13]=(0.052631579f*rho         + -0.1f*v+  0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]-m[ 8])+0.125f*(-m[17]-m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +(-0.25f*(m[14]))));
f[14]=(0.052631579f*rho                  + -0.1f*w+-0.0045948204f*(m[ 1])+-0.015873016f*(m[ 2])                +    0.1f*(m[ 8])+-0.027777778f*((m[ 9])-m[10])+-0.083333333f*((m[11])-m[12]));                                      
f[15]=(0.052631579f*rho+  0.1f*u         + -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+ 0.025f*(m[ 4]-m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*(-m[16]-m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+(-0.25f*(m[15]))));
f[16]=(0.052631579f*rho         +  0.1f*v+ -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             +  0.025f*(m[ 6]-m[ 8])+0.125f*( m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +(-0.25f*(m[14]))));
f[17]=(0.052631579f*rho+ -0.1f*u         + -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])+-0.025f*(m[ 4]+m[ 8])              +0.013888889f*(m[10])-0.041666667f*(m[12])+0.125f*( m[16]-m[18])+ (0.027777778f*(m[ 9]) -0.083333333f*(m[11])+( 0.25f*(m[15]))));
f[18]=(0.052631579f*rho         + -0.1f*v+ -0.1f*w+ 0.0033416876f*(m[ 1])+ 0.003968254f*(m[ 2])             + -0.025f*(m[ 6]+m[ 8])+0.125f*(-m[17]+m[18])-0.027777778f*(m[10])+(-0.055555556f*(m[ 9]) +( 0.25f*(m[14]))));

}

__device__ void xsymmetry_bot(float* f, int y, int z)
{
	if(y == 0 && z == 0){
		f[ 2] = f[ 4];
        f[13]=f[18];
        f[11]=f[18];
        f[16]=f[18];
		f[ 6] =f[ 7];
        f[ 9] =f[14];
        f[12]=f[17];
	}
	else if(y == 0 && z == ZDIM-1){
		f[ 4] = f[ 2];
        f[11]=f[13];
        f[18]=f[13];
        f[16]=f[13];
		f[ 6] =f[ 7];
        f[14]=f[ 9];
        f[17]=f[12];
	}
	else if(y == YDIM-1 && z == 0){
		f[ 4] = f[ 2];
        f[11]=f[16];
        f[18]=f[16];
        f[13]=f[16];
		f[ 7] =f[ 6];
        f[ 9] =f[14];
        f[12]=f[17];
	}
	else if(y == YDIM-1 && z == ZDIM-1){
		f[ 4] = f[ 2];
        f[16]=f[11];
        f[18]=f[11];
        f[13]=f[11];
		f[ 7] =f[ 6];
        f[14]=f[ 9];
        f[17]=f[12];
	}
    else{
	if(y == 0){
        f[ 2] = f[ 4];
        f[11]=f[13];
        f[16]=f[18];
        f[ 8] = f[ 5];
    }
	else if(y == YDIM-1){
         f[ 4]=f[ 2] ;
        f[13]=f[11];
        f[18]=f[16];
         f[ 5]=f[ 8] ;
    }
    }
	f[ 1] = f[ 3] ;
	f[ 5] = f[ 6] ;
	f[ 8] = f[ 7] ;
	f[10]= f[12];
	f[15]= f[17];
}

__device__ void xsymmetry_top(float* f, int y, int z)
{
	if(y == 0 && z == 0){
		f[ 2]  = f[ 4];
		f[13] = f[18];			
		f[11] = f[18];
		f[16] = f[18];
		f[ 5]  = f[ 8];
		f[ 9]  = f[14];
		f[10] = f[15];
	}
	else if(y == 0 && z == ZDIM-1){
		f[ 2]  = f[ 4];
		f[11] = f[13];
		f[18] = f[13];
		f[16] = f[13];
		f[ 5]  = f[ 8];
		f[14] = f[ 9];
		f[15] = f[10];
	}
	else if(y == YDIM-1 && z == 0){
		f[ 4]  = f[ 2];
		f[18] = f[16];
		f[11] = f[16];
		f[13] = f[16];	
		f[ 8]  = f[ 5];
		f[ 9]  = f[14];
		f[10] = f[15];
	}
	else if(y == YDIM-1 && z == ZDIM-1){
		f[ 4]  = f[ 2];
		f[13] = f[11];
		f[16] = f[11];
		f[18] = f[11];
		f[ 8]  = f[ 5];
		f[14] = f[ 9];
		f[15] = f[10];
	}

	else{
	if(y == 0){
		f[ 2] = f[ 4];
		f[11] = f[13];
		f[16] = f[18];
		f[ 5] = f[ 8];
	}
	else if(y == YDIM-1){
		f[ 4] = f[ 2];
		f[13] = f[11];
		f[18] = f[16];
		f[ 8] = f[ 5];
	}
	}
	f[ 3] = f[ 1] ;
	f[ 6] = f[ 5] ;
	f[ 7] = f[ 8] ;
	f[12]= f[10];
	f[17]= f[15];
}

inline __device__ void vel_av(float* f, float& uAv, float& vAv, int t)
{
	float u,v;//,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
    uAv = (uAv*(t-START_VELAV)+u)/((t-START_VELAV)+1);
    vAv = (vAv*(t-START_VELAV)+v)/((t-START_VELAV)+1);
}
inline __device__ void vel_avLR(float* f, float& uAv, float& vAv, float t)
{
	float u,v;//,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
    uAv = (uAv*(t-START_VELAV)+u*LRFACTOR)/((t-START_VELAV)+LRFACTOR);
    vAv = (vAv*(t-START_VELAV)+v*LRFACTOR)/((t-START_VELAV)+LRFACTOR);
}

inline __device__ void vel_fluc(float* f, float& uAv, 
                    float& vAv, float& ufluc, float& vfluc, int t)
{
	float u,v;//,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
    u = (u-uAv)*(u-uAv);
    v = (v-vAv)*(v-vAv);
    ufluc = (ufluc*(t-START_VELFLUC)+u)/((t-START_VELFLUC)+1);
    vfluc = (vfluc*(t-START_VELFLUC)+v)/((t-START_VELFLUC)+1);
}
inline __device__ void vel_flucLR(float* f, float& uAv, 
                    float& vAv, float& ufluc, float& vfluc, float t)
{
	float u,v;//,w;	
	u = f[ 1]-f[ 3]+f[ 5]-f[ 6]-f[ 7]+f[ 8]+f[10]-f[12]+f[15]-f[17];
	v = f[ 2]-f[ 4]+f[ 5]+f[ 6]-f[ 7]-f[ 8]+f[11]-f[13]+f[16]-f[18];
    u = (u-uAv)*(u-uAv);
    v = (v-vAv)*(v-vAv);
    ufluc = (ufluc*(t-START_VELFLUC)+u*LRFACTOR)/((t-START_VELFLUC)+LRFACTOR);
    vfluc = (vfluc*(t-START_VELFLUC)+v*LRFACTOR)/((t-START_VELFLUC)+LRFACTOR);
}



__global__ void initialize(float *fout, size_t pitch, int zInner, int GPU_N, int level)
{
	int x = threadIdx.x+blockIdx.x*blockDim.x;//coord in linear mem
	int y = threadIdx.y+blockIdx.y*blockDim.y;
	int z = threadIdx.z+blockIdx.z*blockDim.z;
    float xcoord = x;
    float ycoord = y;
    float zcoord = z+1+GPU_N*ZDIM;
    if(level > 0){
        xcoord = LRX0+x*LRFACTOR;
        ycoord = LRY0+y*LRFACTOR;
        zcoord = LRZ0+z*LRFACTOR;
    }
	int j = x+y*pitch+z*YDIM*pitch;//index on padded mem (pitch in elements)
    float f[19] = {0};
    float m[19] = {0};
	
	int im = ImageFcn(xcoord,ycoord,zcoord);
	float u,v,w,rho;
	rho = 1.f;
	u = 0.01f;
	v = UMAX;
	w = 0.0;

    if(im == 10 || im == 1){
    u = 0.0f;
    v = 0.0f;
    w = 0.0f;
    }
    
    mrt_meq(m,rho,u,v,w);
    InvertMoments(f,m);
    
    for(int i = 0; i<19; i++)
    fout[j+i *pitch*YDIM*zInner]=f[ i];
}

__global__ void update_top(float* hB, float* hA, float* fA, float* temp,
							float omega, size_t pitch, int GPU, int zInner)//pitch in elements
{
	int x = threadIdx.x+blockIdx.x*blockDim.x;//coord in linear mem
	int y = threadIdx.y+blockIdx.y*blockDim.y;
	int j = x+y*pitch;//index on padded mem (pitch in elements)
	int im = ImageFcn(x,y,(GPU+1)*(zInner+2)-1);
    float f[19];

	f[0 ]= hA  [j];
	f[1 ]= hA  [buff_mem(1 ,x-1,y  ,pitch)];
	f[3 ]= hA  [buff_mem(3 ,x+1,y  ,pitch)];
	f[2 ]= hA  [buff_mem(2 ,x  ,y-1,pitch)];
	f[5 ]= hA  [buff_mem(5 ,x-1,y-1,pitch)];
	f[6 ]= hA  [buff_mem(6 ,x+1,y-1,pitch)];
	f[4 ]= hA  [buff_mem(4 ,x  ,y+1,pitch)];
	f[7 ]= hA  [buff_mem(7 ,x+1,y+1,pitch)];
	f[8 ]= hA  [buff_mem(8 ,x-1,y+1,pitch)];
	f[9 ]= fA  [f_mem   (9 ,x  ,y  ,zInner-1,pitch, zInner)];
	f[10]= fA  [f_mem   (10,x-1,y  ,zInner-1,pitch, zInner)];
	f[11]= fA  [f_mem   (11,x  ,y-1,zInner-1,pitch, zInner)];
	f[12]= fA  [f_mem   (12,x+1,y  ,zInner-1,pitch, zInner)];
	f[13]= fA  [f_mem   (13,x  ,y+1,zInner-1,pitch, zInner)];
	f[14]= temp[buff_mem(14,x  ,y  ,pitch)];
	f[15]= temp[buff_mem(15,x-1,y  ,pitch)];
	f[16]= temp[buff_mem(16,x  ,y-1,pitch)];
	f[17]= temp[buff_mem(17,x+1,y  ,pitch)];
	f[18]= temp[buff_mem(18,x  ,y+1,pitch)];

	if(im == 1 || im ==10){//BB
		hB[buff_mem(0 ,x,y,pitch)] = f[0 ];
		hB[buff_mem(1 ,x,y,pitch)] = f[3 ];
		hB[buff_mem(2 ,x,y,pitch)] = f[4 ];
		hB[buff_mem(3 ,x,y,pitch)] = f[1 ];
		hB[buff_mem(4 ,x,y,pitch)] = f[2 ];
		hB[buff_mem(5 ,x,y,pitch)] = f[7 ];
		hB[buff_mem(6 ,x,y,pitch)] = f[8 ];
		hB[buff_mem(7 ,x,y,pitch)] = f[5 ];
		hB[buff_mem(8 ,x,y,pitch)] = f[6 ];
		hB[buff_mem(9 ,x,y,pitch)] = f[14];
		hB[buff_mem(10,x,y,pitch)] = f[17];
		hB[buff_mem(11,x,y,pitch)] = f[18];
		hB[buff_mem(12,x,y,pitch)] = f[15];
		hB[buff_mem(13,x,y,pitch)] = f[16];
		hB[buff_mem(14,x,y,pitch)] = f[9 ];
		hB[buff_mem(15,x,y,pitch)] = f[12];
		hB[buff_mem(16,x,y,pitch)] = f[13];
		hB[buff_mem(17,x,y,pitch)] = f[10];
		hB[buff_mem(18,x,y,pitch)] = f[11];
	}
	else{
        if(im == 100)//north outlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= hA[buff_mem(i ,x,y-1,pitch)];
			North_Extrap(f,1.0f);
        }
        if(im == 200)//south inlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= hA[buff_mem(i ,x,y+1,pitch)];
			South_Extrap(f,UMAX);
        }
        if(im == 25)
            xsymmetry_top(f,y,(GPU+1)*(zInner+2)-1);
        if(im == 26)
            xsymmetry_bot(f,y,(GPU+1)*(zInner+2)-1);

		mrt_collide(f,omega);

        for(int i = 0; i<19; i++)
		    hB[buff_mem(i ,x,y,pitch)] = f[i ];
	}

}

__global__ void update_bot(float* gB, float* gA, float* fA, float* temp,
							float omega, size_t pitch, int GPU, int zInner)//pitch in elements
{
	int x = threadIdx.x+blockIdx.x*blockDim.x;//coord in linear mem
	int y = threadIdx.y+blockIdx.y*blockDim.y;
	int j = x+y*pitch;//index on padded mem (pitch in elements)
	int im = ImageFcn(x,y,(GPU+1)*(zInner+2)-1);
    float f[19];

	f[0 ]= gA  [j];
	f[1 ]= gA  [buff_mem(1 ,x-1,y  ,pitch)];
	f[3 ]= gA  [buff_mem(3 ,x+1,y  ,pitch)];
	f[2 ]= gA  [buff_mem(2 ,x  ,y-1,pitch)];
	f[5 ]= gA  [buff_mem(5 ,x-1,y-1,pitch)];
	f[6 ]= gA  [buff_mem(6 ,x+1,y-1,pitch)];
	f[4 ]= gA  [buff_mem(4 ,x  ,y+1,pitch)];
	f[7 ]= gA  [buff_mem(7 ,x+1,y+1,pitch)];
	f[8 ]= gA  [buff_mem(8 ,x-1,y+1,pitch)];
	f[9 ]= temp[buff_mem(9 ,x  ,y  ,pitch)];
	f[10]= temp[buff_mem(10,x-1,y  ,pitch)];
	f[11]= temp[buff_mem(11,x  ,y-1,pitch)];
	f[12]= temp[buff_mem(12,x+1,y  ,pitch)];
	f[13]= temp[buff_mem(13,x  ,y+1,pitch)];
	f[14]= fA  [f_mem   (14,x  ,y  ,0,pitch, zInner)];
	f[15]= fA  [f_mem   (15,x-1,y  ,0,pitch, zInner)];
	f[16]= fA  [f_mem   (16,x  ,y-1,0,pitch, zInner)];
	f[17]= fA  [f_mem   (17,x+1,y  ,0,pitch, zInner)];
	f[18]= fA  [f_mem   (18,x  ,y+1,0,pitch, zInner)];

	if(im == 1 || im ==10){//BB
		gB[buff_mem(0 ,x,y,pitch)] = f[0 ];
		gB[buff_mem(1 ,x,y,pitch)] = f[3 ];
		gB[buff_mem(2 ,x,y,pitch)] = f[4 ];
		gB[buff_mem(3 ,x,y,pitch)] = f[1 ];
		gB[buff_mem(4 ,x,y,pitch)] = f[2 ];
		gB[buff_mem(5 ,x,y,pitch)] = f[7 ];
		gB[buff_mem(6 ,x,y,pitch)] = f[8 ];
		gB[buff_mem(7 ,x,y,pitch)] = f[5 ];
		gB[buff_mem(8 ,x,y,pitch)] = f[6 ];
		gB[buff_mem(9 ,x,y,pitch)] = f[14];
		gB[buff_mem(10,x,y,pitch)] = f[17];
		gB[buff_mem(11,x,y,pitch)] = f[18];
		gB[buff_mem(12,x,y,pitch)] = f[15];
		gB[buff_mem(13,x,y,pitch)] = f[16];
		gB[buff_mem(14,x,y,pitch)] = f[9 ];
		gB[buff_mem(15,x,y,pitch)] = f[12];
		gB[buff_mem(16,x,y,pitch)] = f[13];
		gB[buff_mem(17,x,y,pitch)] = f[10];
		gB[buff_mem(18,x,y,pitch)] = f[11];
	}
	else{
        if(im == 100)//north outlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= gA[buff_mem(i ,x,y-1,pitch)];
			North_Extrap(f,1.0f);
        }
        if(im == 200)//south inlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= gA[buff_mem(i ,x,y+1,pitch)];
			South_Extrap(f,UMAX);
        }
        if(im == 25)
            xsymmetry_top(f,y,GPU*(zInner+2));
        if(im == 26)
            xsymmetry_bot(f,y,GPU*(zInner+2));

		mrt_collide(f,omega);

        for(int i = 0; i<19; i++)
		    gB[buff_mem(i ,x,y,pitch)] = f[i ];
	}
}

__global__ void update_inn(float* fB, float* fA, float* g, float* h, float omega, size_t pitch, int GPU, int zInner, float **velAv, float ** velFluc, int t)
{
	int x = threadIdx.x+blockIdx.x*blockDim.x;//coord in linear mem
	int y = threadIdx.y+blockIdx.y*blockDim.y;
	int z = threadIdx.z+blockIdx.z*blockDim.z;
	int j = x+y*pitch+z*YDIM*pitch;//index on padded mem (pitch in elements)
	int im = ImageFcn(x,y,GPU*(zInner+2)+1+z);
	float f[19];

    f[ 0] = fA[j];
	f[ 1] = fA[f_mem   (1 ,x-1,y  ,z  ,pitch, zInner)];
	f[ 3] = fA[f_mem   (3 ,x+1,y  ,z  ,pitch, zInner)];
	f[ 2] = fA[f_mem   (2 ,x  ,y-1,z  ,pitch, zInner)];
	f[ 5] = fA[f_mem   (5 ,x-1,y-1,z  ,pitch, zInner)];
	f[ 6] = fA[f_mem   (6 ,x+1,y-1,z  ,pitch, zInner)];
	f[ 4] = fA[f_mem   (4 ,x  ,y+1,z  ,pitch, zInner)];
	f[ 7] = fA[f_mem   (7 ,x+1,y+1,z  ,pitch, zInner)];
	f[ 8] = fA[f_mem   (8 ,x-1,y+1,z  ,pitch, zInner)];

    if(z==zInner-1){//top nodes need info from h
	f[ 9] = fA[f_mem   (9 ,x  ,y  ,z-1,pitch, zInner)];
	f[10]= fA[f_mem   (10,x-1,y  ,z-1,pitch, zInner)];
	f[11]= fA[f_mem   (11,x  ,y-1,z-1,pitch, zInner)];
	f[12]= fA[f_mem   (12,x+1,y  ,z-1,pitch, zInner)];
	f[13]= fA[f_mem   (13,x  ,y+1,z-1,pitch, zInner)];
	f[14]= h [buff_mem(14,x  ,y  ,pitch)];
	f[15]= h [buff_mem(15,x-1,y  ,pitch)];
	f[16]= h [buff_mem(16,x  ,y-1,pitch)];
	f[17]= h [buff_mem(17,x+1,y  ,pitch)];
	f[18]= h [buff_mem(18,x  ,y+1,pitch)];
    }
    else if(z==0){//bottom nodes need info from g
	f[ 9] =g [buff_mem(9 ,x  ,y  ,pitch)];
	f[10]= g [buff_mem(10,x-1,y  ,pitch)];
	f[11]= g [buff_mem(11,x  ,y-1,pitch)];
	f[12]= g [buff_mem(12,x+1,y  ,pitch)];
	f[13]= g [buff_mem(13,x  ,y+1,pitch)];
	f[14]= fA[f_mem   (14,x  ,y  ,z+1,pitch, zInner)];
	f[15]= fA[f_mem   (15,x-1,y  ,z+1,pitch, zInner)];
	f[16]= fA[f_mem   (16,x  ,y-1,z+1,pitch, zInner)];
	f[17]= fA[f_mem   (17,x+1,y  ,z+1,pitch, zInner)];
	f[18]= fA[f_mem   (18,x  ,y+1,z+1,pitch, zInner)];
    }
    else{//normal nodes
	f[ 9] = fA[f_mem(9 ,x  ,y  ,z-1,pitch,zInner)];
	f[10]= fA[f_mem(10,x-1,y  ,z-1,pitch,zInner)];
	f[11]= fA[f_mem(11,x  ,y-1,z-1,pitch,zInner)];
	f[12]= fA[f_mem(12,x+1,y  ,z-1,pitch,zInner)];
	f[13]= fA[f_mem(13,x  ,y+1,z-1,pitch,zInner)];
	f[14]= fA[f_mem(14,x  ,y  ,z+1,pitch,zInner)];
	f[15]= fA[f_mem(15,x-1,y  ,z+1,pitch,zInner)];
	f[16]= fA[f_mem(16,x  ,y-1,z+1,pitch,zInner)];
	f[17]= fA[f_mem(17,x+1,y  ,z+1,pitch,zInner)];
	f[18]= fA[f_mem(18,x  ,y+1,z+1,pitch,zInner)];

    }//end normal nodes

	if(im == 1 || im ==10){//BB
		fB[f_mem(1 ,x,y,z,pitch,zInner)] = f[ 3] ;
		fB[f_mem(2 ,x,y,z,pitch,zInner)] = f[ 4] ;
		fB[f_mem(3 ,x,y,z,pitch,zInner)] = f[ 1] ;
		fB[f_mem(4 ,x,y,z,pitch,zInner)] = f[ 2] ;
		fB[f_mem(5 ,x,y,z,pitch,zInner)] = f[ 7] ;
		fB[f_mem(6 ,x,y,z,pitch,zInner)] = f[ 8] ;
		fB[f_mem(7 ,x,y,z,pitch,zInner)] = f[ 5] ;
		fB[f_mem(8 ,x,y,z,pitch,zInner)] = f[ 6] ;
		fB[f_mem(9 ,x,y,z,pitch,zInner)] = f[14];
		fB[f_mem(10,x,y,z,pitch,zInner)] = f[17];
		fB[f_mem(11,x,y,z,pitch,zInner)] = f[18];
		fB[f_mem(12,x,y,z,pitch,zInner)] = f[15];
		fB[f_mem(13,x,y,z,pitch,zInner)] = f[16];
		fB[f_mem(14,x,y,z,pitch,zInner)] = f[ 9] ;
		fB[f_mem(15,x,y,z,pitch,zInner)] = f[12];
		fB[f_mem(16,x,y,z,pitch,zInner)] = f[13];
		fB[f_mem(17,x,y,z,pitch,zInner)] = f[10];
		fB[f_mem(18,x,y,z,pitch,zInner)] = f[11];
	}
	else{
        if(im == 100)//north outlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= fA[f_mem(i ,x,y-1,z,pitch,zInner)];
			North_Extrap(f,1.0f);
        }
        if(im == 200)//south inlet
        {
            for(int i = 0; i<19; i++)
           	    f[i ]= fA[f_mem(i ,x,y+1,z,pitch,zInner)];
			South_Extrap(f,UMAX);
        }
        if(im == 25)
            xsymmetry_top(f,y,GPU*(zInner+2)+1+z);
        if(im == 26)
            xsymmetry_bot(f,y,GPU*(zInner+2)+1+z);

		mrt_collide(f,omega);

        if(VELAV == 1){
            if(t>=START_VELAV && t<START_VELFLUC){
                float u_Av = velAv[0][x+y*pitch+(z+1)*pitch*YDIM];
                float v_Av = velAv[1][x+y*pitch+(z+1)*pitch*YDIM];
        		vel_av(f,u_Av,v_Av,t);
                velAv[0][x+y*pitch+(z+1)*pitch*YDIM] = u_Av;
                velAv[1][x+y*pitch+(z+1)*pitch*YDIM] = v_Av;
            }
            else if(t>=START_VELFLUC){
                float u_Av = velAv[0][x+y*pitch+(z+1)*pitch*YDIM];
                float v_Av = velAv[1][x+y*pitch+(z+1)*pitch*YDIM];
                float u_fluc = velFluc[0][x+y*pitch+(z+1)*pitch*YDIM];
                float v_fluc = velFluc[1][x+y*pitch+(z+1)*pitch*YDIM];
        		vel_fluc(f,u_Av,v_Av,u_fluc,v_fluc,t);
                velFluc[0][x+y*pitch+(z+1)*pitch*YDIM] = u_fluc;
                velFluc[1][x+y*pitch+(z+1)*pitch*YDIM] = v_fluc;
            }
        }

        for(int i = 0; i<19; i++)
		    fB[f_mem(i ,x,y,z,pitch,zInner)] = f[ i] ;
	}
//        for(int i = 0; i<19; i++)
//		    fB[f_mem(i ,x,y,z,pitch,zInner)] = 1.f ;
}


void WriteResults(ostream &output, float *fin, float *gin, float *hin, float **velAv,  
                  float **velFluc, float omega, int GPU_N, int GPU)
{
    float f[19];
	output<<"VARIABLES = \"X\",\"Y\",\"Z\",\"u\",\"v\",\"w\",\"rho\",\"velAv[0]\",\"velAv[1]\",\"ufluc\",\"vfluc\"\n";
	output<<"ZONE F=POINT, I="<<XDIM<<", J="<<YDIM<<", K="<<ZDIM/GPU_N<<"\n";

    for(int j = 0; j<YDIM; j++){
    for(int i = 0; i<XDIM; i++){
        float rho = 0;
        for(int l = 0; l<19; l++){
            f[l] = gin[(i+j*XDIM)+l *XDIM*YDIM];
            rho += f[l];
        }
        float u = f[1]-f[3 ]+f[5 ]-f[6 ]-f[7 ]+f[8 ]+f[10]-f[12]+f[15]-f[17];
        float v = f[2]-f[4 ]+f[5 ]+f[6 ]-f[7 ]-f[8 ]+f[11]-f[13]+f[16]-f[18];
        float w = f[9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
        output<<i<<", "<<j<<", "<<(ZDIM/GPU_N*GPU)<<", "<<u<<","<<v<<","<<w<<","<<rho<<","
              <<velAv[0][i+j*XDIM]<<","<<velAv[1][i+j*XDIM]<<", "<<velFluc[0][i+j*XDIM]<<","<<velFluc[1][i+j*XDIM]<<endl;
    }}

    for(int k = 1; k<ZDIM/GPU_N-1; k++){
    for(int j = 0; j<YDIM; j++){
    for(int i = 0; i<XDIM; i++){
        float rho = 0;
        for(int l = 0; l<19; l++){
            f[l] = fin[(i+j*XDIM)+(k-1)*XDIM*YDIM+l*XDIM*YDIM*(ZDIM/GPU_N-2)];
            rho += f[l];
        }
        float u = f[1]-f[3 ]+f[5 ]-f[6 ]-f[7 ]+f[8 ]+f[10]-f[12]+f[15]-f[17];
        float v = f[2]-f[4 ]+f[5 ]+f[6 ]-f[7 ]-f[8 ]+f[11]-f[13]+f[16]-f[18];
        float w = f[9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
        int z = (ZDIM/GPU_N*GPU+k);
        output<<i<<", "<<j<<", "<<z<<", "<<u<<","<<v<<","<<w<<","<<rho<<","
              <<velAv[0][i+j*XDIM+k*XDIM*YDIM]<<","<<velAv[1][i+j*XDIM+k*XDIM*YDIM]<<", "
              <<velFluc[0][i+j*XDIM+k*XDIM*YDIM]<<","<<velFluc[1][i+j*XDIM+k*XDIM*YDIM]<<endl;
    }}}

    for(int j = 0; j<YDIM; j++){
    for(int i = 0; i<XDIM; i++){
        float rho = 0;
        for(int l = 0; l<19; l++){
            f[l] = hin[(i+j*XDIM)+l *XDIM*YDIM];
            rho += f[l];
        }
        float u = f[1]-f[3 ]+f[5 ]-f[6 ]-f[7 ]+f[8 ]+f[10]-f[12]+f[15]-f[17];
        float v = f[2]-f[4 ]+f[5 ]+f[6 ]-f[7 ]-f[8 ]+f[11]-f[13]+f[16]-f[18];
        float w = f[9]+f[10]+f[11]+f[12]+f[13]-f[14]-f[15]-f[16]-f[17]-f[18];
        output<<i<<", "<<j<<", "<<(ZDIM/GPU_N*(GPU+1)-1)<<", "<<u<<","<<v<<","<<w<<","<<rho<<","
              <<velAv[0][i+j*XDIM+(ZDIM-1)*XDIM*YDIM]<<","<<velAv[1][i+j*XDIM+(ZDIM/GPU_N-1)*XDIM*YDIM]<<", "
              <<velFluc[0][i+j*XDIM+(ZDIM-1)*XDIM*YDIM]<<","<<velFluc[1][i+j*XDIM+(ZDIM/GPU_N-1)*XDIM*YDIM]<<endl;
    }}
}



void WriteInputs(ostream &output, float omega, float omegaLR, int GPU_per_node)
{
    output<<"Base domain size \t"<<XDIM<<"x"<<YDIM<<"x"<<ZDIM<<endl;
	output<<"Base blocksize: \t"<<BLOCKSIZEX<<"x"<<BLOCKSIZEY<<"x"<<BLOCKSIZEZ<<endl;
	output<<"Obst1 location: \t("<<OBSTX1<<","<<OBSTY1<<","<<OBSTZ1<<")"<<endl;
	output<<"Obst1 radius: \t"<<OBSTR1<<endl;
	output<<"Obst2 location: \t("<<OBSTX2<<","<<OBSTY2<<","<<OBSTZ2<<")"<<endl;
	output<<"Obst2 radius: \t"<<OBSTR2<<endl;
	output<<"RE: \t"<<RE<<endl;
	output<<"UMAX: \t"<<UMAX<<endl;
    output<<"omega \t: "<<omega<<endl;
	output<<"TMAX: \t"<<TMAX<<endl;
	output<<"STARTF: \t"<<STARTF<<endl;
	output<<"START_VELAV: \t"<<START_VELAV<<endl;
	output<<"START_VELFLUC: \t"<<START_VELFLUC<<endl;
	output<<"REFINEMENT: \t"<<REFINEMENT<<endl;
	output<<"MODEL: \t"<<MODEL<<endl;
	output<<"Smagorinski LES: \t"<<SmagLES<<endl;
	output<<"CS: \t"<<CS<<endl;
    output<<"LR domain size \t"<<XLRDIM<<"x"<<YLRDIM<<"x"<<ZLRDIM<<endl;
    output<<"LR factor \t"<<LRFACTOR<<endl;
    output<<"LR location \t"<<LRX0<<"x"<<LRY0<<"x"<<LRZ0<<endl;
	output<<"LR blocksize: \t"<<BLOCKSIZELRX<<"x"<<BLOCKSIZELRY<<"x"<<BLOCKSIZELRZ<<endl;   
	output<<"omega in LR \t: "<<omegaLR<<endl;
	output<<"GPUs per node \t: "<<GPU_per_node<<endl;
}





int main(int argc, char *argv[])
{
    
	int GPU_N;
	hipGetDeviceCount(&GPU_N);
	cout<<"number of GPUs: "<<GPU_N<<endl;

	ofstream output;
	ofstream outputForce;
	ofstream outputInputs;
	string FileName = CASENAME;
	output.open ((FileName+".dat").c_str());
	outputForce.open ((FileName+".force").c_str());
	outputInputs.open ((FileName+".inputs").c_str());

	//size_t memsize, memsize2;
	size_t pitch = 2;
	while(pitch<XDIM)
		pitch=pitch*2;
	pitch *= sizeof(float);//pitch*sizeof(float);
	size_t pitch_e = pitch/sizeof(float);
	cout<<"Pitch (in elements): "<<pitch/sizeof(float)<<endl;

	float CharLength = OBSTR1*2.f;

	float omega = 1.0f/(3.0f*(UMAX*CharLength/RE)+0.5f);
	float omegaLR = 2.0f/(1.0f+2.0f*(2.0f/omega-1.0f));
	if(LRFACTOR == 0.25f){
	omegaLR = 2.0f/(1.0f+2.0f*(2.0f/omegaLR-1.0f));
	}
	float SF_cf = omega*(1.0f-omegaLR)/((1.0f-omega)*omegaLR/LRFACTOR);
	float SF_fc = 1.f/SF_cf;

    WriteInputs(outputInputs,omega,omegaLR,GPU_N);
    WriteInputs(cout,omega,omegaLR,GPU_N);

	if(abs(LRFACTOR-1.f/LRLEVEL)>0.001f && REFINEMENT == 1){
		cout<<"LRLEVEL and LRFACTOR don't match! Exiting..."<<endl;
		return 0;
	}

    int zInner = ZDIM/GPU_N-2; //excluding halo
    int ForceTime = max(0,TMAX-STARTF);

    dim3 threads(BLOCKSIZEX, BLOCKSIZEY, BLOCKSIZEZ);
	//2 halo layers per GPU (for 2 GPUs)
    dim3 grid  (((XDIM+BLOCKSIZEX-1)/BLOCKSIZEX),((YDIM+BLOCKSIZEY-1)/BLOCKSIZEY),(zInner)/BLOCKSIZEZ);
    dim3 g_grid(((XDIM+BLOCKSIZEX-1)/BLOCKSIZEX),((YDIM+BLOCKSIZEY-1)/BLOCKSIZEY),1);

    hipStream_t stream_halo[GPU_N];
    hipStream_t stream_inner[GPU_N];

    //data pointers as 3D array (GPUxCoord)
    float   *f_h[GPU_N],   *g_h[GPU_N],   *h_h[GPU_N];
    float *f_d[GPU_N][2], *g_d[GPU_N][2], *h_d[GPU_N][2];
    float *g_temp[GPU_N], *h_temp[GPU_N];
    float *F_h[GPU_N][3];
    float *F_d[GPU_N][3];
    float *F_total[3];
    float *velAv_h[GPU_N][3],*velFluc_h[GPU_N][3];
    float *velAv_d[GPU_N][3],*velFluc_d[GPU_N][3];

    for(int i = 0; i<3; i++)
	F_total[i] = (float *)malloc(ForceTime*sizeof(float));
	
    for(int i=0;i<3;i++)
    for(int j=0;j<(ForceTime);j++)
        F_total[i][j] = 0;

    //Malloc and Initialize for each GPU
    for(int n = 0; n<GPU_N; n++){
    	f_h    [n] = (float *)malloc(XDIM*YDIM*zInner*19*sizeof(float));
    	g_h    [n] = (float *)malloc(XDIM*YDIM*       19*sizeof(float));
    	h_h    [n] = (float *)malloc(XDIM*YDIM*       19*sizeof(float));
        for(int i = 0; i<3; i++){
    	F_h      [n][i] = (float *)malloc(ForceTime*sizeof(float));
    	velAv_h  [n][i] = (float *)malloc(XDIM*YDIM*ZDIM/GPU_N*sizeof(float));
    	velFluc_h[n][i] = (float *)malloc(XDIM*YDIM*ZDIM/GPU_N*sizeof(float));
        }
        hipSetDevice(n);
    	hipStreamCreate(&stream_halo[n]);
    	hipStreamCreate(&stream_inner[n]);
        for(int m = 0; m<GPU_N; m++)
            if(m != n) hipDeviceEnablePeerAccess(m,0);

        for(int i = 0; i<2; i++){
       	hipMalloc((void **) &f_d[n][i], pitch_e*YDIM*zInner*19*sizeof(float));
    	hipMalloc((void **) &g_d[n][i], pitch_e*YDIM*       19*sizeof(float));
    	hipMalloc((void **) &h_d[n][i], pitch_e*YDIM*       19*sizeof(float));
        }
    	hipMalloc((void **) & g_temp[n], pitch_e*YDIM*       19*sizeof(float));
    	hipMalloc((void **) & h_temp[n], pitch_e*YDIM*       19*sizeof(float));
        for(int i = 0; i<3; i++){
    	hipMalloc((void **) & F_d      [n][i], (ForceTime)*sizeof(float));
	    hipMalloc((void **) & velAv_d  [n][i], pitch_e*YDIM*ZDIM/GPU_N*sizeof(float));
	    hipMalloc((void **) & velFluc_d[n][i], pitch_e*YDIM*ZDIM/GPU_N*sizeof(float));
        }

    	//initialize host f_inner
    	for (int i = 0; i < XDIM*YDIM*zInner*19; i++)
    		f_h[n][i] = 0;
    	//initialize host g,h
    	for (int i = 0; i < XDIM*YDIM*19; i++){
    		g_h[n][i] = 0;
    		h_h[n][i] = 0;
    	}
        for(int i=0;i<3;i++){
            for(int j=0;j<(ForceTime);j++)
                F_h[n][i][j] = 0;
        	for (int j = 0; j < XDIM*YDIM*ZDIM/GPU_N; j++){
            velAv_h  [n][i][j] = 0;
            velFluc_h[n][i][j] = 0;
            }
    	}
        for(int i = 0; i<2; i++){
    	hipMemcpy2D(f_d[n][i],pitch,f_h[n],XDIM*sizeof(float),XDIM*sizeof(float),YDIM*zInner*19,hipMemcpyHostToDevice);
    	hipMemcpy2D(g_d[n][i],pitch,g_h[n],XDIM*sizeof(float),XDIM*sizeof(float),YDIM       *19,hipMemcpyHostToDevice);
    	hipMemcpy2D(h_d[n][i],pitch,h_h[n],XDIM*sizeof(float),XDIM*sizeof(float),YDIM       *19,hipMemcpyHostToDevice);
        }

        for(int i = 0; i<3; i++){
    	hipMemcpy2D(velAv_d  [n][i],pitch,velAv_h  [n][i],XDIM*sizeof(float),XDIM*sizeof(float),YDIM*ZDIM/GPU_N,hipMemcpyHostToDevice);
    	hipMemcpy2D(velFluc_d[n][i],pitch,velFluc_h[n][i],XDIM*sizeof(float),XDIM*sizeof(float),YDIM*ZDIM/GPU_N,hipMemcpyHostToDevice);
	    hipMemcpy(F_d[n][i],F_h[n][i],sizeof(float)*(ForceTime),hipMemcpyHostToDevice);
        }

        //initialization kernels
        for(int i = 0; i<2; i++){
        initialize<<<  grid,threads>>>(f_d[n][i],pitch_e,zInner,GPU_N,0);
        initialize<<<g_grid,threads>>>(g_d[n][i],pitch_e,     1,GPU_N,0);
        initialize<<<g_grid,threads>>>(h_d[n][i],pitch_e,     1,GPU_N,0);
        }
        initialize<<<g_grid,threads>>>(g_temp[n],pitch_e,     1,GPU_N,0);
        initialize<<<g_grid,threads>>>(h_temp[n],pitch_e,     1,GPU_N,0);

    }//end Malloc and Initialize
    

    //setup LR


    int A = 0;
    int B = 1;
    
	struct timeval tdr0,tdr1;
	double restime;
	hipDeviceSynchronize();
	gettimeofday (&tdr0,NULL);

    for(int n = 0; n<GPU_N; n++){
	hipSetDevice(n);
    size_t mem_avail, mem_total;
    hipMemGetInfo(&mem_avail,&mem_total);
    cout<<"Device memory used for dev"<<n<<" : "<<(mem_total-mem_avail)*pow(10,-9)<<" GB\n";
    cout<<"Device memory available for dev"<<n<<" : "<<(mem_avail)*pow(10,-9)<<" GB\n";
    }
    
    //time loop
    for(int t = 0; t<TMAX; t++)
    {
        for(int n = 0; n<GPU_N; n++)
        {
      		hipSetDevice(n);
    		update_top<<<g_grid, threads, 0, stream_halo [n]>>>(h_d[n][B],h_d[n][A],f_d[n][A],h_temp[n],omega,pitch_e,n,zInner);
    		update_bot<<<g_grid, threads, 0, stream_halo [n]>>>(g_d[n][B],g_d[n][A],f_d[n][A],g_temp[n],omega,pitch_e,n,zInner);
        }
        for(int n = 0; n<GPU_N; n++)
		hipStreamSynchronize(stream_halo[n]);
        for(int n = 0; n<GPU_N; n++){
		    hipSetDevice(n);
		    update_inn<<<grid,threads,0,stream_inner[n]>>>(f_d[n][B],f_d[n][A],g_d[n][A], h_d[n][A],omega,pitch_e,n,zInner,velAv_d[n],velFluc_d[n],t);
        }

        for(int n = 0; n<GPU_N; n++)
            hipMemcpyPeerAsync(&h_temp[n][0],n,&g_d[   (n+1)%GPU_N][B][0],   (n+1)%GPU_N,pitch_e*YDIM*sizeof(float)*19,stream_halo[n]);
        for(int n = 0; n<GPU_N; n++)
            hipMemcpyPeerAsync(&g_temp[n][0],n,&h_d[abs(n-1)%GPU_N][B][0],abs(n-1)%GPU_N,pitch_e*YDIM*sizeof(float)*19,stream_halo[n]);

	    hipDeviceSynchronize();
        swap(A,B);




    }



	hipDeviceSynchronize();
	gettimeofday (&tdr1,NULL);
	timeval_subtract (&restime, &tdr1, &tdr0);
	int Nodes;
	Nodes = XDIM*YDIM*ZDIM;
    if (REFINEMENT == 1)
        Nodes += XLRDIM*YLRDIM*ZLRDIM*LRLEVEL;
	cout<<"Time taken for main kernel: "<<restime<<" ("
			<<double(Nodes*double(TMAX/1000000.f))/restime<<"MLUPS)\n";

    //D2H Memcpy and write results
    for(int n = 0; n<GPU_N; n++){
        hipSetDevice(n);
    	hipMemcpy2D(f_h[n],XDIM*sizeof(float),f_d[n][A],pitch,XDIM*sizeof(float),YDIM*zInner*19,hipMemcpyDeviceToHost);
    	hipMemcpy2D(g_h[n],XDIM*sizeof(float),g_d[n][A],pitch,XDIM*sizeof(float),YDIM       *19,hipMemcpyDeviceToHost);
    	hipMemcpy2D(h_h[n],XDIM*sizeof(float),h_d[n][A],pitch,XDIM*sizeof(float),YDIM       *19,hipMemcpyDeviceToHost);
        for(int i = 0; i<3; i++){
	    hipMemcpy2D(  velAv_h[n][i],XDIM*sizeof(float),velAv_d[n][i],pitch,XDIM*sizeof(float),YDIM*ZDIM/GPU_N,hipMemcpyDeviceToHost);
	    hipMemcpy2D(velFluc_h[n][i],XDIM*sizeof(float),velAv_d[n][i],pitch,XDIM*sizeof(float),YDIM*ZDIM/GPU_N,hipMemcpyDeviceToHost);
	    hipMemcpy(F_h[n][i],F_d[n][i],sizeof(float)*ForceTime,hipMemcpyDeviceToHost);
        }
        WriteResults(output,f_h[n],g_h[n],h_h[n],velAv_h[n],velFluc_h[n],omega,GPU_N,n);
        output<<endl;

        for(int i=0;i<3;i++)
        for(int j=0;j<ForceTime;j++)
            F_total[i][j] += F_h[n][i][j];
        
        for(int i = 0; i<2; i++){
            hipFree(f_d[n][i]);
            hipFree(g_d[n][i]);
            hipFree(h_d[n][i]);
        }
        hipFree(f_d[n]);
        hipFree(g_d[n]);
        hipFree(h_d[n]);
        hipFree(g_temp[n]);
        hipFree(h_temp[n]);
        for(int i=0;i<3;i++)
            hipFree(F_d[n][i]);
        hipFree(F_d[n]);




    }//end Memcpy and write results





    return 0;
}

	.text
	.file	"bak_LRMultiGPU4.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z16timeval_subtractPdP7timevalS1_
.LCPI0_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z16timeval_subtractPdP7timevalS1_
	.type	_Z16timeval_subtractPdP7timevalS1_,@function
_Z16timeval_subtractPdP7timevalS1_:     # @_Z16timeval_subtractPdP7timevalS1_
	.cfi_startproc
# %bb.0:
	movq	%rdx, %rcx
	movq	8(%rsi), %rdx
	movq	(%rcx), %r8
	movq	8(%rcx), %r9
	movq	%r9, %rax
	movabsq	$4835703278458516699, %r10      # imm = 0x431BDE82D7B634DB
	subq	%rdx, %rax
	jle	.LBB0_2
# %bb.1:
	imulq	%r10
	movq	%rdx, %rax
	shrq	$18, %rax
	shrq	$63, %rdx
	addl	%edx, %eax
	incl	%eax
	imull	$1000000, %eax, %edx            # imm = 0xF4240
	movslq	%edx, %rdx
	subq	%rdx, %r9
	movq	%r9, 8(%rcx)
	cltq
	addq	%rax, %r8
	movq	%r8, (%rcx)
	movq	8(%rsi), %rdx
.LBB0_2:
	movq	%rdx, %rax
	subq	%r9, %rax
	cmpq	$1000001, %rax                  # imm = 0xF4241
	jl	.LBB0_4
# %bb.3:
	movq	%r9, %rax
	subq	%rdx, %rax
	imulq	%r10
	movq	%rdx, %rax
	shrq	$63, %rax
	sarq	$18, %rdx
	addq	%rax, %rdx
	movabsq	$4294967296000000, %r10         # imm = 0xF424000000000
	imulq	%rdx, %r10
	sarq	$32, %r10
	addq	%r9, %r10
	movq	%r10, 8(%rcx)
	movslq	%edx, %rax
	subq	%rax, %r8
	movq	%r8, (%rcx)
	movq	8(%rsi), %rax
	subq	%r10, %rax
.LBB0_4:
	movq	(%rsi), %rcx
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI0_0(%rip), %xmm0
	xorl	%eax, %eax
	subq	%r8, %rcx
	cvtsi2sd	%rcx, %xmm1
	addsd	%xmm0, %xmm1
	movsd	%xmm1, (%rdi)
	setl	%al
	retq
.Lfunc_end0:
	.size	_Z16timeval_subtractPdP7timevalS1_, .Lfunc_end0-_Z16timeval_subtractPdP7timevalS1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__initializePfmiii # -- Begin function _Z25__device_stub__initializePfmiii
	.type	_Z25__device_stub__initializePfmiii,@function
_Z25__device_stub__initializePfmiii:    # @_Z25__device_stub__initializePfmiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10initializePfmiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__initializePfmiii, .Lfunc_end1-_Z25__device_stub__initializePfmiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__update_topPfS_S_S_fmii # -- Begin function _Z25__device_stub__update_topPfS_S_S_fmii
	.type	_Z25__device_stub__update_topPfS_S_S_fmii,@function
_Z25__device_stub__update_topPfS_S_S_fmii: # @_Z25__device_stub__update_topPfS_S_S_fmii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	24(%rsp), %r10
	movq	%r8, (%r10)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10update_topPfS_S_S_fmii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__update_topPfS_S_S_fmii, .Lfunc_end2-_Z25__device_stub__update_topPfS_S_S_fmii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__update_botPfS_S_S_fmii # -- Begin function _Z25__device_stub__update_botPfS_S_S_fmii
	.type	_Z25__device_stub__update_botPfS_S_S_fmii,@function
_Z25__device_stub__update_botPfS_S_S_fmii: # @_Z25__device_stub__update_botPfS_S_S_fmii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	24(%rsp), %r10
	movq	%r8, (%r10)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10update_botPfS_S_S_fmii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z25__device_stub__update_botPfS_S_S_fmii, .Lfunc_end3-_Z25__device_stub__update_botPfS_S_S_fmii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i # -- Begin function _Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i
	.type	_Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i,@function
_Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i: # @_Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	24(%rsp), %r10
	movq	%r8, (%r10)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10update_innPfS_S_S_fmiiPS_S0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i, .Lfunc_end4-_Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii # -- Begin function _Z12WriteResultsRSoPfS0_S0_PS0_S1_fii
	.type	_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii,@function
_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii:  # @_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 160(%rsp)                  # 8-byte Spill
	movq	%r8, 152(%rsp)                  # 8-byte Spill
	movq	%rcx, 136(%rsp)                 # 8-byte Spill
	movq	%rdx, %r14
	movq	%rsi, %rbp
	movq	%rdi, %rbx
	movl	$.L.str, %esi
	movl	$80, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$.L.str.1, %esi
	movl	$16, %edx
	movq	%rbx, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, 144(%rsp)                 # 8-byte Spill
	movq	%rbx, %rdi
	movl	$64, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.2, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	$64, %esi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movl	$.L.str.3, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%r15d, %r15d
	movl	$8, %eax
	xorl	%edx, %edx
	idivl	272(%rsp)
	movl	%eax, %ebx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_ZNSolsEi
	movl	$.L.str.4, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, 112(%rsp)                 # 8-byte Spill
                                        # kill: def $ebx killed $ebx killed $rbx def $rbx
	imull	280(%rsp), %ebx
	movq	%rbx, 176(%rsp)                 # 8-byte Spill
.LBB5_1:                                # %.preheader137
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_2 Depth 2
                                        #       Child Loop BB5_3 Depth 3
	movq	%r15, 16(%rsp)                  # 8-byte Spill
	shlq	$6, %r15
	movq	%r15, 24(%rsp)                  # 8-byte Spill
	movq	%r14, 120(%rsp)                 # 8-byte Spill
	xorl	%r12d, %r12d
.LBB5_2:                                # %.preheader136
                                        #   Parent Loop BB5_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB5_3 Depth 3
	xorps	%xmm1, %xmm1
	movq	%r14, %rax
	xorl	%ecx, %ecx
.LBB5_3:                                #   Parent Loop BB5_1 Depth=1
                                        #     Parent Loop BB5_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rax), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 32(%rsp,%rcx,4)
	addss	%xmm0, %xmm1
	incq	%rcx
	addq	$16384, %rax                    # imm = 0x4000
	cmpq	$19, %rcx
	jne	.LBB5_3
# %bb.4:                                #   in Loop: Header=BB5_2 Depth=2
	movss	36(%rsp), %xmm9                 # xmm9 = mem[0],zero,zero,zero
	movss	40(%rsp), %xmm7                 # xmm7 = mem[0],zero,zero,zero
	subss	44(%rsp), %xmm9
	movss	52(%rsp), %xmm3                 # xmm3 = mem[0],zero,zero,zero
	addss	%xmm3, %xmm9
	movss	56(%rsp), %xmm4                 # xmm4 = mem[0],zero,zero,zero
	subss	%xmm4, %xmm9
	movss	60(%rsp), %xmm5                 # xmm5 = mem[0],zero,zero,zero
	subss	%xmm5, %xmm9
	movss	64(%rsp), %xmm6                 # xmm6 = mem[0],zero,zero,zero
	addss	%xmm6, %xmm9
	movss	72(%rsp), %xmm8                 # xmm8 = mem[0],zero,zero,zero
	addss	%xmm8, %xmm9
	movss	80(%rsp), %xmm2                 # xmm2 = mem[0],zero,zero,zero
	subss	%xmm2, %xmm9
	movss	%xmm1, 12(%rsp)                 # 4-byte Spill
	movss	92(%rsp), %xmm1                 # xmm1 = mem[0],zero,zero,zero
	addss	%xmm1, %xmm9
	movss	100(%rsp), %xmm0                # xmm0 = mem[0],zero,zero,zero
	subss	48(%rsp), %xmm7
	subss	%xmm0, %xmm9
	movss	%xmm9, 8(%rsp)                  # 4-byte Spill
	addss	%xmm3, %xmm7
	addss	%xmm4, %xmm7
	subss	%xmm5, %xmm7
	subss	%xmm6, %xmm7
	movss	76(%rsp), %xmm3                 # xmm3 = mem[0],zero,zero,zero
	addss	%xmm3, %xmm7
	movss	84(%rsp), %xmm4                 # xmm4 = mem[0],zero,zero,zero
	subss	%xmm4, %xmm7
	movss	96(%rsp), %xmm5                 # xmm5 = mem[0],zero,zero,zero
	addss	%xmm5, %xmm7
	movss	104(%rsp), %xmm6                # xmm6 = mem[0],zero,zero,zero
	subss	%xmm6, %xmm7
	movss	%xmm7, 4(%rsp)                  # 4-byte Spill
	addss	68(%rsp), %xmm8
	addss	%xmm3, %xmm8
	addss	%xmm2, %xmm8
	addss	%xmm4, %xmm8
	subss	88(%rsp), %xmm8
	subss	%xmm1, %xmm8
	subss	%xmm5, %xmm8
	subss	%xmm0, %xmm8
	subss	%xmm6, %xmm8
	movss	%xmm8, (%rsp)                   # 4-byte Spill
	movq	144(%rsp), %rdi                 # 8-byte Reload
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r13
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r13, %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_ZNSolsEi
	movq	%rax, %r13
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r13, %rdi
	movq	176(%rsp), %rsi                 # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_ZNSolsEi
	movq	%rax, %r13
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0                  # 4-byte Folded Reload
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rsp), %xmm0                   # 4-byte Folded Reload
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	12(%rsp), %xmm0                 # 4-byte Folded Reload
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	152(%rsp), %r15                 # 8-byte Reload
	movq	(%r15), %rax
	movq	24(%rsp), %rcx                  # 8-byte Reload
	leaq	(%r12,%rcx), %rbx
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%rbx,4), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%r15), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%rbx,4), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	160(%rsp), %r15                 # 8-byte Reload
	movq	(%r15), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%rbx,4), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%r15), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%rbx,4), %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r13
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r13, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r12
	addq	$4, %r14
	cmpq	$64, %r12
	jne	.LBB5_2
# %bb.5:                                #   in Loop: Header=BB5_1 Depth=1
	movq	16(%rsp), %r15                  # 8-byte Reload
	incq	%r15
	movq	120(%rsp), %r14                 # 8-byte Reload
	addq	$256, %r14                      # imm = 0x100
	cmpq	$64, %r15
	jne	.LBB5_1
# %bb.6:                                # %.preheader135
	movq	112(%rsp), %rax                 # 8-byte Reload
	leal	-1(%rax), %ecx
	movl	%ecx, 132(%rsp)                 # 4-byte Spill
	cmpl	$3, %eax
	jl	.LBB5_15
# %bb.7:                                # %.preheader134.lr.ph
	movl	132(%rsp), %eax                 # 4-byte Reload
	movq	%rax, 184(%rsp)                 # 8-byte Spill
	movq	112(%rsp), %rax                 # 8-byte Reload
	movl	%eax, %r14d
	shll	$12, %r14d
	addl	$-8192, %r14d                   # imm = 0xE000
	movl	$1, %ecx
	xorl	%edx, %edx
.LBB5_8:                                # %.preheader134
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_9 Depth 2
                                        #       Child Loop BB5_10 Depth 3
                                        #         Child Loop BB5_11 Depth 4
	movq	%rcx, %rax
	shlq	$12, %rax
	movq	%rax, 208(%rsp)                 # 8-byte Spill
	movq	176(%rsp), %rax                 # 8-byte Reload
	movq	%rcx, 200(%rsp)                 # 8-byte Spill
	addl	%ecx, %eax
	movl	%eax, 172(%rsp)                 # 4-byte Spill
	movq	%rdx, 192(%rsp)                 # 8-byte Spill
	movl	%edx, %eax
	xorl	%ecx, %ecx
.LBB5_9:                                # %.preheader133
                                        #   Parent Loop BB5_8 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB5_10 Depth 3
                                        #         Child Loop BB5_11 Depth 4
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
                                        # kill: def $ecx killed $ecx killed $rcx def $rcx
	shll	$6, %ecx
	addl	208(%rsp), %ecx                 # 4-byte Folded Reload
	andl	$-64, %ecx
	movq	%rcx, 120(%rsp)                 # 8-byte Spill
	movl	%eax, 168(%rsp)                 # 4-byte Spill
	xorl	%r12d, %r12d
.LBB5_10:                               # %.preheader132
                                        #   Parent Loop BB5_8 Depth=1
                                        #     Parent Loop BB5_9 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB5_11 Depth 4
	xorps	%xmm1, %xmm1
	movl	%eax, 12(%rsp)                  # 4-byte Spill
                                        # kill: def $eax killed $eax def $rax
	xorl	%ecx, %ecx
.LBB5_11:                               #   Parent Loop BB5_8 Depth=1
                                        #     Parent Loop BB5_9 Depth=2
                                        #       Parent Loop BB5_10 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	cltq
	movss	(%rbp,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 32(%rsp,%rcx,4)
	addss	%xmm0, %xmm1
	incq	%rcx
	addl	%r14d, %eax
	cmpq	$19, %rcx
	jne	.LBB5_11
# %bb.12:                               #   in Loop: Header=BB5_10 Depth=3
	movss	36(%rsp), %xmm9                 # xmm9 = mem[0],zero,zero,zero
	movss	40(%rsp), %xmm7                 # xmm7 = mem[0],zero,zero,zero
	subss	44(%rsp), %xmm9
	movss	52(%rsp), %xmm3                 # xmm3 = mem[0],zero,zero,zero
	addss	%xmm3, %xmm9
	movss	56(%rsp), %xmm4                 # xmm4 = mem[0],zero,zero,zero
	subss	%xmm4, %xmm9
	movss	60(%rsp), %xmm5                 # xmm5 = mem[0],zero,zero,zero
	subss	%xmm5, %xmm9
	movss	64(%rsp), %xmm6                 # xmm6 = mem[0],zero,zero,zero
	addss	%xmm6, %xmm9
	movss	72(%rsp), %xmm8                 # xmm8 = mem[0],zero,zero,zero
	addss	%xmm8, %xmm9
	movss	80(%rsp), %xmm2                 # xmm2 = mem[0],zero,zero,zero
	subss	%xmm2, %xmm9
	movss	%xmm1, 8(%rsp)                  # 4-byte Spill
	movss	92(%rsp), %xmm1                 # xmm1 = mem[0],zero,zero,zero
	addss	%xmm1, %xmm9
	movss	100(%rsp), %xmm0                # xmm0 = mem[0],zero,zero,zero
	subss	48(%rsp), %xmm7
	subss	%xmm0, %xmm9
	movss	%xmm9, 4(%rsp)                  # 4-byte Spill
	addss	%xmm3, %xmm7
	addss	%xmm4, %xmm7
	subss	%xmm5, %xmm7
	subss	%xmm6, %xmm7
	movss	76(%rsp), %xmm3                 # xmm3 = mem[0],zero,zero,zero
	addss	%xmm3, %xmm7
	movss	84(%rsp), %xmm4                 # xmm4 = mem[0],zero,zero,zero
	subss	%xmm4, %xmm7
	movss	96(%rsp), %xmm5                 # xmm5 = mem[0],zero,zero,zero
	addss	%xmm5, %xmm7
	movss	104(%rsp), %xmm6                # xmm6 = mem[0],zero,zero,zero
	subss	%xmm6, %xmm7
	movss	%xmm7, (%rsp)                   # 4-byte Spill
	addss	68(%rsp), %xmm8
	addss	%xmm3, %xmm8
	addss	%xmm2, %xmm8
	addss	%xmm4, %xmm8
	subss	88(%rsp), %xmm8
	subss	%xmm1, %xmm8
	subss	%xmm5, %xmm8
	subss	%xmm0, %xmm8
	subss	%xmm6, %xmm8
	movss	%xmm8, 16(%rsp)                 # 4-byte Spill
	movq	144(%rsp), %rdi                 # 8-byte Reload
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	movl	172(%rsp), %esi                 # 4-byte Reload
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0                  # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rsp), %xmm0                   # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	16(%rsp), %xmm0                 # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	152(%rsp), %r15                 # 8-byte Reload
	movq	(%r15), %rax
	movq	120(%rsp), %rcx                 # 8-byte Reload
	leaq	(%r12,%rcx), %r13
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r13,4), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%r15), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r13,4), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	160(%rsp), %r15                 # 8-byte Reload
	movq	(%r15), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r13,4), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%r15), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r13,4), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r12
	movl	12(%rsp), %eax                  # 4-byte Reload
	incl	%eax
	cmpq	$64, %r12
	jne	.LBB5_10
# %bb.13:                               #   in Loop: Header=BB5_9 Depth=2
	movq	24(%rsp), %rcx                  # 8-byte Reload
	incq	%rcx
	movl	168(%rsp), %eax                 # 4-byte Reload
	addl	$64, %eax
	cmpq	$64, %rcx
	jne	.LBB5_9
# %bb.14:                               #   in Loop: Header=BB5_8 Depth=1
	movq	200(%rsp), %rcx                 # 8-byte Reload
	incq	%rcx
	movq	192(%rsp), %rdx                 # 8-byte Reload
	addl	$4096, %edx                     # imm = 0x1000
	cmpq	184(%rsp), %rcx                 # 8-byte Folded Reload
	jne	.LBB5_8
.LBB5_15:                               # %.preheader131
	movl	280(%rsp), %ecx
	incl	%ecx
	movq	112(%rsp), %rax                 # 8-byte Reload
	imull	%ecx, %eax
	decl	%eax
	movq	%rax, 112(%rsp)                 # 8-byte Spill
	movl	132(%rsp), %eax                 # 4-byte Reload
	shll	$12, %eax
	cltq
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	xorl	%eax, %eax
	movq	136(%rsp), %rbp                 # 8-byte Reload
.LBB5_16:                               # %.preheader130
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_17 Depth 2
                                        #       Child Loop BB5_18 Depth 3
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	shlq	$6, %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	%rbp, 136(%rsp)                 # 8-byte Spill
	xorl	%r12d, %r12d
.LBB5_17:                               # %.preheader
                                        #   Parent Loop BB5_16 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB5_18 Depth 3
	xorps	%xmm1, %xmm1
	movq	%rbp, %rax
	xorl	%ecx, %ecx
.LBB5_18:                               #   Parent Loop BB5_16 Depth=1
                                        #     Parent Loop BB5_17 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rax), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 32(%rsp,%rcx,4)
	addss	%xmm0, %xmm1
	incq	%rcx
	addq	$16384, %rax                    # imm = 0x4000
	cmpq	$19, %rcx
	jne	.LBB5_18
# %bb.19:                               #   in Loop: Header=BB5_17 Depth=2
	movss	36(%rsp), %xmm9                 # xmm9 = mem[0],zero,zero,zero
	movss	40(%rsp), %xmm7                 # xmm7 = mem[0],zero,zero,zero
	subss	44(%rsp), %xmm9
	movss	52(%rsp), %xmm3                 # xmm3 = mem[0],zero,zero,zero
	addss	%xmm3, %xmm9
	movss	56(%rsp), %xmm4                 # xmm4 = mem[0],zero,zero,zero
	subss	%xmm4, %xmm9
	movss	60(%rsp), %xmm5                 # xmm5 = mem[0],zero,zero,zero
	subss	%xmm5, %xmm9
	movss	64(%rsp), %xmm6                 # xmm6 = mem[0],zero,zero,zero
	addss	%xmm6, %xmm9
	movss	72(%rsp), %xmm8                 # xmm8 = mem[0],zero,zero,zero
	addss	%xmm8, %xmm9
	movss	80(%rsp), %xmm2                 # xmm2 = mem[0],zero,zero,zero
	subss	%xmm2, %xmm9
	movss	%xmm1, 12(%rsp)                 # 4-byte Spill
	movss	92(%rsp), %xmm1                 # xmm1 = mem[0],zero,zero,zero
	addss	%xmm1, %xmm9
	movss	100(%rsp), %xmm0                # xmm0 = mem[0],zero,zero,zero
	subss	48(%rsp), %xmm7
	subss	%xmm0, %xmm9
	movss	%xmm9, 8(%rsp)                  # 4-byte Spill
	addss	%xmm3, %xmm7
	addss	%xmm4, %xmm7
	subss	%xmm5, %xmm7
	subss	%xmm6, %xmm7
	movss	76(%rsp), %xmm3                 # xmm3 = mem[0],zero,zero,zero
	addss	%xmm3, %xmm7
	movss	84(%rsp), %xmm4                 # xmm4 = mem[0],zero,zero,zero
	subss	%xmm4, %xmm7
	movss	96(%rsp), %xmm5                 # xmm5 = mem[0],zero,zero,zero
	addss	%xmm5, %xmm7
	movss	104(%rsp), %xmm6                # xmm6 = mem[0],zero,zero,zero
	subss	%xmm6, %xmm7
	movss	%xmm7, 4(%rsp)                  # 4-byte Spill
	addss	68(%rsp), %xmm8
	addss	%xmm3, %xmm8
	addss	%xmm2, %xmm8
	addss	%xmm4, %xmm8
	subss	88(%rsp), %xmm8
	subss	%xmm1, %xmm8
	subss	%xmm5, %xmm8
	subss	%xmm0, %xmm8
	subss	%xmm6, %xmm8
	movss	%xmm8, (%rsp)                   # 4-byte Spill
	movq	144(%rsp), %rdi                 # 8-byte Reload
	movl	%r12d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	movq	112(%rsp), %rsi                 # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0                  # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rsp), %xmm0                   # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	12(%rsp), %xmm0                 # 4-byte Folded Reload
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	152(%rsp), %r15                 # 8-byte Reload
	movq	(%r15), %rax
	movq	24(%rsp), %rcx                  # 8-byte Reload
	leaq	(%r12,%rcx), %r14
	xorps	%xmm0, %xmm0
	cvtss2sd	114688(%rax,%r14,4), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%r15), %rax
	movq	120(%rsp), %rcx                 # 8-byte Reload
	leaq	(%r14,%rcx), %r13
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r13,4), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	160(%rsp), %r15                 # 8-byte Reload
	movq	(%r15), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	114688(%rax,%r14,4), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%r15), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r13,4), %xmm0
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r12
	addq	$4, %rbp
	cmpq	$64, %r12
	jne	.LBB5_17
# %bb.20:                               #   in Loop: Header=BB5_16 Depth=1
	movq	16(%rsp), %rax                  # 8-byte Reload
	incq	%rax
	movq	136(%rsp), %rbp                 # 8-byte Reload
	addq	$256, %rbp                      # imm = 0x100
	cmpq	$64, %rax
	jne	.LBB5_16
# %bb.21:
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii, .Lfunc_end5-_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z11WriteInputsRSoffi
.LCPI6_0:
	.quad	0x4037800000000000              # double 23.5
.LCPI6_1:
	.quad	0x4040400000000000              # double 32.5
.LCPI6_2:
	.quad	0x4010000000000000              # double 4
.LCPI6_3:
	.quad	0x4073f80000000000              # double 319.5
.LCPI6_4:
	.quad	0x407ff80000000000              # double 511.5
.LCPI6_5:
	.quad	0x403f800000000000              # double 31.5
.LCPI6_6:
	.quad	0x4040000000000000              # double 32
.LCPI6_7:
	.quad	0x4034000000000000              # double 20
.LCPI6_8:
	.quad	0x3fb47ae140000000              # double 0.079999998211860657
.LCPI6_9:
	.quad	0x3fb99999a0000000              # double 0.10000000149011612
.LCPI6_10:
	.quad	0x3fe0000000000000              # double 0.5
.LCPI6_11:
	.quad	0x4027800000000000              # double 11.75
.LCPI6_12:
	.quad	0xbfd0000000000000              # double -0.25
	.text
	.globl	_Z11WriteInputsRSoffi
	.type	_Z11WriteInputsRSoffi,@function
_Z11WriteInputsRSoffi:                  # @_Z11WriteInputsRSoffi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%esi, %ebx
	movss	%xmm1, 12(%rsp)                 # 4-byte Spill
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movq	%rdi, %r14
	movl	$.L.str.7, %esi
	movl	$18, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	$64, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	$64, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	$8, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.9, %esi
	movl	$17, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	$64, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.10, %esi
	movl	$18, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movsd	.LCPI6_0(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.11, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r15), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.12, %esi
	movl	$15, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_2(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.13, %esi
	movl	$18, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_3(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_4(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.6, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_5(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.11, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r15), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.14, %esi
	movl	$15, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_6(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.15, %esi
	movl	$5, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_7(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.16, %esi
	movl	$7, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_8(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.17, %esi
	movl	$9, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.18, %esi
	movl	$7, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	$1000, %esi                     # imm = 0x3E8
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.19, %esi
	movl	$9, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.20, %esi
	movl	$14, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	$400000, %esi                   # imm = 0x61A80
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.21, %esi
	movl	$16, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	$700000, %esi                   # imm = 0xAAE60
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.22, %esi
	movl	$13, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.23, %esi
	movl	$8, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$.L.str.24, %esi
	movl	$3, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.25, %esi
	movl	$18, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.26, %esi
	movl	$5, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_9(%rip), %xmm0           # xmm0 = mem[0],zero
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.27, %esi
	movl	$16, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	$48, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	$64, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	$8, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.28, %esi
	movl	$11, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_10(%rip), %xmm0          # xmm0 = mem[0],zero
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.29, %esi
	movl	$13, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_11(%rip), %xmm0          # xmm0 = mem[0],zero
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movsd	.LCPI6_11(%rip), %xmm0          # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	.LCPI6_12(%rip), %xmm0          # xmm0 = mem[0],zero
	movq	%r15, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.30, %esi
	movl	$15, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	$48, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movl	$.L.str.8, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.31, %esi
	movl	$15, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	12(%rsp), %xmm0                 # 4-byte Folded Reload
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.32, %esi
	movl	$17, %edx
	movq	%r14, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZNSo5flushEv                   # TAILCALL
.Lfunc_end6:
	.size	_Z11WriteInputsRSoffi, .Lfunc_end6-_Z11WriteInputsRSoffi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI7_0:
	.long	0x3fd6c3dd                      # float 1.67785227
.LCPI7_1:
	.long	0x3fb8f899                      # float 1.4450866
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI7_2:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI7_3:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI7_4:
	.quad	0x3e112e0be826d695              # double 1.0000000000000001E-9
.LCPI7_5:
	.quad	0x4040624de0000000              # double 32.768001556396484
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$1960, %rsp                     # imm = 0x7A8
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_escape 0x2e, 0x00
	leaq	-44(%rbp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	movl	$.L.str.33, %esi
	movl	$16, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%rbx), %esi
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	.cfi_escape 0x2e, 0x00
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	.cfi_escape 0x2e, 0x00
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	.cfi_escape 0x2e, 0x00
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	.cfi_escape 0x2e, 0x00
	leaq	-968(%rbp), %rdi
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
.Ltmp0:
	.cfi_escape 0x2e, 0x00
	leaq	-1992(%rbp), %rdi
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
.Ltmp1:
# %bb.1:
.Ltmp3:
	.cfi_escape 0x2e, 0x00
	leaq	-1480(%rbp), %rdi
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
.Ltmp4:
# %bb.2:
	leaq	-336(%rbp), %rax
	movq	%rax, -16(%rax)
.Ltmp6:
	.cfi_escape 0x2e, 0x00
	leaq	-352(%rbp), %rdi
	movl	$.L.str.34, %esi
	movl	$.L.str.34+8, %edx
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp7:
# %bb.3:                                # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
	movq	-352(%rbp), %rbx
	movq	-344(%rbp), %r14
	leaq	-144(%rbp), %r15
	movq	%r15, -16(%r15)
	movq	$0, -8(%r15)
	movb	$0, (%r15)
	leaq	4(%r14), %rsi
.Ltmp9:
	.cfi_escape 0x2e, 0x00
	leaq	-160(%rbp), %rdi
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.Ltmp10:
# %bb.4:
.Ltmp11:
	.cfi_escape 0x2e, 0x00
	leaq	-160(%rbp), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm
.Ltmp12:
# %bb.5:
.Ltmp13:
	.cfi_escape 0x2e, 0x00
	leaq	-160(%rbp), %rdi
	movl	$.L.str.35, %esi
	movl	$4, %edx
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm
.Ltmp14:
# %bb.6:                                # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_.exit
	movq	-160(%rbp), %rsi
.Ltmp16:
	.cfi_escape 0x2e, 0x00
	leaq	-968(%rbp), %rdi
	movl	$16, %edx
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp17:
# %bb.7:
	movq	-160(%rbp), %rdi
	cmpq	%r15, %rdi
	je	.LBB7_9
# %bb.8:                                # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
	.cfi_escape 0x2e, 0x00
	callq	_ZdlPv
.LBB7_9:                                # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
	movq	-352(%rbp), %rbx
	movq	-344(%rbp), %r14
	leaq	-160(%rbp), %rdi
	movq	%r15, (%rdi)
	movq	$0, 8(%rdi)
	movb	$0, 16(%rdi)
	leaq	6(%r14), %rsi
.Ltmp19:
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.Ltmp20:
# %bb.10:
.Ltmp21:
	.cfi_escape 0x2e, 0x00
	leaq	-160(%rbp), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm
.Ltmp22:
# %bb.11:
.Ltmp23:
	.cfi_escape 0x2e, 0x00
	leaq	-160(%rbp), %rdi
	movl	$.L.str.36, %esi
	movl	$6, %edx
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm
.Ltmp24:
# %bb.12:                               # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_.exit429
	movq	-160(%rbp), %rsi
.Ltmp26:
	.cfi_escape 0x2e, 0x00
	leaq	-1992(%rbp), %rdi
	movl	$16, %edx
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp27:
# %bb.13:
	movq	-160(%rbp), %rdi
	cmpq	%r15, %rdi
	je	.LBB7_15
# %bb.14:                               # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i430
	.cfi_escape 0x2e, 0x00
	callq	_ZdlPv
.LBB7_15:                               # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit432
	movq	-352(%rbp), %rbx
	movq	-344(%rbp), %r14
	leaq	-160(%rbp), %rdi
	movq	%r15, (%rdi)
	movq	$0, 8(%rdi)
	movb	$0, 16(%rdi)
	leaq	7(%r14), %rsi
.Ltmp29:
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.Ltmp30:
# %bb.16:
.Ltmp31:
	.cfi_escape 0x2e, 0x00
	leaq	-160(%rbp), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm
.Ltmp32:
# %bb.17:
.Ltmp33:
	.cfi_escape 0x2e, 0x00
	leaq	-160(%rbp), %rdi
	movl	$.L.str.37, %esi
	movl	$7, %edx
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm
.Ltmp34:
# %bb.18:                               # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EERKS8_PKS5_.exit438
	movq	-160(%rbp), %rsi
.Ltmp36:
	.cfi_escape 0x2e, 0x00
	leaq	-1480(%rbp), %rdi
	movl	$16, %edx
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp37:
# %bb.19:
	movq	-160(%rbp), %rdi
	cmpq	%r15, %rdi
	je	.LBB7_21
# %bb.20:                               # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i439
	.cfi_escape 0x2e, 0x00
	callq	_ZdlPv
.LBB7_21:                               # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit441
.Ltmp39:
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	movl	$.L.str.38, %esi
	movl	$21, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp40:
# %bb.22:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp41:
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	movl	$64, %esi
	callq	_ZNSo9_M_insertImEERSoT_
.Ltmp42:
# %bb.23:                               # %_ZNSolsEm.exit
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
.Ltmp43:
	.cfi_escape 0x2e, 0x00
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp44:
# %bb.24:                               # %.noexc
.Ltmp45:
	.cfi_escape 0x2e, 0x00
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
.Ltmp46:
# %bb.25:                               # %.noexc470
.Ltmp47:
	.cfi_escape 0x2e, 0x00
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp48:
# %bb.26:                               # %_ZNSolsEPFRSoS_E.exit
	movl	-44(%rbp), %esi
.Ltmp50:
	.cfi_escape 0x2e, 0x00
	leaq	-1480(%rbp), %rdi
	movss	.LCPI7_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI7_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	callq	_Z11WriteInputsRSoffi
.Ltmp51:
# %bb.27:
	movl	-44(%rbp), %esi
.Ltmp52:
	.cfi_escape 0x2e, 0x00
	movss	.LCPI7_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI7_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movl	$_ZSt4cout, %edi
	callq	_Z11WriteInputsRSoffi
.Ltmp53:
# %bb.28:
	movq	%rsp, -360(%rbp)                # 8-byte Spill
	movl	-44(%rbp), %ecx
	xorl	%r14d, %r14d
	movl	$8, %eax
	xorl	%edx, %edx
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, -264(%rbp)                # 8-byte Spill
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rdx
	leaq	15(,%rcx,8), %rax
	andq	$-16, %rax
	subq	%rax, %rdx
	movq	%rdx, -80(%rbp)                 # 8-byte Spill
	movq	%rdx, %rsp
	movl	-44(%rbp), %ebx
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	leaq	15(,%rbx,8), %rax
	andq	$-16, %rax
	subq	%rax, %rcx
	movq	%rcx, -296(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -288(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -280(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -272(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rdx
	movq	%rbx, %rcx
	shlq	$4, %rcx
	subq	%rcx, %rdx
	movq	%rdx, -200(%rbp)                # 8-byte Spill
	movq	%rdx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rdx
	subq	%rcx, %rdx
	movq	%rdx, -232(%rbp)                # 8-byte Spill
	movq	%rdx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rdx
	subq	%rcx, %rdx
	movq	%rdx, -224(%rbp)                # 8-byte Spill
	movq	%rdx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -208(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -216(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	leaq	(%rbx,%rbx,2), %rax
	leaq	15(,%rax,8), %rax
	andq	$-16, %rax
	subq	%rax, %rcx
	movq	%rcx, -192(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -240(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -184(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -176(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -168(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
	.cfi_escape 0x2e, 0x00
	movq	%rsp, %rcx
	subq	%rax, %rcx
	movq	%rcx, -256(%rbp)                # 8-byte Spill
	movq	%rcx, %rsp
.LBB7_29:                               # =>This Inner Loop Header: Depth=1
	.cfi_escape 0x2e, 0x00
	movl	$4000, %edi                     # imm = 0xFA0
	callq	malloc
	movq	%rax, -160(%rbp,%r14,8)
	incq	%r14
	cmpq	$3, %r14
	jne	.LBB7_29
# %bb.30:                               # %.preheader540.preheader
	xorl	%r14d, %r14d
.LBB7_31:                               # %.preheader540
                                        # =>This Inner Loop Header: Depth=1
	movq	-160(%rbp,%r14,8), %rdi
	.cfi_escape 0x2e, 0x00
	movl	$4000, %edx                     # imm = 0xFA0
	xorl	%esi, %esi
	callq	memset@PLT
	incq	%r14
	cmpq	$3, %r14
	jne	.LBB7_31
# %bb.32:                               # %.preheader539
	movq	-264(%rbp), %rax                # 8-byte Reload
	addl	$-2, %eax
	movq	%rax, -72(%rbp)                 # 8-byte Spill
	testl	%ebx, %ebx
	jle	.LBB7_92
# %bb.33:                               # %.lr.ph566
	movq	-72(%rbp), %rcx                 # 8-byte Reload
	imull	$77824, %ecx, %eax              # imm = 0x13000
	movslq	%eax, %rdx
	leaq	(,%rdx,4), %rax
	movq	%rax, -376(%rbp)                # 8-byte Spill
	movslq	%ecx, %rax
	imulq	$311296, %rax, %rcx             # imm = 0x4C000
	movq	%rcx, -408(%rbp)                # 8-byte Spill
	imull	$1216, %eax, %eax               # imm = 0x4C0
	cmpl	$2, %edx
	movl	$1, %ecx
	cmovll	%ecx, %edx
	cltq
	movq	%rax, -400(%rbp)                # 8-byte Spill
	shlq	$2, %rdx
	movq	%rdx, -368(%rbp)                # 8-byte Spill
	xorl	%r12d, %r12d
	movq	-240(%rbp), %rax                # 8-byte Reload
	movq	%rax, -64(%rbp)                 # 8-byte Spill
	movq	-168(%rbp), %r15                # 8-byte Reload
	movq	-256(%rbp), %rax                # 8-byte Reload
	movq	%rax, -88(%rbp)                 # 8-byte Spill
	movq	-192(%rbp), %rax                # 8-byte Reload
	movq	%rax, -96(%rbp)                 # 8-byte Spill
	movq	-184(%rbp), %rax                # 8-byte Reload
	movq	%rax, -104(%rbp)                # 8-byte Spill
	movq	-176(%rbp), %rax                # 8-byte Reload
	movq	%rax, -112(%rbp)                # 8-byte Spill
	xorl	%r14d, %r14d
.LBB7_34:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_35 Depth 2
                                        #     Child Loop BB7_41 Depth 2
                                        #     Child Loop BB7_46 Depth 2
                                        #     Child Loop BB7_53 Depth 2
                                        #     Child Loop BB7_60 Depth 2
                                        #       Child Loop BB7_62 Depth 3
                                        #     Child Loop BB7_65 Depth 2
                                        #     Child Loop BB7_70 Depth 2
                                        #     Child Loop BB7_75 Depth 2
	movq	%r15, -248(%rbp)                # 8-byte Spill
	.cfi_escape 0x2e, 0x00
	movq	-376(%rbp), %rdi                # 8-byte Reload
	callq	malloc
	movq	%rax, %rcx
	movq	-288(%rbp), %rax                # 8-byte Reload
	movq	%rcx, -304(%rbp)                # 8-byte Spill
	movq	%rcx, (%rax,%r14,8)
	.cfi_escape 0x2e, 0x00
	movl	$311296, %edi                   # imm = 0x4C000
	callq	malloc
	movq	%rax, %rcx
	movq	-280(%rbp), %rax                # 8-byte Reload
	movq	%rcx, -128(%rbp)                # 8-byte Spill
	movq	%rcx, (%rax,%r14,8)
	.cfi_escape 0x2e, 0x00
	movl	$311296, %edi                   # imm = 0x4C000
	callq	malloc
	movq	%rax, %rcx
	movq	-272(%rbp), %rax                # 8-byte Reload
	movq	%r14, -56(%rbp)                 # 8-byte Spill
	movq	%rcx, -312(%rbp)                # 8-byte Spill
	movq	%rcx, (%rax,%r14,8)
	movl	$32768, %eax                    # imm = 0x8000
	xorl	%edx, %edx
	idivl	%ebx
	movslq	%eax, %rbx
	shlq	$2, %rbx
	xorl	%r14d, %r14d
	movq	-104(%rbp), %r15                # 8-byte Reload
	movq	-112(%rbp), %r13                # 8-byte Reload
.LBB7_35:                               #   Parent Loop BB7_34 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	.cfi_escape 0x2e, 0x00
	movl	$4000, %edi                     # imm = 0xFA0
	callq	malloc
	movq	-96(%rbp), %rcx                 # 8-byte Reload
	movq	%rax, (%rcx,%r14,8)
	.cfi_escape 0x2e, 0x00
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, (%r15,%r14,8)
	.cfi_escape 0x2e, 0x00
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, (%r13,%r14,8)
	incq	%r14
	cmpq	$3, %r14
	jne	.LBB7_35
# %bb.36:                               #   in Loop: Header=BB7_34 Depth=1
.Ltmp55:
	.cfi_escape 0x2e, 0x00
	movq	-56(%rbp), %rdi                 # 8-byte Reload
                                        # kill: def $edi killed $edi killed $rdi
	callq	hipSetDevice
.Ltmp56:
# %bb.37:                               #   in Loop: Header=BB7_34 Depth=1
	movq	-80(%rbp), %rax                 # 8-byte Reload
	movq	-56(%rbp), %rcx                 # 8-byte Reload
	leaq	(%rax,%rcx,8), %rdi
.Ltmp57:
	.cfi_escape 0x2e, 0x00
	callq	hipStreamCreate
.Ltmp58:
# %bb.38:                               #   in Loop: Header=BB7_34 Depth=1
	movq	-296(%rbp), %rax                # 8-byte Reload
	movq	-56(%rbp), %rcx                 # 8-byte Reload
	leaq	(%rax,%rcx,8), %rdi
.Ltmp59:
	.cfi_escape 0x2e, 0x00
	callq	hipStreamCreate
.Ltmp60:
# %bb.39:                               # %.preheader538
                                        #   in Loop: Header=BB7_34 Depth=1
	movl	-44(%rbp), %eax
	testl	%eax, %eax
	movq	-56(%rbp), %r14                 # 8-byte Reload
	jle	.LBB7_45
# %bb.40:                               # %.lr.ph.preheader
                                        #   in Loop: Header=BB7_34 Depth=1
	xorl	%ebx, %ebx
.LBB7_41:                               # %.lr.ph
                                        #   Parent Loop BB7_34 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	%rbx, %r14
	je	.LBB7_44
# %bb.42:                               #   in Loop: Header=BB7_41 Depth=2
.Ltmp61:
	.cfi_escape 0x2e, 0x00
	movl	%ebx, %edi
	xorl	%esi, %esi
	callq	hipDeviceEnablePeerAccess
.Ltmp62:
# %bb.43:                               # %._crit_edge683
                                        #   in Loop: Header=BB7_41 Depth=2
	movl	-44(%rbp), %eax
.LBB7_44:                               #   in Loop: Header=BB7_41 Depth=2
	incq	%rbx
	cmpl	%eax, %ebx
	jl	.LBB7_41
.LBB7_45:                               # %.preheader537.preheader
                                        #   in Loop: Header=BB7_34 Depth=1
	movb	$1, %bl
	xorl	%r13d, %r13d
.LBB7_46:                               # %.preheader537
                                        #   Parent Loop BB7_34 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	-56(%rbp), %r14                 # 8-byte Reload
	shlq	$4, %r14
	movq	-200(%rbp), %rax                # 8-byte Reload
	addq	%r14, %rax
	movq	%rax, -120(%rbp)                # 8-byte Spill
	leaq	(%rax,%r13,8), %rdi
.Ltmp64:
	.cfi_escape 0x2e, 0x00
	movq	-408(%rbp), %rsi                # 8-byte Reload
	callq	hipMalloc
.Ltmp65:
# %bb.47:                               #   in Loop: Header=BB7_46 Depth=2
	movq	-232(%rbp), %rax                # 8-byte Reload
	leaq	(%rax,%r14), %r15
	leaq	(%r15,%r13,8), %rdi
.Ltmp66:
	.cfi_escape 0x2e, 0x00
	movl	$311296, %esi                   # imm = 0x4C000
	callq	hipMalloc
.Ltmp67:
# %bb.48:                               #   in Loop: Header=BB7_46 Depth=2
	addq	-224(%rbp), %r14                # 8-byte Folded Reload
	leaq	(%r14,%r13,8), %rdi
.Ltmp68:
	.cfi_escape 0x2e, 0x00
	movl	$311296, %esi                   # imm = 0x4C000
	callq	hipMalloc
.Ltmp69:
# %bb.49:                               #   in Loop: Header=BB7_46 Depth=2
	movl	$1, %r13d
	testb	$1, %bl
	movl	$0, %ebx
	jne	.LBB7_46
# %bb.50:                               #   in Loop: Header=BB7_34 Depth=1
	movq	-208(%rbp), %rax                # 8-byte Reload
	movq	-56(%rbp), %rcx                 # 8-byte Reload
	leaq	(%rax,%rcx,8), %rdi
.Ltmp71:
	.cfi_escape 0x2e, 0x00
	movl	$311296, %esi                   # imm = 0x4C000
	movq	%rdi, -392(%rbp)                # 8-byte Spill
	callq	hipMalloc
.Ltmp72:
	movq	-248(%rbp), %r13                # 8-byte Reload
# %bb.51:                               #   in Loop: Header=BB7_34 Depth=1
	movq	-216(%rbp), %rax                # 8-byte Reload
	movq	-56(%rbp), %rcx                 # 8-byte Reload
	leaq	(%rax,%rcx,8), %rdi
.Ltmp73:
	.cfi_escape 0x2e, 0x00
	movl	$311296, %esi                   # imm = 0x4C000
	movq	%rdi, -384(%rbp)                # 8-byte Spill
	callq	hipMalloc
.Ltmp74:
# %bb.52:                               # %.preheader536.preheader
                                        #   in Loop: Header=BB7_34 Depth=1
	xorl	%ebx, %ebx
.LBB7_53:                               # %.preheader536
                                        #   Parent Loop BB7_34 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	-64(%rbp), %rax                 # 8-byte Reload
	leaq	(%rax,%rbx), %rdi
.Ltmp75:
	.cfi_escape 0x2e, 0x00
	movl	$4000, %esi                     # imm = 0xFA0
	callq	hipMalloc
.Ltmp76:
# %bb.54:                               #   in Loop: Header=BB7_53 Depth=2
	leaq	(%rbx,%r13), %rdi
	movslq	-44(%rbp), %rcx
	movl	$32768, %eax                    # imm = 0x8000
	xorl	%edx, %edx
	divq	%rcx
	leal	(,%rax,4), %esi
.Ltmp77:
	.cfi_escape 0x2e, 0x00
	callq	hipMalloc
.Ltmp78:
# %bb.55:                               #   in Loop: Header=BB7_53 Depth=2
	movq	-88(%rbp), %rax                 # 8-byte Reload
	leaq	(%rax,%rbx), %rdi
	movslq	-44(%rbp), %rcx
	movl	$32768, %eax                    # imm = 0x8000
	xorl	%edx, %edx
	divq	%rcx
	leal	(,%rax,4), %esi
.Ltmp79:
	.cfi_escape 0x2e, 0x00
	callq	hipMalloc
.Ltmp80:
# %bb.56:                               #   in Loop: Header=BB7_53 Depth=2
	addq	$8, %rbx
	cmpq	$24, %rbx
	jne	.LBB7_53
# %bb.57:                               # %.preheader535
                                        #   in Loop: Header=BB7_34 Depth=1
	cmpl	$3, -264(%rbp)                  # 4-byte Folded Reload
	jl	.LBB7_59
# %bb.58:                               # %.lr.ph556.preheader
                                        #   in Loop: Header=BB7_34 Depth=1
	.cfi_escape 0x2e, 0x00
	movq	-304(%rbp), %rdi                # 8-byte Reload
	xorl	%esi, %esi
	movq	-368(%rbp), %rdx                # 8-byte Reload
	callq	memset@PLT
.LBB7_59:                               # %.preheader534
                                        #   in Loop: Header=BB7_34 Depth=1
	.cfi_escape 0x2e, 0x00
	movl	$311296, %edx                   # imm = 0x4C000
	movq	-128(%rbp), %rdi                # 8-byte Reload
	xorl	%esi, %esi
	callq	memset@PLT
	.cfi_escape 0x2e, 0x00
	movl	$311296, %edx                   # imm = 0x4C000
	movq	-312(%rbp), %rdi                # 8-byte Reload
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$32768, %eax                    # imm = 0x8000
	xorl	%edx, %edx
	idivl	-44(%rbp)
	movl	%eax, %ebx
	xorl	%r13d, %r13d
.LBB7_60:                               # %.preheader529
                                        #   Parent Loop BB7_34 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB7_62 Depth 3
	movq	-56(%rbp), %rax                 # 8-byte Reload
	leaq	(%rax,%rax,2), %rax
	movq	-192(%rbp), %rcx                # 8-byte Reload
	leaq	(%rcx,%rax,8), %rax
	movq	(%rax,%r13,8), %rdi
	.cfi_escape 0x2e, 0x00
	movl	$4000, %edx                     # imm = 0xFA0
	xorl	%esi, %esi
	callq	memset@PLT
	testl	%ebx, %ebx
	jle	.LBB7_63
# %bb.61:                               # %.lr.ph560
                                        #   in Loop: Header=BB7_60 Depth=2
	movq	-56(%rbp), %rax                 # 8-byte Reload
	leaq	(,%rax,8), %rax
	leaq	(%rax,%rax,2), %rcx
	movq	-184(%rbp), %rax                # 8-byte Reload
	addq	%rcx, %rax
	movq	(%rax,%r13,8), %rax
	addq	-176(%rbp), %rcx                # 8-byte Folded Reload
	movq	(%rcx,%r13,8), %rcx
	xorl	%edx, %edx
.LBB7_62:                               #   Parent Loop BB7_34 Depth=1
                                        #     Parent Loop BB7_60 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	%r12d, (%rax,%rdx,4)
	movl	%r12d, (%rcx,%rdx,4)
	incq	%rdx
	cmpq	%rdx, %rbx
	jne	.LBB7_62
.LBB7_63:                               # %._crit_edge
                                        #   in Loop: Header=BB7_60 Depth=2
	incq	%r13
	cmpq	$3, %r13
	jne	.LBB7_60
# %bb.64:                               # %.preheader532.preheader
                                        #   in Loop: Header=BB7_34 Depth=1
	movb	$1, %bl
	xorl	%r13d, %r13d
.LBB7_65:                               # %.preheader532
                                        #   Parent Loop BB7_34 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	-120(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%r13,8), %rdi
.Ltmp82:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movq	-304(%rbp), %rdx                # 8-byte Reload
	movq	-400(%rbp), %r9                 # 8-byte Reload
	pushq	$1
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp83:
# %bb.66:                               #   in Loop: Header=BB7_65 Depth=2
	movq	(%r15,%r13,8), %rdi
.Ltmp84:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movl	$1216, %r9d                     # imm = 0x4C0
	movq	-128(%rbp), %rdx                # 8-byte Reload
	pushq	$1
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp85:
# %bb.67:                               #   in Loop: Header=BB7_65 Depth=2
	movq	(%r14,%r13,8), %rdi
.Ltmp86:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movl	$1216, %r9d                     # imm = 0x4C0
	movq	-312(%rbp), %rdx                # 8-byte Reload
	pushq	$1
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp87:
# %bb.68:                               #   in Loop: Header=BB7_65 Depth=2
	movl	$1, %r13d
	testb	$1, %bl
	movl	$0, %ebx
	jne	.LBB7_65
# %bb.69:                               # %.preheader531.preheader
                                        #   in Loop: Header=BB7_34 Depth=1
	xorl	%ebx, %ebx
	movq	-248(%rbp), %r13                # 8-byte Reload
.LBB7_70:                               # %.preheader531
                                        #   Parent Loop BB7_34 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	(%r13,%rbx), %rdi
	movq	-104(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx), %r10
	movl	$512, %eax                      # imm = 0x200
	xorl	%edx, %edx
	idivl	-44(%rbp)
	movslq	%eax, %r9
.Ltmp89:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movq	%r10, %rdx
	pushq	$1
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp90:
# %bb.71:                               #   in Loop: Header=BB7_70 Depth=2
	movq	-88(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%rbx), %rdi
	movq	-112(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx), %r10
	movl	$512, %eax                      # imm = 0x200
	xorl	%edx, %edx
	idivl	-44(%rbp)
	movslq	%eax, %r9
.Ltmp91:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movq	%r10, %rdx
	pushq	$1
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp92:
# %bb.72:                               #   in Loop: Header=BB7_70 Depth=2
	movq	-64(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%rbx), %rdi
	movq	-96(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%rbx), %rsi
.Ltmp93:
	.cfi_escape 0x2e, 0x00
	movl	$4000, %edx                     # imm = 0xFA0
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp94:
# %bb.73:                               #   in Loop: Header=BB7_70 Depth=2
	addq	$8, %rbx
	cmpq	$24, %rbx
	jne	.LBB7_70
# %bb.74:                               # %.preheader530.preheader
                                        #   in Loop: Header=BB7_34 Depth=1
	movb	$1, %bl
	xorl	%r13d, %r13d
.LBB7_75:                               # %.preheader530
                                        #   Parent Loop BB7_34 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
.Ltmp96:
	.cfi_escape 0x2e, 0x00
	movabsq	$274877906945, %rdi             # imm = 0x4000000001
	movq	-72(%rbp), %rsi                 # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp97:
# %bb.76:                               #   in Loop: Header=BB7_75 Depth=2
	testl	%eax, %eax
	jne	.LBB7_78
# %bb.77:                               #   in Loop: Header=BB7_75 Depth=2
	movq	-120(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%r13,8), %rdi
	movl	-44(%rbp), %ecx
.Ltmp98:
	.cfi_escape 0x2e, 0x00
	movl	$64, %esi
	movq	-72(%rbp), %rdx                 # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	xorl	%r8d, %r8d
	callq	_Z25__device_stub__initializePfmiii
.Ltmp99:
.LBB7_78:                               #   in Loop: Header=BB7_75 Depth=2
.Ltmp100:
	.cfi_escape 0x2e, 0x00
	movabsq	$274877906945, %rdi             # imm = 0x4000000001
	movl	$1, %esi
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp101:
# %bb.79:                               #   in Loop: Header=BB7_75 Depth=2
	testl	%eax, %eax
	jne	.LBB7_81
# %bb.80:                               #   in Loop: Header=BB7_75 Depth=2
	movq	(%r15,%r13,8), %rdi
	movl	-44(%rbp), %ecx
.Ltmp102:
	.cfi_escape 0x2e, 0x00
	movl	$64, %esi
	movl	$1, %edx
	xorl	%r8d, %r8d
	callq	_Z25__device_stub__initializePfmiii
.Ltmp103:
.LBB7_81:                               #   in Loop: Header=BB7_75 Depth=2
.Ltmp104:
	.cfi_escape 0x2e, 0x00
	movabsq	$274877906945, %rdi             # imm = 0x4000000001
	movl	$1, %esi
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp105:
# %bb.82:                               #   in Loop: Header=BB7_75 Depth=2
	testl	%eax, %eax
	jne	.LBB7_84
# %bb.83:                               #   in Loop: Header=BB7_75 Depth=2
	movq	(%r14,%r13,8), %rdi
	movl	-44(%rbp), %ecx
.Ltmp106:
	.cfi_escape 0x2e, 0x00
	movl	$64, %esi
	movl	$1, %edx
	xorl	%r8d, %r8d
	callq	_Z25__device_stub__initializePfmiii
.Ltmp107:
.LBB7_84:                               #   in Loop: Header=BB7_75 Depth=2
	movl	$1, %r13d
	testb	$1, %bl
	movl	$0, %ebx
	jne	.LBB7_75
# %bb.85:                               #   in Loop: Header=BB7_34 Depth=1
.Ltmp109:
	.cfi_escape 0x2e, 0x00
	movabsq	$274877906945, %rdi             # imm = 0x4000000001
	movl	$1, %esi
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp110:
	movq	-248(%rbp), %r15                # 8-byte Reload
# %bb.86:                               #   in Loop: Header=BB7_34 Depth=1
	testl	%eax, %eax
	jne	.LBB7_88
# %bb.87:                               #   in Loop: Header=BB7_34 Depth=1
	movq	-392(%rbp), %rax                # 8-byte Reload
	movq	(%rax), %rdi
	movl	-44(%rbp), %ecx
.Ltmp111:
	.cfi_escape 0x2e, 0x00
	movl	$64, %esi
	movl	$1, %edx
	xorl	%r8d, %r8d
	callq	_Z25__device_stub__initializePfmiii
.Ltmp112:
.LBB7_88:                               #   in Loop: Header=BB7_34 Depth=1
.Ltmp113:
	.cfi_escape 0x2e, 0x00
	movabsq	$274877906945, %rdi             # imm = 0x4000000001
	movl	$1, %esi
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp114:
# %bb.89:                               #   in Loop: Header=BB7_34 Depth=1
	testl	%eax, %eax
	jne	.LBB7_91
# %bb.90:                               #   in Loop: Header=BB7_34 Depth=1
	movq	-384(%rbp), %rax                # 8-byte Reload
	movq	(%rax), %rdi
	movl	-44(%rbp), %ecx
.Ltmp115:
	.cfi_escape 0x2e, 0x00
	movl	$64, %esi
	movl	$1, %edx
	xorl	%r8d, %r8d
	callq	_Z25__device_stub__initializePfmiii
.Ltmp116:
.LBB7_91:                               #   in Loop: Header=BB7_34 Depth=1
	movq	-56(%rbp), %r14                 # 8-byte Reload
	incq	%r14
	movslq	-44(%rbp), %rbx
	addq	$24, -112(%rbp)                 # 8-byte Folded Spill
	addq	$24, -104(%rbp)                 # 8-byte Folded Spill
	addq	$24, -96(%rbp)                  # 8-byte Folded Spill
	addq	$24, -88(%rbp)                  # 8-byte Folded Spill
	addq	$24, %r15
	addq	$24, -64(%rbp)                  # 8-byte Folded Spill
	cmpq	%rbx, %r14
	jl	.LBB7_34
.LBB7_92:                               # %._crit_edge567
.Ltmp118:
	.cfi_escape 0x2e, 0x00
	callq	hipDeviceSynchronize
.Ltmp119:
# %bb.93:
	.cfi_escape 0x2e, 0x00
	xorl	%eax, %eax
	movq	%rax, -104(%rbp)                # 8-byte Spill
	leaq	-440(%rbp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	cmpl	$0, -44(%rbp)
	jle	.LBB7_108
# %bb.94:                               # %.lr.ph570.preheader
	xorl	%ebx, %ebx
	leaq	-320(%rbp), %r14
	leaq	-416(%rbp), %r15
.LBB7_95:                               # %.lr.ph570
                                        # =>This Inner Loop Header: Depth=1
.Ltmp120:
	.cfi_escape 0x2e, 0x00
	movl	%ebx, %edi
	callq	hipSetDevice
.Ltmp121:
# %bb.96:                               #   in Loop: Header=BB7_95 Depth=1
.Ltmp123:
	.cfi_escape 0x2e, 0x00
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	hipMemGetInfo
.Ltmp124:
# %bb.97:                               #   in Loop: Header=BB7_95 Depth=1
.Ltmp125:
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	movl	$.L.str.39, %esi
	movl	$26, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp126:
# %bb.98:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit451
                                        #   in Loop: Header=BB7_95 Depth=1
.Ltmp127:
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
.Ltmp128:
# %bb.99:                               #   in Loop: Header=BB7_95 Depth=1
.Ltmp129:
	movq	%rax, %r12
	.cfi_escape 0x2e, 0x00
	movl	$.L.str.40, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp130:
# %bb.100:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit452
                                        #   in Loop: Header=BB7_95 Depth=1
	movq	-416(%rbp), %rax
	subq	-320(%rbp), %rax
	movq	%rax, %xmm1
	punpckldq	.LCPI7_2(%rip), %xmm1   # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	subpd	.LCPI7_3(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	.LCPI7_4(%rip), %xmm0
.Ltmp131:
	.cfi_escape 0x2e, 0x00
	movq	%r12, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp132:
# %bb.101:                              # %_ZNSolsEd.exit
                                        #   in Loop: Header=BB7_95 Depth=1
.Ltmp133:
	.cfi_escape 0x2e, 0x00
	movl	$.L.str.41, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp134:
# %bb.102:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit453
                                        #   in Loop: Header=BB7_95 Depth=1
.Ltmp135:
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	movl	$.L.str.42, %esi
	movl	$31, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp136:
# %bb.103:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit454
                                        #   in Loop: Header=BB7_95 Depth=1
.Ltmp137:
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	movl	%ebx, %esi
	callq	_ZNSolsEi
.Ltmp138:
# %bb.104:                              #   in Loop: Header=BB7_95 Depth=1
.Ltmp139:
	movq	%rax, %r12
	.cfi_escape 0x2e, 0x00
	movl	$.L.str.40, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp140:
# %bb.105:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit455
                                        #   in Loop: Header=BB7_95 Depth=1
	movsd	-320(%rbp), %xmm1               # xmm1 = mem[0],zero
	unpcklps	.LCPI7_2(%rip), %xmm1           # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	subpd	.LCPI7_3(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	.LCPI7_4(%rip), %xmm0
.Ltmp141:
	.cfi_escape 0x2e, 0x00
	movq	%r12, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp142:
# %bb.106:                              # %_ZNSolsEd.exit456
                                        #   in Loop: Header=BB7_95 Depth=1
.Ltmp143:
	.cfi_escape 0x2e, 0x00
	movl	$.L.str.41, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp144:
# %bb.107:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit457
                                        #   in Loop: Header=BB7_95 Depth=1
	incl	%ebx
	cmpl	-44(%rbp), %ebx
	jl	.LBB7_95
.LBB7_108:                              # %.preheader526.preheader
	movl	$1, %eax
	movabsq	$274877906945, %r14             # imm = 0x4000000001
	movabsq	$4294967360, %r13               # imm = 0x100000040
	xorl	%ebx, %ebx
.LBB7_109:                              # %.preheader526
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_111 Depth 2
                                        #     Child Loop BB7_121 Depth 2
                                        #     Child Loop BB7_125 Depth 2
                                        #     Child Loop BB7_132 Depth 2
                                        #     Child Loop BB7_135 Depth 2
	cmpl	$0, -44(%rbp)
	movl	%eax, -128(%rbp)                # 4-byte Spill
	movl	%eax, %r12d
	jle	.LBB7_131
# %bb.110:                              # %.lr.ph572
                                        #   in Loop: Header=BB7_109 Depth=1
	movl	%ebx, %eax
	movq	-224(%rbp), %rcx                # 8-byte Reload
	leaq	(%rcx,%r12,8), %rdx
	movq	%rdx, -64(%rbp)                 # 8-byte Spill
	leaq	(%rcx,%rax,8), %rcx
	movq	%rcx, -120(%rbp)                # 8-byte Spill
	movq	-200(%rbp), %rcx                # 8-byte Reload
	leaq	(%rcx,%rax,8), %rcx
	movq	%rcx, -56(%rbp)                 # 8-byte Spill
	movq	-232(%rbp), %rcx                # 8-byte Reload
	movq	%r12, -112(%rbp)                # 8-byte Spill
	leaq	(%rcx,%r12,8), %rdx
	movq	%rdx, -88(%rbp)                 # 8-byte Spill
	leaq	(%rcx,%rax,8), %rax
	movq	%rax, -96(%rbp)                 # 8-byte Spill
	xorl	%r12d, %r12d
	xorl	%r15d, %r15d
.LBB7_111:                              #   Parent Loop BB7_109 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
.Ltmp146:
	.cfi_escape 0x2e, 0x00
	movl	%r15d, %edi
	callq	hipSetDevice
.Ltmp147:
# %bb.112:                              #   in Loop: Header=BB7_111 Depth=2
	movq	-80(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12), %r9
.Ltmp148:
	.cfi_escape 0x2e, 0x00
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
.Ltmp149:
# %bb.113:                              #   in Loop: Header=BB7_111 Depth=2
	testl	%eax, %eax
	jne	.LBB7_115
# %bb.114:                              #   in Loop: Header=BB7_111 Depth=2
	movq	-64(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12,2), %rdi
	movq	-120(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%r12,2), %rsi
	movq	-56(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12,2), %rdx
	movq	-216(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%r12), %rcx
.Ltmp150:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$64, %r8d
	movss	.LCPI7_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	%r15d, %r9d
	pushq	-72(%rbp)                       # 8-byte Folded Reload
	callq	_Z25__device_stub__update_topPfS_S_S_fmii
	addq	$16, %rsp
.Ltmp151:
.LBB7_115:                              #   in Loop: Header=BB7_111 Depth=2
	movq	-80(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12), %r9
.Ltmp152:
	.cfi_escape 0x2e, 0x00
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
.Ltmp153:
# %bb.116:                              #   in Loop: Header=BB7_111 Depth=2
	testl	%eax, %eax
	jne	.LBB7_118
# %bb.117:                              #   in Loop: Header=BB7_111 Depth=2
	movq	-88(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12,2), %rdi
	movq	-96(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12,2), %rsi
	movq	-56(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12,2), %rdx
	movq	-208(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%r12), %rcx
.Ltmp154:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$64, %r8d
	movss	.LCPI7_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	%r15d, %r9d
	pushq	-72(%rbp)                       # 8-byte Folded Reload
	callq	_Z25__device_stub__update_botPfS_S_S_fmii
	addq	$16, %rsp
.Ltmp155:
.LBB7_118:                              #   in Loop: Header=BB7_111 Depth=2
	incq	%r15
	movslq	-44(%rbp), %rax
	addq	$8, %r12
	cmpq	%rax, %r15
	jl	.LBB7_111
# %bb.119:                              # %.preheader525
                                        #   in Loop: Header=BB7_109 Depth=1
	testl	%eax, %eax
	movq	-112(%rbp), %r12                # 8-byte Reload
	jle	.LBB7_131
# %bb.120:                              # %.lr.ph574.preheader
                                        #   in Loop: Header=BB7_109 Depth=1
	movl	%ebx, -88(%rbp)                 # 4-byte Spill
	xorl	%ebx, %ebx
.LBB7_121:                              # %.lr.ph574
                                        #   Parent Loop BB7_109 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	-80(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%rbx,8), %rdi
.Ltmp157:
	.cfi_escape 0x2e, 0x00
	callq	hipStreamSynchronize
.Ltmp158:
# %bb.122:                              #   in Loop: Header=BB7_121 Depth=2
	incq	%rbx
	movslq	-44(%rbp), %rax
	cmpq	%rax, %rbx
	jl	.LBB7_121
# %bb.123:                              # %.preheader524
                                        #   in Loop: Header=BB7_109 Depth=1
	testl	%eax, %eax
	movl	-88(%rbp), %ebx                 # 4-byte Reload
	jle	.LBB7_131
# %bb.124:                              # %.lr.ph576
                                        #   in Loop: Header=BB7_109 Depth=1
	movq	%r14, %r13
	movq	-200(%rbp), %rax                # 8-byte Reload
	leaq	(%rax,%r12,8), %rax
	movq	%rax, -64(%rbp)                 # 8-byte Spill
	xorl	%r12d, %r12d
	movq	-168(%rbp), %r14                # 8-byte Reload
	movq	-256(%rbp), %rbx                # 8-byte Reload
	xorl	%r15d, %r15d
.LBB7_125:                              #   Parent Loop BB7_109 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
.Ltmp160:
	.cfi_escape 0x2e, 0x00
	movl	%r15d, %edi
	callq	hipSetDevice
.Ltmp161:
# %bb.126:                              #   in Loop: Header=BB7_125 Depth=2
	movq	-296(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%r12), %r9
.Ltmp162:
	.cfi_escape 0x2e, 0x00
	movq	%r13, %rdi
	movq	-72(%rbp), %rsi                 # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
.Ltmp163:
# %bb.127:                              #   in Loop: Header=BB7_125 Depth=2
	testl	%eax, %eax
	jne	.LBB7_129
# %bb.128:                              #   in Loop: Header=BB7_125 Depth=2
	movq	-64(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12,2), %rdi
	movq	-56(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12,2), %rsi
	movq	-96(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12,2), %rdx
	movq	-120(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%r12,2), %rcx
.Ltmp164:
	.cfi_escape 0x2e, 0x20
	movl	$64, %r8d
	movss	.LCPI7_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movl	%r15d, %r9d
	pushq	-104(%rbp)                      # 8-byte Folded Reload
	pushq	%rbx
	pushq	%r14
	pushq	-72(%rbp)                       # 8-byte Folded Reload
	callq	_Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i
	addq	$32, %rsp
.Ltmp165:
.LBB7_129:                              #   in Loop: Header=BB7_125 Depth=2
	incq	%r15
	movslq	-44(%rbp), %rax
	addq	$24, %rbx
	addq	$24, %r14
	addq	$8, %r12
	cmpq	%rax, %r15
	jl	.LBB7_125
# %bb.130:                              #   in Loop: Header=BB7_109 Depth=1
	movq	-112(%rbp), %r12                # 8-byte Reload
	movq	%r13, %r14
	movabsq	$4294967360, %r13               # imm = 0x100000040
	movl	-88(%rbp), %ebx                 # 4-byte Reload
.LBB7_131:                              # %.preheader523
                                        #   in Loop: Header=BB7_109 Depth=1
	xorl	%esi, %esi
.LBB7_132:                              #   Parent Loop BB7_109 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	-44(%rbp), %rcx
	cmpq	%rcx, %rsi
	jge	.LBB7_133
# %bb.207:                              #   in Loop: Header=BB7_132 Depth=2
	movq	-216(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rsi,8), %rdi
	leaq	1(%rsi), %r15
	movl	%r15d, %eax
	cltd
	idivl	%ecx
	movl	%edx, %ecx
	movq	%rcx, %rax
	shlq	$4, %rax
	addq	-232(%rbp), %rax                # 8-byte Folded Reload
	movq	(%rax,%r12,8), %rdx
	movq	-80(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%rsi,8), %r9
	leal	-1(%r15), %esi
.Ltmp233:
	.cfi_escape 0x2e, 0x00
	movl	$311296, %r8d                   # imm = 0x4C000
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	hipMemcpyPeerAsync
.Ltmp234:
	movq	%r15, %rsi
	jmp	.LBB7_132
.LBB7_133:                              # %.preheader522
                                        #   in Loop: Header=BB7_109 Depth=1
	testl	%ecx, %ecx
	jle	.LBB7_137
# %bb.134:                              # %.lr.ph578.preheader
                                        #   in Loop: Header=BB7_109 Depth=1
	xorl	%r15d, %r15d
.LBB7_135:                              # %.lr.ph578
                                        #   Parent Loop BB7_109 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	-208(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%r15,8), %rdi
	leal	-1(%r15), %edx
	movl	%edx, %eax
	negl	%eax
	cmovsl	%edx, %eax
	cltd
	idivl	%ecx
	movl	%edx, %ecx
	movq	%rcx, %rax
	shlq	$4, %rax
	addq	-224(%rbp), %rax                # 8-byte Folded Reload
	movq	(%rax,%r12,8), %rdx
	movq	-80(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r15,8), %r9
.Ltmp167:
	.cfi_escape 0x2e, 0x00
	movl	$311296, %r8d                   # imm = 0x4C000
	movl	%r15d, %esi
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	hipMemcpyPeerAsync
.Ltmp168:
# %bb.136:                              #   in Loop: Header=BB7_135 Depth=2
	incq	%r15
	movslq	-44(%rbp), %rcx
	cmpq	%rcx, %r15
	jl	.LBB7_135
.LBB7_137:                              # %._crit_edge579
                                        #   in Loop: Header=BB7_109 Depth=1
.Ltmp170:
	.cfi_escape 0x2e, 0x00
	callq	hipDeviceSynchronize
.Ltmp171:
# %bb.138:                              #   in Loop: Header=BB7_109 Depth=1
	movq	-104(%rbp), %rcx                # 8-byte Reload
	incl	%ecx
	movl	%ebx, %eax
	movl	-128(%rbp), %ebx                # 4-byte Reload
	movq	%rcx, -104(%rbp)                # 8-byte Spill
	cmpl	$1000, %ecx                     # imm = 0x3E8
	jne	.LBB7_109
# %bb.139:
.Ltmp173:
	.cfi_escape 0x2e, 0x00
	callq	hipDeviceSynchronize
.Ltmp174:
# %bb.140:
	.cfi_escape 0x2e, 0x00
	leaq	-456(%rbp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	.cfi_escape 0x2e, 0x00
	leaq	-424(%rbp), %rdi
	leaq	-440(%rbp), %rdx
	movq	%r14, %rsi
	callq	_Z16timeval_subtractPdP7timevalS1_
.Ltmp176:
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	movl	$.L.str.43, %esi
	movl	$28, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp177:
# %bb.141:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit458
	movsd	-424(%rbp), %xmm0               # xmm0 = mem[0],zero
.Ltmp178:
	.cfi_escape 0x2e, 0x00
	movl	$_ZSt4cout, %edi
	movsd	%xmm0, -80(%rbp)                # 8-byte Spill
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp179:
# %bb.142:                              # %_ZNSolsEd.exit459
.Ltmp180:
	movq	%rax, %r14
	.cfi_escape 0x2e, 0x00
	movl	$.L.str.44, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp181:
# %bb.143:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit460
	movsd	.LCPI7_5(%rip), %xmm0           # xmm0 = mem[0],zero
	divsd	-80(%rbp), %xmm0                # 8-byte Folded Reload
.Ltmp182:
	.cfi_escape 0x2e, 0x00
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp183:
# %bb.144:                              # %_ZNSolsEd.exit461
.Ltmp184:
	.cfi_escape 0x2e, 0x00
	movl	$.L.str.45, %esi
	movl	$7, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp185:
# %bb.145:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit462.preheader
	cmpl	$0, -44(%rbp)
	jle	.LBB7_179
# %bb.146:                              # %.lr.ph589
	imull	$1216, -72(%rbp), %eax          # 4-byte Folded Reload
                                        # imm = 0x4C0
	cltq
	movq	%rax, -128(%rbp)                # 8-byte Spill
	xorl	%ebx, %ebx
	movq	-184(%rbp), %rax                # 8-byte Reload
	movq	%rax, -56(%rbp)                 # 8-byte Spill
	movq	-176(%rbp), %rax                # 8-byte Reload
	movq	%rax, -72(%rbp)                 # 8-byte Spill
	movq	-192(%rbp), %rax                # 8-byte Reload
	movq	%rax, -120(%rbp)                # 8-byte Spill
	movq	-240(%rbp), %r14                # 8-byte Reload
	movq	%r12, -112(%rbp)                # 8-byte Spill
.LBB7_147:                              # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_152 Depth 2
                                        #     Child Loop BB7_161 Depth 2
                                        #       Child Loop BB7_162 Depth 3
                                        #     Child Loop BB7_165 Depth 2
                                        #     Child Loop BB7_175 Depth 2
.Ltmp187:
	.cfi_escape 0x2e, 0x00
	movl	%ebx, %edi
	callq	hipSetDevice
.Ltmp188:
# %bb.148:                              #   in Loop: Header=BB7_147 Depth=1
	movq	-288(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx,8), %rdi
	movq	%rbx, %r15
	shlq	$4, %r15
	movq	-200(%rbp), %rax                # 8-byte Reload
	addq	%r15, %rax
	movq	%rax, -80(%rbp)                 # 8-byte Spill
	movq	(%rax,%r12,8), %rdx
.Ltmp189:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movq	%rdi, -64(%rbp)                 # 8-byte Spill
	movq	-128(%rbp), %r9                 # 8-byte Reload
	pushq	$2
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp190:
# %bb.149:                              #   in Loop: Header=BB7_147 Depth=1
	movq	-280(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx,8), %rdi
	movq	-232(%rbp), %rax                # 8-byte Reload
	leaq	(%rax,%r15), %r13
	movq	(%r13,%r12,8), %rdx
.Ltmp191:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movl	$1216, %r9d                     # imm = 0x4C0
	movq	%rdi, -88(%rbp)                 # 8-byte Spill
	pushq	$2
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp192:
# %bb.150:                              #   in Loop: Header=BB7_147 Depth=1
	movq	-272(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx,8), %rdi
	addq	-224(%rbp), %r15                # 8-byte Folded Reload
	movq	(%r15,%r12,8), %rdx
.Ltmp193:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movl	$1216, %r9d                     # imm = 0x4C0
	movq	%rdi, -104(%rbp)                # 8-byte Spill
	pushq	$2
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp194:
# %bb.151:                              # %.preheader521.preheader
                                        #   in Loop: Header=BB7_147 Depth=1
	movq	%rbx, -96(%rbp)                 # 8-byte Spill
	xorl	%ebx, %ebx
.LBB7_152:                              # %.preheader521
                                        #   Parent Loop BB7_147 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	-56(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%rbx), %rdi
	movq	-168(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx), %r10
	movl	$512, %eax                      # imm = 0x200
	xorl	%edx, %edx
	idivl	-44(%rbp)
	movslq	%eax, %r9
.Ltmp195:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movq	%r10, %rdx
	pushq	$2
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp196:
# %bb.153:                              #   in Loop: Header=BB7_152 Depth=2
	movq	-72(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%rbx), %rdi
	movq	-168(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx), %r10
	movl	$512, %eax                      # imm = 0x200
	xorl	%edx, %edx
	idivl	-44(%rbp)
	movslq	%eax, %r9
.Ltmp197:
	.cfi_escape 0x2e, 0x10
	subq	$8, %rsp
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$256, %r8d                      # imm = 0x100
	movq	%r10, %rdx
	pushq	$2
	callq	hipMemcpy2D
	addq	$16, %rsp
.Ltmp198:
# %bb.154:                              #   in Loop: Header=BB7_152 Depth=2
	movq	-120(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx), %rdi
	movq	(%r14,%rbx), %rsi
.Ltmp199:
	.cfi_escape 0x2e, 0x00
	movl	$4000, %edx                     # imm = 0xFA0
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp200:
# %bb.155:                              #   in Loop: Header=BB7_152 Depth=2
	addq	$8, %rbx
	cmpq	$24, %rbx
	jne	.LBB7_152
# %bb.156:                              #   in Loop: Header=BB7_147 Depth=1
	movq	-96(%rbp), %rbx                 # 8-byte Reload
	leaq	(,%rbx,8), %rax
	leaq	(%rax,%rax,2), %r9
	movq	-184(%rbp), %rax                # 8-byte Reload
	leaq	(%rax,%r9), %r8
	addq	-176(%rbp), %r9                 # 8-byte Folded Reload
	movl	-44(%rbp), %eax
.Ltmp202:
	.cfi_escape 0x2e, 0x10
	leaq	-968(%rbp), %rdi
	movq	-64(%rbp), %rsi                 # 8-byte Reload
	movq	-88(%rbp), %rdx                 # 8-byte Reload
	movq	-104(%rbp), %rcx                # 8-byte Reload
	pushq	%rbx
	pushq	%rax
	callq	_Z12WriteResultsRSoPfS0_S0_PS0_S1_fii
	addq	$16, %rsp
.Ltmp203:
# %bb.157:                              #   in Loop: Header=BB7_147 Depth=1
	movq	-968(%rbp), %rax
	movq	-24(%rax), %rdi
	leaq	-968(%rbp), %rax
	addq	%rax, %rdi
.Ltmp204:
	.cfi_escape 0x2e, 0x00
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp205:
# %bb.158:                              # %.noexc472
                                        #   in Loop: Header=BB7_147 Depth=1
.Ltmp206:
	.cfi_escape 0x2e, 0x00
	movsbl	%al, %esi
	leaq	-968(%rbp), %rdi
	callq	_ZNSo3putEc
.Ltmp207:
# %bb.159:                              # %.noexc473
                                        #   in Loop: Header=BB7_147 Depth=1
.Ltmp208:
	.cfi_escape 0x2e, 0x00
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp209:
# %bb.160:                              # %.preheader.preheader
                                        #   in Loop: Header=BB7_147 Depth=1
	leaq	(%rbx,%rbx,2), %rcx
	movq	-192(%rbp), %rax                # 8-byte Reload
	movq	%rcx, -64(%rbp)                 # 8-byte Spill
	leaq	(%rax,%rcx,8), %rax
	xorl	%ecx, %ecx
.LBB7_161:                              # %.preheader
                                        #   Parent Loop BB7_147 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB7_162 Depth 3
	movq	(%rax,%rcx,8), %rdx
	movq	-160(%rbp,%rcx,8), %rsi
	xorl	%edi, %edi
.LBB7_162:                              #   Parent Loop BB7_147 Depth=1
                                        #     Parent Loop BB7_161 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rdx,%rdi,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	addss	(%rsi,%rdi,4), %xmm0
	movss	%xmm0, (%rsi,%rdi,4)
	incq	%rdi
	cmpq	$1000, %rdi                     # imm = 0x3E8
	jne	.LBB7_162
# %bb.163:                              # %_ZNSolsEPFRSoS_E.exit466
                                        #   in Loop: Header=BB7_161 Depth=2
	incq	%rcx
	cmpq	$3, %rcx
	jne	.LBB7_161
# %bb.164:                              # %.preheader520.preheader
                                        #   in Loop: Header=BB7_147 Depth=1
	movb	$1, %bl
	xorl	%r12d, %r12d
.LBB7_165:                              # %.preheader520
                                        #   Parent Loop BB7_147 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	-80(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12,8), %rdi
.Ltmp210:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp211:
# %bb.166:                              #   in Loop: Header=BB7_165 Depth=2
	movq	(%r13,%r12,8), %rdi
.Ltmp212:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp213:
# %bb.167:                              #   in Loop: Header=BB7_165 Depth=2
	movq	(%r15,%r12,8), %rdi
.Ltmp214:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp215:
# %bb.168:                              #   in Loop: Header=BB7_165 Depth=2
	movl	$1, %r12d
	testb	$1, %bl
	movl	$0, %ebx
	jne	.LBB7_165
# %bb.169:                              #   in Loop: Header=BB7_147 Depth=1
.Ltmp217:
	.cfi_escape 0x2e, 0x00
	movq	-80(%rbp), %rdi                 # 8-byte Reload
	callq	hipFree
.Ltmp218:
	movq	-112(%rbp), %r12                # 8-byte Reload
	movq	-96(%rbp), %rbx                 # 8-byte Reload
# %bb.170:                              #   in Loop: Header=BB7_147 Depth=1
.Ltmp219:
	.cfi_escape 0x2e, 0x00
	movq	%r13, %rdi
	callq	hipFree
.Ltmp220:
# %bb.171:                              #   in Loop: Header=BB7_147 Depth=1
.Ltmp221:
	.cfi_escape 0x2e, 0x00
	movq	%r15, %rdi
	callq	hipFree
.Ltmp222:
# %bb.172:                              #   in Loop: Header=BB7_147 Depth=1
	movq	-208(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx,8), %rdi
.Ltmp223:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp224:
# %bb.173:                              #   in Loop: Header=BB7_147 Depth=1
	movq	-216(%rbp), %rax                # 8-byte Reload
	movq	(%rax,%rbx,8), %rdi
.Ltmp225:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp226:
# %bb.174:                              # %.preheader519.preheader
                                        #   in Loop: Header=BB7_147 Depth=1
	xorl	%ebx, %ebx
.LBB7_175:                              # %.preheader519
                                        #   Parent Loop BB7_147 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	(%r14,%rbx,8), %rdi
.Ltmp227:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp228:
# %bb.176:                              #   in Loop: Header=BB7_175 Depth=2
	incq	%rbx
	cmpq	$3, %rbx
	jne	.LBB7_175
# %bb.177:                              #   in Loop: Header=BB7_147 Depth=1
	movq	-240(%rbp), %rax                # 8-byte Reload
	movq	-64(%rbp), %rcx                 # 8-byte Reload
	leaq	(%rax,%rcx,8), %rdi
.Ltmp230:
	.cfi_escape 0x2e, 0x00
	callq	hipFree
.Ltmp231:
	movq	-96(%rbp), %rbx                 # 8-byte Reload
# %bb.178:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit462
                                        #   in Loop: Header=BB7_147 Depth=1
	incq	%rbx
	movslq	-44(%rbp), %rax
	addq	$24, %r14
	addq	$24, -120(%rbp)                 # 8-byte Folded Spill
	addq	$24, -72(%rbp)                  # 8-byte Folded Spill
	addq	$24, -168(%rbp)                 # 8-byte Folded Spill
	addq	$24, -56(%rbp)                  # 8-byte Folded Spill
	cmpq	%rax, %rbx
	jl	.LBB7_147
.LBB7_179:                              # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit462._crit_edge
	movq	-360(%rbp), %rsp                # 8-byte Reload
	movq	-352(%rbp), %rdi
	leaq	-336(%rbp), %rax
	cmpq	%rax, %rdi
	je	.LBB7_181
# %bb.180:                              # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i463
	.cfi_escape 0x2e, 0x00
	callq	_ZdlPv
.LBB7_181:                              # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit465
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rbx
	leaq	-1472(%rbp), %rdi
	movq	%rbx, -8(%rdi)
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE+24(%rip), %r14
	movq	-24(%rbx), %rax
	movq	%r14, -1480(%rbp,%rax)
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
	movl	$248, %r15d
	leaq	-1480(%rbp), %rdi
	addq	%r15, %rdi
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt8ios_baseD2Ev
	leaq	-1984(%rbp), %rdi
	movq	%rbx, -8(%rdi)
	movq	-24(%rbx), %rax
	movq	%r14, -1992(%rbp,%rax)
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
	leaq	-1992(%rbp), %rdi
	addq	%r15, %rdi
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt8ios_baseD2Ev
	leaq	-960(%rbp), %rdi
	movq	%rbx, -8(%rdi)
	movq	-24(%rbx), %rax
	movq	%r14, -968(%rbp,%rax)
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
	leaq	-968(%rbp), %rdi
	addq	%r15, %rdi
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt8ios_baseD2Ev
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.LBB7_196:
	.cfi_def_cfa %rbp, 16
.Ltmp38:
	movq	%rax, %rbx
	movq	-160(%rbp), %rdi
	cmpq	%r15, %rdi
	je	.LBB7_216
# %bb.197:                              # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i448
	.cfi_escape 0x2e, 0x00
	jmp	.LBB7_193
.LBB7_194:
.Ltmp28:
	movq	%rax, %rbx
	movq	-160(%rbp), %rdi
	cmpq	%r15, %rdi
	je	.LBB7_216
# %bb.195:                              # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i445
	.cfi_escape 0x2e, 0x00
	jmp	.LBB7_193
.LBB7_191:
.Ltmp18:
	movq	%rax, %rbx
	movq	-160(%rbp), %rdi
	cmpq	%r15, %rdi
	je	.LBB7_216
# %bb.192:                              # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i442
	.cfi_escape 0x2e, 0x00
	jmp	.LBB7_193
.LBB7_190:
.Ltmp8:
	movq	%rax, %rbx
	jmp	.LBB7_218
.LBB7_189:
.Ltmp5:
	movq	%rax, %rbx
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r14
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE+24(%rip), %r15
	jmp	.LBB7_219
.LBB7_188:
.Ltmp2:
	movq	%rax, %rbx
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r14
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE+24(%rip), %r15
	jmp	.LBB7_220
.LBB7_214:
.Ltmp175:
	jmp	.LBB7_215
.LBB7_199:
.Ltmp54:
	jmp	.LBB7_215
.LBB7_186:
.Ltmp35:
	movq	%rax, %rbx
	movq	-160(%rbp), %rdi
	cmpq	%r15, %rdi
	je	.LBB7_216
# %bb.187:                              # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i.i.i433
	.cfi_escape 0x2e, 0x00
	jmp	.LBB7_193
.LBB7_184:
.Ltmp25:
	movq	%rax, %rbx
	movq	-160(%rbp), %rdi
	cmpq	%r15, %rdi
	je	.LBB7_216
# %bb.185:                              # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i.i.i424
	.cfi_escape 0x2e, 0x00
	jmp	.LBB7_193
.LBB7_182:
.Ltmp15:
	movq	%rax, %rbx
	movq	-160(%rbp), %rdi
	cmpq	%r15, %rdi
	je	.LBB7_216
# %bb.183:                              # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i.i.i
	.cfi_escape 0x2e, 0x00
.LBB7_193:                              # %.body
	callq	_ZdlPv
	jmp	.LBB7_216
.LBB7_211:
.Ltmp186:
	jmp	.LBB7_215
.LBB7_198:
.Ltmp49:
	jmp	.LBB7_215
.LBB7_202:
.Ltmp122:
	jmp	.LBB7_215
.LBB7_210:
.Ltmp172:
	jmp	.LBB7_215
.LBB7_221:
.Ltmp117:
	jmp	.LBB7_215
.LBB7_222:
.Ltmp63:
	jmp	.LBB7_215
.LBB7_203:
.Ltmp145:
	jmp	.LBB7_215
.LBB7_212:
.Ltmp232:
	jmp	.LBB7_215
.LBB7_205:
.Ltmp159:
	jmp	.LBB7_215
.LBB7_206:
.Ltmp166:
	jmp	.LBB7_215
.LBB7_227:
.Ltmp229:
	jmp	.LBB7_215
.LBB7_209:
.Ltmp169:
	jmp	.LBB7_215
.LBB7_208:
.Ltmp235:
	jmp	.LBB7_215
.LBB7_226:
.Ltmp216:
	jmp	.LBB7_215
.LBB7_213:
.Ltmp201:
	jmp	.LBB7_215
.LBB7_200:
.Ltmp95:
	jmp	.LBB7_215
.LBB7_225:
.Ltmp88:
	jmp	.LBB7_215
.LBB7_224:
.Ltmp81:
	jmp	.LBB7_215
.LBB7_223:
.Ltmp70:
	jmp	.LBB7_215
.LBB7_204:
.Ltmp156:
	jmp	.LBB7_215
.LBB7_201:
.Ltmp108:
.LBB7_215:
	movq	%rax, %rbx
.LBB7_216:
	movq	-352(%rbp), %rdi
	leaq	-336(%rbp), %rax
	cmpq	%rax, %rdi
	je	.LBB7_218
# %bb.217:                              # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i467
	.cfi_escape 0x2e, 0x00
	callq	_ZdlPv
.LBB7_218:                              # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit469
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r14
	leaq	-1472(%rbp), %rdi
	movq	%r14, -8(%rdi)
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE+24(%rip), %r15
	movq	-24(%r14), %rax
	movq	%r15, -1480(%rbp,%rax)
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
	leaq	-1232(%rbp), %rdi
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt8ios_baseD2Ev
.LBB7_219:
	leaq	-1984(%rbp), %rdi
	movq	%r14, -8(%rdi)
	movq	-24(%r14), %rax
	movq	%r15, -1992(%rbp,%rax)
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
	leaq	-1744(%rbp), %rdi
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt8ios_baseD2Ev
.LBB7_220:
	leaq	-960(%rbp), %rdi
	movq	%r14, -8(%rdi)
	movq	-24(%r14), %rax
	movq	%r15, -968(%rbp,%rax)
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
	leaq	-720(%rbp), %rdi
	.cfi_escape 0x2e, 0x00
	callq	_ZNSt8ios_baseD2Ev
	.cfi_escape 0x2e, 0x00
	movq	%rbx, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end7:
	.size	main, .Lfunc_end7-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table7:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp4-.Ltmp3                  #   Call between .Ltmp3 and .Ltmp4
	.uleb128 .Ltmp5-.Lfunc_begin0           #     jumps to .Ltmp5
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp7-.Ltmp6                  #   Call between .Ltmp6 and .Ltmp7
	.uleb128 .Ltmp8-.Lfunc_begin0           #     jumps to .Ltmp8
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp9-.Lfunc_begin0           # >> Call Site 5 <<
	.uleb128 .Ltmp14-.Ltmp9                 #   Call between .Ltmp9 and .Ltmp14
	.uleb128 .Ltmp15-.Lfunc_begin0          #     jumps to .Ltmp15
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp16-.Lfunc_begin0          # >> Call Site 6 <<
	.uleb128 .Ltmp17-.Ltmp16                #   Call between .Ltmp16 and .Ltmp17
	.uleb128 .Ltmp18-.Lfunc_begin0          #     jumps to .Ltmp18
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp19-.Lfunc_begin0          # >> Call Site 7 <<
	.uleb128 .Ltmp24-.Ltmp19                #   Call between .Ltmp19 and .Ltmp24
	.uleb128 .Ltmp25-.Lfunc_begin0          #     jumps to .Ltmp25
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp26-.Lfunc_begin0          # >> Call Site 8 <<
	.uleb128 .Ltmp27-.Ltmp26                #   Call between .Ltmp26 and .Ltmp27
	.uleb128 .Ltmp28-.Lfunc_begin0          #     jumps to .Ltmp28
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp29-.Lfunc_begin0          # >> Call Site 9 <<
	.uleb128 .Ltmp34-.Ltmp29                #   Call between .Ltmp29 and .Ltmp34
	.uleb128 .Ltmp35-.Lfunc_begin0          #     jumps to .Ltmp35
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp36-.Lfunc_begin0          # >> Call Site 10 <<
	.uleb128 .Ltmp37-.Ltmp36                #   Call between .Ltmp36 and .Ltmp37
	.uleb128 .Ltmp38-.Lfunc_begin0          #     jumps to .Ltmp38
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp39-.Lfunc_begin0          # >> Call Site 11 <<
	.uleb128 .Ltmp48-.Ltmp39                #   Call between .Ltmp39 and .Ltmp48
	.uleb128 .Ltmp49-.Lfunc_begin0          #     jumps to .Ltmp49
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp50-.Lfunc_begin0          # >> Call Site 12 <<
	.uleb128 .Ltmp53-.Ltmp50                #   Call between .Ltmp50 and .Ltmp53
	.uleb128 .Ltmp54-.Lfunc_begin0          #     jumps to .Ltmp54
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp53-.Lfunc_begin0          # >> Call Site 13 <<
	.uleb128 .Ltmp55-.Ltmp53                #   Call between .Ltmp53 and .Ltmp55
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp55-.Lfunc_begin0          # >> Call Site 14 <<
	.uleb128 .Ltmp60-.Ltmp55                #   Call between .Ltmp55 and .Ltmp60
	.uleb128 .Ltmp117-.Lfunc_begin0         #     jumps to .Ltmp117
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp61-.Lfunc_begin0          # >> Call Site 15 <<
	.uleb128 .Ltmp62-.Ltmp61                #   Call between .Ltmp61 and .Ltmp62
	.uleb128 .Ltmp63-.Lfunc_begin0          #     jumps to .Ltmp63
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp64-.Lfunc_begin0          # >> Call Site 16 <<
	.uleb128 .Ltmp69-.Ltmp64                #   Call between .Ltmp64 and .Ltmp69
	.uleb128 .Ltmp70-.Lfunc_begin0          #     jumps to .Ltmp70
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp71-.Lfunc_begin0          # >> Call Site 17 <<
	.uleb128 .Ltmp74-.Ltmp71                #   Call between .Ltmp71 and .Ltmp74
	.uleb128 .Ltmp117-.Lfunc_begin0         #     jumps to .Ltmp117
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp75-.Lfunc_begin0          # >> Call Site 18 <<
	.uleb128 .Ltmp80-.Ltmp75                #   Call between .Ltmp75 and .Ltmp80
	.uleb128 .Ltmp81-.Lfunc_begin0          #     jumps to .Ltmp81
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp80-.Lfunc_begin0          # >> Call Site 19 <<
	.uleb128 .Ltmp82-.Ltmp80                #   Call between .Ltmp80 and .Ltmp82
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp82-.Lfunc_begin0          # >> Call Site 20 <<
	.uleb128 .Ltmp87-.Ltmp82                #   Call between .Ltmp82 and .Ltmp87
	.uleb128 .Ltmp88-.Lfunc_begin0          #     jumps to .Ltmp88
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp89-.Lfunc_begin0          # >> Call Site 21 <<
	.uleb128 .Ltmp94-.Ltmp89                #   Call between .Ltmp89 and .Ltmp94
	.uleb128 .Ltmp95-.Lfunc_begin0          #     jumps to .Ltmp95
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp96-.Lfunc_begin0          # >> Call Site 22 <<
	.uleb128 .Ltmp107-.Ltmp96               #   Call between .Ltmp96 and .Ltmp107
	.uleb128 .Ltmp108-.Lfunc_begin0         #     jumps to .Ltmp108
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp109-.Lfunc_begin0         # >> Call Site 23 <<
	.uleb128 .Ltmp116-.Ltmp109              #   Call between .Ltmp109 and .Ltmp116
	.uleb128 .Ltmp117-.Lfunc_begin0         #     jumps to .Ltmp117
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp118-.Lfunc_begin0         # >> Call Site 24 <<
	.uleb128 .Ltmp119-.Ltmp118              #   Call between .Ltmp118 and .Ltmp119
	.uleb128 .Ltmp175-.Lfunc_begin0         #     jumps to .Ltmp175
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp120-.Lfunc_begin0         # >> Call Site 25 <<
	.uleb128 .Ltmp121-.Ltmp120              #   Call between .Ltmp120 and .Ltmp121
	.uleb128 .Ltmp122-.Lfunc_begin0         #     jumps to .Ltmp122
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp123-.Lfunc_begin0         # >> Call Site 26 <<
	.uleb128 .Ltmp144-.Ltmp123              #   Call between .Ltmp123 and .Ltmp144
	.uleb128 .Ltmp145-.Lfunc_begin0         #     jumps to .Ltmp145
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp146-.Lfunc_begin0         # >> Call Site 27 <<
	.uleb128 .Ltmp155-.Ltmp146              #   Call between .Ltmp146 and .Ltmp155
	.uleb128 .Ltmp156-.Lfunc_begin0         #     jumps to .Ltmp156
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp157-.Lfunc_begin0         # >> Call Site 28 <<
	.uleb128 .Ltmp158-.Ltmp157              #   Call between .Ltmp157 and .Ltmp158
	.uleb128 .Ltmp159-.Lfunc_begin0         #     jumps to .Ltmp159
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp160-.Lfunc_begin0         # >> Call Site 29 <<
	.uleb128 .Ltmp165-.Ltmp160              #   Call between .Ltmp160 and .Ltmp165
	.uleb128 .Ltmp166-.Lfunc_begin0         #     jumps to .Ltmp166
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp233-.Lfunc_begin0         # >> Call Site 30 <<
	.uleb128 .Ltmp234-.Ltmp233              #   Call between .Ltmp233 and .Ltmp234
	.uleb128 .Ltmp235-.Lfunc_begin0         #     jumps to .Ltmp235
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp167-.Lfunc_begin0         # >> Call Site 31 <<
	.uleb128 .Ltmp168-.Ltmp167              #   Call between .Ltmp167 and .Ltmp168
	.uleb128 .Ltmp169-.Lfunc_begin0         #     jumps to .Ltmp169
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp170-.Lfunc_begin0         # >> Call Site 32 <<
	.uleb128 .Ltmp171-.Ltmp170              #   Call between .Ltmp170 and .Ltmp171
	.uleb128 .Ltmp172-.Lfunc_begin0         #     jumps to .Ltmp172
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp173-.Lfunc_begin0         # >> Call Site 33 <<
	.uleb128 .Ltmp174-.Ltmp173              #   Call between .Ltmp173 and .Ltmp174
	.uleb128 .Ltmp175-.Lfunc_begin0         #     jumps to .Ltmp175
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp176-.Lfunc_begin0         # >> Call Site 34 <<
	.uleb128 .Ltmp185-.Ltmp176              #   Call between .Ltmp176 and .Ltmp185
	.uleb128 .Ltmp186-.Lfunc_begin0         #     jumps to .Ltmp186
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp187-.Lfunc_begin0         # >> Call Site 35 <<
	.uleb128 .Ltmp194-.Ltmp187              #   Call between .Ltmp187 and .Ltmp194
	.uleb128 .Ltmp232-.Lfunc_begin0         #     jumps to .Ltmp232
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp195-.Lfunc_begin0         # >> Call Site 36 <<
	.uleb128 .Ltmp200-.Ltmp195              #   Call between .Ltmp195 and .Ltmp200
	.uleb128 .Ltmp201-.Lfunc_begin0         #     jumps to .Ltmp201
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp202-.Lfunc_begin0         # >> Call Site 37 <<
	.uleb128 .Ltmp209-.Ltmp202              #   Call between .Ltmp202 and .Ltmp209
	.uleb128 .Ltmp232-.Lfunc_begin0         #     jumps to .Ltmp232
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp210-.Lfunc_begin0         # >> Call Site 38 <<
	.uleb128 .Ltmp215-.Ltmp210              #   Call between .Ltmp210 and .Ltmp215
	.uleb128 .Ltmp216-.Lfunc_begin0         #     jumps to .Ltmp216
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp217-.Lfunc_begin0         # >> Call Site 39 <<
	.uleb128 .Ltmp226-.Ltmp217              #   Call between .Ltmp217 and .Ltmp226
	.uleb128 .Ltmp232-.Lfunc_begin0         #     jumps to .Ltmp232
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp227-.Lfunc_begin0         # >> Call Site 40 <<
	.uleb128 .Ltmp228-.Ltmp227              #   Call between .Ltmp227 and .Ltmp228
	.uleb128 .Ltmp229-.Lfunc_begin0         #     jumps to .Ltmp229
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp230-.Lfunc_begin0         # >> Call Site 41 <<
	.uleb128 .Ltmp231-.Ltmp230              #   Call between .Ltmp230 and .Ltmp231
	.uleb128 .Ltmp232-.Lfunc_begin0         #     jumps to .Ltmp232
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp231-.Lfunc_begin0         # >> Call Site 42 <<
	.uleb128 .Lfunc_end7-.Ltmp231           #   Call between .Ltmp231 and .Lfunc_end7
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.section	.text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
	.weak	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
	.p2align	1, 0x90
	.type	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %rbx
	subq	%rsi, %r14
	movq	%r14, (%rsp)
	cmpq	$15, %r14
	jbe	.LBB8_1
# %bb.2:
	movq	%rsp, %r12
	movq	%rbx, %rdi
	movq	%r12, %rsi
	xorl	%edx, %edx
	callq	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm
	movq	%rax, (%rbx)
	movq	(%r12), %rcx
	movq	%rcx, 16(%rbx)
	jmp	.LBB8_3
.LBB8_1:                                # %._crit_edge
	movq	(%rbx), %rax
.LBB8_3:
	testq	%r14, %r14
	je	.LBB8_7
# %bb.4:
	cmpq	$1, %r14
	jne	.LBB8_6
# %bb.5:
	movb	(%r15), %cl
	movb	%cl, (%rax)
	jmp	.LBB8_7
.LBB8_6:
	movq	%rax, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	callq	memcpy@PLT
.LBB8_7:                                # %_ZZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tagEN6_GuardD2Ev.exit
	movq	(%rsp), %rax
	movq	%rax, 8(%rbx)
	movq	(%rbx), %rcx
	movb	$0, (%rcx,%rax)
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .Lfunc_end8-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10initializePfmiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10update_topPfS_S_S_fmii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10update_botPfS_S_S_fmii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10update_innPfS_S_S_fmiiPS_S0_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10initializePfmiii,@object    # @_Z10initializePfmiii
	.section	.rodata,"a",@progbits
	.globl	_Z10initializePfmiii
	.p2align	3, 0x0
_Z10initializePfmiii:
	.quad	_Z25__device_stub__initializePfmiii
	.size	_Z10initializePfmiii, 8

	.type	_Z10update_topPfS_S_S_fmii,@object # @_Z10update_topPfS_S_S_fmii
	.globl	_Z10update_topPfS_S_S_fmii
	.p2align	3, 0x0
_Z10update_topPfS_S_S_fmii:
	.quad	_Z25__device_stub__update_topPfS_S_S_fmii
	.size	_Z10update_topPfS_S_S_fmii, 8

	.type	_Z10update_botPfS_S_S_fmii,@object # @_Z10update_botPfS_S_S_fmii
	.globl	_Z10update_botPfS_S_S_fmii
	.p2align	3, 0x0
_Z10update_botPfS_S_S_fmii:
	.quad	_Z25__device_stub__update_botPfS_S_S_fmii
	.size	_Z10update_botPfS_S_S_fmii, 8

	.type	_Z10update_innPfS_S_S_fmiiPS_S0_i,@object # @_Z10update_innPfS_S_S_fmiiPS_S0_i
	.globl	_Z10update_innPfS_S_S_fmiiPS_S0_i
	.p2align	3, 0x0
_Z10update_innPfS_S_S_fmiiPS_S0_i:
	.quad	_Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i
	.size	_Z10update_innPfS_S_S_fmiiPS_S0_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"VARIABLES = \"X\",\"Y\",\"Z\",\"u\",\"v\",\"w\",\"rho\",\"velAv[0]\",\"velAv[1]\",\"ufluc\",\"vfluc\"\n"
	.size	.L.str, 81

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"ZONE F=POINT, I="
	.size	.L.str.1, 17

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	", J="
	.size	.L.str.2, 5

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	", K="
	.size	.L.str.3, 5

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\n"
	.size	.L.str.4, 2

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	", "
	.size	.L.str.5, 3

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	","
	.size	.L.str.6, 2

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Base domain size \t"
	.size	.L.str.7, 19

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"x"
	.size	.L.str.8, 2

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Base blocksize: \t"
	.size	.L.str.9, 18

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Obst1 location: \t("
	.size	.L.str.10, 19

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	")"
	.size	.L.str.11, 2

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Obst1 radius: \t"
	.size	.L.str.12, 16

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Obst2 location: \t("
	.size	.L.str.13, 19

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"Obst2 radius: \t"
	.size	.L.str.14, 16

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"RE: \t"
	.size	.L.str.15, 6

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"UMAX: \t"
	.size	.L.str.16, 8

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"omega \t: "
	.size	.L.str.17, 10

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"TMAX: \t"
	.size	.L.str.18, 8

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"STARTF: \t"
	.size	.L.str.19, 10

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"START_VELAV: \t"
	.size	.L.str.20, 15

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"START_VELFLUC: \t"
	.size	.L.str.21, 17

	.type	.L.str.22,@object               # @.str.22
.L.str.22:
	.asciz	"REFINEMENT: \t"
	.size	.L.str.22, 14

	.type	.L.str.23,@object               # @.str.23
.L.str.23:
	.asciz	"MODEL: \t"
	.size	.L.str.23, 9

	.type	.L.str.24,@object               # @.str.24
.L.str.24:
	.asciz	"MRT"
	.size	.L.str.24, 4

	.type	.L.str.25,@object               # @.str.25
.L.str.25:
	.asciz	"Smagorinski LES: \t"
	.size	.L.str.25, 19

	.type	.L.str.26,@object               # @.str.26
.L.str.26:
	.asciz	"CS: \t"
	.size	.L.str.26, 6

	.type	.L.str.27,@object               # @.str.27
.L.str.27:
	.asciz	"LR domain size \t"
	.size	.L.str.27, 17

	.type	.L.str.28,@object               # @.str.28
.L.str.28:
	.asciz	"LR factor \t"
	.size	.L.str.28, 12

	.type	.L.str.29,@object               # @.str.29
.L.str.29:
	.asciz	"LR location \t"
	.size	.L.str.29, 14

	.type	.L.str.30,@object               # @.str.30
.L.str.30:
	.asciz	"LR blocksize: \t"
	.size	.L.str.30, 16

	.type	.L.str.31,@object               # @.str.31
.L.str.31:
	.asciz	"omega in LR \t: "
	.size	.L.str.31, 16

	.type	.L.str.32,@object               # @.str.32
.L.str.32:
	.asciz	"GPUs per node \t: "
	.size	.L.str.32, 18

	.type	.L.str.33,@object               # @.str.33
.L.str.33:
	.asciz	"number of GPUs: "
	.size	.L.str.33, 17

	.type	.L.str.34,@object               # @.str.34
.L.str.34:
	.asciz	"test_new"
	.size	.L.str.34, 9

	.type	.L.str.35,@object               # @.str.35
.L.str.35:
	.asciz	".dat"
	.size	.L.str.35, 5

	.type	.L.str.36,@object               # @.str.36
.L.str.36:
	.asciz	".force"
	.size	.L.str.36, 7

	.type	.L.str.37,@object               # @.str.37
.L.str.37:
	.asciz	".inputs"
	.size	.L.str.37, 8

	.type	.L.str.38,@object               # @.str.38
.L.str.38:
	.asciz	"Pitch (in elements): "
	.size	.L.str.38, 22

	.type	.L.str.39,@object               # @.str.39
.L.str.39:
	.asciz	"Device memory used for dev"
	.size	.L.str.39, 27

	.type	.L.str.40,@object               # @.str.40
.L.str.40:
	.asciz	" : "
	.size	.L.str.40, 4

	.type	.L.str.41,@object               # @.str.41
.L.str.41:
	.asciz	" GB\n"
	.size	.L.str.41, 5

	.type	.L.str.42,@object               # @.str.42
.L.str.42:
	.asciz	"Device memory available for dev"
	.size	.L.str.42, 32

	.type	.L.str.43,@object               # @.str.43
.L.str.43:
	.asciz	"Time taken for main kernel: "
	.size	.L.str.43, 29

	.type	.L.str.44,@object               # @.str.44
.L.str.44:
	.asciz	" ("
	.size	.L.str.44, 3

	.type	.L.str.45,@object               # @.str.45
.L.str.45:
	.asciz	"MLUPS)\n"
	.size	.L.str.45, 8

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10initializePfmiii"
	.size	.L__unnamed_1, 21

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10update_topPfS_S_S_fmii"
	.size	.L__unnamed_2, 27

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10update_botPfS_S_S_fmii"
	.size	.L__unnamed_3, 27

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z10update_innPfS_S_S_fmiiPS_S0_i"
	.size	.L__unnamed_4, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__initializePfmiii
	.addrsig_sym _Z25__device_stub__update_topPfS_S_S_fmii
	.addrsig_sym _Z25__device_stub__update_botPfS_S_S_fmii
	.addrsig_sym _Z25__device_stub__update_innPfS_S_S_fmiiPS_S0_i
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z10initializePfmiii
	.addrsig_sym _Z10update_topPfS_S_S_fmii
	.addrsig_sym _Z10update_botPfS_S_S_fmii
	.addrsig_sym _Z10update_innPfS_S_S_fmiiPS_S0_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10initializePfmiii    ; -- Begin function _Z10initializePfmiii
	.globl	_Z10initializePfmiii
	.p2align	8
	.type	_Z10initializePfmiii,@function
_Z10initializePfmiii:                   ; @_Z10initializePfmiii
; %bb.0:
	s_clause 0x2
	s_load_b64 s[6:7], s[0:1], 0x2c
	s_load_b32 s4, s[0:1], 0x10
	s_load_b32 s5, s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	s_mov_b32 s11, 0x3dcccccd
	s_mov_b32 s8, 0xbc4d5033
	s_mov_b32 s12, 0xbb969026
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s6, 16
	s_and_b32 s3, s6, 0xffff
	s_ashr_i32 s6, s4, 31
	s_and_b32 s7, s7, 0xffff
	s_cmp_gt_i32 s5, 0
	s_mov_b32 s5, 0
	s_cselect_b32 vcc_lo, -1, 0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v0, v0, 20, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s14, s2, v[1:2]
	v_mad_u64_u32 v[4:5], null, s13, s3, v[2:3]
	v_cvt_f32_i32_e32 v1, v3
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s13, 0xbdcccccd
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v2, v4
	v_dual_fmaak_f32 v5, 0.5, v1, 0x413c0000 :: v_dual_fmaak_f32 v6, 0.5, v2, 0x413c0000
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v1, v5 :: v_dual_cndmask_b32 v6, v2, v6
	v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
	v_add_f32_e32 v2, 0xc1bc0000, v5
	s_mov_b32 s7, 0x41980000
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v0, 0xc1bc0000, v6
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s6, s2, s6
	s_mul_i32 s3, s3, s4
	v_cmp_lt_f32_e64 s10, |v2|, 4.0
	v_cmp_lt_f32_e64 s9, |v0|, 4.0
	v_lshl_add_u32 v0, v1, 6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 s9, s9, s10
	v_mad_u64_u32 v[12:13], null, v0, s2, v[4:5]
	v_cndmask_b32_e64 v8, 0x3c23d70a, 0, s9
	v_cndmask_b32_e64 v9, 0x3da3d70a, 0, s9
	v_cndmask_b32_e64 v11, 0x3bd1b717, 0, s9
	v_cndmask_b32_e64 v0, 0x3bd4fdf3, 0, s9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v1, v8, v8
	v_dual_fmaak_f32 v15, s13, v8, 0x3d579436 :: v_dual_fmaak_f32 v20, s13, v9, 0x3d579436
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v16, s7, v0, 0xc1300000
	v_mul_f32_e32 v19, 0x3daaaaab, v11
	v_fma_f32 v21, v8, v1, -v11
	s_delay_alu instid0(VALU_DEP_4)
	v_fmamk_f32 v6, v9, 0x3dcccccd, v15
	v_mul_f32_e32 v18, 0xbf2aaaab, v9
	v_fmaak_f32 v10, s11, v9, 0x3d579436
	v_fmamk_f32 v4, v16, 0xbb969026, v20
	v_fmamk_f32 v24, v21, 0x3ce38e39, v19
	v_mul_f32_e32 v17, 0x40f14514, v0
	v_fmac_f32_e32 v6, 0x3b5b0037, v16
	v_fma_f32 v25, 0xbf2aaaab, v8, -v18
	v_fmamk_f32 v2, v16, 0xbb969026, v10
	v_dual_fmamk_f32 v23, v8, 0xbf2aaaab, v18 :: v_dual_add_f32 v26, 0, v24
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v6, 0x3b820821, v17
	v_fmamk_f32 v3, v16, 0xbb969026, v15
	v_mul_f32_e32 v13, 0xbf2aaaab, v8
	v_fmaak_f32 v0, s8, v16, 0x3d579436
	v_fmaak_f32 v27, s12, v16, 0x3d579436
	v_fmac_f32_e32 v6, 0xbccccccd, v25
	s_mul_hi_u32 s7, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s6, s7, s6
	v_add_f32_e32 v6, v24, v6
	v_fmac_f32_e32 v2, 0xbc820821, v17
	v_fmamk_f32 v7, v9, 0xbdcccccd, v15
	v_fmac_f32_e32 v4, 0xbc820821, v17
	v_fmac_f32_e32 v3, 0xbc820821, v17
	v_fmamk_f32 v0, v17, 0x3d430c31, v0
	v_fmac_f32_e32 v2, 0xbdcccccd, v18
	v_fmac_f32_e32 v7, 0x3b5b0037, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v4, 0x3dcccccd, v18 :: v_dual_fmac_f32 v3, 0x3dcccccd, v13
	v_fmac_f32_e32 v27, 0xbc820821, v17
	v_fmac_f32_e32 v2, 0xbce38e39, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v7, 0x3b820821, v17
	v_fmac_f32_e32 v4, 0xbce38e39, v21
	v_fmac_f32_e32 v3, 0x3d638e39, v21
	v_fmac_f32_e32 v27, 0xbce38e39, v21
	v_fmac_f32_e32 v2, 0x3daaaaab, v11
	v_fmac_f32_e32 v7, 0xbccccccd, v23
	v_fmaak_f32 v14, s11, v8, 0x3d579436
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v4, 0x3daaaaab, v11 :: v_dual_add_f32 v7, v7, v26
	v_fmamk_f32 v5, v9, 0x3dcccccd, v14
	v_fmamk_f32 v1, v16, 0xbb969026, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v5, 0x3b5b0037, v16
	v_fmac_f32_e32 v1, 0xbc820821, v17
	v_fmamk_f32 v22, v9, 0xbdcccccd, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v5, 0x3b820821, v17
	v_fmac_f32_e32 v1, 0xbdcccccd, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v5, 0x3ccccccd, v23
	v_fmac_f32_e32 v1, 0x3d638e39, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v26
	s_clause 0x1
	scratch_store_b128 off, v[0:3], off offset:16
	scratch_store_b128 off, v[4:7], off offset:32
	v_fma_f32 v1, 0x3ce38e39, v21, -v19
	v_fmamk_f32 v3, v11, 0xbdaaaaab, v27
	v_fma_f32 v5, 0xbf2aaaab, v8, 0
	v_fma_f32 v8, 0xbf2aaaab, v9, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_add_f32 v11, 0, v1 :: v_dual_fmac_f32 v14, 0x3b5b0037, v16
	v_fmac_f32_e32 v10, 0x3b5b0037, v16
	v_fmac_f32_e32 v15, 0x3b5b0037, v16
	v_fmac_f32_e32 v20, 0x3b5b0037, v16
	v_fmac_f32_e32 v22, 0x3b5b0037, v16
	v_fmac_f32_e32 v14, 0x3b820821, v17
	v_fmac_f32_e32 v10, 0x3b820821, v17
	v_fmac_f32_e32 v15, 0x3b820821, v17
	v_fmac_f32_e32 v20, 0x3b820821, v17
	v_fma_f32 v16, 0xbd638e39, v21, 0
	v_fmamk_f32 v0, v13, 0x3ccccccd, v14
	v_fmamk_f32 v6, v18, 0x3ccccccd, v10
	v_fmamk_f32 v9, v5, 0xbccccccd, v15
	v_fmac_f32_e32 v14, 0x3ccccccd, v5
	v_fmac_f32_e32 v15, 0xbccccccd, v13
	v_ashrrev_i32_e32 v13, 31, v12
	v_fmac_f32_e32 v22, 0x3b820821, v17
	v_fmamk_f32 v7, v8, 0xbccccccd, v20
	v_add_f32_e32 v4, v0, v11
	v_add_f32_e32 v5, v16, v6
	v_fmac_f32_e32 v20, 0xbccccccd, v18
	v_add_f32_e32 v6, v1, v9
	v_add_f32_e32 v9, v1, v14
	v_lshlrev_b64 v[0:1], 2, v[12:13]
	v_fmac_f32_e32 v22, 0x3ccccccd, v25
	v_dual_fmac_f32 v10, 0x3ccccccd, v8 :: v_dual_add_f32 v11, v15, v11
	v_dual_add_f32 v12, v16, v20 :: v_dual_fmac_f32 v7, 0xbd638e39, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_f32_e32 v2, v24, v22
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v10, 0xbd638e39, v21
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_mov_b32_e32 v8, v3
	s_add_i32 s1, s6, s3
	s_mul_i32 s0, s2, s4
	s_clause 0x1
	scratch_store_b128 off, v[2:5], off offset:48
	scratch_store_b128 off, v[6:9], off offset:64
	s_lshl_b64 s[0:1], s[0:1], 8
	scratch_store_b96 off, v[10:12], off offset:80
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s2, s5, 16
	s_add_i32 s5, s5, 4
	scratch_load_b32 v2, off, s2
	s_cmpk_eq_i32 s5, 0x4c
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10initializePfmiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 96
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10initializePfmiii, .Lfunc_end0-_Z10initializePfmiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1196
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 96
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z10update_topPfS_S_S_fmii ; -- Begin function _Z10update_topPfS_S_S_fmii
	.globl	_Z10update_topPfS_S_S_fmii
	.p2align	8
	.type	_Z10update_topPfS_S_S_fmii,@function
_Z10update_topPfS_S_S_fmii:             ; @_Z10update_topPfS_S_S_fmii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x44
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
                                        ; implicit-def: $sgpr4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	v_mad_u64_u32 v[38:39], null, s14, s3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v38
	v_add_f32_e32 v1, 0xc1bc0000, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[31:32], null, s15, s2, v[0:1]
	v_cmp_nlt_f32_e64 s3, |v1|, 4.0
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_f32_e64 |v1|, 4.0
; %bb.1:
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v0, v31
	s_and_not1_b32 s3, s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, 0xc1bc0000, v0
	v_cmp_nlt_f32_e64 s4, |v0|, 4.0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s5, s4, exec_lo
	s_mov_b32 s4, 10
	s_or_b32 s3, s3, s5
; %bb.2:                                ; %Flow653
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v46, s4
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB1_12
; %bb.3:                                ; %NodeBlock
	s_mov_b32 s3, 0
	s_mov_b32 s5, exec_lo
                                        ; implicit-def: $sgpr4
	v_cmpx_lt_i32_e32 62, v31
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB1_7
; %bb.4:                                ; %LeafBlock581
	s_mov_b32 s3, -1
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $sgpr4
	v_cmpx_eq_u32_e32 63, v31
; %bb.5:
	s_movk_i32 s4, 0x64
	s_xor_b32 s3, exec_lo, -1
; %bb.6:                                ; %Flow648
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, exec_lo
.LBB1_7:                                ; %Flow647
	s_or_saveexec_b32 s5, s5
	v_mov_b32_e32 v46, s4
	s_xor_b32 exec_lo, exec_lo, s5
; %bb.8:                                ; %LeafBlock
	v_cmp_ne_u32_e32 vcc_lo, 0, v31
	v_mov_b32_e32 v46, 0xc8
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s3, s4
; %bb.9:                                ; %Flow649
	s_or_b32 exec_lo, exec_lo, s5
	s_and_saveexec_b32 s4, s3
; %bb.10:
	v_cmp_eq_u32_e32 vcc_lo, 63, v38
	v_cndmask_b32_e64 v0, 0, 25, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v38
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v46, 26, v0, vcc_lo
; %bb.11:                               ; %Flow650
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_12:                               ; %Flow654
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x28
	s_load_b256 s[4:11], s[0:1], 0x0
	v_add_nc_u32_e32 v3, 0x7f, v31
	v_add_nc_u32_e32 v4, 0x101, v31
                                        ; implicit-def: $vgpr36
	v_add_nc_u32_e32 v18, 1, v31
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s20, s12, 0x4c0
	s_lshl_b64 s[16:17], s[12:13], 7
	s_lshl_b64 s[18:19], s[12:13], 6
	s_add_i32 s13, s20, -1
	v_add_nc_u32_e32 v0, 64, v31
	v_add_nc_u32_e32 v1, -1, v38
	v_add_nc_u32_e32 v2, 1, v38
	s_mul_i32 s17, s12, 0xc0
	v_mad_u64_u32 v[42:43], null, v31, s12, v[38:39]
	v_mul_lo_u32 v45, v0, s12
	v_mul_lo_u32 v0, v3, s12
	v_mul_lo_u32 v14, v4, s12
	s_lshl_b32 s2, s15, 6
	s_mul_i32 s19, s15, 0x240
	s_sub_i32 s3, s2, 64
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v43, 31, v42
	s_lshl_b32 s21, s15, 7
	v_add_nc_u32_e32 v5, v1, v45
	v_add_nc_u32_e32 v44, s16, v45
	v_add_nc_u32_e32 v6, v38, v0
	v_add_nc_u32_e32 v0, s17, v0
	v_lshlrev_b64 v[3:4], 2, v[42:43]
	v_max_i32_e32 v5, 0, v5
	v_add_nc_u32_e32 v7, v2, v44
	v_max_i32_e32 v6, 0, v6
	v_add_nc_u32_e32 v8, v1, v0
	v_add_nc_u32_e32 v17, s17, v14
	v_cmp_gt_i32_e32 vcc_lo, s20, v5
	v_max_i32_e32 v9, 0, v7
	v_add_nc_u32_e32 v15, v38, v14
	v_max_i32_e32 v8, 0, v8
	v_cndmask_b32_e32 v5, s13, v5, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v6
	v_dual_cndmask_b32 v7, s13, v6 :: v_dual_add_nc_u32 v20, -1, v31
	v_cmp_gt_i32_e32 vcc_lo, s20, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	v_cndmask_b32_e32 v9, s13, v9, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v8
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add3_u32 v0, v0, s18, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v10, 31, v9
	v_cndmask_b32_e32 v11, s13, v8, vcc_lo
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_max_i32_e32 v0, 0, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_ashrrev_i32_e32 v8, 31, v7
	v_cndmask_b32_e32 v13, s13, v0, vcc_lo
	v_max_i32_e32 v0, 0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_dual_cndmask_b32 v15, s13, v0 :: v_dual_add_nc_u32 v0, v2, v17
	v_ashrrev_i32_e32 v12, 31, v11
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_max_i32_e32 v0, 0, v0
	v_ashrrev_i32_e32 v16, 31, v15
	v_add_co_u32 v21, vcc_lo, s6, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v22, vcc_lo, s7, v12, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[11:12], 2, v[15:16]
	v_cndmask_b32_e32 v15, s13, v0, vcc_lo
	v_add3_u32 v0, v17, s18, v1
	v_add_co_u32 v23, vcc_lo, s6, v13
	v_add_co_ci_u32_e32 v24, vcc_lo, s7, v14, vcc_lo
	v_max_i32_e32 v0, 0, v0
	v_ashrrev_i32_e32 v16, 31, v15
	v_add_co_u32 v25, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v26, vcc_lo, s7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_lshlrev_b64 v[11:12], 2, v[15:16]
	v_cndmask_b32_e32 v16, s13, v0, vcc_lo
	v_add3_u32 v0, s19, s3, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v27, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[11:12], null, v0, s12, v[38:39]
	v_add_nc_u32_e32 v0, s2, v0
	s_clause 0x7
	global_load_b32 v12, v[3:4], off
	global_load_b32 v13, v[5:6], off
	global_load_b32 v15, v[9:10], off
	global_load_b32 v14, v[7:8], off
	global_load_b32 v5, v[21:22], off
	global_load_b32 v6, v[23:24], off
	global_load_b32 v4, v[25:26], off
	global_load_b32 v7, v[27:28], off
	v_ashrrev_i32_e32 v17, 31, v16
	s_mul_i32 s2, s15, 0x2c0
	s_mul_i32 s19, s20, s15
	s_add_i32 s2, s2, s3
	v_max_i32_e32 v3, 0, v11
	v_mad_u64_u32 v[10:11], null, v0, s12, v[1:2]
	v_lshlrev_b64 v[8:9], 2, v[16:17]
	v_add_nc_u32_e32 v17, s2, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s19, v3
	s_add_i32 s3, s19, -1
	v_add_nc_u32_e32 v0, s21, v0
	v_cndmask_b32_e32 v16, s3, v3, vcc_lo
	v_max_i32_e32 v3, 0, v10
	v_mad_u64_u32 v[10:11], null, v17, s12, v[38:39]
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s19, v3
	v_mad_u64_u32 v[23:24], null, v0, s12, v[2:3]
	v_ashrrev_i32_e32 v17, 31, v16
	global_load_b32 v0, v[8:9], off
	v_cndmask_b32_e32 v21, s3, v3, vcc_lo
	v_max_i32_e32 v3, 0, v10
	v_add3_u32 v11, s2, s21, v18
	v_lshlrev_b64 v[8:9], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v22, 31, v21
	v_cmp_gt_i32_e32 vcc_lo, s19, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[16:17], null, v11, s12, v[38:39]
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	v_cndmask_b32_e32 v10, s3, v3, vcc_lo
	v_max_i32_e32 v3, 0, v23
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s19, v3
	v_max_i32_e32 v19, 0, v16
	v_ashrrev_i32_e32 v11, 31, v10
	v_cndmask_b32_e32 v23, s3, v3, vcc_lo
	v_add_co_u32 v3, s2, 0x380, v31
	v_add_co_ci_u32_e64 v16, null, 0, 0, s2
	v_add_co_u32 v21, vcc_lo, s8, v21
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[16:17], null, v3, s12, 0
	v_add_co_ci_u32_e32 v22, vcc_lo, s9, v22, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s19, v19
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_mov_b32 s2, 0
	v_add_nc_u32_e32 v3, v38, v16
	v_cndmask_b32_e32 v25, s3, v19, vcc_lo
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	v_add_co_u32 v43, null, v16, s18
	v_add_co_u32 v10, vcc_lo, s8, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v26, 31, v25
	v_max_i32_e32 v3, 0, v3
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	v_add_co_u32 v16, vcc_lo, s8, v23
	v_add_nc_u32_e32 v1, v1, v43
	v_add_nc_u32_e32 v19, 0x3ff, v31
	v_add_co_ci_u32_e32 v17, vcc_lo, s9, v24, vcc_lo
	v_lshlrev_b64 v[23:24], 2, v[25:26]
	v_cmp_gt_i32_e32 vcc_lo, s20, v3
	v_max_i32_e32 v1, 0, v1
	v_mad_u64_u32 v[27:28], null, v19, s12, v[38:39]
	v_add_co_u32 v39, null, v43, s16
	v_cndmask_b32_e32 v25, s13, v3, vcc_lo
	v_add_co_u32 v23, vcc_lo, s8, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v2, v2, v39
	v_add_co_ci_u32_e32 v24, vcc_lo, s9, v24, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v1
	v_max_i32_e32 v3, 0, v27
	v_max_i32_e32 v19, 0, v2
	v_ashrrev_i32_e32 v26, 31, v25
	s_add_i32 s3, s14, 1
	v_cndmask_b32_e32 v27, s13, v1, vcc_lo
	v_add_nc_u32_e32 v1, 0x481, v31
	v_cmp_gt_i32_e32 vcc_lo, s20, v3
	v_lshlrev_b64 v[40:41], 2, v[25:26]
	s_add_i32 s8, s15, 2
	v_ashrrev_i32_e32 v28, 31, v27
	v_mad_u64_u32 v[32:33], null, v1, s12, v[38:39]
	v_cndmask_b32_e32 v29, s13, v3, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v19
	s_clause 0x4
	global_load_b32 v1, v[8:9], off
	global_load_b32 v2, v[21:22], off
	global_load_b32 v3, v[10:11], off
	global_load_b32 v8, v[16:17], off
	global_load_b32 v9, v[23:24], off
	v_lshlrev_b64 v[21:22], 2, v[27:28]
	s_mul_i32 s8, s8, s3
	v_ashrrev_i32_e32 v30, 31, v29
	v_cndmask_b32_e32 v10, s13, v19, vcc_lo
	v_max_i32_e32 v19, 0, v32
	v_add_co_u32 v16, vcc_lo, s10, v40
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s20, v19
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[23:24], 2, v[29:30]
	s_add_i32 s8, s8, -1
	s_mov_b32 s14, 0
	v_cndmask_b32_e32 v25, s13, v19, vcc_lo
	v_add_co_u32 v21, vcc_lo, s10, v21
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_ci_u32_e32 v22, vcc_lo, s11, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v26, 31, v25
	v_add_co_u32 v23, vcc_lo, s10, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s11, v24, vcc_lo
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	v_add_co_u32 v27, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v28, vcc_lo, s11, v11, vcc_lo
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v25, vcc_lo, s10, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, s11, v26, vcc_lo
	s_clause 0x4
	global_load_b32 v10, v[16:17], off
	global_load_b32 v11, v[21:22], off
	global_load_b32 v32, v[23:24], off
	global_load_b32 v33, v[27:28], off
	global_load_b32 v34, v[25:26], off
	s_mov_b32 s11, 0
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
	s_waitcnt vmcnt(15)
	scratch_store_b128 off, v[12:15], off offset:16
	s_waitcnt vmcnt(11)
	scratch_store_b128 off, v[4:7], off offset:32
	s_waitcnt vmcnt(7)
	scratch_store_b128 off, v[0:3], off offset:48
	s_waitcnt vmcnt(3)
	scratch_store_b128 off, v[8:11], off offset:64
	s_waitcnt vmcnt(0)
	scratch_store_b96 off, v[32:34], off offset:80
	v_cmpx_lt_i32_e32 25, v46
	s_xor_b32 s9, exec_lo, s3
	s_cbranch_execz .LBB1_58
; %bb.13:                               ; %NodeBlock597
	s_mov_b32 s3, 0
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	v_cmpx_lt_i32_e32 0x63, v46
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB1_29
; %bb.14:                               ; %NodeBlock595
	s_mov_b32 s15, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	v_cmpx_lt_i32_e32 0xc7, v46
	s_xor_b32 s15, exec_lo, s15
	s_cbranch_execz .LBB1_22
; %bb.15:                               ; %.preheader394.preheader
	v_mad_u64_u32 v[16:17], null, v18, s12, v[38:39]
	s_lshl_b32 s3, s12, 6
.LBB1_16:                               ; %.preheader394
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_max_i32_e32 v17, 0, v16
	v_add_nc_u32_e32 v16, s3, v16
	s_add_i32 s11, s10, 16
	s_add_i32 s10, s10, 4
	s_cmpk_eq_i32 s10, 0x4c
	v_cmp_gt_i32_e32 vcc_lo, s20, v17
	v_cndmask_b32_e32 v17, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, s6, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
	global_load_b32 v17, v[17:18], off
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v17, s11
	s_cbranch_scc0 .LBB1_16
; %bb.17:
	s_clause 0x4
	scratch_load_b128 v[47:50], off, off offset:16
	scratch_load_b128 v[24:27], off, off offset:32
	scratch_load_b128 v[20:23], off, off offset:48
	scratch_load_b128 v[16:19], off, off offset:64
	scratch_load_b96 v[28:30], off, off offset:80
	v_mov_b32_e32 v35, 0x3c03126f
	v_mov_b32_e32 v36, 0xbc03126f
	s_mov_b32 s3, 0
	s_mov_b32 s19, 0
	s_mov_b32 s10, 0
	s_mov_b32 s11, exec_lo
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v37, v47, v48
	v_mul_f32_e32 v51, 0xc1300000, v48
	v_mul_f32_e32 v52, -4.0, v48
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v58, v23, v17
	v_fma_f32 v48, v48, 2.0, -v49
	v_dual_mul_f32 v53, 4.0, v24 :: v_dual_add_f32 v62, v37, v49
	v_fma_f32 v54, -4.0, v21, v22
	v_dual_add_f32 v56, v49, v24 :: v_dual_sub_f32 v61, v22, v23
	v_sub_f32_e32 v57, v25, v26
	v_dual_sub_f32 v59, v22, v16 :: v_dual_fmac_f32 v48, 2.0, v50
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmamk_f32 v37, v47, 0xc1f00000, v51 :: v_dual_add_f32 v56, v56, v25
	v_dual_add_f32 v55, v24, v24 :: v_dual_add_f32 v54, v54, v23
	v_sub_f32_e64 v60, -v26, v25
	s_waitcnt vmcnt(0)
	v_dual_fmamk_f32 v47, v47, 0x41400000, v52 :: v_dual_sub_f32 v58, v58, v28
	v_fma_f32 v51, 4.0, v50, v52
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmac_f32 v53, -4.0, v49 :: v_dual_add_f32 v60, v60, v27
	v_dual_fmac_f32 v52, 2.0, v49 :: v_dual_add_f32 v63, v57, v27
	v_dual_add_f32 v62, v62, v50 :: v_dual_sub_f32 v59, v59, v19
	v_dual_sub_f32 v48, v48, v24 :: v_dual_fmac_f32 v37, 0xc1300000, v49
	v_fma_f32 v55, v49, -2.0, -v55
	v_add_f32_e32 v61, v61, v16
	v_dual_fmac_f32 v47, -4.0, v49 :: v_dual_add_f32 v58, v58, v30
	v_dual_add_f32 v49, v51, v25 :: v_dual_add_f32 v60, v60, v20
	v_dual_add_f32 v51, v25, v53 :: v_dual_add_f32 v62, v62, v24
	v_dual_add_f32 v53, v54, v16 :: v_dual_add_f32 v54, v56, v26
	v_dual_sub_f32 v56, v63, v20 :: v_dual_fmac_f32 v37, 0xc1300000, v50
	v_add_f32_e32 v48, v25, v48
	v_dual_sub_f32 v57, v57, v27 :: v_dual_fmac_f32 v52, -4.0, v50
	v_sub_f32_e32 v49, v49, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v55, v25, v55 :: v_dual_add_f32 v48, v26, v48
	v_dual_fmac_f32 v47, -4.0, v50 :: v_dual_fmac_f32 v52, 2.0, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v57, v57, v20
	v_fmac_f32_e32 v37, 0xc1300000, v24
	v_dual_add_f32 v59, v59, v29 :: v_dual_add_f32 v50, v26, v51
	v_dual_fmac_f32 v47, -4.0, v24 :: v_dual_sub_f32 v24, v49, v27
	v_dual_sub_f32 v61, v61, v17 :: v_dual_mul_f32 v58, 0x3e800000, v58
	v_add_f32_e32 v51, v53, v17
	v_add_f32_e32 v53, v54, v27
	v_dual_add_f32 v54, v26, v55 :: v_dual_sub_f32 v55, v57, v22
	v_add_f32_e32 v24, v24, v20
	v_add_f32_e32 v57, v60, v23
	v_dual_sub_f32 v60, v61, v19 :: v_dual_add_f32 v61, v62, v25
	v_dual_add_f32 v48, v27, v48 :: v_dual_sub_f32 v49, v50, v27
	v_add_f32_e32 v50, v25, v52
	v_dual_add_f32 v52, v53, v20 :: v_dual_add_f32 v53, v27, v54
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v48, v20, v48
	v_dual_add_f32 v54, v55, v16 :: v_dual_sub_f32 v55, v57, v17
	v_add_f32_e32 v24, v24, v22
	v_fmac_f32_e32 v51, 4.0, v18
	v_dual_add_f32 v57, v60, v28 :: v_dual_add_f32 v60, v61, v26
	v_dual_fmac_f32 v37, 0x41000000, v25 :: v_dual_add_f32 v50, v26, v50
	v_add_f32_e32 v25, v25, v47
	v_sub_f32_e32 v47, v49, v20
	v_dual_sub_f32 v49, v51, v19 :: v_dual_sub_f32 v24, v24, v16
	v_sub_f32_e32 v51, v52, v21
	v_dual_add_f32 v52, v20, v53 :: v_dual_fmac_f32 v37, 0x41000000, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v24, v24, v19
	v_fmac_f32_e32 v52, 2.0, v21
	v_dual_add_f32 v25, v26, v25 :: v_dual_add_f32 v26, v47, v23
	v_sub_f32_e32 v47, v49, v28
	v_fmac_f32_e32 v37, 0x41000000, v27
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v25, v27, v25
	v_add_f32_e32 v49, v27, v50
	v_dual_sub_f32 v53, v54, v19 :: v_dual_add_f32 v54, v55, v28
	v_sub_f32_e32 v55, v57, v29
	v_dual_add_f32 v57, v60, v27 :: v_dual_sub_f32 v26, v26, v17
	v_sub_f32_e32 v50, v51, v22
	v_sub_f32_e32 v27, v47, v29
	v_sub_f32_e32 v47, v48, v21
	v_add_f32_e32 v48, v20, v49
	v_add_f32_e32 v51, v53, v29
	v_sub_f32_e32 v53, v54, v30
	v_dual_sub_f32 v49, v50, v16 :: v_dual_sub_f32 v50, v52, v22
	v_dual_add_f32 v54, v55, v30 :: v_dual_add_f32 v55, v57, v20
	v_dual_fmac_f32 v48, 2.0, v21 :: v_dual_fmac_f32 v37, 0x41000000, v20
	v_dual_add_f32 v20, v20, v25 :: v_dual_add_f32 v25, v26, v28
	v_add_f32_e32 v26, v22, v47
	v_sub_f32_e32 v52, v51, v53
	v_sub_f32_e64 v57, -v51, v53
	v_sub_f32_e32 v60, v53, v51
	v_dual_sub_f32 v62, v54, v51 :: v_dual_sub_f32 v63, v53, v54
	v_add_f32_e32 v64, v51, v54
	v_sub_f32_e64 v65, -v53, v54
	v_sub_f32_e64 v66, -v51, v54
	v_add_f32_e32 v67, v53, v54
	v_dual_sub_f32 v47, v50, v16 :: v_dual_fmac_f32 v20, -4.0, v21
	v_add_f32_e32 v61, v51, v53
	v_dual_sub_f32 v50, v24, v29 :: v_dual_sub_f32 v51, v51, v54
	v_dual_fmac_f32 v37, 0xc1300000, v21 :: v_dual_fmac_f32 v26, -2.0, v23
	v_sub_f32_e32 v53, v54, v53
	v_add_f32_e32 v54, v55, v21
	v_sub_f32_e32 v55, v27, v30
	v_sub_f32_e32 v27, v49, v18
	v_add_f32_e32 v21, v22, v48
	v_dual_fmac_f32 v37, 0x41000000, v22 :: v_dual_add_f32 v20, v22, v20
	v_add_f32_e32 v49, v54, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v22, v16, v26 :: v_dual_fmac_f32 v21, -2.0, v23
	v_dual_fmac_f32 v37, 0x41000000, v23 :: v_dual_add_f32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v47, 2.0, v18 :: v_dual_fmac_f32 v22, -2.0, v17
	v_sub_f32_e32 v54, v25, v30
	v_add_f32_e32 v25, v49, v23
	v_add_f32_e32 v21, v16, v21
	v_dual_fmac_f32 v37, 0x41000000, v16 :: v_dual_add_f32 v48, v50, v54
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f32_e32 v25, v25, v16
	v_add_f32_e32 v16, v16, v20
	v_sub_f32_e32 v26, v47, v19
	v_sub_f32_e32 v20, v22, v18
	v_add_f32_e32 v16, v17, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v72, v26, v29
	v_add_f32_e32 v69, v54, v55
	v_sub_f32_e32 v70, v50, v55
	v_sub_f32_e32 v24, v27, v19
	v_fmac_f32_e32 v16, -4.0, v18
	v_add_f32_e32 v68, v50, v55
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v24, v24, v29
	v_dual_add_f32 v16, v19, v16 :: v_dual_add_f32 v25, v25, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v23, 0x3daaaaab, v24
	v_dual_add_f32 v16, v28, v16 :: v_dual_fmac_f32 v21, -2.0, v17
	v_sub_f32_e32 v22, v24, v72
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v24, v25, v18
	v_dual_add_f32 v16, v29, v16 :: v_dual_fmac_f32 v37, 0x41000000, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v17, v19, v20 :: v_dual_add_f32 v20, v24, v19
	v_sub_f32_e32 v71, v54, v55
	v_dual_add_f32 v16, v30, v16 :: v_dual_fmac_f32 v37, 0xc1300000, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v21, 2.0, v18 :: v_dual_add_f32 v20, v20, v28
	v_sub_f32_e32 v49, v50, v54
	v_dual_fmac_f32 v37, 0x41000000, v19 :: v_dual_add_f32 v18, v19, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v20, v29
	v_fmac_f32_e32 v37, 0x41000000, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v18, -2.0, v28 :: v_dual_fmac_f32 v37, 0x41000000, v29
	v_add_f32_e32 v20, v29, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v37, 0x41000000, v30
	v_add_f32_e32 v19, v19, v30
	v_dual_fmac_f32 v20, -2.0, v30 :: v_dual_mul_f32 v75, 0x3b5b0037, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, 0x3d579436, v19
	v_fmamk_f32 v26, v37, 0xbb969026, v35
	v_dual_fmac_f32 v36, 0x3d579436, v19 :: v_dual_fmac_f32 v17, -2.0, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v75, 0x3d579436, v19
	v_mul_f32_e32 v18, 0x3d579436, v19
	v_fmac_f32_e32 v35, 0x3b5b0037, v37
	v_fmamk_f32 v47, v37, 0xbb969026, v36
	v_add_f32_e32 v17, v29, v17
	v_fmac_f32_e32 v75, 0x3b820821, v16
	v_fmac_f32_e32 v36, 0x3b5b0037, v37
	v_fmac_f32_e32 v35, 0x3b820821, v16
	v_fmac_f32_e32 v47, 0xbc820821, v16
	v_fmac_f32_e32 v17, -2.0, v30
	v_fmac_f32_e32 v75, 0xbccccccd, v68
	v_fma_f32 v30, 0x3d579436, v19, 0
	v_fmac_f32_e32 v36, 0x3b820821, v16
	v_fmamk_f32 v19, v49, 0xbccccccd, v35
	v_fmamk_f32 v28, v17, 0x3ce38e39, v23
	v_fma_f32 v29, 0x3ce38e39, v17, -v23
	v_fmamk_f32 v23, v37, 0xbc4d5033, v18
	v_fmac_f32_e32 v75, 0x3c638e39, v20
	v_fmac_f32_e32 v18, 0xbb969026, v37
	v_fmamk_f32 v74, v56, 0x3e800000, v28
	v_fmac_f32_e32 v28, 0xbe800000, v56
	v_fmamk_f32 v24, v16, 0x3d430c31, v23
	v_fmamk_f32 v23, v69, 0x3ccccccd, v35
	v_fmac_f32_e32 v75, 0xbd2aaaab, v72
	v_fmac_f32_e32 v19, 0x3c638e39, v20
	v_fmamk_f32 v21, v37, 0xbb969026, v30
	v_fmac_f32_e32 v47, 0x3dcccccd, v54
	v_fmac_f32_e32 v23, 0x3e000000, v63
	v_fmac_f32_e32 v75, 0x3e000000, v51
	v_fmac_f32_e32 v19, 0x3d2aaaab, v72
	v_fmac_f32_e32 v21, 0xbc820821, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v23, 0xbce38e39, v20
	v_fmamk_f32 v56, v59, 0x3e800000, v29
	v_fmamk_f32 v73, v17, 0xbd638e39, v58
	v_fma_f32 v58, 0xbd638e39, v17, -v58
	v_dual_add_f32 v76, 0xbc03126f, v30 :: v_dual_sub_f32 v17, v17, v20
	v_fmac_f32_e32 v29, 0xbe800000, v59
	v_add_f32_e32 v59, 0x3c03126f, v30
	v_fmac_f32_e32 v19, 0x3e000000, v57
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v76, 0x3b5b0037, v37
	v_fmac_f32_e32 v26, 0xbc820821, v16
	v_fmac_f32_e32 v59, 0x3b5b0037, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v76, 0x3b820821, v16
	v_fmac_f32_e32 v35, 0x3ccccccd, v71
	v_fmac_f32_e32 v59, 0x3b820821, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v76, 0x3ccccccd, v49
	v_fmac_f32_e32 v35, 0x3e000000, v67
	v_add_f32_e32 v49, v28, v19
	v_dual_fmamk_f32 v25, v50, 0xbdcccccd, v21 :: v_dual_fmac_f32 v26, 0xbdcccccd, v54
	v_fmac_f32_e32 v59, 0x3ccccccd, v48
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v35, 0xbce38e39, v20
	v_fmac_f32_e32 v30, 0x3b5b0037, v37
	v_fmamk_f32 v37, v71, 0xbccccccd, v36
	v_fmac_f32_e32 v76, 0x3c638e39, v20
	v_fmac_f32_e32 v59, 0x3c638e39, v20
	v_dual_add_f32 v35, v58, v35 :: v_dual_fmac_f32 v30, 0x3b820821, v16
	v_fmac_f32_e32 v21, 0xbdcccccd, v55
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v76, 0x3d2aaaab, v72
	v_fmac_f32_e32 v59, 0x3d2aaaab, v72
	v_fmac_f32_e32 v25, 0x3d638e39, v17
	v_fmamk_f32 v54, v68, 0x3ccccccd, v30
	v_fmamk_f32 v77, v70, 0xbccccccd, v30
	v_fmac_f32_e32 v30, 0x3ccccccd, v70
	v_fmac_f32_e32 v21, 0xbce38e39, v17
	v_fmac_f32_e32 v59, 0x3e000000, v52
	v_fmac_f32_e32 v54, 0x3c638e39, v20
	v_fmac_f32_e32 v77, 0x3c638e39, v20
	v_fmac_f32_e32 v30, 0x3c638e39, v20
	v_fmac_f32_e32 v76, 0x3e000000, v61
	v_fmac_f32_e32 v21, 0xbdaaaaab, v22
	v_fmac_f32_e32 v54, 0xbd2aaaab, v72
	v_fmac_f32_e32 v77, 0xbd2aaaab, v72
	v_fmac_f32_e32 v30, 0xbd2aaaab, v72
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v54, 0x3e000000, v62 :: v_dual_fmac_f32 v77, 0x3e000000, v64
	v_fmac_f32_e32 v30, 0x3e000000, v66
	v_fmac_f32_e32 v18, 0xbc820821, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v29, v77
	v_add_f32_e32 v19, v29, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmamk_f32 v27, v50, 0x3dcccccd, v18
	v_fmamk_f32 v50, v48, 0xbccccccd, v36
	v_fmac_f32_e32 v36, 0xbccccccd, v69
	v_fmac_f32_e32 v18, 0x3dcccccd, v55
	v_dual_add_f32 v48, v74, v59 :: v_dual_fmac_f32 v27, 0x3d638e39, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v50, 0x3c638e39, v20
	v_fmac_f32_e32 v36, 0x3e000000, v53
	v_fmac_f32_e32 v47, 0xbce38e39, v17
	v_fmac_f32_e32 v18, 0xbce38e39, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v50, 0x3d2aaaab, v72
	v_fmac_f32_e32 v36, 0xbce38e39, v20
	v_fmac_f32_e32 v37, 0x3e000000, v65
	v_fmac_f32_e32 v47, 0x3daaaaab, v22
	v_fmac_f32_e32 v18, 0xbdaaaaab, v22
	v_fmac_f32_e32 v50, 0x3e000000, v60
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v26, 0xbce38e39, v17 :: v_dual_fmac_f32 v37, 0xbce38e39, v20
	v_add_f32_e32 v20, v28, v76
	v_add_f32_e32 v50, v74, v50
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmac_f32 v26, 0x3daaaaab, v22 :: v_dual_add_f32 v17, v58, v37
	v_dual_add_f32 v37, v73, v36 :: v_dual_add_f32 v36, v56, v75
	v_dual_add_f32 v23, v73, v23 :: v_dual_add_f32 v22, v56, v54
	s_clause 0x4
	scratch_store_b128 off, v[24:27], off offset:16
	scratch_store_b128 off, v[47:50], off offset:32
	scratch_store_b128 off, v[20:23], off offset:48
	scratch_store_b128 off, v[16:19], off offset:64
	scratch_store_b96 off, v[35:37], off offset:80
	v_cmpx_lt_i32_e32 25, v46
	s_xor_b32 s11, exec_lo, s11
; %bb.18:                               ; %LeafBlock603
	v_cmp_eq_u32_e32 vcc_lo, 26, v46
	s_mov_b32 s10, exec_lo
	s_and_b32 s19, vcc_lo, exec_lo
; %bb.19:                               ; %Flow634
	s_and_not1_saveexec_b32 s11, s11
; %bb.20:                               ; %LeafBlock601
	v_cmp_eq_u32_e32 vcc_lo, 25, v46
	s_or_b32 s10, s10, exec_lo
	s_and_b32 s3, vcc_lo, exec_lo
; %bb.21:                               ; %Flow635
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s10, exec_lo
	s_and_b32 s10, s3, exec_lo
	s_and_b32 s3, s19, exec_lo
                                        ; implicit-def: $vgpr20
.LBB1_22:                               ; %Flow633
	s_and_not1_saveexec_b32 s15, s15
	s_cbranch_execz .LBB1_28
; %bb.23:                               ; %LeafBlock593
	s_mov_b32 s19, -1
	s_mov_b32 s21, s11
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	v_cmpx_eq_u32_e32 0x64, v46
	s_cbranch_execz .LBB1_27
; %bb.24:                               ; %.preheader.preheader
	v_mad_u64_u32 v[16:17], null, v20, s12, v[38:39]
	s_lshl_b32 s19, s12, 6
	s_mov_b32 s21, 0
.LBB1_25:                               ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_max_i32_e32 v17, 0, v16
	v_add_nc_u32_e32 v16, s19, v16
	s_add_i32 s22, s21, 16
	s_add_i32 s21, s21, 4
	s_cmpk_eq_i32 s21, 0x4c
	v_cmp_gt_i32_e32 vcc_lo, s20, v17
	v_cndmask_b32_e32 v17, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, s6, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
	global_load_b32 v17, v[17:18], off
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v17, s22
	s_cbranch_scc0 .LBB1_25
; %bb.26:
	s_clause 0x4
	scratch_load_b128 v[47:50], off, off offset:16
	scratch_load_b128 v[26:29], off, off offset:32
	scratch_load_b128 v[17:20], off, off offset:48
	scratch_load_b128 v[22:25], off, off offset:64
	scratch_load_b96 v[35:37], off, off offset:80
	s_mov_b32 s7, 0x3dcccccd
	s_mov_b32 s19, 0xbdcccccd
	s_mov_b32 s6, 0xbc4d5033
	s_or_b32 s21, s11, exec_lo
	s_waitcnt vmcnt(4)
	v_dual_sub_f32 v21, v48, v50 :: v_dual_mul_f32 v16, 0xc1f00000, v47
	s_waitcnt vmcnt(1)
	v_dual_sub_f32 v30, v49, v26 :: v_dual_sub_f32 v59, v20, v23
	v_dual_add_f32 v51, v19, v18 :: v_dual_mul_f32 v52, -4.0, v48
	v_dual_mul_f32 v53, 4.0, v26 :: v_dual_sub_f32 v58, v27, v28
	v_fma_f32 v54, -4.0, v18, v19
	v_fma_f32 v55, v48, 2.0, -v49
	v_dual_add_f32 v56, v26, v26 :: v_dual_add_f32 v21, v21, v27
	v_dual_add_f32 v57, v49, v26 :: v_dual_sub_f32 v62, v19, v20
	v_dual_sub_f32 v60, v19, v22 :: v_dual_add_f32 v51, v20, v51
	v_sub_f32_e64 v61, -v28, v27
	v_dual_add_f32 v30, v27, v30 :: v_dual_fmac_f32 v53, -4.0, v49
	v_dual_fmac_f32 v16, 0xc1300000, v48 :: v_dual_fmac_f32 v55, 2.0, v50
	v_dual_fmamk_f32 v48, v47, 0x41400000, v52 :: v_dual_add_f32 v63, v58, v29
	v_fma_f32 v47, 4.0, v50, v52
	v_dual_add_f32 v54, v20, v54 :: v_dual_add_f32 v57, v27, v57
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v52, 2.0, v49 :: v_dual_sub_f32 v59, v59, v35
	v_fma_f32 v56, v49, -2.0, -v56
	v_dual_sub_f32 v60, v60, v25 :: v_dual_sub_f32 v21, v21, v28
	v_sub_f32_e32 v58, v58, v29
	v_dual_add_f32 v61, v61, v29 :: v_dual_add_f32 v62, v22, v62
	v_dual_add_f32 v64, v28, v30 :: v_dual_add_f32 v51, v22, v51
	v_dual_fmac_f32 v16, 0xc1300000, v49 :: v_dual_sub_f32 v55, v55, v26
	v_dual_fmac_f32 v48, -4.0, v49 :: v_dual_add_f32 v49, v27, v47
	v_add_f32_e32 v47, v60, v36
	v_dual_add_f32 v53, v27, v53 :: v_dual_add_f32 v54, v22, v54
	v_dual_fmac_f32 v52, -4.0, v50 :: v_dual_add_f32 v57, v28, v57
	v_add_f32_e32 v56, v27, v56
	v_dual_add_f32 v59, v59, v37 :: v_dual_fmac_f32 v16, 0xc1300000, v50
	v_dual_add_f32 v58, v58, v17 :: v_dual_add_f32 v51, v23, v51
	v_dual_add_f32 v60, v61, v17 :: v_dual_sub_f32 v61, v62, v23
	v_dual_sub_f32 v30, v63, v17 :: v_dual_sub_f32 v49, v49, v28
	v_dual_sub_f32 v21, v21, v29 :: v_dual_fmac_f32 v48, -4.0, v50
	v_sub_f32_e32 v62, v64, v29
	v_dual_add_f32 v50, v28, v53 :: v_dual_mul_f32 v59, 0x3e800000, v59
	v_add_f32_e32 v53, v23, v54
	v_dual_add_f32 v54, v27, v55 :: v_dual_add_f32 v55, v29, v57
	v_dual_fmac_f32 v52, 2.0, v26 :: v_dual_add_f32 v21, v21, v17
	v_dual_sub_f32 v57, v58, v19 :: v_dual_add_f32 v56, v28, v56
	v_add_f32_e32 v58, v60, v20
	v_dual_sub_f32 v60, v61, v25 :: v_dual_sub_f32 v51, v51, v24
	v_dual_sub_f32 v61, v62, v17 :: v_dual_fmac_f32 v16, 0xc1300000, v26
	v_dual_fmac_f32 v53, 4.0, v24 :: v_dual_fmac_f32 v48, -4.0, v26
	v_sub_f32_e32 v26, v49, v29
	v_dual_sub_f32 v49, v50, v29 :: v_dual_add_f32 v50, v28, v54
	v_dual_add_f32 v21, v21, v19 :: v_dual_add_f32 v52, v27, v52
	v_dual_add_f32 v54, v17, v55 :: v_dual_sub_f32 v51, v51, v25
	v_add_f32_e32 v55, v29, v56
	v_dual_add_f32 v56, v57, v22 :: v_dual_sub_f32 v57, v58, v23
	v_add_f32_e32 v58, v35, v60
	v_dual_fmac_f32 v16, 0x41000000, v27 :: v_dual_add_f32 v27, v27, v48
	v_dual_add_f32 v26, v17, v26 :: v_dual_sub_f32 v51, v51, v35
	v_sub_f32_e32 v48, v49, v17
	v_sub_f32_e32 v49, v53, v25
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v27, v28, v27
	v_dual_add_f32 v52, v28, v52 :: v_dual_sub_f32 v21, v21, v22
	v_dual_sub_f32 v53, v54, v18 :: v_dual_add_f32 v60, v20, v61
	v_dual_add_f32 v54, v17, v55 :: v_dual_sub_f32 v55, v56, v25
	v_add_f32_e32 v50, v29, v50
	v_dual_add_f32 v56, v57, v35 :: v_dual_sub_f32 v57, v58, v36
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v58, v60, v23
	v_dual_fmac_f32 v16, 0x41000000, v28 :: v_dual_add_f32 v21, v21, v25
	v_add_f32_e32 v28, v20, v48
	v_dual_sub_f32 v48, v49, v35 :: v_dual_sub_f32 v51, v51, v36
	v_add_f32_e32 v49, v17, v50
	v_add_f32_e32 v50, v29, v52
	v_sub_f32_e32 v52, v53, v19
	v_dual_add_f32 v26, v19, v26 :: v_dual_add_f32 v27, v29, v27
	v_add_f32_e32 v53, v55, v36
	v_dual_sub_f32 v55, v56, v37 :: v_dual_fmac_f32 v54, 2.0, v18
	v_dual_fmac_f32 v16, 0x41000000, v29 :: v_dual_sub_f32 v29, v48, v36
	v_dual_sub_f32 v48, v49, v18 :: v_dual_sub_f32 v51, v51, v37
	v_dual_add_f32 v49, v17, v50 :: v_dual_sub_f32 v28, v28, v23
	v_dual_add_f32 v56, v37, v57 :: v_dual_add_f32 v57, v35, v58
	v_dual_sub_f32 v50, v52, v22 :: v_dual_sub_f32 v21, v21, v36
	v_sub_f32_e64 v58, -v53, v55
	v_dual_sub_f32 v60, v55, v53 :: v_dual_add_f32 v61, v53, v55
	v_sub_f32_e32 v52, v54, v19
	v_dual_sub_f32 v54, v53, v55 :: v_dual_fmac_f32 v49, 2.0, v18
	v_dual_fmac_f32 v16, 0x41000000, v17 :: v_dual_add_f32 v17, v17, v27
	v_dual_add_f32 v27, v35, v28 :: v_dual_sub_f32 v26, v26, v22
	v_dual_add_f32 v67, v55, v56 :: v_dual_sub_f32 v62, v56, v53
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v17, -4.0, v18
	v_sub_f32_e32 v63, v55, v56
	v_add_f32_e32 v64, v53, v56
	v_sub_f32_e64 v65, -v55, v56
	v_sub_f32_e64 v66, -v53, v56
	v_sub_f32_e32 v53, v53, v56
	v_dual_sub_f32 v55, v56, v55 :: v_dual_sub_f32 v28, v29, v37
	v_dual_add_f32 v29, v19, v48 :: v_dual_sub_f32 v56, v57, v37
	v_dual_sub_f32 v48, v50, v24 :: v_dual_sub_f32 v57, v27, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v70, s19, v21, 0x3d579436 :: v_dual_fmac_f32 v29, -2.0, v20
	v_dual_fmaak_f32 v69, s7, v56, 0x3d579436 :: v_dual_fmaak_f32 v68, s7, v21, 0x3d579436
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f32_e32 v77, v57, v28
	v_dual_fmaak_f32 v21, s7, v51, 0x3d579436 :: v_dual_add_f32 v26, v25, v26
	v_sub_f32_e32 v27, v48, v25
	v_dual_sub_f32 v50, v52, v22 :: v_dual_fmaak_f32 v71, s19, v56, 0x3d579436
	v_dual_add_f32 v17, v19, v17 :: v_dual_sub_f32 v52, v26, v36
	v_dual_fmamk_f32 v73, v56, 0xbdcccccd, v70 :: v_dual_add_f32 v26, v19, v49
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v27, v27, v36 :: v_dual_fmac_f32 v16, 0xc1300000, v18
	v_fmac_f32_e32 v50, 2.0, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v75, v52, v28
	v_dual_fmac_f32 v26, -2.0, v20 :: v_dual_add_f32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v16, 0x41000000, v19 :: v_dual_add_f32 v49, v52, v57
	v_dual_add_f32 v19, v22, v29 :: v_dual_fmamk_f32 v48, v56, 0x3dcccccd, v68
	v_dual_add_f32 v17, v22, v17 :: v_dual_fmaak_f32 v18, s19, v51, 0x3d579436
	v_sub_f32_e32 v29, v50, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v19, -2.0, v23 :: v_dual_fmamk_f32 v50, v56, 0x3dcccccd, v70
	v_dual_fmamk_f32 v56, v56, 0xbdcccccd, v68 :: v_dual_add_f32 v17, v23, v17
	v_fmamk_f32 v78, v51, 0x3dcccccd, v70
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v19, v19, v24 :: v_dual_sub_f32 v72, v52, v57
	v_sub_f32_e32 v29, v29, v36
	v_fmac_f32_e32 v17, -4.0, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmamk_f32 v76, v51, 0x3dcccccd, v69 :: v_dual_add_f32 v19, v25, v19
	v_fmac_f32_e32 v16, 0x41000000, v20
	v_dual_add_f32 v20, v22, v26 :: v_dual_add_f32 v17, v25, v17
	v_dual_fmamk_f32 v74, v51, 0x3dcccccd, v68 :: v_dual_sub_f32 v79, v52, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v19, -2.0, v35 :: v_dual_fmac_f32 v16, 0x41000000, v22
	v_dual_fmac_f32 v20, -2.0, v23 :: v_dual_add_f32 v17, v35, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmamk_f32 v22, v51, 0x3dcccccd, v71 :: v_dual_add_f32 v19, v36, v19
	v_fmac_f32_e32 v16, 0x41000000, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v20, 2.0, v24 :: v_dual_add_f32 v17, v36, v17
	v_sub_f32_e32 v23, v57, v28
	v_dual_fmac_f32 v19, -2.0, v37 :: v_dual_fmac_f32 v16, 0xc1300000, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v20, v25, v20
	v_add_f32_e32 v17, v37, v17
	s_xor_b32 s19, exec_lo, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmamk_f32 v81, v19, 0xbd638e39, v59
	v_fma_f32 v59, 0xbd638e39, v19, -v59
	v_fmac_f32_e32 v20, -2.0, v35
	v_add_f32_e32 v20, v36, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, -2.0, v37
	v_fmac_f32_e32 v16, 0x41000000, v25
	v_dual_fmac_f32 v16, 0x41000000, v35 :: v_dual_sub_f32 v35, v27, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0x41000000, v36
	v_fmac_f32_e32 v16, 0x41000000, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmamk_f32 v26, v16, 0xbb969026, v69
	v_fmac_f32_e32 v76, 0x3b5b0037, v16
	v_fmac_f32_e32 v22, 0x3b5b0037, v16
	v_fmac_f32_e32 v18, 0xbb969026, v16
	v_fmac_f32_e32 v26, 0xbc820821, v17
	v_fmac_f32_e32 v69, 0xbdcccccd, v51
	v_fmac_f32_e32 v76, 0x3b820821, v17
	v_fmac_f32_e32 v22, 0x3b820821, v17
	v_fmac_f32_e32 v18, 0xbc820821, v17
	v_fmac_f32_e32 v26, 0xbdcccccd, v57
	v_fmac_f32_e32 v69, 0x3b5b0037, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v22, 0xbccccccd, v23
	v_fmac_f32_e32 v18, 0x3dcccccd, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v69, 0x3b820821, v17
	v_dual_fmac_f32 v76, 0x3ccccccd, v77 :: v_dual_fmac_f32 v69, 0x3ccccccd, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v76, 0x3e000000, v63
	v_dual_fmac_f32 v22, 0x3e000000, v65 :: v_dual_fmac_f32 v69, 0x3e000000, v67
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v76, 0xbce38e39, v20
	v_dual_mul_f32 v24, 0x3daaaaab, v27 :: v_dual_add_f32 v23, v81, v76
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v36, v19, 0x3ce38e39, v24
	v_fma_f32 v80, 0x3ce38e39, v19, -v24
	v_fmamk_f32 v37, v30, 0x3e800000, v36
	v_fmamk_f32 v25, v16, 0xbb969026, v68
	v_fmac_f32_e32 v36, 0xbe800000, v30
	s_delay_alu instid0(VALU_DEP_4)
	v_fmamk_f32 v30, v47, 0x3e800000, v80
	v_fmac_f32_e32 v80, 0xbe800000, v47
	v_fmamk_f32 v27, v16, 0xbb969026, v70
	v_fmac_f32_e32 v25, 0xbc820821, v17
	v_fmac_f32_e32 v68, 0xbdcccccd, v51
	v_fmamk_f32 v47, v16, 0xbb969026, v71
	v_fmac_f32_e32 v21, 0xbb969026, v16
	v_fmac_f32_e32 v27, 0xbc820821, v17
	v_fmac_f32_e32 v25, 0xbdcccccd, v52
	v_fmac_f32_e32 v68, 0x3b5b0037, v16
	v_fmac_f32_e32 v47, 0xbc820821, v17
	v_fmac_f32_e32 v21, 0xbc820821, v17
	v_dual_sub_f32 v19, v19, v20 :: v_dual_fmac_f32 v70, 0xbdcccccd, v51
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v68, 0x3b820821, v17
	v_fmac_f32_e32 v27, 0x3dcccccd, v52
	v_fmac_f32_e32 v21, 0xbdcccccd, v28
	v_fmac_f32_e32 v47, 0x3dcccccd, v57
	v_fmac_f32_e32 v25, 0x3d638e39, v19
	v_fmac_f32_e32 v68, 0x3ccccccd, v79
	v_dual_fmac_f32 v26, 0xbce38e39, v19 :: v_dual_fmac_f32 v69, 0xbce38e39, v20
	v_fmac_f32_e32 v27, 0x3d638e39, v19
	v_dual_fmac_f32 v47, 0xbce38e39, v19 :: v_dual_fmac_f32 v22, 0xbce38e39, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v68, 0x3c638e39, v20
	v_fmac_f32_e32 v21, 0xbce38e39, v19
	v_fmac_f32_e32 v18, 0xbce38e39, v19
	v_fmac_f32_e32 v26, 0x3daaaaab, v35
	v_fmac_f32_e32 v47, 0x3daaaaab, v35
	v_fmac_f32_e32 v68, 0xbd2aaaab, v29
	v_fmac_f32_e32 v21, 0xbdaaaaab, v35
	v_dual_fmac_f32 v18, 0xbdaaaaab, v35 :: v_dual_add_f32 v35, v59, v69
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v68, 0x3e000000, v66
	v_add_f32_e32 v19, v80, v68
	v_fmac_f32_e32 v56, 0x3b5b0037, v16
	v_fmac_f32_e32 v74, 0x3b5b0037, v16
	v_fmac_f32_e32 v48, 0x3b5b0037, v16
	v_fmac_f32_e32 v50, 0x3b5b0037, v16
	v_fmac_f32_e32 v78, 0x3b5b0037, v16
	v_fmac_f32_e32 v56, 0x3b820821, v17
	v_fmac_f32_e32 v74, 0x3b820821, v17
	v_fmac_f32_e32 v70, 0x3b5b0037, v16
	v_fmac_f32_e32 v48, 0x3b820821, v17
	v_fmac_f32_e32 v50, 0x3b820821, v17
	v_fmac_f32_e32 v56, 0x3ccccccd, v72
	v_fmac_f32_e32 v74, 0x3ccccccd, v75
	v_fmac_f32_e32 v78, 0x3b820821, v17
	v_fmac_f32_e32 v70, 0x3b820821, v17
	v_fmac_f32_e32 v48, 0x3ccccccd, v49
	v_fmac_f32_e32 v56, 0x3c638e39, v20
	v_fmac_f32_e32 v74, 0x3c638e39, v20
	v_fmaak_f32 v24, s6, v16, 0x3d579436
	v_fmac_f32_e32 v70, 0xbccccccd, v75
	v_fmac_f32_e32 v48, 0x3c638e39, v20
	v_fmac_f32_e32 v56, 0x3d2aaaab, v29
	v_fmac_f32_e32 v74, 0xbd2aaaab, v29
	v_fmamk_f32 v24, v17, 0x3d430c31, v24
	v_fmac_f32_e32 v70, 0x3c638e39, v20
	v_fmac_f32_e32 v48, 0x3d2aaaab, v29
	v_fmac_f32_e32 v56, 0x3e000000, v61
	v_fmac_f32_e32 v71, 0xbdcccccd, v51
	v_fmac_f32_e32 v74, 0x3e000000, v62
	v_fmac_f32_e32 v73, 0x3b5b0037, v16
	v_fmac_f32_e32 v70, 0xbd2aaaab, v29
	v_fmac_f32_e32 v48, 0x3e000000, v54
	v_fmac_f32_e32 v71, 0x3b5b0037, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, 0x3b820821, v17
	v_fmac_f32_e32 v50, 0xbccccccd, v72
	v_fmac_f32_e32 v70, 0x3e000000, v53
	v_fmac_f32_e32 v71, 0x3b820821, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v78, 0xbccccccd, v79 :: v_dual_fmac_f32 v73, 0xbccccccd, v49
	v_dual_fmac_f32 v50, 0x3c638e39, v20 :: v_dual_add_f32 v17, v59, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v71, 0xbccccccd, v77
	v_fmac_f32_e32 v78, 0x3c638e39, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, 0x3c638e39, v20
	v_fmac_f32_e32 v50, 0x3d2aaaab, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v48, v37, v48 :: v_dual_fmac_f32 v71, 0x3e000000, v55
	v_fmac_f32_e32 v78, 0xbd2aaaab, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, 0x3d2aaaab, v29
	v_fmac_f32_e32 v50, 0x3e000000, v58
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v22, v30, v74 :: v_dual_fmac_f32 v71, 0xbce38e39, v20
	v_fmac_f32_e32 v78, 0x3e000000, v64
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, 0x3e000000, v60
	v_add_f32_e32 v49, v36, v50
	v_add_f32_e32 v20, v36, v56
	v_add_f32_e32 v36, v30, v70
	v_add_f32_e32 v16, v80, v78
	v_add_f32_e32 v50, v37, v73
	v_add_f32_e32 v37, v81, v71
	s_clause 0x4
	scratch_store_b128 off, v[24:27], off offset:16
	scratch_store_b128 off, v[47:50], off offset:32
	scratch_store_b128 off, v[20:23], off offset:48
	scratch_store_b96 off, v[16:18], off offset:64
	scratch_store_b32 off, v35, off offset:80
.LBB1_27:                               ; %Flow637
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s6, s11, exec_lo
	s_and_b32 s7, s21, exec_lo
	s_and_b32 s14, s19, exec_lo
	s_or_b32 s11, s6, s7
.LBB1_28:                               ; %Flow636
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s15, s11, exec_lo
	s_and_b32 s11, s14, exec_lo
	s_and_b32 s10, s10, exec_lo
	s_and_b32 s3, s3, exec_lo
.LBB1_29:                               ; %Flow632
	s_and_not1_saveexec_b32 s2, s2
; %bb.30:                               ; %LeafBlock591
	v_cmp_eq_u32_e32 vcc_lo, 26, v46
	v_dual_mov_b32 v23, v3 :: v_dual_mov_b32 v16, v8
	v_dual_mov_b32 v35, v32 :: v_dual_mov_b32 v36, v33
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v18, v10
	v_mov_b32_e32 v37, v34
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s6, vcc_lo, exec_lo
	s_or_b32 s11, s11, exec_lo
	s_or_b32 s3, s3, s6
; %bb.31:                               ; %Flow638
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s6, s3
	s_cbranch_execz .LBB1_57
; %bb.32:
	v_or_b32_e32 v19, s8, v31
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v19
                                        ; implicit-def: $vgpr19
	s_and_saveexec_b32 s3, vcc_lo
	s_xor_b32 s7, exec_lo, s3
	s_cbranch_execz .LBB1_52
; %bb.33:
	s_cmp_eq_u32 s8, 7
	v_cmp_ne_u32_e32 vcc_lo, 0, v31
	s_cselect_b32 s21, -1, 0
	s_cmp_lg_u32 s8, 7
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s3, vcc_lo
	s_and_saveexec_b32 s14, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB1_49
; %bb.34:
	v_cmp_ne_u32_e64 s3, 63, v31
	s_cmp_lg_u32 s8, 0
	v_cmp_eq_u32_e64 s2, 63, v31
	s_cselect_b32 s22, -1, 0
	s_mov_b32 s19, 0
	s_or_b32 s3, s22, s3
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s22, s3
	s_xor_b32 s3, exec_lo, s22
	s_cbranch_execz .LBB1_46
; %bb.35:
	s_and_b32 s19, s21, s2
	s_mov_b32 s21, 0
	s_xor_b32 s19, s19, -1
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s22, s19
	s_xor_b32 s19, exec_lo, s22
	s_cbranch_execz .LBB1_43
; %bb.36:
                                        ; implicit-def: $sgpr22
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr24
                                        ; implicit-def: $sgpr25
                                        ; implicit-def: $sgpr26
                                        ; implicit-def: $sgpr27
                                        ; implicit-def: $sgpr28
	s_and_saveexec_b32 s29, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s29, exec_lo, s29
	s_cbranch_execz .LBB1_40
; %bb.37:
                                        ; implicit-def: $sgpr22
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr24
                                        ; implicit-def: $sgpr25
                                        ; implicit-def: $sgpr26
                                        ; implicit-def: $sgpr27
                                        ; implicit-def: $sgpr28
	s_and_saveexec_b32 s30, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s30
	s_cbranch_execz .LBB1_39
; %bb.38:
	scratch_load_b32 v37, off, off offset:24
	s_mov_b32 s21, exec_lo
	s_mov_b32 s28, 4
	s_mov_b32 s27, 11
	s_mov_b32 s26, 13
	s_mov_b32 s25, 16
	s_mov_b32 s24, 18
	s_mov_b32 s23, 8
	s_mov_b32 s22, 5
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
.LBB1_39:                               ; %Flow611
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s21, s21, exec_lo
.LBB1_40:                               ; %Flow610
	s_or_saveexec_b32 s2, s29
	v_dual_mov_b32 v19, s22 :: v_dual_mov_b32 v20, s23
	v_dual_mov_b32 v21, s24 :: v_dual_mov_b32 v22, s25
	v_dual_mov_b32 v24, s26 :: v_dual_mov_b32 v25, s27
	v_mov_b32_e32 v26, s28
	s_xor_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_42
; %bb.41:
	scratch_load_b32 v37, off, off offset:32
	v_dual_mov_b32 v19, 8 :: v_dual_mov_b32 v20, 5
	v_dual_mov_b32 v21, 16 :: v_dual_mov_b32 v22, 18
	v_dual_mov_b32 v24, 11 :: v_dual_mov_b32 v25, 13
	v_mov_b32_e32 v26, 2
	s_or_b32 s21, s21, exec_lo
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
.LBB1_42:                               ; %Flow612
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s21, s21, exec_lo
.LBB1_43:                               ; %Flow609
	s_and_not1_saveexec_b32 s2, s19
	s_cbranch_execz .LBB1_45
; %bb.44:
	scratch_load_b32 v16, off, off offset:24
	v_dual_mov_b32 v19, 17 :: v_dual_mov_b32 v20, 12
	v_dual_mov_b32 v21, 14 :: v_dual_mov_b32 v22, 9
	v_dual_mov_b32 v24, 7 :: v_dual_mov_b32 v25, 6
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v26, 13 :: v_dual_mov_b32 v37, v23
	s_or_b32 s21, s21, exec_lo
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v23, off offset:80
	scratch_store_b32 off, v23, off offset:88
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
.LBB1_45:                               ; %Flow613
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s19, s21, exec_lo
.LBB1_46:                               ; %Flow608
	s_and_not1_saveexec_b32 s2, s3
	s_cbranch_execz .LBB1_48
; %bb.47:
	scratch_load_b32 v16, off, off offset:24
	v_dual_mov_b32 v19, 12 :: v_dual_mov_b32 v20, 17
	v_dual_mov_b32 v21, 9 :: v_dual_mov_b32 v22, 14
	v_dual_mov_b32 v24, 7 :: v_dual_mov_b32 v25, 6
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v26, 13 :: v_dual_mov_b32 v37, v35
	s_or_b32 s19, s19, exec_lo
                                        ; implicit-def: $vgpr23
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v35, off offset:60
	scratch_store_b32 off, v35, off offset:88
                                        ; implicit-def: $vgpr16
.LBB1_48:                               ; %Flow614
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s19, exec_lo
.LBB1_49:                               ; %Flow607
	s_and_not1_saveexec_b32 s3, s14
	s_cbranch_execz .LBB1_51
; %bb.50:
	scratch_load_b32 v16, off, off offset:24
	v_dual_mov_b32 v19, 17 :: v_dual_mov_b32 v20, 12
	v_dual_mov_b32 v21, 14 :: v_dual_mov_b32 v22, 9
	v_dual_mov_b32 v24, 6 :: v_dual_mov_b32 v25, 7
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v26, 16 :: v_dual_mov_b32 v37, v17
	s_or_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr23
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v17, off offset:60
	scratch_store_b32 off, v17, off offset:88
                                        ; implicit-def: $vgpr16
.LBB1_51:                               ; %Flow615
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
.LBB1_52:                               ; %Flow
	s_and_not1_saveexec_b32 s3, s7
	s_cbranch_execz .LBB1_54
; %bb.53:
	scratch_load_b32 v16, off, off offset:32
	v_dual_mov_b32 v19, 12 :: v_dual_mov_b32 v20, 17
	v_dual_mov_b32 v21, 9 :: v_dual_mov_b32 v22, 14
	v_dual_mov_b32 v24, 6 :: v_dual_mov_b32 v25, 7
	v_mov_b32_e32 v26, 16
	s_or_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr23
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:24
	scratch_store_b32 off, v37, off offset:68
	scratch_store_b32 off, v37, off offset:60
                                        ; implicit-def: $vgpr16
.LBB1_54:                               ; %Flow616
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_56
; %bb.55:                               ; %.sink.split.i
	v_lshl_add_u32 v16, v26, 2, 16
	v_lshl_add_u32 v17, v25, 2, 16
	v_lshl_add_u32 v18, v22, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v16, v37, off
	scratch_load_b32 v16, v17, off
	v_lshl_add_u32 v17, v24, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v17, v16, off
	scratch_load_b32 v16, v18, off
	v_lshl_add_u32 v17, v21, 2, 16
	v_lshl_add_u32 v18, v20, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v17, v16, off
	scratch_load_b32 v16, v18, off
	v_lshl_add_u32 v17, v19, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v17, v16, off
	s_clause 0x1
	scratch_load_b128 v[19:22], off, off offset:60
	scratch_load_b96 v[35:37], off, off offset:80
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v18, v22 :: v_dual_mov_b32 v17, v21
	v_dual_mov_b32 v23, v19 :: v_dual_mov_b32 v16, v20
.LBB1_56:                               ; %_Z13xsymmetry_botPfii.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:28
	scratch_load_b64 v[20:21], off, off offset:40
	v_mov_b32_e32 v22, v16
	s_waitcnt vmcnt(2)
	v_mov_b32_e32 v19, v36
	s_or_b32 s15, s15, exec_lo
	s_and_not1_b32 s11, s11, exec_lo
	s_waitcnt vmcnt(1)
	scratch_store_b32 off, v24, off offset:20
	s_waitcnt vmcnt(0)
	s_clause 0x1
	scratch_store_b32 off, v20, off offset:36
	scratch_store_b32 off, v21, off offset:48
.LBB1_57:                               ; %Flow639
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s14, s15, exec_lo
	s_and_b32 s11, s11, exec_lo
	s_and_b32 s2, s10, exec_lo
.LBB1_58:                               ; %Flow631
	s_or_saveexec_b32 s3, s9
	s_mov_b32 s7, 0
	s_mov_b32 s6, 0
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB1_62
; %bb.59:                               ; %NodeBlock589
	s_mov_b32 s6, -1
	s_mov_b32 s9, s2
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i32_e32 9, v46
; %bb.60:                               ; %NodeBlock587
	v_cmp_lt_i32_e32 vcc_lo, 24, v46
	s_and_not1_b32 s9, s2, exec_lo
	s_mov_b32 s7, exec_lo
	s_xor_b32 s6, exec_lo, -1
	s_and_b32 s15, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s9, s9, s15
; %bb.61:                               ; %Flow641
	s_or_b32 exec_lo, exec_lo, s10
	v_dual_mov_b32 v23, v3 :: v_dual_mov_b32 v18, v10
	v_mov_b32_e32 v35, v32
	v_mov_b32_e32 v17, v9
	v_mov_b32_e32 v37, v34
	v_mov_b32_e32 v19, v11
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s9, s9, exec_lo
	s_and_b32 s6, s6, exec_lo
	s_and_b32 s7, s7, exec_lo
	s_or_b32 s2, s2, s9
.LBB1_62:                               ; %Flow640
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s9, s2
	s_cbranch_execz .LBB1_88
; %bb.63:
	v_or_b32_e32 v16, s8, v31
                                        ; implicit-def: $vgpr24
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v16
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_85
; %bb.64:
	s_cmp_eq_u32 s8, 7
	v_cmp_ne_u32_e32 vcc_lo, 0, v31
	s_cselect_b32 s19, -1, 0
	s_cmp_lg_u32 s8, 7
                                        ; implicit-def: $vgpr24
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s15, exec_lo, s3
	s_cbranch_execz .LBB1_82
; %bb.65:
	v_cmp_ne_u32_e64 s2, 63, v31
	s_cmp_lg_u32 s8, 0
	v_cmp_eq_u32_e64 s3, 63, v31
	s_cselect_b32 s8, -1, 0
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s8, s8, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s21, s8
	s_xor_b32 s8, exec_lo, s21
	s_cbranch_execz .LBB1_79
; %bb.66:
	s_and_b32 s3, s19, s3
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, -1
	s_and_saveexec_b32 s19, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s19
	s_cbranch_execz .LBB1_76
; %bb.67:
                                        ; implicit-def: $vgpr24
	s_and_saveexec_b32 s19, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s19, exec_lo, s19
	s_cbranch_execz .LBB1_73
; %bb.68:
                                        ; implicit-def: $vgpr24
	s_and_saveexec_b32 s21, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s21
; %bb.69:                               ; %._crit_edge.i
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b32 v25, off, off offset:48
; %bb.70:                               ; %Flow618
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB1_72
; %bb.71:
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b32 v16, off, off offset:24
	v_mov_b32_e32 v17, v23
	v_mov_b32_e32 v37, v35
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v35, off offset:88
	scratch_store_b32 off, v23, off offset:68
	scratch_store_b32 off, v24, off offset:48
	v_mov_b32_e32 v25, v24
.LBB1_72:                               ; %Flow619
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_73:                               ; %Flow621
	s_and_not1_saveexec_b32 s2, s19
	s_cbranch_execz .LBB1_75
; %bb.74:
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:48
	scratch_load_b32 v16, off, off offset:32
	v_mov_b32_e32 v23, v17
	v_mov_b32_e32 v35, v37
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v16, off offset:24
	scratch_store_b32 off, v37, off offset:80
	scratch_store_b32 off, v17, off offset:60
	scratch_store_b32 off, v24, off offset:36
	v_mov_b32_e32 v25, v24
.LBB1_75:                               ; %Flow622
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_76:                               ; %Flow623
	s_and_not1_saveexec_b32 s2, s3
	s_cbranch_execz .LBB1_78
; %bb.77:
	s_clause 0x2
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b64 v[21:22], off, off offset:52
	scratch_load_b32 v16, off, off offset:24
	v_mov_b32_e32 v20, v23
	v_mov_b32_e32 v17, v23
	v_mov_b32_e32 v35, v23
	v_mov_b32_e32 v37, v23
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v25, v24 :: v_dual_mov_b32 v18, v21
	v_mov_b32_e32 v19, v22
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v24, off offset:48
	scratch_store_b32 off, v23, off offset:88
	scratch_store_b128 off, v[20:23], off offset:68
.LBB1_78:                               ; %Flow624
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_79:                               ; %Flow625
	s_and_not1_saveexec_b32 s2, s8
	s_cbranch_execz .LBB1_81
; %bb.80:
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b32 v16, off, off offset:24
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v25, v18 :: v_dual_mov_b32 v26, v19
	v_mov_b32_e32 v27, v35
	v_mov_b32_e32 v23, v35
	v_mov_b32_e32 v17, v35
	v_mov_b32_e32 v37, v35
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[24:27], off offset:48
	v_mov_b32_e32 v25, v24
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v35, off offset:88
	scratch_store_b32 off, v35, off offset:68
.LBB1_81:                               ; %Flow626
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_82:                               ; %Flow627
	s_and_not1_saveexec_b32 s2, s15
	s_cbranch_execz .LBB1_84
; %bb.83:
	s_clause 0x1
	scratch_load_b32 v16, off, off offset:32
	scratch_load_b96 v[20:22], off, off offset:48
	v_mov_b32_e32 v23, v17
	v_mov_b32_e32 v35, v17
	v_mov_b32_e32 v37, v17
	v_mov_b32_e32 v28, v17
	s_waitcnt vmcnt(1)
	scratch_store_b32 off, v16, off offset:24
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v27, v22 :: v_dual_mov_b32 v26, v21
	v_mov_b32_e32 v25, v20
	v_dual_mov_b32 v24, v20 :: v_dual_mov_b32 v19, v22
	v_mov_b32_e32 v18, v21
	s_clause 0x3
	scratch_store_b32 off, v17, off offset:88
	scratch_store_b32 off, v20, off offset:36
	scratch_store_b32 off, v17, off offset:60
	scratch_store_b96 off, v[26:28], off offset:72
.LBB1_84:                               ; %Flow628
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_85:                               ; %Flow629
	s_and_not1_saveexec_b32 s2, s10
	s_cbranch_execz .LBB1_87
; %bb.86:
	s_clause 0x1
	scratch_load_b32 v25, off, off offset:48
	scratch_load_b32 v16, off, off offset:32
	v_dual_mov_b32 v35, v18 :: v_dual_mov_b32 v36, v19
	v_mov_b32_e32 v17, v37
	v_mov_b32_e32 v23, v37
	scratch_store_b96 off, v[35:37], off offset:52
	v_mov_b32_e32 v35, v37
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v16, off offset:24
	scratch_store_b32 off, v25, off offset:36
	scratch_store_b32 off, v37, off offset:68
	scratch_store_b32 off, v37, off offset:80
	v_mov_b32_e32 v24, v25
.LBB1_87:                               ; %_Z13xsymmetry_topPfii.exit
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x1
	scratch_load_b32 v22, off, off offset:56
	scratch_load_b32 v20, off, off offset:20
	v_mov_b32_e32 v36, v19
	s_or_b32 s14, s14, exec_lo
	s_and_not1_b32 s7, s7, exec_lo
	s_waitcnt vmcnt(0)
	s_clause 0x1
	scratch_store_b32 off, v20, off offset:28
	scratch_store_b64 off, v[24:25], off offset:40
	v_mov_b32_e32 v16, v22
.LBB1_88:                               ; %Flow642
	s_or_b32 exec_lo, exec_lo, s9
	s_mov_b32 s3, 0
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
; %bb.89:                               ; %LeafBlock585
	v_cmp_ne_u32_e32 vcc_lo, 10, v46
	s_and_not1_b32 s7, s11, exec_lo
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s11, s7, s8
; %bb.90:                               ; %Flow643
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s7, s6
; %bb.91:                               ; %LeafBlock583
	v_cmp_eq_u32_e32 vcc_lo, 1, v46
	v_cmp_ne_u32_e64 s2, 1, v46
	s_and_not1_b32 s3, s3, exec_lo
	s_and_not1_b32 s6, s11, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s3, s3, s8
	s_or_b32 s11, s6, s2
; %bb.92:                               ; %Flow644
	s_or_b32 exec_lo, exec_lo, s7
	s_and_saveexec_b32 s2, s11
	s_cbranch_execz .LBB1_94
; %bb.93:                               ; %_Z8ImageFcniii.exit._crit_edge
	scratch_load_b32 v22, off, off offset:56
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v19, v11
	v_dual_mov_b32 v36, v33 :: v_dual_mov_b32 v23, v3
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v18, v10
	v_mov_b32_e32 v35, v32
	v_mov_b32_e32 v37, v34
	s_and_not1_b32 s3, s3, exec_lo
	s_or_b32 s14, s14, exec_lo
.LBB1_94:                               ; %Flow645
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s14
	s_cbranch_execz .LBB1_97
; %bb.95:
	s_clause 0x2
	scratch_load_b128 v[28:31], off, off offset:16
	scratch_load_b128 v[24:27], off, off offset:32
	scratch_load_b64 v[20:21], off, off offset:48
	s_waitcnt vmcnt(3)
	v_dual_sub_f32 v46, v22, v23 :: v_dual_sub_f32 v47, v23, v17
	s_load_b32 s1, s[0:1], 0x20
	s_mov_b32 s0, 0
	s_lshl_b32 s6, s12, 6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v46, v16, v46 :: v_dual_sub_f32 v47, v47, v35
	v_sub_f32_e32 v46, v46, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v47, v47, v37
	s_waitcnt vmcnt(1)
	v_dual_mul_f32 v54, -4.0, v29 :: v_dual_add_f32 v59, v30, v24
	v_dual_sub_f32 v53, v25, v28 :: v_dual_sub_f32 v46, v46, v19
	v_mul_f32_e32 v56, 0x40400000, v30
	v_fma_f32 v58, v29, 2.0, -v30
	v_sub_f32_e32 v51, v30, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_add_f32 v53, v26, v53 :: v_dual_add_f32 v46, v35, v46
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v52, v22, v21
	v_dual_add_f32 v60, v24, v24 :: v_dual_add_f32 v59, v25, v59
	v_dual_sub_f32 v50, v29, v31 :: v_dual_sub_f32 v49, v46, v36
	v_sub_f32_e32 v48, v22, v16
	v_sub_f32_e64 v62, -v26, v25
	v_mul_f32_e32 v55, 0x40400000, v29
	v_add_f32_e32 v51, v25, v51
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v49, v37, v49 :: v_dual_sub_f32 v48, v48, v19
	v_dual_fmamk_f32 v54, v28, 0x41400000, v54 :: v_dual_sub_f32 v61, v25, v26
	v_add_f32_e32 v51, v26, v51
	v_add_f32_e32 v50, v50, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v48, v48, v36
	v_dual_add_f32 v52, v23, v52 :: v_dual_add_f32 v63, v61, v27
	v_sub_f32_e32 v61, v61, v27
	v_dual_fmac_f32 v58, 2.0, v31 :: v_dual_add_f32 v53, v27, v53
	v_fma_f32 v60, v30, -2.0, -v60
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v62, v62, v27 :: v_dual_sub_f32 v63, v63, v20
	v_dual_sub_f32 v50, v50, v26 :: v_dual_add_f32 v61, v61, v20
	v_dual_add_f32 v52, v16, v52 :: v_dual_add_f32 v59, v26, v59
	v_dual_fmac_f32 v54, -4.0, v30 :: v_dual_sub_f32 v51, v51, v27
	v_dual_sub_f32 v58, v58, v24 :: v_dual_add_f32 v53, v20, v53
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v60, v25, v60 :: v_dual_add_f32 v59, v27, v59
	v_dual_add_f32 v62, v62, v20 :: v_dual_sub_f32 v61, v61, v22
	v_dual_sub_f32 v50, v50, v27 :: v_dual_sub_f32 v51, v51, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v52, v17, v52 :: v_dual_add_f32 v53, v22, v53
	v_dual_fmac_f32 v54, -4.0, v31 :: v_dual_add_f32 v61, v61, v16
	v_dual_add_f32 v58, v25, v58 :: v_dual_add_f32 v59, v20, v59
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v62, v62, v23 :: v_dual_add_f32 v53, v23, v53
	v_dual_add_f32 v60, v26, v60 :: v_dual_add_f32 v51, v23, v51
	v_dual_add_f32 v50, v50, v20 :: v_dual_sub_f32 v59, v59, v21
	v_dual_sub_f32 v52, v52, v18 :: v_dual_sub_f32 v61, v61, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v62, v62, v17
	v_dual_add_f32 v58, v26, v58 :: v_dual_add_f32 v53, v16, v53
	v_add_f32_e32 v60, v27, v60
	v_dual_add_f32 v50, v50, v22 :: v_dual_add_f32 v61, v61, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v59, v59, v22 :: v_dual_add_f32 v62, v62, v35
	v_fma_f32 v55, 0x40400000, v31, -v55
	v_dual_sub_f32 v52, v52, v19 :: v_dual_add_f32 v53, v17, v53
	v_dual_sub_f32 v59, v59, v16 :: v_dual_sub_f32 v62, v62, v37
	v_add_f32_e32 v58, v27, v58
	v_add_f32_e32 v60, v20, v60
	v_dual_fmac_f32 v54, -4.0, v24 :: v_dual_sub_f32 v51, v51, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v67, v61, v62
	v_dual_sub_f32 v69, v62, v49 :: v_dual_add_f32 v58, v20, v58
	v_add_f32_e32 v53, v19, v53
	v_dual_fmac_f32 v60, 2.0, v21 :: v_dual_sub_f32 v59, v59, v18
	v_dual_add_f32 v54, v25, v54 :: v_dual_add_f32 v51, v35, v51
	v_sub_f32_e32 v50, v50, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_sub_f32 v58, v58, v21 :: v_dual_sub_f32 v59, v59, v19
	v_fma_f32 v56, 0x40400000, v24, -v56
	v_dual_sub_f32 v52, v52, v35 :: v_dual_add_f32 v73, v62, v49
	v_dual_add_f32 v54, v26, v54 :: v_dual_sub_f32 v51, v51, v37
	v_sub_f32_e32 v64, v61, v62
	v_sub_f32_e64 v65, -v61, v62
	v_dual_sub_f32 v66, v62, v61 :: v_dual_sub_f32 v59, v59, v36
	v_sub_f32_e32 v68, v49, v61
	v_add_f32_e32 v70, v61, v49
	v_sub_f32_e64 v71, -v62, v49
	v_sub_f32_e64 v72, -v61, v49
	v_sub_f32_e32 v61, v61, v49
	v_dual_sub_f32 v49, v49, v62 :: v_dual_add_f32 v50, v50, v19
	v_dual_add_f32 v53, v35, v53 :: v_dual_mov_b32 v46, v42
	v_dual_mul_f32 v57, 0x40400000, v21 :: v_dual_add_f32 v56, v56, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v50, v50, v36
	v_sub_f32_e32 v52, v52, v36
	v_sub_f32_e32 v60, v60, v22
	v_fma_f32 v57, 0x40400000, v18, -v57
	v_mul_f32_e32 v77, 0x3fd55555, v56
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v75, v50, v50 :: v_dual_sub_f32 v52, v52, v37
	v_add_f32_e32 v54, v27, v54
	v_dual_mul_f32 v62, v51, v51 :: v_dual_add_f32 v53, v36, v53
	v_mul_f32_e32 v74, v52, v52
	v_add_f32_e32 v57, v57, v52
	v_fma_f32 v47, -v51, v52, v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v54, v20, v54 :: v_dual_add_f32 v53, v37, v53
	v_fma_f32 v78, v51, v51, v74
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v57, 0x3fd55555, v57 :: v_dual_add_f32 v58, v22, v58
	v_add_f32_e32 v55, v55, v50
	v_fma_f32 v63, -v50, v51, v63
	v_fma_f32 v51, v51, v51, -v74
	v_dual_fmac_f32 v62, v50, v50 :: v_dual_mul_f32 v47, 0x3e800000, v47
	v_mul_f32_e32 v76, 0x3fd55555, v55
	v_fmamk_f32 v74, v55, 0x3fd55555, v57
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v51, v59, v51
	v_fmamk_f32 v59, v55, 0x3fd55555, v77
	v_fma_f32 v48, -v50, v52, v48
	v_fma_f32 v50, v50, v75, -v78
	v_dual_fmamk_f32 v75, v56, 0x3fd55555, v57 :: v_dual_fmac_f32 v58, -2.0, v23
	v_fmac_f32_e32 v62, v52, v52
	v_sub_f32_e32 v60, v60, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v58, v16, v58
	v_dual_sub_f32 v53, v53, v62 :: v_dual_fmac_f32 v58, -2.0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v53, 0x41980000, v53 :: v_dual_sub_f32 v58, v58, v18
	v_add_f32_e32 v58, v19, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v58, -2.0, v35
	v_add_f32_e32 v58, v36, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v58, -2.0, v37
	v_sub_f32_e32 v50, v58, v50
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v79, s1, v50 :: v_dual_fmac_f32 v54, -4.0, v21
	v_fmamk_f32 v80, v50, 0xbd638e39, v47
	v_fma_f32 v47, 0xbd638e39, v50, -v47
	v_mul_f32_e32 v78, 0xbc4d5033, v53
	v_mul_f32_e32 v58, 0x3daaaaab, v51
	v_add_f32_e32 v54, v22, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v54, v23, v54
	v_add_f32_e32 v54, v16, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v54, v17, v54
	v_fmac_f32_e32 v54, -4.0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v52, v19, v54
	v_add_f32_e32 v52, v35, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v52, v36, v52
	v_add_f32_e32 v52, v37, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmamk_f32 v52, v62, 0x40f14514, v52
	v_fmamk_f32 v62, v50, 0x3ce38e39, v58
	v_fma_f32 v58, 0x3ce38e39, v50, -v58
	v_fmamk_f32 v81, v63, 0x3e800000, v62
	v_fmac_f32_e32 v62, 0xbe800000, v63
	v_mul_f32_e32 v50, 0xbc820821, v52
	v_fmamk_f32 v63, v52, 0x3d430c31, v78
	v_fmamk_f32 v78, v48, 0x3e800000, v58
	v_mul_f32_e32 v52, 0x3b820821, v52
	v_fmac_f32_e32 v58, 0xbe800000, v48
	v_fmamk_f32 v50, v53, 0xbb969026, v50
	v_sub_f32_e32 v28, v28, v63
	v_fma_f32 v56, 0x3fd55555, v56, -v57
	v_fmamk_f32 v48, v53, 0x3b5b0037, v52
	s_delay_alu instid0(VALU_DEP_4)
	v_fmamk_f32 v63, v76, 0x3dcccccd, v50
	v_fmac_f32_e32 v60, 2.0, v18
	v_fmamk_f32 v83, v57, 0xbdcccccd, v50
	v_fmamk_f32 v53, v77, 0xbdcccccd, v50
	v_fmamk_f32 v87, v56, 0xbccccccd, v48
	v_fmac_f32_e32 v63, 0x3d638e39, v79
	v_dual_sub_f32 v60, v60, v19 :: v_dual_fmamk_f32 v85, v75, 0x3ccccccd, v48
	v_fmamk_f32 v56, v56, 0x3ccccccd, v48
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v87, 0x3e000000, v71
	v_dual_fmac_f32 v53, 0xbce38e39, v79 :: v_dual_sub_f32 v54, v60, v36
	v_fma_f32 v60, 0x3fd55555, v55, -v77
	v_fma_f32 v55, 0x3fd55555, v55, -v57
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v87, s1, v47
	v_fmac_f32_e32 v85, 0x3e000000, v69
	v_fmac_f32_e32 v83, 0xbce38e39, v79
	v_sub_f32_e32 v31, v31, v63
	v_fmamk_f32 v86, v55, 0xbccccccd, v48
	v_fmamk_f32 v55, v55, 0x3ccccccd, v48
	v_sub_f32_e32 v17, v17, v87
	v_fma_f32 v51, v51, s1, -v54
	v_fmac_f32_e32 v85, s1, v80
	v_add_f32_e32 v69, 0, v86
	v_add_f32_e32 v55, 0, v55
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v53, 0x3daaaaab, v51
	v_fmac_f32_e32 v83, 0xbdaaaaab, v51
	v_sub_f32_e32 v23, v23, v85
	v_fmac_f32_e32 v55, 0xbd2aaaab, v54
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v69, 0xbd2aaaab, v54 :: v_dual_sub_f32 v30, v30, v53
	v_sub_f32_e32 v21, v21, v83
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v55, 0x3e000000, v72
	v_fmamk_f32 v52, v76, 0xbdcccccd, v50
	v_fmamk_f32 v76, v77, 0x3dcccccd, v50
	v_fmamk_f32 v77, v59, 0x3ccccccd, v48
	v_fmac_f32_e32 v50, 0x3dcccccd, v57
	v_fmamk_f32 v59, v59, 0xbccccccd, v48
	v_fmac_f32_e32 v52, 0x3d638e39, v79
	v_fmac_f32_e32 v69, 0x3e000000, v70
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v50, 0xbce38e39, v79
	v_add_f32_e32 v59, 0, v59
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v29, v29, v52 :: v_dual_fmamk_f32 v84, v74, 0x3ccccccd, v48
	v_dual_fmamk_f32 v57, v74, 0xbccccccd, v48 :: v_dual_add_f32 v74, 0, v77
	v_fmac_f32_e32 v59, 0x3d2aaaab, v54
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v56, 0x3e000000, v73 :: v_dual_add_f32 v77, 0, v84
	v_dual_add_f32 v57, 0, v57 :: v_dual_fmac_f32 v50, 0xbdaaaaab, v51
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v59, 0x3e000000, v66 :: v_dual_fmac_f32 v56, s1, v47
	v_fmac_f32_e32 v77, 0xbd2aaaab, v54
	v_fmac_f32_e32 v74, 0x3d2aaaab, v54
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v18, v18, v50 :: v_dual_fmac_f32 v59, s1, v81
	v_sub_f32_e32 v35, v35, v56
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v77, 0x3e000000, v68
	v_dual_fmac_f32 v74, 0x3e000000, v64 :: v_dual_sub_f32 v27, v27, v59
	v_fmac_f32_e32 v76, 0xbce38e39, v79
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v74, s1, v81
	v_fmamk_f32 v82, v60, 0xbccccccd, v48
	v_fmamk_f32 v60, v60, 0x3ccccccd, v48
	v_fmac_f32_e32 v48, 0xbccccccd, v75
	v_dual_fmac_f32 v76, 0x3daaaaab, v51 :: v_dual_sub_f32 v25, v25, v74
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v75, 0, v82 :: v_dual_fmac_f32 v48, 0x3e000000, v49
	v_fmac_f32_e32 v57, 0xbd2aaaab, v54
	v_dual_fmac_f32 v75, 0x3d2aaaab, v54 :: v_dual_sub_f32 v24, v24, v76
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v48, s1, v80 :: v_dual_fmac_f32 v57, 0x3e000000, v61
	v_fmac_f32_e32 v75, 0x3e000000, v65
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v37, v37, v48
	v_fmac_f32_e32 v57, s1, v78
	v_fmac_f32_e32 v55, s1, v58
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v75, s1, v62
	v_fmac_f32_e32 v77, s1, v78
	v_dual_fmac_f32 v69, s1, v58 :: v_dual_sub_f32 v36, v36, v57
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v19, v19, v55 :: v_dual_add_f32 v60, 0, v60
	v_sub_f32_e32 v26, v26, v75
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v22, v22, v77
	v_sub_f32_e32 v16, v16, v69
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v60, 0x3d2aaaab, v54
	v_fmac_f32_e32 v60, 0x3e000000, v67
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v60, s1, v62
	v_sub_f32_e32 v20, v20, v60
	s_clause 0x4
	scratch_store_b128 off, v[28:31], off offset:16
	scratch_store_b128 off, v[24:27], off offset:32
	scratch_store_b128 off, v[20:23], off offset:48
	scratch_store_b128 off, v[16:19], off offset:64
	scratch_store_b96 off, v[35:37], off offset:80
.LBB1_96:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s0, 16
	v_max_i32_e32 v16, 0, v46
	scratch_load_b32 v18, off, s1
	v_add_nc_u32_e32 v46, s6, v46
	s_add_i32 s0, s0, 4
	v_cmp_gt_i32_e32 vcc_lo, s20, v16
	s_cmpk_lg_i32 s0, 0x4c
	v_cndmask_b32_e32 v16, s13, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s4, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[16:17], v18, off
	s_cbranch_scc1 .LBB1_96
.LBB1_97:                               ; %Flow646
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB1_99
; %bb.98:
	v_max_i32_e32 v18, 0, v42
	v_mad_u64_u32 v[16:17], null, 0xfffffc40, s12, v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s20, v18
	v_add_nc_u32_e32 v24, s16, v16
	v_dual_cndmask_b32 v17, s13, v18 :: v_dual_add_nc_u32 v20, v38, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v18, 31, v17
	v_max_i32_e32 v21, 0, v20
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v22, v38, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_max_i32_e32 v23, 0, v22
	v_add_nc_u32_e32 v19, v38, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v19, 0, v19
	v_cmp_gt_i32_e32 vcc_lo, s20, v19
	v_cndmask_b32_e32 v19, s13, v19, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v21
	v_cndmask_b32_e32 v21, s13, v21, vcc_lo
	v_add_co_u32 v17, vcc_lo, s4, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v22, 31, v21
	global_store_b32 v[17:18], v12, off
	v_add_nc_u32_e32 v12, v38, v24
	v_ashrrev_i32_e32 v20, 31, v19
	v_max_i32_e32 v12, 0, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	v_add_co_u32 v16, vcc_lo, s4, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v20, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v23
	v_lshlrev_b64 v[18:19], 2, v[21:22]
	v_add_nc_u32_e32 v22, s18, v24
	global_store_b32 v[16:17], v15, off
	v_cndmask_b32_e32 v20, s13, v23, vcc_lo
	v_add_co_u32 v18, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v21, 31, v20
	v_add_nc_u32_e32 v23, v38, v22
	v_cmp_gt_i32_e32 vcc_lo, s20, v12
	global_store_b32 v[18:19], v4, off
	v_add_nc_u32_e32 v19, s18, v22
	v_lshlrev_b64 v[15:16], 2, v[20:21]
	v_max_i32_e32 v4, 0, v23
	v_cndmask_b32_e32 v17, s13, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, s4, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s20, v4
	global_store_b32 v[15:16], v13, off
	v_cndmask_b32_e32 v12, s13, v4, vcc_lo
	v_add_nc_u32_e32 v4, v38, v19
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_nc_u32_e32 v19, s18, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v13, 31, v12
	v_max_i32_e32 v4, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_add_nc_u32_e32 v21, s18, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v15, vcc_lo, s4, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v18, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v4
	v_add_nc_u32_e32 v20, v38, v19
	global_store_b32 v[15:16], v14, off
	v_cndmask_b32_e32 v17, s13, v4, vcc_lo
	v_max_i32_e32 v4, 0, v20
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s20, v4
	v_ashrrev_i32_e32 v18, 31, v17
	global_store_b32 v[12:13], v7, off
	v_add_nc_u32_e32 v7, s18, v21
	v_dual_cndmask_b32 v19, s13, v4 :: v_dual_add_nc_u32 v4, v38, v21
	v_lshlrev_b64 v[14:15], 2, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v20, 31, v19
	v_max_i32_e32 v4, 0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s20, v4
	v_lshlrev_b64 v[14:15], 2, v[19:20]
	global_store_b32 v[12:13], v0, off
	v_cndmask_b32_e32 v16, s13, v4, vcc_lo
	v_add_nc_u32_e32 v4, v38, v7
	v_add_nc_u32_e32 v7, s18, v7
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v0, v38, v7
	v_add_nc_u32_e32 v7, s18, v7
	v_max_i32_e32 v18, 0, v4
	global_store_b32 v[14:15], v5, off
	v_max_i32_e32 v0, 0, v0
	v_add_nc_u32_e32 v15, v38, v7
	v_ashrrev_i32_e32 v17, 31, v16
	v_cmp_gt_i32_e32 vcc_lo, s20, v18
	v_add_nc_u32_e32 v7, s18, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[16:17]
	v_cndmask_b32_e32 v12, s13, v18, vcc_lo
	v_add_nc_u32_e32 v16, v38, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_ashrrev_i32_e32 v13, 31, v12
	global_store_b32 v[4:5], v6, off
	v_cndmask_b32_e32 v14, s13, v0, vcc_lo
	v_max_i32_e32 v0, 0, v15
	v_lshlrev_b64 v[4:5], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v15, 31, v14
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[14:15]
	v_cndmask_b32_e32 v6, s13, v0, vcc_lo
	v_max_i32_e32 v0, 0, v16
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_add_nc_u32_e32 v16, s18, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_ashrrev_i32_e32 v7, 31, v6
	global_store_b32 v[4:5], v10, off
	v_add_nc_u32_e32 v10, v38, v43
	v_cndmask_b32_e32 v14, s13, v0, vcc_lo
	v_add_nc_u32_e32 v0, v38, v16
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_max_i32_e32 v0, 0, v0
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[4:5], 2, v[6:7]
	global_store_b32 v[12:13], v33, off
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_lshlrev_b64 v[6:7], 2, v[14:15]
	v_cndmask_b32_e32 v12, s13, v0, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_nc_u32_e32 v0, s17, v16
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_clause 0x1
	global_store_b32 v[4:5], v34, off
	global_store_b32 v[6:7], v11, off
	v_add_nc_u32_e32 v11, v38, v39
	v_add_nc_u32_e32 v14, v38, v0
	v_max_i32_e32 v6, 0, v10
	v_add_co_u32 v4, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_i32_e32 v7, 0, v14
	v_cmp_gt_i32_e32 vcc_lo, s20, v6
	v_max_i32_e32 v12, 0, v11
	v_add3_u32 v0, v0, s16, v38
	global_store_b32 v[4:5], v32, off
	v_cndmask_b32_e32 v6, s13, v6, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v7
	v_max_i32_e32 v0, 0, v0
	v_cndmask_b32_e32 v10, s13, v7, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v12
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v11, 31, v10
	v_cndmask_b32_e32 v4, s13, v12, vcc_lo
	v_add_co_u32 v12, vcc_lo, s4, v40
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v41, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_cndmask_b32_e32 v14, s13, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, s4, v10
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	s_clause 0x4
	global_store_b32 v[12:13], v1, off
	global_store_b32 v[6:7], v8, off
	global_store_b32 v[10:11], v9, off
	global_store_b32 v[4:5], v2, off
	global_store_b32 v[14:15], v3, off
.LBB1_99:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10update_topPfS_S_S_fmii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 96
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 88
		.amdhsa_next_free_sgpr 31
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10update_topPfS_S_S_fmii, .Lfunc_end1-_Z10update_topPfS_S_S_fmii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 11500
; NumSgprs: 33
; NumVgprs: 88
; ScratchSize: 96
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 10
; NumSGPRsForWavesPerEU: 33
; NumVGPRsForWavesPerEU: 88
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10update_botPfS_S_S_fmii ; -- Begin function _Z10update_botPfS_S_S_fmii
	.globl	_Z10update_botPfS_S_S_fmii
	.p2align	8
	.type	_Z10update_botPfS_S_S_fmii,@function
_Z10update_botPfS_S_S_fmii:             ; @_Z10update_botPfS_S_S_fmii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x44
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
                                        ; implicit-def: $sgpr4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	v_mad_u64_u32 v[38:39], null, s14, s3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v38
	v_add_f32_e32 v1, 0xc1bc0000, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[39:40], null, s15, s2, v[0:1]
	v_cmp_nlt_f32_e64 s3, |v1|, 4.0
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_f32_e64 |v1|, 4.0
; %bb.1:
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v0, v39
	s_and_not1_b32 s3, s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, 0xc1bc0000, v0
	v_cmp_nlt_f32_e64 s4, |v0|, 4.0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s5, s4, exec_lo
	s_mov_b32 s4, 10
	s_or_b32 s3, s3, s5
; %bb.2:                                ; %Flow648
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v31, s4
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB2_12
; %bb.3:                                ; %NodeBlock
	s_mov_b32 s3, 0
	s_mov_b32 s5, exec_lo
                                        ; implicit-def: $sgpr4
	v_cmpx_lt_i32_e32 62, v39
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB2_7
; %bb.4:                                ; %LeafBlock576
	s_mov_b32 s3, -1
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $sgpr4
	v_cmpx_eq_u32_e32 63, v39
; %bb.5:
	s_movk_i32 s4, 0x64
	s_xor_b32 s3, exec_lo, -1
; %bb.6:                                ; %Flow643
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, exec_lo
.LBB2_7:                                ; %Flow642
	s_or_saveexec_b32 s5, s5
	v_mov_b32_e32 v31, s4
	s_xor_b32 exec_lo, exec_lo, s5
; %bb.8:                                ; %LeafBlock
	v_cmp_ne_u32_e32 vcc_lo, 0, v39
	v_mov_b32_e32 v31, 0xc8
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s3, s4
; %bb.9:                                ; %Flow644
	s_or_b32 exec_lo, exec_lo, s5
	s_and_saveexec_b32 s4, s3
; %bb.10:
	v_cmp_eq_u32_e32 vcc_lo, 63, v38
	v_cndmask_b32_e64 v0, 0, 25, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v38
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v31, 26, v0, vcc_lo
; %bb.11:                               ; %Flow645
	s_or_b32 exec_lo, exec_lo, s4
.LBB2_12:                               ; %Flow649
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x28
	s_load_b256 s[4:11], s[0:1], 0x0
	v_add_nc_u32_e32 v3, 0x7f, v39
	v_add_nc_u32_e32 v4, 0x101, v39
                                        ; implicit-def: $vgpr36
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s20, s12, 0x4c0
	s_lshl_b64 s[18:19], s[12:13], 7
	s_lshl_b64 s[16:17], s[12:13], 6
	s_add_i32 s13, s20, -1
	v_add_nc_u32_e32 v0, 64, v39
	v_add_nc_u32_e32 v1, -1, v38
	v_add_nc_u32_e32 v2, 1, v38
	s_mul_i32 s19, s12, 0xc0
	v_mad_u64_u32 v[42:43], null, v39, s12, v[38:39]
	v_mul_lo_u32 v46, v0, s12
	v_mul_lo_u32 v0, v3, s12
	v_mul_lo_u32 v14, v4, s12
	s_mul_i32 s2, s12, 0x140
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v43, 31, v42
	v_add_nc_u32_e32 v5, v1, v46
	v_add_nc_u32_e32 v45, s18, v46
	v_add_nc_u32_e32 v6, v38, v0
	v_add_nc_u32_e32 v0, s19, v0
	v_lshlrev_b64 v[3:4], 2, v[42:43]
	v_max_i32_e32 v5, 0, v5
	v_add_nc_u32_e32 v7, v2, v45
	v_max_i32_e32 v6, 0, v6
	v_add_nc_u32_e32 v8, v1, v0
	v_add_nc_u32_e32 v15, v38, v14
	v_cmp_gt_i32_e32 vcc_lo, s20, v5
	v_max_i32_e32 v9, 0, v7
	v_add_nc_u32_e32 v17, s19, v14
	v_max_i32_e32 v10, 0, v8
	v_cndmask_b32_e32 v5, s13, v5, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v6
	v_add_nc_u32_e32 v20, -1, v39
	v_add_nc_u32_e32 v29, s16, v17
	v_cndmask_b32_e32 v7, s13, v6, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v9
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v23, v1, v29
	v_ashrrev_i32_e32 v8, 31, v7
	v_cndmask_b32_e32 v9, s13, v9, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v10
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add3_u32 v0, v0, s16, v2
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_dual_cndmask_b32 v11, s13, v10 :: v_dual_add_nc_u32 v16, v2, v17
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_max_i32_e32 v0, 0, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_ashrrev_i32_e32 v12, 31, v11
	v_cndmask_b32_e32 v13, s13, v0, vcc_lo
	v_max_i32_e32 v0, 0, v15
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_ashrrev_i32_e32 v14, 31, v13
	v_cndmask_b32_e32 v15, s13, v0, vcc_lo
	v_max_i32_e32 v0, 0, v16
	v_add_co_u32 v18, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_lshlrev_b64 v[11:12], 2, v[13:14]
	v_ashrrev_i32_e32 v16, 31, v15
	v_cndmask_b32_e32 v13, s13, v0, vcc_lo
	v_add_nc_u32_e32 v0, 0x240, v39
	v_add_co_u32 v21, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v22, vcc_lo, s7, v12, vcc_lo
	v_lshlrev_b64 v[11:12], 2, v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v0, v0, s12
	v_ashrrev_i32_e32 v14, 31, v13
	v_max_i32_e32 v15, 0, v23
	v_add_co_u32 v23, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v24, vcc_lo, s7, v12, vcc_lo
	v_add_nc_u32_e32 v11, v38, v0
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_cmp_gt_i32_e32 vcc_lo, s20, v15
	v_add_nc_u32_e32 v43, s16, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_max_i32_e32 v11, 0, v11
	v_cndmask_b32_e32 v25, s13, v15, vcc_lo
	v_add_co_u32 v27, vcc_lo, s6, v13
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v14, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v26, 31, v25
	s_clause 0x7
	global_load_b32 v12, v[3:4], off
	global_load_b32 v13, v[5:6], off
	global_load_b32 v15, v[9:10], off
	global_load_b32 v14, v[7:8], off
	global_load_b32 v5, v[18:19], off
	global_load_b32 v6, v[21:22], off
	global_load_b32 v4, v[23:24], off
	global_load_b32 v7, v[27:28], off
	v_add_nc_u32_e32 v3, 0x2bf, v39
	v_add_nc_u32_e32 v44, s18, v43
	v_cndmask_b32_e32 v10, s13, v11, vcc_lo
	v_add_nc_u32_e32 v0, v1, v43
	v_lshlrev_b64 v[8:9], 2, v[25:26]
	v_mad_u64_u32 v[18:19], null, v3, s12, v[38:39]
	v_add_nc_u32_e32 v3, v2, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_max_i32_e32 v0, 0, v0
	v_ashrrev_i32_e32 v11, 31, v10
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_max_i32_e32 v16, 0, v18
	v_max_i32_e32 v3, 0, v3
	v_lshlrev_b64 v[40:41], 2, v[10:11]
	v_cndmask_b32_e32 v21, s13, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s20, v16
	global_load_b32 v0, v[8:9], off
	v_mad_u64_u32 v[23:24], null, 0x380, s15, v[39:40]
	v_cndmask_b32_e32 v8, s13, v16, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v3
	v_ashrrev_i32_e32 v22, 31, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v9, 31, v8
	v_cndmask_b32_e32 v10, s13, v3, vcc_lo
	v_add3_u32 v3, v29, s2, v38
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	v_add_co_u32 v18, vcc_lo, s10, v40
	v_add_co_ci_u32_e32 v19, vcc_lo, s11, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_i32_e32 v3, 0, v3
	v_add_co_u32 v21, vcc_lo, s10, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, s11, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s20, v3
	v_ashrrev_i32_e32 v11, 31, v10
	v_mad_u64_u32 v[26:27], null, v23, s12, v[38:39]
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_cndmask_b32_e32 v24, s13, v3, vcc_lo
	v_lshl_add_u32 v3, s15, 6, v23
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_lshl_add_u32 v23, s15, 10, v20
	s_mul_i32 s2, s20, s15
	v_ashrrev_i32_e32 v25, 31, v24
	v_add_co_u32 v8, vcc_lo, s10, v8
	v_max_i32_e32 v16, 0, v26
	v_mad_u64_u32 v[26:27], null, v3, s12, v[1:2]
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[24:25], 2, v[24:25]
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	v_mad_u64_u32 v[27:28], null, v23, s12, v[38:39]
	v_add_co_u32 v23, vcc_lo, s10, v24
	v_add_co_ci_u32_e32 v24, vcc_lo, s11, v25, vcc_lo
	v_lshl_add_u32 v1, s15, 7, v3
	v_cmp_gt_i32_e32 vcc_lo, s2, v16
	v_max_i32_e32 v3, 0, v26
	s_add_i32 s3, s2, -1
	s_mov_b32 s11, 0
	v_cndmask_b32_e32 v25, s3, v16, vcc_lo
	v_max_i32_e32 v16, 0, v27
	v_cmp_gt_i32_e32 vcc_lo, s2, v3
	v_mad_u64_u32 v[27:28], null, v1, s12, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v26, 31, v25
	v_cndmask_b32_e32 v28, s3, v3, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s2, v16
	v_add_nc_u32_e32 v17, 1, v39
	v_ashrrev_i32_e32 v29, 31, v28
	v_cndmask_b32_e32 v32, s3, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[1:2], null, 0x480, s15, v[17:18]
	v_max_i32_e32 v16, 0, v27
	v_ashrrev_i32_e32 v33, 31, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s2, v16
	v_mad_u64_u32 v[34:35], null, v1, s12, v[38:39]
	s_clause 0x4
	global_load_b32 v1, v[18:19], off
	global_load_b32 v2, v[21:22], off
	global_load_b32 v3, v[8:9], off
	global_load_b32 v8, v[10:11], off
	global_load_b32 v9, v[23:24], off
	v_lshlrev_b64 v[10:11], 2, v[25:26]
	v_cndmask_b32_e32 v18, s3, v16, vcc_lo
	v_lshlrev_b64 v[21:22], 2, v[28:29]
	v_lshlrev_b64 v[23:24], 2, v[32:33]
	v_max_i32_e32 v16, 0, v34
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s2, v16
	v_ashrrev_i32_e32 v19, 31, v18
	s_mov_b32 s2, 0
	v_cndmask_b32_e32 v25, s3, v16, vcc_lo
	v_add_co_u32 v21, vcc_lo, s8, v21
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_add_co_ci_u32_e32 v22, vcc_lo, s9, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v26, 31, v25
	v_add_co_u32 v23, vcc_lo, s8, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s9, v24, vcc_lo
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	v_add_co_u32 v18, vcc_lo, s8, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
                                        ; implicit-def: $vgpr16
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v25, vcc_lo, s8, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, s9, v26, vcc_lo
	s_clause 0x4
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v[21:22], off
	global_load_b32 v32, v[23:24], off
	global_load_b32 v33, v[18:19], off
	global_load_b32 v34, v[25:26], off
	s_add_i32 s8, s15, 2
	s_mov_b32 s15, 0
                                        ; implicit-def: $vgpr22
	s_waitcnt vmcnt(15)
	scratch_store_b128 off, v[12:15], off offset:16
	s_waitcnt vmcnt(11)
	scratch_store_b128 off, v[4:7], off offset:32
	s_waitcnt vmcnt(7)
	scratch_store_b128 off, v[0:3], off offset:48
	s_waitcnt vmcnt(3)
	scratch_store_b128 off, v[8:11], off offset:64
	s_waitcnt vmcnt(0)
	scratch_store_b96 off, v[32:34], off offset:80
	v_cmpx_lt_i32_e32 25, v31
	s_xor_b32 s9, exec_lo, s3
	s_cbranch_execz .LBB2_58
; %bb.13:                               ; %NodeBlock592
	s_mov_b32 s3, 0
	s_mov_b32 s10, 0
	s_mov_b32 s17, 0
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	v_cmpx_lt_i32_e32 0x63, v31
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB2_29
; %bb.14:                               ; %NodeBlock590
	s_mov_b32 s17, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	v_cmpx_lt_i32_e32 0xc7, v31
	s_xor_b32 s17, exec_lo, s17
	s_cbranch_execz .LBB2_22
; %bb.15:                               ; %.preheader389.preheader
	v_mad_u64_u32 v[18:19], null, v17, s12, v[38:39]
	s_lshl_b32 s3, s12, 6
.LBB2_16:                               ; %.preheader389
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_max_i32_e32 v16, 0, v18
	v_add_nc_u32_e32 v18, s3, v18
	s_add_i32 s11, s10, 16
	s_add_i32 s10, s10, 4
	s_cmpk_eq_i32 s10, 0x4c
	v_cmp_gt_i32_e32 vcc_lo, s20, v16
	v_cndmask_b32_e32 v16, s13, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s6, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
	global_load_b32 v16, v[16:17], off
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v16, s11
	s_cbranch_scc0 .LBB2_16
; %bb.17:
	s_clause 0x4
	scratch_load_b128 v[47:50], off, off offset:16
	scratch_load_b128 v[24:27], off, off offset:32
	scratch_load_b128 v[20:23], off, off offset:48
	scratch_load_b128 v[16:19], off, off offset:64
	scratch_load_b96 v[28:30], off, off offset:80
	v_mov_b32_e32 v35, 0x3c03126f
	v_mov_b32_e32 v36, 0xbc03126f
	s_mov_b32 s3, 0
	s_mov_b32 s21, 0
	s_mov_b32 s10, 0
	s_mov_b32 s11, exec_lo
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v37, v47, v48
	v_mul_f32_e32 v51, 0xc1300000, v48
	v_mul_f32_e32 v52, -4.0, v48
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v58, v23, v17
	v_fma_f32 v48, v48, 2.0, -v49
	v_dual_mul_f32 v53, 4.0, v24 :: v_dual_add_f32 v62, v37, v49
	v_fma_f32 v54, -4.0, v21, v22
	v_dual_add_f32 v56, v49, v24 :: v_dual_sub_f32 v61, v22, v23
	v_sub_f32_e32 v57, v25, v26
	v_dual_sub_f32 v59, v22, v16 :: v_dual_fmac_f32 v48, 2.0, v50
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmamk_f32 v37, v47, 0xc1f00000, v51 :: v_dual_add_f32 v56, v56, v25
	v_dual_add_f32 v55, v24, v24 :: v_dual_add_f32 v54, v54, v23
	v_sub_f32_e64 v60, -v26, v25
	s_waitcnt vmcnt(0)
	v_dual_fmamk_f32 v47, v47, 0x41400000, v52 :: v_dual_sub_f32 v58, v58, v28
	v_fma_f32 v51, 4.0, v50, v52
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmac_f32 v53, -4.0, v49 :: v_dual_add_f32 v60, v60, v27
	v_dual_fmac_f32 v52, 2.0, v49 :: v_dual_add_f32 v63, v57, v27
	v_dual_add_f32 v62, v62, v50 :: v_dual_sub_f32 v59, v59, v19
	v_dual_sub_f32 v48, v48, v24 :: v_dual_fmac_f32 v37, 0xc1300000, v49
	v_fma_f32 v55, v49, -2.0, -v55
	v_add_f32_e32 v61, v61, v16
	v_dual_fmac_f32 v47, -4.0, v49 :: v_dual_add_f32 v58, v58, v30
	v_dual_add_f32 v49, v51, v25 :: v_dual_add_f32 v60, v60, v20
	v_dual_add_f32 v51, v25, v53 :: v_dual_add_f32 v62, v62, v24
	v_dual_add_f32 v53, v54, v16 :: v_dual_add_f32 v54, v56, v26
	v_dual_sub_f32 v56, v63, v20 :: v_dual_fmac_f32 v37, 0xc1300000, v50
	v_add_f32_e32 v48, v25, v48
	v_dual_sub_f32 v57, v57, v27 :: v_dual_fmac_f32 v52, -4.0, v50
	v_sub_f32_e32 v49, v49, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v55, v25, v55 :: v_dual_add_f32 v48, v26, v48
	v_dual_fmac_f32 v47, -4.0, v50 :: v_dual_fmac_f32 v52, 2.0, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v57, v57, v20
	v_fmac_f32_e32 v37, 0xc1300000, v24
	v_dual_add_f32 v59, v59, v29 :: v_dual_add_f32 v50, v26, v51
	v_dual_fmac_f32 v47, -4.0, v24 :: v_dual_sub_f32 v24, v49, v27
	v_dual_sub_f32 v61, v61, v17 :: v_dual_mul_f32 v58, 0x3e800000, v58
	v_add_f32_e32 v51, v53, v17
	v_add_f32_e32 v53, v54, v27
	v_dual_add_f32 v54, v26, v55 :: v_dual_sub_f32 v55, v57, v22
	v_add_f32_e32 v24, v24, v20
	v_add_f32_e32 v57, v60, v23
	v_dual_sub_f32 v60, v61, v19 :: v_dual_add_f32 v61, v62, v25
	v_dual_add_f32 v48, v27, v48 :: v_dual_sub_f32 v49, v50, v27
	v_add_f32_e32 v50, v25, v52
	v_dual_add_f32 v52, v53, v20 :: v_dual_add_f32 v53, v27, v54
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v48, v20, v48
	v_dual_add_f32 v54, v55, v16 :: v_dual_sub_f32 v55, v57, v17
	v_add_f32_e32 v24, v24, v22
	v_fmac_f32_e32 v51, 4.0, v18
	v_dual_add_f32 v57, v60, v28 :: v_dual_add_f32 v60, v61, v26
	v_dual_fmac_f32 v37, 0x41000000, v25 :: v_dual_add_f32 v50, v26, v50
	v_add_f32_e32 v25, v25, v47
	v_sub_f32_e32 v47, v49, v20
	v_dual_sub_f32 v49, v51, v19 :: v_dual_sub_f32 v24, v24, v16
	v_sub_f32_e32 v51, v52, v21
	v_dual_add_f32 v52, v20, v53 :: v_dual_fmac_f32 v37, 0x41000000, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v24, v24, v19
	v_fmac_f32_e32 v52, 2.0, v21
	v_dual_add_f32 v25, v26, v25 :: v_dual_add_f32 v26, v47, v23
	v_sub_f32_e32 v47, v49, v28
	v_fmac_f32_e32 v37, 0x41000000, v27
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v25, v27, v25
	v_add_f32_e32 v49, v27, v50
	v_dual_sub_f32 v53, v54, v19 :: v_dual_add_f32 v54, v55, v28
	v_sub_f32_e32 v55, v57, v29
	v_dual_add_f32 v57, v60, v27 :: v_dual_sub_f32 v26, v26, v17
	v_sub_f32_e32 v50, v51, v22
	v_sub_f32_e32 v27, v47, v29
	v_sub_f32_e32 v47, v48, v21
	v_add_f32_e32 v48, v20, v49
	v_add_f32_e32 v51, v53, v29
	v_sub_f32_e32 v53, v54, v30
	v_dual_sub_f32 v49, v50, v16 :: v_dual_sub_f32 v50, v52, v22
	v_dual_add_f32 v54, v55, v30 :: v_dual_add_f32 v55, v57, v20
	v_dual_fmac_f32 v48, 2.0, v21 :: v_dual_fmac_f32 v37, 0x41000000, v20
	v_dual_add_f32 v20, v20, v25 :: v_dual_add_f32 v25, v26, v28
	v_add_f32_e32 v26, v22, v47
	v_sub_f32_e32 v52, v51, v53
	v_sub_f32_e64 v57, -v51, v53
	v_sub_f32_e32 v60, v53, v51
	v_dual_sub_f32 v62, v54, v51 :: v_dual_sub_f32 v63, v53, v54
	v_add_f32_e32 v64, v51, v54
	v_sub_f32_e64 v65, -v53, v54
	v_sub_f32_e64 v66, -v51, v54
	v_add_f32_e32 v67, v53, v54
	v_dual_sub_f32 v47, v50, v16 :: v_dual_fmac_f32 v20, -4.0, v21
	v_add_f32_e32 v61, v51, v53
	v_dual_sub_f32 v50, v24, v29 :: v_dual_sub_f32 v51, v51, v54
	v_dual_fmac_f32 v37, 0xc1300000, v21 :: v_dual_fmac_f32 v26, -2.0, v23
	v_sub_f32_e32 v53, v54, v53
	v_add_f32_e32 v54, v55, v21
	v_sub_f32_e32 v55, v27, v30
	v_sub_f32_e32 v27, v49, v18
	v_add_f32_e32 v21, v22, v48
	v_dual_fmac_f32 v37, 0x41000000, v22 :: v_dual_add_f32 v20, v22, v20
	v_add_f32_e32 v49, v54, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v22, v16, v26 :: v_dual_fmac_f32 v21, -2.0, v23
	v_dual_fmac_f32 v37, 0x41000000, v23 :: v_dual_add_f32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v47, 2.0, v18 :: v_dual_fmac_f32 v22, -2.0, v17
	v_sub_f32_e32 v54, v25, v30
	v_add_f32_e32 v25, v49, v23
	v_add_f32_e32 v21, v16, v21
	v_dual_fmac_f32 v37, 0x41000000, v16 :: v_dual_add_f32 v48, v50, v54
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f32_e32 v25, v25, v16
	v_add_f32_e32 v16, v16, v20
	v_sub_f32_e32 v26, v47, v19
	v_sub_f32_e32 v20, v22, v18
	v_add_f32_e32 v16, v17, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v72, v26, v29
	v_add_f32_e32 v69, v54, v55
	v_sub_f32_e32 v70, v50, v55
	v_sub_f32_e32 v24, v27, v19
	v_fmac_f32_e32 v16, -4.0, v18
	v_add_f32_e32 v68, v50, v55
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v24, v24, v29
	v_dual_add_f32 v16, v19, v16 :: v_dual_add_f32 v25, v25, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v23, 0x3daaaaab, v24
	v_dual_add_f32 v16, v28, v16 :: v_dual_fmac_f32 v21, -2.0, v17
	v_sub_f32_e32 v22, v24, v72
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v24, v25, v18
	v_dual_add_f32 v16, v29, v16 :: v_dual_fmac_f32 v37, 0x41000000, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v17, v19, v20 :: v_dual_add_f32 v20, v24, v19
	v_sub_f32_e32 v71, v54, v55
	v_dual_add_f32 v16, v30, v16 :: v_dual_fmac_f32 v37, 0xc1300000, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v21, 2.0, v18 :: v_dual_add_f32 v20, v20, v28
	v_sub_f32_e32 v49, v50, v54
	v_dual_fmac_f32 v37, 0x41000000, v19 :: v_dual_add_f32 v18, v19, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v20, v29
	v_fmac_f32_e32 v37, 0x41000000, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v18, -2.0, v28 :: v_dual_fmac_f32 v37, 0x41000000, v29
	v_add_f32_e32 v20, v29, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v37, 0x41000000, v30
	v_add_f32_e32 v19, v19, v30
	v_dual_fmac_f32 v20, -2.0, v30 :: v_dual_mul_f32 v75, 0x3b5b0037, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, 0x3d579436, v19
	v_fmamk_f32 v26, v37, 0xbb969026, v35
	v_dual_fmac_f32 v36, 0x3d579436, v19 :: v_dual_fmac_f32 v17, -2.0, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v75, 0x3d579436, v19
	v_mul_f32_e32 v18, 0x3d579436, v19
	v_fmac_f32_e32 v35, 0x3b5b0037, v37
	v_fmamk_f32 v47, v37, 0xbb969026, v36
	v_add_f32_e32 v17, v29, v17
	v_fmac_f32_e32 v75, 0x3b820821, v16
	v_fmac_f32_e32 v36, 0x3b5b0037, v37
	v_fmac_f32_e32 v35, 0x3b820821, v16
	v_fmac_f32_e32 v47, 0xbc820821, v16
	v_fmac_f32_e32 v17, -2.0, v30
	v_fmac_f32_e32 v75, 0xbccccccd, v68
	v_fma_f32 v30, 0x3d579436, v19, 0
	v_fmac_f32_e32 v36, 0x3b820821, v16
	v_fmamk_f32 v19, v49, 0xbccccccd, v35
	v_fmamk_f32 v28, v17, 0x3ce38e39, v23
	v_fma_f32 v29, 0x3ce38e39, v17, -v23
	v_fmamk_f32 v23, v37, 0xbc4d5033, v18
	v_fmac_f32_e32 v75, 0x3c638e39, v20
	v_fmac_f32_e32 v18, 0xbb969026, v37
	v_fmamk_f32 v74, v56, 0x3e800000, v28
	v_fmac_f32_e32 v28, 0xbe800000, v56
	v_fmamk_f32 v24, v16, 0x3d430c31, v23
	v_fmamk_f32 v23, v69, 0x3ccccccd, v35
	v_fmac_f32_e32 v75, 0xbd2aaaab, v72
	v_fmac_f32_e32 v19, 0x3c638e39, v20
	v_fmamk_f32 v21, v37, 0xbb969026, v30
	v_fmac_f32_e32 v47, 0x3dcccccd, v54
	v_fmac_f32_e32 v23, 0x3e000000, v63
	v_fmac_f32_e32 v75, 0x3e000000, v51
	v_fmac_f32_e32 v19, 0x3d2aaaab, v72
	v_fmac_f32_e32 v21, 0xbc820821, v16
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v23, 0xbce38e39, v20
	v_fmamk_f32 v56, v59, 0x3e800000, v29
	v_fmamk_f32 v73, v17, 0xbd638e39, v58
	v_fma_f32 v58, 0xbd638e39, v17, -v58
	v_dual_add_f32 v76, 0xbc03126f, v30 :: v_dual_sub_f32 v17, v17, v20
	v_fmac_f32_e32 v29, 0xbe800000, v59
	v_add_f32_e32 v59, 0x3c03126f, v30
	v_fmac_f32_e32 v19, 0x3e000000, v57
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v76, 0x3b5b0037, v37
	v_fmac_f32_e32 v26, 0xbc820821, v16
	v_fmac_f32_e32 v59, 0x3b5b0037, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v76, 0x3b820821, v16
	v_fmac_f32_e32 v35, 0x3ccccccd, v71
	v_fmac_f32_e32 v59, 0x3b820821, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v76, 0x3ccccccd, v49
	v_fmac_f32_e32 v35, 0x3e000000, v67
	v_add_f32_e32 v49, v28, v19
	v_dual_fmamk_f32 v25, v50, 0xbdcccccd, v21 :: v_dual_fmac_f32 v26, 0xbdcccccd, v54
	v_fmac_f32_e32 v59, 0x3ccccccd, v48
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v35, 0xbce38e39, v20
	v_fmac_f32_e32 v30, 0x3b5b0037, v37
	v_fmamk_f32 v37, v71, 0xbccccccd, v36
	v_fmac_f32_e32 v76, 0x3c638e39, v20
	v_fmac_f32_e32 v59, 0x3c638e39, v20
	v_dual_add_f32 v35, v58, v35 :: v_dual_fmac_f32 v30, 0x3b820821, v16
	v_fmac_f32_e32 v21, 0xbdcccccd, v55
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v76, 0x3d2aaaab, v72
	v_fmac_f32_e32 v59, 0x3d2aaaab, v72
	v_fmac_f32_e32 v25, 0x3d638e39, v17
	v_fmamk_f32 v54, v68, 0x3ccccccd, v30
	v_fmamk_f32 v77, v70, 0xbccccccd, v30
	v_fmac_f32_e32 v30, 0x3ccccccd, v70
	v_fmac_f32_e32 v21, 0xbce38e39, v17
	v_fmac_f32_e32 v59, 0x3e000000, v52
	v_fmac_f32_e32 v54, 0x3c638e39, v20
	v_fmac_f32_e32 v77, 0x3c638e39, v20
	v_fmac_f32_e32 v30, 0x3c638e39, v20
	v_fmac_f32_e32 v76, 0x3e000000, v61
	v_fmac_f32_e32 v21, 0xbdaaaaab, v22
	v_fmac_f32_e32 v54, 0xbd2aaaab, v72
	v_fmac_f32_e32 v77, 0xbd2aaaab, v72
	v_fmac_f32_e32 v30, 0xbd2aaaab, v72
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v54, 0x3e000000, v62 :: v_dual_fmac_f32 v77, 0x3e000000, v64
	v_fmac_f32_e32 v30, 0x3e000000, v66
	v_fmac_f32_e32 v18, 0xbc820821, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v29, v77
	v_add_f32_e32 v19, v29, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmamk_f32 v27, v50, 0x3dcccccd, v18
	v_fmamk_f32 v50, v48, 0xbccccccd, v36
	v_fmac_f32_e32 v36, 0xbccccccd, v69
	v_fmac_f32_e32 v18, 0x3dcccccd, v55
	v_dual_add_f32 v48, v74, v59 :: v_dual_fmac_f32 v27, 0x3d638e39, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v50, 0x3c638e39, v20
	v_fmac_f32_e32 v36, 0x3e000000, v53
	v_fmac_f32_e32 v47, 0xbce38e39, v17
	v_fmac_f32_e32 v18, 0xbce38e39, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v50, 0x3d2aaaab, v72
	v_fmac_f32_e32 v36, 0xbce38e39, v20
	v_fmac_f32_e32 v37, 0x3e000000, v65
	v_fmac_f32_e32 v47, 0x3daaaaab, v22
	v_fmac_f32_e32 v18, 0xbdaaaaab, v22
	v_fmac_f32_e32 v50, 0x3e000000, v60
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v26, 0xbce38e39, v17 :: v_dual_fmac_f32 v37, 0xbce38e39, v20
	v_add_f32_e32 v20, v28, v76
	v_add_f32_e32 v50, v74, v50
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmac_f32 v26, 0x3daaaaab, v22 :: v_dual_add_f32 v17, v58, v37
	v_dual_add_f32 v37, v73, v36 :: v_dual_add_f32 v36, v56, v75
	v_dual_add_f32 v23, v73, v23 :: v_dual_add_f32 v22, v56, v54
	s_clause 0x4
	scratch_store_b128 off, v[24:27], off offset:16
	scratch_store_b128 off, v[47:50], off offset:32
	scratch_store_b128 off, v[20:23], off offset:48
	scratch_store_b128 off, v[16:19], off offset:64
	scratch_store_b96 off, v[35:37], off offset:80
	v_cmpx_lt_i32_e32 25, v31
	s_xor_b32 s11, exec_lo, s11
; %bb.18:                               ; %LeafBlock598
	v_cmp_eq_u32_e32 vcc_lo, 26, v31
	s_mov_b32 s10, exec_lo
	s_and_b32 s21, vcc_lo, exec_lo
; %bb.19:                               ; %Flow629
	s_and_not1_saveexec_b32 s11, s11
; %bb.20:                               ; %LeafBlock596
	v_cmp_eq_u32_e32 vcc_lo, 25, v31
	s_or_b32 s10, s10, exec_lo
	s_and_b32 s3, vcc_lo, exec_lo
; %bb.21:                               ; %Flow630
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s10, exec_lo
	s_and_b32 s10, s3, exec_lo
	s_and_b32 s3, s21, exec_lo
                                        ; implicit-def: $vgpr20
.LBB2_22:                               ; %Flow628
	s_and_not1_saveexec_b32 s17, s17
	s_cbranch_execz .LBB2_28
; %bb.23:                               ; %LeafBlock588
	s_mov_b32 s21, -1
	s_mov_b32 s22, s11
	s_mov_b32 s15, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	v_cmpx_eq_u32_e32 0x64, v31
	s_cbranch_execz .LBB2_27
; %bb.24:                               ; %.preheader.preheader
	v_mad_u64_u32 v[16:17], null, v20, s12, v[38:39]
	s_lshl_b32 s21, s12, 6
	s_mov_b32 s22, 0
.LBB2_25:                               ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_max_i32_e32 v17, 0, v16
	v_add_nc_u32_e32 v16, s21, v16
	s_add_i32 s23, s22, 16
	s_add_i32 s22, s22, 4
	s_cmpk_eq_i32 s22, 0x4c
	v_cmp_gt_i32_e32 vcc_lo, s20, v17
	v_cndmask_b32_e32 v17, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, s6, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
	global_load_b32 v17, v[17:18], off
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v17, s23
	s_cbranch_scc0 .LBB2_25
; %bb.26:
	s_clause 0x4
	scratch_load_b128 v[47:50], off, off offset:16
	scratch_load_b128 v[26:29], off, off offset:32
	scratch_load_b128 v[17:20], off, off offset:48
	scratch_load_b128 v[22:25], off, off offset:64
	scratch_load_b96 v[35:37], off, off offset:80
	s_mov_b32 s7, 0x3dcccccd
	s_mov_b32 s21, 0xbdcccccd
	s_mov_b32 s6, 0xbc4d5033
	s_or_b32 s22, s11, exec_lo
	s_waitcnt vmcnt(4)
	v_dual_sub_f32 v21, v48, v50 :: v_dual_mul_f32 v16, 0xc1f00000, v47
	s_waitcnt vmcnt(1)
	v_dual_sub_f32 v30, v49, v26 :: v_dual_sub_f32 v59, v20, v23
	v_dual_add_f32 v51, v19, v18 :: v_dual_mul_f32 v52, -4.0, v48
	v_dual_mul_f32 v53, 4.0, v26 :: v_dual_sub_f32 v58, v27, v28
	v_fma_f32 v54, -4.0, v18, v19
	v_fma_f32 v55, v48, 2.0, -v49
	v_dual_add_f32 v56, v26, v26 :: v_dual_add_f32 v21, v21, v27
	v_dual_add_f32 v57, v49, v26 :: v_dual_sub_f32 v62, v19, v20
	v_dual_sub_f32 v60, v19, v22 :: v_dual_add_f32 v51, v20, v51
	v_sub_f32_e64 v61, -v28, v27
	v_dual_add_f32 v30, v27, v30 :: v_dual_fmac_f32 v53, -4.0, v49
	v_dual_fmac_f32 v16, 0xc1300000, v48 :: v_dual_fmac_f32 v55, 2.0, v50
	v_dual_fmamk_f32 v48, v47, 0x41400000, v52 :: v_dual_add_f32 v63, v58, v29
	v_fma_f32 v47, 4.0, v50, v52
	v_dual_add_f32 v54, v20, v54 :: v_dual_add_f32 v57, v27, v57
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v52, 2.0, v49 :: v_dual_sub_f32 v59, v59, v35
	v_fma_f32 v56, v49, -2.0, -v56
	v_dual_sub_f32 v60, v60, v25 :: v_dual_sub_f32 v21, v21, v28
	v_sub_f32_e32 v58, v58, v29
	v_dual_add_f32 v61, v61, v29 :: v_dual_add_f32 v62, v22, v62
	v_dual_add_f32 v64, v28, v30 :: v_dual_add_f32 v51, v22, v51
	v_dual_fmac_f32 v16, 0xc1300000, v49 :: v_dual_sub_f32 v55, v55, v26
	v_dual_fmac_f32 v48, -4.0, v49 :: v_dual_add_f32 v49, v27, v47
	v_add_f32_e32 v47, v60, v36
	v_dual_add_f32 v53, v27, v53 :: v_dual_add_f32 v54, v22, v54
	v_dual_fmac_f32 v52, -4.0, v50 :: v_dual_add_f32 v57, v28, v57
	v_add_f32_e32 v56, v27, v56
	v_dual_add_f32 v59, v59, v37 :: v_dual_fmac_f32 v16, 0xc1300000, v50
	v_dual_add_f32 v58, v58, v17 :: v_dual_add_f32 v51, v23, v51
	v_dual_add_f32 v60, v61, v17 :: v_dual_sub_f32 v61, v62, v23
	v_dual_sub_f32 v30, v63, v17 :: v_dual_sub_f32 v49, v49, v28
	v_dual_sub_f32 v21, v21, v29 :: v_dual_fmac_f32 v48, -4.0, v50
	v_sub_f32_e32 v62, v64, v29
	v_dual_add_f32 v50, v28, v53 :: v_dual_mul_f32 v59, 0x3e800000, v59
	v_add_f32_e32 v53, v23, v54
	v_dual_add_f32 v54, v27, v55 :: v_dual_add_f32 v55, v29, v57
	v_dual_fmac_f32 v52, 2.0, v26 :: v_dual_add_f32 v21, v21, v17
	v_dual_sub_f32 v57, v58, v19 :: v_dual_add_f32 v56, v28, v56
	v_add_f32_e32 v58, v60, v20
	v_dual_sub_f32 v60, v61, v25 :: v_dual_sub_f32 v51, v51, v24
	v_dual_sub_f32 v61, v62, v17 :: v_dual_fmac_f32 v16, 0xc1300000, v26
	v_dual_fmac_f32 v53, 4.0, v24 :: v_dual_fmac_f32 v48, -4.0, v26
	v_sub_f32_e32 v26, v49, v29
	v_dual_sub_f32 v49, v50, v29 :: v_dual_add_f32 v50, v28, v54
	v_dual_add_f32 v21, v21, v19 :: v_dual_add_f32 v52, v27, v52
	v_dual_add_f32 v54, v17, v55 :: v_dual_sub_f32 v51, v51, v25
	v_add_f32_e32 v55, v29, v56
	v_dual_add_f32 v56, v57, v22 :: v_dual_sub_f32 v57, v58, v23
	v_add_f32_e32 v58, v35, v60
	v_dual_fmac_f32 v16, 0x41000000, v27 :: v_dual_add_f32 v27, v27, v48
	v_dual_add_f32 v26, v17, v26 :: v_dual_sub_f32 v51, v51, v35
	v_sub_f32_e32 v48, v49, v17
	v_sub_f32_e32 v49, v53, v25
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v27, v28, v27
	v_dual_add_f32 v52, v28, v52 :: v_dual_sub_f32 v21, v21, v22
	v_dual_sub_f32 v53, v54, v18 :: v_dual_add_f32 v60, v20, v61
	v_dual_add_f32 v54, v17, v55 :: v_dual_sub_f32 v55, v56, v25
	v_add_f32_e32 v50, v29, v50
	v_dual_add_f32 v56, v57, v35 :: v_dual_sub_f32 v57, v58, v36
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v58, v60, v23
	v_dual_fmac_f32 v16, 0x41000000, v28 :: v_dual_add_f32 v21, v21, v25
	v_add_f32_e32 v28, v20, v48
	v_dual_sub_f32 v48, v49, v35 :: v_dual_sub_f32 v51, v51, v36
	v_add_f32_e32 v49, v17, v50
	v_add_f32_e32 v50, v29, v52
	v_sub_f32_e32 v52, v53, v19
	v_dual_add_f32 v26, v19, v26 :: v_dual_add_f32 v27, v29, v27
	v_add_f32_e32 v53, v55, v36
	v_dual_sub_f32 v55, v56, v37 :: v_dual_fmac_f32 v54, 2.0, v18
	v_dual_fmac_f32 v16, 0x41000000, v29 :: v_dual_sub_f32 v29, v48, v36
	v_dual_sub_f32 v48, v49, v18 :: v_dual_sub_f32 v51, v51, v37
	v_dual_add_f32 v49, v17, v50 :: v_dual_sub_f32 v28, v28, v23
	v_dual_add_f32 v56, v37, v57 :: v_dual_add_f32 v57, v35, v58
	v_dual_sub_f32 v50, v52, v22 :: v_dual_sub_f32 v21, v21, v36
	v_sub_f32_e64 v58, -v53, v55
	v_dual_sub_f32 v60, v55, v53 :: v_dual_add_f32 v61, v53, v55
	v_sub_f32_e32 v52, v54, v19
	v_dual_sub_f32 v54, v53, v55 :: v_dual_fmac_f32 v49, 2.0, v18
	v_dual_fmac_f32 v16, 0x41000000, v17 :: v_dual_add_f32 v17, v17, v27
	v_dual_add_f32 v27, v35, v28 :: v_dual_sub_f32 v26, v26, v22
	v_dual_add_f32 v67, v55, v56 :: v_dual_sub_f32 v62, v56, v53
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v17, -4.0, v18
	v_sub_f32_e32 v63, v55, v56
	v_add_f32_e32 v64, v53, v56
	v_sub_f32_e64 v65, -v55, v56
	v_sub_f32_e64 v66, -v53, v56
	v_sub_f32_e32 v53, v53, v56
	v_dual_sub_f32 v55, v56, v55 :: v_dual_sub_f32 v28, v29, v37
	v_dual_add_f32 v29, v19, v48 :: v_dual_sub_f32 v56, v57, v37
	v_dual_sub_f32 v48, v50, v24 :: v_dual_sub_f32 v57, v27, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v70, s21, v21, 0x3d579436 :: v_dual_fmac_f32 v29, -2.0, v20
	v_dual_fmaak_f32 v69, s7, v56, 0x3d579436 :: v_dual_fmaak_f32 v68, s7, v21, 0x3d579436
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f32_e32 v77, v57, v28
	v_dual_fmaak_f32 v21, s7, v51, 0x3d579436 :: v_dual_add_f32 v26, v25, v26
	v_sub_f32_e32 v27, v48, v25
	v_dual_sub_f32 v50, v52, v22 :: v_dual_fmaak_f32 v71, s21, v56, 0x3d579436
	v_dual_add_f32 v17, v19, v17 :: v_dual_sub_f32 v52, v26, v36
	v_dual_fmamk_f32 v73, v56, 0xbdcccccd, v70 :: v_dual_add_f32 v26, v19, v49
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v27, v27, v36 :: v_dual_fmac_f32 v16, 0xc1300000, v18
	v_fmac_f32_e32 v50, 2.0, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v75, v52, v28
	v_dual_fmac_f32 v26, -2.0, v20 :: v_dual_add_f32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v16, 0x41000000, v19 :: v_dual_add_f32 v49, v52, v57
	v_dual_add_f32 v19, v22, v29 :: v_dual_fmamk_f32 v48, v56, 0x3dcccccd, v68
	v_dual_add_f32 v17, v22, v17 :: v_dual_fmaak_f32 v18, s21, v51, 0x3d579436
	v_sub_f32_e32 v29, v50, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v19, -2.0, v23 :: v_dual_fmamk_f32 v50, v56, 0x3dcccccd, v70
	v_dual_fmamk_f32 v56, v56, 0xbdcccccd, v68 :: v_dual_add_f32 v17, v23, v17
	v_fmamk_f32 v78, v51, 0x3dcccccd, v70
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v19, v19, v24 :: v_dual_sub_f32 v72, v52, v57
	v_sub_f32_e32 v29, v29, v36
	v_fmac_f32_e32 v17, -4.0, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmamk_f32 v76, v51, 0x3dcccccd, v69 :: v_dual_add_f32 v19, v25, v19
	v_fmac_f32_e32 v16, 0x41000000, v20
	v_dual_add_f32 v20, v22, v26 :: v_dual_add_f32 v17, v25, v17
	v_dual_fmamk_f32 v74, v51, 0x3dcccccd, v68 :: v_dual_sub_f32 v79, v52, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v19, -2.0, v35 :: v_dual_fmac_f32 v16, 0x41000000, v22
	v_dual_fmac_f32 v20, -2.0, v23 :: v_dual_add_f32 v17, v35, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmamk_f32 v22, v51, 0x3dcccccd, v71 :: v_dual_add_f32 v19, v36, v19
	v_fmac_f32_e32 v16, 0x41000000, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v20, 2.0, v24 :: v_dual_add_f32 v17, v36, v17
	v_sub_f32_e32 v23, v57, v28
	v_dual_fmac_f32 v19, -2.0, v37 :: v_dual_fmac_f32 v16, 0xc1300000, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v20, v25, v20
	v_add_f32_e32 v17, v37, v17
	s_xor_b32 s21, exec_lo, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmamk_f32 v81, v19, 0xbd638e39, v59
	v_fma_f32 v59, 0xbd638e39, v19, -v59
	v_fmac_f32_e32 v20, -2.0, v35
	v_add_f32_e32 v20, v36, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, -2.0, v37
	v_fmac_f32_e32 v16, 0x41000000, v25
	v_dual_fmac_f32 v16, 0x41000000, v35 :: v_dual_sub_f32 v35, v27, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0x41000000, v36
	v_fmac_f32_e32 v16, 0x41000000, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmamk_f32 v26, v16, 0xbb969026, v69
	v_fmac_f32_e32 v76, 0x3b5b0037, v16
	v_fmac_f32_e32 v22, 0x3b5b0037, v16
	v_fmac_f32_e32 v18, 0xbb969026, v16
	v_fmac_f32_e32 v26, 0xbc820821, v17
	v_fmac_f32_e32 v69, 0xbdcccccd, v51
	v_fmac_f32_e32 v76, 0x3b820821, v17
	v_fmac_f32_e32 v22, 0x3b820821, v17
	v_fmac_f32_e32 v18, 0xbc820821, v17
	v_fmac_f32_e32 v26, 0xbdcccccd, v57
	v_fmac_f32_e32 v69, 0x3b5b0037, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v22, 0xbccccccd, v23
	v_fmac_f32_e32 v18, 0x3dcccccd, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v69, 0x3b820821, v17
	v_dual_fmac_f32 v76, 0x3ccccccd, v77 :: v_dual_fmac_f32 v69, 0x3ccccccd, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v76, 0x3e000000, v63
	v_dual_fmac_f32 v22, 0x3e000000, v65 :: v_dual_fmac_f32 v69, 0x3e000000, v67
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v76, 0xbce38e39, v20
	v_dual_mul_f32 v24, 0x3daaaaab, v27 :: v_dual_add_f32 v23, v81, v76
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v36, v19, 0x3ce38e39, v24
	v_fma_f32 v80, 0x3ce38e39, v19, -v24
	v_fmamk_f32 v37, v30, 0x3e800000, v36
	v_fmamk_f32 v25, v16, 0xbb969026, v68
	v_fmac_f32_e32 v36, 0xbe800000, v30
	s_delay_alu instid0(VALU_DEP_4)
	v_fmamk_f32 v30, v47, 0x3e800000, v80
	v_fmac_f32_e32 v80, 0xbe800000, v47
	v_fmamk_f32 v27, v16, 0xbb969026, v70
	v_fmac_f32_e32 v25, 0xbc820821, v17
	v_fmac_f32_e32 v68, 0xbdcccccd, v51
	v_fmamk_f32 v47, v16, 0xbb969026, v71
	v_fmac_f32_e32 v21, 0xbb969026, v16
	v_fmac_f32_e32 v27, 0xbc820821, v17
	v_fmac_f32_e32 v25, 0xbdcccccd, v52
	v_fmac_f32_e32 v68, 0x3b5b0037, v16
	v_fmac_f32_e32 v47, 0xbc820821, v17
	v_fmac_f32_e32 v21, 0xbc820821, v17
	v_dual_sub_f32 v19, v19, v20 :: v_dual_fmac_f32 v70, 0xbdcccccd, v51
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v68, 0x3b820821, v17
	v_fmac_f32_e32 v27, 0x3dcccccd, v52
	v_fmac_f32_e32 v21, 0xbdcccccd, v28
	v_fmac_f32_e32 v47, 0x3dcccccd, v57
	v_fmac_f32_e32 v25, 0x3d638e39, v19
	v_fmac_f32_e32 v68, 0x3ccccccd, v79
	v_dual_fmac_f32 v26, 0xbce38e39, v19 :: v_dual_fmac_f32 v69, 0xbce38e39, v20
	v_fmac_f32_e32 v27, 0x3d638e39, v19
	v_dual_fmac_f32 v47, 0xbce38e39, v19 :: v_dual_fmac_f32 v22, 0xbce38e39, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v68, 0x3c638e39, v20
	v_fmac_f32_e32 v21, 0xbce38e39, v19
	v_fmac_f32_e32 v18, 0xbce38e39, v19
	v_fmac_f32_e32 v26, 0x3daaaaab, v35
	v_fmac_f32_e32 v47, 0x3daaaaab, v35
	v_fmac_f32_e32 v68, 0xbd2aaaab, v29
	v_fmac_f32_e32 v21, 0xbdaaaaab, v35
	v_dual_fmac_f32 v18, 0xbdaaaaab, v35 :: v_dual_add_f32 v35, v59, v69
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v68, 0x3e000000, v66
	v_add_f32_e32 v19, v80, v68
	v_fmac_f32_e32 v56, 0x3b5b0037, v16
	v_fmac_f32_e32 v74, 0x3b5b0037, v16
	v_fmac_f32_e32 v48, 0x3b5b0037, v16
	v_fmac_f32_e32 v50, 0x3b5b0037, v16
	v_fmac_f32_e32 v78, 0x3b5b0037, v16
	v_fmac_f32_e32 v56, 0x3b820821, v17
	v_fmac_f32_e32 v74, 0x3b820821, v17
	v_fmac_f32_e32 v70, 0x3b5b0037, v16
	v_fmac_f32_e32 v48, 0x3b820821, v17
	v_fmac_f32_e32 v50, 0x3b820821, v17
	v_fmac_f32_e32 v56, 0x3ccccccd, v72
	v_fmac_f32_e32 v74, 0x3ccccccd, v75
	v_fmac_f32_e32 v78, 0x3b820821, v17
	v_fmac_f32_e32 v70, 0x3b820821, v17
	v_fmac_f32_e32 v48, 0x3ccccccd, v49
	v_fmac_f32_e32 v56, 0x3c638e39, v20
	v_fmac_f32_e32 v74, 0x3c638e39, v20
	v_fmaak_f32 v24, s6, v16, 0x3d579436
	v_fmac_f32_e32 v70, 0xbccccccd, v75
	v_fmac_f32_e32 v48, 0x3c638e39, v20
	v_fmac_f32_e32 v56, 0x3d2aaaab, v29
	v_fmac_f32_e32 v74, 0xbd2aaaab, v29
	v_fmamk_f32 v24, v17, 0x3d430c31, v24
	v_fmac_f32_e32 v70, 0x3c638e39, v20
	v_fmac_f32_e32 v48, 0x3d2aaaab, v29
	v_fmac_f32_e32 v56, 0x3e000000, v61
	v_fmac_f32_e32 v71, 0xbdcccccd, v51
	v_fmac_f32_e32 v74, 0x3e000000, v62
	v_fmac_f32_e32 v73, 0x3b5b0037, v16
	v_fmac_f32_e32 v70, 0xbd2aaaab, v29
	v_fmac_f32_e32 v48, 0x3e000000, v54
	v_fmac_f32_e32 v71, 0x3b5b0037, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, 0x3b820821, v17
	v_fmac_f32_e32 v50, 0xbccccccd, v72
	v_fmac_f32_e32 v70, 0x3e000000, v53
	v_fmac_f32_e32 v71, 0x3b820821, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v78, 0xbccccccd, v79 :: v_dual_fmac_f32 v73, 0xbccccccd, v49
	v_dual_fmac_f32 v50, 0x3c638e39, v20 :: v_dual_add_f32 v17, v59, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v71, 0xbccccccd, v77
	v_fmac_f32_e32 v78, 0x3c638e39, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, 0x3c638e39, v20
	v_fmac_f32_e32 v50, 0x3d2aaaab, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v48, v37, v48 :: v_dual_fmac_f32 v71, 0x3e000000, v55
	v_fmac_f32_e32 v78, 0xbd2aaaab, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, 0x3d2aaaab, v29
	v_fmac_f32_e32 v50, 0x3e000000, v58
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v22, v30, v74 :: v_dual_fmac_f32 v71, 0xbce38e39, v20
	v_fmac_f32_e32 v78, 0x3e000000, v64
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v73, 0x3e000000, v60
	v_add_f32_e32 v49, v36, v50
	v_add_f32_e32 v20, v36, v56
	v_add_f32_e32 v36, v30, v70
	v_add_f32_e32 v16, v80, v78
	v_add_f32_e32 v50, v37, v73
	v_add_f32_e32 v37, v81, v71
	s_clause 0x4
	scratch_store_b128 off, v[24:27], off offset:16
	scratch_store_b128 off, v[47:50], off offset:32
	scratch_store_b128 off, v[20:23], off offset:48
	scratch_store_b96 off, v[16:18], off offset:64
	scratch_store_b32 off, v35, off offset:80
.LBB2_27:                               ; %Flow632
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s6, s11, exec_lo
	s_and_b32 s7, s22, exec_lo
	s_and_b32 s15, s21, exec_lo
	s_or_b32 s11, s6, s7
.LBB2_28:                               ; %Flow631
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s17, s11, exec_lo
	s_and_b32 s11, s15, exec_lo
	s_and_b32 s10, s10, exec_lo
	s_and_b32 s3, s3, exec_lo
.LBB2_29:                               ; %Flow627
	s_and_not1_saveexec_b32 s2, s2
; %bb.30:                               ; %LeafBlock586
	v_cmp_eq_u32_e32 vcc_lo, 26, v31
	v_dual_mov_b32 v23, v3 :: v_dual_mov_b32 v16, v8
	v_dual_mov_b32 v35, v32 :: v_dual_mov_b32 v36, v33
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v18, v10
	v_mov_b32_e32 v37, v34
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s6, vcc_lo, exec_lo
	s_or_b32 s11, s11, exec_lo
	s_or_b32 s3, s3, s6
; %bb.31:                               ; %Flow633
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s6, s3
	s_cbranch_execz .LBB2_57
; %bb.32:
	s_mul_i32 s21, s8, s14
	s_mov_b32 s2, 0
	v_or_b32_e32 v19, s21, v39
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v19
                                        ; implicit-def: $vgpr19
	s_and_saveexec_b32 s3, vcc_lo
	s_xor_b32 s7, exec_lo, s3
	s_cbranch_execz .LBB2_52
; %bb.33:
	s_cmp_eq_u32 s21, 7
	v_cmp_ne_u32_e32 vcc_lo, 0, v39
	s_cselect_b32 s22, -1, 0
	s_cmp_lg_u32 s21, 7
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s3, vcc_lo
	s_and_saveexec_b32 s15, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s15, exec_lo, s15
	s_cbranch_execz .LBB2_49
; %bb.34:
	v_cmp_ne_u32_e64 s3, 63, v39
	s_cmp_lg_u32 s21, 0
	v_cmp_eq_u32_e64 s2, 63, v39
	s_cselect_b32 s23, -1, 0
	s_mov_b32 s21, 0
	s_or_b32 s3, s23, s3
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s23, s3
	s_xor_b32 s3, exec_lo, s23
	s_cbranch_execz .LBB2_46
; %bb.35:
	s_and_b32 s21, s22, s2
	s_mov_b32 s22, 0
	s_xor_b32 s21, s21, -1
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s23, s21
	s_xor_b32 s21, exec_lo, s23
	s_cbranch_execz .LBB2_43
; %bb.36:
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr24
                                        ; implicit-def: $sgpr25
                                        ; implicit-def: $sgpr26
                                        ; implicit-def: $sgpr27
                                        ; implicit-def: $sgpr28
                                        ; implicit-def: $sgpr29
	s_and_saveexec_b32 s30, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s30, exec_lo, s30
	s_cbranch_execz .LBB2_40
; %bb.37:
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr24
                                        ; implicit-def: $sgpr25
                                        ; implicit-def: $sgpr26
                                        ; implicit-def: $sgpr27
                                        ; implicit-def: $sgpr28
                                        ; implicit-def: $sgpr29
	s_and_saveexec_b32 s31, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s31
	s_cbranch_execz .LBB2_39
; %bb.38:
	scratch_load_b32 v37, off, off offset:24
	s_mov_b32 s22, exec_lo
	s_mov_b32 s29, 4
	s_mov_b32 s28, 11
	s_mov_b32 s27, 13
	s_mov_b32 s26, 16
	s_mov_b32 s25, 18
	s_mov_b32 s24, 8
	s_mov_b32 s23, 5
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
.LBB2_39:                               ; %Flow606
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s22, s22, exec_lo
.LBB2_40:                               ; %Flow605
	s_or_saveexec_b32 s2, s30
	v_dual_mov_b32 v19, s23 :: v_dual_mov_b32 v20, s24
	v_dual_mov_b32 v21, s25 :: v_dual_mov_b32 v22, s26
	v_dual_mov_b32 v24, s27 :: v_dual_mov_b32 v25, s28
	v_mov_b32_e32 v26, s29
	s_xor_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_42
; %bb.41:
	scratch_load_b32 v37, off, off offset:32
	v_dual_mov_b32 v19, 8 :: v_dual_mov_b32 v20, 5
	v_dual_mov_b32 v21, 16 :: v_dual_mov_b32 v22, 18
	v_dual_mov_b32 v24, 11 :: v_dual_mov_b32 v25, 13
	v_mov_b32_e32 v26, 2
	s_or_b32 s22, s22, exec_lo
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
.LBB2_42:                               ; %Flow607
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s22, s22, exec_lo
.LBB2_43:                               ; %Flow604
	s_and_not1_saveexec_b32 s2, s21
	s_cbranch_execz .LBB2_45
; %bb.44:
	scratch_load_b32 v16, off, off offset:24
	v_dual_mov_b32 v19, 17 :: v_dual_mov_b32 v20, 12
	v_dual_mov_b32 v21, 14 :: v_dual_mov_b32 v22, 9
	v_dual_mov_b32 v24, 7 :: v_dual_mov_b32 v25, 6
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v26, 13 :: v_dual_mov_b32 v37, v23
	s_or_b32 s22, s22, exec_lo
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v23, off offset:80
	scratch_store_b32 off, v23, off offset:88
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
.LBB2_45:                               ; %Flow608
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s21, s22, exec_lo
.LBB2_46:                               ; %Flow603
	s_and_not1_saveexec_b32 s2, s3
	s_cbranch_execz .LBB2_48
; %bb.47:
	scratch_load_b32 v16, off, off offset:24
	v_dual_mov_b32 v19, 12 :: v_dual_mov_b32 v20, 17
	v_dual_mov_b32 v21, 9 :: v_dual_mov_b32 v22, 14
	v_dual_mov_b32 v24, 7 :: v_dual_mov_b32 v25, 6
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v26, 13 :: v_dual_mov_b32 v37, v35
	s_or_b32 s21, s21, exec_lo
                                        ; implicit-def: $vgpr23
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v35, off offset:60
	scratch_store_b32 off, v35, off offset:88
                                        ; implicit-def: $vgpr16
.LBB2_48:                               ; %Flow609
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s21, exec_lo
.LBB2_49:                               ; %Flow602
	s_and_not1_saveexec_b32 s3, s15
	s_cbranch_execz .LBB2_51
; %bb.50:
	scratch_load_b32 v16, off, off offset:24
	v_dual_mov_b32 v19, 17 :: v_dual_mov_b32 v20, 12
	v_dual_mov_b32 v21, 14 :: v_dual_mov_b32 v22, 9
	v_dual_mov_b32 v24, 6 :: v_dual_mov_b32 v25, 7
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v26, 16 :: v_dual_mov_b32 v37, v17
	s_or_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr23
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v17, off offset:60
	scratch_store_b32 off, v17, off offset:88
                                        ; implicit-def: $vgpr16
.LBB2_51:                               ; %Flow610
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
.LBB2_52:                               ; %Flow
	s_and_not1_saveexec_b32 s3, s7
	s_cbranch_execz .LBB2_54
; %bb.53:
	scratch_load_b32 v16, off, off offset:32
	v_dual_mov_b32 v19, 12 :: v_dual_mov_b32 v20, 17
	v_dual_mov_b32 v21, 9 :: v_dual_mov_b32 v22, 14
	v_dual_mov_b32 v24, 6 :: v_dual_mov_b32 v25, 7
	v_mov_b32_e32 v26, 16
	s_or_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr23
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:24
	scratch_store_b32 off, v37, off offset:68
	scratch_store_b32 off, v37, off offset:60
                                        ; implicit-def: $vgpr16
.LBB2_54:                               ; %Flow611
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_56
; %bb.55:                               ; %.sink.split.i
	v_lshl_add_u32 v16, v26, 2, 16
	v_lshl_add_u32 v17, v25, 2, 16
	v_lshl_add_u32 v18, v22, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v16, v37, off
	scratch_load_b32 v16, v17, off
	v_lshl_add_u32 v17, v24, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v17, v16, off
	scratch_load_b32 v16, v18, off
	v_lshl_add_u32 v17, v21, 2, 16
	v_lshl_add_u32 v18, v20, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v17, v16, off
	scratch_load_b32 v16, v18, off
	v_lshl_add_u32 v17, v19, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v17, v16, off
	s_clause 0x1
	scratch_load_b128 v[19:22], off, off offset:60
	scratch_load_b96 v[35:37], off, off offset:80
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v18, v22 :: v_dual_mov_b32 v17, v21
	v_dual_mov_b32 v23, v19 :: v_dual_mov_b32 v16, v20
.LBB2_56:                               ; %_Z13xsymmetry_botPfii.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:28
	scratch_load_b64 v[20:21], off, off offset:40
	v_mov_b32_e32 v22, v16
	s_waitcnt vmcnt(2)
	v_mov_b32_e32 v19, v36
	s_or_b32 s17, s17, exec_lo
	s_and_not1_b32 s11, s11, exec_lo
	s_waitcnt vmcnt(1)
	scratch_store_b32 off, v24, off offset:20
	s_waitcnt vmcnt(0)
	s_clause 0x1
	scratch_store_b32 off, v20, off offset:36
	scratch_store_b32 off, v21, off offset:48
.LBB2_57:                               ; %Flow634
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s15, s17, exec_lo
	s_and_b32 s11, s11, exec_lo
	s_and_b32 s2, s10, exec_lo
.LBB2_58:                               ; %Flow626
	s_or_saveexec_b32 s3, s9
	s_mov_b32 s7, 0
	s_mov_b32 s6, 0
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB2_62
; %bb.59:                               ; %NodeBlock584
	s_mov_b32 s6, -1
	s_mov_b32 s9, s2
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i32_e32 9, v31
; %bb.60:                               ; %NodeBlock582
	v_cmp_lt_i32_e32 vcc_lo, 24, v31
	s_and_not1_b32 s9, s2, exec_lo
	s_mov_b32 s7, exec_lo
	s_xor_b32 s6, exec_lo, -1
	s_and_b32 s17, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s9, s9, s17
; %bb.61:                               ; %Flow636
	s_or_b32 exec_lo, exec_lo, s10
	v_dual_mov_b32 v23, v3 :: v_dual_mov_b32 v18, v10
	v_mov_b32_e32 v35, v32
	v_mov_b32_e32 v17, v9
	v_mov_b32_e32 v37, v34
	v_mov_b32_e32 v19, v11
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s9, s9, exec_lo
	s_and_b32 s6, s6, exec_lo
	s_and_b32 s7, s7, exec_lo
	s_or_b32 s2, s2, s9
.LBB2_62:                               ; %Flow635
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s9, s2
	s_cbranch_execz .LBB2_88
; %bb.63:
	s_mul_i32 s3, s8, s14
                                        ; implicit-def: $vgpr24
	s_mov_b32 s2, exec_lo
	v_or_b32_e32 v16, s3, v39
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v16
	s_xor_b32 s8, exec_lo, s2
	s_cbranch_execz .LBB2_85
; %bb.64:
	s_cmp_eq_u32 s3, 7
	v_cmp_ne_u32_e32 vcc_lo, 0, v39
	s_cselect_b32 s17, -1, 0
	s_cmp_lg_u32 s3, 7
                                        ; implicit-def: $vgpr24
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s10, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB2_82
; %bb.65:
	v_cmp_ne_u32_e64 s2, 63, v39
	s_cmp_lg_u32 s3, 0
	v_cmp_eq_u32_e64 s3, 63, v39
	s_cselect_b32 s14, -1, 0
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s14, s14, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s21, s14
	s_xor_b32 s14, exec_lo, s21
	s_cbranch_execz .LBB2_79
; %bb.66:
	s_and_b32 s3, s17, s3
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, -1
	s_and_saveexec_b32 s17, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s17
	s_cbranch_execz .LBB2_76
; %bb.67:
                                        ; implicit-def: $vgpr24
	s_and_saveexec_b32 s17, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s17, exec_lo, s17
	s_cbranch_execz .LBB2_73
; %bb.68:
                                        ; implicit-def: $vgpr24
	s_and_saveexec_b32 s21, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s21
; %bb.69:                               ; %._crit_edge.i
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b32 v25, off, off offset:48
; %bb.70:                               ; %Flow613
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB2_72
; %bb.71:
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b32 v16, off, off offset:24
	v_mov_b32_e32 v17, v23
	v_mov_b32_e32 v37, v35
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v35, off offset:88
	scratch_store_b32 off, v23, off offset:68
	scratch_store_b32 off, v24, off offset:48
	v_mov_b32_e32 v25, v24
.LBB2_72:                               ; %Flow614
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_73:                               ; %Flow616
	s_and_not1_saveexec_b32 s2, s17
	s_cbranch_execz .LBB2_75
; %bb.74:
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:48
	scratch_load_b32 v16, off, off offset:32
	v_mov_b32_e32 v23, v17
	v_mov_b32_e32 v35, v37
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v16, off offset:24
	scratch_store_b32 off, v37, off offset:80
	scratch_store_b32 off, v17, off offset:60
	scratch_store_b32 off, v24, off offset:36
	v_mov_b32_e32 v25, v24
.LBB2_75:                               ; %Flow617
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_76:                               ; %Flow618
	s_and_not1_saveexec_b32 s2, s3
	s_cbranch_execz .LBB2_78
; %bb.77:
	s_clause 0x2
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b64 v[21:22], off, off offset:52
	scratch_load_b32 v16, off, off offset:24
	v_mov_b32_e32 v20, v23
	v_mov_b32_e32 v17, v23
	v_mov_b32_e32 v35, v23
	v_mov_b32_e32 v37, v23
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v25, v24 :: v_dual_mov_b32 v18, v21
	v_mov_b32_e32 v19, v22
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v24, off offset:48
	scratch_store_b32 off, v23, off offset:88
	scratch_store_b128 off, v[20:23], off offset:68
.LBB2_78:                               ; %Flow619
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_79:                               ; %Flow620
	s_and_not1_saveexec_b32 s2, s14
	s_cbranch_execz .LBB2_81
; %bb.80:
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b32 v16, off, off offset:24
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v25, v18 :: v_dual_mov_b32 v26, v19
	v_mov_b32_e32 v27, v35
	v_mov_b32_e32 v23, v35
	v_mov_b32_e32 v17, v35
	v_mov_b32_e32 v37, v35
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[24:27], off offset:48
	v_mov_b32_e32 v25, v24
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v35, off offset:88
	scratch_store_b32 off, v35, off offset:68
.LBB2_81:                               ; %Flow621
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_82:                               ; %Flow622
	s_and_not1_saveexec_b32 s2, s10
	s_cbranch_execz .LBB2_84
; %bb.83:
	s_clause 0x1
	scratch_load_b32 v16, off, off offset:32
	scratch_load_b96 v[20:22], off, off offset:48
	v_mov_b32_e32 v23, v17
	v_mov_b32_e32 v35, v17
	v_mov_b32_e32 v37, v17
	v_mov_b32_e32 v28, v17
	s_waitcnt vmcnt(1)
	scratch_store_b32 off, v16, off offset:24
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v27, v22 :: v_dual_mov_b32 v26, v21
	v_mov_b32_e32 v25, v20
	v_dual_mov_b32 v24, v20 :: v_dual_mov_b32 v19, v22
	v_mov_b32_e32 v18, v21
	s_clause 0x3
	scratch_store_b32 off, v17, off offset:88
	scratch_store_b32 off, v20, off offset:36
	scratch_store_b32 off, v17, off offset:60
	scratch_store_b96 off, v[26:28], off offset:72
.LBB2_84:                               ; %Flow623
	s_or_b32 exec_lo, exec_lo, s2
.LBB2_85:                               ; %Flow624
	s_and_not1_saveexec_b32 s2, s8
	s_cbranch_execz .LBB2_87
; %bb.86:
	s_clause 0x1
	scratch_load_b32 v25, off, off offset:48
	scratch_load_b32 v16, off, off offset:32
	v_dual_mov_b32 v35, v18 :: v_dual_mov_b32 v36, v19
	v_mov_b32_e32 v17, v37
	v_mov_b32_e32 v23, v37
	scratch_store_b96 off, v[35:37], off offset:52
	v_mov_b32_e32 v35, v37
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v16, off offset:24
	scratch_store_b32 off, v25, off offset:36
	scratch_store_b32 off, v37, off offset:68
	scratch_store_b32 off, v37, off offset:80
	v_mov_b32_e32 v24, v25
.LBB2_87:                               ; %_Z13xsymmetry_topPfii.exit
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x1
	scratch_load_b32 v22, off, off offset:56
	scratch_load_b32 v20, off, off offset:20
	v_mov_b32_e32 v36, v19
	s_or_b32 s15, s15, exec_lo
	s_and_not1_b32 s7, s7, exec_lo
	s_waitcnt vmcnt(0)
	s_clause 0x1
	scratch_store_b32 off, v20, off offset:28
	scratch_store_b64 off, v[24:25], off offset:40
	v_mov_b32_e32 v16, v22
.LBB2_88:                               ; %Flow637
	s_or_b32 exec_lo, exec_lo, s9
	s_mov_b32 s3, 0
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
; %bb.89:                               ; %LeafBlock580
	v_cmp_ne_u32_e32 vcc_lo, 10, v31
	s_and_not1_b32 s7, s11, exec_lo
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s11, s7, s8
; %bb.90:                               ; %Flow638
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s7, s6
; %bb.91:                               ; %LeafBlock578
	v_cmp_eq_u32_e32 vcc_lo, 1, v31
	v_cmp_ne_u32_e64 s2, 1, v31
	s_and_not1_b32 s3, s3, exec_lo
	s_and_not1_b32 s6, s11, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr36
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s3, s3, s8
	s_or_b32 s11, s6, s2
; %bb.92:                               ; %Flow639
	s_or_b32 exec_lo, exec_lo, s7
	s_and_saveexec_b32 s2, s11
	s_cbranch_execz .LBB2_94
; %bb.93:                               ; %_Z8ImageFcniii.exit._crit_edge
	scratch_load_b32 v22, off, off offset:56
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v19, v11
	v_dual_mov_b32 v36, v33 :: v_dual_mov_b32 v23, v3
	v_dual_mov_b32 v17, v9 :: v_dual_mov_b32 v18, v10
	v_mov_b32_e32 v35, v32
	v_mov_b32_e32 v37, v34
	s_and_not1_b32 s3, s3, exec_lo
	s_or_b32 s15, s15, exec_lo
.LBB2_94:                               ; %Flow640
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s15
	s_cbranch_execz .LBB2_97
; %bb.95:
	s_clause 0x2
	scratch_load_b128 v[28:31], off, off offset:16
	scratch_load_b128 v[24:27], off, off offset:32
	scratch_load_b64 v[20:21], off, off offset:48
	s_waitcnt vmcnt(3)
	v_dual_sub_f32 v47, v22, v23 :: v_dual_sub_f32 v48, v23, v17
	v_sub_f32_e32 v49, v22, v16
	s_load_b32 s1, s[0:1], 0x20
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v47, v16, v47
	s_lshl_b32 s6, s12, 6
	v_dual_sub_f32 v48, v48, v35 :: v_dual_sub_f32 v47, v47, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v48, v48, v37 :: v_dual_sub_f32 v47, v47, v19
	v_add_f32_e32 v47, v35, v47
	s_waitcnt vmcnt(1)
	v_dual_sub_f32 v51, v29, v31 :: v_dual_add_f32 v60, v30, v24
	v_sub_f32_e32 v52, v30, v24
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v53, v22, v21 :: v_dual_sub_f32 v62, v25, v26
	v_dual_sub_f32 v50, v47, v36 :: v_dual_mov_b32 v47, v42
	v_dual_sub_f32 v54, v25, v28 :: v_dual_mul_f32 v55, -4.0, v29
	v_add_f32_e32 v52, v25, v52
	v_dual_mul_f32 v56, 0x40400000, v29 :: v_dual_sub_f32 v49, v49, v19
	v_dual_mul_f32 v57, 0x40400000, v30 :: v_dual_add_f32 v60, v25, v60
	v_fma_f32 v59, v29, 2.0, -v30
	v_dual_add_f32 v61, v24, v24 :: v_dual_add_f32 v54, v26, v54
	v_sub_f32_e64 v63, -v26, v25
	v_dual_add_f32 v51, v51, v25 :: v_dual_add_f32 v64, v62, v27
	v_dual_add_f32 v53, v23, v53 :: v_dual_sub_f32 v62, v62, v27
	v_dual_fmamk_f32 v55, v28, 0x41400000, v55 :: v_dual_add_f32 v52, v26, v52
	v_dual_fmac_f32 v59, 2.0, v31 :: v_dual_add_f32 v54, v27, v54
	v_fma_f32 v61, v30, -2.0, -v61
	v_dual_add_f32 v63, v63, v27 :: v_dual_add_f32 v60, v26, v60
	v_dual_add_f32 v53, v16, v53 :: v_dual_add_f32 v62, v62, v20
	v_dual_sub_f32 v51, v51, v26 :: v_dual_sub_f32 v64, v64, v20
	v_dual_fmac_f32 v55, -4.0, v30 :: v_dual_sub_f32 v52, v52, v27
	v_dual_sub_f32 v59, v59, v24 :: v_dual_add_f32 v54, v20, v54
	v_dual_add_f32 v61, v25, v61 :: v_dual_add_f32 v60, v27, v60
	v_dual_add_f32 v63, v63, v20 :: v_dual_sub_f32 v62, v62, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v51, v51, v27 :: v_dual_sub_f32 v52, v52, v20
	v_dual_fmac_f32 v55, -4.0, v31 :: v_dual_add_f32 v60, v20, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v59, v25, v59 :: v_dual_add_f32 v62, v62, v16
	v_add_f32_e32 v63, v63, v23
	v_dual_add_f32 v53, v17, v53 :: v_dual_add_f32 v54, v22, v54
	v_dual_add_f32 v61, v26, v61 :: v_dual_add_f32 v52, v23, v52
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_add_f32 v51, v51, v20 :: v_dual_sub_f32 v62, v62, v19
	v_sub_f32_e32 v60, v60, v21
	v_dual_sub_f32 v63, v63, v17 :: v_dual_add_f32 v50, v37, v50
	v_dual_sub_f32 v53, v53, v18 :: v_dual_sub_f32 v52, v52, v17
	v_dual_fmac_f32 v55, -4.0, v24 :: v_dual_add_f32 v54, v23, v54
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v62, v62, v36 :: v_dual_add_f32 v63, v63, v35
	v_fma_f32 v56, 0x40400000, v31, -v56
	v_dual_add_f32 v59, v26, v59 :: v_dual_add_f32 v54, v16, v54
	v_dual_add_f32 v61, v27, v61 :: v_dual_sub_f32 v60, v60, v22
	v_dual_sub_f32 v53, v53, v19 :: v_dual_add_f32 v52, v35, v52
	v_sub_f32_e32 v63, v63, v37
	v_add_f32_e32 v55, v25, v55
	v_fma_f32 v57, 0x40400000, v24, -v57
	v_dual_add_f32 v51, v51, v22 :: v_dual_sub_f32 v60, v60, v16
	v_dual_add_f32 v59, v27, v59 :: v_dual_add_f32 v54, v17, v54
	v_dual_add_f32 v61, v20, v61 :: v_dual_add_f32 v68, v62, v63
	v_dual_sub_f32 v53, v53, v35 :: v_dual_add_f32 v74, v63, v50
	v_dual_sub_f32 v70, v63, v50 :: v_dual_add_f32 v55, v26, v55
	v_sub_f32_e32 v52, v52, v37
	v_dual_add_f32 v59, v20, v59 :: v_dual_add_f32 v54, v19, v54
	v_dual_fmac_f32 v61, 2.0, v21 :: v_dual_sub_f32 v60, v60, v18
	v_sub_f32_e32 v53, v53, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f32_e32 v57, v57, v52
	v_dual_add_f32 v49, v49, v36 :: v_dual_mul_f32 v58, 0x40400000, v21
	v_sub_f32_e32 v51, v51, v16
	v_dual_sub_f32 v59, v59, v21 :: v_dual_sub_f32 v60, v60, v19
	v_dual_sub_f32 v65, v62, v63 :: v_dual_mul_f32 v78, 0x3fd55555, v57
	v_dual_add_f32 v54, v35, v54 :: v_dual_sub_f32 v53, v53, v37
	v_fma_f32 v58, 0x40400000, v18, -v58
	v_sub_f32_e64 v66, -v62, v63
	v_dual_sub_f32 v67, v63, v62 :: v_dual_sub_f32 v60, v60, v36
	v_add_f32_e32 v71, v62, v50
	v_sub_f32_e64 v72, -v63, v50
	v_sub_f32_e64 v73, -v62, v50
	v_fma_f32 v48, -v52, v53, v48
	v_sub_f32_e32 v69, v50, v62
	v_sub_f32_e32 v62, v62, v50
	v_sub_f32_e32 v50, v50, v63
	v_dual_add_f32 v51, v51, v19 :: v_dual_add_f32 v58, v58, v53
	v_mul_f32_e32 v75, v53, v53
	v_mul_f32_e32 v63, v52, v52
	v_dual_add_f32 v55, v27, v55 :: v_dual_add_f32 v54, v36, v54
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v51, v51, v36 :: v_dual_mul_f32 v58, 0x3fd55555, v58
	v_sub_f32_e32 v61, v61, v22
	v_add_f32_e32 v59, v22, v59
	v_fma_f32 v79, v52, v52, v75
	v_add_f32_e32 v56, v56, v51
	v_add_f32_e32 v76, v51, v51
	v_fma_f32 v64, -v51, v52, v64
	v_fma_f32 v52, v52, v52, -v75
	v_fmac_f32_e32 v63, v51, v51
	v_dual_add_f32 v55, v20, v55 :: v_dual_add_f32 v54, v37, v54
	v_mul_f32_e32 v48, 0x3e800000, v48
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v52, v60, v52
	v_fmamk_f32 v60, v56, 0x3fd55555, v78
	v_fma_f32 v49, -v51, v53, v49
	v_fma_f32 v51, v51, v76, -v79
	v_dual_fmamk_f32 v76, v57, 0x3fd55555, v58 :: v_dual_fmac_f32 v59, -2.0, v23
	v_fmac_f32_e32 v63, v53, v53
	v_sub_f32_e32 v61, v61, v16
	v_fmac_f32_e32 v55, -4.0, v21
	v_mul_f32_e32 v77, 0x3fd55555, v56
	v_add_f32_e32 v59, v16, v59
	v_dual_sub_f32 v54, v54, v63 :: v_dual_fmamk_f32 v75, v56, 0x3fd55555, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v59, -2.0, v17 :: v_dual_mul_f32 v54, 0x41980000, v54
	v_sub_f32_e32 v59, v59, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v59, v19, v59
	v_fmac_f32_e32 v59, -2.0, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v59, v36, v59
	v_fmac_f32_e32 v59, -2.0, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v51, v59, v51
	v_fmamk_f32 v81, v51, 0xbd638e39, v48
	v_fma_f32 v48, 0xbd638e39, v51, -v48
	v_mul_f32_e32 v79, 0xbc4d5033, v54
	v_add_f32_e32 v55, v22, v55
	s_waitcnt lgkmcnt(0)
	v_dual_mul_f32 v59, 0x3daaaaab, v52 :: v_dual_mul_f32 v80, s1, v51
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v55, v23, v55
	v_add_f32_e32 v55, v16, v55
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v55, v17, v55
	v_fmac_f32_e32 v55, -4.0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v53, v19, v55
	v_add_f32_e32 v53, v35, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v53, v36, v53
	v_add_f32_e32 v53, v37, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmamk_f32 v53, v63, 0x40f14514, v53
	v_fmamk_f32 v63, v51, 0x3ce38e39, v59
	v_fma_f32 v59, 0x3ce38e39, v51, -v59
	v_fmamk_f32 v82, v64, 0x3e800000, v63
	v_fmac_f32_e32 v63, 0xbe800000, v64
	v_mul_f32_e32 v51, 0xbc820821, v53
	v_fmamk_f32 v64, v53, 0x3d430c31, v79
	v_fmamk_f32 v79, v49, 0x3e800000, v59
	v_fmac_f32_e32 v59, 0xbe800000, v49
	v_mul_f32_e32 v53, 0x3b820821, v53
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmamk_f32 v51, v54, 0xbb969026, v51 :: v_dual_sub_f32 v28, v28, v64
	v_fma_f32 v57, 0x3fd55555, v57, -v58
	v_fmamk_f32 v49, v54, 0x3b5b0037, v53
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmamk_f32 v64, v77, 0x3dcccccd, v51
	v_fmac_f32_e32 v61, 2.0, v18
	v_fmamk_f32 v53, v77, 0xbdcccccd, v51
	v_fmamk_f32 v54, v78, 0xbdcccccd, v51
	v_fmamk_f32 v86, v76, 0x3ccccccd, v49
	v_dual_fmac_f32 v64, 0x3d638e39, v80 :: v_dual_sub_f32 v61, v61, v19
	v_fmamk_f32 v77, v78, 0x3dcccccd, v51
	v_fmamk_f32 v84, v58, 0xbdcccccd, v51
	v_fmac_f32_e32 v51, 0x3dcccccd, v58
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_fmac_f32 v86, 0x3e000000, v70 :: v_dual_sub_f32 v55, v61, v36
	v_fma_f32 v61, 0x3fd55555, v56, -v78
	v_fmamk_f32 v78, v60, 0x3ccccccd, v49
	v_fmamk_f32 v60, v60, 0xbccccccd, v49
	v_fma_f32 v56, 0x3fd55555, v56, -v58
	v_fmamk_f32 v58, v75, 0xbccccccd, v49
	v_fmamk_f32 v83, v61, 0xbccccccd, v49
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmamk_f32 v61, v61, 0x3ccccccd, v49 :: v_dual_add_f32 v60, 0, v60
	v_fma_f32 v52, v52, s1, -v55
	v_add_f32_e32 v58, 0, v58
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v84, 0xbce38e39, v80 :: v_dual_add_f32 v61, 0, v61
	v_fmac_f32_e32 v60, 0x3d2aaaab, v55
	v_fmac_f32_e32 v51, 0xbce38e39, v80
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v58, 0xbd2aaaab, v55
	v_fmac_f32_e32 v84, 0xbdaaaaab, v52
	v_fmac_f32_e32 v61, 0x3d2aaaab, v55
	v_fmac_f32_e32 v60, 0x3e000000, v67
	v_fmac_f32_e32 v51, 0xbdaaaaab, v52
	v_fmac_f32_e32 v58, 0x3e000000, v62
	v_fmac_f32_e32 v54, 0xbce38e39, v80
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v61, 0x3e000000, v68 :: v_dual_fmac_f32 v60, s1, v82
	v_sub_f32_e32 v18, v18, v51
	v_fmac_f32_e32 v86, s1, v81
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v54, 0x3daaaaab, v52 :: v_dual_fmac_f32 v61, s1, v63
	v_sub_f32_e32 v27, v27, v60
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v23, v23, v86
	v_sub_f32_e32 v30, v30, v54
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v20, v20, v61 :: v_dual_fmamk_f32 v85, v75, 0x3ccccccd, v49
	v_fmamk_f32 v87, v56, 0xbccccccd, v49
	v_dual_fmamk_f32 v56, v56, 0x3ccccccd, v49 :: v_dual_add_f32 v75, 0, v78
	v_fmamk_f32 v88, v57, 0xbccccccd, v49
	v_dual_add_f32 v78, 0, v85 :: v_dual_fmamk_f32 v57, v57, 0x3ccccccd, v49
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v56, 0, v56
	v_sub_f32_e32 v31, v31, v64
	v_fmac_f32_e32 v49, 0xbccccccd, v76
	v_fmac_f32_e32 v78, 0xbd2aaaab, v55
	v_fmac_f32_e32 v57, 0x3e000000, v74
	v_dual_fmac_f32 v56, 0xbd2aaaab, v55 :: v_dual_sub_f32 v21, v21, v84
	v_add_f32_e32 v70, 0, v87
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v78, 0x3e000000, v69
	v_fmac_f32_e32 v75, 0x3d2aaaab, v55
	v_fmac_f32_e32 v56, 0x3e000000, v73
	v_fmac_f32_e32 v88, 0x3e000000, v72
	v_fmac_f32_e32 v70, 0xbd2aaaab, v55
	v_fmac_f32_e32 v49, 0x3e000000, v50
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v75, 0x3e000000, v65 :: v_dual_fmac_f32 v56, s1, v59
	v_fmac_f32_e32 v78, s1, v79
	v_dual_fmac_f32 v70, 0x3e000000, v71 :: v_dual_fmac_f32 v49, s1, v81
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v58, s1, v79 :: v_dual_fmac_f32 v75, s1, v82
	v_sub_f32_e32 v22, v22, v78
	v_add_f32_e32 v76, 0, v83
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v70, s1, v59
	v_dual_fmac_f32 v88, s1, v48 :: v_dual_sub_f32 v25, v25, v75
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v19, v19, v56 :: v_dual_fmac_f32 v76, 0x3d2aaaab, v55
	v_dual_fmac_f32 v57, s1, v48 :: v_dual_sub_f32 v16, v16, v70
	v_fmac_f32_e32 v77, 0xbce38e39, v80
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v17, v17, v88 :: v_dual_fmac_f32 v76, 0x3e000000, v66
	v_sub_f32_e32 v35, v35, v57
	v_sub_f32_e32 v37, v37, v49
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v77, 0x3daaaaab, v52 :: v_dual_sub_f32 v36, v36, v58
	v_fmac_f32_e32 v76, s1, v63
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, v24, v77
	v_sub_f32_e32 v26, v26, v76
	v_fmac_f32_e32 v53, 0x3d638e39, v80
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v29, v29, v53
	s_clause 0x4
	scratch_store_b128 off, v[28:31], off offset:16
	scratch_store_b128 off, v[24:27], off offset:32
	scratch_store_b128 off, v[20:23], off offset:48
	scratch_store_b128 off, v[16:19], off offset:64
	scratch_store_b96 off, v[35:37], off offset:80
.LBB2_96:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s0, 16
	v_max_i32_e32 v16, 0, v47
	scratch_load_b32 v18, off, s1
	v_add_nc_u32_e32 v47, s6, v47
	s_add_i32 s0, s0, 4
	v_cmp_gt_i32_e32 vcc_lo, s20, v16
	s_cmpk_lg_i32 s0, 0x4c
	v_cndmask_b32_e32 v16, s13, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s4, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[16:17], v18, off
	s_cbranch_scc1 .LBB2_96
.LBB2_97:                               ; %Flow641
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB2_99
; %bb.98:
	v_add_nc_u32_e32 v16, 0x80, v39
	v_max_i32_e32 v17, 0, v42
	v_add_nc_u32_e32 v20, v38, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v19, v16, s12
	v_cmp_gt_i32_e32 vcc_lo, s20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v20, 0, v20
	v_dual_cndmask_b32 v16, s13, v17 :: v_dual_add_nc_u32 v21, v38, v19
	v_add_nc_u32_e32 v23, s18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v17, 31, v16
	v_max_i32_e32 v21, 0, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v24, v38, v23
	v_add_nc_u32_e32 v25, s16, v23
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_max_i32_e32 v24, 0, v24
	v_add_nc_u32_e32 v18, v38, v46
	v_add_nc_u32_e32 v26, v38, v25
	v_add_nc_u32_e32 v25, s16, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v18, 0, v18
	v_cmp_gt_i32_e32 vcc_lo, s20, v18
	v_cndmask_b32_e32 v18, s13, v18, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v19, 31, v18
	v_cndmask_b32_e32 v20, s13, v20, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v21
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v22, s13, v21, vcc_lo
	v_add_co_u32 v16, vcc_lo, s4, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v23, 31, v22
	v_add_co_u32 v18, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, s4, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v23, vcc_lo
	s_clause 0x2
	global_store_b32 v[16:17], v12, off
	global_store_b32 v[18:19], v15, off
	global_store_b32 v[22:23], v4, off
	v_lshlrev_b64 v[15:16], 2, v[20:21]
	v_cmp_gt_i32_e32 vcc_lo, s20, v24
	v_max_i32_e32 v4, 0, v26
	v_add_nc_u32_e32 v12, v38, v25
	v_add_nc_u32_e32 v21, s16, v25
	v_cndmask_b32_e32 v17, s13, v24, vcc_lo
	v_add_co_u32 v15, vcc_lo, s4, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
	v_max_i32_e32 v19, 0, v12
	v_cmp_gt_i32_e32 vcc_lo, s20, v4
	v_ashrrev_i32_e32 v18, 31, v17
	global_store_b32 v[15:16], v13, off
	v_add_nc_u32_e32 v23, s16, v21
	v_cndmask_b32_e32 v12, s13, v4, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v19
	v_add_nc_u32_e32 v4, v38, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v21, v38, v23
	v_lshlrev_b64 v[15:16], 2, v[17:18]
	v_ashrrev_i32_e32 v13, 31, v12
	v_cndmask_b32_e32 v19, s13, v19, vcc_lo
	v_max_i32_e32 v4, 0, v4
	v_add_co_u32 v15, vcc_lo, s4, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v20, 31, v19
	v_cmp_gt_i32_e32 vcc_lo, s20, v4
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[17:18], 2, v[19:20]
	v_cndmask_b32_e32 v19, s13, v4, vcc_lo
	v_max_i32_e32 v4, 0, v21
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s20, v4
	v_ashrrev_i32_e32 v20, 31, v19
	s_clause 0x1
	global_store_b32 v[15:16], v14, off
	global_store_b32 v[12:13], v7, off
	v_add_nc_u32_e32 v7, s19, v23
	v_cndmask_b32_e32 v21, s13, v4, vcc_lo
	v_add_co_u32 v17, vcc_lo, s4, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v22, 31, v21
	v_lshlrev_b64 v[12:13], 2, v[19:20]
	v_add_nc_u32_e32 v16, v38, v7
	global_store_b32 v[17:18], v0, off
	v_add_nc_u32_e32 v0, v38, v43
	v_lshlrev_b64 v[14:15], 2, v[21:22]
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_max_i32_e32 v0, 0, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	global_store_b32 v[12:13], v5, off
	v_add_nc_u32_e32 v12, v38, v44
	global_store_b32 v[14:15], v6, off
	v_cndmask_b32_e32 v4, s13, v0, vcc_lo
	v_max_i32_e32 v0, 0, v16
	v_add_nc_u32_e32 v16, s18, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_cndmask_b32_e32 v6, s13, v0, vcc_lo
	v_max_i32_e32 v0, 0, v12
	v_add_co_u32 v12, vcc_lo, s4, v40
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v41, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_ashrrev_i32_e32 v7, 31, v6
	global_store_b32 v[12:13], v10, off
	v_cndmask_b32_e32 v14, s13, v0, vcc_lo
	v_add_nc_u32_e32 v0, v38, v16
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_max_i32_e32 v0, 0, v0
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	global_store_b32 v[4:5], v33, off
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_lshlrev_b64 v[4:5], 2, v[14:15]
	v_cndmask_b32_e32 v12, s13, v0, vcc_lo
	v_add_nc_u32_e32 v0, s16, v16
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_nc_u32_e32 v10, v38, v0
	v_add_nc_u32_e32 v0, s16, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_clause 0x1
	global_store_b32 v[6:7], v34, off
	global_store_b32 v[4:5], v11, off
	v_max_i32_e32 v6, 0, v10
	v_add_nc_u32_e32 v7, s16, v0
	v_add_nc_u32_e32 v0, v38, v0
	v_add_co_u32 v4, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v10, v38, v7
	v_cmp_gt_i32_e32 vcc_lo, s20, v6
	v_add_nc_u32_e32 v11, s16, v7
	v_max_i32_e32 v0, 0, v0
	global_store_b32 v[4:5], v32, off
	v_max_i32_e32 v5, 0, v10
	v_cndmask_b32_e32 v6, s13, v6, vcc_lo
	v_add_nc_u32_e32 v12, v38, v11
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_add3_u32 v13, v11, s16, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v6
	v_cndmask_b32_e32 v4, s13, v0, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s20, v5
	v_max_i32_e32 v0, 0, v12
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_cndmask_b32_e32 v10, s13, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v11, 31, v10
	v_cndmask_b32_e32 v12, s13, v0, vcc_lo
	v_max_i32_e32 v0, 0, v13
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s20, v0
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_cndmask_b32_e32 v14, s13, v0, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v10, vcc_lo, s4, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	s_clause 0x4
	global_store_b32 v[6:7], v1, off
	global_store_b32 v[4:5], v8, off
	global_store_b32 v[10:11], v9, off
	global_store_b32 v[12:13], v2, off
	global_store_b32 v[14:15], v3, off
.LBB2_99:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10update_botPfS_S_S_fmii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 96
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 89
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10update_botPfS_S_S_fmii, .Lfunc_end2-_Z10update_botPfS_S_S_fmii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 11404
; NumSgprs: 34
; NumVgprs: 89
; ScratchSize: 96
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 89
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10update_innPfS_S_S_fmiiPS_S0_i ; -- Begin function _Z10update_innPfS_S_S_fmiiPS_S0_i
	.globl	_Z10update_innPfS_S_S_fmiiPS_S0_i
	.p2align	8
	.type	_Z10update_innPfS_S_S_fmiiPS_S0_i,@function
_Z10update_innPfS_S_S_fmiiPS_S0_i:      ; @_Z10update_innPfS_S_S_fmiiPS_S0_i
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x5c
	v_and_b32_e32 v1, 0x3ff, v0
                                        ; implicit-def: $sgpr5
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[33:34], null, s13, s4, v[1:2]
	v_bfe_u32 v1, v0, 10, 10
	v_cvt_f32_i32_e32 v2, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, 0xc1bc0000, v2
	v_mad_u64_u32 v[34:35], null, s14, s2, v[1:2]
	v_cmp_nlt_f32_e64 s4, |v2|, 4.0
	s_and_b32 s2, s3, 0xffff
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_f32_e64 |v2|, 4.0
; %bb.1:
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v34
	s_and_not1_b32 s4, s4, exec_lo
	v_add_f32_e32 v1, 0xc1bc0000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_nlt_f32_e64 s5, |v1|, 4.0
	s_and_b32 s6, s5, exec_lo
	s_mov_b32 s5, 10
	s_or_b32 s4, s4, s6
; %bb.2:                                ; %Flow901
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v40, s5
	s_and_saveexec_b32 s3, s4
	s_cbranch_execz .LBB3_12
; %bb.3:                                ; %NodeBlock
	s_mov_b32 s4, 0
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $sgpr5
	v_cmpx_lt_i32_e32 62, v34
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB3_7
; %bb.4:                                ; %LeafBlock824
	s_mov_b32 s4, -1
	s_mov_b32 s7, exec_lo
                                        ; implicit-def: $sgpr5
	v_cmpx_eq_u32_e32 63, v34
; %bb.5:
	s_movk_i32 s5, 0x64
	s_xor_b32 s4, exec_lo, -1
; %bb.6:                                ; %Flow896
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s4, exec_lo
.LBB3_7:                                ; %Flow895
	s_or_saveexec_b32 s6, s6
	v_mov_b32_e32 v40, s5
	s_xor_b32 exec_lo, exec_lo, s6
; %bb.8:                                ; %LeafBlock
	v_cmp_ne_u32_e32 vcc_lo, 0, v34
	v_mov_b32_e32 v40, 0xc8
	s_and_not1_b32 s4, s4, exec_lo
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s4, s5
; %bb.9:                                ; %Flow897
	s_or_b32 exec_lo, exec_lo, s6
	s_and_saveexec_b32 s5, s4
; %bb.10:
	v_cmp_eq_u32_e32 vcc_lo, 63, v33
	v_cndmask_b32_e64 v1, 0, 25, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v33
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v40, 26, v1, vcc_lo
; %bb.11:                               ; %Flow898
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_12:                               ; %Flow902
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b128 s[16:19], s[0:1], 0x28
	v_bfe_u32 v0, v0, 20, 10
	s_and_b32 s2, s2, 0xffff
	s_mov_b32 s3, 0
	v_add_nc_u32_e32 v18, 1, v34
	v_add_nc_u32_e32 v12, 1, v33
	v_mad_u64_u32 v[16:17], null, s15, s2, v[0:1]
	s_load_b256 s[8:15], s[0:1], 0x0
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v39, 6, v16
	v_add_co_u32 v35, null, v39, v34
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s2, s19
	s_mul_i32 s4, s16, 0x4c0
	s_lshl_b64 s[6:7], s[2:3], 6
	s_lshl_b32 s17, s19, 8
	v_add_nc_u32_e32 v0, s6, v35
	s_mul_i32 s7, s4, s19
	v_add3_u32 v11, v39, v18, s17
	s_add_i32 s17, s7, -1
	v_add_nc_u32_e32 v21, -1, v34
	v_mul_lo_u32 v36, v0, s16
	s_lshl_b64 s[20:21], s[2:3], 7
	v_add_nc_u32_e32 v13, -1, v33
	v_add_nc_u32_e32 v2, s20, v0
	v_mad_u64_u32 v[0:1], null, v35, s16, v[33:34]
	v_add3_u32 v1, v39, v21, s20
	s_mul_i32 s5, s19, 0xc0
	v_add_nc_u32_e32 v4, v13, v36
	v_mul_lo_u32 v37, v2, s16
	s_add_i32 s3, s19, -1
	v_mad_u64_u32 v[2:3], null, v1, s16, v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_max_i32_e32 v6, 0, v4
	v_add_nc_u32_e32 v5, s5, v1
	v_ashrrev_i32_e32 v1, 31, v0
	v_cmp_gt_i32_e32 vcc_lo, s7, v6
	v_max_i32_e32 v2, 0, v2
	v_add_nc_u32_e32 v7, v12, v37
	v_mad_u64_u32 v[3:4], null, v5, s16, v[13:14]
	v_cndmask_b32_e32 v4, s17, v6, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_max_i32_e32 v6, 0, v7
	v_add_nc_u32_e32 v7, s6, v5
	v_ashrrev_i32_e32 v5, 31, v4
	v_max_i32_e32 v14, 0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s7, v6
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_cndmask_b32_e32 v6, s17, v6, vcc_lo
	v_mad_u64_u32 v[8:9], null, v7, s16, v[12:13]
	v_cmp_gt_i32_e32 vcc_lo, s7, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v6
	v_cndmask_b32_e32 v2, s17, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s10, v6
	v_mad_u64_u32 v[4:5], null, v11, s16, v[33:34]
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
	v_add_nc_u32_e32 v5, s5, v11
	v_cmp_gt_i32_e32 vcc_lo, s7, v14
	v_max_i32_e32 v8, 0, v8
	v_ashrrev_i32_e32 v3, 31, v2
	v_max_i32_e32 v11, 0, v4
	v_mad_u64_u32 v[19:20], null, v5, s16, v[12:13]
	v_cndmask_b32_e32 v14, s17, v14, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v8
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_nc_u32_e32 v5, s6, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v15, 31, v14
	v_cndmask_b32_e32 v4, s17, v8, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v11
	v_max_i32_e32 v8, 0, v19
	v_mad_u64_u32 v[19:20], null, v5, s16, v[13:14]
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_cndmask_b32_e32 v22, s17, v11, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v8
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v23, 31, v22
                                        ; implicit-def: $vgpr11
	v_cndmask_b32_e32 v24, s17, v8, vcc_lo
	v_max_i32_e32 v8, 0, v19
	v_add_co_u32 v14, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s7, v8
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_lshlrev_b64 v[19:20], 2, v[22:23]
	v_ashrrev_i32_e32 v25, 31, v24
	v_cndmask_b32_e32 v22, s17, v8, vcc_lo
	v_add_co_u32 v26, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v27, vcc_lo, s11, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v23, 31, v22
	v_lshlrev_b64 v[4:5], 2, v[24:25]
	v_add_co_u32 v19, vcc_lo, s10, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s11, v20, vcc_lo
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v24, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v25, vcc_lo, s11, v5, vcc_lo
	v_add_co_u32 v22, vcc_lo, s10, v22
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v23, vcc_lo, s11, v23, vcc_lo
	s_clause 0x8
	global_load_b32 v4, v[0:1], off
	global_load_b32 v5, v[9:10], off
	global_load_b32 v7, v[6:7], off
	global_load_b32 v6, v[2:3], off
	global_load_b32 v1, v[14:15], off
	global_load_b32 v2, v[26:27], off
	global_load_b32 v0, v[19:20], off
	global_load_b32 v3, v[24:25], off
	global_load_b32 v38, v[22:23], off
	v_cmp_ne_u32_e32 vcc_lo, s3, v16
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr19_vgpr20
	s_waitcnt vmcnt(5)
	scratch_store_b128 off, v[4:7], off offset:16
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[0:3], off offset:32
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v38, off offset:48
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB3_18
; %bb.13:
	s_mul_i32 s21, s2, 0x380
	s_mul_i32 s5, s2, 0x480
	s_mov_b32 s22, exec_lo
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr17
	v_cmpx_ne_u32_e32 0, v16
	s_xor_b32 s22, exec_lo, s22
	s_cbranch_execz .LBB3_15
; %bb.14:
	v_subrev_nc_u32_e32 v4, 64, v39
	s_mul_i32 s23, s2, 0x240
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v10, v4, v34, s23
	s_mul_i32 s23, s2, 0x2c0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v11, s23, v21, v4
	s_mul_i32 s23, s2, 0x340
	v_mad_u64_u32 v[8:9], null, v10, s16, v[33:34]
	v_add_nc_u32_e32 v14, s6, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[9:10], null, v11, s16, v[33:34]
	v_add3_u32 v4, s23, v18, v4
	s_lshl_b32 s23, s2, 10
	v_mad_u64_u32 v[10:11], null, v14, s16, v[13:14]
	v_add_nc_u32_e32 v11, s20, v14
	v_max_i32_e32 v14, 0, v8
	v_max_i32_e32 v15, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, v11, s16, v[12:13]
	v_cmp_gt_i32_e32 vcc_lo, s7, v14
	v_max_i32_e32 v10, 0, v10
	v_cndmask_b32_e32 v9, s17, v14, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v15
	v_max_i32_e32 v22, 0, v8
	v_cndmask_b32_e32 v14, s17, v15, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v15, 31, v14
	v_cndmask_b32_e32 v19, s17, v10, vcc_lo
	v_ashrrev_i32_e32 v10, 31, v9
	v_cmp_gt_i32_e32 vcc_lo, s7, v22
	v_add_nc_u32_e32 v17, 64, v39
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 2, v[9:10]
	v_lshlrev_b64 v[10:11], 2, v[14:15]
	v_cndmask_b32_e32 v14, s17, v22, vcc_lo
	v_mad_u64_u32 v[22:23], null, v4, s16, v[33:34]
	v_add3_u32 v4, v17, v34, s21
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	v_add_co_u32 v8, vcc_lo, s10, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v26, s6, v4
	v_max_i32_e32 v25, 0, v22
	v_mad_u64_u32 v[22:23], null, v4, s16, v[33:34]
	v_add_co_u32 v19, vcc_lo, s10, v19
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_co_ci_u32_e32 v20, vcc_lo, s11, v20, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_mad_u64_u32 v[23:24], null, v26, s16, v[13:14]
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	v_lshlrev_b64 v[13:14], 2, v[14:15]
	v_add3_u32 v4, s23, v21, v17
	v_cmp_gt_i32_e32 vcc_lo, s7, v25
	v_max_i32_e32 v15, 0, v22
	v_cndmask_b32_e32 v21, s17, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[24:25], null, v4, s16, v[33:34]
	v_max_i32_e32 v4, 0, v23
	v_cmp_gt_i32_e32 vcc_lo, s7, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v22, 31, v21
	v_cndmask_b32_e32 v23, s17, v15, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v4
	v_add_nc_u32_e32 v15, s20, v26
	v_cndmask_b32_e32 v25, s17, v4, vcc_lo
	v_max_i32_e32 v4, 0, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[27:28], null, v15, s16, v[12:13]
	v_add_co_u32 v28, vcc_lo, s10, v13
	v_add_co_ci_u32_e32 v29, vcc_lo, s11, v14, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v4
	v_lshlrev_b64 v[12:13], 2, v[21:22]
	v_ashrrev_i32_e32 v24, 31, v23
	v_ashrrev_i32_e32 v26, 31, v25
	v_cndmask_b32_e32 v14, s17, v4, vcc_lo
	v_max_i32_e32 v4, 0, v27
	v_add_co_u32 v21, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v22, vcc_lo, s11, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s7, v4
	v_lshlrev_b64 v[12:13], 2, v[23:24]
	v_lshlrev_b64 v[23:24], 2, v[25:26]
	v_ashrrev_i32_e32 v15, 31, v14
	v_cndmask_b32_e32 v25, s17, v4, vcc_lo
	v_add_co_u32 v30, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v31, vcc_lo, s11, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v26, 31, v25
	v_lshlrev_b64 v[12:13], 2, v[14:15]
	v_add_co_u32 v23, vcc_lo, s10, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s11, v24, vcc_lo
	v_lshlrev_b64 v[14:15], 2, v[25:26]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v25, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v26, vcc_lo, s11, v13, vcc_lo
	v_add_co_u32 v41, vcc_lo, s10, v14
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v42, vcc_lo, s11, v15, vcc_lo
	s_clause 0x8
	global_load_b32 v12, v[8:9], off
	global_load_b32 v13, v[19:20], off
	global_load_b32 v14, v[10:11], off
	global_load_b32 v15, v[28:29], off
	global_load_b32 v8, v[21:22], off
	global_load_b32 v9, v[30:31], off
	global_load_b32 v10, v[23:24], off
	global_load_b32 v11, v[25:26], off
	global_load_b32 v4, v[41:42], off
	v_add3_u32 v19, s5, v18, v17
                                        ; implicit-def: $vgpr21
	s_waitcnt vmcnt(5)
	scratch_store_b128 off, v[12:15], off offset:52
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[8:11], off offset:68
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v4, off offset:84
	v_mad_u64_u32 v[17:18], null, v19, s16, v[33:34]
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v17, 0, v17
	v_cmp_gt_i32_e32 vcc_lo, s7, v17
	v_cndmask_b32_e32 v17, s17, v17, vcc_lo
.LBB3_15:                               ; %Flow891
	s_or_saveexec_b32 s22, s22
	v_dual_mov_b32 v20, s11 :: v_dual_mov_b32 v19, s10
	s_xor_b32 exec_lo, exec_lo, s22
	s_cbranch_execz .LBB3_17
; %bb.16:
	v_add_nc_u32_e32 v4, 0x240, v34
	v_add_nc_u32_e32 v10, 0x2c0, v21
	s_add_i32 s23, s4, -1
	s_lshl_b32 s24, s16, 7
	v_add_nc_u32_e32 v11, 0x340, v18
	v_mul_lo_u32 v4, v4, s16
	v_mad_u64_u32 v[8:9], null, v10, s16, v[33:34]
	v_add3_u32 v17, v34, s21, 64
	s_lshl_b32 s21, s2, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v9, v33, v4
	v_lshl_add_u32 v4, s16, 6, v4
	v_max_i32_e32 v8, 0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v9, 0, v9
	v_add_nc_u32_e32 v14, v13, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s4, v8
	v_add3_u32 v4, v4, s24, v12
	v_max_i32_e32 v19, 0, v14
	v_cndmask_b32_e32 v8, s23, v8, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s4, v9
	v_mad_u64_u32 v[14:15], null, v11, s16, v[33:34]
	v_max_i32_e32 v4, 0, v4
	v_cndmask_b32_e32 v10, s23, v9, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s4, v19
	v_ashrrev_i32_e32 v9, 31, v8
	v_max_i32_e32 v26, 0, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v11, 31, v10
	v_cndmask_b32_e32 v19, s23, v19, vcc_lo
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_cmp_gt_i32_e32 vcc_lo, s4, v4
	v_mad_u64_u32 v[14:15], null, v17, s16, v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v20, 31, v19
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_cndmask_b32_e32 v22, s23, v4, vcc_lo
	v_add_co_u32 v8, vcc_lo, s12, v8
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	v_add_nc_u32_e32 v4, s6, v17
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s12, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
	v_add_co_u32 v19, vcc_lo, s12, v19
	v_mad_u64_u32 v[24:25], null, v4, s16, v[13:14]
	v_add_co_ci_u32_e32 v20, vcc_lo, s13, v20, vcc_lo
	v_add3_u32 v15, v21, s21, 64
	v_cmp_gt_i32_e32 vcc_lo, s4, v26
	v_max_i32_e32 v17, 0, v14
	v_ashrrev_i32_e32 v23, 31, v22
	v_add_nc_u32_e32 v4, s20, v4
	v_cndmask_b32_e32 v13, s23, v26, vcc_lo
	v_mad_u64_u32 v[25:26], null, v15, s16, v[33:34]
	v_max_i32_e32 v15, 0, v24
	v_cmp_gt_i32_e32 vcc_lo, s7, v17
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_ashrrev_i32_e32 v14, 31, v13
	v_mad_u64_u32 v[26:27], null, v4, s16, v[12:13]
	v_cndmask_b32_e32 v21, s17, v17, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[12:13], 2, v[13:14]
	v_cndmask_b32_e32 v24, s17, v15, vcc_lo
	v_max_i32_e32 v15, 0, v25
	v_add_co_u32 v27, vcc_lo, s12, v22
	v_add_co_ci_u32_e32 v28, vcc_lo, s13, v23, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v15
	v_max_i32_e32 v4, 0, v26
	v_ashrrev_i32_e32 v22, 31, v21
	v_ashrrev_i32_e32 v25, 31, v24
	v_cndmask_b32_e32 v14, s17, v15, vcc_lo
	v_add_co_u32 v29, vcc_lo, s12, v12
	v_add_co_ci_u32_e32 v30, vcc_lo, s13, v13, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v4
	v_lshlrev_b64 v[12:13], 2, v[21:22]
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[21:22], 2, v[24:25]
	v_cndmask_b32_e32 v23, s17, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v25, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v26, vcc_lo, s11, v13, vcc_lo
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[12:13], 2, v[14:15]
	v_add_co_u32 v21, vcc_lo, s10, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, s11, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 2, v[23:24]
	v_add_co_u32 v23, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v24, vcc_lo, s11, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v31, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v32, vcc_lo, s11, v15, vcc_lo
	s_clause 0x4
	global_load_b32 v12, v[10:11], off
	global_load_b32 v13, v[19:20], off
	global_load_b32 v14, v[8:9], off
	global_load_b32 v15, v[27:28], off
	global_load_b32 v8, v[29:30], off
	s_clause 0x3
	global_load_b32 v9, v[25:26], off
	global_load_b32 v10, v[21:22], off
	global_load_b32 v11, v[23:24], off
	global_load_b32 v4, v[31:32], off
	v_add3_u32 v19, v18, s5, 64
	s_waitcnt vmcnt(5)
	scratch_store_b128 off, v[12:15], off offset:52
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[8:11], off offset:68
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v4, off offset:84
	v_mad_u64_u32 v[17:18], null, v19, s16, v[33:34]
	v_dual_mov_b32 v20, s11 :: v_dual_mov_b32 v19, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v17, 0, v17
	v_cmp_gt_i32_e32 vcc_lo, s7, v17
	v_cndmask_b32_e32 v17, s17, v17, vcc_lo
.LBB3_17:                               ; %Flow892
	s_or_b32 exec_lo, exec_lo, s22
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr18
.LBB3_18:                               ; %Flow894
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB3_20
; %bb.19:
	v_subrev_nc_u32_e32 v4, 64, v39
	s_mul_i32 s5, s2, 0x240
	v_add_nc_u32_e32 v17, 0x380, v34
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v10, v4, v34, s5
	s_mul_i32 s5, s2, 0x2c0
	s_mulk_i32 s2, 0x340
	v_add3_u32 v11, s5, v21, v4
	v_add3_u32 v4, s2, v18, v4
	v_mad_u64_u32 v[8:9], null, v10, s16, v[33:34]
	v_add_nc_u32_e32 v14, s6, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, v11, s16, v[33:34]
	s_add_i32 s2, s4, -1
	s_lshl_b32 s5, s16, 7
	v_mad_u64_u32 v[10:11], null, v14, s16, v[13:14]
	v_add_nc_u32_e32 v11, s20, v14
	v_max_i32_e32 v14, 0, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_max_i32_e32 v15, 0, v9
	v_mad_u64_u32 v[8:9], null, v11, s16, v[12:13]
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s7, v14
	v_max_i32_e32 v10, 0, v10
	v_cndmask_b32_e32 v9, s17, v14, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v15
	v_max_i32_e32 v22, 0, v8
	v_cndmask_b32_e32 v14, s17, v15, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v15, 31, v14
	v_cndmask_b32_e32 v19, s17, v10, vcc_lo
	v_ashrrev_i32_e32 v10, 31, v9
	v_cmp_gt_i32_e32 vcc_lo, s7, v22
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[8:9], 2, v[9:10]
	v_lshlrev_b64 v[10:11], 2, v[14:15]
	v_cndmask_b32_e32 v14, s17, v22, vcc_lo
	v_mad_u64_u32 v[22:23], null, v4, s16, v[33:34]
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	v_add_co_u32 v8, vcc_lo, s10, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v15, 31, v14
	v_mul_lo_u32 v4, v17, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
	v_add_co_u32 v19, vcc_lo, s10, v19
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_ci_u32_e32 v20, vcc_lo, s11, v20, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	v_max_i32_e32 v17, 0, v22
	v_lshl_add_u32 v26, s16, 6, v4
	v_add_nc_u32_e32 v4, v33, v4
	v_add_co_u32 v22, vcc_lo, s10, v14
	v_add_co_ci_u32_e32 v23, vcc_lo, s11, v15, vcc_lo
	v_add_nc_u32_e32 v15, 0x400, v21
	v_cmp_gt_i32_e32 vcc_lo, s7, v17
	v_add_nc_u32_e32 v14, v13, v26
	v_max_i32_e32 v4, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[24:25], null, v15, s16, v[33:34]
	v_cndmask_b32_e32 v13, s17, v17, vcc_lo
	v_max_i32_e32 v15, 0, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s4, v4
	v_ashrrev_i32_e32 v14, 31, v13
	v_cndmask_b32_e32 v25, s2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s4, v15
	v_max_i32_e32 v4, 0, v24
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_cndmask_b32_e32 v27, s2, v15, vcc_lo
	v_add3_u32 v15, v26, s5, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s4, v4
	v_ashrrev_i32_e32 v26, 31, v25
	v_ashrrev_i32_e32 v28, 31, v27
	v_cndmask_b32_e32 v12, s2, v4, vcc_lo
	v_max_i32_e32 v4, 0, v15
	v_add_co_u32 v29, vcc_lo, s10, v13
	v_add_co_ci_u32_e32 v30, vcc_lo, s11, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s4, v4
	v_lshlrev_b64 v[14:15], 2, v[25:26]
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[24:25], 2, v[27:28]
	v_cndmask_b32_e32 v26, s2, v4, vcc_lo
	v_add_co_u32 v31, vcc_lo, s14, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_ashrrev_i32_e32 v27, 31, v26
	v_add_co_ci_u32_e32 v32, vcc_lo, s15, v15, vcc_lo
	v_add_co_u32 v24, vcc_lo, s14, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 2, v[26:27]
	v_add_co_ci_u32_e32 v25, vcc_lo, s15, v25, vcc_lo
	v_add_co_u32 v26, vcc_lo, s14, v12
	v_add_co_ci_u32_e32 v27, vcc_lo, s15, v13, vcc_lo
	v_add_co_u32 v41, vcc_lo, s14, v14
	v_add_co_ci_u32_e32 v42, vcc_lo, s15, v15, vcc_lo
	s_clause 0x4
	global_load_b32 v12, v[8:9], off
	global_load_b32 v13, v[19:20], off
	global_load_b32 v14, v[10:11], off
	global_load_b32 v15, v[22:23], off
	global_load_b32 v8, v[29:30], off
	s_clause 0x3
	global_load_b32 v9, v[31:32], off
	global_load_b32 v10, v[24:25], off
	global_load_b32 v11, v[26:27], off
	global_load_b32 v4, v[41:42], off
	v_add_nc_u32_e32 v19, 0x480, v18
	s_waitcnt vmcnt(5)
	scratch_store_b128 off, v[12:15], off offset:52
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[8:11], off offset:68
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v4, off offset:84
	v_mad_u64_u32 v[17:18], null, v19, s16, v[33:34]
	v_dual_mov_b32 v20, s15 :: v_dual_mov_b32 v19, s14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v17, 0, v17
	v_cmp_gt_i32_e32 vcc_lo, s4, v17
	v_cndmask_b32_e32 v17, s2, v17, vcc_lo
.LBB3_20:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	s_add_i32 s2, s19, 2
	s_mov_b32 s12, 0
	s_mul_i32 s2, s2, s18
	s_mov_b32 s15, 0
	v_lshlrev_b64 v[12:13], 2, v[17:18]
	v_add3_u32 v42, s2, 1, v16
	s_mov_b32 s2, 0
	s_mov_b32 s18, 0
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr29
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v19, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, v20, v13, vcc_lo
	global_load_b32 v41, v[12:13], off
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v41, off offset:88
	v_cmpx_lt_i32_e32 25, v40
	s_xor_b32 s13, exec_lo, s3
	s_cbranch_execz .LBB3_66
; %bb.21:                               ; %NodeBlock840
	s_mov_b32 s3, 0
	s_mov_b32 s14, 0
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr29
	v_cmpx_lt_i32_e32 0x63, v40
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_37
; %bb.22:                               ; %NodeBlock838
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
	s_mov_b32 s15, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr29
	v_cmpx_lt_i32_e32 0xc7, v40
	s_xor_b32 s15, exec_lo, s15
	s_cbranch_execz .LBB3_30
; %bb.23:                               ; %.preheader700.preheader
	v_add_nc_u32_e32 v12, v34, v39
	s_mul_i32 s3, s19, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b32 s3, s3, 6
	v_mul_lo_u32 v12, s16, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v12, v12, s16, v33
.LBB3_24:                               ; %.preheader700
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_max_i32_e32 v13, 0, v12
	v_add_nc_u32_e32 v12, s3, v12
	s_add_i32 s5, s4, 16
	s_add_i32 s4, s4, 4
	s_cmpk_eq_i32 s4, 0x4c
	v_cmp_gt_i32_e32 vcc_lo, s7, v13
	v_cndmask_b32_e32 v16, s17, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
	global_load_b32 v13, v[16:17], off
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v13, s5
	s_cbranch_scc0 .LBB3_24
; %bb.25:
	s_clause 0x4
	scratch_load_b128 v[43:46], off, off offset:16
	scratch_load_b128 v[24:27], off, off offset:32
	scratch_load_b128 v[20:23], off, off offset:48
	scratch_load_b128 v[16:19], off, off offset:64
	scratch_load_b96 v[28:30], off, off offset:80
	v_mov_b32_e32 v12, 0x3c03126f
	v_mov_b32_e32 v13, 0xbc03126f
	s_mov_b32 s3, 0
	s_mov_b32 s18, 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v31, v43, v44
	s_waitcnt vmcnt(3)
	v_mul_f32_e32 v48, 4.0, v24
	s_waitcnt vmcnt(1)
	v_dual_mul_f32 v32, 0xc1300000, v44 :: v_dual_sub_f32 v53, v23, v17
	v_dual_mul_f32 v47, -4.0, v44 :: v_dual_sub_f32 v52, v25, v26
	v_fma_f32 v49, -4.0, v21, v22
	v_fma_f32 v44, v44, 2.0, -v45
	v_dual_add_f32 v50, v24, v24 :: v_dual_add_f32 v57, v31, v45
	v_dual_add_f32 v51, v45, v24 :: v_dual_sub_f32 v56, v22, v23
	v_dual_sub_f32 v54, v22, v16 :: v_dual_fmamk_f32 v31, v43, 0xc1f00000, v32
	v_sub_f32_e64 v55, -v26, v25
	v_dual_fmamk_f32 v32, v43, 0x41400000, v47 :: v_dual_add_f32 v49, v49, v23
	v_fma_f32 v43, 4.0, v46, v47
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v48, -4.0, v45 :: v_dual_sub_f32 v53, v53, v28
	v_dual_fmac_f32 v44, 2.0, v46 :: v_dual_fmac_f32 v47, 2.0, v45
	v_dual_add_f32 v51, v51, v25 :: v_dual_add_f32 v58, v52, v27
	v_fma_f32 v50, v45, -2.0, -v50
	v_dual_sub_f32 v54, v54, v19 :: v_dual_add_f32 v57, v57, v46
	v_dual_sub_f32 v52, v52, v27 :: v_dual_fmac_f32 v31, 0xc1300000, v45
	v_dual_add_f32 v55, v55, v27 :: v_dual_add_f32 v56, v56, v16
	v_dual_fmac_f32 v32, -4.0, v45 :: v_dual_add_f32 v45, v25, v48
	v_dual_add_f32 v43, v43, v25 :: v_dual_add_f32 v48, v49, v16
	v_dual_sub_f32 v44, v44, v24 :: v_dual_fmac_f32 v47, -4.0, v46
	v_dual_add_f32 v49, v51, v26 :: v_dual_add_f32 v54, v54, v29
	v_dual_add_f32 v50, v25, v50 :: v_dual_sub_f32 v51, v58, v20
	v_dual_add_f32 v53, v53, v30 :: v_dual_add_f32 v52, v52, v20
	v_dual_add_f32 v55, v55, v20 :: v_dual_sub_f32 v56, v56, v17
	v_dual_add_f32 v57, v57, v24 :: v_dual_fmac_f32 v32, -4.0, v46
	v_dual_fmac_f32 v31, 0xc1300000, v46 :: v_dual_add_f32 v46, v48, v17
	v_dual_sub_f32 v43, v43, v26 :: v_dual_add_f32 v44, v25, v44
	v_dual_add_f32 v45, v26, v45 :: v_dual_add_f32 v48, v49, v27
	v_fmac_f32_e32 v47, 2.0, v24
	v_add_f32_e32 v49, v26, v50
	v_sub_f32_e32 v50, v52, v22
	v_add_f32_e32 v52, v55, v23
	v_dual_sub_f32 v55, v56, v19 :: v_dual_add_f32 v56, v57, v25
	v_dual_mul_f32 v53, 0x3e800000, v53 :: v_dual_fmac_f32 v32, -4.0, v24
	v_dual_fmac_f32 v31, 0xc1300000, v24 :: v_dual_sub_f32 v24, v43, v27
	v_dual_sub_f32 v43, v45, v27 :: v_dual_fmac_f32 v46, 4.0, v18
	v_dual_add_f32 v44, v26, v44 :: v_dual_add_f32 v45, v25, v47
	v_dual_add_f32 v47, v48, v20 :: v_dual_add_f32 v48, v27, v49
	v_dual_add_f32 v49, v50, v16 :: v_dual_sub_f32 v50, v52, v17
	v_dual_add_f32 v52, v55, v28 :: v_dual_add_f32 v55, v56, v26
	v_dual_fmac_f32 v31, 0x41000000, v25 :: v_dual_add_f32 v24, v24, v20
	v_add_f32_e32 v25, v25, v32
	v_dual_sub_f32 v32, v43, v20 :: v_dual_sub_f32 v43, v46, v19
	v_dual_add_f32 v44, v27, v44 :: v_dual_add_f32 v45, v26, v45
	v_dual_sub_f32 v46, v47, v21 :: v_dual_add_f32 v47, v20, v48
	v_dual_sub_f32 v48, v49, v19 :: v_dual_add_f32 v49, v50, v28
	v_sub_f32_e32 v50, v52, v29
	v_dual_add_f32 v52, v55, v27 :: v_dual_fmac_f32 v31, 0x41000000, v26
	v_dual_add_f32 v25, v26, v25 :: v_dual_add_f32 v24, v24, v22
	v_add_f32_e32 v26, v32, v23
	v_dual_sub_f32 v32, v43, v28 :: v_dual_fmac_f32 v47, 2.0, v21
	v_dual_add_f32 v43, v20, v44 :: v_dual_add_f32 v44, v27, v45
	v_dual_sub_f32 v45, v46, v22 :: v_dual_add_f32 v46, v48, v29
	v_dual_sub_f32 v48, v49, v30 :: v_dual_fmac_f32 v31, 0x41000000, v27
	v_dual_add_f32 v49, v50, v30 :: v_dual_add_f32 v50, v52, v20
	v_dual_add_f32 v25, v27, v25 :: v_dual_sub_f32 v24, v24, v16
	v_sub_f32_e32 v26, v26, v17
	v_sub_f32_e32 v27, v32, v29
	v_dual_sub_f32 v32, v43, v21 :: v_dual_add_f32 v43, v20, v44
	v_dual_sub_f32 v44, v45, v16 :: v_dual_sub_f32 v45, v47, v22
	v_sub_f32_e32 v47, v46, v48
	v_sub_f32_e64 v52, -v46, v48
	v_dual_sub_f32 v55, v48, v46 :: v_dual_add_f32 v56, v46, v48
	v_dual_sub_f32 v57, v49, v46 :: v_dual_sub_f32 v58, v48, v49
	v_add_f32_e32 v59, v46, v49
	v_sub_f32_e64 v60, -v48, v49
	v_sub_f32_e64 v61, -v46, v49
	v_dual_add_f32 v62, v48, v49 :: v_dual_fmac_f32 v31, 0x41000000, v20
	v_dual_sub_f32 v63, v46, v49 :: v_dual_add_f32 v24, v24, v19
	v_sub_f32_e32 v46, v49, v48
	v_dual_add_f32 v48, v50, v21 :: v_dual_sub_f32 v49, v27, v30
	v_dual_add_f32 v20, v20, v25 :: v_dual_add_f32 v25, v26, v28
	v_dual_add_f32 v26, v22, v32 :: v_dual_fmac_f32 v43, 2.0, v21
	v_dual_sub_f32 v27, v44, v18 :: v_dual_sub_f32 v32, v45, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v44, v48, v22 :: v_dual_fmac_f32 v31, 0xc1300000, v21
	v_dual_fmac_f32 v20, -4.0, v21 :: v_dual_add_f32 v21, v22, v43
	v_dual_sub_f32 v45, v24, v29 :: v_dual_sub_f32 v48, v25, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v26, -2.0, v23 :: v_dual_fmac_f32 v31, 0x41000000, v22
	v_dual_sub_f32 v24, v27, v19 :: v_dual_sub_f32 v65, v45, v49
	v_dual_fmac_f32 v32, 2.0, v18 :: v_dual_add_f32 v25, v44, v23
	v_dual_add_f32 v20, v22, v20 :: v_dual_fmac_f32 v21, -2.0, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v22, v16, v26
	v_dual_sub_f32 v24, v24, v29 :: v_dual_fmac_f32 v31, 0x41000000, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v25, v25, v16
	v_add_f32_e32 v20, v23, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v26, v32, v19 :: v_dual_mul_f32 v23, 0x3daaaaab, v24
	v_dual_add_f32 v32, v45, v48 :: v_dual_add_f32 v21, v16, v21
	v_dual_add_f32 v50, v45, v49 :: v_dual_fmac_f32 v31, 0x41000000, v16
	v_dual_add_f32 v25, v25, v17 :: v_dual_add_f32 v16, v16, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v21, -2.0, v17 :: v_dual_sub_f32 v44, v45, v48
	v_sub_f32_e32 v67, v26, v29
	v_dual_fmac_f32 v31, 0x41000000, v17 :: v_dual_add_f32 v16, v17, v16
	v_fmac_f32_e32 v22, -2.0, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v64, v48, v49 :: v_dual_fmac_f32 v21, 2.0, v18
	v_fmac_f32_e32 v31, 0xc1300000, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v20, v22, v18
	v_dual_sub_f32 v66, v48, v49 :: v_dual_fmac_f32 v31, 0x41000000, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, v19, v20
	v_fmac_f32_e32 v31, 0x41000000, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v17, -2.0, v28 :: v_dual_sub_f32 v22, v24, v67
	v_dual_add_f32 v24, v25, v18 :: v_dual_fmac_f32 v31, 0x41000000, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v17, v29, v17 :: v_dual_add_f32 v20, v24, v19
	v_fmac_f32_e32 v31, 0x41000000, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v17, -2.0, v30 :: v_dual_add_f32 v20, v20, v28
	v_fmac_f32_e32 v16, -4.0, v18
	v_add_f32_e32 v18, v19, v21
	v_fma_f32 v68, 0x3ce38e39, v17, -v23
	v_fmamk_f32 v69, v17, 0xbd638e39, v53
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v71, 0x3b5b0037, v31 :: v_dual_add_f32 v16, v19, v16
	v_dual_fmac_f32 v18, -2.0, v28 :: v_dual_add_f32 v19, v20, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v28, v16
	v_fma_f32 v28, 0xbd638e39, v17, -v53
	v_add_f32_e32 v19, v19, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v20, v29, v18
	v_add_f32_e32 v16, v29, v16
	v_fmamk_f32 v29, v17, 0x3ce38e39, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v13, 0x3d579436, v19 :: v_dual_fmac_f32 v20, -2.0, v30
	v_fma_f32 v53, 0x3d579436, v19, 0
	v_fmamk_f32 v70, v51, 0x3e800000, v29
	v_fmac_f32_e32 v29, 0xbe800000, v51
	v_fmamk_f32 v51, v54, 0x3e800000, v68
	v_dual_mul_f32 v18, 0x3d579436, v19 :: v_dual_sub_f32 v17, v17, v20
	v_dual_add_f32 v16, v30, v16 :: v_dual_fmamk_f32 v43, v31, 0xbb969026, v13
	v_fmac_f32_e32 v13, 0x3b5b0037, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmamk_f32 v23, v31, 0xbc4d5033, v18
	v_add_f32_e32 v72, 0xbc03126f, v53
	v_dual_fmamk_f32 v21, v31, 0xbb969026, v53 :: v_dual_fmac_f32 v18, 0xbb969026, v31
	v_fmac_f32_e32 v13, 0x3b820821, v16
	v_fmac_f32_e32 v43, 0xbc820821, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v72, 0x3b5b0037, v31
	v_fmac_f32_e32 v21, 0xbc820821, v16
	v_fmac_f32_e32 v18, 0xbc820821, v16
	v_fmamk_f32 v30, v66, 0xbccccccd, v13
	v_fmac_f32_e32 v43, 0x3dcccccd, v48
	v_fmac_f32_e32 v72, 0x3b820821, v16
	v_fmamk_f32 v24, v16, 0x3d430c31, v23
	v_fmamk_f32 v27, v45, 0x3dcccccd, v18
	v_fmac_f32_e32 v18, 0x3dcccccd, v49
	v_fmac_f32_e32 v30, 0x3e000000, v60
	v_fmac_f32_e32 v43, 0xbce38e39, v17
	v_fmac_f32_e32 v72, 0x3ccccccd, v44
	v_fmac_f32_e32 v27, 0x3d638e39, v17
	v_fmac_f32_e32 v18, 0xbce38e39, v17
	v_fmac_f32_e32 v30, 0xbce38e39, v20
	v_fmac_f32_e32 v12, 0x3d579436, v19
	v_fmac_f32_e32 v72, 0x3c638e39, v20
	v_fmac_f32_e32 v43, 0x3daaaaab, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmamk_f32 v26, v31, 0xbb969026, v12
	v_fmac_f32_e32 v72, 0x3d2aaaab, v67
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v26, 0xbc820821, v16
	v_fmamk_f32 v25, v45, 0xbdcccccd, v21
	v_fmac_f32_e32 v21, 0xbdcccccd, v49
	v_fmac_f32_e32 v72, 0x3e000000, v56
	v_fmac_f32_e32 v71, 0x3d579436, v19
	v_fmac_f32_e32 v26, 0xbdcccccd, v48
	v_fmac_f32_e32 v25, 0x3d638e39, v17
	v_fmac_f32_e32 v21, 0xbce38e39, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v71, 0x3b820821, v16
	v_dual_fmac_f32 v26, 0xbce38e39, v17 :: v_dual_add_f32 v17, v28, v30
	v_fmac_f32_e32 v12, 0x3b5b0037, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v71, 0xbccccccd, v50
	v_fmac_f32_e32 v12, 0x3b820821, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v71, 0x3c638e39, v20
	v_fmamk_f32 v23, v64, 0x3ccccccd, v12
	v_fmamk_f32 v19, v44, 0xbccccccd, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v71, 0xbd2aaaab, v67
	v_fmac_f32_e32 v12, 0x3ccccccd, v66
	v_fmac_f32_e32 v23, 0x3e000000, v58
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v19, 0x3c638e39, v20
	v_fmac_f32_e32 v71, 0x3e000000, v63
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v23, 0xbce38e39, v20
	v_fmac_f32_e32 v68, 0xbe800000, v54
	v_add_f32_e32 v54, 0x3c03126f, v53
	v_fmac_f32_e32 v19, 0x3d2aaaab, v67
	v_dual_fmac_f32 v12, 0x3e000000, v62 :: v_dual_add_f32 v23, v69, v23
	v_fmac_f32_e32 v53, 0x3b5b0037, v31
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v54, 0x3b5b0037, v31
	v_fmamk_f32 v31, v32, 0xbccccccd, v13
	v_fmac_f32_e32 v13, 0xbccccccd, v64
	v_fmac_f32_e32 v19, 0x3e000000, v52
	v_fmac_f32_e32 v53, 0x3b820821, v16
	v_fmac_f32_e32 v54, 0x3b820821, v16
	v_fmac_f32_e32 v31, 0x3c638e39, v20
	v_fmac_f32_e32 v13, 0x3e000000, v46
	v_fmac_f32_e32 v12, 0xbce38e39, v20
	v_fmamk_f32 v48, v50, 0x3ccccccd, v53
	v_fmamk_f32 v73, v65, 0xbccccccd, v53
	v_dual_fmac_f32 v53, 0x3ccccccd, v65 :: v_dual_fmac_f32 v54, 0x3ccccccd, v32
	v_fmac_f32_e32 v31, 0x3d2aaaab, v67
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v48, 0x3c638e39, v20
	v_fmac_f32_e32 v73, 0x3c638e39, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v53, 0x3c638e39, v20
	v_fmac_f32_e32 v54, 0x3c638e39, v20
	v_fmac_f32_e32 v13, 0xbce38e39, v20
	v_fmac_f32_e32 v48, 0xbd2aaaab, v67
	v_fmac_f32_e32 v73, 0xbd2aaaab, v67
	v_fmac_f32_e32 v53, 0xbd2aaaab, v67
	v_fmac_f32_e32 v54, 0x3d2aaaab, v67
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v31, 0x3e000000, v55 :: v_dual_fmac_f32 v48, 0x3e000000, v57
	v_fmac_f32_e32 v73, 0x3e000000, v59
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmac_f32 v53, 0x3e000000, v61 :: v_dual_fmac_f32 v54, 0x3e000000, v47
	v_fmac_f32_e32 v26, 0x3daaaaab, v22
	v_fmac_f32_e32 v21, 0xbdaaaaab, v22
	v_fmac_f32_e32 v18, 0xbdaaaaab, v22
	v_add_f32_e32 v28, v28, v12
	v_add_f32_e32 v30, v69, v13
	v_dual_add_f32 v45, v29, v19 :: v_dual_add_f32 v22, v51, v48
	v_add_f32_e32 v16, v68, v73
	v_dual_add_f32 v20, v29, v72 :: v_dual_add_f32 v19, v68, v53
	v_add_f32_e32 v29, v51, v71
	v_add_f32_e32 v46, v70, v31
	v_add_f32_e32 v44, v70, v54
	s_clause 0x4
	scratch_store_b128 off, v[24:27], off offset:16
	scratch_store_b128 off, v[43:46], off offset:32
	scratch_store_b128 off, v[20:23], off offset:48
	scratch_store_b128 off, v[16:19], off offset:64
	scratch_store_b96 off, v[28:30], off offset:80
	v_cmpx_lt_i32_e32 25, v40
	s_xor_b32 s5, exec_lo, s5
; %bb.26:                               ; %LeafBlock846
	v_cmp_eq_u32_e32 vcc_lo, 26, v40
	s_mov_b32 s4, exec_lo
	s_and_b32 s18, vcc_lo, exec_lo
; %bb.27:                               ; %Flow877
	s_and_not1_saveexec_b32 s5, s5
; %bb.28:                               ; %LeafBlock844
	v_cmp_eq_u32_e32 vcc_lo, 25, v40
	s_or_b32 s4, s4, exec_lo
	s_and_b32 s3, vcc_lo, exec_lo
; %bb.29:                               ; %Flow878
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s4, exec_lo
	s_and_b32 s4, s3, exec_lo
	s_and_b32 s3, s18, exec_lo
.LBB3_30:                               ; %Flow876
	s_and_not1_saveexec_b32 s15, s15
	s_cbranch_execz .LBB3_36
; %bb.31:                               ; %LeafBlock836
	s_mov_b32 s18, -1
	s_mov_b32 s21, s5
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr29
	v_cmpx_eq_u32_e32 0x64, v40
	s_cbranch_execz .LBB3_35
; %bb.32:                               ; %.preheader.preheader
	v_add3_u32 v16, v34, v39, -1
	s_mul_i32 s18, s19, s16
	s_mov_b32 s21, 0
	s_lshl_b32 s18, s18, 6
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v16, s16, v[33:34]
.LBB3_33:                               ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_max_i32_e32 v13, 0, v12
	v_add_nc_u32_e32 v12, s18, v12
	s_add_i32 s22, s21, 16
	s_add_i32 s21, s21, 4
	s_cmpk_eq_i32 s21, 0x4c
	v_cmp_gt_i32_e32 vcc_lo, s7, v13
	v_cndmask_b32_e32 v16, s17, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s10, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
	global_load_b32 v13, v[16:17], off
	s_waitcnt vmcnt(0)
	scratch_store_b32 off, v13, s22
	s_cbranch_scc0 .LBB3_33
; %bb.34:
	s_clause 0x4
	scratch_load_b128 v[43:46], off, off offset:16
	scratch_load_b128 v[26:29], off, off offset:32
	scratch_load_b128 v[17:20], off, off offset:48
	scratch_load_b128 v[22:25], off, off offset:64
	scratch_load_b96 v[30:32], off, off offset:80
	s_mov_b32 s11, 0x3dcccccd
	s_mov_b32 s18, 0xbdcccccd
	s_mov_b32 s10, 0xbc4d5033
	s_or_b32 s21, s5, exec_lo
	s_waitcnt vmcnt(4)
	v_dual_sub_f32 v13, v44, v46 :: v_dual_mul_f32 v12, 0xc1f00000, v43
	s_waitcnt vmcnt(3)
	v_dual_sub_f32 v16, v45, v26 :: v_dual_mul_f32 v47, -4.0, v44
	s_waitcnt vmcnt(1)
	v_dual_add_f32 v21, v19, v18 :: v_dual_sub_f32 v54, v20, v23
	v_dual_mul_f32 v48, 4.0, v26 :: v_dual_sub_f32 v53, v27, v28
	v_fma_f32 v49, -4.0, v18, v19
	v_fma_f32 v50, v44, 2.0, -v45
	v_dual_add_f32 v51, v26, v26 :: v_dual_add_f32 v16, v27, v16
	v_dual_add_f32 v52, v45, v26 :: v_dual_sub_f32 v57, v19, v20
	v_dual_sub_f32 v55, v19, v22 :: v_dual_fmac_f32 v12, 0xc1300000, v44
	v_sub_f32_e64 v56, -v28, v27
	v_dual_add_f32 v13, v13, v27 :: v_dual_fmac_f32 v48, -4.0, v45
	v_dual_add_f32 v21, v20, v21 :: v_dual_fmac_f32 v50, 2.0, v46
	v_dual_fmamk_f32 v43, v43, 0x41400000, v47 :: v_dual_add_f32 v58, v53, v29
	v_fma_f32 v44, 4.0, v46, v47
	v_dual_add_f32 v49, v20, v49 :: v_dual_add_f32 v52, v27, v52
	v_fma_f32 v51, v45, -2.0, -v51
	v_fmac_f32_e32 v12, 0xc1300000, v45
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v47, 2.0, v45 :: v_dual_sub_f32 v54, v54, v30
	v_dual_sub_f32 v55, v55, v25 :: v_dual_add_f32 v60, v28, v16
	v_dual_sub_f32 v53, v53, v29 :: v_dual_add_f32 v44, v27, v44
	v_dual_add_f32 v56, v56, v29 :: v_dual_sub_f32 v59, v13, v28
	v_add_f32_e32 v57, v22, v57
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_add_f32 v21, v22, v21 :: v_dual_add_f32 v16, v55, v31
	v_fmac_f32_e32 v43, -4.0, v45
	v_dual_add_f32 v45, v27, v48 :: v_dual_add_f32 v48, v22, v49
	v_fmac_f32_e32 v47, -4.0, v46
	v_dual_sub_f32 v49, v50, v26 :: v_dual_add_f32 v50, v28, v52
	v_dual_add_f32 v51, v27, v51 :: v_dual_fmac_f32 v12, 0xc1300000, v46
	v_dual_sub_f32 v13, v58, v17 :: v_dual_sub_f32 v44, v44, v28
	v_dual_add_f32 v52, v54, v32 :: v_dual_add_f32 v53, v53, v17
	v_dual_add_f32 v54, v56, v17 :: v_dual_sub_f32 v55, v57, v23
	v_sub_f32_e32 v56, v59, v29
	v_add_f32_e32 v21, v23, v21
	v_fmac_f32_e32 v43, -4.0, v46
	v_dual_add_f32 v45, v28, v45 :: v_dual_fmac_f32 v12, 0xc1300000, v26
	v_add_f32_e32 v46, v23, v48
	v_dual_add_f32 v48, v27, v49 :: v_dual_add_f32 v49, v29, v50
	v_add_f32_e32 v50, v28, v51
	v_dual_sub_f32 v57, v60, v29 :: v_dual_mul_f32 v52, 0x3e800000, v52
	v_fmac_f32_e32 v47, 2.0, v26
	v_dual_sub_f32 v51, v53, v19 :: v_dual_fmac_f32 v46, 4.0, v24
	v_dual_add_f32 v53, v54, v20 :: v_dual_sub_f32 v54, v55, v25
	v_dual_fmac_f32 v43, -4.0, v26 :: v_dual_sub_f32 v26, v44, v29
	v_dual_sub_f32 v44, v45, v29 :: v_dual_add_f32 v45, v28, v48
	v_add_f32_e32 v48, v17, v49
	v_dual_add_f32 v49, v29, v50 :: v_dual_fmac_f32 v12, 0x41000000, v27
	v_dual_add_f32 v55, v56, v17 :: v_dual_add_f32 v50, v51, v22
	v_sub_f32_e32 v56, v57, v17
	v_sub_f32_e32 v21, v21, v24
	v_dual_add_f32 v47, v27, v47 :: v_dual_add_f32 v26, v17, v26
	v_sub_f32_e32 v51, v53, v23
	v_add_f32_e32 v53, v30, v54
	v_dual_add_f32 v27, v27, v43 :: v_dual_fmac_f32 v12, 0x41000000, v28
	v_dual_add_f32 v54, v55, v19 :: v_dual_add_f32 v55, v20, v56
	v_sub_f32_e32 v43, v44, v17
	v_sub_f32_e32 v44, v46, v25
	v_sub_f32_e32 v21, v21, v25
	v_dual_add_f32 v45, v29, v45 :: v_dual_add_f32 v26, v19, v26
	v_add_f32_e32 v46, v28, v47
	v_dual_sub_f32 v47, v48, v18 :: v_dual_add_f32 v48, v17, v49
	v_dual_sub_f32 v49, v50, v25 :: v_dual_add_f32 v50, v51, v30
	v_sub_f32_e32 v51, v53, v31
	v_dual_add_f32 v27, v28, v27 :: v_dual_fmac_f32 v12, 0x41000000, v29
	v_dual_sub_f32 v53, v54, v22 :: v_dual_sub_f32 v54, v55, v23
	v_add_f32_e32 v28, v20, v43
	v_dual_sub_f32 v43, v44, v30 :: v_dual_add_f32 v44, v17, v45
	v_dual_add_f32 v45, v29, v46 :: v_dual_sub_f32 v46, v47, v19
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v28, v28, v23
	v_fmac_f32_e32 v48, 2.0, v18
	v_sub_f32_e32 v21, v21, v30
	v_dual_add_f32 v47, v49, v31 :: v_dual_sub_f32 v26, v26, v22
	v_dual_sub_f32 v49, v50, v32 :: v_dual_add_f32 v50, v32, v51
	v_dual_add_f32 v27, v29, v27 :: v_dual_fmac_f32 v12, 0x41000000, v17
	v_add_f32_e32 v51, v53, v25
	v_add_f32_e32 v53, v30, v54
	v_sub_f32_e32 v29, v43, v31
	v_dual_sub_f32 v43, v44, v18 :: v_dual_add_f32 v44, v17, v45
	v_dual_sub_f32 v45, v46, v22 :: v_dual_sub_f32 v46, v48, v19
	v_dual_sub_f32 v21, v21, v31 :: v_dual_add_f32 v56, v47, v49
	v_sub_f32_e32 v48, v47, v49
	v_sub_f32_e64 v54, -v47, v49
	v_dual_sub_f32 v55, v49, v47 :: v_dual_fmac_f32 v44, 2.0, v18
	v_dual_sub_f32 v57, v50, v47 :: v_dual_add_f32 v62, v49, v50
	v_sub_f32_e32 v58, v49, v50
	v_sub_f32_e64 v60, -v49, v50
	v_dual_sub_f32 v49, v50, v49 :: v_dual_fmac_f32 v12, 0xc1300000, v18
	v_add_f32_e32 v59, v47, v50
	v_sub_f32_e64 v61, -v47, v50
	v_sub_f32_e32 v47, v47, v50
	v_dual_sub_f32 v50, v51, v31 :: v_dual_sub_f32 v51, v53, v32
	v_dual_sub_f32 v53, v21, v32 :: v_dual_fmac_f32 v12, 0x41000000, v19
	v_add_f32_e32 v17, v17, v27
	v_dual_add_f32 v21, v25, v26 :: v_dual_add_f32 v26, v30, v28
	v_add_f32_e32 v27, v19, v43
	v_fmaak_f32 v63, s11, v50, 0x3d579436
	v_sub_f32_e32 v43, v46, v22
	v_fmaak_f32 v50, s18, v50, 0x3d579436
	v_sub_f32_e32 v46, v26, v32
	v_add_f32_e32 v26, v19, v44
	v_dual_fmaak_f32 v64, s11, v51, 0x3d579436 :: v_dual_fmac_f32 v17, -4.0, v18
	v_sub_f32_e32 v28, v29, v32
	v_dual_sub_f32 v29, v45, v24 :: v_dual_fmamk_f32 v44, v51, 0x3dcccccd, v63
	v_dual_fmaak_f32 v18, s18, v53, 0x3d579436 :: v_dual_sub_f32 v45, v21, v31
	v_fmac_f32_e32 v12, 0x41000000, v20
	v_fmac_f32_e32 v26, -2.0, v20
	v_dual_fmac_f32 v27, -2.0, v20 :: v_dual_fmamk_f32 v72, v53, 0x3dcccccd, v64
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_add_f32 v66, v45, v46 :: v_dual_add_f32 v17, v19, v17
	v_fmamk_f32 v74, v53, 0x3dcccccd, v50
	v_sub_f32_e32 v29, v29, v25
	v_dual_add_f32 v19, v22, v27 :: v_dual_fmac_f32 v12, 0x41000000, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_add_f32 v17, v20, v17 :: v_dual_add_f32 v20, v22, v26
	v_add_f32_e32 v71, v45, v28
	v_sub_f32_e32 v68, v45, v46
	v_fmac_f32_e32 v12, 0x41000000, v23
	v_sub_f32_e32 v27, v29, v31
	v_fmac_f32_e32 v20, -2.0, v23
	v_fmaak_f32 v65, s18, v51, 0x3d579436
	v_fmamk_f32 v70, v53, 0x3dcccccd, v63
	v_fmac_f32_e32 v12, 0xc1300000, v24
	v_fmac_f32_e32 v43, 2.0, v24
	v_dual_fmac_f32 v20, 2.0, v24 :: v_dual_fmaak_f32 v21, s11, v53, 0x3d579436
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v73, v46, v28 :: v_dual_fmac_f32 v12, 0x41000000, v25
	v_dual_fmac_f32 v19, -2.0, v23 :: v_dual_add_f32 v20, v25, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v29, v43, v25
	v_dual_sub_f32 v75, v45, v28 :: v_dual_fmac_f32 v12, 0x41000000, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v19, v19, v24 :: v_dual_fmac_f32 v20, -2.0, v30
	v_dual_add_f32 v17, v22, v17 :: v_dual_fmamk_f32 v22, v53, 0x3dcccccd, v65
	v_sub_f32_e32 v29, v29, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v12, 0x41000000, v31
	v_dual_add_f32 v19, v25, v19 :: v_dual_add_f32 v20, v31, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, v23, v17
	s_xor_b32 s18, exec_lo, -1
	v_dual_fmac_f32 v12, 0x41000000, v32 :: v_dual_fmac_f32 v19, -2.0, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, -2.0, v32
	v_dual_fmac_f32 v17, -4.0, v24 :: v_dual_mul_f32 v24, 0x3daaaaab, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmamk_f32 v26, v12, 0xbb969026, v64 :: v_dual_add_f32 v19, v31, v19
	v_dual_fmac_f32 v44, 0x3b5b0037, v12 :: v_dual_add_f32 v17, v25, v17
	v_fmac_f32_e32 v70, 0x3b5b0037, v12
	v_fmac_f32_e32 v72, 0x3b5b0037, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v19, -2.0, v32
	v_dual_fmac_f32 v74, 0x3b5b0037, v12 :: v_dual_add_f32 v17, v30, v17
	v_fmamk_f32 v43, v12, 0xbb969026, v65
	v_fmac_f32_e32 v64, 0xbdcccccd, v53
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v76, 0x3ce38e39, v19, -v24
	v_fmac_f32_e32 v65, 0xbdcccccd, v53
	v_add_f32_e32 v17, v31, v17
	v_fmamk_f32 v31, v19, 0x3ce38e39, v24
	v_sub_f32_e32 v23, v46, v28
	v_fmac_f32_e32 v64, 0x3b5b0037, v12
	v_fmac_f32_e32 v65, 0x3b5b0037, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_add_f32 v17, v32, v17 :: v_dual_fmamk_f32 v32, v13, 0x3e800000, v31
	v_fmac_f32_e32 v31, 0xbe800000, v13
	v_fmamk_f32 v13, v16, 0x3e800000, v76
	v_fmac_f32_e32 v76, 0xbe800000, v16
	v_fmac_f32_e32 v44, 0x3b820821, v17
	v_fmac_f32_e32 v70, 0x3b820821, v17
	v_fmac_f32_e32 v64, 0x3b820821, v17
	v_fmac_f32_e32 v65, 0x3b820821, v17
	v_sub_f32_e32 v30, v27, v29
	v_fmac_f32_e32 v44, 0x3ccccccd, v66
	v_fmac_f32_e32 v70, 0x3ccccccd, v71
	v_fmac_f32_e32 v64, 0x3ccccccd, v23
	v_fmac_f32_e32 v65, 0xbccccccd, v73
	v_fmac_f32_e32 v74, 0x3b820821, v17
	v_fmac_f32_e32 v44, 0x3c638e39, v20
	v_fmac_f32_e32 v70, 0x3c638e39, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v64, 0x3e000000, v62 :: v_dual_fmac_f32 v65, 0x3e000000, v49
	v_fmac_f32_e32 v74, 0xbccccccd, v75
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v44, 0x3d2aaaab, v29
	v_fmac_f32_e32 v70, 0xbd2aaaab, v29
	v_dual_fmamk_f32 v25, v12, 0xbb969026, v63 :: v_dual_fmac_f32 v18, 0xbb969026, v12
	v_fmac_f32_e32 v65, 0xbce38e39, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v44, 0x3e000000, v48
	v_fmamk_f32 v67, v51, 0x3dcccccd, v50
	v_fmac_f32_e32 v70, 0x3e000000, v57
	v_fmamk_f32 v69, v51, 0xbdcccccd, v50
	v_fmamk_f32 v51, v51, 0xbdcccccd, v63
	v_fmamk_f32 v27, v12, 0xbb969026, v50
	v_fmac_f32_e32 v50, 0xbdcccccd, v53
	v_add_f32_e32 v44, v32, v44
	v_fmac_f32_e32 v67, 0x3b5b0037, v12
	v_fmac_f32_e32 v51, 0x3b5b0037, v12
	v_fmac_f32_e32 v74, 0x3c638e39, v20
	v_fmac_f32_e32 v50, 0x3b5b0037, v12
	v_fmac_f32_e32 v43, 0xbc820821, v17
	v_fmac_f32_e32 v67, 0x3b820821, v17
	v_fmac_f32_e32 v51, 0x3b820821, v17
	v_fmac_f32_e32 v74, 0xbd2aaaab, v29
	v_fmac_f32_e32 v50, 0x3b820821, v17
	v_fmaak_f32 v16, s10, v12, 0x3d579436
	v_fmac_f32_e32 v67, 0xbccccccd, v68
	v_fmac_f32_e32 v51, 0x3ccccccd, v68
	v_fmac_f32_e32 v21, 0xbb969026, v12
	v_fmac_f32_e32 v50, 0xbccccccd, v71
	v_fmac_f32_e32 v18, 0xbc820821, v17
	v_fmac_f32_e32 v43, 0x3dcccccd, v46
	v_fmac_f32_e32 v51, 0x3c638e39, v20
	v_fmac_f32_e32 v74, 0x3e000000, v59
	v_fmac_f32_e32 v50, 0x3c638e39, v20
	v_fmac_f32_e32 v18, 0x3dcccccd, v28
	v_fmamk_f32 v77, v19, 0xbd638e39, v52
	v_fmac_f32_e32 v51, 0x3d2aaaab, v29
	v_fma_f32 v52, 0xbd638e39, v19, -v52
	v_dual_fmac_f32 v50, 0xbd2aaaab, v29 :: v_dual_sub_f32 v19, v19, v20
	v_fmamk_f32 v24, v17, 0x3d430c31, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v51, 0x3e000000, v56
	v_fmac_f32_e32 v21, 0xbc820821, v17
	v_fmac_f32_e32 v50, 0x3e000000, v47
	v_fmac_f32_e32 v72, 0x3b820821, v17
	v_dual_add_f32 v16, v76, v74 :: v_dual_fmac_f32 v67, 0x3c638e39, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v21, 0xbdcccccd, v28
	v_fmac_f32_e32 v18, 0xbce38e39, v19
	v_fmac_f32_e32 v72, 0x3ccccccd, v73
	v_fmac_f32_e32 v64, 0xbce38e39, v20
	v_fmac_f32_e32 v67, 0x3d2aaaab, v29
	v_fmac_f32_e32 v21, 0xbce38e39, v19
	v_fmac_f32_e32 v69, 0x3b5b0037, v12
	v_fmac_f32_e32 v72, 0x3e000000, v58
	v_fmac_f32_e32 v43, 0xbce38e39, v19
	v_fmac_f32_e32 v25, 0xbc820821, v17
	v_fmac_f32_e32 v21, 0xbdaaaaab, v30
	v_fmac_f32_e32 v18, 0xbdaaaaab, v30
	v_fmac_f32_e32 v72, 0xbce38e39, v20
	v_fmac_f32_e32 v26, 0xbc820821, v17
	v_fmac_f32_e32 v63, 0xbdcccccd, v53
	v_fmac_f32_e32 v43, 0x3daaaaab, v30
	v_dual_fmac_f32 v67, 0x3e000000, v54 :: v_dual_add_f32 v28, v52, v64
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v26, 0xbdcccccd, v46
	v_fmac_f32_e32 v63, 0x3b5b0037, v12
	v_fmac_f32_e32 v22, 0x3b5b0037, v12
	v_fmac_f32_e32 v69, 0x3b820821, v17
	v_fmac_f32_e32 v25, 0xbdcccccd, v45
	v_fmac_f32_e32 v26, 0xbce38e39, v19
	v_fmac_f32_e32 v63, 0x3b820821, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v25, 0x3d638e39, v19
	v_fmac_f32_e32 v26, 0x3daaaaab, v30
	v_add_f32_e32 v30, v77, v65
	v_fmac_f32_e32 v27, 0xbc820821, v17
	v_fmac_f32_e32 v63, 0x3ccccccd, v75
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v27, 0x3dcccccd, v45
	v_dual_add_f32 v45, v31, v67 :: v_dual_fmac_f32 v22, 0x3b820821, v17
	v_fmac_f32_e32 v69, 0xbccccccd, v66
	v_fmac_f32_e32 v63, 0x3c638e39, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v27, 0x3d638e39, v19
	v_fmac_f32_e32 v22, 0xbccccccd, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v69, 0x3c638e39, v20
	v_fmac_f32_e32 v63, 0xbd2aaaab, v29
	v_add_f32_e32 v23, v77, v72
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v22, 0x3e000000, v60
	v_fmac_f32_e32 v69, 0x3d2aaaab, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v63, 0x3e000000, v61
	v_fmac_f32_e32 v22, 0xbce38e39, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v69, 0x3e000000, v55
	v_add_f32_e32 v20, v31, v51
	v_add_f32_e32 v19, v76, v63
	v_add_f32_e32 v29, v13, v50
	v_add_f32_e32 v17, v52, v22
	v_add_f32_e32 v22, v13, v70
	v_add_f32_e32 v46, v32, v69
	s_clause 0x4
	scratch_store_b128 off, v[24:27], off offset:16
	scratch_store_b128 off, v[43:46], off offset:32
	scratch_store_b128 off, v[20:23], off offset:48
	scratch_store_b96 off, v[16:18], off offset:64
	scratch_store_b32 off, v28, off offset:80
.LBB3_35:                               ; %Flow880
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s10, s21, exec_lo
	s_and_b32 s14, s18, exec_lo
	s_or_b32 s5, s5, s10
.LBB3_36:                               ; %Flow879
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s18, s5, exec_lo
	s_and_b32 s15, s14, exec_lo
	s_and_b32 s14, s4, exec_lo
	s_and_b32 s3, s3, exec_lo
.LBB3_37:                               ; %Flow875
	s_and_not1_saveexec_b32 s2, s2
; %bb.38:                               ; %LeafBlock834
	v_cmp_eq_u32_e32 vcc_lo, 26, v40
	v_dual_mov_b32 v23, v14 :: v_dual_mov_b32 v28, v11
	v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v30, v41
	v_dual_mov_b32 v16, v15 :: v_dual_mov_b32 v29, v4
	v_mov_b32_e32 v18, v9
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_or_b32 s15, s15, exec_lo
	s_or_b32 s3, s3, s4
; %bb.39:                               ; %Flow881
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s10, s3
	s_cbranch_execz .LBB3_65
; %bb.40:
	v_or_b32_e32 v12, v42, v34
	s_mov_b32 s2, 0
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v12
                                        ; implicit-def: $vgpr12
	s_and_saveexec_b32 s3, vcc_lo
	s_xor_b32 s11, exec_lo, s3
	s_cbranch_execz .LBB3_60
; %bb.41:
	v_cmp_ne_u32_e32 vcc_lo, 0, v34
	v_cmp_ne_u32_e64 s2, 7, v42
	v_cmp_eq_u32_e64 s3, 7, v42
	s_mov_b32 s4, 0
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s5, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s21, exec_lo, s5
	s_cbranch_execz .LBB3_57
; %bb.42:
	v_cmp_ne_u32_e64 s4, 0, v42
	v_cmp_ne_u32_e64 s5, 63, v34
	v_cmp_eq_u32_e64 s2, 63, v34
	s_mov_b32 s22, 0
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s5, s4
	s_and_saveexec_b32 s5, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s5
	s_cbranch_execz .LBB3_54
; %bb.43:
	s_and_b32 s3, s2, s3
	s_mov_b32 s5, 0
	s_xor_b32 s3, s3, -1
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s22, s3
	s_xor_b32 s3, exec_lo, s22
	s_cbranch_execz .LBB3_51
; %bb.44:
                                        ; implicit-def: $sgpr22
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr24
                                        ; implicit-def: $sgpr25
                                        ; implicit-def: $sgpr26
                                        ; implicit-def: $sgpr27
                                        ; implicit-def: $sgpr28
	s_and_saveexec_b32 s29, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s29, exec_lo, s29
	s_cbranch_execz .LBB3_48
; %bb.45:
                                        ; implicit-def: $sgpr22
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr24
                                        ; implicit-def: $sgpr25
                                        ; implicit-def: $sgpr26
                                        ; implicit-def: $sgpr27
                                        ; implicit-def: $sgpr28
	s_and_saveexec_b32 s30, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s30
	s_cbranch_execz .LBB3_47
; %bb.46:
	scratch_load_b32 v30, off, off offset:24
	s_mov_b32 s5, exec_lo
	s_mov_b32 s28, 4
	s_mov_b32 s27, 11
	s_mov_b32 s26, 13
	s_mov_b32 s25, 16
	s_mov_b32 s24, 18
	s_mov_b32 s23, 8
	s_mov_b32 s22, 5
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
.LBB3_47:                               ; %Flow854
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s5, exec_lo
.LBB3_48:                               ; %Flow853
	s_or_saveexec_b32 s2, s29
	v_dual_mov_b32 v12, s22 :: v_dual_mov_b32 v13, s23
	v_dual_mov_b32 v19, s24 :: v_dual_mov_b32 v20, s25
	v_dual_mov_b32 v21, s26 :: v_dual_mov_b32 v22, s27
	v_mov_b32_e32 v24, s28
	s_xor_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB3_50
; %bb.49:
	scratch_load_b32 v30, off, off offset:32
	v_dual_mov_b32 v12, 8 :: v_dual_mov_b32 v13, 5
	v_dual_mov_b32 v19, 16 :: v_dual_mov_b32 v20, 18
	v_dual_mov_b32 v21, 11 :: v_dual_mov_b32 v22, 13
	v_mov_b32_e32 v24, 2
	s_or_b32 s5, s5, exec_lo
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
.LBB3_50:                               ; %Flow855
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s5, exec_lo
.LBB3_51:                               ; %Flow852
	s_and_not1_saveexec_b32 s2, s3
	s_cbranch_execz .LBB3_53
; %bb.52:
	scratch_load_b32 v16, off, off offset:24
	v_dual_mov_b32 v12, 17 :: v_dual_mov_b32 v13, 12
	v_dual_mov_b32 v19, 14 :: v_dual_mov_b32 v20, 9
	v_dual_mov_b32 v21, 7 :: v_dual_mov_b32 v22, 6
	v_mov_b32_e32 v24, 13
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v30, v23
	s_or_b32 s5, s5, exec_lo
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v23, off offset:80
	scratch_store_b32 off, v23, off offset:88
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr23
.LBB3_53:                               ; %Flow856
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s22, s5, exec_lo
.LBB3_54:                               ; %Flow851
	s_and_not1_saveexec_b32 s2, s4
	s_cbranch_execz .LBB3_56
; %bb.55:
	scratch_load_b32 v16, off, off offset:24
	v_dual_mov_b32 v12, 12 :: v_dual_mov_b32 v13, 17
	v_dual_mov_b32 v19, 9 :: v_dual_mov_b32 v20, 14
	v_dual_mov_b32 v21, 7 :: v_dual_mov_b32 v22, 6
	v_mov_b32_e32 v24, 13
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v30, v28
	s_or_b32 s22, s22, exec_lo
                                        ; implicit-def: $vgpr23
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v28, off offset:60
	scratch_store_b32 off, v28, off offset:88
                                        ; implicit-def: $vgpr16
.LBB3_56:                               ; %Flow857
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s22, exec_lo
.LBB3_57:                               ; %Flow850
	s_and_not1_saveexec_b32 s2, s21
	s_cbranch_execz .LBB3_59
; %bb.58:
	scratch_load_b32 v16, off, off offset:24
	v_dual_mov_b32 v12, 17 :: v_dual_mov_b32 v13, 12
	v_dual_mov_b32 v19, 14 :: v_dual_mov_b32 v20, 9
	v_dual_mov_b32 v21, 6 :: v_dual_mov_b32 v22, 7
	v_mov_b32_e32 v24, 16
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v30, v17
	s_or_b32 s4, s4, exec_lo
                                        ; implicit-def: $vgpr23
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:32
	scratch_store_b32 off, v17, off offset:60
	scratch_store_b32 off, v17, off offset:88
                                        ; implicit-def: $vgpr16
.LBB3_59:                               ; %Flow858
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s4, exec_lo
.LBB3_60:                               ; %Flow
	s_and_not1_saveexec_b32 s3, s11
	s_cbranch_execz .LBB3_62
; %bb.61:
	scratch_load_b32 v16, off, off offset:32
	v_dual_mov_b32 v12, 12 :: v_dual_mov_b32 v13, 17
	v_dual_mov_b32 v19, 9 :: v_dual_mov_b32 v20, 14
	v_dual_mov_b32 v21, 6 :: v_dual_mov_b32 v22, 7
	v_mov_b32_e32 v24, 16
	s_or_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr23
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v16, off offset:24
	scratch_store_b32 off, v30, off offset:68
	scratch_store_b32 off, v30, off offset:60
                                        ; implicit-def: $vgpr16
.LBB3_62:                               ; %Flow859
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_64
; %bb.63:                               ; %.sink.split.i
	v_lshl_add_u32 v16, v24, 2, 16
	v_lshl_add_u32 v17, v22, 2, 16
	v_lshl_add_u32 v18, v20, 2, 16
	v_lshl_add_u32 v13, v13, 2, 16
	v_lshl_add_u32 v12, v12, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v16, v30, off
	scratch_load_b32 v16, v17, off
	v_lshl_add_u32 v17, v21, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v17, v16, off
	scratch_load_b32 v16, v18, off
	v_lshl_add_u32 v17, v19, 2, 16
	s_waitcnt vmcnt(0)
	scratch_store_b32 v17, v16, off
	scratch_load_b32 v13, v13, off
	s_waitcnt vmcnt(0)
	scratch_store_b32 v12, v13, off
	s_clause 0x1
	scratch_load_b128 v[19:22], off, off offset:60
	scratch_load_b96 v[28:30], off, off offset:80
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v18, v22 :: v_dual_mov_b32 v17, v21
	v_dual_mov_b32 v23, v19 :: v_dual_mov_b32 v16, v20
.LBB3_64:                               ; %_Z13xsymmetry_botPfii.exit
	s_or_b32 exec_lo, exec_lo, s3
	s_clause 0x1
	scratch_load_b32 v20, off, off offset:28
	scratch_load_b64 v[12:13], off, off offset:40
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v22, v16 :: v_dual_mov_b32 v19, v29
	s_or_b32 s18, s18, exec_lo
	s_and_not1_b32 s15, s15, exec_lo
	s_waitcnt vmcnt(1)
	scratch_store_b32 off, v20, off offset:20
	s_waitcnt vmcnt(0)
	s_clause 0x1
	scratch_store_b32 off, v12, off offset:36
	scratch_store_b32 off, v13, off offset:48
.LBB3_65:                               ; %Flow882
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s18, s18, exec_lo
	s_and_b32 s15, s15, exec_lo
	s_and_b32 s2, s14, exec_lo
.LBB3_66:                               ; %Flow874
	s_or_saveexec_b32 s3, s13
	s_mov_b32 s10, 0
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB3_70
; %bb.67:                               ; %NodeBlock832
	s_mov_b32 s4, 0
	s_mov_b32 s10, -1
	s_mov_b32 s5, s2
	s_mov_b32 s11, exec_lo
	v_cmpx_lt_i32_e32 9, v40
; %bb.68:                               ; %NodeBlock830
	v_cmp_lt_i32_e32 vcc_lo, 24, v40
	s_and_not1_b32 s5, s2, exec_lo
	s_mov_b32 s4, exec_lo
	s_xor_b32 s10, exec_lo, -1
	s_and_b32 s12, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s5, s5, s12
; %bb.69:                               ; %Flow884
	s_or_b32 exec_lo, exec_lo, s11
	v_dual_mov_b32 v23, v14 :: v_dual_mov_b32 v28, v11
	v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v30, v41
	v_dual_mov_b32 v18, v9 :: v_dual_mov_b32 v19, v10
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s5, exec_lo
	s_and_b32 s10, s10, exec_lo
	s_and_b32 s12, s4, exec_lo
	s_or_b32 s2, s2, s5
.LBB3_70:                               ; %Flow883
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s11, s2
	s_cbranch_execz .LBB3_96
; %bb.71:
	v_or_b32_e32 v12, v42, v34
                                        ; implicit-def: $vgpr24
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v12
	s_xor_b32 s13, exec_lo, s2
	s_cbranch_execz .LBB3_93
; %bb.72:
	v_cmp_ne_u32_e32 vcc_lo, 0, v34
	v_cmp_ne_u32_e64 s2, 7, v42
	v_cmp_eq_u32_e64 s3, 7, v42
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s4, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s4
	s_cbranch_execz .LBB3_90
; %bb.73:
	v_cmp_ne_u32_e64 s5, 0, v42
	v_cmp_ne_u32_e64 s2, 63, v34
	v_cmp_eq_u32_e64 s4, 63, v34
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s5, s2, s5
	s_and_saveexec_b32 s21, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s21
	s_cbranch_execz .LBB3_87
; %bb.74:
	s_and_b32 s3, s4, s3
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, -1
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s4
	s_cbranch_execz .LBB3_84
; %bb.75:
                                        ; implicit-def: $vgpr24
	s_and_saveexec_b32 s4, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB3_81
; %bb.76:
                                        ; implicit-def: $vgpr24
	s_and_saveexec_b32 s21, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s21
; %bb.77:                               ; %._crit_edge.i
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b32 v25, off, off offset:48
; %bb.78:                               ; %Flow861
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_80
; %bb.79:
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b32 v12, off, off offset:24
	v_dual_mov_b32 v17, v23 :: v_dual_mov_b32 v30, v28
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v12, off offset:32
	scratch_store_b32 off, v28, off offset:88
	scratch_store_b32 off, v23, off offset:68
	scratch_store_b32 off, v24, off offset:48
	v_mov_b32_e32 v25, v24
.LBB3_80:                               ; %Flow862
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_81:                               ; %Flow864
	s_and_not1_saveexec_b32 s2, s4
	s_cbranch_execz .LBB3_83
; %bb.82:
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:48
	scratch_load_b32 v12, off, off offset:32
	v_dual_mov_b32 v23, v17 :: v_dual_mov_b32 v28, v30
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v12, off offset:24
	scratch_store_b32 off, v30, off offset:80
	scratch_store_b32 off, v17, off offset:60
	scratch_store_b32 off, v24, off offset:36
	v_mov_b32_e32 v25, v24
.LBB3_83:                               ; %Flow865
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_84:                               ; %Flow866
	s_and_not1_saveexec_b32 s2, s3
	s_cbranch_execz .LBB3_86
; %bb.85:
	s_clause 0x2
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b64 v[21:22], off, off offset:52
	scratch_load_b32 v12, off, off offset:24
	v_mov_b32_e32 v20, v23
	v_mov_b32_e32 v17, v23
	v_mov_b32_e32 v28, v23
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v30, v23 :: v_dual_mov_b32 v25, v24
	s_waitcnt vmcnt(1)
	v_dual_mov_b32 v19, v22 :: v_dual_mov_b32 v18, v21
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v12, off offset:32
	scratch_store_b32 off, v24, off offset:48
	scratch_store_b32 off, v23, off offset:88
	scratch_store_b128 off, v[20:23], off offset:68
.LBB3_86:                               ; %Flow867
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_87:                               ; %Flow868
	s_and_not1_saveexec_b32 s2, s5
	s_cbranch_execz .LBB3_89
; %bb.88:
	s_clause 0x1
	scratch_load_b32 v24, off, off offset:36
	scratch_load_b32 v12, off, off offset:24
	s_waitcnt vmcnt(2)
	v_dual_mov_b32 v25, v18 :: v_dual_mov_b32 v26, v19
	v_mov_b32_e32 v27, v28
	v_mov_b32_e32 v23, v28
	v_mov_b32_e32 v17, v28
	v_mov_b32_e32 v30, v28
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[24:27], off offset:48
	v_mov_b32_e32 v25, v24
	s_waitcnt vmcnt(0)
	s_clause 0x2
	scratch_store_b32 off, v12, off offset:32
	scratch_store_b32 off, v28, off offset:88
	scratch_store_b32 off, v28, off offset:68
.LBB3_89:                               ; %Flow869
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_90:                               ; %Flow870
	s_and_not1_saveexec_b32 s2, s14
	s_cbranch_execz .LBB3_92
; %bb.91:
	s_clause 0x1
	scratch_load_b32 v12, off, off offset:32
	scratch_load_b96 v[20:22], off, off offset:48
	v_mov_b32_e32 v23, v17
	v_mov_b32_e32 v28, v17
	v_mov_b32_e32 v30, v17
	v_mov_b32_e32 v44, v17
	s_waitcnt vmcnt(1)
	scratch_store_b32 off, v12, off offset:24
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v43, v22 :: v_dual_mov_b32 v42, v21
	v_dual_mov_b32 v19, v22 :: v_dual_mov_b32 v24, v20
	v_dual_mov_b32 v25, v20 :: v_dual_mov_b32 v18, v21
	s_clause 0x3
	scratch_store_b32 off, v17, off offset:88
	scratch_store_b32 off, v20, off offset:36
	scratch_store_b32 off, v17, off offset:60
	scratch_store_b96 off, v[42:44], off offset:72
.LBB3_92:                               ; %Flow871
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_93:                               ; %Flow872
	s_and_not1_saveexec_b32 s2, s13
	s_cbranch_execz .LBB3_95
; %bb.94:
	s_clause 0x1
	scratch_load_b32 v25, off, off offset:48
	scratch_load_b32 v12, off, off offset:32
	v_dual_mov_b32 v28, v18 :: v_dual_mov_b32 v29, v19
	v_mov_b32_e32 v17, v30
	v_mov_b32_e32 v23, v30
	scratch_store_b96 off, v[28:30], off offset:52
	v_mov_b32_e32 v28, v30
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b32 off, v12, off offset:24
	scratch_store_b32 off, v25, off offset:36
	scratch_store_b32 off, v30, off offset:68
	scratch_store_b32 off, v30, off offset:80
	v_mov_b32_e32 v24, v25
.LBB3_95:                               ; %_Z13xsymmetry_topPfii.exit
	s_or_b32 exec_lo, exec_lo, s2
	s_clause 0x1
	scratch_load_b32 v22, off, off offset:56
	scratch_load_b32 v12, off, off offset:20
	s_or_b32 s18, s18, exec_lo
	s_and_not1_b32 s12, s12, exec_lo
	v_mov_b32_e32 v29, v19
	s_waitcnt vmcnt(0)
	s_clause 0x1
	scratch_store_b32 off, v12, off offset:28
	scratch_store_b64 off, v[24:25], off offset:40
	v_mov_b32_e32 v16, v22
.LBB3_96:                               ; %Flow885
	s_or_b32 exec_lo, exec_lo, s11
	s_mov_b32 s3, 0
	s_and_saveexec_b32 s2, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
; %bb.97:                               ; %LeafBlock828
	v_cmp_ne_u32_e32 vcc_lo, 10, v40
	s_and_not1_b32 s4, s15, exec_lo
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr29
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s15, s4, s5
; %bb.98:                               ; %Flow886
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s4, s10
; %bb.99:                               ; %LeafBlock826
	v_cmp_eq_u32_e32 vcc_lo, 1, v40
	v_cmp_ne_u32_e64 s2, 1, v40
	s_and_not1_b32 s3, s3, exec_lo
	s_and_not1_b32 s5, s15, exec_lo
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr29
	s_and_b32 s10, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s3, s3, s10
	s_or_b32 s15, s5, s2
; %bb.100:                              ; %Flow887
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s2, s15
	s_cbranch_execz .LBB3_102
; %bb.101:                              ; %._crit_edge
	scratch_load_b32 v22, off, off offset:56
	v_dual_mov_b32 v16, v15 :: v_dual_mov_b32 v19, v10
	v_dual_mov_b32 v29, v4 :: v_dual_mov_b32 v28, v11
	v_dual_mov_b32 v23, v14 :: v_dual_mov_b32 v30, v41
	v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v18, v9
	s_and_not1_b32 s3, s3, exec_lo
	s_or_b32 s18, s18, exec_lo
.LBB3_102:                              ; %Flow888
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s18
	s_cbranch_execz .LBB3_105
; %bb.103:
	s_clause 0x2
	scratch_load_b128 v[24:27], off, off offset:16
	scratch_load_b128 v[10:13], off, off offset:32
	scratch_load_b64 v[14:15], off, off offset:48
	s_waitcnt vmcnt(3)
	v_dual_sub_f32 v20, v23, v17 :: v_dual_sub_f32 v21, v22, v16
	v_add_nc_u32_e32 v31, v34, v39
	s_load_b32 s1, s[0:1], 0x20
	s_mul_i32 s4, s19, s16
	s_delay_alu instid0(VALU_DEP_2)
	v_sub_f32_e32 v32, v20, v28
	v_sub_f32_e32 v34, v21, v19
	v_sub_f32_e32 v8, v22, v23
	s_mov_b32 s0, 0
	s_lshl_b32 s4, s4, 6
	s_waitcnt vmcnt(2)
	v_fma_f32 v46, v25, 2.0, -v26
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v47, v26, v10
	v_mad_u64_u32 v[20:21], null, v31, s16, v[33:34]
	v_add_f32_e32 v21, v32, v30
	v_dual_add_f32 v8, v16, v8 :: v_dual_add_f32 v31, v34, v29
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v39, v22, v15
	v_dual_sub_f32 v34, v26, v10 :: v_dual_add_f32 v47, v11, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v8, v17
	v_dual_add_f32 v48, v10, v10 :: v_dual_mul_f32 v43, 0x40400000, v25
	v_sub_f32_e64 v50, -v12, v11
	v_add_f32_e32 v47, v12, v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v8, v19
	v_fma_f32 v48, v26, -2.0, -v48
	v_mul_f32_e32 v45, 0x40400000, v15
	v_fma_f32 v43, 0x40400000, v27, -v43
	v_sub_f32_e32 v49, v11, v12
	v_add_f32_e32 v8, v28, v8
	v_sub_f32_e32 v40, v11, v24
	v_mul_f32_e32 v44, 0x40400000, v26
	v_fma_f32 v45, 0x40400000, v18, -v45
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_add_f32 v39, v23, v39 :: v_dual_sub_f32 v8, v8, v29
	v_mul_f32_e32 v42, -4.0, v25
	v_add_f32_e32 v51, v49, v13
	v_sub_f32_e32 v32, v25, v27
	v_dual_sub_f32 v49, v49, v13 :: v_dual_add_f32 v8, v30, v8
	v_dual_add_f32 v40, v12, v40 :: v_dual_add_f32 v47, v13, v47
	v_dual_add_f32 v39, v16, v39 :: v_dual_add_f32 v34, v11, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v51, v51, v14 :: v_dual_add_f32 v32, v32, v11
	v_add_f32_e32 v49, v49, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f32_e32 v39, v17, v39
	v_fmac_f32_e32 v46, 2.0, v27
	v_fmamk_f32 v42, v24, 0x41400000, v42
	v_dual_sub_f32 v32, v32, v12 :: v_dual_add_f32 v47, v14, v47
	v_sub_f32_e32 v39, v39, v18
	v_add_f32_e32 v34, v12, v34
	v_dual_sub_f32 v49, v49, v22 :: v_dual_add_f32 v50, v50, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v40, v13, v40 :: v_dual_sub_f32 v47, v47, v15
	v_dual_sub_f32 v39, v39, v19 :: v_dual_sub_f32 v46, v46, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v49, v49, v16 :: v_dual_fmac_f32 v42, -4.0, v26
	v_dual_sub_f32 v32, v32, v13 :: v_dual_sub_f32 v47, v47, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v39, v39, v28 :: v_dual_add_f32 v50, v50, v14
	v_dual_sub_f32 v49, v49, v19 :: v_dual_add_f32 v48, v11, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v34, v34, v13 :: v_dual_sub_f32 v47, v47, v16
	v_sub_f32_e32 v39, v39, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v49, v49, v29 :: v_dual_add_f32 v48, v12, v48
	v_fma_f32 v44, 0x40400000, v10, -v44
	v_dual_add_f32 v50, v50, v23 :: v_dual_sub_f32 v39, v39, v30
	v_add_f32_e32 v32, v32, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v56, v8, v49
	v_add_f32_e32 v58, v49, v8
	v_sub_f32_e64 v60, -v49, v8
	v_dual_add_f32 v45, v45, v39 :: v_dual_add_f32 v32, v32, v22
	v_mul_f32_e32 v62, v39, v39
	v_dual_add_f32 v48, v13, v48 :: v_dual_sub_f32 v47, v47, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v45, 0x3fd55555, v45 :: v_dual_sub_f32 v32, v32, v16
	v_sub_f32_e32 v47, v47, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v32, v32, v19 :: v_dual_sub_f32 v47, v47, v29
	v_sub_f32_e32 v32, v32, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v34, v34, v14 :: v_dual_add_f32 v43, v43, v32
	v_dual_add_f32 v34, v23, v34 :: v_dual_add_f32 v63, v32, v32
	v_fma_f32 v31, -v32, v39, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v64, 0x3fd55555, v43
	v_sub_f32_e32 v34, v34, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v34, v28, v34
	v_sub_f32_e32 v34, v34, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v44, v44, v34
	v_sub_f32_e32 v50, v50, v17
	v_fma_f32 v66, v34, v34, v62
	v_fma_f32 v51, -v32, v34, v51
	v_fma_f32 v21, -v34, v39, v21
	v_mul_f32_e32 v65, 0x3fd55555, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v50, v50, v28 :: v_dual_mul_f32 v21, 0x3e800000, v21
	v_sub_f32_e32 v50, v50, v30
	v_fmac_f32_e32 v42, -4.0, v27
	v_add_f32_e32 v40, v14, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v46, v11, v46 :: v_dual_add_f32 v61, v50, v8
	v_dual_sub_f32 v57, v50, v8 :: v_dual_fmac_f32 v42, -4.0, v10
	v_sub_f32_e32 v52, v49, v50
	v_sub_f32_e64 v53, -v49, v50
	v_dual_sub_f32 v54, v50, v49 :: v_dual_add_f32 v55, v49, v50
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v42, v11, v42
	v_sub_f32_e64 v59, -v50, v8
	v_dual_sub_f32 v49, v49, v8 :: v_dual_sub_f32 v8, v8, v50
	v_mul_f32_e32 v50, v34, v34
	v_add_f32_e32 v40, v22, v40
	v_add_f32_e32 v46, v12, v46
	v_fma_f32 v34, v34, v34, -v62
	v_fmamk_f32 v62, v43, 0x3fd55555, v45
	v_fmac_f32_e32 v50, v32, v32
	v_fma_f32 v32, v32, v63, -v66
	v_fmamk_f32 v63, v44, 0x3fd55555, v45
	v_add_f32_e32 v42, v12, v42
	v_add_f32_e32 v46, v13, v46
	v_fmac_f32_e32 v50, v39, v39
	v_sub_f32_e32 v34, v47, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmamk_f32 v47, v43, 0x3fd55555, v65 :: v_dual_add_f32 v42, v13, v42
	v_fma_f32 v44, 0x3fd55555, v44, -v45
	v_add_f32_e32 v42, v14, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v42, -4.0, v15
	v_add_f32_e32 v42, v22, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v42, v23, v42
	v_add_f32_e32 v42, v16, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v42, v17, v42
	v_fmac_f32_e32 v42, -4.0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v48, v14, v48 :: v_dual_add_f32 v39, v19, v42
	v_dual_add_f32 v40, v23, v40 :: v_dual_add_f32 v39, v28, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v39, v29, v39
	v_dual_add_f32 v39, v30, v39 :: v_dual_add_f32 v40, v16, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v39, v50, 0x40f14514, v39 :: v_dual_add_f32 v40, v17, v40
	v_add_f32_e32 v40, v19, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v40, v28, v40
	v_add_f32_e32 v40, v29, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v40, v30, v40
	v_sub_f32_e32 v40, v40, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v40, 0x41980000, v40
	v_mul_f32_e32 v66, 0xbc4d5033, v40
	v_add_f32_e32 v46, v14, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v46, v46, v15
	v_add_f32_e32 v46, v22, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v46, -2.0, v23
	v_add_f32_e32 v46, v16, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v46, -2.0, v17
	v_sub_f32_e32 v46, v46, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v46, v19, v46
	v_fmac_f32_e32 v46, -2.0, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v46, v29, v46
	v_fmac_f32_e32 v46, -2.0, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v32, v46, v32
	s_waitcnt lgkmcnt(0)
	v_dual_mul_f32 v46, 0x3daaaaab, v34 :: v_dual_mul_f32 v67, s1, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmamk_f32 v50, v32, 0x3ce38e39, v46
	v_fma_f32 v46, 0x3ce38e39, v32, -v46
	v_fmamk_f32 v68, v32, 0xbd638e39, v21
	v_fma_f32 v21, 0xbd638e39, v32, -v21
	v_fmamk_f32 v69, v51, 0x3e800000, v50
	v_fmac_f32_e32 v50, 0xbe800000, v51
	v_fmamk_f32 v51, v39, 0x3d430c31, v66
	v_fmamk_f32 v66, v31, 0x3e800000, v46
	v_mul_f32_e32 v32, 0xbc820821, v39
	v_mul_f32_e32 v39, 0x3b820821, v39
	v_fmac_f32_e32 v48, 2.0, v15
	v_fmac_f32_e32 v46, 0xbe800000, v31
	v_sub_f32_e32 v24, v24, v51
	v_fmamk_f32 v32, v40, 0xbb969026, v32
	v_fmamk_f32 v31, v40, 0x3b5b0037, v39
	v_sub_f32_e32 v48, v48, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v39, v64, 0xbdcccccd, v32
	v_dual_fmamk_f32 v73, v63, 0x3ccccccd, v31 :: v_dual_sub_f32 v48, v48, v16
	v_fmamk_f32 v40, v65, 0xbdcccccd, v32
	v_fmamk_f32 v51, v64, 0x3dcccccd, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v39, 0x3d638e39, v67
	v_dual_fmac_f32 v73, 0x3e000000, v57 :: v_dual_fmac_f32 v48, 2.0, v18
	v_fmamk_f32 v64, v65, 0x3dcccccd, v32
	v_fmamk_f32 v75, v44, 0xbccccccd, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v25, v25, v39
	v_dual_fmamk_f32 v71, v45, 0xbdcccccd, v32 :: v_dual_sub_f32 v48, v48, v19
	v_fmamk_f32 v72, v62, 0x3ccccccd, v31
	v_fmac_f32_e32 v32, 0x3dcccccd, v45
	v_fmamk_f32 v44, v44, 0x3ccccccd, v31
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_fmac_f32 v75, 0x3e000000, v59 :: v_dual_sub_f32 v42, v48, v29
	v_fma_f32 v48, 0x3fd55555, v43, -v65
	v_fma_f32 v43, 0x3fd55555, v43, -v45
	v_fmamk_f32 v65, v47, 0x3ccccccd, v31
	v_fmamk_f32 v47, v47, 0xbccccccd, v31
	v_fmamk_f32 v45, v62, 0xbccccccd, v31
	v_fmamk_f32 v70, v48, 0xbccccccd, v31
	v_fmamk_f32 v74, v43, 0xbccccccd, v31
	v_fmamk_f32 v43, v43, 0x3ccccccd, v31
	v_fmamk_f32 v48, v48, 0x3ccccccd, v31
	v_dual_add_f32 v62, 0, v65 :: v_dual_fmac_f32 v31, 0xbccccccd, v63
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v57, 0, v74
	v_add_f32_e32 v59, 0, v43
	v_add_f32_e32 v63, 0, v70
	v_dual_add_f32 v47, 0, v47 :: v_dual_add_f32 v48, 0, v48
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v57, 0xbd2aaaab, v42
	v_dual_add_f32 v65, 0, v72 :: v_dual_fmac_f32 v44, 0x3e000000, v61
	v_dual_add_f32 v61, 0, v45 :: v_dual_fmac_f32 v40, 0xbce38e39, v67
	v_fmac_f32_e32 v57, 0x3e000000, v58
	v_fmac_f32_e32 v62, 0x3d2aaaab, v42
	v_fmac_f32_e32 v59, 0xbd2aaaab, v42
	v_fmac_f32_e32 v63, 0x3d2aaaab, v42
	v_fmac_f32_e32 v47, 0x3d2aaaab, v42
	v_fmac_f32_e32 v48, 0x3d2aaaab, v42
	v_fmac_f32_e32 v65, 0xbd2aaaab, v42
	v_fmac_f32_e32 v62, 0x3e000000, v52
	v_fmac_f32_e32 v61, 0xbd2aaaab, v42
	v_fmac_f32_e32 v59, 0x3e000000, v60
	v_fma_f32 v34, v34, s1, -v42
	v_fmac_f32_e32 v64, 0xbce38e39, v67
	v_fmac_f32_e32 v63, 0x3e000000, v53
	v_fmac_f32_e32 v47, 0x3e000000, v54
	v_fmac_f32_e32 v71, 0xbce38e39, v67
	v_dual_fmac_f32 v48, 0x3e000000, v55 :: v_dual_fmac_f32 v65, 0x3e000000, v56
	v_fmac_f32_e32 v62, s1, v69
	v_fmac_f32_e32 v32, 0xbce38e39, v67
	v_fmac_f32_e32 v31, 0x3e000000, v8
	v_fmac_f32_e32 v61, 0x3e000000, v49
	v_fmac_f32_e32 v51, 0x3d638e39, v67
	v_fmac_f32_e32 v40, 0x3daaaaab, v34
	v_fmac_f32_e32 v64, 0x3daaaaab, v34
	v_fmac_f32_e32 v63, s1, v50
	v_fmac_f32_e32 v47, s1, v69
	v_dual_fmac_f32 v71, 0xbdaaaaab, v34 :: v_dual_fmac_f32 v44, s1, v21
	v_fmac_f32_e32 v48, s1, v50
	v_fmac_f32_e32 v65, s1, v66
	v_sub_f32_e32 v11, v11, v62
	v_fmac_f32_e32 v73, s1, v68
	v_dual_fmac_f32 v75, s1, v21 :: v_dual_fmac_f32 v32, 0xbdaaaaab, v34
	v_fmac_f32_e32 v57, s1, v46
	v_fmac_f32_e32 v59, s1, v46
	v_fmac_f32_e32 v31, s1, v68
	v_fmac_f32_e32 v61, s1, v66
	v_dual_sub_f32 v27, v27, v51 :: v_dual_sub_f32 v26, v26, v40
	v_sub_f32_e32 v10, v10, v64
	v_sub_f32_e32 v12, v12, v63
	v_sub_f32_e32 v13, v13, v47
	v_sub_f32_e32 v43, v15, v71
	v_sub_f32_e32 v45, v23, v73
	v_sub_f32_e32 v21, v28, v44
	v_sub_f32_e32 v42, v14, v48
	v_dual_sub_f32 v44, v22, v65 :: v_dual_sub_f32 v17, v17, v75
	v_sub_f32_e32 v18, v18, v32
	v_dual_sub_f32 v16, v16, v57 :: v_dual_sub_f32 v19, v19, v59
	v_dual_sub_f32 v23, v30, v31 :: v_dual_sub_f32 v22, v29, v61
	s_clause 0x4
	scratch_store_b128 off, v[24:27], off offset:16
	scratch_store_b128 off, v[10:13], off offset:32
	scratch_store_b128 off, v[42:45], off offset:48
	scratch_store_b128 off, v[16:19], off offset:64
	scratch_store_b96 off, v[21:23], off offset:80
.LBB3_104:                              ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s0, 16
	v_max_i32_e32 v10, 0, v20
	scratch_load_b32 v8, off, s1
	v_add_nc_u32_e32 v20, s4, v20
	s_add_i32 s0, s0, 4
	v_cmp_gt_i32_e32 vcc_lo, s7, v10
	s_cmpk_lg_i32 s0, 0x4c
	v_cndmask_b32_e32 v10, s17, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v8, off
	s_cbranch_scc1 .LBB3_104
.LBB3_105:                              ; %Flow889
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB3_107
; %bb.106:
	s_clause 0x2
	scratch_load_b64 v[14:15], off, off offset:76
	scratch_load_b128 v[10:13], off, off offset:52
	scratch_load_b32 v30, off, off offset:68
	v_add_nc_u32_e32 v16, v33, v37
	v_add_nc_u32_e32 v18, s20, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_max_i32_e32 v19, 0, v16
	v_add_nc_u32_e32 v8, v33, v36
	v_mad_u64_u32 v[16:17], null, v18, s16, v[33:34]
	v_add_nc_u32_e32 v18, s20, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_max_i32_e32 v8, 0, v8
	s_waitcnt vmcnt(3)
	v_mad_u64_u32 v[21:22], null, v18, s16, v[33:34]
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s7, v8
	v_max_i32_e32 v16, 0, v16
	v_cndmask_b32_e32 v17, s17, v8, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v19
	v_add_nc_u32_e32 v8, s6, v18
	v_max_i32_e32 v25, 0, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v18, 31, v17
	v_cndmask_b32_e32 v19, s17, v19, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v16
	v_mad_u64_u32 v[22:23], null, v8, s16, v[33:34]
	v_add_nc_u32_e32 v8, s6, v8
	v_ashrrev_i32_e32 v20, 31, v19
	v_lshlrev_b64 v[23:24], 2, v[17:18]
	v_cndmask_b32_e32 v16, s17, v16, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v25
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[18:19], 2, v[19:20]
	v_mad_u64_u32 v[20:21], null, v8, s16, v[33:34]
	v_cndmask_b32_e32 v21, s17, v25, vcc_lo
	v_add_co_u32 v23, vcc_lo, s8, v23
	v_add_nc_u32_e32 v8, s6, v8
	v_max_i32_e32 v27, 0, v22
	v_add_co_ci_u32_e32 v24, vcc_lo, s9, v24, vcc_lo
	v_add_co_u32 v18, vcc_lo, s8, v18
	v_ashrrev_i32_e32 v17, 31, v16
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
	v_mad_u64_u32 v[25:26], null, v8, s16, v[33:34]
	v_cmp_gt_i32_e32 vcc_lo, s7, v27
	v_max_i32_e32 v20, 0, v20
	v_add_nc_u32_e32 v8, s6, v8
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	v_ashrrev_i32_e32 v22, 31, v21
	v_cndmask_b32_e32 v26, s17, v27, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v20
	v_mad_u64_u32 v[28:29], null, v8, s16, v[33:34]
	v_max_i32_e32 v25, 0, v25
	v_add_nc_u32_e32 v29, s6, v8
	v_cndmask_b32_e32 v20, s17, v20, vcc_lo
	v_add_co_u32 v16, vcc_lo, s8, v16
	v_ashrrev_i32_e32 v27, 31, v26
	global_store_b32 v[23:24], v7, off
	v_lshlrev_b64 v[7:8], 2, v[21:22]
	v_add_co_ci_u32_e32 v17, vcc_lo, s9, v17, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v25
	v_mad_u64_u32 v[22:23], null, v29, s16, v[33:34]
	v_lshlrev_b64 v[23:24], 2, v[26:27]
	v_max_i32_e32 v27, 0, v28
	v_cndmask_b32_e32 v25, s17, v25, vcc_lo
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_nc_u32_e32 v29, s6, v29
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v27
	v_ashrrev_i32_e32 v21, 31, v20
	s_clause 0x1
	global_store_b32 v[16:17], v0, off
	global_store_b32 v[18:19], v5, off
	v_mad_u64_u32 v[16:17], null, v29, s16, v[33:34]
	v_max_i32_e32 v22, 0, v22
	v_cndmask_b32_e32 v5, s17, v27, vcc_lo
	global_store_b32 v[7:8], v6, off
	v_add_co_u32 v7, vcc_lo, s8, v23
	v_add_nc_u32_e32 v0, s6, v29
	v_lshlrev_b64 v[17:18], 2, v[20:21]
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v24, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v22
	v_ashrrev_i32_e32 v26, 31, v25
	v_mad_u64_u32 v[19:20], null, v0, s16, v[33:34]
	v_max_i32_e32 v24, 0, v16
	v_cndmask_b32_e32 v22, s17, v22, vcc_lo
	global_store_b32 v[7:8], v3, off
	v_add_co_u32 v7, vcc_lo, s8, v17
	v_add_nc_u32_e32 v0, s6, v0
	v_lshlrev_b64 v[20:21], 2, v[25:26]
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v18, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v24
	v_max_i32_e32 v3, 0, v19
	v_ashrrev_i32_e32 v6, 31, v5
	v_mad_u64_u32 v[16:17], null, v0, s16, v[33:34]
	v_cndmask_b32_e32 v17, s17, v24, vcc_lo
	global_store_b32 v[7:8], v38, off
	v_add_co_u32 v7, vcc_lo, s8, v20
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v21, vcc_lo
	v_add_nc_u32_e32 v0, s6, v0
	v_cmp_gt_i32_e32 vcc_lo, s7, v3
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_ashrrev_i32_e32 v23, 31, v22
	v_ashrrev_i32_e32 v18, 31, v17
	v_mad_u64_u32 v[19:20], null, v0, s16, v[33:34]
	v_add_nc_u32_e32 v24, s6, v0
	v_cndmask_b32_e32 v0, s17, v3, vcc_lo
	v_max_i32_e32 v3, 0, v16
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_lshlrev_b64 v[20:21], 2, v[22:23]
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s7, v3
	global_store_b32 v[7:8], v1, off
	v_mad_u64_u32 v[7:8], null, v24, s16, v[33:34]
	v_max_i32_e32 v22, 0, v19
	v_lshlrev_b64 v[16:17], 2, v[17:18]
	v_cndmask_b32_e32 v18, s17, v3, vcc_lo
	global_store_b32 v[5:6], v2, off
	v_add_co_u32 v2, vcc_lo, s8, v20
	v_add_nc_u32_e32 v8, s6, v24
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v21, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v22
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[5:6], null, v8, s16, v[33:34]
	v_max_i32_e32 v21, 0, v7
	v_cndmask_b32_e32 v6, s17, v22, vcc_lo
	global_store_b32 v[2:3], v9, off
	v_add_co_u32 v2, vcc_lo, s8, v16
	v_add_nc_u32_e32 v20, s6, v8
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v17, vcc_lo
	v_ashrrev_i32_e32 v19, 31, v18
	v_cmp_gt_i32_e32 vcc_lo, s7, v21
	v_mad_u64_u32 v[8:9], null, v20, s16, v[33:34]
	v_max_i32_e32 v5, 0, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[16:17], 2, v[18:19]
	v_cndmask_b32_e32 v18, s17, v21, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_nc_u32_e32 v9, s6, v20
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v5
	v_ashrrev_i32_e32 v7, 31, v6
	global_store_b32 v[2:3], v4, off
	v_mad_u64_u32 v[2:3], null, v9, s16, v[33:34]
	v_max_i32_e32 v20, 0, v8
	v_add_nc_u32_e32 v9, s6, v9
	v_cndmask_b32_e32 v5, s17, v5, vcc_lo
	global_store_b32 v[0:1], v41, off
	v_add_co_u32 v0, vcc_lo, s8, v16
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[3:4], 2, v[6:7]
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v17, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v20
	v_mad_u64_u32 v[7:8], null, v9, s16, v[33:34]
	v_lshlrev_b64 v[8:9], 2, v[18:19]
	v_max_i32_e32 v18, 0, v2
	v_cndmask_b32_e32 v16, s17, v20, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v4, vcc_lo
	v_ashrrev_i32_e32 v6, 31, v5
	v_cmp_gt_i32_e32 vcc_lo, s7, v18
	v_ashrrev_i32_e32 v17, 31, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_cndmask_b32_e32 v6, s17, v18, vcc_lo
	v_max_i32_e32 v18, 0, v7
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s7, v18
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	v_cndmask_b32_e32 v18, s17, v18, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	v_ashrrev_i32_e32 v19, 31, v18
	v_add_co_u32 v16, vcc_lo, s8, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s9, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v18, vcc_lo, s8, v18
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v19, vcc_lo
	s_waitcnt vmcnt(2)
	s_clause 0x1
	global_store_b32 v[0:1], v14, off
	global_store_b32 v[2:3], v15, off
	s_waitcnt vmcnt(1)
	s_clause 0x1
	global_store_b32 v[8:9], v10, off
	global_store_b32 v[4:5], v13, off
	s_waitcnt vmcnt(0)
	s_clause 0x2
	global_store_b32 v[16:17], v30, off
	global_store_b32 v[6:7], v11, off
	global_store_b32 v[18:19], v12, off
.LBB3_107:                              ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10update_innPfS_S_S_fmiiPS_S0_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 96
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 78
		.amdhsa_next_free_sgpr 31
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z10update_innPfS_S_S_fmiiPS_S0_i, .Lfunc_end3-_Z10update_innPfS_S_S_fmiiPS_S0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 13084
; NumSgprs: 33
; NumVgprs: 78
; ScratchSize: 96
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 33
; NumVGPRsForWavesPerEU: 78
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10initializePfmiii
    .private_segment_fixed_size: 96
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10initializePfmiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10update_topPfS_S_S_fmii
    .private_segment_fixed_size: 96
    .sgpr_count:     33
    .sgpr_spill_count: 0
    .symbol:         _Z10update_topPfS_S_S_fmii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     88
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10update_botPfS_S_S_fmii
    .private_segment_fixed_size: 96
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z10update_botPfS_S_S_fmii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     89
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10update_innPfS_S_S_fmiiPS_S0_i
    .private_segment_fixed_size: 96
    .sgpr_count:     33
    .sgpr_spill_count: 0
    .symbol:         _Z10update_innPfS_S_S_fmiiPS_S0_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     78
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
