#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <ctime>
#include <cmath>

#define	N	(1024*1024)		

__global__ void kernel(float *data)
{
   int   idx = blockIdx.x * blockDim.x + threadIdx.x;
   float x   = 2.0f * 3.1415926f * (float) idx / (float) N;
   data [idx] = tanf (x);
}

int main (int argc, char *argv[])
{
    //-------------------- GPU PART --------------------
 
    float *a = new float [N];	
    float *dev = NULL;
		
    cudaEvent_t start, stop;
	  float gpuTime = 0.0f;
	  cudaEventCreate(&start);
	  cudaEventCreate(&stop);
 
	  cudaEventRecord(start, 0);

    cudaMalloc((void**)&dev, N * sizeof(float));

    kernel<<<dim3((N/512),1), dim3(512,1)>>> (dev);

    cudaMemcpy(a, dev, N * sizeof(float), cudaMemcpyDeviceToHost);
 
    cudaThreadSynchronize();
	  cudaEventRecord(stop, 0);

	  cudaEventSynchronize(stop);
  	cudaEventElapsedTime(&gpuTime, start, stop);

    printf("\n====================   GPU TIME   ====================\n");
  	printf("\nGPU compute time: %.2f milliseconds\n\n", gpuTime);
    
    cudaFree(dev);
         
    //-------------------- CPU PART --------------------
  
    int start2, time2;
    float *data2 = new float [N];
    
	  start2 = clock();
		
    for (int idx2 = 0; idx2 < N; idx2++)
    {
        float x2   = 2.0f * 3.1415926f * (float) idx2 / (float) N;
        data2 [idx2] = sinf (x2);
        //printf("a[%d] = %.5f\n", idx2, data2[idx2]);
    }
    
    time2 = clock() - start2;
	  double time_CPU = time2;

	  printf("====================   CPU TIME   ====================\n");
	  printf("\nCPU compute time: %f milliseconds\n\n", time_CPU);
    
    //-------------------- PRINT VALUES PART --------------------
 
    printf("=====================   Values   =====================\n");

    int idx = 0;
    printf("\nValue at point (zero):\na[%d] = %.5f\n", idx, a[idx]);
 
    idx = N/12;
    printf("\nValue at point (Pi/6):\na[%d] = %.5f\n", idx, a[idx]);
 
    idx = N/8;
    printf("\nValue at point (Pi/4):\na[%d] = %.5f\n", idx, a[idx]);
 
    idx = N/6;
    printf("\nValue at point (Pi/3):\na[%d] = %.5f\n", idx, a[idx]);
 
    idx = N/4;
    printf("\nValue at point (Pi/2):\na[%d] = %.5f\n", idx, a[idx]);
    
    printf("\n=======================================================\n");

    return 0;
}
	.file	"tmpxft_0023a185_00000000-6_LR1_VorobevAV.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z25__device_stub__Z6kernelPfPf
	.type	_Z25__device_stub__Z6kernelPfPf, @function
_Z25__device_stub__Z6kernelPfPf:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z6kernelPf(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L2:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z25__device_stub__Z6kernelPfPf, .-_Z25__device_stub__Z6kernelPfPf
	.globl	_Z6kernelPf
	.type	_Z6kernelPf, @function
_Z6kernelPf:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z6kernelPfPf
	.cfi_endproc
.LFE2053:
	.size	_Z6kernelPf, .-_Z6kernelPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"\n====================   GPU TIME   ====================\n"
.LC2:
	.string	"\nGPU compute time: %.2f milliseconds\n\n"
.LC5:
	.string	"====================   CPU TIME   ====================\n"
.LC6:
	.string	"\nCPU compute time: %f milliseconds\n\n"
.LC7:
	.string	"=====================   Values   =====================\n"
.LC8:
	.string	"\nValue at point (zero):\na[%d] = %.5f\n"
.LC9:
	.string	"\nValue at point (Pi/6):\na[%d] = %.5f\n"
.LC10:
	.string	"\nValue at point (Pi/4):\na[%d] = %.5f\n"
.LC11:
	.string	"\nValue at point (Pi/3):\na[%d] = %.5f\n"
.LC12:
	.string	"\nValue at point (Pi/2):\na[%d] = %.5f\n"
.LC13:
	.string	"\n=======================================================\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$4194304, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	leaq	32(%rsp), %rdi
	movl	$0x00000000, 20(%rsp)
	movq	%rax, %rbx
	xorl	%eax, %eax
	movq	%rax, 24(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	24(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$2097153, %edi
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$11, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	24(%rsp), %rdi
	call	_Z25__device_stub__Z6kernelPfPf
.L9:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	xorl	%ebp, %ebp
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	20(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movl	$4194304, %edi
	call	_Znam@PLT
	movq	%rax, %r13
	call	clock@PLT
	movq	%rax, %r12
.L10:
	cvtsi2ssl	%ebp, %xmm0
	mulss	.LC3(%rip), %xmm0
	mulss	.LC4(%rip), %xmm0
	call	sinf@PLT
	movss	%xmm0, 0(%r13,%rbp,4)
	incq	%rbp
	cmpq	$1048576, %rbp
	jne	.L10
	call	clock@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	subl	%r12d, %eax
	cvtsi2sdl	%eax, %xmm0
	xorl	%eax, %eax
	movsd	%xmm0, 8(%rsp)
	call	__printf_chk@PLT
	movsd	8(%rsp), %xmm0
	leaq	.LC6(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%edx, %edx
	leaq	.LC8(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	(%rbx), %xmm0
	call	__printf_chk@PLT
	movl	$87381, %edx
	leaq	.LC9(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	349524(%rbx), %xmm0
	call	__printf_chk@PLT
	movl	$131072, %edx
	leaq	.LC10(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	524288(%rbx), %xmm0
	call	__printf_chk@PLT
	movl	$174762, %edx
	leaq	.LC11(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	699048(%rbx), %xmm0
	call	__printf_chk@PLT
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movl	$262144, %edx
	cvtss2sd	1048576(%rbx), %xmm0
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC13(%rip), %rsi
	call	__printf_chk@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC14:
	.string	"_Z6kernelPf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kernelPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1086918618
	.align 4
.LC4:
	.long	897581056
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include "hip/hip_runtime.h"

#include <stdio.h>
#include <ctime>
#include <cmath>

#define	N	(1024*1024)		

__global__ void kernel(float *data)
{
   int   idx = blockIdx.x * blockDim.x + threadIdx.x;
   float x   = 2.0f * 3.1415926f * (float) idx / (float) N;
   data [idx] = tanf (x);
}

int main (int argc, char *argv[])
{
    //-------------------- GPU PART --------------------
 
    float *a = new float [N];	
    float *dev = NULL;
		
    hipEvent_t start, stop;
	  float gpuTime = 0.0f;
	  hipEventCreate(&start);
	  hipEventCreate(&stop);
 
	  hipEventRecord(start, 0);

    hipMalloc((void**)&dev, N * sizeof(float));

    kernel<<<dim3((N/512),1), dim3(512,1)>>> (dev);

    hipMemcpy(a, dev, N * sizeof(float), hipMemcpyDeviceToHost);
 
    hipDeviceSynchronize();
	  hipEventRecord(stop, 0);

	  hipEventSynchronize(stop);
  	hipEventElapsedTime(&gpuTime, start, stop);

    printf("\n====================   GPU TIME   ====================\n");
  	printf("\nGPU compute time: %.2f milliseconds\n\n", gpuTime);
    
    hipFree(dev);
         
    //-------------------- CPU PART --------------------
  
    int start2, time2;
    float *data2 = new float [N];
    
	  start2 = clock();
		
    for (int idx2 = 0; idx2 < N; idx2++)
    {
        float x2   = 2.0f * 3.1415926f * (float) idx2 / (float) N;
        data2 [idx2] = sinf (x2);
        //printf("a[%d] = %.5f\n", idx2, data2[idx2]);
    }
    
    time2 = clock() - start2;
	  double time_CPU = time2;

	  printf("====================   CPU TIME   ====================\n");
	  printf("\nCPU compute time: %f milliseconds\n\n", time_CPU);
    
    //-------------------- PRINT VALUES PART --------------------
 
    printf("=====================   Values   =====================\n");

    int idx = 0;
    printf("\nValue at point (zero):\na[%d] = %.5f\n", idx, a[idx]);
 
    idx = N/12;
    printf("\nValue at point (Pi/6):\na[%d] = %.5f\n", idx, a[idx]);
 
    idx = N/8;
    printf("\nValue at point (Pi/4):\na[%d] = %.5f\n", idx, a[idx]);
 
    idx = N/6;
    printf("\nValue at point (Pi/3):\na[%d] = %.5f\n", idx, a[idx]);
 
    idx = N/4;
    printf("\nValue at point (Pi/2):\na[%d] = %.5f\n", idx, a[idx]);
    
    printf("\n=======================================================\n");

    return 0;
}
	.text
	.file	"LR1_VorobevAV.hip"
	.globl	_Z21__device_stub__kernelPf     # -- Begin function _Z21__device_stub__kernelPf
	.type	_Z21__device_stub__kernelPf,@function
_Z21__device_stub__kernelPf:            # @_Z21__device_stub__kernelPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelPf, .Lfunc_end0-_Z21__device_stub__kernelPf
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x40c90fda                      # float 6.283185
.LCPI1_1:
	.long	0x35800000                      # float 9.53674316E-7
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %rbx
	leaq	16(%rsp), %r14
	movq	$0, (%r14)
	movl	$0, 28(%rsp)
	leaq	40(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r14, %rdi
	callq	hipMalloc
	movabsq	$4294967808, %rdx               # imm = 0x100000200
	leaq	1536(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	16(%rsp), %rdi
	callq	_Z21__device_stub__kernelPf
.LBB1_2:
	movq	16(%rsp), %rsi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	28(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movl	$.Lstr, %edi
	callq	puts@PLT
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	16(%rsp), %rdi
	callq	hipFree
	callq	clock
	movq	%rax, %r14
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r15d, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	mulss	.LCPI1_1(%rip), %xmm0
	callq	sinf
	incl	%r15d
	cmpl	$1048576, %r15d                 # imm = 0x100000
	jne	.LBB1_3
# %bb.4:
	callq	clock
	subl	%r14d, %eax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	movsd	%xmm0, 32(%rsp)                 # 8-byte Spill
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$.L.str.3, %edi
	movsd	32(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.5, %edi
	xorl	%esi, %esi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	349524(%rbx), %xmm0
	movl	$.L.str.6, %edi
	movl	$87381, %esi                    # imm = 0x15555
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	524288(%rbx), %xmm0
	movl	$.L.str.7, %edi
	movl	$131072, %esi                   # imm = 0x20000
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	699048(%rbx), %xmm0
	movl	$.L.str.8, %edi
	movl	$174762, %esi                   # imm = 0x2AAAA
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	1048576(%rbx), %xmm0
	movl	$.L.str.9, %edi
	movl	$262144, %esi                   # imm = 0x40000
	movb	$1, %al
	callq	printf
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kernelPf,@object             # @_Z6kernelPf
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelPf
	.p2align	3, 0x0
_Z6kernelPf:
	.quad	_Z21__device_stub__kernelPf
	.size	_Z6kernelPf, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"\nGPU compute time: %.2f milliseconds\n\n"
	.size	.L.str.1, 39

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"\nCPU compute time: %f milliseconds\n\n"
	.size	.L.str.3, 37

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"\nValue at point (zero):\na[%d] = %.5f\n"
	.size	.L.str.5, 38

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\nValue at point (Pi/6):\na[%d] = %.5f\n"
	.size	.L.str.6, 38

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"\nValue at point (Pi/4):\na[%d] = %.5f\n"
	.size	.L.str.7, 38

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"\nValue at point (Pi/3):\na[%d] = %.5f\n"
	.size	.L.str.8, 38

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"\nValue at point (Pi/2):\na[%d] = %.5f\n"
	.size	.L.str.9, 38

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kernelPf"
	.size	.L__unnamed_1, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n====================   GPU TIME   ===================="
	.size	.Lstr, 56

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"====================   CPU TIME   ===================="
	.size	.Lstr.1, 55

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"=====================   Values   ====================="
	.size	.Lstr.2, 55

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"\n======================================================="
	.size	.Lstr.3, 57

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kernelPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kernelPf             ; -- Begin function _Z6kernelPf
	.globl	_Z6kernelPf
	.p2align	8
	.type	_Z6kernelPf,@function
_Z6kernelPf:                            ; @_Z6kernelPf
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
                                        ; implicit-def: $vgpr4
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
                                        ; implicit-def: $vgpr2
	v_cvt_f32_i32_e32 v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, 0x40c90fda, v0
	v_mul_f32_e32 v0, 0x35800000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v3, 0x7fffffff, v0
	v_cmpx_ngt_f32_e64 0x48000000, |v0|
	s_xor_b32 s4, exec_lo, s3
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v6, 0
	v_and_or_b32 v2, v3, s2, 0x800000
	v_lshrrev_b32_e32 v11, 23, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, 0xfe5163ab, v2, 0
	v_add_nc_u32_e32 v12, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v12
	v_mad_u64_u32 v[7:8], null, 0x3c439041, v2, v[5:6]
	v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v5, v8
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, 0xdb629599, v2, v[5:6]
	v_cmp_lt_u32_e64 s2, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s2
	v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v14, v13
	v_mad_u64_u32 v[9:10], null, 0xf534ddc0, v2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v14
	v_mov_b32_e32 v5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v9, v7, vcc_lo
	v_mad_u64_u32 v[10:11], null, 0xfc2757d1, v2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v5, v11
	v_mad_u64_u32 v[11:12], null, 0x4e441529, v2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v5, v12
	v_mad_u64_u32 v[12:13], null, 0xa2f9836e, v2, v[5:6]
	v_cndmask_b32_e64 v2, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v5, v11, v9 :: v_dual_add_nc_u32 v2, v2, v14
	v_dual_cndmask_b32 v6, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
	v_cndmask_b32_e32 v10, v10, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v9, v6, v5, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, v11, v6, s2
	v_cndmask_b32_e64 v5, v5, v10, s2
	v_sub_nc_u32_e32 v11, 32, v2
	v_cndmask_b32_e64 v10, v10, v7, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, v6, v9, s3
	v_cndmask_b32_e64 v9, v9, v5, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, v5, v10, s3
	v_alignbit_b32 v12, v6, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v8, v9, v5, v11
	v_cndmask_b32_e32 v2, v12, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v8, v9, vcc_lo
	v_cndmask_b32_e64 v4, v7, v4, s2
	v_bfe_u32 v7, v2, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v2, v6, 30
	v_cndmask_b32_e64 v4, v10, v4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, 0, v7
	v_alignbit_b32 v10, v5, v4, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v8, v9
	v_cndmask_b32_e32 v5, v10, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v10, v8
	v_alignbit_b32 v6, v6, v5, 30
	v_alignbit_b32 v4, v5, v4, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_u32_e32 v10, 32, v10
	v_xor_b32_e32 v5, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v9
	v_sub_nc_u32_e32 v6, 31, v10
	v_lshlrev_b32_e32 v12, 23, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v8, v8, v5, v6
	v_alignbit_b32 v4, v5, v4, v6
	v_lshrrev_b32_e32 v6, 29, v2
	v_lshrrev_b32_e32 v2, 30, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v8, v4, 9
	v_lshlrev_b32_e32 v6, 31, v6
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v2, v7, v2
	v_clz_i32_u32_e32 v9, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v11, 0.5, v6
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v12
	v_sub_nc_u32_e32 v13, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v4, v5, v4, v13
	v_or_b32_e32 v5, v8, v11
	v_add_lshl_u32 v8, v9, v10, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v4, 9, v4
	v_mul_f32_e32 v9, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v4, v8
	v_fma_f32 v8, 0x3fc90fda, v5, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 0x33000000, v4
	v_fmamk_f32 v5, v5, 0x33a22168, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v4, v4, v6
	v_fmac_f32_e32 v5, 0x3fc90fda, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v9, v5
.LBB0_2:                                ; %Flow
	s_and_not1_saveexec_b32 s2, s4
; %bb.3:
	v_mul_f32_e64 v2, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v2, v2
	v_fma_f32 v4, 0xbfc90fda, v2, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v4, v2, 0xb3a22168, v4
	v_fmamk_f32 v4, v2, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v2, v2
; %bb.4:                                ; %_ZL4tanff.exit
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, v4, v4
	s_mov_b32 s2, 0x3c971480
	s_load_b64 s[0:1], s[0:1], 0x0
	v_and_b32_e32 v2, 1, v2
	v_fmaak_f32 v6, s2, v5, 0xbf039337
	s_mov_b32 s2, 0xbc8cedd3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v7, s2, v5, 0x3ec54587
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v6, v5, v6, 0x3f93f425
	v_ashrrev_i32_e32 v2, 31, v1
	v_rcp_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, v7, v6
	v_mul_f32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v5, v4, v4
	v_sub_f32_e32 v8, v6, v4
	v_rcp_f32_e32 v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v5, v4, -v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, v6, -v7, 1.0
	v_fma_f32 v4, v4, -v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v4, -v7, -v7
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v3, v3, v0, v4
	v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kernelPf, .Lfunc_end0-_Z6kernelPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1088
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
