#include <cuda.h>
#include <stdio.h>
#include <string.h>

__global__ void CountSort(int*, int*, int, int);

__host__ void counting_sort(int* arr, int size, int max_val)
{
	int block_num = 1000;
	int thread_num_per_block = 1000;
	uint64_t histo_size = sizeof(int)*max_val;
	printf("size: %d\n", size);
	printf("max_val: %d\n", max_val);
	printf("block_num: %d\n", block_num);
	printf("thread_per_block: %d\n", thread_num_per_block);

	int* darr;
	cudaMalloc(&darr, sizeof(int)*size);
	cudaMemcpy(darr, arr, sizeof(int)*size, cudaMemcpyHostToDevice); 

	int* dhisto;
	cudaMalloc(&dhisto, histo_size);
	cudaMemset(dhisto, 0, histo_size);

	printf("countsort start\n");
	CountSort<<<block_num, thread_num_per_block>>>(darr, dhisto, size, max_val);
	printf("countsort end\n");
	
	//int* histo = (int*)calloc(max_val, sizeof(int)); 
	//cudaMemcpy(histo, dhisto, sizeof(int)*max_val, cudaMemcpyDeviceToHost);
	cudaMemcpy(arr, darr, sizeof(int)*size, cudaMemcpyDeviceToHost);
	
	
	/*
	int cnt = 0;
	for(int i=0; i<max_val; i++) {
		cnt += histo[i];
	}
	printf("cnt: %d\n", cnt);
	*/
	
	/*
	int idx = 0;
	for(int i=0; i<max_val; i++) {
		for(int j=0; j<histo[i]; j++) {
			arr[idx++] = i;
		}
	}
	*/
	//cudaFree(dhisto);
	//cudaFree(darr);
	//free(histo);
	printf("return to main\n");
}

__global__ void CountSort(int* darr, int* dhisto, int size, int max_val) {

	uint64_t thread_per_block = blockDim.x;
	uint64_t total_block = gridDim.x;
	uint64_t bid = blockIdx.x;
	uint64_t tid = threadIdx.x;
	uint64_t size_per_block, bstart, size_per_thread, start, end;

	// update histogram	in each block
	if(size % total_block != 0 && bid == total_block - 1) {
		size_per_block = size / total_block + size % total_block;
		bstart = bid * (size / total_block);
		size_per_thread = size_per_block / thread_per_block;
		start = bstart + tid * size_per_thread;
		end = start + size_per_thread;
		if(size_per_block % thread_per_block != 0 && 
				tid == thread_per_block - 1) {
			end += size_per_block % thread_per_block;
		}
	}
	else {
		size_per_block = size / total_block;
		bstart = bid * size_per_block;	
		size_per_thread = size_per_block / thread_per_block;
		start = bstart + tid * size_per_thread;
		end = start + size_per_thread;
		if(size_per_block % thread_per_block != 0 && tid == thread_per_block - 1) {
			end += size_per_block % thread_per_block;
		}
	}
	for(uint64_t i=start; i<end; i++) {
		atomicAdd(&dhisto[darr[i]], 1);
	}
	__syncthreads();


	if(bid == 0 && tid == 0) {
		/*
		for(int i=0; i<max_val; i++) {
			printf("histo[%d]: %d\n", i, dhisto[i]);
		}
		*/
		for(int i=1; i<max_val; i++) {
			dhisto[i] += dhisto[i-1];
		}
		/*
		for(int i=0; i<max_val; i++) {
			printf("histo[%d]: %d\n", i, dhisto[i]);
		}
		*/
	}
	__syncthreads();

	//printf("thread_per_block: %d\n", thread_per_block);
	size_per_block = max_val / total_block;		
	bstart = bid * size_per_block;
	size_per_thread = size_per_block / thread_per_block;
	start = bstart + tid * size_per_thread;
	end = start + size_per_thread;
	//printf("size_per_block: %d, thread_per_block: %d, bstart: %d, size_per_thread: %d\n", size_per_block, thread_per_block, bstart, size_per_thread);
	//printf("bid: %d, tid: %d => start: %d, end: %d\n", tid, bid, start, end);
	for(uint64_t i=start; i<end; i++) {
		darr[i] = i;
	}

	__syncthreads();
}

	.file	"tmpxft_0032ca43_00000000-6_counting_sort.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z9CountSortPiS_iiPiS_ii
	.type	_Z32__device_stub__Z9CountSortPiS_iiPiS_ii, @function
_Z32__device_stub__Z9CountSortPiS_iiPiS_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9CountSortPiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z32__device_stub__Z9CountSortPiS_iiPiS_ii, .-_Z32__device_stub__Z9CountSortPiS_iiPiS_ii
	.globl	_Z9CountSortPiS_ii
	.type	_Z9CountSortPiS_ii, @function
_Z9CountSortPiS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9CountSortPiS_iiPiS_ii
	.cfi_endproc
.LFE2053:
	.size	_Z9CountSortPiS_ii, .-_Z9CountSortPiS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"size: %d\n"
.LC1:
	.string	"max_val: %d\n"
.LC2:
	.string	"block_num: %d\n"
.LC3:
	.string	"thread_per_block: %d\n"
.LC4:
	.string	"countsort start\n"
.LC5:
	.string	"countsort end\n"
.LC6:
	.string	"return to main\n"
	.text
	.globl	_Z13counting_sortPiii
	.type	_Z13counting_sortPiii, @function
_Z13counting_sortPiii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movslq	%edx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdi, %r13
	movl	$2, %edi
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%r14, %r12
	salq	$2, %r14
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movslq	%esi, %rbx
	leaq	.LC0(%rip), %rsi
	movl	%ebx, %edx
	movq	%rbx, %rbp
	salq	$2, %rbx
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%r12d, %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rsi
	call	__printf_chk@PLT
	movl	$1000, %edx
	leaq	.LC2(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$1000, %edx
	leaq	.LC3(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%r14, %rdx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$536871037, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z32__device_stub__Z9CountSortPiS_iiPiS_ii
.L9:
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	(%rsp), %rsi
	movq	%r13, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC6(%rip), %rsi
	call	__printf_chk@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z13counting_sortPiii, .-_Z13counting_sortPiii
	.section	.rodata.str1.1
.LC7:
	.string	"_Z9CountSortPiS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9CountSortPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>

__global__ void CountSort(int*, int*, int, int);

__host__ void counting_sort(int* arr, int size, int max_val)
{
	int block_num = 1000;
	int thread_num_per_block = 1000;
	uint64_t histo_size = sizeof(int)*max_val;
	printf("size: %d\n", size);
	printf("max_val: %d\n", max_val);
	printf("block_num: %d\n", block_num);
	printf("thread_per_block: %d\n", thread_num_per_block);

	int* darr;
	hipMalloc(&darr, sizeof(int)*size);
	hipMemcpy(darr, arr, sizeof(int)*size, hipMemcpyHostToDevice); 

	int* dhisto;
	hipMalloc(&dhisto, histo_size);
	hipMemset(dhisto, 0, histo_size);

	printf("countsort start\n");
	CountSort<<<block_num, thread_num_per_block>>>(darr, dhisto, size, max_val);
	printf("countsort end\n");
	
	//int* histo = (int*)calloc(max_val, sizeof(int)); 
	//cudaMemcpy(histo, dhisto, sizeof(int)*max_val, cudaMemcpyDeviceToHost);
	hipMemcpy(arr, darr, sizeof(int)*size, hipMemcpyDeviceToHost);
	
	
	/*
	int cnt = 0;
	for(int i=0; i<max_val; i++) {
		cnt += histo[i];
	}
	printf("cnt: %d\n", cnt);
	*/
	
	/*
	int idx = 0;
	for(int i=0; i<max_val; i++) {
		for(int j=0; j<histo[i]; j++) {
			arr[idx++] = i;
		}
	}
	*/
	//cudaFree(dhisto);
	//cudaFree(darr);
	//free(histo);
	printf("return to main\n");
}

__global__ void CountSort(int* darr, int* dhisto, int size, int max_val) {

	uint64_t thread_per_block = blockDim.x;
	uint64_t total_block = gridDim.x;
	uint64_t bid = blockIdx.x;
	uint64_t tid = threadIdx.x;
	uint64_t size_per_block, bstart, size_per_thread, start, end;

	// update histogram	in each block
	if(size % total_block != 0 && bid == total_block - 1) {
		size_per_block = size / total_block + size % total_block;
		bstart = bid * (size / total_block);
		size_per_thread = size_per_block / thread_per_block;
		start = bstart + tid * size_per_thread;
		end = start + size_per_thread;
		if(size_per_block % thread_per_block != 0 && 
				tid == thread_per_block - 1) {
			end += size_per_block % thread_per_block;
		}
	}
	else {
		size_per_block = size / total_block;
		bstart = bid * size_per_block;	
		size_per_thread = size_per_block / thread_per_block;
		start = bstart + tid * size_per_thread;
		end = start + size_per_thread;
		if(size_per_block % thread_per_block != 0 && tid == thread_per_block - 1) {
			end += size_per_block % thread_per_block;
		}
	}
	for(uint64_t i=start; i<end; i++) {
		atomicAdd(&dhisto[darr[i]], 1);
	}
	__syncthreads();


	if(bid == 0 && tid == 0) {
		/*
		for(int i=0; i<max_val; i++) {
			printf("histo[%d]: %d\n", i, dhisto[i]);
		}
		*/
		for(int i=1; i<max_val; i++) {
			dhisto[i] += dhisto[i-1];
		}
		/*
		for(int i=0; i<max_val; i++) {
			printf("histo[%d]: %d\n", i, dhisto[i]);
		}
		*/
	}
	__syncthreads();

	//printf("thread_per_block: %d\n", thread_per_block);
	size_per_block = max_val / total_block;		
	bstart = bid * size_per_block;
	size_per_thread = size_per_block / thread_per_block;
	start = bstart + tid * size_per_thread;
	end = start + size_per_thread;
	//printf("size_per_block: %d, thread_per_block: %d, bstart: %d, size_per_thread: %d\n", size_per_block, thread_per_block, bstart, size_per_thread);
	//printf("bid: %d, tid: %d => start: %d, end: %d\n", tid, bid, start, end);
	for(uint64_t i=start; i<end; i++) {
		darr[i] = i;
	}

	__syncthreads();
}

	.text
	.file	"counting_sort.hip"
	.globl	_Z13counting_sortPiii           # -- Begin function _Z13counting_sortPiii
	.type	_Z13counting_sortPiii,@function
_Z13counting_sortPiii:                  # @_Z13counting_sortPiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movslq	%edx, %r15
	leaq	(,%r15,4), %r12
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.2, %edi
	movl	$1000, %esi                     # imm = 0x3E8
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.3, %edi
	movl	$1000, %esi                     # imm = 0x3E8
	xorl	%eax, %eax
	callq	printf
	movslq	%r14d, %r15
	shlq	$2, %r15
	leaq	8(%rsp), %r13
	movq	%r13, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	hipMemset
	movl	$.Lstr, %edi
	callq	puts@PLT
	movabsq	$4294968296, %rdi               # imm = 0x1000003E8
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	callq	_Z24__device_stub__CountSortPiS_ii
.LBB0_2:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z13counting_sortPiii, .Lfunc_end0-_Z13counting_sortPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__CountSortPiS_ii # -- Begin function _Z24__device_stub__CountSortPiS_ii
	.type	_Z24__device_stub__CountSortPiS_ii,@function
_Z24__device_stub__CountSortPiS_ii:     # @_Z24__device_stub__CountSortPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9CountSortPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__CountSortPiS_ii, .Lfunc_end1-_Z24__device_stub__CountSortPiS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9CountSortPiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"size: %d\n"
	.size	.L.str, 10

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"max_val: %d\n"
	.size	.L.str.1, 13

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"block_num: %d\n"
	.size	.L.str.2, 15

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"thread_per_block: %d\n"
	.size	.L.str.3, 22

	.type	_Z9CountSortPiS_ii,@object      # @_Z9CountSortPiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z9CountSortPiS_ii
	.p2align	3, 0x0
_Z9CountSortPiS_ii:
	.quad	_Z24__device_stub__CountSortPiS_ii
	.size	_Z9CountSortPiS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9CountSortPiS_ii"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"countsort start"
	.size	.Lstr, 16

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"countsort end"
	.size	.Lstr.1, 14

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"return to main"
	.size	.Lstr.2, 15

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__CountSortPiS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9CountSortPiS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9CountSortPiS_ii      ; -- Begin function _Z9CountSortPiS_ii
	.globl	_Z9CountSortPiS_ii
	.p2align	8
	.type	_Z9CountSortPiS_ii,@function
_Z9CountSortPiS_ii:                     ; @_Z9CountSortPiS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s10, s[0:1], 0x18
	s_load_b32 s4, s[0:1], 0x24
	v_cvt_f32_u32_e32 v1, 0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mov_b32 s8, s15
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v2, s10
	s_and_b32 s11, s4, 0xffff
	s_ashr_i32 s7, s2, 31
	s_sub_u32 s6, 0, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, 0x4f800000, v1
	s_subb_u32 s9, 0, 0
	v_cvt_f32_u32_e32 v8, s11
	v_rcp_f32_e32 v1, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, 0xcf800000, v2
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s4, v2
	v_readfirstlane_b32 s5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s12, s6, s4
	s_mul_hi_u32 s14, s6, s5
	s_mul_i32 s13, s9, s5
	s_add_i32 s12, s14, s12
	s_mul_i32 s15, s6, s5
	s_add_i32 s12, s12, s13
	s_mul_hi_u32 s14, s5, s15
	s_mul_hi_u32 s16, s4, s15
	s_mul_i32 s13, s4, s15
	s_mul_hi_u32 s15, s5, s12
	s_mul_i32 s5, s5, s12
	s_mul_hi_u32 s17, s4, s12
	s_add_u32 s5, s14, s5
	s_addc_u32 s14, 0, s15
	s_add_u32 s5, s5, s13
	s_mul_i32 s12, s4, s12
	s_addc_u32 s5, s14, s16
	s_addc_u32 s13, s17, 0
	s_add_u32 s5, s5, s12
	s_addc_u32 s12, 0, s13
	v_add_co_u32 v1, s5, v1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s5, 0
	s_addc_u32 s4, s4, s12
	v_readfirstlane_b32 s5, v1
	s_mul_i32 s12, s6, s4
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s13, s6, s5
	s_mul_i32 s9, s9, s5
	s_add_i32 s12, s13, s12
	s_mul_i32 s6, s6, s5
	s_add_i32 s12, s12, s9
	s_mul_hi_u32 s13, s4, s6
	s_mul_i32 s14, s4, s6
	s_mul_hi_u32 s6, s5, s6
	s_mul_hi_u32 s15, s5, s12
	s_mul_i32 s5, s5, s12
	s_mul_hi_u32 s9, s4, s12
	s_add_u32 s5, s6, s5
	s_addc_u32 s6, 0, s15
	s_add_u32 s5, s5, s14
	s_mul_i32 s12, s4, s12
	s_addc_u32 s5, s6, s13
	s_addc_u32 s6, s9, 0
	s_add_u32 s5, s5, s12
	s_addc_u32 s6, 0, s6
	v_add_co_u32 v1, s5, v1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s5, 0
	s_addc_u32 s4, s4, s6
	v_readfirstlane_b32 s5, v1
	s_mul_i32 s9, s2, s4
	s_mul_hi_u32 s6, s2, s4
	s_mul_hi_u32 s12, s7, s4
	s_mul_i32 s4, s7, s4
	s_mul_hi_u32 s13, s2, s5
	s_mul_hi_u32 s14, s7, s5
	s_mul_i32 s5, s7, s5
	s_add_u32 s9, s13, s9
	s_addc_u32 s6, 0, s6
	s_add_u32 s5, s9, s5
	s_addc_u32 s5, s6, s14
	s_addc_u32 s6, s12, 0
	s_add_u32 s4, s5, s4
	s_addc_u32 s5, 0, s6
	s_mul_hi_u32 s6, s10, s4
	s_mul_i32 s12, s10, s5
	s_mul_i32 s13, s10, s4
	s_add_i32 s6, s6, s12
	v_sub_co_u32 v1, s12, s2, s13
	s_mul_i32 s9, s4, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s6, s6, s9
	v_sub_co_u32 v2, s13, v1, s10
	s_sub_i32 s9, s7, s6
	s_cmp_lg_u32 s12, 0
	s_subb_u32 s9, s9, 0
	s_cmp_lg_u32 s13, 0
	v_readfirstlane_b32 s13, v2
	s_subb_u32 s9, s9, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_ge_u32 s9, 0
	s_cselect_b32 s14, -1, 0
	s_cmp_ge_u32 s13, s10
	s_cselect_b32 s13, -1, 0
	s_cmp_eq_u32 s9, 0
	s_cselect_b32 s9, s13, s14
	s_add_u32 s13, s4, 1
	s_addc_u32 s14, s5, 0
	s_add_u32 s15, s4, 2
	s_addc_u32 s16, s5, 0
	s_cmp_lg_u32 s9, 0
	s_cselect_b32 s9, s15, s13
	s_cselect_b32 s13, s16, s14
	s_cmp_lg_u32 s12, 0
	v_readfirstlane_b32 s12, v1
	v_mov_b32_e32 v1, 0
	s_subb_u32 s6, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s6, 0
	s_cselect_b32 s14, -1, 0
	s_cmp_ge_u32 s12, s10
	s_cselect_b32 s12, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s6, s12, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s6, 0
	s_cselect_b32 s12, s9, s4
	s_cselect_b32 s13, s13, s5
	s_mul_i32 s4, s12, 0
	s_mul_hi_u32 s5, s12, s10
	s_mul_i32 s6, s13, s10
	s_add_i32 s4, s5, s4
	s_mul_i32 s5, s12, s10
	s_add_i32 s4, s4, s6
	s_sub_u32 s6, s2, s5
	s_subb_u32 s7, s7, s4
	s_mov_b32 s9, 0
	s_cmp_lg_u64 s[6:7], 0
	s_mul_i32 s14, s13, s8
	s_cselect_b32 s2, -1, 0
	s_add_u32 s4, s10, -1
	s_addc_u32 s5, 0, -1
	s_mul_hi_u32 s15, s12, s8
	s_cmp_eq_u64 s[4:5], s[8:9]
	s_cselect_b32 s4, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s2, s4
	s_mov_b32 s2, -1
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_mul_i32 s4, s12, s8
	s_cbranch_vccz .LBB0_2
; %bb.1:
	v_fmamk_f32 v2, 0, 0x4f800000, v8
	s_add_i32 s5, s15, s14
	s_sub_u32 s17, 0, s11
	s_subb_u32 s18, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x5f7ffffc, v2
	v_mul_f32_e32 v3, 0x2f800000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v3, v3
	v_fmac_f32_e32 v2, 0xcf800000, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v2, v2
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s16, v2
	s_mul_i32 s19, s17, s2
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s21, s17, s16
	s_mul_i32 s20, s18, s16
	s_add_i32 s19, s21, s19
	s_mul_i32 s22, s17, s16
	s_add_i32 s19, s19, s20
	s_mul_hi_u32 s21, s16, s22
	s_mul_hi_u32 s23, s2, s22
	s_mul_i32 s20, s2, s22
	s_mul_hi_u32 s22, s16, s19
	s_mul_i32 s16, s16, s19
	s_mul_hi_u32 s24, s2, s19
	s_add_u32 s16, s21, s16
	s_addc_u32 s21, 0, s22
	s_add_u32 s16, s16, s20
	s_mul_i32 s19, s2, s19
	s_addc_u32 s16, s21, s23
	s_addc_u32 s20, s24, 0
	s_add_u32 s16, s16, s19
	s_addc_u32 s19, 0, s20
	v_add_co_u32 v2, s16, v2, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s16, 0
	s_addc_u32 s2, s2, s19
	v_readfirstlane_b32 s16, v2
	s_mul_i32 s19, s17, s2
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s20, s17, s16
	s_mul_i32 s18, s18, s16
	s_add_i32 s19, s20, s19
	s_mul_i32 s17, s17, s16
	s_add_i32 s19, s19, s18
	s_mul_hi_u32 s20, s2, s17
	s_mul_i32 s21, s2, s17
	s_mul_hi_u32 s17, s16, s17
	s_mul_hi_u32 s22, s16, s19
	s_mul_i32 s16, s16, s19
	s_mul_hi_u32 s18, s2, s19
	s_add_u32 s16, s17, s16
	s_addc_u32 s17, 0, s22
	s_add_u32 s16, s16, s21
	s_mul_i32 s19, s2, s19
	s_addc_u32 s16, s17, s20
	s_addc_u32 s17, s18, 0
	s_add_u32 s16, s16, s19
	s_addc_u32 s17, 0, s17
	v_add_co_u32 v2, s16, v2, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s16, 0
	s_addc_u32 s2, s2, s17
	v_readfirstlane_b32 s16, v2
	s_mul_i32 s18, s12, s2
	s_mul_hi_u32 s17, s12, s2
	s_mul_hi_u32 s19, s13, s2
	s_mul_i32 s2, s13, s2
	s_mul_hi_u32 s20, s12, s16
	s_mul_hi_u32 s21, s13, s16
	s_mul_i32 s16, s13, s16
	s_add_u32 s18, s20, s18
	s_addc_u32 s17, 0, s17
	s_add_u32 s16, s18, s16
	s_addc_u32 s16, s17, s21
	s_addc_u32 s17, s19, 0
	s_add_u32 s16, s16, s2
	s_addc_u32 s17, 0, s17
	s_mul_i32 s19, s11, s16
	s_add_u32 s18, s16, 1
	v_sub_co_u32 v2, s19, s12, s19
	s_mul_hi_u32 s2, s11, s16
	s_addc_u32 s20, s17, 0
	s_mul_i32 s21, s11, s17
	s_add_u32 s22, s16, 2
	s_addc_u32 s23, s17, 0
	s_add_i32 s2, s2, s21
	s_cmp_lg_u32 s19, 0
	v_sub_co_u32 v3, s19, v2, s11
	s_subb_u32 s2, s13, s2
	s_cmp_lg_u32 s19, 0
	v_mov_b32_e32 v4, s22
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	s_subb_u32 s19, s2, 0
	v_mov_b32_e32 v5, s23
	s_cmp_eq_u32 s19, 0
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, -1, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v2
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, -1, v2, s2
	v_cndmask_b32_e32 v3, s18, v4, vcc_lo
	v_cndmask_b32_e32 v4, s20, v5, vcc_lo
	s_mov_b32 s2, s9
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, s16, v3, vcc_lo
	v_cndmask_b32_e32 v6, s17, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, v0, s[4:5]
	v_mad_u64_u32 v[4:5], null, v6, v0, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v3, v4
	v_add_co_u32 v4, vcc_lo, v2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v3, v6, vcc_lo
	s_branch .LBB0_3
.LBB0_2:
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_3:                                ; %Flow135
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_5
; %bb.4:
	v_fmamk_f32 v2, 0, 0x4f800000, v8
	s_add_u32 s12, s12, s6
	s_addc_u32 s13, s13, s7
	s_add_i32 s5, s15, s14
	s_sub_u32 s7, 0, s11
	v_rcp_f32_e32 v2, v2
	s_subb_u32 s9, 0, 0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x5f7ffffc, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x2f800000, v2
	v_trunc_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v2, v3, 0xcf800000, v2
	v_cvt_u32_f32_e32 v3, v3
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v3
	v_readfirstlane_b32 s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s14, s7, s2
	s_mul_hi_u32 s16, s7, s6
	s_mul_i32 s15, s9, s6
	s_add_i32 s14, s16, s14
	s_mul_i32 s17, s7, s6
	s_add_i32 s14, s14, s15
	s_mul_hi_u32 s16, s6, s17
	s_mul_hi_u32 s18, s2, s17
	s_mul_i32 s15, s2, s17
	s_mul_hi_u32 s17, s6, s14
	s_mul_i32 s6, s6, s14
	s_mul_hi_u32 s19, s2, s14
	s_add_u32 s6, s16, s6
	s_addc_u32 s16, 0, s17
	s_add_u32 s6, s6, s15
	s_mul_i32 s14, s2, s14
	s_addc_u32 s6, s16, s18
	s_addc_u32 s15, s19, 0
	s_add_u32 s6, s6, s14
	s_addc_u32 s14, 0, s15
	v_add_co_u32 v2, s6, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s6, 0
	s_addc_u32 s2, s2, s14
	v_readfirstlane_b32 s6, v2
	s_mul_i32 s14, s7, s2
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s15, s7, s6
	s_mul_i32 s9, s9, s6
	s_add_i32 s14, s15, s14
	s_mul_i32 s7, s7, s6
	s_add_i32 s14, s14, s9
	s_mul_hi_u32 s15, s2, s7
	s_mul_i32 s16, s2, s7
	s_mul_hi_u32 s7, s6, s7
	s_mul_hi_u32 s17, s6, s14
	s_mul_i32 s6, s6, s14
	s_mul_hi_u32 s9, s2, s14
	s_add_u32 s6, s7, s6
	s_addc_u32 s7, 0, s17
	s_add_u32 s6, s6, s16
	s_mul_i32 s14, s2, s14
	s_addc_u32 s6, s7, s15
	s_addc_u32 s7, s9, 0
	s_add_u32 s6, s6, s14
	s_addc_u32 s7, 0, s7
	v_add_co_u32 v2, s6, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s6, 0
	s_addc_u32 s2, s2, s7
	v_readfirstlane_b32 s6, v2
	s_mul_i32 s9, s12, s2
	s_mul_hi_u32 s7, s12, s2
	s_mul_hi_u32 s14, s13, s2
	s_mul_i32 s2, s13, s2
	s_mul_hi_u32 s15, s12, s6
	s_mul_hi_u32 s16, s13, s6
	s_mul_i32 s6, s13, s6
	s_add_u32 s9, s15, s9
	s_addc_u32 s7, 0, s7
	s_add_u32 s6, s9, s6
	s_addc_u32 s6, s7, s16
	s_addc_u32 s7, s14, 0
	s_add_u32 s6, s6, s2
	s_addc_u32 s7, 0, s7
	s_mul_i32 s14, s11, s6
	s_add_u32 s9, s6, 1
	v_sub_co_u32 v2, s14, s12, s14
	s_mul_hi_u32 s2, s11, s6
	s_addc_u32 s15, s7, 0
	s_mul_i32 s16, s11, s7
	s_add_u32 s17, s6, 2
	s_addc_u32 s18, s7, 0
	s_add_i32 s2, s2, s16
	s_cmp_lg_u32 s14, 0
	v_sub_co_u32 v3, s14, v2, s11
	s_subb_u32 s2, s13, s2
	s_cmp_lg_u32 s14, 0
	v_mov_b32_e32 v4, s17
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	s_subb_u32 s14, s2, 0
	v_mov_b32_e32 v5, s18
	s_cmp_eq_u32 s14, 0
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, -1, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v2
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, -1, v2, s2
	v_cndmask_b32_e32 v3, s9, v4, vcc_lo
	v_cndmask_b32_e32 v4, s15, v5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, s6, v3, vcc_lo
	v_cndmask_b32_e32 v6, s7, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, v0, s[4:5]
	v_mad_u64_u32 v[4:5], null, v6, v0, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v3, v4
	v_add_co_u32 v4, vcc_lo, v2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v3, v6, vcc_lo
.LBB0_5:
	v_fmamk_f32 v6, 0, 0x4f800000, v8
	s_sub_u32 s2, 0, s11
	s_subb_u32 s4, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x5f7ffffc, v6
	v_mul_f32_e32 v7, 0x2f800000, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v7, v7
	v_fmamk_f32 v6, v7, 0xcf800000, v6
	v_cvt_u32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v6, v6
	v_mul_lo_u32 v9, s2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, s2, v6
	v_mul_lo_u32 v11, s4, v6
	v_add_nc_u32_e32 v9, v10, v9
	v_mul_lo_u32 v10, s2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v11
	v_mul_hi_u32 v11, v6, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v12, v6, v9
	v_mul_hi_u32 v13, v6, v9
	v_mul_hi_u32 v14, v7, v10
	v_mul_lo_u32 v10, v7, v10
	v_mul_hi_u32 v15, v7, v9
	v_mul_lo_u32 v9, v7, v9
	v_add_co_u32 v11, vcc_lo, v11, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v11, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, s2, v6
	v_mul_lo_u32 v11, s4, v6
	v_mul_lo_u32 v10, s2, v7
	s_add_u32 s4, s11, -1
	s_addc_u32 s5, 0, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v10
	v_mul_lo_u32 v10, s2, v6
	v_add_nc_u32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v6, v10
	v_mul_lo_u32 v12, v6, v9
	v_mul_hi_u32 v13, v6, v9
	v_mul_hi_u32 v14, v7, v10
	v_mul_lo_u32 v10, v7, v10
	v_mul_hi_u32 v15, v7, v9
	v_mul_lo_u32 v9, v7, v9
	v_add_co_u32 v11, vcc_lo, v11, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v11, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, s12, v6
	v_mul_hi_u32 v12, s13, v6
	v_mul_lo_u32 v10, s12, v7
	v_mul_hi_u32 v11, s12, v7
	v_mul_lo_u32 v6, s13, v6
	v_mul_hi_u32 v13, s13, v7
	v_mul_lo_u32 v7, s13, v7
	v_add_co_u32 v9, vcc_lo, v9, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v9, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v12, vcc_lo
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, s11, v6
	v_mul_lo_u32 v6, s11, v6
	v_mul_lo_u32 v7, s11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v6, vcc_lo, s12, v6
	v_add_nc_u32_e32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
	v_sub_co_u32 v9, vcc_lo, v6, s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v9
	v_cmp_eq_u32_e64 s2, 0, v7
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v6
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, -1, v11, vcc_lo
	v_sub_co_u32 v13, vcc_lo, v9, s11
	v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v11
	v_cndmask_b32_e64 v11, -1, v12, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v10, v14 :: v_dual_cndmask_b32 v9, v9, v13
	v_cmp_ne_u32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, v7, v10 :: v_dual_cndmask_b32 v6, v6, v9
	v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s1, exec_lo
	v_cmp_ne_u64_e64 s2, 0, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, s2, vcc_lo
	s_mov_b32 s2, 0
	v_dual_cndmask_b32 v6, 0, v6 :: v_dual_cndmask_b32 v1, 0, v7
	v_add_co_u32 v4, vcc_lo, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v1, vcc_lo
	v_cmpx_lt_u64_e64 v[2:3], v[4:5]
	s_cbranch_execz .LBB0_8
; %bb.6:                                ; %.lr.ph.preheader
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_mov_b32_e32 v1, 1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
.LBB0_7:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v9, v[6:7], off
	v_add_co_u32 v6, s0, v6, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	global_atomic_add_u32 v[9:10], v1, off
	v_cmp_ge_u64_e32 vcc_lo, v[2:3], v[4:5]
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_7
.LBB0_8:                                ; %Flow134
	s_or_b32 exec_lo, exec_lo, s1
	v_or_b32_e32 v1, s8, v0
	s_cmp_gt_i32 s3, 1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_cselect_b32 s0, -1, 0
	s_barrier
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	buffer_gl0_inv
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_11
; %bb.9:                                ; %.lr.ph98.preheader
	v_mov_b32_e32 v1, 0
	s_add_i32 s9, s3, -1
	s_add_u32 s0, s6, 4
	s_addc_u32 s1, s7, 0
	global_load_b32 v2, v1, s[6:7]
.LBB0_10:                               ; %.lr.ph98
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v3, v1, s[0:1]
	s_add_i32 s9, s9, -1
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v1, v2, s[0:1]
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s9, 0
	s_cbranch_scc1 .LBB0_10
.LBB0_11:                               ; %Flow132
	s_or_b32 exec_lo, exec_lo, s2
	v_cvt_f32_u32_e32 v1, s10
	v_rcp_iflag_f32_e32 v2, v8
	s_sub_i32 s1, 0, s10
	s_waitcnt_vscnt null, 0x0
	s_barrier
	v_rcp_iflag_f32_e32 v1, v1
	buffer_gl0_inv
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s0, v1
	v_mul_f32_e32 v1, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s1, s1, s0
	v_cvt_u32_f32_e32 v1, v1
	s_mul_hi_u32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s0, s0, s1
	v_readfirstlane_b32 s6, v1
	s_mul_hi_u32 s0, s3, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s0, s10
	s_add_i32 s2, s0, 1
	s_sub_i32 s1, s3, s1
	s_sub_i32 s3, s1, s10
	s_cmp_ge_u32 s1, s10
	s_cselect_b32 s0, s2, s0
	s_cselect_b32 s1, s3, s1
	s_add_i32 s2, s0, 1
	s_cmp_ge_u32 s1, s10
	s_cselect_b32 s0, s2, s0
	s_sub_i32 s1, 0, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s6
	s_mul_hi_u32 s1, s6, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s6, s1
	s_mul_hi_u32 s2, s0, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s1, s2, s11
	s_add_i32 s6, s2, 1
	s_sub_i32 s3, s0, s1
	s_mul_hi_u32 s1, s0, s8
	s_sub_i32 s7, s3, s11
	s_cmp_ge_u32 s3, s11
	s_mul_i32 s0, s0, s8
	s_cselect_b32 s2, s6, s2
	s_cselect_b32 s3, s7, s3
	s_add_i32 s6, s2, 1
	s_cmp_ge_u32 s3, s11
	s_cselect_b32 s2, s6, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, v0, s[0:1]
	s_mov_b32 s1, 0
	v_add_co_u32 v3, vcc_lo, v1, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_u64_e64 v[1:2], v[3:4]
	s_cbranch_execz .LBB0_14
; %bb.12:                               ; %.lr.ph101.preheader
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
.LBB0_13:                               ; %.lr.ph101
                                        ; =>This Inner Loop Header: Depth=1
	global_store_b32 v[5:6], v1, off
	v_add_co_u32 v1, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	v_add_co_u32 v5, s0, v5, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
	v_cmp_ge_u64_e32 vcc_lo, v[1:2], v[3:4]
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_13
.LBB0_14:                               ; %Flow130
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9CountSortPiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9CountSortPiS_ii, .Lfunc_end0-_Z9CountSortPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3248
; NumSgprs: 27
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9CountSortPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     27
    .sgpr_spill_count: 0
    .symbol:         _Z9CountSortPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
