#include <iostream>
#include <math.h>

//Solves the wave equation

const int xDim = 101; //Width
const int yDim = 101; //Height

const double x_s = 0.0;
const double x_f = 1.0;
const double y_s = 0.0;
const double y_f = 1.0;

const double dt = 0.001;

const double D = 1.0;
const int save_frame = 20;


__device__
double u_(int x_off, int y_off, int index, int xpos, int ypos, double *Grid) //x_set is x_offset
{
    //Cannot be on edge boundary
    int xfind = xpos+x_off;
    int yfind = ypos+y_off;
    return Grid[yfind*xDim + xfind];
        
}

__device__
double next_val(double *Grid1, double *Grid2, double *Grid3, int index)
{
    int xpos = index % xDim;
    int ypos = index / xDim;    
    
    double dx = 1.0/double(xDim-1);
    double dy = 1.0/double(yDim-1);
    

    //Check if on boundary and set to BC condition 0
    
    if (((xpos == 0) || (xpos == xDim-1)) || ((ypos == 0) || (ypos == yDim-1)))
    {
        return 0.0 ;   
    }
    
    //Calculate return val
    double u_E = u_(1,0, index, xpos, ypos, Grid2);
    double u_W = u_(-1,0, index, xpos, ypos, Grid2);
    double u_O = u_(0,0, index, xpos, ypos, Grid2);
    double u_N = u_(0,1, index, xpos, ypos, Grid2);
    double u_S = u_(0,-1, index, xpos, ypos, Grid2);
    
    double u_D = Grid3[index];
    

    double u_xx = D*(u_E-2*u_O+u_W)/(dx*dx); 
    double u_yy = D*(u_N-2*u_O+u_S)/(dy*dy);
    double u_tt = u_xx + u_yy;
    
    return dt*dt*u_tt + 2*u_O - u_D;
    
}


//Function to run on GPU
__global__
void calc_next(double *Grid1, double *Grid2, double *Grid3)
{
    
    int index = blockIdx.x*blockDim.x+threadIdx.x;
    int stride = blockDim.x*gridDim.x; //Get number of threads in block
    

    
    //Run over all elements
    //Use Grid2 and Grid3 to render to Grid1

    for (int i = index; i < xDim*yDim; i+=stride)
    {
        Grid1[i] = next_val(Grid1, Grid2, Grid3, i);
    }
}

double ic_pos(double x,double y)
{
    return x*y;
}

double ic_vel(double x,double y)
{
    return 0.0;
}

int main()
{
  double *Grid1, *Grid2, *Grid3;

  // Allocate Unified Memory accessible from CPU or GPU
  cudaMallocManaged(&Grid1, xDim*yDim*sizeof(double));
  cudaMallocManaged(&Grid2, xDim*yDim*sizeof(double));
  cudaMallocManaged(&Grid3, xDim*yDim*sizeof(double));

  //Initialise initial conditions on host
  double x;
  double y;
  
  //Set Grid2 and Grid3
  for (int y_i = 0; y_i < yDim; y_i++){
    for (int x_i = 0; x_i < xDim; x_i++)
    {
        int index = y_i*xDim + x_i;
        x = (double(x_i)/(double(xDim-1)))*(x_f-x_s) + x_s;
        y = (double(y_i)/(double(yDim-1)))*(y_f-y_s) + y_s;
        Grid3[index] = ic_pos(x,y);
        Grid2[index] = ic_pos(x,y) + dt*ic_vel(x,y);        
    }  
  }
  
  
  for (int j = 0; j < 8000; j++)
  {
  calc_next<<<30,100>>>(Grid1, Grid2, Grid3);
  
  // Wait for GPU to finish before accessing on host
  cudaDeviceSynchronize();
  
  //Save frame if multiple of save number
  if (j%save_frame==0){
      for (int i = 0; i < xDim*yDim; i++ )
        {
            std::cout<<Grid1[i]<<'\n';
        }
  }
  
  //Swap Grids don't need info in Grid3 anymore
  double * swap = Grid3; 
  
  Grid3 = Grid2;
  Grid2 = Grid1;
  Grid1 = swap;
  

  
  }

  return 0;
}
	.file	"tmpxft_002aee06_00000000-6_PDE_Solver.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3642:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3642:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z2u_iiiiiPd
	.type	_Z2u_iiiiiPd, @function
_Z2u_iiiiiPd:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z2u_iiiiiPd, .-_Z2u_iiiiiPd
	.globl	_Z8next_valPdS_S_i
	.type	_Z8next_valPdS_S_i, @function
_Z8next_valPdS_S_i:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3636:
	.size	_Z8next_valPdS_S_i, .-_Z8next_valPdS_S_i
	.globl	_Z6ic_posdd
	.type	_Z6ic_posdd, @function
_Z6ic_posdd:
.LFB3637:
	.cfi_startproc
	endbr64
	mulsd	%xmm1, %xmm0
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z6ic_posdd, .-_Z6ic_posdd
	.globl	_Z6ic_veldd
	.type	_Z6ic_veldd, @function
_Z6ic_veldd:
.LFB3638:
	.cfi_startproc
	endbr64
	xorps	%xmm0, %xmm0
	ret
	.cfi_endproc
.LFE3638:
	.size	_Z6ic_veldd, .-_Z6ic_veldd
	.globl	_Z32__device_stub__Z9calc_nextPdS_S_PdS_S_
	.type	_Z32__device_stub__Z9calc_nextPdS_S_PdS_S_, @function
_Z32__device_stub__Z9calc_nextPdS_S_PdS_S_:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9calc_nextPdS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z32__device_stub__Z9calc_nextPdS_S_PdS_S_, .-_Z32__device_stub__Z9calc_nextPdS_S_PdS_S_
	.globl	_Z9calc_nextPdS_S_
	.type	_Z9calc_nextPdS_S_, @function
_Z9calc_nextPdS_S_:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9calc_nextPdS_S_PdS_S_
	.cfi_endproc
.LFE3665:
	.size	_Z9calc_nextPdS_S_, .-_Z9calc_nextPdS_S_
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$1, %edx
	movl	$81608, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$81608, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$81608, %esi
	movl	$1, %edx
	call	cudaMallocManaged@PLT
	movq	24(%rsp), %rsi
	xorl	%eax, %eax
	xorps	%xmm2, %xmm2
	movq	16(%rsp), %rdi
	movsd	.LC1(%rip), %xmm3
.L15:
	cvtsi2sdl	%eax, %xmm1
	xorl	%edx, %edx
	imulq	$808, %rax, %rcx
	divsd	%xmm3, %xmm1
	addsd	%xmm2, %xmm1
.L16:
	cvtsi2sdl	%edx, %xmm0
	incl	%edx
	divsd	%xmm3, %xmm0
	addsd	%xmm2, %xmm0
	mulsd	%xmm1, %xmm0
	movsd	%xmm0, (%rsi,%rcx)
	addsd	%xmm2, %xmm0
	movsd	%xmm0, (%rdi,%rcx)
	addq	$8, %rcx
	cmpl	$101, %edx
	jne	.L16
	incq	%rax
	cmpq	$101, %rax
	jne	.L15
	movabsq	$4294967396, %r12
	xorl	%ebx, %ebx
.L17:
	movl	$2147483663, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	addq	%rdi, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%r12, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z32__device_stub__Z9calc_nextPdS_S_PdS_S_
.L18:
	call	cudaDeviceSynchronize@PLT
	movl	%ebx, %eax
	movl	$20, %ecx
	cltd
	idivl	%ecx
	testl	%edx, %edx
	jne	.L19
	xorl	%ebp, %ebp
	leaq	_ZSt4cout(%rip), %r13
.L22:
	movq	8(%rsp), %rax
	movq	%r13, %rdi
	movsd	(%rax,%rbp), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movb	$10, 44(%rsp)
	movq	%rax, %rdi
	movq	(%rax), %rax
	movq	-24(%rax), %rax
	cmpq	$0, 16(%rdi,%rax)
	je	.L20
	leaq	44(%rsp), %rsi
	movl	$1, %edx
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	jmp	.L21
.L20:
	movl	$10, %esi
	call	_ZNSo3putEc@PLT
.L21:
	addq	$8, %rbp
	cmpq	$81608, %rbp
	jne	.L22
.L19:
	movq	16(%rsp), %rdx
	movq	24(%rsp), %rax
	incl	%ebx
	movq	%rdx, 24(%rsp)
	movq	8(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	%rdx, 16(%rsp)
	cmpl	$8000, %ebx
	jne	.L17
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3639:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_Z9calc_nextPdS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3667:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9calc_nextPdS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3667:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1079574528
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>

//Solves the wave equation

const int xDim = 101; //Width
const int yDim = 101; //Height

const double x_s = 0.0;
const double x_f = 1.0;
const double y_s = 0.0;
const double y_f = 1.0;

const double dt = 0.001;

const double D = 1.0;
const int save_frame = 20;


__device__
double u_(int x_off, int y_off, int index, int xpos, int ypos, double *Grid) //x_set is x_offset
{
    //Cannot be on edge boundary
    int xfind = xpos+x_off;
    int yfind = ypos+y_off;
    return Grid[yfind*xDim + xfind];
        
}

__device__
double next_val(double *Grid1, double *Grid2, double *Grid3, int index)
{
    int xpos = index % xDim;
    int ypos = index / xDim;    
    
    double dx = 1.0/double(xDim-1);
    double dy = 1.0/double(yDim-1);
    

    //Check if on boundary and set to BC condition 0
    
    if (((xpos == 0) || (xpos == xDim-1)) || ((ypos == 0) || (ypos == yDim-1)))
    {
        return 0.0 ;   
    }
    
    //Calculate return val
    double u_E = u_(1,0, index, xpos, ypos, Grid2);
    double u_W = u_(-1,0, index, xpos, ypos, Grid2);
    double u_O = u_(0,0, index, xpos, ypos, Grid2);
    double u_N = u_(0,1, index, xpos, ypos, Grid2);
    double u_S = u_(0,-1, index, xpos, ypos, Grid2);
    
    double u_D = Grid3[index];
    

    double u_xx = D*(u_E-2*u_O+u_W)/(dx*dx); 
    double u_yy = D*(u_N-2*u_O+u_S)/(dy*dy);
    double u_tt = u_xx + u_yy;
    
    return dt*dt*u_tt + 2*u_O - u_D;
    
}


//Function to run on GPU
__global__
void calc_next(double *Grid1, double *Grid2, double *Grid3)
{
    
    int index = blockIdx.x*blockDim.x+threadIdx.x;
    int stride = blockDim.x*gridDim.x; //Get number of threads in block
    

    
    //Run over all elements
    //Use Grid2 and Grid3 to render to Grid1

    for (int i = index; i < xDim*yDim; i+=stride)
    {
        Grid1[i] = next_val(Grid1, Grid2, Grid3, i);
    }
}

double ic_pos(double x,double y)
{
    return x*y;
}

double ic_vel(double x,double y)
{
    return 0.0;
}

int main()
{
  double *Grid1, *Grid2, *Grid3;

  // Allocate Unified Memory accessible from CPU or GPU
  hipMallocManaged(&Grid1, xDim*yDim*sizeof(double));
  hipMallocManaged(&Grid2, xDim*yDim*sizeof(double));
  hipMallocManaged(&Grid3, xDim*yDim*sizeof(double));

  //Initialise initial conditions on host
  double x;
  double y;
  
  //Set Grid2 and Grid3
  for (int y_i = 0; y_i < yDim; y_i++){
    for (int x_i = 0; x_i < xDim; x_i++)
    {
        int index = y_i*xDim + x_i;
        x = (double(x_i)/(double(xDim-1)))*(x_f-x_s) + x_s;
        y = (double(y_i)/(double(yDim-1)))*(y_f-y_s) + y_s;
        Grid3[index] = ic_pos(x,y);
        Grid2[index] = ic_pos(x,y) + dt*ic_vel(x,y);        
    }  
  }
  
  
  for (int j = 0; j < 8000; j++)
  {
  calc_next<<<30,100>>>(Grid1, Grid2, Grid3);
  
  // Wait for GPU to finish before accessing on host
  hipDeviceSynchronize();
  
  //Save frame if multiple of save number
  if (j%save_frame==0){
      for (int i = 0; i < xDim*yDim; i++ )
        {
            std::cout<<Grid1[i]<<'\n';
        }
  }
  
  //Swap Grids don't need info in Grid3 anymore
  double * swap = Grid3; 
  
  Grid3 = Grid2;
  Grid2 = Grid1;
  Grid1 = swap;
  

  
  }

  return 0;
}
	.text
	.file	"PDE_Solver.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z24__device_stub__calc_nextPdS_S_ # -- Begin function _Z24__device_stub__calc_nextPdS_S_
	.type	_Z24__device_stub__calc_nextPdS_S_,@function
_Z24__device_stub__calc_nextPdS_S_:     # @_Z24__device_stub__calc_nextPdS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9calc_nextPdS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__calc_nextPdS_S_, .Lfunc_end0-_Z24__device_stub__calc_nextPdS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z6ic_posdd                     # -- Begin function _Z6ic_posdd
	.type	_Z6ic_posdd,@function
_Z6ic_posdd:                            # @_Z6ic_posdd
	.cfi_startproc
# %bb.0:
	mulsd	%xmm1, %xmm0
	retq
.Lfunc_end1:
	.size	_Z6ic_posdd, .Lfunc_end1-_Z6ic_posdd
	.cfi_endproc
                                        # -- End function
	.globl	_Z6ic_veldd                     # -- Begin function _Z6ic_veldd
	.type	_Z6ic_veldd,@function
_Z6ic_veldd:                            # @_Z6ic_veldd
	.cfi_startproc
# %bb.0:
	xorps	%xmm0, %xmm0
	retq
.Lfunc_end2:
	.size	_Z6ic_veldd, .Lfunc_end2-_Z6ic_veldd
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0x4059000000000000              # double 100
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	8(%rsp), %rdi
	movl	$81608, %esi                    # imm = 0x13EC8
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	24(%rsp), %rbx
	movl	$81608, %esi                    # imm = 0x13EC8
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %r14
	movl	$81608, %esi                    # imm = 0x13EC8
	movq	%r14, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%r14), %rax
	xorl	%ecx, %ecx
	movq	(%rbx), %rdx
	movsd	.LCPI3_0(%rip), %xmm0           # xmm0 = mem[0],zero
	xorpd	%xmm1, %xmm1
	movl	$808, %esi                      # imm = 0x328
.LBB3_1:                                # %.preheader32
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	xorps	%xmm2, %xmm2
	cvtsi2sd	%ecx, %xmm2
	divsd	%xmm0, %xmm2
	addsd	%xmm1, %xmm2
	xorl	%edi, %edi
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm3, %xmm3
	cvtsi2sd	%edi, %xmm3
	divsd	%xmm0, %xmm3
	addsd	%xmm1, %xmm3
	mulsd	%xmm2, %xmm3
	movsd	%xmm3, (%rax,%rdi,8)
	addsd	%xmm1, %xmm3
	movsd	%xmm3, (%rdx,%rdi,8)
	incq	%rdi
	cmpq	$101, %rdi
	jne	.LBB3_2
# %bb.3:                                #   in Loop: Header=BB3_1 Depth=1
	incq	%rcx
	addq	%rsi, %rdx
	addq	%rsi, %rax
	cmpq	$101, %rcx
	jne	.LBB3_1
# %bb.4:                                # %.preheader31.preheader
	xorl	%r12d, %r12d
	movabsq	$4294967326, %rbx               # imm = 0x10000001E
	leaq	70(%rbx), %r14
	leaq	7(%rsp), %r15
.LBB3_5:                                # %.preheader31
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_9 Depth 2
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_7
# %bb.6:                                #   in Loop: Header=BB3_5 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	callq	_Z24__device_stub__calc_nextPdS_S_
.LBB3_7:                                #   in Loop: Header=BB3_5 Depth=1
	callq	hipDeviceSynchronize
	imull	$-13107, %r12d, %eax            # imm = 0xCCCD
	rorw	$2, %ax
	movzwl	%ax, %eax
	cmpl	$3276, %eax                     # imm = 0xCCC
	ja	.LBB3_13
# %bb.8:                                # %.preheader.preheader
                                        #   in Loop: Header=BB3_5 Depth=1
	xorl	%r13d, %r13d
.LBB3_9:                                # %.preheader
                                        #   Parent Loop BB3_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	8(%rsp), %rax
	movsd	(%rax,%r13,8), %xmm0            # xmm0 = mem[0],zero
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movb	$10, 7(%rsp)
	movq	(%rax), %rcx
	movq	-24(%rcx), %rcx
	cmpq	$0, 16(%rax,%rcx)
	je	.LBB3_11
# %bb.10:                               #   in Loop: Header=BB3_9 Depth=2
	movl	$1, %edx
	movq	%rax, %rdi
	movq	%r15, %rsi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB3_12
.LBB3_11:                               #   in Loop: Header=BB3_9 Depth=2
	movq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNSo3putEc
.LBB3_12:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
                                        #   in Loop: Header=BB3_9 Depth=2
	incq	%r13
	cmpq	$10201, %r13                    # imm = 0x27D9
	jne	.LBB3_9
.LBB3_13:                               # %.loopexit
                                        #   in Loop: Header=BB3_5 Depth=1
	movq	16(%rsp), %rax
	movq	24(%rsp), %rcx
	movq	%rcx, 16(%rsp)
	movq	8(%rsp), %rcx
	movq	%rcx, 24(%rsp)
	movq	%rax, 8(%rsp)
	incl	%r12d
	cmpl	$8000, %r12d                    # imm = 0x1F40
	jne	.LBB3_5
# %bb.14:
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9calc_nextPdS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9calc_nextPdS_S_,@object      # @_Z9calc_nextPdS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z9calc_nextPdS_S_
	.p2align	3, 0x0
_Z9calc_nextPdS_S_:
	.quad	_Z24__device_stub__calc_nextPdS_S_
	.size	_Z9calc_nextPdS_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9calc_nextPdS_S_"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__calc_nextPdS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9calc_nextPdS_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9calc_nextPdS_S_      ; -- Begin function _Z9calc_nextPdS_S_
	.globl	_Z9calc_nextPdS_S_
	.p2align	8
	.type	_Z9calc_nextPdS_S_,@function
_Z9calc_nextPdS_S_:                     ; @_Z9calc_nextPdS_S_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x24
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s14, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x27d9, v1
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s10, 0xeb1c432d
	s_mov_b32 s12, 0xa0b5ed8d
	s_mov_b32 s11, 0x3f1a36e2
	s_mov_b32 s13, 0x3eb0c6f7
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s15, s14, 31
	s_lshl_b64 s[16:17], s[14:15], 3
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_mul_hi_i32 v0, 0x288df0cb, v1
	v_add_nc_u32_e32 v5, 0xffffd88c, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s2, 0x64, v5
	v_lshrrev_b32_e32 v4, 31, v0
	v_ashrrev_i32_e32 v0, 4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v4
	v_add_nc_u32_e32 v4, 0x64, v1
	v_cmp_lt_u32_e64 s1, 0xc8, v4
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	v_mul_lo_u32 v0, 0x65, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v1, v0
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_cmp_ne_u32_e64 s0, 0x64, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s2, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v8, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
	v_add_nc_u32_e32 v10, -1, v1
	v_add_nc_u32_e32 v12, 0xffffff9b, v1
	s_clause 0x1
	global_load_b128 v[4:7], v[8:9], off
	global_load_b64 v[8:9], v[8:9], off offset:808
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	s_clause 0x1
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[12:13], v[12:13], off
	s_waitcnt vmcnt(3)
	v_fma_f64 v[6:7], v[4:5], -2.0, v[6:7]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[8:9], v[4:5], -2.0, v[8:9]
	v_add_f64 v[4:5], v[4:5], v[4:5]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[10:11], v[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[10:11], null, s[10:11], s[10:11], v[6:7]
	v_div_scale_f64 v[12:13], null, s[10:11], s[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[10:11]
	v_rcp_f64_e32 v[16:17], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	v_add_co_u32 v18, vcc_lo, s8, v2
	v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v3, vcc_lo
	v_div_scale_f64 v[24:25], vcc_lo, v[6:7], s[10:11], v[6:7]
	global_load_b64 v[18:19], v[18:19], off
	v_fma_f64 v[20:21], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[22:23], -v[12:13], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_div_scale_f64 v[20:21], s0, v[8:9], s[10:11], v[8:9]
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[22:23], v[24:25], v[14:15]
	v_mul_f64 v[26:27], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], -v[10:11], v[22:23], v[24:25]
	v_fma_f64 v[12:13], -v[12:13], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[6:7], v[10:11], s[10:11], v[6:7]
	v_div_fixup_f64 v[8:9], v[12:13], s[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_fma_f64 v[4:5], v[6:7], s[12:13], v[4:5]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], -v[18:19]
.LBB0_4:                                ; %_Z8next_valPdS_S_i.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v1, s14, v1
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, 0x27d8, v1
	v_add_co_u32 v2, s0, v2, s16
	v_add_co_ci_u32_e64 v3, s0, s17, v3, s0
	s_or_b32 s3, vcc_lo, s3
	global_store_b64 v[6:7], v[4:5], off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_5:                                ; %Flow28
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9calc_nextPdS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9calc_nextPdS_S_, .Lfunc_end0-_Z9calc_nextPdS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 824
; NumSgprs: 20
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9calc_nextPdS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z9calc_nextPdS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
