#include <iostream>
#include <math.h>
#include <cstdio>

using namespace std;

// Thread block size
const int blockSize = 16;

// Matrices are stored in row-major order:
// M(row, clo) = *(M.elements + row*M.stride + col);
typedef struct {
  int width;
  int height;
  int stride;
  float* elements;
} Matrix;

// Get a matrix element
__device__ float GetElement(const Matrix A, int row, int col) {
  return A.elements[row * A.stride + col];
}

// Set a matrix element
__device__ void SetElement(Matrix A, int row, int col, float value) {
  A.elements[row * A.stride + col] = value;
}

// Get the blockSizexblockSize sub-matrix Asub of A that is
// located col sub-matrices to the right and row sub-matrices down
// from the upper-left corner of A
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) {
  Matrix Asub;
  Asub.width = blockSize;
  Asub.height = blockSize;
  Asub.stride = A.stride;
  Asub.elements = &A.elements[A.stride * blockSize * row + blockSize * col];
  return Asub;
}

// CPU matrix multiplication for evaluating results
void cpu_matrix_multi(float *matA, float *matB, float *matC, int m, int k, int n) {
  for (int i = 0; i < m; i++) {
    for (int j = 0; j < n; j++) {
      float tmp = 0.0;
      for (int l = 0; l < k; l++) {
        tmp += matA[i*k + l] * matB[l*n + j];
      }
      matC[i*n + j] = tmp;
    }
  }
}

// Matrix multiplication kernel called by MatMul()
__global__
void MatMulKernel_SharMem(const Matrix A, const Matrix B, Matrix C) {
  // Block row and col
  int blockRow = blockIdx.y;
  int blockCol = blockIdx.x;

  // Each thread block computes one sub-matrix Csubof C
  Matrix Csub = GetSubMatrix(C, blockRow, blockCol);

  // Each thread computes one element of Csub
  // by accumulating results into Cvalue
  float Cvalue = 0;

  // Thread row and column within Csub
  int row = threadIdx.y;
  int col = threadIdx.x;

  // Loop over all the sub-matrices of A and B that are
  // required to compute Csub
  // Multiply each pair of sub-matrices together 
  // and accumulate results
  for (int m = 0; m < A.width/blockSize; m++) {

    // Get sub-matrix Asub of A
    Matrix Asub = GetSubMatrix(A, blockRow, m);

    // Get sub-matrix Bsub of B
    Matrix Bsub = GetSubMatrix(B, m, blockCol);

    // Shared memory used to store Asub and Bsub respectively
    __shared__ float As[blockSize][blockSize];
    __shared__ float Bs[blockSize][blockSize];

    // Load Asub and Bsub from device memory to shared memory
    // Each thread loads one element of each sub-matrix
    As[row][col] = GetElement(Asub, row, col); 
    Bs[row][col] = GetElement(Bsub, row, col);

    // Synchronize to make sure the sub-matrices are loaded
    // before starting the computation
    __syncthreads();

    // Multiply Asub and Bsub together
    for (int e = 0; e < blockSize; e++)
      Cvalue += As[row][e] * Bs[e][col];

    // Synchronize to make sure that the preceding 
    // computation is done before loading two new
    // sub-matrices of A and B in the next iteration
    __syncthreads();
  }

  // Write Csub to device memory 
  // Each thread write one element
  SetElement(Csub, row, col, Cvalue);
}

// Matrix multiplication - host code
// Matrix dimensions are assumed to be multiples of blockSize
void MatMul(const Matrix A, const Matrix B, Matrix C) {
  // Load A and B to device memory
  Matrix d_A;
  d_A.width = d_A.stride = A.width; d_A.height = A.height;
  size_t size = A.width * A.height * sizeof(float);
  cudaMalloc(&d_A.elements, size);
  cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
  Matrix d_B;
  d_B.width = d_B.stride = B.width; d_B.height = B.width;
  size = B.width * B.height * sizeof(float);
  cudaMalloc(&d_B.elements, size);
  cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);

  // Allocate C in device memory
  Matrix d_C;
  d_C.width = d_C.stride = C.width; d_C.height = C.height;
  size = C.width * C.height * sizeof(float);
  cudaMalloc(&d_C.elements, size);
  
  // Invoke kernel
  dim3 dimBlock(blockSize, blockSize, 1);
  dim3 dimGrid(B.width/dimBlock.x, A.height/dimBlock.y, 1);
  MatMulKernel_SharMem<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);

  // Read C from device
  cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
  cudaThreadSynchronize();

  // Free device memory
  cudaFree(d_A.elements);
  cudaFree(d_B.elements);
  cudaFree(d_C.elements);
}

int main() {
  // Initiate A and B elements on host memory
  Matrix h_A;
  h_A.height = 1024; h_A.width = h_A.stride = 1024;
  float* h_matA = new float[h_A.height * h_A.width];
  std::srand(1103);
  for (int i = 0; i < h_A.height; i++)
    for (int j = 0; j < h_A.width; j++)
      h_matA[i*h_A.width+j] = float(std::rand())/float(RAND_MAX);
  h_A.elements = h_matA;

  Matrix h_B;
  h_B.height = 1024; h_B.width = h_B.stride = 1024;
  float* h_matB = new float[h_B.height * h_B.width];
  for (int i = 0; i < h_B.height; i++)
    for (int j = 0; j < h_B.width; j++)
      h_matB[i*h_B.width+j] = float(std::rand())/float(RAND_MAX);
  h_B.elements = h_matB;

  // Matrix C size
  Matrix h_C;
  h_C.height = h_A.height; h_C.width = h_C.stride = h_B.width;
  float* h_matC = new float[h_A.height * h_B.width];
  h_C.elements = h_matC;

  // Call MatMul()
  MatMul(h_A, h_B, h_C);

  // Evaluate results
  float* h_matC_cpu = new float[h_A.height * h_B.width];
//  cpu_matrix_multi(h_matA, h_matB, h_matC_cpu, h_A.height, h_A.width, h_B.width);
  cpu_matrix_multi(h_A.elements, h_B.elements, h_matC_cpu, h_A.height, h_A.width, h_B.width);
  bool res_flag = false;
  float resol = 0.000001;
  for (int i = 0; i < h_C.height; i++) {
    for (int j = 0; j < h_C.width; j++) {
      if (fabs(*(h_C.elements+i*h_C.width+j) - h_matC[i*h_C.width+j]) > resol)
	res_flag = true;
    }
  }
	
  if (res_flag == false)
    cout << "Matrix multiplication by GPU is right! " << endl;
  else
    cout << "Results are not right! " << endl;

  // Free memory on host 
  delete [] h_matA;
  delete [] h_matB;
  delete [] h_matC;
  delete [] h_matC_cpu;

  return 0;
}


	.file	"tmpxft_00282097_00000000-6_gpucppMatMulSharMem.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3643:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3643:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10GetElement6Matrixii
	.type	_Z10GetElement6Matrixii, @function
_Z10GetElement6Matrixii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z10GetElement6Matrixii, .-_Z10GetElement6Matrixii
	.globl	_Z10SetElement6Matrixiif
	.type	_Z10SetElement6Matrixiif, @function
_Z10SetElement6Matrixiif:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3636:
	.size	_Z10SetElement6Matrixiif, .-_Z10SetElement6Matrixiif
	.globl	_Z12GetSubMatrix6Matrixii
	.type	_Z12GetSubMatrix6Matrixii, @function
_Z12GetSubMatrix6Matrixii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3637:
	.size	_Z12GetSubMatrix6Matrixii, .-_Z12GetSubMatrix6Matrixii
	.globl	_Z16cpu_matrix_multiPfS_S_iii
	.type	_Z16cpu_matrix_multiPfS_S_iii, @function
_Z16cpu_matrix_multiPfS_S_iii:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r10d, %r10d
	xorl	%r11d, %r11d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	xorl	%ecx, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	movq	%rdx, %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%r9d, %rbx
	salq	$2, %rbx
.L9:
	cmpl	%r12d, %r11d
	jge	.L8
	movslq	%r10d, %rax
	leaq	(%rsi,%rax,4), %r15
	movslq	%ecx, %rax
	leaq	(%rdi,%rax,4), %r14
	xorl	%eax, %eax
.L14:
	cmpl	%eax, %r9d
	jle	.L11
	leaq	0(%rbp,%rax,4), %r13
	xorl	%edx, %edx
	xorps	%xmm0, %xmm0
.L12:
	cmpl	%edx, %r8d
	jle	.L17
	movss	(%r14,%rdx,4), %xmm1
	mulss	0(%r13), %xmm1
	incq	%rdx
	addq	%rbx, %r13
	addss	%xmm1, %xmm0
	jmp	.L12
.L17:
	movss	%xmm0, (%r15,%rax,4)
	incq	%rax
	jmp	.L14
.L11:
	incl	%r11d
	addl	%r9d, %r10d
	addl	%r8d, %ecx
	jmp	.L9
.L8:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	_Z16cpu_matrix_multiPfS_S_iii, .-_Z16cpu_matrix_multiPfS_S_iii
	.globl	_Z49__device_stub__Z20MatMulKernel_SharMem6MatrixS_S_RK6MatrixS1_RS_
	.type	_Z49__device_stub__Z20MatMulKernel_SharMem6MatrixS_S_RK6MatrixS1_RS_, @function
_Z49__device_stub__Z20MatMulKernel_SharMem6MatrixS_S_RK6MatrixS1_RS_:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rcx
	movq	%rdi, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rsi, 72(%rsp)
	leaq	16(%rsp), %rdi
	leaq	28(%rsp), %rsi
	movq	%rdx, 80(%rsp)
	movq	%rsp, %rdx
	movq	%rax, 16(%rsp)
	movl	$1, 24(%rsp)
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	8(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z20MatMulKernel_SharMem6MatrixS_S_(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 128
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L18:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z49__device_stub__Z20MatMulKernel_SharMem6MatrixS_S_RK6MatrixS1_RS_, .-_Z49__device_stub__Z20MatMulKernel_SharMem6MatrixS_S_RK6MatrixS1_RS_
	.globl	_Z20MatMulKernel_SharMem6MatrixS_S_
	.type	_Z20MatMulKernel_SharMem6MatrixS_S_, @function
_Z20MatMulKernel_SharMem6MatrixS_S_:
.LFB3666:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	64(%rsp), %rdx
	leaq	40(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	_Z49__device_stub__Z20MatMulKernel_SharMem6MatrixS_S_RK6MatrixS1_RS_
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z20MatMulKernel_SharMem6MatrixS_S_, .-_Z20MatMulKernel_SharMem6MatrixS_S_
	.globl	_Z6MatMul6MatrixS_S_
	.type	_Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	movl	224(%rsp), %edx
	movl	228(%rsp), %r12d
	leaq	40(%rsp), %rdi
	movl	248(%rsp), %r13d
	movl	272(%rsp), %ebx
	movl	%edx, 32(%rsp)
	movl	276(%rsp), %r14d
	movl	%edx, 24(%rsp)
	imull	%r12d, %edx
	movl	%r12d, 28(%rsp)
	shrl	$4, %r12d
	movslq	%edx, %rbp
	salq	$2, %rbp
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	240(%rsp), %rsi
	movq	40(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	64(%rsp), %rdi
	movl	%r13d, 56(%rsp)
	movl	252(%rsp), %ebp
	movl	%r13d, 48(%rsp)
	imull	%r13d, %ebp
	movl	%r13d, 52(%rsp)
	movslq	%ebp, %rbp
	salq	$2, %rbp
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	264(%rsp), %rsi
	movq	64(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%ebx, 80(%rsp)
	leaq	88(%rsp), %rdi
	movl	%ebx, 72(%rsp)
	imull	%r14d, %ebx
	movl	%r14d, 76(%rsp)
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movl	%r13d, %eax
	movl	%r12d, 16(%rsp)
	xorl	%r9d, %r9d
	shrl	$4, %eax
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	%eax, 12(%rsp)
	movq	12(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	40(%rsp), %rax
	movups	24(%rsp), %xmm0
	leaq	144(%rsp), %rdx
	leaq	120(%rsp), %rsi
	movups	48(%rsp), %xmm1
	movups	72(%rsp), %xmm2
	leaq	96(%rsp), %rdi
	movq	%rax, 112(%rsp)
	movq	64(%rsp), %rax
	movups	%xmm0, 96(%rsp)
	movq	%rax, 136(%rsp)
	movq	88(%rsp), %rax
	movups	%xmm1, 120(%rsp)
	movq	%rax, 160(%rsp)
	movups	%xmm2, 144(%rsp)
	call	_Z49__device_stub__Z20MatMulKernel_SharMem6MatrixS_S_RK6MatrixS1_RS_
.L25:
	movq	88(%rsp), %rsi
	movq	288(%rsp), %rdi
	movl	$2, %ecx
	movq	%rbx, %rdx
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$176, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3639:
	.size	_Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"Matrix multiplication by GPU is right! "
.LC5:
	.string	"Results are not right! "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$4194304, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	call	_Znam@PLT
	movl	$1103, %edi
	movq	%rax, %rbp
	call	srand@PLT
.L29:
	movq	%r12, %r13
	xorl	%ebx, %ebx
	salq	$12, %r13
	addq	%rbp, %r13
.L30:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC1(%rip), %xmm0
	movss	%xmm0, 0(%r13,%rbx,4)
	incq	%rbx
	cmpq	$1024, %rbx
	jne	.L30
	incq	%r12
	cmpq	$1024, %r12
	jne	.L29
	movl	$4194304, %edi
	xorl	%r13d, %r13d
	call	_Znam@PLT
	movq	%rax, %rbx
.L32:
	movq	%r13, %r14
	xorl	%r12d, %r12d
	salq	$12, %r14
	addq	%rbx, %r14
.L33:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC1(%rip), %xmm0
	movss	%xmm0, (%r14,%r12,4)
	incq	%r12
	cmpq	$1024, %r12
	jne	.L33
	incq	%r13
	cmpq	$1024, %r13
	jne	.L32
	movl	$4194304, %edi
	call	_Znam@PLT
	movl	$1024, 16(%rsp)
	subq	$80, %rsp
	.cfi_def_cfa_offset 208
	movq	%rax, %r12
	movabsq	$4398046512128, %rax
	movl	$1024, 120(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rax, 112(%rsp)
	movq	%rax, 136(%rsp)
	movl	$1024, 144(%rsp)
	movups	112(%rsp), %xmm3
	movups	136(%rsp), %xmm2
	movups	88(%rsp), %xmm4
	movq	%r12, 64(%rsp)
	movups	%xmm3, 24(%rsp)
	movups	%xmm2, 48(%rsp)
	movups	%xmm4, (%rsp)
	movq	%rbx, 40(%rsp)
	movq	%rbp, 16(%rsp)
	call	_Z6MatMul6MatrixS_S_
	addq	$80, %rsp
	.cfi_def_cfa_offset 128
	movl	$4194304, %edi
	call	_Znam@PLT
	movl	$1024, %ecx
	movq	%rbp, %rdi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	movl	$1024, %r9d
	movl	$1024, %r8d
	movq	%rax, %r13
	call	_Z16cpu_matrix_multiPfS_S_iii
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	movb	$1, %dil
	movss	.LC2(%rip), %xmm1
.L35:
	leaq	(%r12,%rdx,4), %rsi
	xorl	%eax, %eax
.L37:
	movss	(%rsi,%rax,4), %xmm0
	subss	%xmm0, %xmm0
	andps	%xmm1, %xmm0
	ucomiss	.LC3(%rip), %xmm0
	cmova	%edi, %ecx
	incq	%rax
	cmpq	$1024, %rax
	jne	.L37
	addq	$1024, %rdx
	cmpq	$1048576, %rdx
	jne	.L35
	testb	%cl, %cl
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	je	.L46
	leaq	.LC5(%rip), %rsi
.L46:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	%r13, %rdi
	call	_ZdaPv@PLT
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3640:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z20MatMulKernel_SharMem6MatrixS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3668:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z20MatMulKernel_SharMem6MatrixS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3668:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	805306368
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC2:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst4
	.align 4
.LC3:
	.long	897988541
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <cstdio>

using namespace std;

// Thread block size
const int blockSize = 16;

// Matrices are stored in row-major order:
// M(row, clo) = *(M.elements + row*M.stride + col);
typedef struct {
  int width;
  int height;
  int stride;
  float* elements;
} Matrix;

// Get a matrix element
__device__ float GetElement(const Matrix A, int row, int col) {
  return A.elements[row * A.stride + col];
}

// Set a matrix element
__device__ void SetElement(Matrix A, int row, int col, float value) {
  A.elements[row * A.stride + col] = value;
}

// Get the blockSizexblockSize sub-matrix Asub of A that is
// located col sub-matrices to the right and row sub-matrices down
// from the upper-left corner of A
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) {
  Matrix Asub;
  Asub.width = blockSize;
  Asub.height = blockSize;
  Asub.stride = A.stride;
  Asub.elements = &A.elements[A.stride * blockSize * row + blockSize * col];
  return Asub;
}

// CPU matrix multiplication for evaluating results
void cpu_matrix_multi(float *matA, float *matB, float *matC, int m, int k, int n) {
  for (int i = 0; i < m; i++) {
    for (int j = 0; j < n; j++) {
      float tmp = 0.0;
      for (int l = 0; l < k; l++) {
        tmp += matA[i*k + l] * matB[l*n + j];
      }
      matC[i*n + j] = tmp;
    }
  }
}

// Matrix multiplication kernel called by MatMul()
__global__
void MatMulKernel_SharMem(const Matrix A, const Matrix B, Matrix C) {
  // Block row and col
  int blockRow = blockIdx.y;
  int blockCol = blockIdx.x;

  // Each thread block computes one sub-matrix Csubof C
  Matrix Csub = GetSubMatrix(C, blockRow, blockCol);

  // Each thread computes one element of Csub
  // by accumulating results into Cvalue
  float Cvalue = 0;

  // Thread row and column within Csub
  int row = threadIdx.y;
  int col = threadIdx.x;

  // Loop over all the sub-matrices of A and B that are
  // required to compute Csub
  // Multiply each pair of sub-matrices together 
  // and accumulate results
  for (int m = 0; m < A.width/blockSize; m++) {

    // Get sub-matrix Asub of A
    Matrix Asub = GetSubMatrix(A, blockRow, m);

    // Get sub-matrix Bsub of B
    Matrix Bsub = GetSubMatrix(B, m, blockCol);

    // Shared memory used to store Asub and Bsub respectively
    __shared__ float As[blockSize][blockSize];
    __shared__ float Bs[blockSize][blockSize];

    // Load Asub and Bsub from device memory to shared memory
    // Each thread loads one element of each sub-matrix
    As[row][col] = GetElement(Asub, row, col); 
    Bs[row][col] = GetElement(Bsub, row, col);

    // Synchronize to make sure the sub-matrices are loaded
    // before starting the computation
    __syncthreads();

    // Multiply Asub and Bsub together
    for (int e = 0; e < blockSize; e++)
      Cvalue += As[row][e] * Bs[e][col];

    // Synchronize to make sure that the preceding 
    // computation is done before loading two new
    // sub-matrices of A and B in the next iteration
    __syncthreads();
  }

  // Write Csub to device memory 
  // Each thread write one element
  SetElement(Csub, row, col, Cvalue);
}

// Matrix multiplication - host code
// Matrix dimensions are assumed to be multiples of blockSize
void MatMul(const Matrix A, const Matrix B, Matrix C) {
  // Load A and B to device memory
  Matrix d_A;
  d_A.width = d_A.stride = A.width; d_A.height = A.height;
  size_t size = A.width * A.height * sizeof(float);
  hipMalloc(&d_A.elements, size);
  hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
  Matrix d_B;
  d_B.width = d_B.stride = B.width; d_B.height = B.width;
  size = B.width * B.height * sizeof(float);
  hipMalloc(&d_B.elements, size);
  hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);

  // Allocate C in device memory
  Matrix d_C;
  d_C.width = d_C.stride = C.width; d_C.height = C.height;
  size = C.width * C.height * sizeof(float);
  hipMalloc(&d_C.elements, size);
  
  // Invoke kernel
  dim3 dimBlock(blockSize, blockSize, 1);
  dim3 dimGrid(B.width/dimBlock.x, A.height/dimBlock.y, 1);
  MatMulKernel_SharMem<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);

  // Read C from device
  hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
  hipDeviceSynchronize();

  // Free device memory
  hipFree(d_A.elements);
  hipFree(d_B.elements);
  hipFree(d_C.elements);
}

int main() {
  // Initiate A and B elements on host memory
  Matrix h_A;
  h_A.height = 1024; h_A.width = h_A.stride = 1024;
  float* h_matA = new float[h_A.height * h_A.width];
  std::srand(1103);
  for (int i = 0; i < h_A.height; i++)
    for (int j = 0; j < h_A.width; j++)
      h_matA[i*h_A.width+j] = float(std::rand())/float(RAND_MAX);
  h_A.elements = h_matA;

  Matrix h_B;
  h_B.height = 1024; h_B.width = h_B.stride = 1024;
  float* h_matB = new float[h_B.height * h_B.width];
  for (int i = 0; i < h_B.height; i++)
    for (int j = 0; j < h_B.width; j++)
      h_matB[i*h_B.width+j] = float(std::rand())/float(RAND_MAX);
  h_B.elements = h_matB;

  // Matrix C size
  Matrix h_C;
  h_C.height = h_A.height; h_C.width = h_C.stride = h_B.width;
  float* h_matC = new float[h_A.height * h_B.width];
  h_C.elements = h_matC;

  // Call MatMul()
  MatMul(h_A, h_B, h_C);

  // Evaluate results
  float* h_matC_cpu = new float[h_A.height * h_B.width];
//  cpu_matrix_multi(h_matA, h_matB, h_matC_cpu, h_A.height, h_A.width, h_B.width);
  cpu_matrix_multi(h_A.elements, h_B.elements, h_matC_cpu, h_A.height, h_A.width, h_B.width);
  bool res_flag = false;
  float resol = 0.000001;
  for (int i = 0; i < h_C.height; i++) {
    for (int j = 0; j < h_C.width; j++) {
      if (fabs(*(h_C.elements+i*h_C.width+j) - h_matC[i*h_C.width+j]) > resol)
	res_flag = true;
    }
  }
	
  if (res_flag == false)
    cout << "Matrix multiplication by GPU is right! " << endl;
  else
    cout << "Results are not right! " << endl;

  // Free memory on host 
  delete [] h_matA;
  delete [] h_matB;
  delete [] h_matC;
  delete [] h_matC_cpu;

  return 0;
}


	.text
	.file	"gpucppMatMulSharMem.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z16cpu_matrix_multiPfS_S_iii   # -- Begin function _Z16cpu_matrix_multiPfS_S_iii
	.type	_Z16cpu_matrix_multiPfS_S_iii,@function
_Z16cpu_matrix_multiPfS_S_iii:          # @_Z16cpu_matrix_multiPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, -8(%rsp)                  # 8-byte Spill
	movq	%rsi, -16(%rsp)                 # 8-byte Spill
	movq	%rdi, -24(%rsp)                 # 8-byte Spill
	testl	%ecx, %ecx
	jle	.LBB0_9
# %bb.1:                                # %.preheader27.lr.ph
	movslq	%r9d, %rdi
	movl	%ecx, %ecx
	movl	%edi, %r10d
	movl	%r8d, %r11d
	leaq	(,%rdi,4), %rbx
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
.LBB0_2:                                # %.preheader27
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
                                        #       Child Loop BB0_6 Depth 3
	testl	%r9d, %r9d
	jle	.LBB0_8
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	movl	%r14d, %eax
	movq	-24(%rsp), %rdx                 # 8-byte Reload
	leaq	(%rdx,%rax,4), %r12
	movq	%r15, %rax
	imulq	%rdi, %rax
	movq	-8(%rsp), %rdx                  # 8-byte Reload
	leaq	(%rdx,%rax,4), %r13
	movq	-16(%rsp), %rsi                 # 8-byte Reload
	xorl	%eax, %eax
.LBB0_4:                                # %.preheader
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_6 Depth 3
	xorps	%xmm0, %xmm0
	testl	%r8d, %r8d
	jle	.LBB0_7
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB0_4 Depth=2
	movq	%rsi, %rbp
	xorl	%edx, %edx
.LBB0_6:                                # %.lr.ph
                                        #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r12,%rdx,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%rbp), %xmm1
	addss	%xmm1, %xmm0
	incq	%rdx
	addq	%rbx, %rbp
	cmpq	%rdx, %r11
	jne	.LBB0_6
.LBB0_7:                                # %._crit_edge
                                        #   in Loop: Header=BB0_4 Depth=2
	movss	%xmm0, (%r13,%rax,4)
	incq	%rax
	addq	$4, %rsi
	cmpq	%r10, %rax
	jne	.LBB0_4
.LBB0_8:                                # %._crit_edge31
                                        #   in Loop: Header=BB0_2 Depth=1
	incq	%r15
	addl	%r8d, %r14d
	cmpq	%rcx, %r15
	jne	.LBB0_2
.LBB0_9:                                # %._crit_edge33
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z16cpu_matrix_multiPfS_S_iii, .Lfunc_end0-_Z16cpu_matrix_multiPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__MatMulKernel_SharMem6MatrixS_S_ # -- Begin function _Z35__device_stub__MatMulKernel_SharMem6MatrixS_S_
	.type	_Z35__device_stub__MatMulKernel_SharMem6MatrixS_S_,@function
_Z35__device_stub__MatMulKernel_SharMem6MatrixS_S_: # @_Z35__device_stub__MatMulKernel_SharMem6MatrixS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	128(%rsp), %rax
	leaq	48(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	152(%rsp), %rax
	movq	%rax, 8(%rbx)
	leaq	176(%rsp), %rax
	movq	%rax, 16(%rbx)
	leaq	32(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20MatMulKernel_SharMem6MatrixS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z35__device_stub__MatMulKernel_SharMem6MatrixS_S_, .Lfunc_end1-_Z35__device_stub__MatMulKernel_SharMem6MatrixS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z6MatMul6MatrixS_S_            # -- Begin function _Z6MatMul6MatrixS_S_
	.type	_Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_:                   # @_Z6MatMul6MatrixS_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$248, %rsp
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	352(%rsp), %r13
	movl	304(%rsp), %eax
	movl	308(%rsp), %r14d
	leaq	72(%rsp), %rbx
	movl	%eax, -8(%rbx)
	movl	%eax, -16(%rbx)
	movl	%r14d, -12(%rbx)
	imull	%r14d, %eax
	movslq	%eax, %r15
	shlq	$2, %r15
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	320(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movslq	328(%rsp), %r12
	leaq	48(%rsp), %rbx
	movl	%r12d, -8(%rbx)
	movl	%r12d, -16(%rbx)
	movl	%r12d, -12(%rbx)
	movslq	332(%rsp), %r15
	imulq	%r12, %r15
	shlq	$2, %r15
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	344(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	(%r13), %eax
	movl	4(%r13), %ecx
	leaq	24(%rsp), %rdi
	movl	%eax, -8(%rdi)
	movl	%eax, -16(%rdi)
	movl	%ecx, -12(%rdi)
	imull	%eax, %ecx
	movslq	%ecx, %rbx
	shlq	$2, %rbx
	movq	%rbx, %rsi
	callq	hipMalloc
	shrl	$4, %r12d
	shrl	$4, %r14d
	shlq	$32, %r14
	orq	%r12, %r14
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movq	%r14, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	72(%rsp), %rax
	leaq	128(%rsp), %rcx
	movq	%rax, 16(%rcx)
	movups	56(%rsp), %xmm0
	movaps	%xmm0, (%rcx)
	movq	48(%rsp), %rax
	leaq	160(%rsp), %rdx
	movq	%rax, 16(%rdx)
	movups	32(%rsp), %xmm0
	movaps	%xmm0, (%rdx)
	movq	24(%rsp), %rax
	leaq	192(%rsp), %rsi
	movq	%rax, 16(%rsi)
	movups	8(%rsp), %xmm0
	movaps	%xmm0, (%rsi)
	leaq	224(%rsp), %r14
	movq	%rcx, (%r14)
	movq	%rdx, 8(%r14)
	movq	%rsi, 16(%r14)
	leaq	112(%rsp), %r15
	leaq	96(%rsp), %r12
	leaq	88(%rsp), %r13
	leaq	80(%rsp), %rbp
	movq	%r15, %rdi
	movq	%r12, %rsi
	movq	%r13, %rdx
	movq	%rbp, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r15), %rsi
	movl	8(%r15), %edx
	movq	(%r12), %rcx
	movl	8(%r12), %r8d
	movl	$_Z20MatMulKernel_SharMem6MatrixS_S_, %edi
	movq	%r14, %r9
	pushq	(%rbp)
	.cfi_adjust_cfa_offset 8
	pushq	(%r13)
	leaq	368(%rsp), %r13
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB2_2:
	movq	16(%r13), %rdi
	movq	24(%rsp), %rsi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	addq	$248, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z6MatMul6MatrixS_S_, .Lfunc_end2-_Z6MatMul6MatrixS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI3_2:
	.long	0x358637bd                      # float 9.99999997E-7
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI3_1:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %rbx
	movl	$1103, %edi                     # imm = 0x44F
	callq	srand
	xorl	%r14d, %r14d
	movq	%rbx, %r15
.LBB3_1:                                # %.preheader63
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	xorl	%r12d, %r12d
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movss	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	%xmm1, %xmm0
	movss	%xmm0, (%r15,%r12,4)
	incq	%r12
	cmpq	$1024, %r12                     # imm = 0x400
	jne	.LBB3_2
# %bb.3:                                #   in Loop: Header=BB3_1 Depth=1
	incq	%r14
	addq	$4096, %r15                     # imm = 0x1000
	cmpq	$1024, %r14                     # imm = 0x400
	jne	.LBB3_1
# %bb.4:
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %r14
	xorl	%r15d, %r15d
	movq	%rax, %r12
.LBB3_5:                                # %.preheader62
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_6 Depth 2
	xorl	%r13d, %r13d
.LBB3_6:                                #   Parent Loop BB3_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI3_0(%rip), %xmm0
	movss	%xmm0, (%r12,%r13,4)
	incq	%r13
	cmpq	$1024, %r13                     # imm = 0x400
	jne	.LBB3_6
# %bb.7:                                #   in Loop: Header=BB3_5 Depth=1
	incq	%r15
	addq	$4096, %r12                     # imm = 0x1000
	cmpq	$1024, %r15                     # imm = 0x400
	jne	.LBB3_5
# %bb.8:                                # %.preheader.preheader
	movl	$4194304, %edi                  # imm = 0x400000
	callq	_Znam
	movq	%rax, %r15
	movabsq	$4398046512128, %rax            # imm = 0x40000000400
	movq	%rax, 96(%rsp)
	movl	$1024, %ecx                     # imm = 0x400
	movl	%ecx, 104(%rsp)
	movq	%rbx, 112(%rsp)
	movq	%rax, 72(%rsp)
	movl	%ecx, 80(%rsp)
	movq	%r14, 88(%rsp)
	movq	%rax, 120(%rsp)
	movl	%ecx, 128(%rsp)
	movq	%r15, 136(%rsp)
	movq	%r15, 64(%rsp)
	movups	120(%rsp), %xmm0
	movups	%xmm0, 48(%rsp)
	movq	88(%rsp), %rax
	movq	%rax, 40(%rsp)
	movups	72(%rsp), %xmm0
	movups	%xmm0, 24(%rsp)
	movq	112(%rsp), %rax
	movq	%rax, 16(%rsp)
	movups	96(%rsp), %xmm0
	movups	%xmm0, (%rsp)
	callq	_Z6MatMul6MatrixS_S_
	xorl	%eax, %eax
	movaps	.LCPI3_1(%rip), %xmm0           # xmm0 = [NaN,NaN,NaN,NaN]
	movss	.LCPI3_2(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	movl	$1, %ecx
	movq	%r15, %rdx
	xorl	%esi, %esi
.LBB3_9:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_10 Depth 2
	xorl	%edi, %edi
.LBB3_10:                               #   Parent Loop BB3_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rdx,%rdi,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	subss	%xmm2, %xmm2
	andps	%xmm0, %xmm2
	ucomiss	%xmm1, %xmm2
	movzbl	%sil, %esi
	cmoval	%ecx, %esi
	incq	%rdi
	cmpq	$1024, %rdi                     # imm = 0x400
	jne	.LBB3_10
# %bb.11:                               # %_Z16cpu_matrix_multiPfS_S_iii.exit
                                        #   in Loop: Header=BB3_9 Depth=1
	incq	%rax
	addq	$4096, %rdx                     # imm = 0x1000
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB3_9
# %bb.12:
	movl	$_ZSt4cout, %edi
	testb	$1, %sil
	jne	.LBB3_14
# %bb.13:
	movl	$.L.str, %esi
	movl	$39, %edx
	jmp	.LBB3_15
.LBB3_14:
	movl	$.L.str.1, %esi
	movl	$23, %edx
.LBB3_15:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	movq	%r15, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$144, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20MatMulKernel_SharMem6MatrixS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20MatMulKernel_SharMem6MatrixS_S_,@object # @_Z20MatMulKernel_SharMem6MatrixS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z20MatMulKernel_SharMem6MatrixS_S_
	.p2align	3, 0x0
_Z20MatMulKernel_SharMem6MatrixS_S_:
	.quad	_Z35__device_stub__MatMulKernel_SharMem6MatrixS_S_
	.size	_Z20MatMulKernel_SharMem6MatrixS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Matrix multiplication by GPU is right! "
	.size	.L.str, 40

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Results are not right! "
	.size	.L.str.1, 24

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z20MatMulKernel_SharMem6MatrixS_S_"
	.size	.L__unnamed_1, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__MatMulKernel_SharMem6MatrixS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20MatMulKernel_SharMem6MatrixS_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20MatMulKernel_SharMem6MatrixS_S_ ; -- Begin function _Z20MatMulKernel_SharMem6MatrixS_S_
	.globl	_Z20MatMulKernel_SharMem6MatrixS_S_
	.p2align	8
	.type	_Z20MatMulKernel_SharMem6MatrixS_S_,@function
_Z20MatMulKernel_SharMem6MatrixS_S_:    ; @_Z20MatMulKernel_SharMem6MatrixS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x40
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s5, 16
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph
	s_clause 0x3
	s_load_b32 s10, s[0:1], 0x8
	s_load_b32 s4, s[0:1], 0x20
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b64 s[8:9], s[0:1], 0x28
	v_lshlrev_b32_e32 v2, 2, v0
	v_lshlrev_b32_e32 v3, 6, v1
	s_ashr_i32 s11, s5, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_lshr_b32 s11, s11, 28
	v_add_nc_u32_e32 v4, 0x400, v2
	s_add_i32 s5, s5, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_ashr_i32 s5, s5, 4
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[5:6], null, s10, v1, v[0:1]
	v_mad_u64_u32 v[7:8], null, s4, v1, v[0:1]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[9:10], 2, v[5:6]
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[11:12], 2, v[7:8]
	v_add_nc_u32_e32 v6, v4, v3
	v_add_co_u32 v7, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v12, vcc_lo
	s_mul_i32 s6, s10, s15
	s_mov_b32 s7, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s8, s7, s4
	s_add_i32 s9, s7, s6
	s_add_i32 s10, s8, s14
	s_lshl_b32 s8, s9, 4
	s_lshl_b32 s10, s10, 4
	s_ashr_i32 s9, s8, 31
	s_ashr_i32 s11, s10, 31
	s_lshl_b64 s[8:9], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v11, vcc_lo, v7, s8
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
	s_lshl_b64 s[8:9], s[10:11], 2
	v_add_co_u32 v13, vcc_lo, v9, s8
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v10, vcc_lo
	global_load_b32 v12, v[11:12], off
	global_load_b32 v13, v[13:14], off
	v_mov_b32_e32 v11, v4
	s_mov_b32 s8, 0
	s_waitcnt vmcnt(1)
	ds_store_b32 v5, v12
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v12, s8, v3
	s_add_i32 s8, s8, 4
	ds_load_b32 v13, v11
	ds_load_b32 v12, v12
	v_add_nc_u32_e32 v11, 64, v11
	s_cmp_eq_u32 s8, 64
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, v12, v13
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, s5
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %Flow101
	s_load_b32 s0, s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, s0, v1, v[0:1]
	s_mul_i32 s0, s0, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	s_lshl_b32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_ashrrev_i32_e32 v4, 31, v3
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20MatMulKernel_SharMem6MatrixS_S_
		.amdhsa_group_segment_fixed_size 2048
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 72
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20MatMulKernel_SharMem6MatrixS_S_, .Lfunc_end0-_Z20MatMulKernel_SharMem6MatrixS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 540
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           24
        .value_kind:     by_value
      - .offset:         24
        .size:           24
        .value_kind:     by_value
      - .offset:         48
        .size:           24
        .value_kind:     by_value
    .group_segment_fixed_size: 2048
    .kernarg_segment_align: 8
    .kernarg_segment_size: 72
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20MatMulKernel_SharMem6MatrixS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20MatMulKernel_SharMem6MatrixS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
