#include "includes.h"
__global__ void KernelLBSSimple(int aCount, const int* b_global, int bCount, int* indices_global) {

__shared__ int data_shared[NT * VT];

int tid = threadIdx.x;

// Load bCount elements from B into data_shared.
int x[VT];
#pragma unroll
for(int i = 0; i < VT; ++i) {
int index = NT * i + tid;
if(index < bCount) x[i] = b_global[index];
}

#pragma unroll
for(int i = 0; i < VT; ++i)
data_shared[NT * i + tid] = x[i];
__syncthreads();

// Each thread searches for its Merge Path partition.
int diag = VT * tid;
int begin = max(0, diag - bCount);
int end = min(diag, aCount);

while(begin < end) {
int mid = (begin + end)>> 1;
int aKey = mid;
int bKey = data_shared[diag - 1 - mid];
bool pred = aKey < bKey;
if(pred) begin = mid + 1;
else end = mid;
}
int mp = begin;

// Sequentially search, comparing indices a to elements data_shared[b].
// Store indices for A in the right-side of the shared memory array.
// This lets us complete the search in just a single pass, rather than
// the search and compact passes of the generalized vectorized sorted
// search function.
int a = mp;
int b = diag - a;

#pragma unroll
for(int i = 0; i < VT; ++i) {
bool p;
if(b >= bCount) p = true;
else if(a >= aCount) p = false;
else p = a < data_shared[b];

if(p)
// If a < data_shared[b], advance A and store the index b - 1.
data_shared[bCount + a++] = b - 1;
else
// Just advance b.
++b;
}
__syncthreads();

// Store all indices to global memory.
for(int i = tid; i < aCount; i += NT)
indices_global[i] = data_shared[bCount + i];
}
	.file	"tmpxft_002688cb_00000000-6_KernelLBSSimple.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z15KernelLBSSimpleiPKiiPiiPKiiPi
	.type	_Z40__device_stub__Z15KernelLBSSimpleiPKiiPiiPKiiPi, @function
_Z40__device_stub__Z15KernelLBSSimpleiPKiiPiiPKiiPi:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15KernelLBSSimpleiPKiiPi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z40__device_stub__Z15KernelLBSSimpleiPKiiPiiPKiiPi, .-_Z40__device_stub__Z15KernelLBSSimpleiPKiiPiiPKiiPi
	.globl	_Z15KernelLBSSimpleiPKiiPi
	.type	_Z15KernelLBSSimpleiPKiiPi, @function
_Z15KernelLBSSimpleiPKiiPi:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15KernelLBSSimpleiPKiiPiiPKiiPi
	.cfi_endproc
.LFE2033:
	.size	_Z15KernelLBSSimpleiPKiiPi, .-_Z15KernelLBSSimpleiPKiiPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15KernelLBSSimpleiPKiiPi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15KernelLBSSimpleiPKiiPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KernelLBSSimple(int aCount, const int* b_global, int bCount, int* indices_global) {

__shared__ int data_shared[NT * VT];

int tid = threadIdx.x;

// Load bCount elements from B into data_shared.
int x[VT];
#pragma unroll
for(int i = 0; i < VT; ++i) {
int index = NT * i + tid;
if(index < bCount) x[i] = b_global[index];
}

#pragma unroll
for(int i = 0; i < VT; ++i)
data_shared[NT * i + tid] = x[i];
__syncthreads();

// Each thread searches for its Merge Path partition.
int diag = VT * tid;
int begin = max(0, diag - bCount);
int end = min(diag, aCount);

while(begin < end) {
int mid = (begin + end)>> 1;
int aKey = mid;
int bKey = data_shared[diag - 1 - mid];
bool pred = aKey < bKey;
if(pred) begin = mid + 1;
else end = mid;
}
int mp = begin;

// Sequentially search, comparing indices a to elements data_shared[b].
// Store indices for A in the right-side of the shared memory array.
// This lets us complete the search in just a single pass, rather than
// the search and compact passes of the generalized vectorized sorted
// search function.
int a = mp;
int b = diag - a;

#pragma unroll
for(int i = 0; i < VT; ++i) {
bool p;
if(b >= bCount) p = true;
else if(a >= aCount) p = false;
else p = a < data_shared[b];

if(p)
// If a < data_shared[b], advance A and store the index b - 1.
data_shared[bCount + a++] = b - 1;
else
// Just advance b.
++b;
}
__syncthreads();

// Store all indices to global memory.
for(int i = tid; i < aCount; i += NT)
indices_global[i] = data_shared[bCount + i];
}
	.text
	.file	"KernelLBSSimple.hip"
	.globl	_Z30__device_stub__KernelLBSSimpleiPKiiPi # -- Begin function _Z30__device_stub__KernelLBSSimpleiPKiiPi
	.type	_Z30__device_stub__KernelLBSSimpleiPKiiPi,@function
_Z30__device_stub__KernelLBSSimpleiPKiiPi: # @_Z30__device_stub__KernelLBSSimpleiPKiiPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15KernelLBSSimpleiPKiiPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__KernelLBSSimpleiPKiiPi, .Lfunc_end0-_Z30__device_stub__KernelLBSSimpleiPKiiPi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15KernelLBSSimpleiPKiiPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15KernelLBSSimpleiPKiiPi,@object # @_Z15KernelLBSSimpleiPKiiPi
	.section	.rodata,"a",@progbits
	.globl	_Z15KernelLBSSimpleiPKiiPi
	.p2align	3, 0x0
_Z15KernelLBSSimpleiPKiiPi:
	.quad	_Z30__device_stub__KernelLBSSimpleiPKiiPi
	.size	_Z15KernelLBSSimpleiPKiiPi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15KernelLBSSimpleiPKiiPi"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__KernelLBSSimpleiPKiiPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15KernelLBSSimpleiPKiiPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15KernelLBSSimpleiPKiiPi ; -- Begin function _Z15KernelLBSSimpleiPKiiPi
	.globl	_Z15KernelLBSSimpleiPKiiPi
	.p2align	8
	.type	_Z15KernelLBSSimpleiPKiiPi,@function
_Z15KernelLBSSimpleiPKiiPi:             ; @_Z15KernelLBSSimpleiPKiiPi
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x8
	v_lshlrev_b32_e32 v9, 2, v0
	s_mov_b32 s5, exec_lo
                                        ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	global_load_b32 v1, v9, s[2:3]
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v10, 0x80, v0
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v10
	s_cbranch_execz .LBB0_4
; %bb.3:
	global_load_b32 v2, v9, s[2:3] offset:512
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v10, 0x100, v0
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v10
	s_cbranch_execz .LBB0_6
; %bb.5:
	global_load_b32 v3, v9, s[2:3] offset:1024
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v10, 0x180, v0
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v10
	s_cbranch_execz .LBB0_8
; %bb.7:
	global_load_b32 v4, v9, s[2:3] offset:1536
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v10, 0x200, v0
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v10
	s_cbranch_execz .LBB0_10
; %bb.9:
	global_load_b32 v5, v9, s[2:3] offset:2048
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v10, 0x280, v0
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v10
	s_cbranch_execz .LBB0_12
; %bb.11:
	global_load_b32 v6, v9, s[2:3] offset:2560
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v10, 0x300, v0
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v10
	s_cbranch_execz .LBB0_14
; %bb.13:
	global_load_b32 v7, v9, s[2:3] offset:3072
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v10, 0x380, v0
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v10
	s_cbranch_execz .LBB0_16
; %bb.15:
	global_load_b32 v8, v9, s[2:3] offset:3584
.LBB0_16:                               ; %.preheader
	s_or_b32 exec_lo, exec_lo, s5
	s_load_b32 s2, s[0:1], 0x0
	v_lshlrev_b32_e32 v11, 3, v0
	s_mov_b32 s5, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v9, v1, v2 offset1:2
	ds_store_2addr_stride64_b32 v9, v3, v4 offset0:4 offset1:6
	ds_store_2addr_stride64_b32 v9, v5, v6 offset0:8 offset1:10
	ds_store_2addr_stride64_b32 v9, v7, v8 offset0:12 offset1:14
	s_waitcnt lgkmcnt(0)
	v_subrev_nc_u32_e32 v10, s4, v11
	s_barrier
	buffer_gl0_inv
	v_max_i32_e32 v10, 0, v10
	v_min_i32_e32 v12, s2, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v10, v12
	s_cbranch_execz .LBB0_19
.LBB0_17:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 1, v1
	v_not_b32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v2, v11, v2, 2
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v1, v2
	v_dual_cndmask_b32 v12, v1, v12 :: v_dual_add_nc_u32 v3, 1, v1
	v_cndmask_b32_e32 v10, v10, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v10, v12
	s_or_b32 s5, vcc_lo, s5
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_17
; %bb.18:                               ; %Flow122
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_19:                               ; %Flow123
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_sub_nc_u32_e32 v2, v11, v10
	s_mov_b32 s5, -1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_gt_i32_e64 s4, v2
	s_cbranch_execz .LBB0_25
; %bb.20:
	s_mov_b32 s6, -1
	s_mov_b32 s5, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_i32_e64 s2, v10
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_lshlrev_b32_e32 v1, 2, v2
	s_mov_b32 s5, exec_lo
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v10, v1
	s_or_not1_b32 s6, vcc_lo, exec_lo
.LBB0_22:                               ; %Flow120
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s7, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s7
; %bb.23:                               ; %.critedge73
	v_add_nc_u32_e32 v1, 1, v2
	s_and_not1_b32 s5, s5, exec_lo
; %bb.24:                               ; %Flow121
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s5, s5, exec_lo
.LBB0_25:                               ; %Flow119
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_27
; %bb.26:                               ; %.critedge
	v_add_nc_u32_e32 v1, 1, v10
	v_add_nc_u32_e32 v3, -1, v2
	v_add_lshl_u32 v4, v10, s4, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v10, v1 :: v_dual_mov_b32 v1, v2
	ds_store_b32 v4, v3
.LBB0_27:
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s5, -1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr2
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_33
; %bb.28:
	v_cmp_le_i32_e64 s6, s2, v10
	s_mov_b32 s5, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_i32_e64 s2, v10
	s_cbranch_execz .LBB0_30
; %bb.29:
	v_lshlrev_b32_e32 v2, 2, v1
	s_and_not1_b32 s6, s6, exec_lo
	s_mov_b32 s5, exec_lo
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v10, v2
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s6, s8
.LBB0_30:                               ; %Flow117
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s7, s6
; %bb.31:                               ; %.critedge73.1
	v_add_nc_u32_e32 v2, 1, v1
	s_and_not1_b32 s5, s5, exec_lo
; %bb.32:                               ; %Flow118
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s5, s5, exec_lo
.LBB0_33:                               ; %Flow116
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_35
; %bb.34:                               ; %.critedge.1
	v_add_nc_u32_e32 v2, 1, v10
	v_add_nc_u32_e32 v3, -1, v1
	v_add_lshl_u32 v4, v10, s4, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v10, v2
	v_mov_b32_e32 v2, v1
	ds_store_b32 v4, v3
.LBB0_35:
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s5, -1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_gt_i32_e64 s4, v2
	s_cbranch_execz .LBB0_41
; %bb.36:
	v_cmp_le_i32_e64 s6, s2, v10
	s_mov_b32 s5, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_i32_e64 s2, v10
	s_cbranch_execz .LBB0_38
; %bb.37:
	v_lshlrev_b32_e32 v1, 2, v2
	s_and_not1_b32 s6, s6, exec_lo
	s_mov_b32 s5, exec_lo
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v10, v1
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s6, s8
.LBB0_38:                               ; %Flow114
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s7, s6
; %bb.39:                               ; %.critedge73.2
	v_add_nc_u32_e32 v1, 1, v2
	s_and_not1_b32 s5, s5, exec_lo
; %bb.40:                               ; %Flow115
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s5, s5, exec_lo
.LBB0_41:                               ; %Flow113
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_43
; %bb.42:                               ; %.critedge.2
	v_add_nc_u32_e32 v1, 1, v10
	v_add_nc_u32_e32 v3, -1, v2
	v_add_lshl_u32 v4, v10, s4, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v10, v1 :: v_dual_mov_b32 v1, v2
	ds_store_b32 v4, v3
.LBB0_43:
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s5, -1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr2
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_49
; %bb.44:
	v_cmp_le_i32_e64 s6, s2, v10
	s_mov_b32 s5, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_i32_e64 s2, v10
	s_cbranch_execz .LBB0_46
; %bb.45:
	v_lshlrev_b32_e32 v2, 2, v1
	s_and_not1_b32 s6, s6, exec_lo
	s_mov_b32 s5, exec_lo
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v10, v2
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s6, s8
.LBB0_46:                               ; %Flow111
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s7, s6
; %bb.47:                               ; %.critedge73.3
	v_add_nc_u32_e32 v2, 1, v1
	s_and_not1_b32 s5, s5, exec_lo
; %bb.48:                               ; %Flow112
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s5, s5, exec_lo
.LBB0_49:                               ; %Flow110
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_51
; %bb.50:                               ; %.critedge.3
	v_add_nc_u32_e32 v2, 1, v10
	v_add_nc_u32_e32 v3, -1, v1
	v_add_lshl_u32 v4, v10, s4, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v10, v2
	v_mov_b32_e32 v2, v1
	ds_store_b32 v4, v3
.LBB0_51:
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s5, -1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_gt_i32_e64 s4, v2
	s_cbranch_execz .LBB0_57
; %bb.52:
	v_cmp_le_i32_e64 s6, s2, v10
	s_mov_b32 s5, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_i32_e64 s2, v10
	s_cbranch_execz .LBB0_54
; %bb.53:
	v_lshlrev_b32_e32 v1, 2, v2
	s_and_not1_b32 s6, s6, exec_lo
	s_mov_b32 s5, exec_lo
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v10, v1
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s6, s8
.LBB0_54:                               ; %Flow108
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s7, s6
; %bb.55:                               ; %.critedge73.4
	v_add_nc_u32_e32 v1, 1, v2
	s_and_not1_b32 s5, s5, exec_lo
; %bb.56:                               ; %Flow109
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s5, s5, exec_lo
.LBB0_57:                               ; %Flow107
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_59
; %bb.58:                               ; %.critedge.4
	v_add_nc_u32_e32 v1, 1, v10
	v_add_nc_u32_e32 v3, -1, v2
	v_add_lshl_u32 v4, v10, s4, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v10, v1 :: v_dual_mov_b32 v1, v2
	ds_store_b32 v4, v3
.LBB0_59:
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s5, -1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr2
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_65
; %bb.60:
	v_cmp_le_i32_e64 s6, s2, v10
	s_mov_b32 s5, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_i32_e64 s2, v10
	s_cbranch_execz .LBB0_62
; %bb.61:
	v_lshlrev_b32_e32 v2, 2, v1
	s_and_not1_b32 s6, s6, exec_lo
	s_mov_b32 s5, exec_lo
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v10, v2
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s6, s8
.LBB0_62:                               ; %Flow105
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s7, s6
; %bb.63:                               ; %.critedge73.5
	v_add_nc_u32_e32 v2, 1, v1
	s_and_not1_b32 s5, s5, exec_lo
; %bb.64:                               ; %Flow106
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s5, s5, exec_lo
.LBB0_65:                               ; %Flow104
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_67
; %bb.66:                               ; %.critedge.5
	v_add_nc_u32_e32 v2, 1, v10
	v_add_nc_u32_e32 v3, -1, v1
	v_add_lshl_u32 v4, v10, s4, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v10, v2
	v_mov_b32_e32 v2, v1
	ds_store_b32 v4, v3
.LBB0_67:
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s5, -1
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_gt_i32_e64 s4, v2
	s_cbranch_execz .LBB0_73
; %bb.68:
	v_cmp_le_i32_e64 s6, s2, v10
	s_mov_b32 s5, 0
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_i32_e64 s2, v10
	s_cbranch_execz .LBB0_70
; %bb.69:
	v_lshlrev_b32_e32 v1, 2, v2
	s_and_not1_b32 s6, s6, exec_lo
	s_mov_b32 s5, exec_lo
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v10, v1
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s6, s8
.LBB0_70:                               ; %Flow102
	s_or_b32 exec_lo, exec_lo, s7
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s7, s6
; %bb.71:                               ; %.critedge73.6
	v_add_nc_u32_e32 v1, 1, v2
	s_and_not1_b32 s5, s5, exec_lo
; %bb.72:                               ; %Flow103
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s5, s5, exec_lo
.LBB0_73:                               ; %Flow101
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_75
; %bb.74:                               ; %.critedge.6
	v_add_nc_u32_e32 v1, 1, v10
	v_add_nc_u32_e32 v3, -1, v2
	v_add_lshl_u32 v4, v10, s4, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v10, v1 :: v_dual_mov_b32 v1, v2
	ds_store_b32 v4, v3
.LBB0_75:
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s5, -1
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_79
; %bb.76:
	s_mov_b32 s6, 0
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_i32_e64 s2, v10
	s_cbranch_execz .LBB0_78
; %bb.77:
	v_lshlrev_b32_e32 v2, 2, v1
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v10, v2
	s_and_b32 s6, vcc_lo, exec_lo
.LBB0_78:                               ; %Flow100
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s5, s6, exec_lo
.LBB0_79:                               ; %Flow99
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB0_81
; %bb.80:                               ; %.critedge.7
	v_add_nc_u32_e32 v1, -1, v1
	v_add_lshl_u32 v2, v10, s4, 2
	ds_store_b32 v2, v1
.LBB0_81:                               ; %.critedge73.7
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB0_84
; %bb.82:                               ; %.lr.ph85.preheader
	s_load_b64 s[0:1], s[0:1], 0x18
	v_add_lshl_u32 v3, v0, s4, 2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, s0, s0, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, null, s1, 0, s0
	s_mov_b32 s1, 0
.LBB0_83:                               ; %.lr.ph85
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v4, v3
	v_add_nc_u32_e32 v0, 0x80, v0
	v_add_nc_u32_e32 v3, 0x200, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s2, v0
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[1:2], v4, off
	v_add_co_u32 v1, s0, 0x200, v1
	v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_83
.LBB0_84:                               ; %Flow98
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15KernelLBSSimpleiPKiiPi
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 9
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15KernelLBSSimpleiPKiiPi, .Lfunc_end0-_Z15KernelLBSSimpleiPKiiPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1972
; NumSgprs: 11
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 11
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15KernelLBSSimpleiPKiiPi
    .private_segment_fixed_size: 0
    .sgpr_count:     11
    .sgpr_spill_count: 0
    .symbol:         _Z15KernelLBSSimpleiPKiiPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
