#include <cuda.h>
#include <cuda_runtime_api.h>

#define ID3_BASE_WIDTH		3	
#define ID3_BASE_HEIGHT		6
#define ID3_MID_WIDTH		1
#define ID3_THRESHOLD		.19f	//definitely needs to be changed
#define ID3_SKIP_AMOUNT		1 		//amount to skip in pixels, we can change this to be multiplied by scale if necessary/desirable


//This identifier is 3 vertical bars going dark light dark
__global__ 
void ID3kernel(float* intImage, size_t stride, int* offsets, int windowSize, int numSubWindows, int scale, int* faceDetected, float* results, float* heatMap) {

	int threadNum = blockIdx.x * blockDim.x + threadIdx.x;
	if(threadNum < numSubWindows){
		int startX = offsets[threadNum]/(stride);
		int startY = offsets[threadNum]%stride;
		float maxFitValue = 0.0f;
		
		for (int i = startX; (i+ID3_BASE_WIDTH*scale) < (startX+windowSize); i = i+ID3_SKIP_AMOUNT){ //use ID3_SKIP_AMOUNT * scale for it to scale up as identifier scales
			for (int j = startY; (j+ID3_BASE_HEIGHT*scale) < (startY + windowSize); j = j+ID3_SKIP_AMOUNT){
				// take important corners from image
				float upperLeft 		= intImage[i*stride + j];
				float upperRight 		= intImage[(i+ID3_BASE_WIDTH*scale)*stride + j];
				
				float midLeftTop 		= intImage[(i+ID3_BASE_WIDTH*scale/2 - ID3_MID_WIDTH*scale/2)*stride + j];
				float midRightTop		= intImage[(i+ID3_BASE_WIDTH*scale/2 + ID3_MID_WIDTH*scale/2)*stride + j];
				float midLeftBot 		= intImage[(i+ID3_BASE_WIDTH*scale/2 - ID3_MID_WIDTH*scale/2)*stride + j+ID3_BASE_HEIGHT*scale];
				float midRightBot		= intImage[(i+ID3_BASE_WIDTH*scale/2 + ID3_MID_WIDTH*scale/2)*stride + j+ID3_BASE_HEIGHT*scale];
				
				float lowerLeft 		= intImage[i*stride + j+(ID3_BASE_HEIGHT*scale)];
				float lowerRight 		= intImage[(i+ID3_BASE_WIDTH*scale)*stride + j+(ID3_BASE_HEIGHT*scale)];
			
				//calculate fit value based on identifier (hard-coded)
				// float fitValue = (midRightBot + midLeftTop - midRightTop - midLeftBot)*2.0 - lowerRight - upperLeft + upperRight + lowerLeft;
				float fitValue = 2.0*(midRightBot - midLeftBot - midRightTop + midLeftTop) - (lowerRight - lowerLeft - upperRight + upperLeft) ;
				
				if(fitValue < 0)	
					fitValue = -fitValue;
				
				if(fitValue > maxFitValue){
					maxFitValue = fitValue;
				}
			}
		}
		float goodnessValue = maxFitValue/(ID3_BASE_WIDTH*scale*ID3_BASE_HEIGHT*scale); // goodnessValue = fit/area
	
		// results[threadNum] = goodnessValue;
		
		if(goodnessValue > ID3_THRESHOLD){
			faceDetected[threadNum] = 1;

			// for(int i = 0; i < windowSize; ++i){
			// 	for(int j = 0; j < windowSize; ++j){
			// 		heatMap[offsets[threadNum] + i*stride + j] = heatMap[offsets[threadNum] + i*stride + j] + 1.0f;
			// 	}
			// }
		}
	}
}

	.file	"tmpxft_002a0de4_00000000-6_identify3.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z9ID3kernelPfmPiiiiS0_S_S_PfmPiiiiS0_S_S_
	.type	_Z41__device_stub__Z9ID3kernelPfmPiiiiS0_S_S_PfmPiiiiS0_S_S_, @function
_Z41__device_stub__Z9ID3kernelPfmPiiiiS0_S_S_PfmPiiiiS0_S_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	240(%rsp), %rax
	movl	%ecx, 36(%rsp)
	leaq	72(%rsp), %rcx
	movl	%r8d, 32(%rsp)
	movl	%r9d, 28(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z9ID3kernelPfmPiiiiS0_S_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z41__device_stub__Z9ID3kernelPfmPiiiiS0_S_S_PfmPiiiiS0_S_S_, .-_Z41__device_stub__Z9ID3kernelPfmPiiiiS0_S_S_PfmPiiiiS0_S_S_
	.globl	_Z9ID3kernelPfmPiiiiS0_S_S_
	.type	_Z9ID3kernelPfmPiiiiS0_S_S_, @function
_Z9ID3kernelPfmPiiiiS0_S_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z9ID3kernelPfmPiiiiS0_S_S_PfmPiiiiS0_S_S_
	.cfi_endproc
.LFE2033:
	.size	_Z9ID3kernelPfmPiiiiS0_S_S_, .-_Z9ID3kernelPfmPiiiiS0_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z9ID3kernelPfmPiiiiS0_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9ID3kernelPfmPiiiiS0_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>

#define ID3_BASE_WIDTH		3	
#define ID3_BASE_HEIGHT		6
#define ID3_MID_WIDTH		1
#define ID3_THRESHOLD		.19f	//definitely needs to be changed
#define ID3_SKIP_AMOUNT		1 		//amount to skip in pixels, we can change this to be multiplied by scale if necessary/desirable


//This identifier is 3 vertical bars going dark light dark
__global__ 
void ID3kernel(float* intImage, size_t stride, int* offsets, int windowSize, int numSubWindows, int scale, int* faceDetected, float* results, float* heatMap) {

	int threadNum = blockIdx.x * blockDim.x + threadIdx.x;
	if(threadNum < numSubWindows){
		int startX = offsets[threadNum]/(stride);
		int startY = offsets[threadNum]%stride;
		float maxFitValue = 0.0f;
		
		for (int i = startX; (i+ID3_BASE_WIDTH*scale) < (startX+windowSize); i = i+ID3_SKIP_AMOUNT){ //use ID3_SKIP_AMOUNT * scale for it to scale up as identifier scales
			for (int j = startY; (j+ID3_BASE_HEIGHT*scale) < (startY + windowSize); j = j+ID3_SKIP_AMOUNT){
				// take important corners from image
				float upperLeft 		= intImage[i*stride + j];
				float upperRight 		= intImage[(i+ID3_BASE_WIDTH*scale)*stride + j];
				
				float midLeftTop 		= intImage[(i+ID3_BASE_WIDTH*scale/2 - ID3_MID_WIDTH*scale/2)*stride + j];
				float midRightTop		= intImage[(i+ID3_BASE_WIDTH*scale/2 + ID3_MID_WIDTH*scale/2)*stride + j];
				float midLeftBot 		= intImage[(i+ID3_BASE_WIDTH*scale/2 - ID3_MID_WIDTH*scale/2)*stride + j+ID3_BASE_HEIGHT*scale];
				float midRightBot		= intImage[(i+ID3_BASE_WIDTH*scale/2 + ID3_MID_WIDTH*scale/2)*stride + j+ID3_BASE_HEIGHT*scale];
				
				float lowerLeft 		= intImage[i*stride + j+(ID3_BASE_HEIGHT*scale)];
				float lowerRight 		= intImage[(i+ID3_BASE_WIDTH*scale)*stride + j+(ID3_BASE_HEIGHT*scale)];
			
				//calculate fit value based on identifier (hard-coded)
				// float fitValue = (midRightBot + midLeftTop - midRightTop - midLeftBot)*2.0 - lowerRight - upperLeft + upperRight + lowerLeft;
				float fitValue = 2.0*(midRightBot - midLeftBot - midRightTop + midLeftTop) - (lowerRight - lowerLeft - upperRight + upperLeft) ;
				
				if(fitValue < 0)	
					fitValue = -fitValue;
				
				if(fitValue > maxFitValue){
					maxFitValue = fitValue;
				}
			}
		}
		float goodnessValue = maxFitValue/(ID3_BASE_WIDTH*scale*ID3_BASE_HEIGHT*scale); // goodnessValue = fit/area
	
		// results[threadNum] = goodnessValue;
		
		if(goodnessValue > ID3_THRESHOLD){
			faceDetected[threadNum] = 1;

			// for(int i = 0; i < windowSize; ++i){
			// 	for(int j = 0; j < windowSize; ++j){
			// 		heatMap[offsets[threadNum] + i*stride + j] = heatMap[offsets[threadNum] + i*stride + j] + 1.0f;
			// 	}
			// }
		}
	}
}

	.text
	.file	"identify3.hip"
	.globl	_Z24__device_stub__ID3kernelPfmPiiiiS0_S_S_ # -- Begin function _Z24__device_stub__ID3kernelPfmPiiiiS0_S_S_
	.type	_Z24__device_stub__ID3kernelPfmPiiiiS0_S_S_,@function
_Z24__device_stub__ID3kernelPfmPiiiiS0_S_S_: # @_Z24__device_stub__ID3kernelPfmPiiiiS0_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9ID3kernelPfmPiiiiS0_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__ID3kernelPfmPiiiiS0_S_S_, .Lfunc_end0-_Z24__device_stub__ID3kernelPfmPiiiiS0_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9ID3kernelPfmPiiiiS0_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9ID3kernelPfmPiiiiS0_S_S_,@object # @_Z9ID3kernelPfmPiiiiS0_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z9ID3kernelPfmPiiiiS0_S_S_
	.p2align	3, 0x0
_Z9ID3kernelPfmPiiiiS0_S_S_:
	.quad	_Z24__device_stub__ID3kernelPfmPiiiiS0_S_S_
	.size	_Z9ID3kernelPfmPiiiiS0_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9ID3kernelPfmPiiiiS0_S_S_"
	.size	.L__unnamed_1, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__ID3kernelPfmPiiiiS0_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9ID3kernelPfmPiiiiS0_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9ID3kernelPfmPiiiiS0_S_S_ ; -- Begin function _Z9ID3kernelPfmPiiiiS0_S_S_
	.globl	_Z9ID3kernelPfmPiiiiS0_S_S_
	.p2align	8
	.type	_Z9ID3kernelPfmPiiiiS0_S_S_,@function
_Z9ID3kernelPfmPiiiiS0_S_S_:            ; @_Z9ID3kernelPfmPiiiiS0_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s5, v1
	s_cbranch_execz .LBB0_11
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v4, 0
	s_mul_i32 s3, s6, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_ge_i32 s3, s4
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_cbranch_scc1 .LBB0_9
; %bb.2:                                ; %.preheader.lr.ph
	s_load_b64 s[8:9], s[0:1], 0x10
	s_mul_i32 s12, s6, 6
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	s_load_b128 s[8:11], s[0:1], 0x0
	global_load_b32 v8, v[2:3], off
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v2, s10
	v_cvt_f32_u32_e32 v3, s11
	s_sub_u32 s2, 0, s10
	s_subb_u32 s5, 0, s11
	s_cmp_lt_i32 s12, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmamk_f32 v2, v3, 0x4f800000, v2
	s_cselect_b32 s14, -1, 0
	s_ashr_i32 s13, s12, 31
	v_rcp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x5f7ffffc, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x2f800000, v2
	v_trunc_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v2, v3, 0xcf800000, v2
	v_cvt_u32_f32_e32 v3, v3
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s2, v3
	v_mul_hi_u32 v5, s2, v2
	v_mul_lo_u32 v6, s5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_mul_lo_u32 v5, s2, v2
	v_add_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v2, v5
	v_mul_lo_u32 v7, v2, v4
	v_mul_hi_u32 v9, v2, v4
	v_mul_hi_u32 v10, v3, v5
	v_mul_lo_u32 v5, v3, v5
	v_mul_hi_u32 v11, v3, v4
	v_mul_lo_u32 v4, v3, v4
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v10, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v4, s2, v2
	v_mul_lo_u32 v6, s5, v2
	v_mul_lo_u32 v5, s2, v3
	s_lshr_b32 s5, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s6, s5
	s_ashr_i32 s16, s5, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v5
	v_mul_lo_u32 v5, s2, v2
	v_add_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v2, v5
	v_mul_lo_u32 v7, v2, v4
	v_mul_hi_u32 v9, v2, v4
	v_mul_hi_u32 v10, v3, v5
	v_mul_lo_u32 v5, v3, v5
	v_mul_hi_u32 v11, v3, v4
	v_mul_lo_u32 v4, v3, v4
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v10, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v10, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, v8, v9, 0
	v_mul_hi_u32 v11, v8, v6
	v_mad_u64_u32 v[4:5], null, v10, v6, 0
	v_mad_u64_u32 v[6:7], null, v10, v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v3, v5, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	v_mul_lo_u32 v6, s11, v4
	v_mad_u64_u32 v[2:3], null, s10, v4, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, s10, v5
	v_sub_co_u32 v2, vcc_lo, v8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v3, v5, v6
	v_add_nc_u32_e32 v6, 2, v4
	v_sub_nc_u32_e32 v5, v10, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v5, s2, s11, v5, vcc_lo
	v_sub_co_u32 v7, s2, v2, s10
	v_sub_co_ci_u32_e32 v3, vcc_lo, v10, v3, vcc_lo
	v_subrev_co_ci_u32_e64 v5, s2, 0, v5, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s10, v7
	s_lshr_b32 s2, s3, 31
	s_add_i32 s2, s3, s2
	v_cndmask_b32_e64 v7, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v5
	s_ashr_i32 s15, s2, 1
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s10, v2
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s11, v5
	v_cndmask_b32_e32 v5, v9, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s11, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v2, v10, v2 :: v_dual_add_nc_u32 v7, 1, v4
	v_cmp_ne_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v7, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v5, v4, v3 :: v_dual_mov_b32 v4, 0
	v_add_nc_u32_e32 v7, s4, v5
	v_mul_lo_u32 v2, v5, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v8, v2
	v_add_nc_u32_e32 v2, s3, v5
	v_add_nc_u32_e32 v8, s4, v6
	s_lshl_b64 s[4:5], s[12:13], 2
.LBB0_3:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_7
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v3, s15, v5
	v_ashrrev_i32_e32 v11, 31, v5
	v_mul_lo_u32 v13, v5, s11
	v_mad_u64_u32 v[9:10], null, v5, s10, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v14, s16, v3
	v_mul_lo_u32 v15, v11, s10
	v_ashrrev_i32_e32 v16, 31, v2
	v_add_nc_u32_e32 v19, s16, v3
	v_mul_lo_u32 v17, v2, s11
	v_ashrrev_i32_e32 v18, 31, v14
	v_mad_u64_u32 v[11:12], null, v2, s10, 0
	v_mul_lo_u32 v16, v16, s10
	v_add3_u32 v10, v10, v13, v15
	v_ashrrev_i32_e32 v13, 31, v19
	v_mul_lo_u32 v15, v18, s10
	v_mul_lo_u32 v18, v14, s11
	v_mad_u64_u32 v[2:3], null, v14, s10, 0
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add3_u32 v12, v12, v17, v16
	v_mul_lo_u32 v16, v13, s10
	v_mul_lo_u32 v17, v19, s11
	v_mad_u64_u32 v[13:14], null, v19, s10, 0
	v_add3_u32 v3, v3, v18, v15
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_u32 v9, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	v_add3_u32 v14, v14, v17, v16
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v11, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[15:16], 2, v[13:14]
	v_add_co_u32 v13, vcc_lo, s8, v2
	v_mov_b32_e32 v2, v6
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, s8, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
	s_mov_b32 s13, 0
.LBB0_5:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[17:18], 2, v[2:3]
	v_add_nc_u32_e32 v2, 1, v2
	v_add_co_u32 v19, vcc_lo, v9, v17
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v20, vcc_lo, v10, v18, vcc_lo
	v_add_co_u32 v21, vcc_lo, v11, v17
	v_add_co_ci_u32_e32 v22, vcc_lo, v12, v18, vcc_lo
	v_add_co_u32 v23, vcc_lo, v13, v17
	v_add_co_ci_u32_e32 v24, vcc_lo, v14, v18, vcc_lo
	v_add_co_u32 v17, vcc_lo, v15, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, v16, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v25, vcc_lo, v23, s4
	v_add_co_ci_u32_e32 v26, vcc_lo, s5, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v27, vcc_lo, v17, s4
	v_add_co_ci_u32_e32 v28, vcc_lo, s5, v18, vcc_lo
	v_add_co_u32 v29, vcc_lo, v19, s4
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v20, vcc_lo
	v_add_co_u32 v31, vcc_lo, v21, s4
	v_add_co_ci_u32_e32 v32, vcc_lo, s5, v22, vcc_lo
	s_clause 0x7
	global_load_b32 v3, v[19:20], off
	global_load_b32 v19, v[21:22], off
	global_load_b32 v20, v[23:24], off
	global_load_b32 v17, v[17:18], off
	global_load_b32 v18, v[25:26], off
	global_load_b32 v21, v[27:28], off
	global_load_b32 v22, v[29:30], off
	global_load_b32 v23, v[31:32], off
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v18, v21, v18
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v21, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v18, v17 :: v_dual_sub_f32 v18, v21, v19
	v_add_f32_e32 v17, v20, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v3, v18
	v_cvt_f64_f32_e32 v[17:18], v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[19:20], v3
	v_fma_f64 v[17:18], v[17:18], 2.0, -v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v3, v[17:18]
	v_add_nc_u32_e32 v17, s12, v2
	v_cmp_gt_f32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v3, v3, -v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_i32_e32 vcc_lo, v17, v8
	v_cmp_gt_f32_e64 s2, v3, v4
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v3, s2
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow121
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_7:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s3, v5
	v_cmp_ge_i32_e32 vcc_lo, v2, v7
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_3
; %bb.8:                                ; %Flow123
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_9:                                ; %._crit_edge100
	s_mul_i32 s2, s6, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s2, 18
	v_cvt_f32_i32_e32 v2, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v3, null, v2, v2, v4
	v_rcp_f32_e32 v5, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v3, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v4, v2, v4
	v_mul_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v3, v7, v6
	v_fmac_f32_e32 v7, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v7, v6
	v_div_fmas_f32 v3, v3, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v2, v3, v2, v4
	v_cmp_lt_f32_e32 vcc_lo, 0x3e428f5c, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_load_b64 s[0:1], s[0:1], 0x28
	v_mov_b32_e32 v2, 1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9ID3kernelPfmPiiiiS0_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9ID3kernelPfmPiiiiS0_S_S_, .Lfunc_end0-_Z9ID3kernelPfmPiiiiS0_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1728
; NumSgprs: 19
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9ID3kernelPfmPiiiiS0_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z9ID3kernelPfmPiiiiS0_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
