
__global__ void Kernel_4 (int* B,int* D, int* Kernel_4_output, int* Start_A, int* Start_B, int* Length_Seq_K4, 
							int K3_Length, int K3_Report, int K3_Safety, int K_3_R, int MyProc,
							int Start_Th1, int End_Th1,int K4_S1, int K4_S2,int K4_S3)
{
   
    for(int Sub_Block =(MyProc * K_3_R + blockIdx.x); Sub_Block < ((MyProc+1)*K_3_R); Sub_Block += gridDim.x)
	{
		for (int Sub_Thread1=Start_Th1+threadIdx.x; Sub_Thread1<End_Th1; Sub_Thread1+=blockDim.x)
		{			
			int Sub_Thread = Sub_Thread1 % blockDim.x;
			int A_Loc = Start_A[Sub_Thread1] * K3_Safety * K3_Length + Sub_Block * K3_Safety * K3_Length * K3_Report;
			int B_Loc = Start_B[Sub_Thread1] * K3_Safety * K3_Length + Sub_Block * K3_Safety * K3_Length * K3_Report;
			int End_A = Length_Seq_K4[Start_A[Sub_Thread1] + Sub_Block * K3_Report];
			int End_B = Length_Seq_K4[Start_B[Sub_Thread1] + Sub_Block * K3_Report];

			for (int i = 0; i<End_B; i++ )
			{
				for (int j = 0; j<End_A; j++) 
				{
					int D_Sim;
					int Num  =  i   *(K3_Length+1) + j + Sub_Thread*(K3_Length+1)*(K3_Length+1) + Sub_Block * (K3_Length+1)*(K3_Length+1)*(blockDim.x+1);
					int Num1 = (i+1)*(K3_Length+1) + j + Sub_Thread*(K3_Length+1)*(K3_Length+1) + Sub_Block * (K3_Length+1)*(K3_Length+1)*(blockDim.x+1);
											
					if (B[A_Loc + j]==B[B_Loc + i])
						D_Sim = D[Num]+K4_S1;
					else
						D_Sim=D[Num]+K4_S2;
					
					int F = D[Num+1] + K4_S3;
					int E = D[Num1]  + K4_S3; 
					
					D[Num1+1] = min(min(E,F),D_Sim);             
				}
			}
			int Index_1 = Sub_Thread1 + Sub_Block *  K3_Report * K3_Report;
			int Num1 = (End_B)*(K3_Length+1) + End_A-1 + Sub_Thread*(K3_Length+1)*(K3_Length+1) + Sub_Block * (K3_Length+1)*(K3_Length+1)*(blockDim.x+1); 
			Kernel_4_output[Index_1] = D[Num1+1];
		}
	}
}
//	__syncthreads();


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	.file	"tmpxft_00258189_00000000-6_SW_kernel_4.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z8Kernel_4PiS_S_S_S_S_iiiiiiiiiiPiS_S_S_S_S_iiiiiiiiii
	.type	_Z47__device_stub__Z8Kernel_4PiS_S_S_S_S_iiiiiiiiiiPiS_S_S_S_S_iiiiiiiiii, @function
_Z47__device_stub__Z8Kernel_4PiS_S_S_S_S_iiiiiiiiiiPiS_S_S_S_S_iiiiiiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 288
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z47__device_stub__Z8Kernel_4PiS_S_S_S_S_iiiiiiiiiiPiS_S_S_S_S_iiiiiiiiii, .-_Z47__device_stub__Z8Kernel_4PiS_S_S_S_S_iiiiiiiiiiPiS_S_S_S_S_iiiiiiiiii
	.globl	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.type	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii, @function
_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z8Kernel_4PiS_S_S_S_S_iiiiiiiiiiPiS_S_S_S_S_iiiiiiiiii
	.cfi_endproc
.LFE2033:
	.size	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii, .-_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>

__global__ void Kernel_4 (int* B,int* D, int* Kernel_4_output, int* Start_A, int* Start_B, int* Length_Seq_K4, 
							int K3_Length, int K3_Report, int K3_Safety, int K_3_R, int MyProc,
							int Start_Th1, int End_Th1,int K4_S1, int K4_S2,int K4_S3)
{
   
    for(int Sub_Block =(MyProc * K_3_R + blockIdx.x); Sub_Block < ((MyProc+1)*K_3_R); Sub_Block += gridDim.x)
	{
		for (int Sub_Thread1=Start_Th1+threadIdx.x; Sub_Thread1<End_Th1; Sub_Thread1+=blockDim.x)
		{			
			int Sub_Thread = Sub_Thread1 % blockDim.x;
			int A_Loc = Start_A[Sub_Thread1] * K3_Safety * K3_Length + Sub_Block * K3_Safety * K3_Length * K3_Report;
			int B_Loc = Start_B[Sub_Thread1] * K3_Safety * K3_Length + Sub_Block * K3_Safety * K3_Length * K3_Report;
			int End_A = Length_Seq_K4[Start_A[Sub_Thread1] + Sub_Block * K3_Report];
			int End_B = Length_Seq_K4[Start_B[Sub_Thread1] + Sub_Block * K3_Report];

			for (int i = 0; i<End_B; i++ )
			{
				for (int j = 0; j<End_A; j++) 
				{
					int D_Sim;
					int Num  =  i   *(K3_Length+1) + j + Sub_Thread*(K3_Length+1)*(K3_Length+1) + Sub_Block * (K3_Length+1)*(K3_Length+1)*(blockDim.x+1);
					int Num1 = (i+1)*(K3_Length+1) + j + Sub_Thread*(K3_Length+1)*(K3_Length+1) + Sub_Block * (K3_Length+1)*(K3_Length+1)*(blockDim.x+1);
											
					if (B[A_Loc + j]==B[B_Loc + i])
						D_Sim = D[Num]+K4_S1;
					else
						D_Sim=D[Num]+K4_S2;
					
					int F = D[Num+1] + K4_S3;
					int E = D[Num1]  + K4_S3; 
					
					D[Num1+1] = min(min(E,F),D_Sim);             
				}
			}
			int Index_1 = Sub_Thread1 + Sub_Block *  K3_Report * K3_Report;
			int Num1 = (End_B)*(K3_Length+1) + End_A-1 + Sub_Thread*(K3_Length+1)*(K3_Length+1) + Sub_Block * (K3_Length+1)*(K3_Length+1)*(blockDim.x+1); 
			Kernel_4_output[Index_1] = D[Num1+1];
		}
	}
}
//	__syncthreads();


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	.text
	.file	"SW_kernel_4.hip"
	.globl	_Z23__device_stub__Kernel_4PiS_S_S_S_S_iiiiiiiiii # -- Begin function _Z23__device_stub__Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.type	_Z23__device_stub__Kernel_4PiS_S_S_S_S_iiiiiiiiii,@function
_Z23__device_stub__Kernel_4PiS_S_S_S_S_iiiiiiiiii: # @_Z23__device_stub__Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__Kernel_4PiS_S_S_S_S_iiiiiiiiii, .Lfunc_end0-_Z23__device_stub__Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii,@object # @_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.p2align	3, 0x0
_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii:
	.quad	_Z23__device_stub__Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.size	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii ; -- Begin function _Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.globl	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
	.p2align	8
	.type	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii,@function
_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii:      ; @_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s8, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_add_i32 s25, s2, s15
	s_add_i32 s7, s2, s7
	s_cmp_ge_i32 s25, s7
	s_cbranch_scc1 .LBB0_15
; %bb.1:                                ; %.lr.ph125
	s_clause 0x3
	s_load_b256 s[12:19], s[0:1], 0x0
	s_load_b32 s26, s[0:1], 0x58
	s_load_b64 s[2:3], s[0:1], 0x50
	s_load_b128 s[20:23], s[0:1], 0x20
	v_add_nc_u32_e32 v10, s9, v0
	s_add_u32 s8, s0, 0x58
	s_mul_i32 s0, s6, s5
	s_addc_u32 s9, s1, 0
	s_add_i32 s28, s4, 1
	v_cmp_gt_i32_e32 vcc_lo, s10, v10
	s_mul_i32 s27, s6, s4
	s_mul_i32 s33, s0, s4
	s_mul_i32 s0, s28, s28
	s_mul_i32 s29, s27, s5
	s_mul_i32 s4, s33, s25
	s_mul_i32 s30, s25, s0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s31, s14, 4
	s_mul_i32 s33, s33, s26
	s_addc_u32 s34, s15, 0
	s_mul_i32 s35, s26, s0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
	s_and_saveexec_b32 s36, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.3:                                ; %.lr.ph121
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_load_b32 s0, s[8:9], 0xc
	s_mul_i32 s38, s25, s5
	s_mul_i32 s6, s29, s25
	s_mul_i32 s39, s38, s5
	s_mov_b32 s41, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s37, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s37
	s_sub_i32 s0, 0, s37
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s0, v0
	s_add_i32 s0, s37, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_mul_i32 s40, s0, s25
	s_mul_i32 s24, s30, s0
	v_mul_hi_u32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v10 :: v_dual_add_nc_u32 v11, v0, v1
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s42, exec_lo
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s0, s20, v1
	v_add_co_ci_u32_e64 v4, s0, s21, v2, s0
	v_add_co_u32 v1, s0, s18, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, s19, v2, s0
	global_load_b32 v4, v[3:4], off
	global_load_b32 v5, v[1:2], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v1, s38, v4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v6, s38, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s0, s22, v1
	v_add_co_ci_u32_e64 v2, s0, s23, v2, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s0, s22, v6
	v_add_co_ci_u32_e64 v7, s0, s23, v7, s0
	s_clause 0x1
	global_load_b32 v1, v[1:2], off
	global_load_b32 v12, v[6:7], off
	v_mul_hi_u32 v2, v0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s37
	v_sub_nc_u32_e32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v3, s37, v2
	v_cmp_le_u32_e64 s0, s37, v2
	v_cndmask_b32_e64 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v3, s37, v2
	v_cmp_le_u32_e64 s0, s37, v2
	v_cndmask_b32_e64 v13, v2, v3, s0
	s_waitcnt vmcnt(1)
	v_cmpx_lt_i32_e32 0, v1
	s_cbranch_execz .LBB0_13
; %bb.5:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_mad_u64_u32 v[2:3], null, s27, v4, s[6:7]
	v_mad_u64_u32 v[3:4], null, s27, v5, s[4:5]
	v_mul_lo_u32 v14, s28, v13
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e64 s0, 1, v12
	v_mov_b32_e32 v4, 0
	s_mov_b32 s43, 0
.LBB0_6:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_10 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v15, 1, v4
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
; %bb.7:                                ; %.preheader.._crit_edge_crit_edge
                                        ;   in Loop: Header=BB0_6 Depth=3
	v_add_nc_u32_e32 v4, 1, v4
                                        ; implicit-def: $vgpr15
; %bb.8:                                ; %Flow184
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_and_not1_saveexec_b32 s44, s1
	s_cbranch_execz .LBB0_12
; %bb.9:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, v2, v4
	v_add_nc_u32_e32 v16, v14, v4
	v_mov_b32_e32 v4, v3
	s_mov_b32 s45, 0
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[8:9], 2, v[5:6]
	v_mad_u64_u32 v[6:7], null, s28, v16, s[24:25]
	v_mov_b32_e32 v16, v12
	v_add_co_u32 v8, s1, s12, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, s13, v9, s1
.LBB0_10:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v17, s28, v6
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_nc_u32_e32 v16, -1, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[19:20], 2, v[4:5]
	v_ashrrev_i32_e32 v18, 31, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[21:22], 2, v[6:7]
	v_add_nc_u32_e32 v4, 1, v4
	v_add_nc_u32_e32 v6, 1, v6
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_add_co_u32 v19, s1, s12, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v20, s1, s13, v20, s1
	v_add_co_u32 v21, s1, s14, v21
	s_clause 0x1
	global_load_b32 v5, v[19:20], off
	global_load_b32 v7, v[8:9], off
	v_add_co_ci_u32_e64 v22, s1, s15, v22, s1
	v_add_co_u32 v17, s1, s14, v17
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v18, s1, s15, v18, s1
	s_clause 0x1
	global_load_b64 v[19:20], v[21:22], off
	global_load_b32 v21, v[17:18], off
	v_mov_b32_e32 v22, s11
	s_waitcnt vmcnt(2)
	v_cmp_eq_u32_e64 s1, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, s2, v22, s1
	v_cmp_eq_u32_e64 s1, 0, v16
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v7, s3, v20
	v_add_nc_u32_e32 v5, v19, v5
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v19, s3, v21
	s_or_b32 s45, s1, s45
	s_delay_alu instid0(VALU_DEP_1)
	v_min3_i32 v5, v19, v7, v5
	global_store_b32 v[17:18], v5, off offset:4
	s_and_not1_b32 exec_lo, exec_lo, s45
	s_cbranch_execnz .LBB0_10
; %bb.11:                               ; %Flow
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s45
	v_mov_b32_e32 v4, v15
.LBB0_12:                               ; %Flow185
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s1, v4, v1
	s_or_b32 s43, s1, s43
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s43
	s_cbranch_execnz .LBB0_6
.LBB0_13:                               ; %Flow187
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s42
	v_add_nc_u32_e32 v4, s40, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v4, s28, v[1:2]
	v_mul_lo_u32 v1, v2, s28
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v12, v1, -1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, s0, s31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v2, s0, s34, v2, s0
	global_load_b32 v3, v[1:2], off
	v_add_nc_u32_e32 v1, s39, v0
	v_add_nc_u32_e32 v0, s37, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e64 s0, s10, v0
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s41, s0, s41
	v_add_co_u32 v1, s1, s16, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s1, s17, v2, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v[1:2], v3, off
	s_and_not1_b32 exec_lo, exec_lo, s41
	s_cbranch_execnz .LBB0_4
.LBB0_14:                               ; %Flow189
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s36
	s_add_i32 s25, s26, s25
	s_add_i32 s4, s4, s33
	s_add_i32 s30, s30, s35
	s_cmp_ge_i32 s25, s7
	s_cbranch_scc0 .LBB0_2
.LBB0_15:                               ; %._crit_edge126
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 46
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii, .Lfunc_end0-_Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1168
; NumSgprs: 48
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 48
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     48
    .sgpr_spill_count: 0
    .symbol:         _Z8Kernel_4PiS_S_S_S_S_iiiiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
