#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>

#define DEBUG

typedef unsigned long ulong;
typedef unsigned short ushort;

__device__ ushort add(long a, long b)
{
	return (ushort)((a + b) % 65536l);
}

__device__ ushort multiply(long a, long b)
{
	long ch, cl, c;

	if (a == 0) a = 65536l;
	if (b == 0) b = 65536l;
	c = a * b;
	if (c) {
		ch = (c >> 16) & 65535l;
		cl = c & 65535l;
		if (cl >= ch) return (ushort) (cl - ch);
		return (ushort) ((cl - ch + 65537l) & 65535l);
	}
	if (a == b) return 1;
	return 0;
}

__global__ void IDEA_encryption(ushort *X, ushort *Y, long *K)
{
	
	ushort a, r, t0, t1, t2;
	//ushort i;	
	int tid = threadIdx.x;
	for (r = 0; r < 8; r++) {
		X[tid * 4 + 0] = multiply(X[tid * 4 + 0], K[r*6+0]);
		X[tid * 4 + 3] = multiply(X[tid * 4 + 3], K[r*6+3]);
		X[tid * 4 + 1] = add(X[tid * 4 + 1], K[r*6+1]);
		X[tid * 4 + 2] = add(X[tid * 4 + 2], K[r*6+2]);
		t0 = multiply(K[r*6+4], X[tid * 4 + 0] ^ X[tid * 4 + 2]);
		t1 = multiply(K[r*6+5], add(t0, X[tid * 4 + 1] ^ X[tid * 4 + 3]));
		t2 = add(t0, t1);
		X[tid * 4 + 0] ^= t1;
		X[tid * 4 + 3] ^= t2;
		a = X[tid * 4 + 1] ^ t2;
		X[tid * 4 + 1] = X[tid * 4 + 2] ^ t1;
		X[tid * 4 + 2] = a;
		#ifdef DEBUG
		/*printf("%u ", r + 1);
		for (i = 0; i < 6; i++)
			printf("%hu ", (ushort) K[r*6+i]);
		printf("%hu %hu %hu %hu\n", X[0], X[1], X[2], X[3]);*/
		#endif
	}
	Y[tid * 4 + 0] = multiply(X[tid * 4 + 0], K[8*6+0]);
	Y[tid * 4 + 3] = multiply(X[tid * 4 + 3], K[8*6+3]);
	Y[tid * 4 + 1] = add(X[tid * 4 + 2], K[8*6+1]);
	Y[tid * 4 + 2] = add(X[tid * 4 + 1], K[8*6+2]);
	#ifdef DEBUG
	/*printf("9 ");
	for (i = 0; i < 6; i++)
		printf("%hu ", (ushort) K[8*6+i]);
	printf("%hu %hu %hu %hu\n", Y[0], Y[1], Y[2], Y[3]);*/
	#endif
}

__device__ ushort bits_to_ushort(ushort *bits)
{
	ushort i, value = bits[0];

	for (i = 1; i < 16; i++)
		value = (ushort) ((value << 1) + bits[i]);
	return value;
}

__device__ void ushort_to_bits(ushort number, ushort *bits)
{
	ushort i, temp[16];
	int tid = threadIdx.x;
	for (i = 0; i < 16; i++) {
		temp[i] = (ushort) (number & 1);
		number >>= 1;
	}
	/*for (i = 0; i < 16; i++)
		bits[i] = temp[15 - i];*/
	if(tid<16)
	bits[tid] = temp[15-tid];

}

__device__ void cyclic_left_shift(ushort index, ushort *bits1,
                       ushort *bits2, long *K)
{
	ushort i;
	int tid = threadIdx.x;
	if (index == 0) {
		for (i = 0; i < 6; i++)
			ushort_to_bits((ushort) K[0*6+i], bits1 + 16 * i);
		ushort_to_bits((ushort) K[1*6+0], bits1 + 96);
		ushort_to_bits((ushort) K[1*6+1], bits1 + 112);
	}
	/*i = 0;
	for (j = 25; j < 128; j++)
		bits2[i++] = bits1[j];
	for (j = 0; j < 25; j++)
		bits2[i++] = bits1[j];*/
	if( tid < 103)
  		bits2[tid] = bits1[tid + 25];
	else if(tid >= 103 && tid <128)
  		bits2[tid] = bits1[tid - 103];

	
	switch (index) {
		case 0 :
			/*for (i = 2; i < 6; i++)
				K[1][i] = bits_to_ushort(bits2 + 16 * (i - 2));
			for (i = 0; i < 4; i++)
				K[2][i] = bits_to_ushort(bits2 + 64 + 16 * i);*/
			if(tid >=2 && tid < 6)
				K[1*6+tid] = bits_to_ushort(bits2 + 16 * (tid - 2 ));
			if(tid < 4)
				K[2*6+tid] = bits_to_ushort(bits2 + 64 + 16 * tid);

		break;
		case 1 :
			K[2*6+4] = bits_to_ushort(bits2);
			K[2*6+5] = bits_to_ushort(bits2 + 16);
			/*for (i = 0; i < 6; i++)
				K[3][i] = bits_to_ushort(bits2 + 32 + 16 * i);*/
			if(tid < 6)
				K[3*6+tid] = bits_to_ushort(bits2 + 32 + 16 * tid);
		break;

		case 2 :
	
			/*for (i = 0; i < 6; i++)
				K[4*6+i] = bits_to_ushort(bits2 + 16 * i);*/
			if(tid < 6)
				K[4*6+tid] = bits_to_ushort(bits2 + 16 * tid);
			K[5*6+0] = bits_to_ushort(bits2 + 96);
			K[5*6+1] = bits_to_ushort(bits2 + 112);
		break;
		case 3 :
	
			/*for (i = 2; i < 6; i++)
				K[5][i] = bits_to_ushort(bits2 + 16 * (i - 2));
			for (i = 0; i < 4; i++)
				K[6][i] = bits_to_ushort(bits2 + 64 + 16 * i);*/
    
			if(tid >=2 && tid < 6)
				        K[5*6+tid] = bits_to_ushort(bits2 + 16 * (tid - 2));
			 if(tid < 4)
				        K[6*6+tid] = bits_to_ushort(bits2 + 64 + 16 * tid);
		break;
		case 4 :
			K[6*6+4] = bits_to_ushort(bits2);
			K[6*6+5] = bits_to_ushort(bits2 + 16);

			/*for (i = 0; i < 6; i++)
				K[7][i] = bits_to_ushort(bits2 + 32 + 16 * i);*/

			if(tid < 6)
				K[7*6+tid] = bits_to_ushort(bits2 + 32 + 16 * tid);
		break;
		case 5 :
			/*for (i = 0; i < 4; i++)
				K[8][i] = bits_to_ushort(bits2 + 16 * i);*/

			if(tid < 4)
		        K[8*6+tid] = bits_to_ushort(bits2 + 16 * tid);
		break;
	}
}

__global__ void IDEA_encryption_key_schedule(ushort *key, long *K)
{
	ushort bits1[128], bits2[128];
	int tid = threadIdx.x;

	//for (i = 0; i < 6; i++) K[0][i] = key[i];
	if(tid < 6)
	  	K[0*6+tid] = key[tid];
	if(tid == 32)
  		K[1*6+0] = key[6], K[1*6+1] = key[7];
  
	cyclic_left_shift(0, bits1, bits2, K);
	cyclic_left_shift(1, bits2, bits1, K);
	cyclic_left_shift(2, bits1, bits2, K);
	cyclic_left_shift(3, bits2, bits1, K);
	cyclic_left_shift(4, bits1, bits2, K);
	cyclic_left_shift(5, bits2, bits1, K);
	
}

__device__ void extended_euclidean(long a, long b, long *x, long *y, long *d)
{
	long q, r, x1, x2, y1, y2;

	if (b == 0) {
		*d = a, *x = 1, *y = 0;
		return;
	}
	x2 = 1, x1 = 0, y2 = 0, y1 = 1;
	while (b > 0) {
		q = a / b, r = a - q * b;
		*x = x2 - q * x1;
		*y = y2 - q * y1;
		a = b, b = r, x2 = x1, x1 = *x, y2 = y1, y1 = *y;
	}
	*d = a, *x = x2, *y = y2;
}

__device__ long inv(ushort ub)
{
	long d, a = 65537l, b = ub, x, y;

	if (ub == 0) return 65536l;
	extended_euclidean(a, b, &x, &y, &d);
	if (y >= 0) return (ushort) y;
	return (ushort) (y + 65537l);
}

__global__ void IDEA_decryption_key_schedule(long *K, long *L)
{
	ushort r8, r9;
	int tid = threadIdx.x;
	if(tid == 0){
		L[0*6+0] = inv((ushort) K[8*6+0]);
		L[0*6+1] = - K[8*6+1];
		L[0*6+2] = - K[8*6+2];
		L[0*6+3] = inv((ushort) K[8*6+3]);
		L[0*6+4] =  K[7*6+4];
		L[0*6+5] =  K[7*6+5];
}

	if(tid>0 && tid <8){
    		r9 = (ushort) (8 - tid);
    		r8 = (ushort) (7 - tid);
    		L[tid*6+0] = inv((ushort) K[r9*6+0]);
    		L[tid*6+1] = - K[r9*6+2];
    		L[tid*6+2] = - K[r9*6+1];
    		L[tid*6+3] = inv((ushort) K[r9*6+3]);
    		L[tid*6+4] = K[r8*6+4];
    		L[tid*6+5] = K[r8*6+5];
	}

	if(tid == 0){
		L[8*6+0] = inv((ushort) K[0*6+0]);
		L[8*6+1] = - K[0*6+1];
		L[8*6+2] = - K[0*6+2];
		L[8*6+3] = inv((ushort) K[0*6+3]);
		L[8*6+4] = L[8*6+6] = 0;
	}
}

int main(int argc, char *argv[])
{	
	/*int devcount;
	cudaGetDeviceCount(&devcount);
	printf("%d ",devcount);
	for(int i=0;i<devcount;i++){
		cudaDeviceProp prop;
		cudaGetDeviceProperties(&prop , i);
		printf("%d ",prop.warpSize);
	}*/
	int tc=512;
	int count;
	long *K, *L;K=NULL;L=NULL;
	long *dev_K , *dev_L; dev_K=NULL; dev_L = NULL;
	ushort key[8] = {1, 2, 3, 4, 5, 6, 7, 8};
	ushort *X, *Y;
	ushort *dev_X, *dev_Y;
	ushort *dev_key = NULL;
  
	FILE *in_file  = fopen("/home/pratik/input.jpg", "r"); 
	FILE *out_file = fopen("/home/pratik/output.jpg", "w"); 
	FILE *mid_w = fopen("/home/pratik/encrypt.jpg", "w");
	if (in_file == NULL || out_file == NULL) 
	{
		printf("Error! Could not open file\n"); 
		exit(-1); 
	}
	
	K = (long *)malloc(54 * sizeof(long ));
	L = (long *)malloc(54 * sizeof(long ));

	cudaMalloc((void **) &dev_key , 16);
	cudaMemcpy( dev_key, key, 16, cudaMemcpyHostToDevice);

 	size_t pitch;
	cudaMallocPitch(&dev_K, &pitch, sizeof(long)*9, 6);
	cudaMallocPitch(&dev_L, &pitch, sizeof(long)*9, 6);
	
	IDEA_encryption_key_schedule<<<1,128>>>(dev_key, dev_K);

	cudaMemcpy( K , dev_K, 9*6* sizeof(long *),cudaMemcpyDeviceToHost);

	X = (ushort *)malloc(tc * 4 * sizeof(ushort));
	Y = (ushort *)malloc(tc * 4 * sizeof(ushort));

	count = fread( X,2,tc*4,in_file);

	cudaMalloc((void **) &dev_Y , tc*4*2);
	cudaMalloc((void **) &dev_X , tc*4*2);	

	while(count==tc * 4){
	   	cudaMemcpy( dev_X, X,tc * 8, cudaMemcpyHostToDevice);
   
		IDEA_encryption<<<1,tc>>>(dev_X, dev_Y, dev_K);

		cudaMemcpy( Y, dev_Y,tc * 8, cudaMemcpyDeviceToHost);

		fwrite( Y,2,tc*4,mid_w);
		count = fread( X,2,tc*4,in_file);
	}
	if(count < tc*4 && count > 0){
		fwrite( X,2,count,mid_w);
	}
	
	fclose(mid_w);
	FILE *mid_file = fopen("/home/pratik/encrypt.jpg", "r");

	IDEA_decryption_key_schedule<<<1,8>>>(dev_K, dev_L);

	count = fread( Y,2,tc*4,mid_file);
	while(count==tc * 4){
		cudaMemcpy( dev_Y, Y,tc * 8, cudaMemcpyHostToDevice);
	
		IDEA_encryption<<<1,tc>>>(dev_Y, dev_X, dev_L);
	
		cudaMemcpy( X, dev_X,tc * 8, cudaMemcpyDeviceToHost);
 
		fwrite( X,2,tc*4,out_file);
		count = fread( Y,2,tc*4,mid_file);
	}
	if(count < tc*4 && count > 0){
		fwrite( Y,2,count,out_file);
	} 
	free(K);
	free(L);
	return 0;
}

	.file	"tmpxft_0027c35b_00000000-6_idea.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z3addll
	.type	_Z3addll, @function
_Z3addll:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z3addll, .-_Z3addll
	.globl	_Z8multiplyll
	.type	_Z8multiplyll, @function
_Z8multiplyll:
.LFB2184:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z3addll
	.cfi_endproc
.LFE2184:
	.size	_Z8multiplyll, .-_Z8multiplyll
	.globl	_Z14bits_to_ushortPt
	.type	_Z14bits_to_ushortPt, @function
_Z14bits_to_ushortPt:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z14bits_to_ushortPt, .-_Z14bits_to_ushortPt
	.globl	_Z14ushort_to_bitstPt
	.type	_Z14ushort_to_bitstPt, @function
_Z14ushort_to_bitstPt:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2030:
	.size	_Z14ushort_to_bitstPt, .-_Z14ushort_to_bitstPt
	.globl	_Z17cyclic_left_shifttPtS_Pl
	.type	_Z17cyclic_left_shifttPtS_Pl, @function
_Z17cyclic_left_shifttPtS_Pl:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z17cyclic_left_shifttPtS_Pl, .-_Z17cyclic_left_shifttPtS_Pl
	.globl	_Z18extended_euclideanllPlS_S_
	.type	_Z18extended_euclideanllPlS_S_, @function
_Z18extended_euclideanllPlS_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2032:
	.size	_Z18extended_euclideanllPlS_S_, .-_Z18extended_euclideanllPlS_S_
	.globl	_Z3invt
	.type	_Z3invt, @function
_Z3invt:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2033:
	.size	_Z3invt, .-_Z3invt
	.globl	_Z39__device_stub__Z15IDEA_encryptionPtS_PlPtS_Pl
	.type	_Z39__device_stub__Z15IDEA_encryptionPtS_PlPtS_Pl, @function
_Z39__device_stub__Z15IDEA_encryptionPtS_PlPtS_Pl:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15IDEA_encryptionPtS_Pl(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L16:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z39__device_stub__Z15IDEA_encryptionPtS_PlPtS_Pl, .-_Z39__device_stub__Z15IDEA_encryptionPtS_PlPtS_Pl
	.globl	_Z15IDEA_encryptionPtS_Pl
	.type	_Z15IDEA_encryptionPtS_Pl, @function
_Z15IDEA_encryptionPtS_Pl:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z15IDEA_encryptionPtS_PlPtS_Pl
	.cfi_endproc
.LFE2060:
	.size	_Z15IDEA_encryptionPtS_Pl, .-_Z15IDEA_encryptionPtS_Pl
	.globl	_Z50__device_stub__Z28IDEA_encryption_key_schedulePtPlPtPl
	.type	_Z50__device_stub__Z28IDEA_encryption_key_schedulePtPlPtPl, @function
_Z50__device_stub__Z28IDEA_encryption_key_schedulePtPlPtPl:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z28IDEA_encryption_key_schedulePtPl(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L22:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z50__device_stub__Z28IDEA_encryption_key_schedulePtPlPtPl, .-_Z50__device_stub__Z28IDEA_encryption_key_schedulePtPlPtPl
	.globl	_Z28IDEA_encryption_key_schedulePtPl
	.type	_Z28IDEA_encryption_key_schedulePtPl, @function
_Z28IDEA_encryption_key_schedulePtPl:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z28IDEA_encryption_key_schedulePtPlPtPl
	.cfi_endproc
.LFE2062:
	.size	_Z28IDEA_encryption_key_schedulePtPl, .-_Z28IDEA_encryption_key_schedulePtPl
	.globl	_Z50__device_stub__Z28IDEA_decryption_key_schedulePlS_PlS_
	.type	_Z50__device_stub__Z28IDEA_decryption_key_schedulePlS_PlS_, @function
_Z50__device_stub__Z28IDEA_decryption_key_schedulePlS_PlS_:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z28IDEA_decryption_key_schedulePlS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L27:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z50__device_stub__Z28IDEA_decryption_key_schedulePlS_PlS_, .-_Z50__device_stub__Z28IDEA_decryption_key_schedulePlS_PlS_
	.globl	_Z28IDEA_decryption_key_schedulePlS_
	.type	_Z28IDEA_decryption_key_schedulePlS_, @function
_Z28IDEA_decryption_key_schedulePlS_:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z28IDEA_decryption_key_schedulePlS_PlS_
	.cfi_endproc
.LFE2064:
	.size	_Z28IDEA_decryption_key_schedulePlS_, .-_Z28IDEA_decryption_key_schedulePlS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"/home/pratik/input.jpg"
.LC2:
	.string	"w"
.LC3:
	.string	"/home/pratik/output.jpg"
.LC4:
	.string	"/home/pratik/encrypt.jpg"
.LC5:
	.string	"Error! Could not open file\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edx, %edx
	leaq	.LC1(%rip), %rdi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	.LC0(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r14, %rsi
	leaq	.LC4(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	.LC2(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	xorl	%eax, %eax
	movq	%rdx, 64(%rsp)
	movq	%rax, 32(%rsp)
	movq	%rax, 40(%rsp)
	movabsq	$1125912791875585, %rax
	movq	%rax, 104(%rsp)
	movabsq	$2251829878849541, %rax
	movq	%rax, 112(%rsp)
	call	fopen@PLT
	movq	%rbp, %rsi
	leaq	.LC3(%rip), %rdi
	movq	%rax, %r12
	call	fopen@PLT
	movq	%rbp, %rsi
	movq	%r13, %rdi
	movq	%rax, %rbx
	call	fopen@PLT
	movq	%rax, 16(%rsp)
	testq	%r12, %r12
	je	.L46
	testq	%rbx, %rbx
	jne	.L33
.L46:
	movl	$2, %edi
	leaq	.LC5(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L33:
	movl	$432, %edi
	leaq	72(%rsp), %r15
	call	malloc@PLT
	leaq	64(%rsp), %rdi
	movl	$16, %esi
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	movq	64(%rsp), %rdi
	leaq	104(%rsp), %rsi
	movl	$1, %ecx
	movl	$16, %edx
	call	cudaMemcpy@PLT
	leaq	32(%rsp), %rdi
	movl	$6, %ecx
	movq	%r15, %rsi
	movl	$72, %edx
	call	cudaMallocPitch@PLT
	leaq	40(%rsp), %rdi
	movl	$6, %ecx
	movq	%r15, %rsi
	movl	$72, %edx
	call	cudaMallocPitch@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rdi, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movq	32(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z50__device_stub__Z28IDEA_encryption_key_schedulePtPlPtPl
.L35:
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movl	$432, %edx
	movabsq	$4294967808, %r15
	call	cudaMemcpy@PLT
	movl	$4096, %edi
	call	malloc@PLT
	movl	$4096, %edi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%r12, %r8
	movl	$2048, %ecx
	movl	$2, %edx
	movl	$4096, %esi
	movq	%rax, 8(%rsp)
	call	__fread_chk@PLT
	leaq	56(%rsp), %rdi
	movl	$4096, %esi
	movl	%eax, %ebp
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
.L36:
	cmpl	$2048, %ebp
	jne	.L48
	movq	(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r15, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%r15, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rdi, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	movq	32(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z39__device_stub__Z15IDEA_encryptionPtS_PlPtS_Pl
.L37:
	movq	56(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdi
	movl	$2048, %edx
	movl	$2, %esi
	call	fwrite@PLT
	movq	(%rsp), %rdi
	movq	%r12, %r8
	movl	$2048, %ecx
	movl	$2, %edx
	movl	$4096, %esi
	call	__fread_chk@PLT
	movl	%eax, %ebp
	jmp	.L36
.L48:
	leal	-1(%rbp), %eax
	cmpl	$2046, %eax
	ja	.L39
	movq	16(%rsp), %rcx
	movq	(%rsp), %rdi
	movslq	%ebp, %rdx
	movl	$2, %esi
	call	fwrite@PLT
.L39:
	movq	16(%rsp), %rdi
	call	fclose@PLT
	movq	%r14, %rsi
	movq	%r13, %rdi
	call	fopen@PLT
	movl	$536870913, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$3, %rdx
	movl	$1, %ecx
	movq	%rax, %rbp
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdx, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rdi, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z50__device_stub__Z28IDEA_decryption_key_schedulePlS_PlS_
.L40:
	movq	8(%rsp), %rdi
	movq	%rbp, %r8
	movl	$2048, %ecx
	movl	$2, %edx
	movabsq	$4294967808, %r12
	movl	$4096, %esi
	call	__fread_chk@PLT
.L41:
	cmpl	$2048, %eax
	jne	.L49
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%r12, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rdi, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	40(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z39__device_stub__Z15IDEA_encryptionPtS_PlPtS_Pl
.L42:
	movq	48(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	movq	%rbx, %rcx
	movl	$2048, %edx
	movl	$2, %esi
	call	fwrite@PLT
	movq	8(%rsp), %rdi
	movq	%rbp, %r8
	movl	$2048, %ecx
	movl	$2, %edx
	movl	$4096, %esi
	call	__fread_chk@PLT
	jmp	.L41
.L49:
	leal	-1(%rax), %edx
	cmpl	$2046, %edx
	ja	.L44
	movq	8(%rsp), %rdi
	movslq	%eax, %rdx
	movq	%rbx, %rcx
	movl	$2, %esi
	call	fwrite@PLT
.L44:
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z28IDEA_decryption_key_schedulePlS_"
.LC7:
	.string	"_Z28IDEA_encryption_key_schedulePtPl"
.LC8:
	.string	"_Z15IDEA_encryptionPtS_Pl"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z28IDEA_decryption_key_schedulePlS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28IDEA_encryption_key_schedulePtPl(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15IDEA_encryptionPtS_Pl(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2066:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>

#define DEBUG

typedef unsigned long ulong;
typedef unsigned short ushort;

__device__ ushort add(long a, long b)
{
	return (ushort)((a + b) % 65536l);
}

__device__ ushort multiply(long a, long b)
{
	long ch, cl, c;

	if (a == 0) a = 65536l;
	if (b == 0) b = 65536l;
	c = a * b;
	if (c) {
		ch = (c >> 16) & 65535l;
		cl = c & 65535l;
		if (cl >= ch) return (ushort) (cl - ch);
		return (ushort) ((cl - ch + 65537l) & 65535l);
	}
	if (a == b) return 1;
	return 0;
}

__global__ void IDEA_encryption(ushort *X, ushort *Y, long *K)
{
	
	ushort a, r, t0, t1, t2;
	//ushort i;	
	int tid = threadIdx.x;
	for (r = 0; r < 8; r++) {
		X[tid * 4 + 0] = multiply(X[tid * 4 + 0], K[r*6+0]);
		X[tid * 4 + 3] = multiply(X[tid * 4 + 3], K[r*6+3]);
		X[tid * 4 + 1] = add(X[tid * 4 + 1], K[r*6+1]);
		X[tid * 4 + 2] = add(X[tid * 4 + 2], K[r*6+2]);
		t0 = multiply(K[r*6+4], X[tid * 4 + 0] ^ X[tid * 4 + 2]);
		t1 = multiply(K[r*6+5], add(t0, X[tid * 4 + 1] ^ X[tid * 4 + 3]));
		t2 = add(t0, t1);
		X[tid * 4 + 0] ^= t1;
		X[tid * 4 + 3] ^= t2;
		a = X[tid * 4 + 1] ^ t2;
		X[tid * 4 + 1] = X[tid * 4 + 2] ^ t1;
		X[tid * 4 + 2] = a;
		#ifdef DEBUG
		/*printf("%u ", r + 1);
		for (i = 0; i < 6; i++)
			printf("%hu ", (ushort) K[r*6+i]);
		printf("%hu %hu %hu %hu\n", X[0], X[1], X[2], X[3]);*/
		#endif
	}
	Y[tid * 4 + 0] = multiply(X[tid * 4 + 0], K[8*6+0]);
	Y[tid * 4 + 3] = multiply(X[tid * 4 + 3], K[8*6+3]);
	Y[tid * 4 + 1] = add(X[tid * 4 + 2], K[8*6+1]);
	Y[tid * 4 + 2] = add(X[tid * 4 + 1], K[8*6+2]);
	#ifdef DEBUG
	/*printf("9 ");
	for (i = 0; i < 6; i++)
		printf("%hu ", (ushort) K[8*6+i]);
	printf("%hu %hu %hu %hu\n", Y[0], Y[1], Y[2], Y[3]);*/
	#endif
}

__device__ ushort bits_to_ushort(ushort *bits)
{
	ushort i, value = bits[0];

	for (i = 1; i < 16; i++)
		value = (ushort) ((value << 1) + bits[i]);
	return value;
}

__device__ void ushort_to_bits(ushort number, ushort *bits)
{
	ushort i, temp[16];
	int tid = threadIdx.x;
	for (i = 0; i < 16; i++) {
		temp[i] = (ushort) (number & 1);
		number >>= 1;
	}
	/*for (i = 0; i < 16; i++)
		bits[i] = temp[15 - i];*/
	if(tid<16)
	bits[tid] = temp[15-tid];

}

__device__ void cyclic_left_shift(ushort index, ushort *bits1,
                       ushort *bits2, long *K)
{
	ushort i;
	int tid = threadIdx.x;
	if (index == 0) {
		for (i = 0; i < 6; i++)
			ushort_to_bits((ushort) K[0*6+i], bits1 + 16 * i);
		ushort_to_bits((ushort) K[1*6+0], bits1 + 96);
		ushort_to_bits((ushort) K[1*6+1], bits1 + 112);
	}
	/*i = 0;
	for (j = 25; j < 128; j++)
		bits2[i++] = bits1[j];
	for (j = 0; j < 25; j++)
		bits2[i++] = bits1[j];*/
	if( tid < 103)
  		bits2[tid] = bits1[tid + 25];
	else if(tid >= 103 && tid <128)
  		bits2[tid] = bits1[tid - 103];

	
	switch (index) {
		case 0 :
			/*for (i = 2; i < 6; i++)
				K[1][i] = bits_to_ushort(bits2 + 16 * (i - 2));
			for (i = 0; i < 4; i++)
				K[2][i] = bits_to_ushort(bits2 + 64 + 16 * i);*/
			if(tid >=2 && tid < 6)
				K[1*6+tid] = bits_to_ushort(bits2 + 16 * (tid - 2 ));
			if(tid < 4)
				K[2*6+tid] = bits_to_ushort(bits2 + 64 + 16 * tid);

		break;
		case 1 :
			K[2*6+4] = bits_to_ushort(bits2);
			K[2*6+5] = bits_to_ushort(bits2 + 16);
			/*for (i = 0; i < 6; i++)
				K[3][i] = bits_to_ushort(bits2 + 32 + 16 * i);*/
			if(tid < 6)
				K[3*6+tid] = bits_to_ushort(bits2 + 32 + 16 * tid);
		break;

		case 2 :
	
			/*for (i = 0; i < 6; i++)
				K[4*6+i] = bits_to_ushort(bits2 + 16 * i);*/
			if(tid < 6)
				K[4*6+tid] = bits_to_ushort(bits2 + 16 * tid);
			K[5*6+0] = bits_to_ushort(bits2 + 96);
			K[5*6+1] = bits_to_ushort(bits2 + 112);
		break;
		case 3 :
	
			/*for (i = 2; i < 6; i++)
				K[5][i] = bits_to_ushort(bits2 + 16 * (i - 2));
			for (i = 0; i < 4; i++)
				K[6][i] = bits_to_ushort(bits2 + 64 + 16 * i);*/
    
			if(tid >=2 && tid < 6)
				        K[5*6+tid] = bits_to_ushort(bits2 + 16 * (tid - 2));
			 if(tid < 4)
				        K[6*6+tid] = bits_to_ushort(bits2 + 64 + 16 * tid);
		break;
		case 4 :
			K[6*6+4] = bits_to_ushort(bits2);
			K[6*6+5] = bits_to_ushort(bits2 + 16);

			/*for (i = 0; i < 6; i++)
				K[7][i] = bits_to_ushort(bits2 + 32 + 16 * i);*/

			if(tid < 6)
				K[7*6+tid] = bits_to_ushort(bits2 + 32 + 16 * tid);
		break;
		case 5 :
			/*for (i = 0; i < 4; i++)
				K[8][i] = bits_to_ushort(bits2 + 16 * i);*/

			if(tid < 4)
		        K[8*6+tid] = bits_to_ushort(bits2 + 16 * tid);
		break;
	}
}

__global__ void IDEA_encryption_key_schedule(ushort *key, long *K)
{
	ushort bits1[128], bits2[128];
	int tid = threadIdx.x;

	//for (i = 0; i < 6; i++) K[0][i] = key[i];
	if(tid < 6)
	  	K[0*6+tid] = key[tid];
	if(tid == 32)
  		K[1*6+0] = key[6], K[1*6+1] = key[7];
  
	cyclic_left_shift(0, bits1, bits2, K);
	cyclic_left_shift(1, bits2, bits1, K);
	cyclic_left_shift(2, bits1, bits2, K);
	cyclic_left_shift(3, bits2, bits1, K);
	cyclic_left_shift(4, bits1, bits2, K);
	cyclic_left_shift(5, bits2, bits1, K);
	
}

__device__ void extended_euclidean(long a, long b, long *x, long *y, long *d)
{
	long q, r, x1, x2, y1, y2;

	if (b == 0) {
		*d = a, *x = 1, *y = 0;
		return;
	}
	x2 = 1, x1 = 0, y2 = 0, y1 = 1;
	while (b > 0) {
		q = a / b, r = a - q * b;
		*x = x2 - q * x1;
		*y = y2 - q * y1;
		a = b, b = r, x2 = x1, x1 = *x, y2 = y1, y1 = *y;
	}
	*d = a, *x = x2, *y = y2;
}

__device__ long inv(ushort ub)
{
	long d, a = 65537l, b = ub, x, y;

	if (ub == 0) return 65536l;
	extended_euclidean(a, b, &x, &y, &d);
	if (y >= 0) return (ushort) y;
	return (ushort) (y + 65537l);
}

__global__ void IDEA_decryption_key_schedule(long *K, long *L)
{
	ushort r8, r9;
	int tid = threadIdx.x;
	if(tid == 0){
		L[0*6+0] = inv((ushort) K[8*6+0]);
		L[0*6+1] = - K[8*6+1];
		L[0*6+2] = - K[8*6+2];
		L[0*6+3] = inv((ushort) K[8*6+3]);
		L[0*6+4] =  K[7*6+4];
		L[0*6+5] =  K[7*6+5];
}

	if(tid>0 && tid <8){
    		r9 = (ushort) (8 - tid);
    		r8 = (ushort) (7 - tid);
    		L[tid*6+0] = inv((ushort) K[r9*6+0]);
    		L[tid*6+1] = - K[r9*6+2];
    		L[tid*6+2] = - K[r9*6+1];
    		L[tid*6+3] = inv((ushort) K[r9*6+3]);
    		L[tid*6+4] = K[r8*6+4];
    		L[tid*6+5] = K[r8*6+5];
	}

	if(tid == 0){
		L[8*6+0] = inv((ushort) K[0*6+0]);
		L[8*6+1] = - K[0*6+1];
		L[8*6+2] = - K[0*6+2];
		L[8*6+3] = inv((ushort) K[0*6+3]);
		L[8*6+4] = L[8*6+6] = 0;
	}
}

int main(int argc, char *argv[])
{	
	/*int devcount;
	cudaGetDeviceCount(&devcount);
	printf("%d ",devcount);
	for(int i=0;i<devcount;i++){
		cudaDeviceProp prop;
		cudaGetDeviceProperties(&prop , i);
		printf("%d ",prop.warpSize);
	}*/
	int tc=512;
	int count;
	long *K, *L;K=NULL;L=NULL;
	long *dev_K , *dev_L; dev_K=NULL; dev_L = NULL;
	ushort key[8] = {1, 2, 3, 4, 5, 6, 7, 8};
	ushort *X, *Y;
	ushort *dev_X, *dev_Y;
	ushort *dev_key = NULL;
  
	FILE *in_file  = fopen("/home/pratik/input.jpg", "r"); 
	FILE *out_file = fopen("/home/pratik/output.jpg", "w"); 
	FILE *mid_w = fopen("/home/pratik/encrypt.jpg", "w");
	if (in_file == NULL || out_file == NULL) 
	{
		printf("Error! Could not open file\n"); 
		exit(-1); 
	}
	
	K = (long *)malloc(54 * sizeof(long ));
	L = (long *)malloc(54 * sizeof(long ));

	hipMalloc((void **) &dev_key , 16);
	hipMemcpy( dev_key, key, 16, hipMemcpyHostToDevice);

 	size_t pitch;
	hipMallocPitch(&dev_K, &pitch, sizeof(long)*9, 6);
	hipMallocPitch(&dev_L, &pitch, sizeof(long)*9, 6);
	
	IDEA_encryption_key_schedule<<<1,128>>>(dev_key, dev_K);

	hipMemcpy( K , dev_K, 9*6* sizeof(long *),hipMemcpyDeviceToHost);

	X = (ushort *)malloc(tc * 4 * sizeof(ushort));
	Y = (ushort *)malloc(tc * 4 * sizeof(ushort));

	count = fread( X,2,tc*4,in_file);

	hipMalloc((void **) &dev_Y , tc*4*2);
	hipMalloc((void **) &dev_X , tc*4*2);	

	while(count==tc * 4){
	   	hipMemcpy( dev_X, X,tc * 8, hipMemcpyHostToDevice);
   
		IDEA_encryption<<<1,tc>>>(dev_X, dev_Y, dev_K);

		hipMemcpy( Y, dev_Y,tc * 8, hipMemcpyDeviceToHost);

		fwrite( Y,2,tc*4,mid_w);
		count = fread( X,2,tc*4,in_file);
	}
	if(count < tc*4 && count > 0){
		fwrite( X,2,count,mid_w);
	}
	
	fclose(mid_w);
	FILE *mid_file = fopen("/home/pratik/encrypt.jpg", "r");

	IDEA_decryption_key_schedule<<<1,8>>>(dev_K, dev_L);

	count = fread( Y,2,tc*4,mid_file);
	while(count==tc * 4){
		hipMemcpy( dev_Y, Y,tc * 8, hipMemcpyHostToDevice);
	
		IDEA_encryption<<<1,tc>>>(dev_Y, dev_X, dev_L);
	
		hipMemcpy( X, dev_X,tc * 8, hipMemcpyDeviceToHost);
 
		fwrite( X,2,tc*4,out_file);
		count = fread( Y,2,tc*4,mid_file);
	}
	if(count < tc*4 && count > 0){
		fwrite( Y,2,count,out_file);
	} 
	free(K);
	free(L);
	return 0;
}

	.text
	.file	"idea.hip"
	.globl	_Z30__device_stub__IDEA_encryptionPtS_Pl # -- Begin function _Z30__device_stub__IDEA_encryptionPtS_Pl
	.type	_Z30__device_stub__IDEA_encryptionPtS_Pl,@function
_Z30__device_stub__IDEA_encryptionPtS_Pl: # @_Z30__device_stub__IDEA_encryptionPtS_Pl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15IDEA_encryptionPtS_Pl, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__IDEA_encryptionPtS_Pl, .Lfunc_end0-_Z30__device_stub__IDEA_encryptionPtS_Pl
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__IDEA_encryption_key_schedulePtPl # -- Begin function _Z43__device_stub__IDEA_encryption_key_schedulePtPl
	.type	_Z43__device_stub__IDEA_encryption_key_schedulePtPl,@function
_Z43__device_stub__IDEA_encryption_key_schedulePtPl: # @_Z43__device_stub__IDEA_encryption_key_schedulePtPl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28IDEA_encryption_key_schedulePtPl, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z43__device_stub__IDEA_encryption_key_schedulePtPl, .Lfunc_end1-_Z43__device_stub__IDEA_encryption_key_schedulePtPl
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__IDEA_decryption_key_schedulePlS_ # -- Begin function _Z43__device_stub__IDEA_decryption_key_schedulePlS_
	.type	_Z43__device_stub__IDEA_decryption_key_schedulePlS_,@function
_Z43__device_stub__IDEA_decryption_key_schedulePlS_: # @_Z43__device_stub__IDEA_decryption_key_schedulePlS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28IDEA_decryption_key_schedulePlS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z43__device_stub__IDEA_decryption_key_schedulePlS_, .Lfunc_end2-_Z43__device_stub__IDEA_decryption_key_schedulePlS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI3_0:
	.short	1                               # 0x1
	.short	2                               # 0x2
	.short	3                               # 0x3
	.short	4                               # 0x4
	.short	5                               # 0x5
	.short	6                               # 0x6
	.short	7                               # 0x7
	.short	8                               # 0x8
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%eax, %eax
	movq	%rax, 8(%rsp)
	movq	%rax, 32(%rsp)
	movaps	.LCPI3_0(%rip), %xmm0           # xmm0 = [1,2,3,4,5,6,7,8]
	movaps	%xmm0, 64(%rsp)
	movq	%rax, 40(%rsp)
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %r14
	movl	$.L.str.2, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	$.L.str.4, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	testq	%r14, %r14
	je	.LBB3_23
# %bb.1:
	testq	%rbx, %rbx
	je	.LBB3_23
# %bb.2:
	movq	%rax, %rbp
	movq	%rbx, 56(%rsp)                  # 8-byte Spill
	movabsq	$4294967297, %r15               # imm = 0x100000001
	movl	$432, %edi                      # imm = 0x1B0
	callq	malloc
	movq	%rax, %r12
	leaq	40(%rsp), %rbx
	movl	$16, %esi
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	64(%rsp), %rsi
	movl	$16, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rdi
	leaq	80(%rsp), %rbx
	movl	$72, %edx
	movl	$6, %ecx
	movq	%rbx, %rsi
	callq	hipMallocPitch
	leaq	32(%rsp), %rdi
	movl	$72, %edx
	movl	$6, %ecx
	movq	%rbx, %rsi
	callq	hipMallocPitch
	leaq	127(%r15), %rdx
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	40(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z43__device_stub__IDEA_encryption_key_schedulePtPl
.LBB3_4:
	movq	8(%rsp), %rsi
	movl	$432, %edx                      # imm = 0x1B0
	movq	%r12, 48(%rsp)                  # 8-byte Spill
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %r13
	movl	$4096, %edi                     # imm = 0x1000
	callq	malloc
	movq	%rax, %r12
	movl	$2, %esi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r13, %rdi
	movq	%r14, %rcx
	callq	fread
	movq	%rax, %rbx
	leaq	16(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	movl	%ebx, %eax
	cmpl	$2048, %ebx                     # imm = 0x800
	jne	.LBB3_10
# %bb.5:                                # %.lr.ph.preheader
	leaq	511(%r15), %rbx
.LBB3_6:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	24(%rsp), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:                                #   in Loop: Header=BB3_6 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z30__device_stub__IDEA_encryptionPtS_Pl
.LBB3_8:                                #   in Loop: Header=BB3_6 Depth=1
	movq	16(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$2, %esi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r12, %rdi
	movq	%rbp, %rcx
	callq	fwrite
	movl	$2, %esi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r13, %rdi
	movq	%r14, %rcx
	callq	fread
	cmpl	$2048, %eax                     # imm = 0x800
	je	.LBB3_6
# %bb.9:
	movq	%rax, %rbx
.LBB3_10:                               # %._crit_edge
	decl	%eax
	cmpl	$2046, %eax                     # imm = 0x7FE
	ja	.LBB3_12
# %bb.11:
	movl	%ebx, %edx
	movl	$2, %esi
	movq	%r13, %rdi
	movq	%rbp, %rcx
	callq	fwrite
.LBB3_12:
	movq	%rbp, %rdi
	callq	fclose
	movl	$.L.str.4, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %r14
	leaq	7(%r15), %rdx
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_14
# %bb.13:
	movq	8(%rsp), %rdi
	movq	32(%rsp), %rsi
	callq	_Z43__device_stub__IDEA_decryption_key_schedulePlS_
.LBB3_14:
	movl	$2, %esi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r12, %rdi
	movq	%r14, %rcx
	callq	fread
	movl	%eax, %ecx
	cmpl	$2048, %eax                     # imm = 0x800
	movq	56(%rsp), %rbp                  # 8-byte Reload
	jne	.LBB3_20
# %bb.15:                               # %.lr.ph102.preheader
	leaq	511(%r15), %rbx
.LBB3_16:                               # %.lr.ph102
                                        # =>This Inner Loop Header: Depth=1
	movq	16(%rsp), %rdi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_18
# %bb.17:                               #   in Loop: Header=BB3_16 Depth=1
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	32(%rsp), %rdx
	callq	_Z30__device_stub__IDEA_encryptionPtS_Pl
.LBB3_18:                               #   in Loop: Header=BB3_16 Depth=1
	movq	24(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$2, %esi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r13, %rdi
	movq	%rbp, %rcx
	callq	fwrite
	movl	$2, %esi
	movl	$2048, %edx                     # imm = 0x800
	movq	%r12, %rdi
	movq	%r14, %rcx
	callq	fread
	movq	%rax, %rcx
	cmpl	$2048, %ecx                     # imm = 0x800
	je	.LBB3_16
# %bb.19:
	movq	%rcx, %rax
.LBB3_20:                               # %._crit_edge103
	decl	%ecx
	cmpl	$2046, %ecx                     # imm = 0x7FE
	ja	.LBB3_22
# %bb.21:
	movl	%eax, %edx
	movl	$2, %esi
	movq	%r12, %rdi
	movq	%rbp, %rcx
	callq	fwrite
.LBB3_22:
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	free
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_23:
	.cfi_def_cfa_offset 144
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$-1, %edi
	callq	exit
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15IDEA_encryptionPtS_Pl, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28IDEA_encryption_key_schedulePtPl, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28IDEA_decryption_key_schedulePlS_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15IDEA_encryptionPtS_Pl,@object # @_Z15IDEA_encryptionPtS_Pl
	.section	.rodata,"a",@progbits
	.globl	_Z15IDEA_encryptionPtS_Pl
	.p2align	3, 0x0
_Z15IDEA_encryptionPtS_Pl:
	.quad	_Z30__device_stub__IDEA_encryptionPtS_Pl
	.size	_Z15IDEA_encryptionPtS_Pl, 8

	.type	_Z28IDEA_encryption_key_schedulePtPl,@object # @_Z28IDEA_encryption_key_schedulePtPl
	.globl	_Z28IDEA_encryption_key_schedulePtPl
	.p2align	3, 0x0
_Z28IDEA_encryption_key_schedulePtPl:
	.quad	_Z43__device_stub__IDEA_encryption_key_schedulePtPl
	.size	_Z28IDEA_encryption_key_schedulePtPl, 8

	.type	_Z28IDEA_decryption_key_schedulePlS_,@object # @_Z28IDEA_decryption_key_schedulePlS_
	.globl	_Z28IDEA_decryption_key_schedulePlS_
	.p2align	3, 0x0
_Z28IDEA_decryption_key_schedulePlS_:
	.quad	_Z43__device_stub__IDEA_decryption_key_schedulePlS_
	.size	_Z28IDEA_decryption_key_schedulePlS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/pratik/input.jpg"
	.size	.L.str, 23

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"/home/pratik/output.jpg"
	.size	.L.str.2, 24

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"w"
	.size	.L.str.3, 2

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"/home/pratik/encrypt.jpg"
	.size	.L.str.4, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15IDEA_encryptionPtS_Pl"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z28IDEA_encryption_key_schedulePtPl"
	.size	.L__unnamed_2, 37

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z28IDEA_decryption_key_schedulePlS_"
	.size	.L__unnamed_3, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Error! Could not open file"
	.size	.Lstr, 27

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__IDEA_encryptionPtS_Pl
	.addrsig_sym _Z43__device_stub__IDEA_encryption_key_schedulePtPl
	.addrsig_sym _Z43__device_stub__IDEA_decryption_key_schedulePlS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15IDEA_encryptionPtS_Pl
	.addrsig_sym _Z28IDEA_encryption_key_schedulePtPl
	.addrsig_sym _Z28IDEA_decryption_key_schedulePlS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15IDEA_encryptionPtS_Pl ; -- Begin function _Z15IDEA_encryptionPtS_Pl
	.globl	_Z15IDEA_encryptionPtS_Pl
	.p2align	8
	.type	_Z15IDEA_encryptionPtS_Pl,@function
_Z15IDEA_encryptionPtS_Pl:              ; @_Z15IDEA_encryptionPtS_Pl
; %bb.0:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x10
	v_lshlrev_b32_e32 v1, 3, v0
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v6, 2, v0
	s_mov_b32 s6, 0
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[4:5], v1, s[8:9]
	v_add_co_u32 v0, s0, s8, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, null, s9, 0, s0
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v2, 16, v4
	v_lshrrev_b32_e32 v7, 16, v5
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_mul_i32 s1, s6, 6
	v_dual_mov_b32 v8, v3 :: v_dual_and_b32 v9, 0xffff, v4
	v_cmp_ne_u16_e64 s0, 0, v4
	s_and_b32 s1, s1, 0xfffe
	v_dual_mov_b32 v11, v3 :: v_dual_and_b32 v12, 0xffff, v7
	s_lshl_b32 s1, s1, 3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v15, 0x10000, v9, s0
	s_clause 0x1
	s_load_b256 s[12:19], s[4:5], s1 offset:0x0
	s_load_b128 s[0:3], s[4:5], s1 offset:0x20
	v_cmp_ne_u16_e32 vcc_lo, 0, v7
	v_cndmask_b32_e32 v16, 0x10000, v12, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u64 s[12:13], 0
	v_add_nc_u16 v18, v5, s16
	s_cselect_b32 s8, s12, 0x10000
	s_cselect_b32 s7, s13, 0
	v_mad_u64_u32 v[4:5], null, s8, v15, 0
	s_cmp_lg_u64 s[18:19], 0
	v_add_nc_u16 v17, v2, s14
	s_cselect_b32 s9, s18, 0x10000
	s_cselect_b32 s8, s19, 0
	v_mad_u64_u32 v[12:13], null, s9, v16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v2, v5
	v_dual_mov_b32 v10, v3 :: v_dual_and_b32 v7, 0xffff, v4
	s_cmp_lg_u64 s[0:1], 0
	s_cselect_b32 s0, s0, 0x10000
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v5, v13
	v_and_b32_e32 v9, 0xffff, v12
	v_mad_u64_u32 v[13:14], null, s7, v15, v[2:3]
	s_cselect_b32 s1, s1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, s8, v16, v[5:6]
	s_cmp_lg_u64 s[2:3], 0
	v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v5, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v13, v2, v4, 16
	v_alignbit_b32 v14, v5, v12, 16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v2, 0xffff, v13
	v_sub_nc_u32_e32 v4, v4, v13
	v_sub_nc_u32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_add_nc_u16 v13, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v18, v13
	v_and_b32_e32 v4, 0xffff, v2
	v_cmp_ne_u16_e32 vcc_lo, 0, v2
	v_and_b32_e32 v2, 0xffff, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, 0x10000, v4, vcc_lo
	v_cmp_lt_u64_e32 vcc_lo, v[9:10], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v15, s0, 0
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	s_cselect_b32 s0, s2, 0x10000
	v_add_nc_u16 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v2, v5
	v_and_b32_e32 v10, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v9, v17
	v_mad_u64_u32 v[7:8], null, v15, s1, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v7
	v_alignbit_b32 v7, v2, v4, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, 0xffff, v7
	v_sub_nc_u32_e32 v4, v4, v7
	v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v4, vcc_lo
	v_add_nc_u16 v2, v5, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, 0xffff, v2
	v_cmp_ne_u16_e32 vcc_lo, 0, v2
	v_cndmask_b32_e32 v11, 0x10000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v11, s0, 0
	s_cselect_b32 s0, s3, 0
	v_mov_b32_e32 v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[7:8], null, v11, s0, v[2:3]
	v_mov_b32_e32 v8, v3
	v_cmp_lt_u16_e64 s0, s6, 7
	v_dual_mov_b32 v2, v7 :: v_dual_and_b32 v7, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v5, v2, v4, 16
	v_and_b32_e32 v2, 0xffff, v5
	v_sub_nc_u32_e32 v4, v4, v5
	v_add_nc_u16 v5, s6, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_readfirstlane_b32 s6, v5
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u16 v2, v2, v4
	v_add_nc_u16 v5, v2, v10
	v_xor_b32_e32 v4, v2, v13
	v_xor_b32_e32 v2, v2, v18
	s_delay_alu instid0(VALU_DEP_3)
	v_xor_b32_e32 v7, v5, v9
	v_xor_b32_e32 v5, v5, v17
	s_cbranch_vccnz .LBB0_1
; %bb.2:
	s_load_b256 s[0:7], s[4:5], 0x180
	v_and_b32_e32 v3, 0xffff, v4
	v_cmp_ne_u16_e32 vcc_lo, 0, v4
	v_perm_b32 v2, v2, v4, 0x5040100
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_cndmask_b32 v11, 0x10000, v3 :: v_dual_lshlrev_b32 v6, 1, v6
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u64 s[0:1], 0
	s_cselect_b32 s0, s0, 0x10000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[8:9], null, s0, v11, 0
	s_cselect_b32 s0, s1, 0
	s_cmp_lg_u64 s[6:7], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v9
	v_mad_u64_u32 v[9:10], null, s0, v11, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v11, 0xffff, v8
	s_cselect_b32 s0, s6, 0x10000
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v3, v3, v8, 16
	v_and_b32_e32 v9, 0xffff, v3
	v_sub_nc_u32_e32 v8, v8, v3
	v_perm_b32 v3, v7, v5, 0x5040100
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	v_add_nc_u16 v4, v9, v8
	global_store_b64 v[0:1], v[2:3], off
	global_store_b16 v6, v4, s[10:11]
	global_load_u16 v2, v[0:1], off offset:6
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v2
	v_cmp_ne_u16_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, 0x10000, v3, vcc_lo
	v_mad_u64_u32 v[2:3], null, s0, v7, 0
	s_cselect_b32 s0, s7, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s0, v7, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v4 :: v_dual_mov_b32 v4, v10
	v_alignbit_b32 v5, v3, v2, 16
	v_and_b32_e32 v3, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v9, 0xffff, v5
	v_sub_nc_u32_e32 v2, v2, v5
	v_cmp_lt_u64_e32 vcc_lo, v[3:4], v[9:10]
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u16 v2, v3, v2
	global_store_b16 v6, v2, s[10:11] offset:6
	global_load_u16 v2, v[0:1], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v2, s2
	global_store_b16 v6, v2, s[10:11] offset:2
	global_load_u16 v0, v[0:1], off offset:2
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v0, v0, s4
	global_store_b16 v6, v0, s[10:11] offset:4
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15IDEA_encryptionPtS_Pl
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15IDEA_encryptionPtS_Pl, .Lfunc_end0-_Z15IDEA_encryptionPtS_Pl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1148
; NumSgprs: 22
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z28IDEA_encryption_key_schedulePtPl ; -- Begin function _Z28IDEA_encryption_key_schedulePtPl
	.globl	_Z28IDEA_encryption_key_schedulePtPl
	.p2align	8
	.type	_Z28IDEA_encryption_key_schedulePtPl,@function
_Z28IDEA_encryption_key_schedulePtPl:   ; @_Z28IDEA_encryption_key_schedulePtPl
; %bb.0:
	s_load_b128 s[16:19], s[0:1], 0x0
	v_cmp_gt_u32_e64 s0, 6, v0
	v_lshlrev_b32_e32 v3, 3, v0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_mov_b32 s2, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0
	s_waitcnt lgkmcnt(0)
	global_load_u16 v1, v1, s[16:17]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	global_store_b64 v3, v[1:2], s[18:19]
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 32, v0
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_mov_b32_e32 v5, 0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v1, v5, s[16:17] offset:12
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xffff, v1
	v_lshrrev_b32_e32 v2, 16, v1
	v_mov_b32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_or_b32 v6, 0, 16, v2
	global_store_b128 v5, v[4:7], s[18:19] offset:48
.LBB1_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_gt_u32_e64 s1, 16, v0
	v_xor_b32_e32 v4, 15, v0
	v_mov_b32_e32 v6, 0
	v_lshl_add_u32 v5, v0, 1, 16
	s_mov_b32 s21, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s20, s21
.LBB1_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_6 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[20:21], 3
	v_mov_b32_e32 v14, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s18, s2
	s_addc_u32 s3, s19, s3
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr7
	global_load_b64 v[1:2], v6, s[2:3]
                                        ; implicit-def: $vgpr2
.LBB1_6:                                ;   Parent Loop BB1_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_cmp_eq_u16_e64 s8, 14, v14
	v_cmp_eq_u16_e64 s9, 12, v14
	v_cmp_eq_u16_e64 s10, 10, v14
	v_cmp_eq_u16_e64 s11, 8, v14
	v_cmp_eq_u16_e64 s12, 6, v14
	v_cmp_eq_u16_e64 s13, 4, v14
	v_cmp_eq_u16_e64 s14, 2, v14
	v_cmp_eq_u16_e64 s15, 0, v14
	v_add_nc_u16 v24, v14, 1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, 0xffff, v1
	v_and_b32_e32 v1, 1, v1
	v_lshrrev_b32_e32 v16, 16, v2
	v_lshrrev_b32_e32 v17, 16, v7
	v_cmp_eq_u16_e32 vcc_lo, 13, v14
	v_lshrrev_b32_e32 v18, 16, v8
	v_cmp_eq_u16_e64 s2, 11, v14
	v_lshrrev_b32_e32 v19, 16, v9
	v_cmp_eq_u16_e64 s3, 9, v14
	v_lshrrev_b32_e32 v20, 16, v10
	v_cmp_eq_u16_e64 s4, 7, v14
	v_lshrrev_b32_e32 v21, 16, v11
	v_cmp_eq_u16_e64 s5, 5, v14
	v_lshrrev_b32_e32 v22, 16, v12
	v_cmp_eq_u16_e64 s6, 3, v14
	v_lshrrev_b32_e32 v23, 16, v13
	v_cmp_eq_u16_e64 s7, 1, v14
	v_cmp_eq_u16_e64 s17, 15, v14
	v_cndmask_b32_e64 v2, v2, v1, s8
	v_cndmask_b32_e64 v7, v7, v1, s9
	v_cndmask_b32_e64 v8, v8, v1, s10
	v_cndmask_b32_e64 v9, v9, v1, s11
	v_cndmask_b32_e64 v10, v10, v1, s12
	v_cndmask_b32_e64 v11, v11, v1, s13
	v_cndmask_b32_e64 v13, v13, v1, s15
	v_cndmask_b32_e64 v12, v12, v1, s14
	v_cndmask_b32_e64 v16, v16, v1, s17
	v_cndmask_b32_e32 v17, v17, v1, vcc_lo
	v_cndmask_b32_e64 v18, v18, v1, s2
	v_cndmask_b32_e64 v19, v19, v1, s3
	v_and_b32_e32 v12, 0xffff, v12
	v_cndmask_b32_e64 v20, v20, v1, s4
	v_cndmask_b32_e64 v21, v21, v1, s5
	v_cndmask_b32_e64 v22, v22, v1, s6
	v_cndmask_b32_e64 v23, v23, v1, s7
	v_and_b32_e32 v13, 0xffff, v13
	v_and_b32_e32 v11, 0xffff, v11
	v_and_b32_e32 v10, 0xffff, v10
	v_and_b32_e32 v9, 0xffff, v9
	v_and_b32_e32 v8, 0xffff, v8
	v_and_b32_e32 v7, 0xffff, v7
	v_and_b32_e32 v2, 0xffff, v2
	v_cmp_gt_u16_e64 s16, 15, v14
	v_mov_b32_e32 v14, v24
	v_lshrrev_b32_e32 v1, 1, v15
	v_lshl_or_b32 v13, v23, 16, v13
	v_lshl_or_b32 v12, v22, 16, v12
	v_lshl_or_b32 v11, v21, 16, v11
	v_lshl_or_b32 v10, v20, 16, v10
	v_lshl_or_b32 v9, v19, 16, v9
	v_lshl_or_b32 v8, v18, 16, v8
	v_lshl_or_b32 v7, v17, 16, v7
	v_lshl_or_b32 v2, v16, 16, v2
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_6
; %bb.7:                                ;   in Loop: Header=BB1_5 Depth=1
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_9
; %bb.8:                                ;   in Loop: Header=BB1_5 Depth=1
	v_lshrrev_b32_e32 v1, 16, v13
	v_cmp_eq_u32_e32 vcc_lo, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v1, v13, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v4
	v_lshrrev_b32_e32 v13, 16, v12
	v_cndmask_b32_e32 v1, v1, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v4
	v_lshrrev_b32_e32 v12, 16, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v13, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v4
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v4
	v_lshrrev_b32_e32 v11, 16, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 6, v4
	v_cndmask_b32_e32 v1, v1, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 7, v4
	v_lshrrev_b32_e32 v10, 16, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 8, v4
	v_cndmask_b32_e32 v1, v1, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 9, v4
	v_lshrrev_b32_e32 v9, 16, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 10, v4
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 11, v4
	v_lshrrev_b32_e32 v8, 16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 12, v4
	v_cndmask_b32_e32 v1, v1, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 13, v4
	v_lshl_add_u32 v7, s20, 5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 14, v4
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_lshrrev_b32_e32 v2, 16, v2
	v_cmp_eq_u32_e32 vcc_lo, 15, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	scratch_store_b16 v7, v1, off
.LBB1_9:                                ; %_Z14ushort_to_bitstPt.exit.i
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s20, s20, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s20, 6
	s_cbranch_scc1 .LBB1_5
; %bb.10:
	v_mov_b32_e32 v13, 0
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr6
	global_load_b64 v[1:2], v13, s[18:19] offset:48
                                        ; implicit-def: $vgpr2
.LBB1_11:                               ; =>This Inner Loop Header: Depth=1
	v_cmp_eq_u16_e64 s8, 14, v13
	v_cmp_eq_u16_e64 s9, 12, v13
	v_cmp_eq_u16_e64 s10, 10, v13
	v_cmp_eq_u16_e64 s11, 8, v13
	v_cmp_eq_u16_e64 s12, 6, v13
	v_cmp_eq_u16_e64 s13, 4, v13
	v_cmp_eq_u16_e64 s14, 2, v13
	v_cmp_eq_u16_e64 s15, 0, v13
	v_add_nc_u16 v23, v13, 1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v14, 0xffff, v1
	v_and_b32_e32 v1, 1, v1
	v_lshrrev_b32_e32 v15, 16, v2
	v_lshrrev_b32_e32 v16, 16, v6
	v_cmp_eq_u16_e32 vcc_lo, 13, v13
	v_lshrrev_b32_e32 v17, 16, v7
	v_cmp_eq_u16_e64 s2, 11, v13
	v_lshrrev_b32_e32 v18, 16, v8
	v_cmp_eq_u16_e64 s3, 9, v13
	v_lshrrev_b32_e32 v19, 16, v9
	v_cmp_eq_u16_e64 s4, 7, v13
	v_lshrrev_b32_e32 v20, 16, v10
	v_cmp_eq_u16_e64 s5, 5, v13
	v_lshrrev_b32_e32 v21, 16, v11
	v_cmp_eq_u16_e64 s6, 3, v13
	v_lshrrev_b32_e32 v22, 16, v12
	v_cmp_eq_u16_e64 s7, 1, v13
	v_cmp_eq_u16_e64 s17, 15, v13
	v_cndmask_b32_e64 v2, v2, v1, s8
	v_cndmask_b32_e64 v6, v6, v1, s9
	v_cndmask_b32_e64 v7, v7, v1, s10
	v_cndmask_b32_e64 v8, v8, v1, s11
	v_cndmask_b32_e64 v9, v9, v1, s12
	v_cndmask_b32_e64 v10, v10, v1, s13
	v_cndmask_b32_e64 v12, v12, v1, s15
	v_cndmask_b32_e64 v11, v11, v1, s14
	v_cndmask_b32_e64 v15, v15, v1, s17
	v_cndmask_b32_e32 v16, v16, v1, vcc_lo
	v_cndmask_b32_e64 v17, v17, v1, s2
	v_cndmask_b32_e64 v18, v18, v1, s3
	v_and_b32_e32 v11, 0xffff, v11
	v_cndmask_b32_e64 v19, v19, v1, s4
	v_cndmask_b32_e64 v20, v20, v1, s5
	v_cndmask_b32_e64 v21, v21, v1, s6
	v_cndmask_b32_e64 v22, v22, v1, s7
	v_and_b32_e32 v12, 0xffff, v12
	v_and_b32_e32 v10, 0xffff, v10
	v_and_b32_e32 v9, 0xffff, v9
	v_and_b32_e32 v8, 0xffff, v8
	v_and_b32_e32 v7, 0xffff, v7
	v_and_b32_e32 v6, 0xffff, v6
	v_and_b32_e32 v2, 0xffff, v2
	v_cmp_gt_u16_e64 s16, 15, v13
	v_mov_b32_e32 v13, v23
	v_lshrrev_b32_e32 v1, 1, v14
	v_lshl_or_b32 v12, v22, 16, v12
	v_lshl_or_b32 v11, v21, 16, v11
	v_lshl_or_b32 v10, v20, 16, v10
	v_lshl_or_b32 v9, v19, 16, v9
	v_lshl_or_b32 v8, v18, 16, v8
	v_lshl_or_b32 v7, v17, 16, v7
	v_lshl_or_b32 v6, v16, 16, v6
	v_lshl_or_b32 v2, v15, 16, v2
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_11
; %bb.12:
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_14
; %bb.13:
	v_lshrrev_b32_e32 v1, 16, v12
	v_cmp_eq_u32_e32 vcc_lo, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v1, v12, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v4
	v_lshrrev_b32_e32 v12, 16, v11
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v4
	v_lshrrev_b32_e32 v11, 16, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v4
	v_cndmask_b32_e32 v1, v1, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v4
	v_lshrrev_b32_e32 v10, 16, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 6, v4
	v_cndmask_b32_e32 v1, v1, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 7, v4
	v_lshrrev_b32_e32 v9, 16, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 8, v4
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 9, v4
	v_lshrrev_b32_e32 v8, 16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 10, v4
	v_cndmask_b32_e32 v1, v1, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 11, v4
	v_lshrrev_b32_e32 v7, 16, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 12, v4
	v_cndmask_b32_e32 v1, v1, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 14, v4
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_lshrrev_b32_e32 v2, 16, v2
	v_cmp_eq_u32_e32 vcc_lo, 15, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	scratch_store_b16 v5, v1, off offset:192
.LBB1_14:                               ; %_Z14ushort_to_bitstPt.exit86.i
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v13, 0
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr6
	global_load_b64 v[1:2], v13, s[18:19] offset:56
                                        ; implicit-def: $vgpr2
.LBB1_15:                               ; =>This Inner Loop Header: Depth=1
	v_cmp_eq_u16_e64 s8, 14, v13
	v_cmp_eq_u16_e64 s9, 12, v13
	v_cmp_eq_u16_e64 s10, 10, v13
	v_cmp_eq_u16_e64 s11, 8, v13
	v_cmp_eq_u16_e64 s12, 6, v13
	v_cmp_eq_u16_e64 s13, 4, v13
	v_cmp_eq_u16_e64 s14, 2, v13
	v_cmp_eq_u16_e64 s15, 0, v13
	v_add_nc_u16 v23, v13, 1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v14, 0xffff, v1
	v_and_b32_e32 v1, 1, v1
	v_lshrrev_b32_e32 v15, 16, v2
	v_lshrrev_b32_e32 v16, 16, v6
	v_cmp_eq_u16_e32 vcc_lo, 13, v13
	v_lshrrev_b32_e32 v17, 16, v7
	v_cmp_eq_u16_e64 s2, 11, v13
	v_lshrrev_b32_e32 v18, 16, v8
	v_cmp_eq_u16_e64 s3, 9, v13
	v_lshrrev_b32_e32 v19, 16, v9
	v_cmp_eq_u16_e64 s4, 7, v13
	v_lshrrev_b32_e32 v20, 16, v10
	v_cmp_eq_u16_e64 s5, 5, v13
	v_lshrrev_b32_e32 v21, 16, v11
	v_cmp_eq_u16_e64 s6, 3, v13
	v_lshrrev_b32_e32 v22, 16, v12
	v_cmp_eq_u16_e64 s7, 1, v13
	v_cmp_eq_u16_e64 s17, 15, v13
	v_cndmask_b32_e64 v2, v2, v1, s8
	v_cndmask_b32_e64 v6, v6, v1, s9
	v_cndmask_b32_e64 v7, v7, v1, s10
	v_cndmask_b32_e64 v8, v8, v1, s11
	v_cndmask_b32_e64 v9, v9, v1, s12
	v_cndmask_b32_e64 v10, v10, v1, s13
	v_cndmask_b32_e64 v12, v12, v1, s15
	v_cndmask_b32_e64 v11, v11, v1, s14
	v_cndmask_b32_e64 v15, v15, v1, s17
	v_cndmask_b32_e32 v16, v16, v1, vcc_lo
	v_cndmask_b32_e64 v17, v17, v1, s2
	v_cndmask_b32_e64 v18, v18, v1, s3
	v_and_b32_e32 v11, 0xffff, v11
	v_cndmask_b32_e64 v19, v19, v1, s4
	v_cndmask_b32_e64 v20, v20, v1, s5
	v_cndmask_b32_e64 v21, v21, v1, s6
	v_cndmask_b32_e64 v22, v22, v1, s7
	v_and_b32_e32 v12, 0xffff, v12
	v_and_b32_e32 v10, 0xffff, v10
	v_and_b32_e32 v9, 0xffff, v9
	v_and_b32_e32 v8, 0xffff, v8
	v_and_b32_e32 v7, 0xffff, v7
	v_and_b32_e32 v6, 0xffff, v6
	v_and_b32_e32 v2, 0xffff, v2
	v_cmp_gt_u16_e64 s16, 15, v13
	v_mov_b32_e32 v13, v23
	v_lshrrev_b32_e32 v1, 1, v14
	v_lshl_or_b32 v12, v22, 16, v12
	v_lshl_or_b32 v11, v21, 16, v11
	v_lshl_or_b32 v10, v20, 16, v10
	v_lshl_or_b32 v9, v19, 16, v9
	v_lshl_or_b32 v8, v18, 16, v8
	v_lshl_or_b32 v7, v17, 16, v7
	v_lshl_or_b32 v6, v16, 16, v6
	v_lshl_or_b32 v2, v15, 16, v2
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_15
; %bb.16:
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_18
; %bb.17:
	v_lshrrev_b32_e32 v1, 16, v12
	v_cmp_eq_u32_e32 vcc_lo, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v1, v12, v1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v4
	v_lshrrev_b32_e32 v12, 16, v11
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v4
	v_lshrrev_b32_e32 v11, 16, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 4, v4
	v_cndmask_b32_e32 v1, v1, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 5, v4
	v_lshrrev_b32_e32 v10, 16, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 6, v4
	v_cndmask_b32_e32 v1, v1, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 7, v4
	v_lshrrev_b32_e32 v9, 16, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 8, v4
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 9, v4
	v_lshrrev_b32_e32 v8, 16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 10, v4
	v_cndmask_b32_e32 v1, v1, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 11, v4
	v_lshrrev_b32_e32 v7, 16, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 12, v4
	v_cndmask_b32_e32 v1, v1, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 14, v4
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_lshrrev_b32_e32 v2, 16, v2
	v_cmp_eq_u32_e32 vcc_lo, 15, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	scratch_store_b16 v5, v1, off offset:224
.LBB1_18:                               ; %_Z14ushort_to_bitstPt.exit90.i
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v1, -2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e64 s1, 4, v1
	v_lshlrev_b32_e32 v1, 5, v0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_22
; %bb.19:
	scratch_load_u16 v2, v1, off offset:208
	v_mov_b32_e32 v4, 0x110
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v4, v1, 0xffffffc2
.LBB1_20:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, s3, v4
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 1, v2
	s_add_i32 s3, s3, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, 30
	scratch_load_u16 v5, v5, off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v5, v2
	s_cbranch_scc1 .LBB1_20
; %bb.21:                               ; %_Z14bits_to_ushortPt.exit.i
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, s3 :: v_dual_and_b32 v4, 0xffff, v2
	global_store_b64 v3, v[4:5], s[18:19] offset:48
.LBB1_22:                               ; %Flow301
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u32_e32 vcc_lo, 4, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_26
; %bb.23:
	scratch_load_u16 v2, v1, off offset:400
	v_mov_b32_e32 v4, 0x110
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v4, v1, 0x82
.LBB1_24:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, s3, v4
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 1, v2
	s_add_i32 s3, s3, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, 30
	scratch_load_u16 v5, v5, off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v5, v2
	s_cbranch_scc1 .LBB1_24
; %bb.25:                               ; %_Z14bits_to_ushortPt.exit93.i
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, s3 :: v_dual_and_b32 v4, 0xffff, v2
	v_lshl_or_b32 v2, v0, 3, 0x60
	global_store_b64 v2, v[4:5], s[18:19]
.LBB1_26:                               ; %Flow300
	s_or_b32 exec_lo, exec_lo, s2
	scratch_load_u16 v2, off, off offset:16
	s_mov_b32 s2, 2
.LBB1_27:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_i32 s3, s2, 16
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 1, v2
	scratch_load_u16 v4, off, s3
	s_add_i32 s2, s2, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v4, v2
	s_cbranch_scc1 .LBB1_27
; %bb.28:                               ; %_Z14bits_to_ushortPt.exit96.i
	scratch_load_u16 v4, off, off offset:48
	s_mov_b32 s2, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v6, s2 :: v_dual_and_b32 v5, 0xffff, v2
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, 34
	global_store_b64 v2, v[5:6], s[18:19] offset:128
.LBB1_29:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s3, s2, 16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b16 v4, 1, v4
	scratch_load_u16 v2, off, s3
	s_add_i32 s2, s2, 2
	s_cmp_lg_u32 s2, 64
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v4, v2, v4
	s_cbranch_scc1 .LBB1_29
; %bb.30:                               ; %_Z14bits_to_ushortPt.exit99.i
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, s3 :: v_dual_and_b32 v4, 0xffff, v4
	v_mov_b32_e32 v2, 0
	global_store_b64 v2, v[4:5], s[18:19] offset:136
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB1_36
; %bb.31:
	scratch_load_u16 v2, v1, off offset:80
	v_dual_mov_b32 v5, 16 :: v_dual_lshlrev_b32 v4, 4, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v5, v5, v1, 0x42
.LBB1_32:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, s3, v5
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 1, v2
	s_add_i32 s3, s3, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, 30
	scratch_load_u16 v6, v6, off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v6, v2
	s_cbranch_scc1 .LBB1_32
; %bb.33:                               ; %_Z14bits_to_ushortPt.exit102.i
	s_mov_b32 s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v6, s3 :: v_dual_lshlrev_b32 v7, 1, v4
	v_and_b32_e32 v5, 0xffff, v2
	s_mov_b32 s3, 2
	scratch_load_u16 v4, v7, off offset:272
	v_add_nc_u32_e32 v2, 0x110, v7
	global_store_b64 v3, v[5:6], s[18:19] offset:144
.LBB1_34:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshlrev_b16 v4, 1, v4
	s_add_i32 s3, s3, 2
	s_cmp_lg_u32 s3, 32
	scratch_load_u16 v5, v5, off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v4, v5, v4
	s_cbranch_scc1 .LBB1_34
; %bb.35:                               ; %_Z14bits_to_ushortPt.exit105.i
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, s3 :: v_dual_and_b32 v4, 0xffff, v4
	v_lshl_or_b32 v2, v0, 3, 0xc0
	global_store_b64 v2, v[4:5], s[18:19]
.LBB1_36:                               ; %Flow299
	s_or_b32 exec_lo, exec_lo, s2
	scratch_load_u16 v2, off, off offset:464
	s_movk_i32 s2, 0xc2
.LBB1_37:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_i32 s3, s2, 0x110
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 1, v2
	scratch_load_u16 v4, off, s3
	s_add_i32 s2, s2, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lg_i32 s2, 0xe0
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v4, v2
	s_cbranch_scc1 .LBB1_37
; %bb.38:                               ; %_Z14bits_to_ushortPt.exit108.i
	scratch_load_u16 v4, off, off offset:496
	s_mov_b32 s2, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v6, s2 :: v_dual_and_b32 v5, 0xffff, v2
	v_mov_b32_e32 v2, 0
	s_movk_i32 s2, 0xe2
	global_store_b64 v2, v[5:6], s[18:19] offset:240
.LBB1_39:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s3, s2, 0x110
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b16 v4, 1, v4
	scratch_load_u16 v2, off, s3
	s_add_i32 s2, s2, 2
	s_cmpk_lg_i32 s2, 0x100
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v4, v2, v4
	s_cbranch_scc1 .LBB1_39
; %bb.40:                               ; %_Z17cyclic_left_shifttPtS_Pl.exit20
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, s3 :: v_dual_and_b32 v4, 0xffff, v4
	v_mov_b32_e32 v2, 0
	global_store_b64 v2, v[4:5], s[18:19] offset:248
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB1_44
; %bb.41:
	scratch_load_u16 v2, v1, off offset:-48
	v_mov_b32_e32 v4, 16
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v4, v1, 0xffffffc2
.LBB1_42:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, s3, v4
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 1, v2
	s_add_i32 s3, s3, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, 30
	scratch_load_u16 v5, v5, off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v5, v2
	s_cbranch_scc1 .LBB1_42
; %bb.43:                               ; %_Z14bits_to_ushortPt.exit114.i
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, s1 :: v_dual_and_b32 v4, 0xffff, v2
	global_store_b64 v3, v[4:5], s[18:19] offset:240
.LBB1_44:                               ; %Flow298
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB1_48
; %bb.45:
	scratch_load_u16 v2, v1, off offset:144
	v_mov_b32_e32 v4, 16
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v4, v1, 0x82
.LBB1_46:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, s2, v4
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 1, v2
	s_add_i32 s2, s2, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 30
	scratch_load_u16 v5, v5, off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v5, v2
	s_cbranch_scc1 .LBB1_46
; %bb.47:                               ; %_Z14bits_to_ushortPt.exit117.i
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, s2 :: v_dual_and_b32 v4, 0xffff, v2
	v_lshl_or_b32 v2, v0, 3, 0x120
	global_store_b64 v2, v[4:5], s[18:19]
.LBB1_48:                               ; %Flow297
	s_or_b32 exec_lo, exec_lo, s1
	scratch_load_u16 v2, off, off offset:272
	s_mov_b32 s1, 2
.LBB1_49:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_i32 s2, s1, 0x110
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 1, v2
	scratch_load_u16 v4, off, s2
	s_add_i32 s1, s1, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s1, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v4, v2
	s_cbranch_scc1 .LBB1_49
; %bb.50:                               ; %_Z14bits_to_ushortPt.exit120.i
	scratch_load_u16 v4, off, off offset:304
	s_mov_b32 s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v6, s1 :: v_dual_and_b32 v5, 0xffff, v2
	v_mov_b32_e32 v2, 0
	s_mov_b32 s1, 34
	global_store_b64 v2, v[5:6], s[18:19] offset:320
.LBB1_51:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s2, s1, 0x110
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b16 v4, 1, v4
	scratch_load_u16 v2, off, s2
	s_add_i32 s1, s1, 2
	s_cmp_lg_u32 s1, 64
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v4, v2, v4
	s_cbranch_scc1 .LBB1_51
; %bb.52:                               ; %_Z14bits_to_ushortPt.exit123.i
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, s2 :: v_dual_and_b32 v4, 0xffff, v4
	v_mov_b32_e32 v2, 0
	global_store_b64 v2, v[4:5], s[18:19] offset:328
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_56
; %bb.53:
	scratch_load_u16 v2, v1, off offset:336
	v_mov_b32_e32 v4, 0x110
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v4, v1, 0x42
.LBB1_54:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, s2, v4
	s_waitcnt vmcnt(0)
	v_lshlrev_b16 v2, 1, v2
	s_add_i32 s2, s2, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 30
	scratch_load_u16 v5, v5, off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v5, v2
	s_cbranch_scc1 .LBB1_54
; %bb.55:                               ; %_Z14bits_to_ushortPt.exit126.i
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, s0 :: v_dual_and_b32 v4, 0xffff, v2
	global_store_b64 v3, v[4:5], s[18:19] offset:336
.LBB1_56:                               ; %Flow296
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB1_60
; %bb.57:
	scratch_load_u16 v2, v1, off offset:16
	v_add_nc_u32_e32 v1, 16, v1
	s_mov_b32 s0, 2
.LBB1_58:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, s0, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshlrev_b16 v2, 1, v2
	s_add_i32 s0, s0, 2
	s_cmp_lg_u32 s0, 32
	scratch_load_u16 v3, v3, off
	s_waitcnt vmcnt(0)
	v_add_nc_u16 v2, v3, v2
	s_cbranch_scc1 .LBB1_58
; %bb.59:                               ; %_Z14bits_to_ushortPt.exit129.i
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v2, s0 :: v_dual_and_b32 v1, 0xffff, v2
	v_lshl_or_b32 v0, v0, 3, 0x180
	global_store_b64 v0, v[1:2], s[18:19]
.LBB1_60:                               ; %_Z17cyclic_left_shifttPtS_Pl.exit26
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28IDEA_encryption_key_schedulePtPl
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 528
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z28IDEA_encryption_key_schedulePtPl, .Lfunc_end1-_Z28IDEA_encryption_key_schedulePtPl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3920
; NumSgprs: 24
; NumVgprs: 25
; ScratchSize: 528
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z28IDEA_decryption_key_schedulePlS_ ; -- Begin function _Z28IDEA_decryption_key_schedulePlS_
	.globl	_Z28IDEA_decryption_key_schedulePlS_
	.p2align	8
	.type	_Z28IDEA_decryption_key_schedulePlS_,@function
_Z28IDEA_decryption_key_schedulePlS_:   ; @_Z28IDEA_decryption_key_schedulePlS_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_cmp_eq_u32_e64 s0, 0, v0
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_20
; %bb.1:
	s_waitcnt lgkmcnt(0)
	s_load_b32 s2, s[4:5], 0x180
	s_mov_b64 s[10:11], 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[8:9], 0
	s_cbranch_scc1 .LBB2_6
; %bb.2:                                ; %.lr.ph.i.i.preheader
	s_mov_b64 s[12:13], 0x10001
	s_mov_b64 s[14:15], 1
.LBB2_3:                                ; %.lr.ph.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v1, s8
	v_cvt_f32_u32_e32 v2, s9
	s_mov_b64 s[2:3], s[14:15]
	s_sub_u32 s14, 0, s8
	s_subb_u32 s15, 0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, 0x4f800000, v2
	v_rcp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, 0xcf800000, v2
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s16, v2
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s18, s14, s16
	s_mul_hi_u32 s20, s14, s17
	s_mul_i32 s19, s15, s17
	s_add_i32 s18, s20, s18
	s_mul_i32 s21, s14, s17
	s_add_i32 s18, s18, s19
	s_mul_hi_u32 s20, s17, s21
	s_mul_hi_u32 s19, s17, s18
	s_mul_i32 s17, s17, s18
	s_mul_hi_u32 s22, s16, s21
	s_mul_i32 s21, s16, s21
	s_add_u32 s17, s20, s17
	s_addc_u32 s19, 0, s19
	s_mul_hi_u32 s23, s16, s18
	s_add_u32 s17, s17, s21
	s_mul_i32 s18, s16, s18
	s_addc_u32 s17, s19, s22
	s_addc_u32 s19, s23, 0
	s_add_u32 s17, s17, s18
	s_addc_u32 s18, 0, s19
	v_add_co_u32 v1, s17, v1, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s17, 0
	s_addc_u32 s16, s16, s18
	v_readfirstlane_b32 s17, v1
	s_mul_i32 s18, s14, s16
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s19, s14, s17
	s_mul_i32 s15, s15, s17
	s_add_i32 s18, s19, s18
	s_mul_i32 s14, s14, s17
	s_add_i32 s18, s18, s15
	s_mul_hi_u32 s19, s16, s14
	s_mul_i32 s20, s16, s14
	s_mul_hi_u32 s14, s17, s14
	s_mul_hi_u32 s21, s17, s18
	s_mul_i32 s17, s17, s18
	s_mul_hi_u32 s15, s16, s18
	s_add_u32 s14, s14, s17
	s_addc_u32 s17, 0, s21
	s_add_u32 s14, s14, s20
	s_mul_i32 s18, s16, s18
	s_addc_u32 s14, s17, s19
	s_addc_u32 s15, s15, 0
	s_add_u32 s14, s14, s18
	s_addc_u32 s15, 0, s15
	v_add_co_u32 v1, s14, v1, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s14, 0
	s_addc_u32 s14, s16, s15
	v_readfirstlane_b32 s15, v1
	s_mul_i32 s17, s12, s14
	s_mul_hi_u32 s16, s12, s14
	s_mul_hi_u32 s18, s13, s14
	s_mul_i32 s14, s13, s14
	s_mul_hi_u32 s19, s12, s15
	s_mul_hi_u32 s20, s13, s15
	s_mul_i32 s15, s13, s15
	s_add_u32 s17, s19, s17
	s_addc_u32 s16, 0, s16
	s_add_u32 s15, s17, s15
	s_addc_u32 s15, s16, s20
	s_addc_u32 s16, s18, 0
	s_add_u32 s14, s15, s14
	s_addc_u32 s15, 0, s16
	s_mul_i32 s18, s8, s14
	s_mul_hi_u32 s16, s8, s14
	s_mul_i32 s19, s8, s15
	v_sub_co_u32 v1, s18, s12, s18
	s_mul_i32 s17, s9, s14
	s_add_i32 s16, s16, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s16, s16, s17
	v_sub_co_u32 v2, s19, v1, s8
	s_sub_i32 s17, s13, s16
	s_cmp_lg_u32 s18, 0
	v_readfirstlane_b32 s20, v1
	s_subb_u32 s17, s17, s9
	s_cmp_lg_u32 s19, 0
	v_readfirstlane_b32 s19, v2
	s_subb_u32 s17, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_ge_u32 s17, s9
	s_cselect_b32 s21, -1, 0
	s_cmp_ge_u32 s19, s8
	s_cselect_b32 s19, -1, 0
	s_cmp_eq_u32 s17, s9
	s_cselect_b32 s17, s19, s21
	s_add_u32 s19, s14, 1
	s_addc_u32 s21, s15, 0
	s_add_u32 s22, s14, 2
	s_addc_u32 s23, s15, 0
	s_cmp_lg_u32 s17, 0
	s_cselect_b32 s17, s22, s19
	s_cselect_b32 s19, s23, s21
	s_cmp_lg_u32 s18, 0
	s_subb_u32 s16, s13, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s16, s9
	s_cselect_b32 s18, -1, 0
	s_cmp_ge_u32 s20, s8
	s_cselect_b32 s20, -1, 0
	s_cmp_eq_u32 s16, s9
	s_cselect_b32 s16, s20, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s16, 0
	s_cselect_b32 s14, s17, s14
	s_cselect_b32 s15, s19, s15
	s_mul_i32 s16, s14, s9
	s_mul_hi_u32 s17, s14, s8
	s_mul_i32 s18, s15, s8
	s_mul_i32 s22, s15, s2
	s_add_i32 s15, s17, s16
	s_mul_i32 s19, s14, s8
	s_add_i32 s15, s15, s18
	s_mul_i32 s20, s14, s3
	s_mul_hi_u32 s21, s14, s2
	s_mul_i32 s16, s14, s2
	s_sub_u32 s14, s12, s19
	s_subb_u32 s15, s13, s15
	s_add_i32 s17, s21, s20
	v_cmp_gt_i64_e64 s18, s[14:15], 0
	s_add_i32 s17, s17, s22
	s_mov_b64 s[12:13], s[8:9]
	s_mov_b64 s[8:9], s[14:15]
	s_sub_u32 s14, s10, s16
	s_subb_u32 s15, s11, s17
	s_and_b32 vcc_lo, exec_lo, s18
	s_mov_b64 s[10:11], s[2:3]
	s_cbranch_vccnz .LBB2_3
; %bb.4:                                ; %_Z18extended_euclideanllPlS_S_.exit.i
	v_cmp_lt_i64_e64 s3, s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_7
; %bb.5:
	s_add_i32 s3, s2, 1
	s_mov_b32 s9, 0
	s_and_b32 s8, s3, 0xffff
	s_branch .LBB2_8
.LBB2_6:
	s_mov_b64 s[8:9], 0x10000
	s_branch .LBB2_10
.LBB2_7:
	s_mov_b32 s9, -1
.LBB2_8:                                ; %Flow115
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB2_10
; %bb.9:
	s_and_b32 s8, s2, 0xffff
	s_mov_b32 s9, 0
.LBB2_10:                               ; %_Z3invt.exit
	v_mov_b32_e32 v1, s8
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s9
	s_mov_b32 s9, 0
	s_mov_b64 s[10:11], 0
	global_store_b64 v3, v[1:2], s[6:7]
	global_load_b64 v[1:2], v3, s[4:5] offset:392
	s_waitcnt vmcnt(0)
	v_sub_co_u32 v1, vcc_lo, 0, v1
	v_sub_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	global_store_b64 v3, v[1:2], s[6:7] offset:8
	global_load_b64 v[1:2], v3, s[4:5] offset:400
	s_waitcnt vmcnt(0)
	v_sub_co_u32 v1, vcc_lo, 0, v1
	v_sub_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	global_store_b64 v3, v[1:2], s[6:7] offset:16
	global_load_b32 v1, v3, s[4:5] offset:408
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s8, s2, 0xffff
	s_cmp_eq_u64 s[8:9], 0
	s_cbranch_scc1 .LBB2_15
; %bb.11:                               ; %.lr.ph.i.i54.preheader
	s_mov_b64 s[12:13], 0x10001
	s_mov_b64 s[14:15], 1
.LBB2_12:                               ; %.lr.ph.i.i54
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v1, s8
	v_cvt_f32_u32_e32 v2, s9
	s_mov_b64 s[2:3], s[14:15]
	s_sub_u32 s14, 0, s8
	s_subb_u32 s15, 0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, 0x4f800000, v2
	v_rcp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, 0xcf800000, v2
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s16, v2
	v_readfirstlane_b32 s17, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s18, s14, s16
	s_mul_hi_u32 s20, s14, s17
	s_mul_i32 s19, s15, s17
	s_add_i32 s18, s20, s18
	s_mul_i32 s21, s14, s17
	s_add_i32 s18, s18, s19
	s_mul_hi_u32 s20, s17, s21
	s_mul_hi_u32 s19, s17, s18
	s_mul_i32 s17, s17, s18
	s_mul_hi_u32 s22, s16, s21
	s_mul_i32 s21, s16, s21
	s_add_u32 s17, s20, s17
	s_addc_u32 s19, 0, s19
	s_mul_hi_u32 s23, s16, s18
	s_add_u32 s17, s17, s21
	s_mul_i32 s18, s16, s18
	s_addc_u32 s17, s19, s22
	s_addc_u32 s19, s23, 0
	s_add_u32 s17, s17, s18
	s_addc_u32 s18, 0, s19
	v_add_co_u32 v1, s17, v1, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s17, 0
	s_addc_u32 s16, s16, s18
	v_readfirstlane_b32 s17, v1
	s_mul_i32 s18, s14, s16
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s19, s14, s17
	s_mul_i32 s15, s15, s17
	s_add_i32 s18, s19, s18
	s_mul_i32 s14, s14, s17
	s_add_i32 s18, s18, s15
	s_mul_hi_u32 s19, s16, s14
	s_mul_i32 s20, s16, s14
	s_mul_hi_u32 s14, s17, s14
	s_mul_hi_u32 s21, s17, s18
	s_mul_i32 s17, s17, s18
	s_mul_hi_u32 s15, s16, s18
	s_add_u32 s14, s14, s17
	s_addc_u32 s17, 0, s21
	s_add_u32 s14, s14, s20
	s_mul_i32 s18, s16, s18
	s_addc_u32 s14, s17, s19
	s_addc_u32 s15, s15, 0
	s_add_u32 s14, s14, s18
	s_addc_u32 s15, 0, s15
	v_add_co_u32 v1, s14, v1, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s14, 0
	s_addc_u32 s14, s16, s15
	v_readfirstlane_b32 s15, v1
	s_mul_i32 s17, s12, s14
	s_mul_hi_u32 s16, s12, s14
	s_mul_hi_u32 s18, s13, s14
	s_mul_i32 s14, s13, s14
	s_mul_hi_u32 s19, s12, s15
	s_mul_hi_u32 s20, s13, s15
	s_mul_i32 s15, s13, s15
	s_add_u32 s17, s19, s17
	s_addc_u32 s16, 0, s16
	s_add_u32 s15, s17, s15
	s_addc_u32 s15, s16, s20
	s_addc_u32 s16, s18, 0
	s_add_u32 s14, s15, s14
	s_addc_u32 s15, 0, s16
	s_mul_i32 s18, s8, s14
	s_mul_hi_u32 s16, s8, s14
	s_mul_i32 s19, s8, s15
	v_sub_co_u32 v1, s18, s12, s18
	s_mul_i32 s17, s9, s14
	s_add_i32 s16, s16, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s16, s16, s17
	v_sub_co_u32 v2, s19, v1, s8
	s_sub_i32 s17, s13, s16
	s_cmp_lg_u32 s18, 0
	v_readfirstlane_b32 s20, v1
	s_subb_u32 s17, s17, s9
	s_cmp_lg_u32 s19, 0
	v_readfirstlane_b32 s19, v2
	s_subb_u32 s17, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_ge_u32 s17, s9
	s_cselect_b32 s21, -1, 0
	s_cmp_ge_u32 s19, s8
	s_cselect_b32 s19, -1, 0
	s_cmp_eq_u32 s17, s9
	s_cselect_b32 s17, s19, s21
	s_add_u32 s19, s14, 1
	s_addc_u32 s21, s15, 0
	s_add_u32 s22, s14, 2
	s_addc_u32 s23, s15, 0
	s_cmp_lg_u32 s17, 0
	s_cselect_b32 s17, s22, s19
	s_cselect_b32 s19, s23, s21
	s_cmp_lg_u32 s18, 0
	s_subb_u32 s16, s13, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s16, s9
	s_cselect_b32 s18, -1, 0
	s_cmp_ge_u32 s20, s8
	s_cselect_b32 s20, -1, 0
	s_cmp_eq_u32 s16, s9
	s_cselect_b32 s16, s20, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s16, 0
	s_cselect_b32 s14, s17, s14
	s_cselect_b32 s15, s19, s15
	s_mul_i32 s16, s14, s9
	s_mul_hi_u32 s17, s14, s8
	s_mul_i32 s18, s15, s8
	s_mul_i32 s22, s15, s2
	s_add_i32 s15, s17, s16
	s_mul_i32 s19, s14, s8
	s_add_i32 s15, s15, s18
	s_mul_i32 s20, s14, s3
	s_mul_hi_u32 s21, s14, s2
	s_mul_i32 s16, s14, s2
	s_sub_u32 s14, s12, s19
	s_subb_u32 s15, s13, s15
	s_add_i32 s17, s21, s20
	v_cmp_gt_i64_e64 s18, s[14:15], 0
	s_add_i32 s17, s17, s22
	s_mov_b64 s[12:13], s[8:9]
	s_mov_b64 s[8:9], s[14:15]
	s_sub_u32 s14, s10, s16
	s_subb_u32 s15, s11, s17
	s_and_b32 vcc_lo, exec_lo, s18
	s_mov_b64 s[10:11], s[2:3]
	s_cbranch_vccnz .LBB2_12
; %bb.13:                               ; %_Z18extended_euclideanllPlS_S_.exit.i59
	v_cmp_lt_i64_e64 s3, s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_16
; %bb.14:
	s_add_i32 s3, s2, 1
	s_mov_b32 s9, 0
	s_and_b32 s8, s3, 0xffff
	s_branch .LBB2_17
.LBB2_15:
	s_mov_b64 s[8:9], 0x10000
	s_branch .LBB2_19
.LBB2_16:
	s_mov_b32 s9, -1
.LBB2_17:                               ; %Flow112
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB2_19
; %bb.18:
	s_and_b32 s8, s2, 0xffff
	s_mov_b32 s9, 0
.LBB2_19:                               ; %_Z3invt.exit61
	v_mov_b32_e32 v1, s8
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s9
	global_store_b64 v3, v[1:2], s[6:7] offset:24
	global_load_b64 v[1:2], v3, s[4:5] offset:368
	s_waitcnt vmcnt(0)
	global_store_b64 v3, v[1:2], s[6:7] offset:32
	global_load_b64 v[1:2], v3, s[4:5] offset:376
	s_waitcnt vmcnt(0)
	global_store_b64 v3, v[1:2], s[6:7] offset:40
.LBB2_20:                               ; %Flow118
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v1, -1, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 7, v1
	s_cbranch_execz .LBB2_38
; %bb.21:
	v_sub_nc_u32_e32 v1, 8, v0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0x10000
	v_mov_b32_e32 v6, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_i32_i24_e32 v3, 6, v1
	v_lshlrev_b64 v[1:2], 3, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v3, v[1:2], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u64_e32 0, v[3:4]
	s_cbranch_execz .LBB2_29
; %bb.22:                               ; %.lr.ph.i.i62.preheader
	v_mov_b32_e32 v5, 0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, 1
	v_dual_mov_b32 v7, 0x10001 :: v_dual_mov_b32 v10, 0
	v_mov_b32_e32 v8, 0
	s_mov_b32 s8, 0
.LBB2_23:                               ; %.lr.ph.i.i62
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v11, v3
	v_cvt_f32_u32_e32 v12, v4
	v_sub_co_u32 v18, vcc_lo, 0, v3
	v_sub_co_ci_u32_e32 v19, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, 0x4f800000, v12
	v_rcp_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, 0x5f7ffffc, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, 0x2f800000, v11
	v_trunc_f32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, 0xcf800000, v12
	v_cvt_u32_f32_e32 v20, v12
	v_cvt_u32_f32_e32 v21, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v13, v18, v20
	v_mul_lo_u32 v14, v19, v21
	v_mad_u64_u32 v[11:12], null, v18, v21, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v22, v12, v13, v14
	v_mul_hi_u32 v23, v21, v11
	v_mad_u64_u32 v[12:13], null, v20, v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, v21, v22, 0
	v_mad_u64_u32 v[16:17], null, v20, v22, 0
	v_add_co_u32 v11, vcc_lo, v23, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v11, vcc_lo, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, v14, v13, vcc_lo
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v17, vcc_lo
	v_add_co_u32 v11, vcc_lo, v11, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	v_add_co_u32 v17, vcc_lo, v21, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v20, vcc_lo, v20, v12, vcc_lo
	v_mad_u64_u32 v[11:12], null, v18, v17, 0
	v_mul_lo_u32 v15, v19, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v16, v18, v20
	v_mad_u64_u32 v[13:14], null, v20, v11, 0
	v_mul_hi_u32 v18, v17, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v19, v12, v16, v15
	v_mad_u64_u32 v[11:12], null, v17, v19, 0
	v_mad_u64_u32 v[15:16], null, v20, v19, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, v18, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v11, v13
	v_add_co_ci_u32_e32 v11, vcc_lo, v12, v14, vcc_lo
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v11, v15
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v17, v11
	v_add_co_ci_u32_e32 v17, vcc_lo, v20, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v18, v7, v13
	v_mad_u64_u32 v[11:12], null, v8, v13, 0
	v_mad_u64_u32 v[13:14], null, v7, v17, 0
	v_mad_u64_u32 v[15:16], null, v8, v17, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, v18, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v13, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, v14, v12, vcc_lo
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v11, v15
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v15, v4, v13
	v_mad_u64_u32 v[11:12], null, v3, v13, 0
	v_mul_lo_u32 v18, v3, v14
	v_add_co_u32 v16, vcc_lo, v13, 1
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v17, s1, v13, 2
	v_sub_co_u32 v11, vcc_lo, v7, v11
	v_add3_u32 v12, v12, v18, v15
	v_add_co_ci_u32_e64 v19, s1, 0, v14, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v8, v12
	v_sub_co_ci_u32_e64 v15, s1, v15, v4, vcc_lo
	v_sub_co_ci_u32_e32 v12, vcc_lo, v8, v12, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v11, v3
	v_sub_co_u32 v18, s1, v11, v3
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v15, vcc_lo, 0, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v18, v3
	v_cmp_ge_u32_e64 s1, v15, v4
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v12, v4
	v_cndmask_b32_e64 v21, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v12, v4
	v_cndmask_b32_e64 v12, 0, -1, s1
	v_cmp_eq_u32_e64 s1, v15, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v21, v11, vcc_lo
	v_cndmask_b32_e64 v12, v12, v18, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s1, 0, v11
	v_cmp_ne_u32_e32 vcc_lo, 0, v12
	v_cndmask_b32_e32 v12, v16, v17, vcc_lo
	v_cndmask_b32_e32 v11, v20, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v13, v12, s1
	v_cndmask_b32_e64 v16, v14, v11, s1
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v17, v15, v4
	v_mad_u64_u32 v[13:14], null, v15, v3, 0
	v_mul_lo_u32 v18, v16, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v19, v15, v12
	v_mad_u64_u32 v[9:10], null, v15, v11, 0
	v_mul_lo_u32 v15, v16, v11
	v_sub_co_u32 v13, vcc_lo, v7, v13
	v_add3_u32 v14, v14, v17, v18
	v_add3_u32 v7, v10, v19, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v14, vcc_lo, v8, v14, vcc_lo
	v_sub_co_u32 v9, vcc_lo, v5, v9
	v_sub_co_ci_u32_e32 v10, vcc_lo, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i64_e64 s1, 1, v[13:14]
	v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
	v_mov_b32_e32 v3, v13
	v_dual_mov_b32 v5, v11 :: v_dual_mov_b32 v6, v12
	v_mov_b32_e32 v4, v14
	s_or_b32 s8, s1, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_23
; %bb.24:                               ; %_Z18extended_euclideanllPlS_S_.exit.i67
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr5_vgpr6
	v_cmpx_gt_i64_e32 0, v[11:12]
	s_xor_b32 s1, exec_lo, s1
; %bb.25:
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v3, 1, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v5, 0xffff, v3
; %bb.26:                               ; %Flow108
	s_and_not1_saveexec_b32 s1, s1
; %bb.27:
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v5, 0xffff, v11
; %bb.28:                               ; %Flow109
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_29:                               ; %Flow110
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mul_u32_u24_e32 v3, 6, v0
	s_mov_b32 s3, exec_lo
	v_lshlrev_b32_e32 v7, 3, v3
	global_store_b64 v7, v[5:6], s[6:7]
	global_load_b64 v[3:4], v[1:2], off offset:16
	v_mov_b32_e32 v5, 0x10000
	v_mov_b32_e32 v6, 0
	s_waitcnt vmcnt(0)
	v_sub_co_u32 v3, vcc_lo, 0, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	global_store_b64 v7, v[3:4], s[6:7] offset:8
	global_load_b64 v[3:4], v[1:2], off offset:8
	s_waitcnt vmcnt(0)
	v_sub_co_u32 v3, vcc_lo, 0, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	global_store_b64 v7, v[3:4], s[6:7] offset:16
	v_mov_b32_e32 v4, 0
	global_load_b32 v1, v[1:2], off offset:24
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, 0xffff, v1
	v_add_co_u32 v1, s1, s6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v2, null, s7, 0, s1
	v_cmpx_ne_u64_e32 0, v[3:4]
	s_cbranch_execz .LBB2_37
; %bb.30:                               ; %.lr.ph.i.i70.preheader
	v_mov_b32_e32 v5, 0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, 1
	v_dual_mov_b32 v7, 0x10001 :: v_dual_mov_b32 v10, 0
	v_mov_b32_e32 v8, 0
	s_mov_b32 s8, 0
.LBB2_31:                               ; %.lr.ph.i.i70
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v11, v3
	v_cvt_f32_u32_e32 v12, v4
	v_sub_co_u32 v18, vcc_lo, 0, v3
	v_sub_co_ci_u32_e32 v19, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, 0x4f800000, v12
	v_rcp_f32_e32 v11, v11
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, 0x5f7ffffc, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, 0x2f800000, v11
	v_trunc_f32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, 0xcf800000, v12
	v_cvt_u32_f32_e32 v20, v12
	v_cvt_u32_f32_e32 v21, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v13, v18, v20
	v_mul_lo_u32 v14, v19, v21
	v_mad_u64_u32 v[11:12], null, v18, v21, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v22, v12, v13, v14
	v_mul_hi_u32 v23, v21, v11
	v_mad_u64_u32 v[12:13], null, v20, v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, v21, v22, 0
	v_mad_u64_u32 v[16:17], null, v20, v22, 0
	v_add_co_u32 v11, vcc_lo, v23, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v11, vcc_lo, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, v14, v13, vcc_lo
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v17, vcc_lo
	v_add_co_u32 v11, vcc_lo, v11, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	v_add_co_u32 v17, vcc_lo, v21, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v20, vcc_lo, v20, v12, vcc_lo
	v_mad_u64_u32 v[11:12], null, v18, v17, 0
	v_mul_lo_u32 v15, v19, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v16, v18, v20
	v_mad_u64_u32 v[13:14], null, v20, v11, 0
	v_mul_hi_u32 v18, v17, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v19, v12, v16, v15
	v_mad_u64_u32 v[11:12], null, v17, v19, 0
	v_mad_u64_u32 v[15:16], null, v20, v19, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, v18, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v11, v13
	v_add_co_ci_u32_e32 v11, vcc_lo, v12, v14, vcc_lo
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v11, v15
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v17, v11
	v_add_co_ci_u32_e32 v17, vcc_lo, v20, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v18, v7, v13
	v_mad_u64_u32 v[11:12], null, v8, v13, 0
	v_mad_u64_u32 v[13:14], null, v7, v17, 0
	v_mad_u64_u32 v[15:16], null, v8, v17, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, v18, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v13, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, v14, v12, vcc_lo
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v11, v15
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v15, v4, v13
	v_mad_u64_u32 v[11:12], null, v3, v13, 0
	v_mul_lo_u32 v18, v3, v14
	v_add_co_u32 v16, vcc_lo, v13, 1
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v17, s1, v13, 2
	v_sub_co_u32 v11, vcc_lo, v7, v11
	v_add3_u32 v12, v12, v18, v15
	v_add_co_ci_u32_e64 v19, s1, 0, v14, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v8, v12
	v_sub_co_ci_u32_e64 v15, s1, v15, v4, vcc_lo
	v_sub_co_ci_u32_e32 v12, vcc_lo, v8, v12, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v11, v3
	v_sub_co_u32 v18, s1, v11, v3
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v15, vcc_lo, 0, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v18, v3
	v_cmp_ge_u32_e64 s1, v15, v4
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v12, v4
	v_cndmask_b32_e64 v21, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v12, v4
	v_cndmask_b32_e64 v12, 0, -1, s1
	v_cmp_eq_u32_e64 s1, v15, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v21, v11, vcc_lo
	v_cndmask_b32_e64 v12, v12, v18, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s1, 0, v11
	v_cmp_ne_u32_e32 vcc_lo, 0, v12
	v_cndmask_b32_e32 v12, v16, v17, vcc_lo
	v_cndmask_b32_e32 v11, v20, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v13, v12, s1
	v_cndmask_b32_e64 v16, v14, v11, s1
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v17, v15, v4
	v_mad_u64_u32 v[13:14], null, v15, v3, 0
	v_mul_lo_u32 v18, v16, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v19, v15, v12
	v_mad_u64_u32 v[9:10], null, v15, v11, 0
	v_mul_lo_u32 v15, v16, v11
	v_sub_co_u32 v13, vcc_lo, v7, v13
	v_add3_u32 v14, v14, v17, v18
	v_add3_u32 v7, v10, v19, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v14, vcc_lo, v8, v14, vcc_lo
	v_sub_co_u32 v9, vcc_lo, v5, v9
	v_sub_co_ci_u32_e32 v10, vcc_lo, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_i64_e64 s1, 1, v[13:14]
	v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
	v_mov_b32_e32 v3, v13
	v_dual_mov_b32 v5, v11 :: v_dual_mov_b32 v6, v12
	v_mov_b32_e32 v4, v14
	s_or_b32 s8, s1, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB2_31
; %bb.32:                               ; %_Z18extended_euclideanllPlS_S_.exit.i75
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr5_vgpr6
	v_cmpx_gt_i64_e32 0, v[11:12]
	s_xor_b32 s1, exec_lo, s1
; %bb.33:
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v3, 1, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v5, 0xffff, v3
; %bb.34:                               ; %Flow105
	s_and_not1_saveexec_b32 s1, s1
; %bb.35:
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v5, 0xffff, v11
; %bb.36:                               ; %Flow106
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_37:                               ; %Flow107
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_xor_b32_e32 v0, 7, v0
	global_store_b64 v[1:2], v[5:6], off offset:24
	v_mul_u32_u24_e32 v0, 6, v0
	v_lshlrev_b32_e32 v0, 3, v0
	global_load_b64 v[3:4], v0, s[4:5] offset:32
	s_waitcnt vmcnt(0)
	global_store_b64 v[1:2], v[3:4], off offset:32
	global_load_b64 v[3:4], v0, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	global_store_b64 v[1:2], v[3:4], off offset:40
.LBB2_38:                               ; %Flow111
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_58
; %bb.39:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s3, 0
	s_mov_b64 s[8:9], 0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v0, v0, s[4:5]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, 0xffff
	s_cmp_eq_u64 s[2:3], 0
	s_cbranch_scc1 .LBB2_44
; %bb.40:                               ; %.lr.ph.i.i78.preheader
	s_mov_b64 s[10:11], 0x10001
	s_mov_b64 s[12:13], 1
.LBB2_41:                               ; %.lr.ph.i.i78
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v0, s2
	v_cvt_f32_u32_e32 v1, s3
	s_mov_b64 s[0:1], s[12:13]
	s_sub_u32 s12, 0, s2
	s_subb_u32 s13, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, 0x4f800000, v1
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x2f800000, v0
	v_trunc_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, 0xcf800000, v1
	v_cvt_u32_f32_e32 v1, v1
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s14, v1
	v_readfirstlane_b32 s15, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s16, s12, s14
	s_mul_hi_u32 s18, s12, s15
	s_mul_i32 s17, s13, s15
	s_add_i32 s16, s18, s16
	s_mul_i32 s19, s12, s15
	s_add_i32 s16, s16, s17
	s_mul_hi_u32 s18, s15, s19
	s_mul_hi_u32 s17, s15, s16
	s_mul_i32 s15, s15, s16
	s_mul_hi_u32 s20, s14, s19
	s_mul_i32 s19, s14, s19
	s_add_u32 s15, s18, s15
	s_addc_u32 s17, 0, s17
	s_mul_hi_u32 s21, s14, s16
	s_add_u32 s15, s15, s19
	s_mul_i32 s16, s14, s16
	s_addc_u32 s15, s17, s20
	s_addc_u32 s17, s21, 0
	s_add_u32 s15, s15, s16
	s_addc_u32 s16, 0, s17
	v_add_co_u32 v0, s15, v0, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s15, 0
	s_addc_u32 s14, s14, s16
	v_readfirstlane_b32 s15, v0
	s_mul_i32 s16, s12, s14
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s17, s12, s15
	s_mul_i32 s13, s13, s15
	s_add_i32 s16, s17, s16
	s_mul_i32 s12, s12, s15
	s_add_i32 s16, s16, s13
	s_mul_hi_u32 s17, s14, s12
	s_mul_i32 s18, s14, s12
	s_mul_hi_u32 s12, s15, s12
	s_mul_hi_u32 s19, s15, s16
	s_mul_i32 s15, s15, s16
	s_mul_hi_u32 s13, s14, s16
	s_add_u32 s12, s12, s15
	s_addc_u32 s15, 0, s19
	s_add_u32 s12, s12, s18
	s_mul_i32 s16, s14, s16
	s_addc_u32 s12, s15, s17
	s_addc_u32 s13, s13, 0
	s_add_u32 s12, s12, s16
	s_addc_u32 s13, 0, s13
	v_add_co_u32 v0, s12, v0, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s12, 0
	s_addc_u32 s12, s14, s13
	v_readfirstlane_b32 s13, v0
	s_mul_i32 s15, s10, s12
	s_mul_hi_u32 s14, s10, s12
	s_mul_hi_u32 s16, s11, s12
	s_mul_i32 s12, s11, s12
	s_mul_hi_u32 s17, s10, s13
	s_mul_hi_u32 s18, s11, s13
	s_mul_i32 s13, s11, s13
	s_add_u32 s15, s17, s15
	s_addc_u32 s14, 0, s14
	s_add_u32 s13, s15, s13
	s_addc_u32 s13, s14, s18
	s_addc_u32 s14, s16, 0
	s_add_u32 s12, s13, s12
	s_addc_u32 s13, 0, s14
	s_mul_i32 s16, s2, s12
	s_mul_hi_u32 s14, s2, s12
	s_mul_i32 s17, s2, s13
	v_sub_co_u32 v0, s16, s10, s16
	s_mul_i32 s15, s3, s12
	s_add_i32 s14, s14, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s14, s14, s15
	v_sub_co_u32 v1, s17, v0, s2
	s_sub_i32 s15, s11, s14
	s_cmp_lg_u32 s16, 0
	v_readfirstlane_b32 s18, v0
	s_subb_u32 s15, s15, s3
	s_cmp_lg_u32 s17, 0
	v_readfirstlane_b32 s17, v1
	s_subb_u32 s15, s15, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_ge_u32 s15, s3
	s_cselect_b32 s19, -1, 0
	s_cmp_ge_u32 s17, s2
	s_cselect_b32 s17, -1, 0
	s_cmp_eq_u32 s15, s3
	s_cselect_b32 s15, s17, s19
	s_add_u32 s17, s12, 1
	s_addc_u32 s19, s13, 0
	s_add_u32 s20, s12, 2
	s_addc_u32 s21, s13, 0
	s_cmp_lg_u32 s15, 0
	s_cselect_b32 s15, s20, s17
	s_cselect_b32 s17, s21, s19
	s_cmp_lg_u32 s16, 0
	s_subb_u32 s14, s11, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s14, s3
	s_cselect_b32 s16, -1, 0
	s_cmp_ge_u32 s18, s2
	s_cselect_b32 s18, -1, 0
	s_cmp_eq_u32 s14, s3
	s_cselect_b32 s14, s18, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s14, 0
	s_cselect_b32 s12, s15, s12
	s_cselect_b32 s13, s17, s13
	s_mul_i32 s14, s12, s3
	s_mul_hi_u32 s15, s12, s2
	s_mul_i32 s16, s13, s2
	s_mul_i32 s20, s13, s0
	s_add_i32 s13, s15, s14
	s_mul_i32 s17, s12, s2
	s_add_i32 s13, s13, s16
	s_mul_i32 s18, s12, s1
	s_mul_hi_u32 s19, s12, s0
	s_mul_i32 s14, s12, s0
	s_sub_u32 s12, s10, s17
	s_subb_u32 s13, s11, s13
	s_add_i32 s15, s19, s18
	v_cmp_gt_i64_e64 s16, s[12:13], 0
	s_add_i32 s15, s15, s20
	s_mov_b64 s[10:11], s[2:3]
	s_mov_b64 s[2:3], s[12:13]
	s_sub_u32 s12, s8, s14
	s_subb_u32 s13, s9, s15
	s_and_b32 vcc_lo, exec_lo, s16
	s_mov_b64 s[8:9], s[0:1]
	s_cbranch_vccnz .LBB2_41
; %bb.42:                               ; %_Z18extended_euclideanllPlS_S_.exit.i83
	v_cmp_lt_i64_e64 s1, s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_45
; %bb.43:
	s_add_i32 s1, s0, 1
	s_mov_b32 s3, 0
	s_and_b32 s2, s1, 0xffff
	s_branch .LBB2_46
.LBB2_44:
	s_mov_b64 s[2:3], 0x10000
	s_branch .LBB2_48
.LBB2_45:
	s_mov_b32 s3, -1
.LBB2_46:                               ; %Flow101
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB2_48
; %bb.47:
	s_and_b32 s2, s0, 0xffff
	s_mov_b32 s3, 0
.LBB2_48:                               ; %_Z3invt.exit85
	v_mov_b32_e32 v0, s2
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
	s_mov_b32 s3, 0
	global_store_b64 v2, v[0:1], s[6:7] offset:384
	global_load_b64 v[0:1], v2, s[4:5] offset:8
	s_waitcnt vmcnt(0)
	v_sub_co_u32 v0, vcc_lo, 0, v0
	v_sub_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	global_store_b64 v2, v[0:1], s[6:7] offset:392
	global_load_b64 v[0:1], v2, s[4:5] offset:16
	s_waitcnt vmcnt(0)
	v_sub_co_u32 v0, vcc_lo, 0, v0
	v_sub_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	global_store_b64 v2, v[0:1], s[6:7] offset:400
	global_load_b32 v0, v2, s[4:5] offset:24
	s_mov_b64 s[4:5], 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s0, 0xffff
	s_cmp_eq_u64 s[2:3], 0
	s_cbranch_scc1 .LBB2_53
; %bb.49:                               ; %.lr.ph.i.i86.preheader
	s_mov_b64 s[8:9], 0x10001
	s_mov_b64 s[10:11], 1
.LBB2_50:                               ; %.lr.ph.i.i86
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v0, s2
	v_cvt_f32_u32_e32 v1, s3
	s_mov_b64 s[0:1], s[10:11]
	s_sub_u32 s10, 0, s2
	s_subb_u32 s11, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, 0x4f800000, v1
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x2f800000, v0
	v_trunc_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, 0xcf800000, v1
	v_cvt_u32_f32_e32 v1, v1
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s12, v1
	v_readfirstlane_b32 s13, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s14, s10, s12
	s_mul_hi_u32 s16, s10, s13
	s_mul_i32 s15, s11, s13
	s_add_i32 s14, s16, s14
	s_mul_i32 s17, s10, s13
	s_add_i32 s14, s14, s15
	s_mul_hi_u32 s16, s13, s17
	s_mul_hi_u32 s15, s13, s14
	s_mul_i32 s13, s13, s14
	s_mul_hi_u32 s18, s12, s17
	s_mul_i32 s17, s12, s17
	s_add_u32 s13, s16, s13
	s_addc_u32 s15, 0, s15
	s_mul_hi_u32 s19, s12, s14
	s_add_u32 s13, s13, s17
	s_mul_i32 s14, s12, s14
	s_addc_u32 s13, s15, s18
	s_addc_u32 s15, s19, 0
	s_add_u32 s13, s13, s14
	s_addc_u32 s14, 0, s15
	v_add_co_u32 v0, s13, v0, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s13, 0
	s_addc_u32 s12, s12, s14
	v_readfirstlane_b32 s13, v0
	s_mul_i32 s14, s10, s12
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s15, s10, s13
	s_mul_i32 s11, s11, s13
	s_add_i32 s14, s15, s14
	s_mul_i32 s10, s10, s13
	s_add_i32 s14, s14, s11
	s_mul_hi_u32 s15, s12, s10
	s_mul_i32 s16, s12, s10
	s_mul_hi_u32 s10, s13, s10
	s_mul_hi_u32 s17, s13, s14
	s_mul_i32 s13, s13, s14
	s_mul_hi_u32 s11, s12, s14
	s_add_u32 s10, s10, s13
	s_addc_u32 s13, 0, s17
	s_add_u32 s10, s10, s16
	s_mul_i32 s14, s12, s14
	s_addc_u32 s10, s13, s15
	s_addc_u32 s11, s11, 0
	s_add_u32 s10, s10, s14
	s_addc_u32 s11, 0, s11
	v_add_co_u32 v0, s10, v0, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s10, 0
	s_addc_u32 s10, s12, s11
	v_readfirstlane_b32 s11, v0
	s_mul_i32 s13, s8, s10
	s_mul_hi_u32 s12, s8, s10
	s_mul_hi_u32 s14, s9, s10
	s_mul_i32 s10, s9, s10
	s_mul_hi_u32 s15, s8, s11
	s_mul_hi_u32 s16, s9, s11
	s_mul_i32 s11, s9, s11
	s_add_u32 s13, s15, s13
	s_addc_u32 s12, 0, s12
	s_add_u32 s11, s13, s11
	s_addc_u32 s11, s12, s16
	s_addc_u32 s12, s14, 0
	s_add_u32 s10, s11, s10
	s_addc_u32 s11, 0, s12
	s_mul_i32 s14, s2, s10
	s_mul_hi_u32 s12, s2, s10
	s_mul_i32 s15, s2, s11
	v_sub_co_u32 v0, s14, s8, s14
	s_mul_i32 s13, s3, s10
	s_add_i32 s12, s12, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s12, s12, s13
	v_sub_co_u32 v1, s15, v0, s2
	s_sub_i32 s13, s9, s12
	s_cmp_lg_u32 s14, 0
	v_readfirstlane_b32 s16, v0
	s_subb_u32 s13, s13, s3
	s_cmp_lg_u32 s15, 0
	v_readfirstlane_b32 s15, v1
	s_subb_u32 s13, s13, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_ge_u32 s13, s3
	s_cselect_b32 s17, -1, 0
	s_cmp_ge_u32 s15, s2
	s_cselect_b32 s15, -1, 0
	s_cmp_eq_u32 s13, s3
	s_cselect_b32 s13, s15, s17
	s_add_u32 s15, s10, 1
	s_addc_u32 s17, s11, 0
	s_add_u32 s18, s10, 2
	s_addc_u32 s19, s11, 0
	s_cmp_lg_u32 s13, 0
	s_cselect_b32 s13, s18, s15
	s_cselect_b32 s15, s19, s17
	s_cmp_lg_u32 s14, 0
	s_subb_u32 s12, s9, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s12, s3
	s_cselect_b32 s14, -1, 0
	s_cmp_ge_u32 s16, s2
	s_cselect_b32 s16, -1, 0
	s_cmp_eq_u32 s12, s3
	s_cselect_b32 s12, s16, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s12, 0
	s_cselect_b32 s10, s13, s10
	s_cselect_b32 s11, s15, s11
	s_mul_i32 s12, s10, s3
	s_mul_hi_u32 s13, s10, s2
	s_mul_i32 s14, s11, s2
	s_mul_i32 s18, s11, s0
	s_add_i32 s11, s13, s12
	s_mul_i32 s15, s10, s2
	s_add_i32 s11, s11, s14
	s_mul_i32 s16, s10, s1
	s_mul_hi_u32 s17, s10, s0
	s_mul_i32 s12, s10, s0
	s_sub_u32 s10, s8, s15
	s_subb_u32 s11, s9, s11
	s_add_i32 s13, s17, s16
	v_cmp_gt_i64_e64 s14, s[10:11], 0
	s_add_i32 s13, s13, s18
	s_mov_b64 s[8:9], s[2:3]
	s_mov_b64 s[2:3], s[10:11]
	s_sub_u32 s10, s4, s12
	s_subb_u32 s11, s5, s13
	s_and_b32 vcc_lo, exec_lo, s14
	s_mov_b64 s[4:5], s[0:1]
	s_cbranch_vccnz .LBB2_50
; %bb.51:                               ; %_Z18extended_euclideanllPlS_S_.exit.i91
	v_cmp_lt_i64_e64 s1, s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_54
; %bb.52:
	s_add_i32 s1, s0, 1
	s_mov_b32 s3, 0
	s_and_b32 s2, s1, 0xffff
	s_branch .LBB2_55
.LBB2_53:
	s_mov_b64 s[2:3], 0x10000
	s_branch .LBB2_57
.LBB2_54:
	s_mov_b32 s3, -1
.LBB2_55:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB2_57
; %bb.56:
	s_and_b32 s2, s0, 0xffff
	s_mov_b32 s3, 0
.LBB2_57:                               ; %_Z3invt.exit93
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, v2
	s_clause 0x1
	global_store_b64 v2, v[2:3], s[6:7] offset:432
	global_store_b128 v2, v[0:3], s[6:7] offset:408
.LBB2_58:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28IDEA_decryption_key_schedulePlS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z28IDEA_decryption_key_schedulePlS_, .Lfunc_end2-_Z28IDEA_decryption_key_schedulePlS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5660
; NumSgprs: 26
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15IDEA_encryptionPtS_Pl
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z15IDEA_encryptionPtS_Pl.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28IDEA_encryption_key_schedulePtPl
    .private_segment_fixed_size: 528
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z28IDEA_encryption_key_schedulePtPl.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28IDEA_decryption_key_schedulePlS_
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z28IDEA_decryption_key_schedulePlS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
