#include <stdio.h>
#include <cuda.h>
#include <math.h>

typedef unsigned long long ll;

void printSum(float * H, ll ss) {

	float all = 0;
	for (ll i = 0; i < ss; i++) {
		all += H[i];
		
	}
	printf("avg = %.3f\n", all/ss);
}
__device__ bool zeroArea (ll i, ll n, ll iter)
{
    ll row = i/(1+n);
    ll col = i%(1+n);
    return iter < row && row < n-iter && iter < col && col < n - iter;
}

__device__ ll mediumTrans(ll n, ll iter, ll i)
{
    ll temp = (n+2)*(n-iter-1)+1;
     if (i>= temp){ 
	return i-(n-2*iter-1)*(n-2*iter-1);
	}
    else if ( i<temp&&(n+1)*(iter+1)+iter<i) {
        return i-((i-(iter+1)*(n+2))/(n+1)+1)*(n-2*iter-1);
    }
    
    return i;
}

__device__ ll revertMediumTrans (ll n, ll iter, ll newIdx)
{
    ll temp = 3*iter*n+3*n-4*iter*iter-6*iter-2;
    if (newIdx >= temp){
        return newIdx + (n-2*iter-1)*(n-2*iter-1);
    }
    else if ( newIdx<temp &&(n+1)*(iter+1)+iter<newIdx) {
        return newIdx + ((newIdx-(n+2)*(iter+1))*(n-2*iter-1)/(2*(iter+1))+1);
    }
   
    return newIdx;
}

__device__ ll matrixTrans (ll n, ll idx)
{
    return n+2+idx+2*(idx/(n-1));
}


__device__ ll revertMatrixTrans (ll n, ll iter, ll midiumIdx)
{
    ll idx = midiumIdx;
    ll temp = 3*iter*n-4*iter*iter-4*iter;
	
	if(midiumIdx >= temp){
        idx = midiumIdx+(n-2*iter-1)*(n-2*iter-1);
        return matrixTrans(n, idx);
    }
	else if(midiumIdx< temp && iter*n-1<midiumIdx) {
        idx=((midiumIdx-iter*n)/(2*iter)+1)*(n-2*iter-1)+midiumIdx;
        return matrixTrans(n, idx);
    }
    
    return matrixTrans(n, idx);
}

ll transHost(ll n, ll iter, ll i)
{
    ll temp = (n+2)*(n-iter-1) + 1;
    if (i>= temp){ 
	return i-pow((n-2*iter-1),2);
	}
    else if ( i<temp && ((n+1)*(iter + 1)+iter) < i){ 
	    return i-(n-2*iter-1)*((i-(n+2)*(iter+1))/(n+1)+1);
	}
    return i;
}

void printDeviceInfo(ll index) {
	cudaDeviceProp prop;
	if (cudaGetDeviceProperties(&prop, index) != cudaSuccess) {
		printf("Get device properties error!");
		exit(EXIT_FAILURE);
	}
	printf("\n#Device %d#\n\nName: %s\nWarp size: %d\nMax threads per block: %d\nMax thread dimension: x => %d, y => %d, z=> %d\n Max grid dimension: x => %d, y = %d, z => %d\n",index, prop.name, prop.warpSize, prop.maxThreadsPerBlock, prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2], prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);

}

__global__ void calculateKernel(float * A, float * B, ll qq) {

        int gridnum = blockIdx.x * blockDim.x + threadIdx.x;
        int indexindex =qq+gridnum%(qq-2)+qq*(gridnum/(qq-2))+1;

        if ( gridnum<(qq-2)*(qq-2))  {
                B[indexindex] = (A[indexindex-qq]+A[indexindex+qq]+ A[indexindex+1]+ A[indexindex-1])/4;
        }
}

__global__ void calculateKernelUpdate(float * A, float * B, ll n, ll iter) {

	ll i = blockIdx.x * blockDim.x + threadIdx.x;
	if (blockIdx.x * blockDim.x + threadIdx.x >= 4 * iter * (n-iter-1) ) return;

    float lf;
    float rr;
	float uu;
    float dd;

	i = revertMatrixTrans(n, iter, (blockIdx.x * blockDim.x + threadIdx.x));
        lf = zeroArea(i-1, n, iter) ? 0 : A[mediumTrans(n, iter, i - 1)];
        rr = zeroArea(i+1, n, iter) ? 0 : A[mediumTrans(n, iter, i + 1)];

        uu = zeroArea(i-(n + 1), n, iter) ? 0 : A[mediumTrans(n, iter, i - n - 1)];
        dd = zeroArea(i+(n + 1), n, iter) ? 0 : A[mediumTrans(n, iter, i + n + 1)];
        
	B[mediumTrans(n, iter, i)] = (lf + rr + uu + dd) / 4;
	
}
const int BS = 1024;

void calcDist(ll n, int iter, bool initialState) {

        ll i= (n+1)*(n+1)*sizeof(float);
        ll memsize = (n+1)*(n+1)*sizeof(float);

        float * H = (float*) calloc ((n+1)*(n+1), sizeof(float));

        for (i = 0; i < n+1; i++) {
                H[i] = (i >= 10 && i <= 30) ? 150 : 80;
                H[i*(n+1)] = 80;
                H[n*(n+1)+i] = 80;
                H[i*(n+1) + n] = 80;
        }

        float *Pd, *Qd;


        cudaMalloc((void**) &Qd, memsize);
        cudaMalloc((void**) &Pd, memsize);
        cudaMemcpy(Pd, H, memsize, cudaMemcpyHostToDevice);
        cudaMemcpy(Qd, H, memsize, cudaMemcpyHostToDevice);


        for (i = 0; i < iter; i++) {
                if (i%2 == 0)
                        calculateKernel<<<ceil((double) (n-1)*(n-1)/BS), BS>>>(Pd, Qd, n+1);
                else
                        calculateKernel<<<ceil((double) (n-1)*(n-1)/BS), BS>>>(Qd, Pd, n+1);
        }


        cudaMemcpy(H, (i%2==1)?Qd:Pd , memsize, cudaMemcpyDeviceToHost);

        if(initialState) printSum(H,(n+1)*(n+1));
        //CLEAN UP
        cudaFree(Pd);
        cudaFree(Qd);

        free(H);
}

void calcDistOptimized(ll n, ll iter, bool initialState) {

	ll i = (4*n+4*iter*(n-iter-1))*sizeof(float);
    ll memsize = (4*n+4*iter*(n-iter-1))*sizeof(float);
	float * H = (float*) calloc ((4*n+4*iter*(n-iter-1)), sizeof(float));

	for (i = 0; i < n+1; i++) {
		H[transHost(n, iter, i)] = (i >= 10 && i <= 30) ? 150 : 80;
		H[transHost(n, iter, i * (n + 1))] = 80;
		H[transHost(n, iter, (n + 1)*n + i)] = 80;
		H[transHost(n, iter, i * (n + 1) + n)] = 80;
	}

	float *Pd, *Qd;
	
	cudaMalloc((void**) &Qd, memsize);
	cudaMalloc((void**) &Pd, memsize);
	cudaMemcpy(Pd, H, memsize, cudaMemcpyHostToDevice);
	cudaMemcpy(Qd, H, memsize, cudaMemcpyHostToDevice);

	for (i = 0; i < iter; i++) {
		if (i%2 == 0)
			calculateKernelUpdate<<<ceil((double) (4*iter*(n-iter-1))/BS), BS>>>(Pd, Qd, n, iter); 
		else
			calculateKernelUpdate<<<ceil((double) (4*iter*(n-iter-1))/BS), BS>>>(Qd, Pd, n, iter);
	}

	cudaMemcpy(H, (i%2==1)?Qd:Pd , memsize, cudaMemcpyDeviceToHost);

	if(initialState) printSum(H, n);
		
	cudaFree(Pd);
	cudaFree(Qd);

	free(H);
	
}
int main(int argc, char * argv[]) {
  
   //clock_t start = clock();
	ll n = 10000;
	ll iter = 500;

	bool initialState = false;
	if (argc > 1) n = atoi(argv[1]);
	if (argc > 2) iter = atoi(argv[2]);
	if (argc > 3) initialState = true;

	//dim3 dimGrid(
	int count, i;
	if (cudaGetDeviceCount(&count) != cudaSuccess) {
		printf("Get device count error!");
		exit(EXIT_FAILURE);
	}

	for (i = 0; i < count; i++) {
	}
	if ( n+1 > 2*(iter+1)) calcDistOptimized(n, iter, initialState);
	else calcDist(n, iter, initialState); 
	//clock_t end = (clock() - start)/1000;
  //printf("time: %ldms\n", end);
		
}


	.file	"tmpxft_003129f5_00000000-6_cuda-optimized.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2040:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2040:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"avg = %.3f\n"
	.text
	.globl	_Z8printSumPfy
	.type	_Z8printSumPfy, @function
_Z8printSumPfy:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L3:
	cmpq	%rsi, %rax
	je	.L6
	addss	(%rdi,%rax,4), %xmm0
	incq	%rax
	jmp	.L3
.L6:
	cvtsi2ssq	%rax, %xmm1
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z8printSumPfy, .-_Z8printSumPfy
	.globl	_Z8zeroAreayyy
	.type	_Z8zeroAreayyy, @function
_Z8zeroAreayyy:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z8zeroAreayyy, .-_Z8zeroAreayyy
	.globl	_Z11mediumTransyyy
	.type	_Z11mediumTransyyy, @function
_Z11mediumTransyyy:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z11mediumTransyyy, .-_Z11mediumTransyyy
	.globl	_Z17revertMediumTransyyy
	.type	_Z17revertMediumTransyyy, @function
_Z17revertMediumTransyyy:
.LFB2185:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2185:
	.size	_Z17revertMediumTransyyy, .-_Z17revertMediumTransyyy
	.globl	_Z11matrixTransyy
	.type	_Z11matrixTransyy, @function
_Z11matrixTransyy:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z11matrixTransyy, .-_Z11matrixTransyy
	.globl	_Z17revertMatrixTransyyy
	.type	_Z17revertMatrixTransyyy, @function
_Z17revertMatrixTransyyy:
.LFB2187:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2187:
	.size	_Z17revertMatrixTransyyy, .-_Z17revertMatrixTransyyy
	.globl	_Z9transHostyyy
	.type	_Z9transHostyyy, @function
_Z9transHostyyy:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	%rdi, %rcx
	movq	%rsi, %rdi
	movq	%rdx, %rsi
	movq	%rcx, %rax
	leaq	2(%rcx), %rdx
	subq	%rdi, %rax
	decq	%rax
	imulq	%rdx, %rax
	incq	%rax
	cmpq	%rax, %rsi
	jb	.L18
	decq	%rcx
	leaq	(%rdi,%rdi), %rdx
	subq	%rdx, %rcx
	js	.L19
	cvtsi2sdq	%rcx, %xmm1
	jmp	.L20
.L19:
	movq	%rcx, %rax
	andl	$1, %ecx
	shrq	%rax
	orq	%rcx, %rax
	cvtsi2sdq	%rax, %xmm1
	addsd	%xmm1, %xmm1
.L20:
	testq	%rsi, %rsi
	js	.L21
	cvtsi2sdq	%rsi, %xmm0
	jmp	.L22
.L21:
	movq	%rsi, %rax
	andl	$1, %esi
	shrq	%rax
	orq	%rsi, %rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L22:
	mulsd	%xmm1, %xmm1
	subsd	%xmm1, %xmm0
	movsd	.LC2(%rip), %xmm1
	comisd	%xmm1, %xmm0
	jnb	.L23
	cvttsd2siq	%xmm0, %rsi
	jmp	.L25
.L23:
	subsd	%xmm1, %xmm0
	cvttsd2siq	%xmm0, %rsi
	btcq	$63, %rsi
	jmp	.L25
.L18:
	leaq	1(%rcx), %r8
	leaq	1(%rdi), %rax
	movq	%r8, %rdx
	imulq	%rax, %rdx
	leaq	(%rdx,%rdi), %r9
	cmpq	%rsi, %r9
	jnb	.L25
	addq	%rax, %rdx
	movq	%rsi, %rax
	decq	%rcx
	subq	%rdx, %rax
	xorl	%edx, %edx
	divq	%r8
	leaq	(%rdi,%rdi), %rdx
	subq	%rdx, %rcx
	incq	%rax
	imulq	%rcx, %rax
	subq	%rax, %rsi
.L25:
	movq	%rsi, %rax
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z9transHostyyy, .-_Z9transHostyyy
	.section	.rodata.str1.1
.LC3:
	.string	"Get device properties error!"
.LC4:
	.string	"\n#Device %d#\n\nName: %s\nWarp size: %d\nMax threads per block: %d\nMax thread dimension: x => %d, y => %d, z=> %d\n Max grid dimension: x => %d, y = %d, z => %d\n"
	.text
	.globl	_Z15printDeviceInfoy
	.type	_Z15printDeviceInfoy, @function
_Z15printDeviceInfoy:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%edi, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	subq	$1048, %rsp
	.cfi_def_cfa_offset 1072
	movq	%fs:40, %rax
	movq	%rax, 1032(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rbp
	movq	%rbp, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	testl	%eax, %eax
	je	.L27
	movl	$2, %edi
	leaq	.LC3(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L27:
	movl	344(%rsp), %eax
	movq	%rbp, %rcx
	movq	%rbx, %rdx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	pushq	%rax
	.cfi_def_cfa_offset 1080
	movl	348(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 1088
	movl	352(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 1096
	movl	356(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 1104
	movl	360(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 1112
	movl	364(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 1120
	movl	368(%rsp), %r9d
	xorl	%eax, %eax
	movl	356(%rsp), %r8d
	call	__printf_chk@PLT
	addq	$48, %rsp
	.cfi_def_cfa_offset 1072
	movq	1032(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$1048, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z15printDeviceInfoy, .-_Z15printDeviceInfoy
	.globl	_Z38__device_stub__Z15calculateKernelPfS_yPfS_y
	.type	_Z38__device_stub__Z15calculateKernelPfS_yPfS_y, @function
_Z38__device_stub__Z15calculateKernelPfS_yPfS_y:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15calculateKernelPfS_y(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L30:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z38__device_stub__Z15calculateKernelPfS_yPfS_y, .-_Z38__device_stub__Z15calculateKernelPfS_yPfS_y
	.globl	_Z15calculateKernelPfS_y
	.type	_Z15calculateKernelPfS_y, @function
_Z15calculateKernelPfS_y:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z15calculateKernelPfS_yPfS_y
	.cfi_endproc
.LFE2063:
	.size	_Z15calculateKernelPfS_y, .-_Z15calculateKernelPfS_y
	.globl	_Z8calcDistyib
	.type	_Z8calcDistyib, @function
_Z8calcDistyib:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%esi, %r15
	movl	$4, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	1(%rdi), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movq	%rbp, %rax
	imulq	%rbp, %rax
	movq	%rax, 8(%rsp)
	movq	8(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, (%rsp)
	call	calloc@PLT
	movss	.LC6(%rip), %xmm0
	movq	%rax, %rbx
	leaq	0(,%r12,4), %rax
	leaq	4(%rax), %rsi
	movq	%rbx, %rcx
	imulq	%rbp, %rax
	leaq	(%rbx,%rax), %rdx
	xorl	%eax, %eax
.L36:
	cmpq	%rbp, %rax
	jnb	.L57
	leaq	-10(%rax), %rdi
	movaps	%xmm0, %xmm1
	cmpq	$20, %rdi
	ja	.L37
	movss	.LC5(%rip), %xmm1
.L37:
	movss	%xmm1, (%rbx,%rax,4)
	movss	%xmm0, (%rcx)
	movss	%xmm0, (%rdx,%rax,4)
	incq	%rax
	movss	%xmm0, (%rcx,%r12,4)
	addq	%rsi, %rcx
	jmp	.L36
.L57:
	movq	(%rsp), %rsi
	leaq	24(%rsp), %rdi
	xorl	%r13d, %r13d
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	16(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	24(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
.L39:
	movq	%r13, %rax
	andl	$1, %eax
	cmpq	%r15, %r13
	jnb	.L58
	testq	%rax, %rax
	movl	$1, 52(%rsp)
	movabsq	$4294968320, %rdx
	movsd	.LC7(%rip), %xmm1
	movq	%rdx, 44(%rsp)
	leaq	-1(%r12), %rax
	jne	.L40
	testq	%rax, %rax
	js	.L41
	cvtsi2sdq	%rax, %xmm0
	jmp	.L42
.L41:
	movq	%rax, %rdx
	andl	$1, %eax
	shrq	%rdx
	orq	%rax, %rdx
	cvtsi2sdq	%rdx, %xmm0
	addsd	%xmm0, %xmm0
.L42:
	mulsd	%xmm0, %xmm0
	mulsd	%xmm1, %xmm0
	call	ceil@PLT
	movl	52(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttsd2siq	%xmm0, %rax
	movq	44(%rsp), %rdx
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	jmp	.L56
.L40:
	testq	%rax, %rax
	js	.L45
	cvtsi2sdq	%rax, %xmm0
	jmp	.L46
.L45:
	movq	%rax, %rdx
	andl	$1, %eax
	shrq	%rdx
	orq	%rax, %rdx
	cvtsi2sdq	%rdx, %xmm0
	addsd	%xmm0, %xmm0
.L46:
	mulsd	%xmm0, %xmm0
	mulsd	%xmm1, %xmm0
	call	ceil@PLT
	movl	52(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttsd2siq	%xmm0, %rax
	movq	44(%rsp), %rdx
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdi
	movq	%rbp, %rdx
.L56:
	call	_Z38__device_stub__Z15calculateKernelPfS_yPfS_y
.L44:
	incq	%r13
	jmp	.L39
.L58:
	testq	%rax, %rax
	je	.L49
	movq	24(%rsp), %rsi
	jmp	.L50
.L49:
	movq	16(%rsp), %rsi
.L50:
	movq	(%rsp), %rdx
	movl	$2, %ecx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	testb	%r14b, %r14b
	je	.L51
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	call	_Z8printSumPfy
.L51:
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE2035:
	.size	_Z8calcDistyib, .-_Z8calcDistyib
	.globl	_Z45__device_stub__Z21calculateKernelUpdatePfS_yyPfS_yy
	.type	_Z45__device_stub__Z21calculateKernelUpdatePfS_yyPfS_yy, @function
_Z45__device_stub__Z21calculateKernelUpdatePfS_yyPfS_yy:
.LFB2064:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21calculateKernelUpdatePfS_yy(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L59:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2064:
	.size	_Z45__device_stub__Z21calculateKernelUpdatePfS_yyPfS_yy, .-_Z45__device_stub__Z21calculateKernelUpdatePfS_yyPfS_yy
	.globl	_Z21calculateKernelUpdatePfS_yy
	.type	_Z21calculateKernelUpdatePfS_yy, @function
_Z21calculateKernelUpdatePfS_yy:
.LFB2065:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z21calculateKernelUpdatePfS_yyPfS_yy
	.cfi_endproc
.LFE2065:
	.size	_Z21calculateKernelUpdatePfS_yy, .-_Z21calculateKernelUpdatePfS_yy
	.globl	_Z17calcDistOptimizedyyb
	.type	_Z17calcDistOptimizedyyb, @function
_Z17calcDistOptimizedyyb:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	%rsi, %rbp
	movq	%rdi, %rbx
	decq	%rbp
	leaq	1(%rbx), %r15
	imulq	%rsi, %rbp
	movl	$4, %esi
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movl	%edx, 12(%rsp)
	addq	%rbp, %rdi
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movq	%rdi, %rax
	salq	$2, %rdi
	salq	$4, %rax
	movq	%rax, (%rsp)
	call	calloc@PLT
	movq	%r15, %r11
	movss	.LC6(%rip), %xmm2
	xorl	%r10d, %r10d
	imulq	%rbx, %r11
	movq	%rax, %r12
.L65:
	cmpq	%r15, %r14
	jnb	.L86
	leaq	-10(%r14), %rax
	movaps	%xmm2, %xmm3
	cmpq	$20, %rax
	ja	.L66
	movss	.LC5(%rip), %xmm3
.L66:
	movq	%r14, %rdx
	movq	%r13, %rsi
	movq	%rbx, %rdi
	call	_Z9transHostyyy
	movq	%r10, %rdx
	movq	%r13, %rsi
	movq	%rbx, %rdi
	movss	%xmm3, (%r12,%rax,4)
	call	_Z9transHostyyy
	leaq	(%r11,%r14), %rdx
	movq	%r13, %rsi
	movq	%rbx, %rdi
	movss	%xmm2, (%r12,%rax,4)
	incq	%r14
	call	_Z9transHostyyy
	leaq	(%r10,%rbx), %rdx
	movq	%r13, %rsi
	movq	%rbx, %rdi
	movss	%xmm2, (%r12,%rax,4)
	addq	%r15, %r10
	call	_Z9transHostyyy
	movss	%xmm2, (%r12,%rax,4)
	jmp	.L65
.L86:
	movq	(%rsp), %rsi
	leaq	24(%rsp), %rdi
	salq	$2, %rbp
	xorl	%r14d, %r14d
	movabsq	$4294968320, %r15
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdx
	movq	16(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	24(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
.L68:
	movq	%r14, %rax
	andl	$1, %eax
	cmpq	%r13, %r14
	je	.L87
	testq	%rax, %rax
	movq	%r15, 44(%rsp)
	movsd	.LC7(%rip), %xmm1
	movl	$1, 52(%rsp)
	jne	.L69
	testq	%rbp, %rbp
	js	.L70
	cvtsi2sdq	%rbp, %xmm0
	jmp	.L71
.L70:
	movq	%rbp, %rax
	shrq	%rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L71:
	mulsd	%xmm1, %xmm0
	call	ceil@PLT
	movl	52(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttsd2siq	%xmm0, %rax
	movq	44(%rsp), %rdx
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L73
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movq	%r13, %rcx
	movq	%rbx, %rdx
	jmp	.L85
.L69:
	testq	%rbp, %rbp
	js	.L74
	cvtsi2sdq	%rbp, %xmm0
	jmp	.L75
.L74:
	movq	%rbp, %rax
	shrq	%rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L75:
	mulsd	%xmm1, %xmm0
	call	ceil@PLT
	movl	52(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttsd2siq	%xmm0, %rax
	movq	44(%rsp), %rdx
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L73
	movq	16(%rsp), %rsi
	movq	24(%rsp), %rdi
	movq	%r13, %rcx
	movq	%rbx, %rdx
.L85:
	call	_Z45__device_stub__Z21calculateKernelUpdatePfS_yyPfS_yy
.L73:
	incq	%r14
	jmp	.L68
.L87:
	testq	%rax, %rax
	je	.L78
	movq	24(%rsp), %rsi
	jmp	.L79
.L78:
	movq	16(%rsp), %rsi
.L79:
	movq	(%rsp), %rdx
	movl	$2, %ecx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	cmpb	$0, 12(%rsp)
	je	.L80
	movq	%rbx, %rsi
	movq	%r12, %rdi
	call	_Z8printSumPfy
.L80:
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L81
	call	__stack_chk_fail@PLT
.L81:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	movq	%r12, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE2036:
	.size	_Z17calcDistOptimizedyyb, .-_Z17calcDistOptimizedyyb
	.section	.rodata.str1.1
.LC8:
	.string	"Get device count error!"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	%edi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	decl	%edi
	jle	.L95
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	call	atoi@PLT
	movslq	%eax, %rbp
	cmpl	$2, %r12d
	je	.L96
	movq	16(%rbx), %rdi
	call	atoi@PLT
	movslq	%eax, %rsi
	jmp	.L89
.L95:
	movl	$10000, %ebp
	movl	$500, %esi
.L89:
	cmpl	$3, %r12d
	setg	%r12b
	jmp	.L90
.L96:
	movl	$500, %esi
	xorl	%r12d, %r12d
.L90:
	leaq	20(%rsp), %rdi
	movq	%rsi, 8(%rsp)
	call	cudaGetDeviceCount@PLT
	movq	8(%rsp), %rsi
	testl	%eax, %eax
	je	.L91
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L91:
	leaq	1(%rsi), %rax
	leaq	1(%rbp), %rcx
	movzbl	%r12b, %edx
	movq	%rbp, %rdi
	addq	%rax, %rax
	cmpq	%rcx, %rax
	jnb	.L92
	call	_Z17calcDistOptimizedyyb
	jmp	.L93
.L92:
	call	_Z8calcDistyib
.L93:
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L94
	call	__stack_chk_fail@PLT
.L94:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z21calculateKernelUpdatePfS_yy"
.LC10:
	.string	"_Z15calculateKernelPfS_y"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z21calculateKernelUpdatePfS_yy(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15calculateKernelPfS_y(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2067:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1138753536
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC5:
	.long	1125515264
	.align 4
.LC6:
	.long	1117782016
	.section	.rodata.cst8
	.align 8
.LC7:
	.long	0
	.long	1062207488
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>

typedef unsigned long long ll;

void printSum(float * H, ll ss) {

	float all = 0;
	for (ll i = 0; i < ss; i++) {
		all += H[i];
		
	}
	printf("avg = %.3f\n", all/ss);
}
__device__ bool zeroArea (ll i, ll n, ll iter)
{
    ll row = i/(1+n);
    ll col = i%(1+n);
    return iter < row && row < n-iter && iter < col && col < n - iter;
}

__device__ ll mediumTrans(ll n, ll iter, ll i)
{
    ll temp = (n+2)*(n-iter-1)+1;
     if (i>= temp){ 
	return i-(n-2*iter-1)*(n-2*iter-1);
	}
    else if ( i<temp&&(n+1)*(iter+1)+iter<i) {
        return i-((i-(iter+1)*(n+2))/(n+1)+1)*(n-2*iter-1);
    }
    
    return i;
}

__device__ ll revertMediumTrans (ll n, ll iter, ll newIdx)
{
    ll temp = 3*iter*n+3*n-4*iter*iter-6*iter-2;
    if (newIdx >= temp){
        return newIdx + (n-2*iter-1)*(n-2*iter-1);
    }
    else if ( newIdx<temp &&(n+1)*(iter+1)+iter<newIdx) {
        return newIdx + ((newIdx-(n+2)*(iter+1))*(n-2*iter-1)/(2*(iter+1))+1);
    }
   
    return newIdx;
}

__device__ ll matrixTrans (ll n, ll idx)
{
    return n+2+idx+2*(idx/(n-1));
}


__device__ ll revertMatrixTrans (ll n, ll iter, ll midiumIdx)
{
    ll idx = midiumIdx;
    ll temp = 3*iter*n-4*iter*iter-4*iter;
	
	if(midiumIdx >= temp){
        idx = midiumIdx+(n-2*iter-1)*(n-2*iter-1);
        return matrixTrans(n, idx);
    }
	else if(midiumIdx< temp && iter*n-1<midiumIdx) {
        idx=((midiumIdx-iter*n)/(2*iter)+1)*(n-2*iter-1)+midiumIdx;
        return matrixTrans(n, idx);
    }
    
    return matrixTrans(n, idx);
}

ll transHost(ll n, ll iter, ll i)
{
    ll temp = (n+2)*(n-iter-1) + 1;
    if (i>= temp){ 
	return i-pow((n-2*iter-1),2);
	}
    else if ( i<temp && ((n+1)*(iter + 1)+iter) < i){ 
	    return i-(n-2*iter-1)*((i-(n+2)*(iter+1))/(n+1)+1);
	}
    return i;
}

void printDeviceInfo(ll index) {
	hipDeviceProp_t prop;
	if (hipGetDeviceProperties(&prop, index) != hipSuccess) {
		printf("Get device properties error!");
		exit(EXIT_FAILURE);
	}
	printf("\n#Device %d#\n\nName: %s\nWarp size: %d\nMax threads per block: %d\nMax thread dimension: x => %d, y => %d, z=> %d\n Max grid dimension: x => %d, y = %d, z => %d\n",index, prop.name, prop.warpSize, prop.maxThreadsPerBlock, prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2], prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);

}

__global__ void calculateKernel(float * A, float * B, ll qq) {

        int gridnum = blockIdx.x * blockDim.x + threadIdx.x;
        int indexindex =qq+gridnum%(qq-2)+qq*(gridnum/(qq-2))+1;

        if ( gridnum<(qq-2)*(qq-2))  {
                B[indexindex] = (A[indexindex-qq]+A[indexindex+qq]+ A[indexindex+1]+ A[indexindex-1])/4;
        }
}

__global__ void calculateKernelUpdate(float * A, float * B, ll n, ll iter) {

	ll i = blockIdx.x * blockDim.x + threadIdx.x;
	if (blockIdx.x * blockDim.x + threadIdx.x >= 4 * iter * (n-iter-1) ) return;

    float lf;
    float rr;
	float uu;
    float dd;

	i = revertMatrixTrans(n, iter, (blockIdx.x * blockDim.x + threadIdx.x));
        lf = zeroArea(i-1, n, iter) ? 0 : A[mediumTrans(n, iter, i - 1)];
        rr = zeroArea(i+1, n, iter) ? 0 : A[mediumTrans(n, iter, i + 1)];

        uu = zeroArea(i-(n + 1), n, iter) ? 0 : A[mediumTrans(n, iter, i - n - 1)];
        dd = zeroArea(i+(n + 1), n, iter) ? 0 : A[mediumTrans(n, iter, i + n + 1)];
        
	B[mediumTrans(n, iter, i)] = (lf + rr + uu + dd) / 4;
	
}
const int BS = 1024;

void calcDist(ll n, int iter, bool initialState) {

        ll i= (n+1)*(n+1)*sizeof(float);
        ll memsize = (n+1)*(n+1)*sizeof(float);

        float * H = (float*) calloc ((n+1)*(n+1), sizeof(float));

        for (i = 0; i < n+1; i++) {
                H[i] = (i >= 10 && i <= 30) ? 150 : 80;
                H[i*(n+1)] = 80;
                H[n*(n+1)+i] = 80;
                H[i*(n+1) + n] = 80;
        }

        float *Pd, *Qd;


        hipMalloc((void**) &Qd, memsize);
        hipMalloc((void**) &Pd, memsize);
        hipMemcpy(Pd, H, memsize, hipMemcpyHostToDevice);
        hipMemcpy(Qd, H, memsize, hipMemcpyHostToDevice);


        for (i = 0; i < iter; i++) {
                if (i%2 == 0)
                        calculateKernel<<<ceil((double) (n-1)*(n-1)/BS), BS>>>(Pd, Qd, n+1);
                else
                        calculateKernel<<<ceil((double) (n-1)*(n-1)/BS), BS>>>(Qd, Pd, n+1);
        }


        hipMemcpy(H, (i%2==1)?Qd:Pd , memsize, hipMemcpyDeviceToHost);

        if(initialState) printSum(H,(n+1)*(n+1));
        //CLEAN UP
        hipFree(Pd);
        hipFree(Qd);

        free(H);
}

void calcDistOptimized(ll n, ll iter, bool initialState) {

	ll i = (4*n+4*iter*(n-iter-1))*sizeof(float);
    ll memsize = (4*n+4*iter*(n-iter-1))*sizeof(float);
	float * H = (float*) calloc ((4*n+4*iter*(n-iter-1)), sizeof(float));

	for (i = 0; i < n+1; i++) {
		H[transHost(n, iter, i)] = (i >= 10 && i <= 30) ? 150 : 80;
		H[transHost(n, iter, i * (n + 1))] = 80;
		H[transHost(n, iter, (n + 1)*n + i)] = 80;
		H[transHost(n, iter, i * (n + 1) + n)] = 80;
	}

	float *Pd, *Qd;
	
	hipMalloc((void**) &Qd, memsize);
	hipMalloc((void**) &Pd, memsize);
	hipMemcpy(Pd, H, memsize, hipMemcpyHostToDevice);
	hipMemcpy(Qd, H, memsize, hipMemcpyHostToDevice);

	for (i = 0; i < iter; i++) {
		if (i%2 == 0)
			calculateKernelUpdate<<<ceil((double) (4*iter*(n-iter-1))/BS), BS>>>(Pd, Qd, n, iter); 
		else
			calculateKernelUpdate<<<ceil((double) (4*iter*(n-iter-1))/BS), BS>>>(Qd, Pd, n, iter);
	}

	hipMemcpy(H, (i%2==1)?Qd:Pd , memsize, hipMemcpyDeviceToHost);

	if(initialState) printSum(H, n);
		
	hipFree(Pd);
	hipFree(Qd);

	free(H);
	
}
int main(int argc, char * argv[]) {
  
   //clock_t start = clock();
	ll n = 10000;
	ll iter = 500;

	bool initialState = false;
	if (argc > 1) n = atoi(argv[1]);
	if (argc > 2) iter = atoi(argv[2]);
	if (argc > 3) initialState = true;

	//dim3 dimGrid(
	int count, i;
	if (hipGetDeviceCount(&count) != hipSuccess) {
		printf("Get device count error!");
		exit(EXIT_FAILURE);
	}

	for (i = 0; i < count; i++) {
	}
	if ( n+1 > 2*(iter+1)) calcDistOptimized(n, iter, initialState);
	else calcDist(n, iter, initialState); 
	//clock_t end = (clock() - start)/1000;
  //printf("time: %ldms\n", end);
		
}


	.text
	.file	"cuda-optimized.hip"
	.globl	_Z8printSumPfy                  # -- Begin function _Z8printSumPfy
	.type	_Z8printSumPfy,@function
_Z8printSumPfy:                         # @_Z8printSumPfy
	.cfi_startproc
# %bb.0:
	xorps	%xmm0, %xmm0
	testq	%rsi, %rsi
	je	.LBB0_1
# %bb.5:                                # %.lr.ph.preheader
	xorl	%eax, %eax
.LBB0_6:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	addss	(%rdi,%rax,4), %xmm0
	incq	%rax
	cmpq	%rax, %rsi
	jne	.LBB0_6
.LBB0_1:                                # %._crit_edge
	testq	%rsi, %rsi
	js	.LBB0_2
# %bb.3:                                # %._crit_edge
	cvtsi2ss	%rsi, %xmm1
	jmp	.LBB0_4
.LBB0_2:
	movq	%rsi, %rax
	shrq	%rax
	andl	$1, %esi
	orq	%rax, %rsi
	cvtsi2ss	%rsi, %xmm1
	addss	%xmm1, %xmm1
.LBB0_4:                                # %._crit_edge
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	jmp	printf                          # TAILCALL
.Lfunc_end0:
	.size	_Z8printSumPfy, .Lfunc_end0-_Z8printSumPfy
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z9transHostyyy
.LCPI1_0:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI1_1:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_2:
	.quad	0x43e0000000000000              # double 9.2233720368547758E+18
	.text
	.globl	_Z9transHostyyy
	.type	_Z9transHostyyy,@function
_Z9transHostyyy:                        # @_Z9transHostyyy
	.cfi_startproc
# %bb.0:
	movq	%rdx, %rcx
	leaq	2(%rdi), %rax
	movq	%rsi, %rdx
	notq	%rdx
	addq	%rdi, %rdx
	imulq	%rax, %rdx
	incq	%rdx
	cmpq	%rcx, %rdx
	jbe	.LBB1_1
# %bb.2:
	leaq	1(%rdi), %r8
	leaq	1(%rsi), %rdx
	movq	%rdx, %r9
	imulq	%r8, %r9
	addq	%rsi, %r9
	cmpq	%rcx, %r9
	jae	.LBB1_4
# %bb.3:
	addq	%rsi, %rsi
	notq	%rsi
	addq	%rdi, %rsi
	imulq	%rax, %rdx
	movq	%rcx, %rax
	subq	%rdx, %rax
	xorl	%edx, %edx
	divq	%r8
	notq	%rax
	imulq	%rsi, %rax
	addq	%rax, %rcx
	jmp	.LBB1_4
.LBB1_1:
	movq	%rcx, %xmm0
	movdqa	.LCPI1_0(%rip), %xmm1           # xmm1 = [1127219200,1160773632,0,0]
	punpckldq	%xmm1, %xmm0            # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
	movapd	.LCPI1_1(%rip), %xmm2           # xmm2 = [4.503599627370496E+15,1.9342813113834067E+25]
	subpd	%xmm2, %xmm0
	movapd	%xmm0, %xmm3
	unpckhpd	%xmm0, %xmm3                    # xmm3 = xmm3[1],xmm0[1]
	addsd	%xmm0, %xmm3
	addq	%rsi, %rsi
	notq	%rsi
	addq	%rdi, %rsi
	movq	%rsi, %xmm0
	punpckldq	%xmm1, %xmm0            # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
	subpd	%xmm2, %xmm0
	movapd	%xmm0, %xmm1
	unpckhpd	%xmm0, %xmm1                    # xmm1 = xmm1[1],xmm0[1]
	addsd	%xmm0, %xmm1
	mulsd	%xmm1, %xmm1
	subsd	%xmm1, %xmm3
	cvttsd2si	%xmm3, %rax
	movq	%rax, %rdx
	sarq	$63, %rdx
	subsd	.LCPI1_2(%rip), %xmm3
	cvttsd2si	%xmm3, %rcx
	andq	%rdx, %rcx
	orq	%rax, %rcx
.LBB1_4:
	movq	%rcx, %rax
	retq
.Lfunc_end1:
	.size	_Z9transHostyyy, .Lfunc_end1-_Z9transHostyyy
	.cfi_endproc
                                        # -- End function
	.globl	_Z15printDeviceInfoy            # -- Begin function _Z15printDeviceInfoy
	.type	_Z15printDeviceInfoy,@function
_Z15printDeviceInfoy:                   # @_Z15printDeviceInfoy
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$1480, %rsp                     # imm = 0x5C8
	.cfi_def_cfa_offset 1520
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	leaq	8(%rsp), %rdi
	movl	%ebx, %esi
	callq	hipGetDevicePropertiesR0600
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	leaq	8(%rsp), %rdx
	movl	308(%rdx), %ecx
	movl	320(%rdx), %r8d
	movl	324(%rdx), %r9d
	movl	328(%rdx), %r10d
	movl	332(%rdx), %r11d
	movl	336(%rdx), %r14d
	movl	340(%rdx), %r15d
	movl	344(%rdx), %r12d
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$.L.str.2, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%r11
	.cfi_adjust_cfa_offset 8
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	callq	printf
	addq	$1528, %rsp                     # imm = 0x5F8
	.cfi_adjust_cfa_offset -1528
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 1520
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z15printDeviceInfoy, .Lfunc_end2-_Z15printDeviceInfoy
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__calculateKernelPfS_y # -- Begin function _Z30__device_stub__calculateKernelPfS_y
	.type	_Z30__device_stub__calculateKernelPfS_y,@function
_Z30__device_stub__calculateKernelPfS_y: # @_Z30__device_stub__calculateKernelPfS_y
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15calculateKernelPfS_y, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z30__device_stub__calculateKernelPfS_y, .Lfunc_end3-_Z30__device_stub__calculateKernelPfS_y
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__calculateKernelUpdatePfS_yy # -- Begin function _Z36__device_stub__calculateKernelUpdatePfS_yy
	.type	_Z36__device_stub__calculateKernelUpdatePfS_yy,@function
_Z36__device_stub__calculateKernelUpdatePfS_yy: # @_Z36__device_stub__calculateKernelUpdatePfS_yy
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21calculateKernelUpdatePfS_yy, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z36__device_stub__calculateKernelUpdatePfS_yy, .Lfunc_end4-_Z36__device_stub__calculateKernelUpdatePfS_yy
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z8calcDistyib
.LCPI5_0:
	.long	0x42a00000                      # float 80
	.long	0x43160000                      # float 150
.LCPI5_3:
	.quad	0x3f50000000000000              # double 9.765625E-4
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI5_1:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI5_2:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.text
	.globl	_Z8calcDistyib
	.type	_Z8calcDistyib,@function
_Z8calcDistyib:                         # @_Z8calcDistyib
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, 16(%rsp)                  # 4-byte Spill
	movl	%esi, 20(%rsp)                  # 4-byte Spill
	movq	%rdi, %rbp
	leaq	1(%rdi), %r14
	imulq	%r14, %r14
	leaq	(,%r14,4), %r13
	movl	$4, %esi
	movq	%r14, %rdi
	callq	calloc
	movq	%rax, %rbx
	movq	%rbp, %r12
	incq	%r12
	je	.LBB5_3
# %bb.1:                                # %.lr.ph
	movq	%rbp, %rax
	negq	%rax
	leaq	(,%rbp,4), %rcx
	leaq	4(,%rbp,4), %rdx
	movq	%rbp, %rsi
	imulq	%r12, %rsi
	leaq	(%rbx,%rsi,4), %rsi
	movq	$-10, %rdi
	movl	$1117782016, %r8d               # imm = 0x42A00000
	movq	%rbx, %r9
.LBB5_2:                                # =>This Inner Loop Header: Depth=1
	xorl	%r10d, %r10d
	cmpq	$21, %rdi
	setb	%r10b
	movss	.LCPI5_0(,%r10,4), %xmm0        # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 40(%rbx,%rdi,4)
	movl	%r8d, (%r9)
	movl	%r8d, 40(%rsi,%rdi,4)
	movl	%r8d, (%r9,%rcx)
	leaq	(%rax,%rdi), %r10
	incq	%r10
	incq	%rdi
	addq	%rdx, %r9
	cmpq	$-9, %r10
	jne	.LBB5_2
.LBB5_3:                                # %._crit_edge
	movq	%rsp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %r15
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rax
	movq	(%rax), %rdi
	movq	%rbx, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	20(%rsp), %eax                  # 4-byte Reload
	testl	%eax, %eax
	je	.LBB5_4
# %bb.5:                                # %.lr.ph69
	movq	%r13, 24(%rsp)                  # 8-byte Spill
	movq	%r14, 32(%rsp)                  # 8-byte Spill
	movslq	%eax, %r15
	movabsq	$4294967296, %r14               # imm = 0x100000000
	decq	%rbp
	movq	%rbp, %xmm1
	punpckldq	.LCPI5_1(%rip), %xmm1   # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	subpd	.LCPI5_2(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	%xmm0, %xmm0
	mulsd	.LCPI5_3(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %rax
	movl	%eax, %ebp
	btsq	$32, %rbp
	xorl	%r13d, %r13d
	addq	$1024, %r14                     # imm = 0x400
.LBB5_6:                                # =>This Inner Loop Header: Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testb	$1, %r13b
	jne	.LBB5_9
# %bb.7:                                #   in Loop: Header=BB5_6 Depth=1
	testl	%eax, %eax
	jne	.LBB5_12
# %bb.8:                                #   in Loop: Header=BB5_6 Depth=1
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	jmp	.LBB5_11
.LBB5_9:                                #   in Loop: Header=BB5_6 Depth=1
	testl	%eax, %eax
	jne	.LBB5_12
# %bb.10:                               #   in Loop: Header=BB5_6 Depth=1
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
.LBB5_11:                               #   in Loop: Header=BB5_6 Depth=1
	movq	%r12, %rdx
	callq	_Z30__device_stub__calculateKernelPfS_y
.LBB5_12:                               #   in Loop: Header=BB5_6 Depth=1
	incq	%r13
	cmpq	%r13, %r15
	jne	.LBB5_6
# %bb.13:                               # %._crit_edge70
	testb	$1, %r15b
	movq	%rsp, %rax
	leaq	8(%rsp), %rcx
	cmoveq	%rcx, %rax
	movq	(%rax), %rsi
	movq	32(%rsp), %r14                  # 8-byte Reload
	movl	16(%rsp), %ebp                  # 4-byte Reload
	movq	24(%rsp), %r13                  # 8-byte Reload
	jmp	.LBB5_14
.LBB5_4:                                # %._crit_edge70.thread
	movq	8(%rsp), %rsi
	movl	16(%rsp), %ebp                  # 4-byte Reload
.LBB5_14:
	movq	%rbx, %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testb	%bpl, %bpl
	je	.LBB5_16
# %bb.15:
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_Z8printSumPfy
.LBB5_16:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z8calcDistyib, .Lfunc_end5-_Z8calcDistyib
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z17calcDistOptimizedyyb
.LCPI6_0:
	.long	0x42a00000                      # float 80
	.long	0x43160000                      # float 150
.LCPI6_3:
	.quad	0x3f50000000000000              # double 9.765625E-4
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI6_1:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI6_2:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.text
	.globl	_Z17calcDistOptimizedyyb
	.type	_Z17calcDistOptimizedyyb,@function
_Z17calcDistOptimizedyyb:               # @_Z17calcDistOptimizedyyb
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, 16(%rsp)                  # 4-byte Spill
	movq	%rsi, %r12
	movq	%rdi, %rbp
	leaq	(,%rdi,4), %rax
	movq	%rsi, %rcx
	notq	%rcx
	addq	%rdi, %rcx
	imulq	%rsi, %rcx
	movq	%rcx, 40(%rsp)                  # 8-byte Spill
	leaq	(%rax,%rcx,4), %rdi
	leaq	(,%rdi,4), %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movl	$4, %esi
	callq	calloc
	movq	%rax, %r14
	movq	%rbp, %rax
	incq	%rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	je	.LBB6_3
# %bb.1:                                # %.lr.ph
	movq	32(%rsp), %rax                  # 8-byte Reload
	imulq	%rbp, %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	xorl	%r15d, %r15d
	xorl	%r13d, %r13d
	movl	$1117782016, %ebx               # imm = 0x42A00000
.LBB6_2:                                # =>This Inner Loop Header: Depth=1
	leaq	-10(%r13), %rax
	xorl	%ecx, %ecx
	cmpq	$21, %rax
	setb	%cl
	movss	.LCPI6_0(,%rcx,4), %xmm0        # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 20(%rsp)                 # 4-byte Spill
	movq	%rbp, %rdi
	movq	%r12, %rsi
	movq	%r13, %rdx
	callq	_Z9transHostyyy
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r14,%rax,4)
	movq	%rbp, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	callq	_Z9transHostyyy
	movl	%ebx, (%r14,%rax,4)
	movq	48(%rsp), %rax                  # 8-byte Reload
	leaq	(%rax,%r13), %rdx
	movq	%rbp, %rdi
	movq	%r12, %rsi
	callq	_Z9transHostyyy
	movl	%ebx, (%r14,%rax,4)
	leaq	(%r15,%rbp), %rdx
	movq	%rbp, %rdi
	movq	%r12, %rsi
	callq	_Z9transHostyyy
	movl	%ebx, (%r14,%rax,4)
	incq	%r13
	movq	32(%rsp), %rax                  # 8-byte Reload
	addq	%rax, %r15
	cmpq	%r13, %rax
	jne	.LBB6_2
.LBB6_3:                                # %._crit_edge
	leaq	8(%rsp), %r15
	movq	%r15, %rdi
	movq	24(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%rsp, %r13
	movq	%r13, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testq	%r12, %r12
	je	.LBB6_4
# %bb.5:                                # %.lr.ph86
	movq	40(%rsp), %rax                  # 8-byte Reload
	shlq	$2, %rax
	movq	%rax, %xmm1
	punpckldq	.LCPI6_1(%rip), %xmm1   # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	movabsq	$4294967296, %rbx               # imm = 0x100000000
	subpd	.LCPI6_2(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	.LCPI6_3(%rip), %xmm0
	callq	ceil@PLT
	cvttsd2si	%xmm0, %rax
	movl	%eax, %r15d
	btsq	$32, %r15
	xorl	%r13d, %r13d
	addq	$1024, %rbx                     # imm = 0x400
.LBB6_6:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testb	$1, %r13b
	jne	.LBB6_9
# %bb.7:                                #   in Loop: Header=BB6_6 Depth=1
	testl	%eax, %eax
	jne	.LBB6_12
# %bb.8:                                #   in Loop: Header=BB6_6 Depth=1
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	jmp	.LBB6_11
.LBB6_9:                                #   in Loop: Header=BB6_6 Depth=1
	testl	%eax, %eax
	jne	.LBB6_12
# %bb.10:                               #   in Loop: Header=BB6_6 Depth=1
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
.LBB6_11:                               #   in Loop: Header=BB6_6 Depth=1
	movq	%rbp, %rdx
	movq	%r12, %rcx
	callq	_Z36__device_stub__calculateKernelUpdatePfS_yy
.LBB6_12:                               #   in Loop: Header=BB6_6 Depth=1
	incq	%r13
	cmpq	%r13, %r12
	jne	.LBB6_6
# %bb.13:                               # %._crit_edge87
	testb	$1, %r12b
	leaq	8(%rsp), %rax
	movq	%rsp, %rcx
	cmoveq	%rcx, %rax
	movq	(%rax), %rsi
	jmp	.LBB6_14
.LBB6_4:                                # %._crit_edge87.thread
	movq	(%rsp), %rsi
.LBB6_14:
	movq	%r14, %rdi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	cmpb	$0, 16(%rsp)                    # 1-byte Folded Reload
	je	.LBB6_16
# %bb.15:
	movq	%r14, %rdi
	movq	%rbp, %rsi
	callq	_Z8printSumPfy
.LBB6_16:
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	free
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z17calcDistOptimizedyyb, .Lfunc_end6-_Z17calcDistOptimizedyyb
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebp
	movl	$500, %ebx                      # imm = 0x1F4
	movl	$10000, %r14d                   # imm = 0x2710
	cmpl	$2, %edi
	jl	.LBB7_3
# %bb.1:
	movq	%rsi, %r15
	movq	8(%rsi), %rdi
	callq	atoi
	movslq	%eax, %r14
	cmpl	$2, %ebp
	je	.LBB7_3
# %bb.2:
	movq	16(%r15), %rdi
	callq	atoi
	movslq	%eax, %rbx
.LBB7_3:                                # %.thread
	leaq	4(%rsp), %rdi
	callq	hipGetDeviceCount
	testl	%eax, %eax
	jne	.LBB7_8
# %bb.4:                                # %.preheader
	leaq	1(%r14), %rax
	leaq	2(,%rbx,2), %rcx
	xorl	%edx, %edx
	cmpq	%rcx, %rax
	jbe	.LBB7_6
# %bb.5:
	cmpl	$4, %ebp
	setge	%dl
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_Z17calcDistOptimizedyyb
	jmp	.LBB7_7
.LBB7_6:
	cmpl	$4, %ebp
	setge	%dl
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_Z8calcDistyib
.LBB7_7:
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB7_8:
	.cfi_def_cfa_offset 48
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end7:
	.size	main, .Lfunc_end7-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15calculateKernelPfS_y, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21calculateKernelUpdatePfS_yy, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"avg = %.3f\n"
	.size	.L.str, 12

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Get device properties error!"
	.size	.L.str.1, 29

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\n#Device %d#\n\nName: %s\nWarp size: %d\nMax threads per block: %d\nMax thread dimension: x => %d, y => %d, z=> %d\n Max grid dimension: x => %d, y = %d, z => %d\n"
	.size	.L.str.2, 157

	.type	_Z15calculateKernelPfS_y,@object # @_Z15calculateKernelPfS_y
	.section	.rodata,"a",@progbits
	.globl	_Z15calculateKernelPfS_y
	.p2align	3, 0x0
_Z15calculateKernelPfS_y:
	.quad	_Z30__device_stub__calculateKernelPfS_y
	.size	_Z15calculateKernelPfS_y, 8

	.type	_Z21calculateKernelUpdatePfS_yy,@object # @_Z21calculateKernelUpdatePfS_yy
	.globl	_Z21calculateKernelUpdatePfS_yy
	.p2align	3, 0x0
_Z21calculateKernelUpdatePfS_yy:
	.quad	_Z36__device_stub__calculateKernelUpdatePfS_yy
	.size	_Z21calculateKernelUpdatePfS_yy, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"Get device count error!"
	.size	.L.str.3, 24

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15calculateKernelPfS_y"
	.size	.L__unnamed_1, 25

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z21calculateKernelUpdatePfS_yy"
	.size	.L__unnamed_2, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__calculateKernelPfS_y
	.addrsig_sym _Z36__device_stub__calculateKernelUpdatePfS_yy
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15calculateKernelPfS_y
	.addrsig_sym _Z21calculateKernelUpdatePfS_yy
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15calculateKernelPfS_y ; -- Begin function _Z15calculateKernelPfS_y
	.globl	_Z15calculateKernelPfS_y
	.p2align	8
	.type	_Z15calculateKernelPfS_y,@function
_Z15calculateKernelPfS_y:               ; @_Z15calculateKernelPfS_y
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[8:9], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_add_u32 s3, s8, -2
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_addc_u32 s4, s9, -1
	s_mul_hi_u32 s2, s3, s3
	s_mul_i32 s5, s3, s4
	s_mul_i32 s6, s3, s3
	s_add_i32 s2, s2, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s7, s2, s5
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[6:7], v[1:2]
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_cvt_f32_u32_e32 v0, s3
	v_cvt_f32_u32_e32 v3, s4
	s_sub_u32 s2, 0, s3
	s_subb_u32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v3, 0x4f800000, v0
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x2f800000, v0
	v_trunc_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v3, 0xcf800000, v0
	v_cvt_u32_f32_e32 v3, v3
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s2, v3
	v_mul_hi_u32 v5, s2, v0
	v_mul_lo_u32 v6, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_mul_lo_u32 v5, s2, v0
	v_add_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v0, v5
	v_mul_lo_u32 v7, v0, v4
	v_mul_hi_u32 v8, v0, v4
	v_mul_hi_u32 v9, v3, v5
	v_mul_lo_u32 v5, v3, v5
	v_mul_hi_u32 v10, v3, v4
	v_mul_lo_u32 v4, v3, v4
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v4, s2, v0
	v_mul_lo_u32 v6, s5, v0
	v_mul_lo_u32 v5, s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v5
	v_mul_lo_u32 v5, s2, v0
	v_add_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v0, v5
	v_mul_lo_u32 v7, v0, v4
	v_mul_hi_u32 v8, v0, v4
	v_mul_hi_u32 v9, v3, v5
	v_mul_lo_u32 v5, v3, v5
	v_mul_hi_u32 v10, v3, v4
	v_mul_lo_u32 v4, v3, v4
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v10, v1, v0
	v_mad_u64_u32 v[5:6], null, v2, v0, 0
	v_mad_u64_u32 v[3:4], null, v1, v9, 0
	v_mad_u64_u32 v[7:8], null, v2, v9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v10, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v5
	v_add_co_ci_u32_e32 v0, vcc_lo, v3, v6, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, s4, v0
	v_mad_u64_u32 v[3:4], null, s3, v0, 0
	v_mul_lo_u32 v5, s3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v3, vcc_lo, v1, v3
	v_add3_u32 v4, v4, v5, v6
	v_add_nc_u32_e32 v6, 2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v2, v4
	v_subrev_co_ci_u32_e64 v5, s2, s4, v5, vcc_lo
	v_sub_co_u32 v7, s2, v3, s3
	v_sub_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v5, s2, 0, v5, s2
	v_cmp_le_u32_e32 vcc_lo, s3, v7
	v_cndmask_b32_e64 v4, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s4, v5
	v_cndmask_b32_e64 v7, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v2
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s4, v5
	v_cndmask_b32_e32 v4, v7, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s4, v2
	v_add_nc_u32_e32 v5, 1, v0
	s_load_b128 s[4:7], s[0:1], 0x0
	v_cndmask_b32_e32 v2, v8, v3, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v5, v6, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_mul_lo_u32 v2, v0, s3
	v_mul_lo_u32 v0, v0, s8
	s_lshl_b64 s[2:3], s[8:9], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v1, v2
	v_add_co_u32 v2, vcc_lo, 0, 0
	v_add3_u32 v0, v1, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, s0, 1, v0, vcc_lo
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v7, 31, v3
	v_sub_co_u32 v6, s0, v3, s8
	v_ashrrev_i64 v[4:5], 30, v[2:3]
	v_add_co_ci_u32_e32 v3, vcc_lo, 2, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v7, vcc_lo, s9, v7, s0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s2, s4
	s_addc_u32 s1, s3, s5
	v_add_co_u32 v8, vcc_lo, s0, v4
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_ashrrev_i64 v[2:3], 30, v[2:3]
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v5, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[8:9], off
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v1, v6, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x3e800000, v0
	v_add_co_u32 v0, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15calculateKernelPfS_y
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15calculateKernelPfS_y, .Lfunc_end0-_Z15calculateKernelPfS_y
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1100
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z21calculateKernelUpdatePfS_yy ; -- Begin function _Z21calculateKernelUpdatePfS_yy
	.globl	_Z21calculateKernelUpdatePfS_yy
	.p2align	8
	.type	_Z21calculateKernelUpdatePfS_yy,@function
_Z21calculateKernelUpdatePfS_yy:        ; @_Z21calculateKernelUpdatePfS_yy
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s2, 0xffff
	v_alignbit_b32 v1, s11, s10, 30
	s_not_b64 s[2:3], s[10:11]
	s_lshl_b64 s[0:1], s[10:11], 2
	s_add_u32 s16, s2, s8
	s_addc_u32 s17, s3, s9
	v_mul_lo_u32 v1, v1, s16
	s_mul_hi_u32 s2, s0, s16
	s_mul_i32 s3, s0, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_i32 s2, s2, s3
	s_mul_i32 s3, s0, s16
	v_mad_u64_u32 v[2:3], null, s15, s12, v[0:1]
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s3
	v_add_nc_u32_e32 v1, s2, v1
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 v[0:1], v[2:3]
	s_cbranch_execz .LBB1_48
; %bb.1:
	s_mul_i32 s2, s10, s9
	s_mul_hi_u32 s3, s10, s8
	s_mul_i32 s14, s10, s8
	s_add_i32 s13, s3, s2
	s_mul_i32 s2, s11, s8
                                        ; implicit-def: $vgpr0_vgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s13, s13, s2
	s_mul_hi_u32 s2, s14, 3
	s_mul_i32 s3, s13, 3
	s_add_i32 s2, s2, s3
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_mul_i32 s12, s0, s11
	s_mul_hi_u32 s15, s0, s10
	s_mul_i32 s1, s1, s10
	s_add_i32 s12, s15, s12
	s_mul_i32 s3, s14, 3
	s_mul_i32 s0, s0, s10
	s_add_i32 s12, s12, s1
	s_sub_u32 s0, s3, s0
	s_subb_u32 s1, s2, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u64_e32 vcc_lo, s[0:1], v[2:3]
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_lshl_b64 s[2:3], s[10:11], 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_not_b64 s[2:3], s[2:3]
	s_add_u32 s0, s2, s8
	s_addc_u32 s2, s3, s9
	s_add_u32 s3, s8, 2
	s_addc_u32 s12, s9, 0
	s_add_u32 s15, s8, -1
	s_addc_u32 s18, s9, -1
	v_cvt_f32_u32_e32 v0, s15
	v_cvt_f32_u32_e32 v1, s18
	s_sub_u32 s19, 1, s8
	s_subb_u32 s20, 0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v1, 0x4f800000, v0
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x2f800000, v0
	v_trunc_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v1, 0xcf800000, v0
	v_cvt_u32_f32_e32 v1, v1
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s19, v1
	v_mul_hi_u32 v5, s19, v0
	v_mul_lo_u32 v6, s20, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_mul_lo_u32 v5, s19, v0
	v_add_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v0, v5
	v_mul_lo_u32 v7, v0, v4
	v_mul_hi_u32 v8, v0, v4
	v_mul_hi_u32 v9, v1, v5
	v_mul_lo_u32 v5, v1, v5
	v_mul_hi_u32 v10, v1, v4
	v_mul_lo_u32 v4, v1, v4
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v1, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v0, s19, v4
	v_mul_lo_u32 v6, s20, v4
	v_mul_lo_u32 v1, s19, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v0, v1
	v_mul_lo_u32 v1, s19, v4
	v_add_nc_u32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v4, v1
	v_mul_lo_u32 v7, v4, v0
	v_mul_hi_u32 v8, v4, v0
	v_mul_hi_u32 v9, v5, v1
	v_mul_lo_u32 v1, v5, v1
	v_mul_hi_u32 v10, v5, v0
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	v_mul_lo_u32 v8, v5, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v6, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v10, vcc_lo
	v_mad_u64_u32 v[0:1], null, s0, s0, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, v6, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
	s_mul_i32 s0, s0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, v5, v3, vcc_lo
	v_add3_u32 v8, s0, s0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, v0, v6
	v_mad_u64_u32 v[1:2], null, v0, v7, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v8, v6, 0
	v_mad_u64_u32 v[5:6], null, v8, v7, 0
	v_add_co_u32 v1, vcc_lo, v9, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v2, v4, vcc_lo
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, v1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
	v_mul_lo_u32 v5, s18, v3
	v_mad_u64_u32 v[1:2], null, s15, v3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, s15, v4
	v_sub_co_u32 v1, vcc_lo, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v2, v6, v5
	v_sub_nc_u32_e32 v5, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v5, s0, s18, v5, vcc_lo
	v_add_co_u32 v6, s0, v3, 2
	v_add_co_ci_u32_e64 v7, s0, 0, v4, s0
	v_sub_co_u32 v9, s0, v1, s15
	v_sub_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	v_subrev_co_ci_u32_e64 v5, s0, 0, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s15, v9
	v_cmp_eq_u32_e64 s0, s18, v2
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v5
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s15, v1
	v_cndmask_b32_e64 v1, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v2
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v11, v1, s0
	v_cndmask_b32_e32 v5, v10, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v2, v10, v7 :: v_dual_cndmask_b32 v5, v9, v6
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_dual_cndmask_b32 v1, v3, v5 :: v_dual_cndmask_b32 v2, v4, v2
	v_add_co_u32 v0, vcc_lo, s3, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s12, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 1, v[1:2]
	v_add_co_u32 v0, vcc_lo, v0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v2, vcc_lo
                                        ; implicit-def: $vgpr2_vgpr3
.LBB1_3:                                ; %Flow113
	s_and_not1_saveexec_b32 s12, s1
	s_cbranch_execz .LBB1_9
; %bb.4:
	s_add_u32 s0, s14, -1
	s_addc_u32 s1, s13, -1
                                        ; implicit-def: $vgpr0_vgpr1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u64_e32 vcc_lo, s[0:1], v[2:3]
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB1_6
; %bb.5:
	s_add_u32 s2, s8, 2
	s_addc_u32 s3, s9, 0
	s_add_u32 s15, s8, -1
	s_addc_u32 s18, s9, -1
	v_cvt_f32_u32_e32 v0, s15
	v_cvt_f32_u32_e32 v1, s18
	s_sub_u32 s0, 1, s8
	s_subb_u32 s19, 0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v1, 0x4f800000, v0
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, 0x2f800000, v0
	v_trunc_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v1, 0xcf800000, v0
	v_cvt_u32_f32_e32 v1, v1
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, s0, v1
	v_mul_hi_u32 v4, s0, v0
	v_mul_lo_u32 v5, s19, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_mul_lo_u32 v4, s0, v0
	v_add_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, v4
	v_mul_lo_u32 v6, v0, v3
	v_mul_hi_u32 v7, v0, v3
	v_mul_hi_u32 v8, v1, v4
	v_mul_lo_u32 v4, v1, v4
	v_mul_hi_u32 v9, v1, v3
	v_mul_lo_u32 v3, v1, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s0, v0
	v_mul_lo_u32 v5, s19, v0
	v_mul_lo_u32 v4, s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s0, v0
	v_add_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, v4
	v_mul_lo_u32 v6, v0, v3
	v_mul_hi_u32 v7, v0, v3
	v_mul_hi_u32 v8, v1, v4
	v_mul_lo_u32 v4, v1, v4
	v_mul_hi_u32 v9, v1, v3
	v_mul_lo_u32 v3, v1, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, v1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, v2, v0
	v_mad_u64_u32 v[0:1], null, v2, v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, v5, 0
	v_mad_u64_u32 v[3:4], null, s18, v5, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v0, vcc_lo, v2, v0
	v_sub_nc_u32_e32 v1, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v1, s0, s18, v1, vcc_lo
	v_add_co_u32 v4, s0, v5, 2
	v_add_co_ci_u32_e64 v6, null, 0, 0, s0
	v_sub_co_u32 v7, s0, v0, s15
	v_sub_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_subrev_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s15, v7
	v_cndmask_b32_e64 v7, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v1
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s15, v0
	v_cndmask_b32_e64 v0, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v3
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v1
	v_cndmask_b32_e32 v1, v8, v7, vcc_lo
	v_add_co_u32 v7, s0, v5, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v8, null, 0, 0, s0
	v_cmp_eq_u32_e64 s0, s18, v3
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v0, v9, v0, s0
	v_cndmask_b32_e32 v1, v8, v6, vcc_lo
	v_cndmask_b32_e32 v3, v7, v4, vcc_lo
	v_add_co_u32 v2, s0, s2, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, v5, v3
	v_add_co_ci_u32_e64 v3, null, s3, 0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 1, v[0:1]
	v_add_co_u32 v0, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
                                        ; implicit-def: $vgpr2_vgpr3
.LBB1_6:                                ; %Flow111
	s_and_not1_saveexec_b32 s15, s1
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_alignbit_b32 v8, s11, s10, 31
	s_lshl_b64 s[2:3], s[10:11], 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v0, s2
	s_sub_u32 s21, 0, s2
	v_cvt_f32_u32_e32 v1, v8
	s_subb_u32 s22, 0, s3
	s_not_b64 s[0:1], s[2:3]
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_u32 s23, s0, s8
	v_fmac_f32_e32 v0, 0x4f800000, v1
	s_addc_u32 s24, s1, s9
	s_add_u32 s3, s8, 2
	s_addc_u32 s18, s9, 0
	s_add_u32 s20, s8, -1
	v_rcp_f32_e32 v0, v0
	s_addc_u32 s19, s9, -1
	v_cvt_f32_u32_e32 v4, s20
	v_cvt_f32_u32_e32 v7, s19
	s_sub_u32 s1, 1, s8
	v_sub_co_u32 v13, s0, v2, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v14, null, 0, s13, s0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	v_mul_f32_e32 v1, 0x2f800000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v1, v1
	v_fmac_f32_e32 v0, 0xcf800000, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v5, s21, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, s21, v0
	v_mul_lo_u32 v9, s22, v0
	v_add_nc_u32_e32 v5, v6, v5
	v_mul_lo_u32 v6, s21, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v4, 0x4f800000, v7 :: v_dual_add_nc_u32 v5, v5, v9
	v_rcp_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v0, v6
	v_mul_lo_u32 v9, v0, v5
	v_mul_hi_u32 v10, v0, v5
	v_mul_hi_u32 v11, v1, v6
	v_mul_lo_u32 v6, v1, v6
	v_mul_hi_u32 v12, v1, v5
	v_mul_lo_u32 v5, v1, v5
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, 0x5f7ffffc, v4
	v_add_co_u32 v7, vcc_lo, v7, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v6, vcc_lo, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, v9, v11, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v12, vcc_lo
	v_mul_f32_e32 v9, 0x2f800000, v4
	v_add_co_u32 v5, vcc_lo, v6, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	v_trunc_f32_e32 v7, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v0, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v4, 0xcf800000, v7
	v_mul_hi_u32 v5, s21, v0
	v_cvt_u32_f32_e32 v9, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, s21, v1
	v_mul_lo_u32 v12, s21, v0
	v_cvt_u32_f32_e32 v10, v4
	v_mul_lo_u32 v4, s22, v0
	s_subb_u32 s22, 0, s9
	v_mul_hi_u32 v7, s1, v10
	v_add_nc_u32_e32 v5, v5, v6
	v_mul_lo_u32 v6, s1, v9
	v_mul_hi_u32 v19, v1, v12
	v_mul_lo_u32 v11, s1, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v4, v5, v4
	v_mul_lo_u32 v5, s22, v10
	v_add_nc_u32_e32 v6, v7, v6
	v_mul_hi_u32 v7, v0, v12
	v_mul_lo_u32 v15, v0, v4
	v_mul_hi_u32 v17, v0, v4
	v_mul_lo_u32 v12, v1, v12
	v_mul_hi_u32 v20, v1, v4
	v_mul_lo_u32 v4, v1, v4
	v_add_nc_u32_e32 v5, v6, v5
	v_mul_hi_u32 v16, v10, v11
	v_mul_hi_u32 v18, v9, v11
	v_add_co_u32 v7, vcc_lo, v7, v15
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v17, vcc_lo
	v_mul_lo_u32 v17, v10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v12
	v_add_co_ci_u32_e32 v7, vcc_lo, v15, v19, vcc_lo
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v20, vcc_lo
	v_mul_hi_u32 v15, v10, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v7, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v12, vcc_lo
	v_mul_hi_u32 v20, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v12, vcc_lo, v1, v7, vcc_lo
	v_mul_lo_u32 v21, v9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v19, v13, v6
	v_mad_u64_u32 v[4:5], null, v14, v6, 0
	v_mad_u64_u32 v[0:1], null, v13, v12, 0
	v_mad_u64_u32 v[6:7], null, v14, v12, 0
	v_mul_lo_u32 v11, v9, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v19, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v12, vcc_lo, v16, v17
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v0, vcc_lo, v1, v5, vcc_lo
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, v12, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s0, v0, v6
	v_add_co_ci_u32_e64 v6, s0, 0, v1, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, v15, v18, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, v8, v5
	v_mad_u64_u32 v[0:1], null, s2, v5, 0
	v_mul_lo_u32 v12, s2, v6
	v_add_co_u32 v4, vcc_lo, v4, v21
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, v10, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v1, v1, v12, v11
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v7, vcc_lo
	v_add_co_u32 v11, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v19, v14, v1
	v_sub_co_u32 v0, vcc_lo, v13, v0
	v_add_co_u32 v10, s0, v5, 2
	v_add_co_ci_u32_e64 v15, s0, 0, v6, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_co_ci_u32_e64 v13, s0, v19, v8, vcc_lo
	v_sub_co_ci_u32_e32 v1, vcc_lo, v14, v1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s2, v0
	v_sub_co_u32 v19, s0, v0, s2
	v_mul_hi_u32 v16, s1, v4
	v_mul_lo_u32 v18, s1, v7
	v_cndmask_b32_e64 v0, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v13, vcc_lo, 0, v13, s0
	v_cmp_le_u32_e32 vcc_lo, s2, v19
	v_mul_lo_u32 v17, s22, v4
	v_mul_lo_u32 v9, s1, v4
	v_add_nc_u32_e32 v14, v16, v18
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v1, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v14, v14, v17
	v_mul_hi_u32 v20, v7, v9
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v13, v8
	v_mul_lo_u32 v21, v7, v9
	v_mul_hi_u32 v9, v4, v9
	v_cndmask_b32_e64 v19, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v1, v8
	v_cndmask_b32_e32 v0, v18, v0, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v13, v8
	v_mul_lo_u32 v8, v4, v14
	v_mul_hi_u32 v13, v7, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e64 s0, 0, v0
	v_cndmask_b32_e32 v1, v19, v16, vcc_lo
	v_mul_hi_u32 v16, v4, v14
	v_mul_lo_u32 v14, v7, v14
	v_add_co_u32 v0, s1, v9, v8
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_dual_cndmask_b32 v1, v12, v15 :: v_dual_cndmask_b32 v8, v11, v10
	v_add_co_ci_u32_e64 v9, vcc_lo, 0, v16, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v0, v21
	v_cndmask_b32_e64 v0, v6, v1, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v1, v5, v8, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v20, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_mul_lo_u32 v9, v8, s24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, v0, s23
	v_mad_u64_u32 v[0:1], null, v8, s23, v[2:3]
	v_add_co_u32 v5, vcc_lo, v4, v5
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v6, vcc_lo
	v_add3_u32 v8, v10, v1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[1:2], null, v0, v7, 0
	v_mul_hi_u32 v9, v0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v8, v5, 0
	v_mad_u64_u32 v[5:6], null, v8, v7, 0
	v_add_co_u32 v1, vcc_lo, v9, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, v1, v3
	v_add_co_ci_u32_e32 v1, vcc_lo, v2, v4, vcc_lo
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v5, s19, v3
	v_mad_u64_u32 v[1:2], null, s20, v3, 0
	v_mul_lo_u32 v6, s20, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v1, vcc_lo, v0, v1
	v_add3_u32 v2, v2, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v8, v2
	v_subrev_co_ci_u32_e64 v5, s0, s19, v5, vcc_lo
	v_add_co_u32 v6, s0, v3, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s0, 0, v4, s0
	v_sub_co_u32 v9, s0, v1, s20
	v_sub_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
	v_subrev_co_ci_u32_e64 v5, s0, 0, v5, s0
	v_cmp_le_u32_e32 vcc_lo, s20, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e64 s0, s19, v2
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v5
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v1
	v_cndmask_b32_e64 v1, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v2
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s19, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v11, v1, s0
	v_cndmask_b32_e32 v5, v10, v9, vcc_lo
	v_add_co_u32 v9, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v2, v10, v7 :: v_dual_cndmask_b32 v5, v9, v6
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_dual_cndmask_b32 v1, v3, v5 :: v_dual_cndmask_b32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 1, v[1:2]
	v_add_co_u32 v1, vcc_lo, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s18, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, v1, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v2, v8, vcc_lo
.LBB1_8:                                ; %Flow112
	s_or_b32 exec_lo, exec_lo, s15
.LBB1_9:                                ; %_Z17revertMatrixTransyyy.exit
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	s_add_u32 s19, s8, 1
	s_addc_u32 s18, s9, 0
	v_cvt_f32_u32_e32 v2, s19
	v_cvt_f32_u32_e32 v3, s18
	s_not_b64 s[14:15], s[8:9]
	s_sub_u32 s12, s8, s10
	s_subb_u32 s13, s9, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v2, v3, 0x4f800000, v2
	v_rcp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x5f7ffffc, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x2f800000, v2
	v_trunc_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v2, v3, 0xcf800000, v2
	v_cvt_u32_f32_e32 v4, v3
	v_cvt_u32_f32_e32 v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, s14, v4
	v_mul_hi_u32 v3, s14, v5
	v_mul_lo_u32 v6, s15, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	v_mul_lo_u32 v3, s14, v5
	v_add_nc_u32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v5, v3
	v_mul_lo_u32 v7, v5, v2
	v_mul_hi_u32 v8, v5, v2
	v_mul_hi_u32 v9, v4, v3
	v_mul_lo_u32 v3, v4, v3
	v_mul_hi_u32 v10, v4, v2
	v_mul_lo_u32 v2, v4, v2
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v3, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v5, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v2, s14, v6
	v_mul_lo_u32 v8, s15, v6
	v_mul_lo_u32 v7, s14, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v7
	v_mul_lo_u32 v7, s14, v6
	v_add_nc_u32_e32 v2, v2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v6, v7
	v_mul_lo_u32 v9, v6, v2
	v_mul_hi_u32 v10, v6, v2
	v_mul_hi_u32 v11, v3, v7
	v_mul_lo_u32 v7, v3, v7
	v_mul_hi_u32 v12, v3, v2
	v_mul_lo_u32 v2, v3, v2
	v_add_co_u32 v8, vcc_lo, v8, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v8, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v7, v2
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v2, vcc_lo, v0, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, v6, v7
	v_add_co_ci_u32_e64 v12, s0, v3, v8, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, -1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v13, v2, v10
	v_mad_u64_u32 v[6:7], null, v2, v12, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, v3, v10, 0
	v_mad_u64_u32 v[10:11], null, v3, v12, 0
	v_add_co_u32 v6, vcc_lo, v13, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
	v_mul_lo_u32 v10, s18, v8
	v_mad_u64_u32 v[6:7], null, s19, v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, s19, v9
	v_sub_co_u32 v6, vcc_lo, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v7, v7, v11, v10
	v_sub_nc_u32_e32 v10, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v10, s0, s18, v10, vcc_lo
	v_add_co_u32 v11, s0, v8, 2
	v_add_co_ci_u32_e64 v12, s0, 0, v9, s0
	v_sub_co_u32 v13, s0, v6, s19
	v_sub_co_ci_u32_e32 v7, vcc_lo, v3, v7, vcc_lo
	v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s19, v13
	v_cmp_eq_u32_e64 s0, s18, v7
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v10
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v6
	v_cndmask_b32_e64 v6, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v7
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v15, v6, s0
	v_cndmask_b32_e32 v10, v14, v13, vcc_lo
	v_add_co_u32 v13, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, v14, v12 :: v_dual_cndmask_b32 v10, v13, v11
	v_cmp_ne_u32_e32 vcc_lo, 0, v6
	v_dual_cndmask_b32 v7, v9, v7 :: v_dual_cndmask_b32 v6, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v7, s19
	v_mul_lo_u32 v11, v6, s18
	v_mad_u64_u32 v[8:9], null, v6, s19, 0
	v_cmp_ge_u64_e64 s2, s[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v9, v9, v11, v10
	v_sub_co_u32 v8, vcc_lo, v2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v9, vcc_lo, v3, v9, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[12:13], v[6:7]
	v_mov_b32_e32 v6, 0
	v_cmp_le_u64_e64 s0, s[12:13], v[8:9]
	v_cmp_ge_u64_e64 s1, s[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s2, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_17
; %bb.10:
	s_add_u32 s0, s8, 2
	s_addc_u32 s2, s9, 0
	s_mul_hi_u32 s3, s16, s0
	s_mul_i32 s2, s16, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s2, s3, s2
	s_mul_i32 s3, s17, s0
	s_mul_i32 s0, s16, s0
	s_add_i32 s3, s2, s3
	s_add_u32 s2, s0, 1
	s_addc_u32 s3, s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_le_u64_e64 s[2:3], v[2:3]
	s_xor_b32 s0, exec_lo, s0
; %bb.11:
	s_lshl_b64 s[2:3], s[10:11], 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_not_b64 s[2:3], s[2:3]
	s_add_u32 s2, s2, s8
	s_addc_u32 s3, s3, s9
	s_mul_hi_u32 s20, s2, s2
	s_mul_i32 s3, s2, s3
	s_mul_i32 s2, s2, s2
	s_add_i32 s20, s20, s3
	v_sub_co_u32 v2, vcc_lo, v2, s2
	s_add_i32 s20, s20, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, s20, v3, vcc_lo
; %bb.12:                               ; %Flow109
	s_and_not1_saveexec_b32 s2, s0
	s_cbranch_execz .LBB1_16
; %bb.13:
	s_add_u32 s0, s10, 1
	s_addc_u32 s20, s11, 0
	s_mul_i32 s3, s0, s18
	s_mul_hi_u32 s21, s0, s19
	s_mul_i32 s22, s20, s19
	s_add_i32 s3, s21, s3
	s_mul_i32 s21, s0, s19
	s_add_i32 s22, s3, s22
	s_add_u32 s24, s21, s10
	s_addc_u32 s25, s22, s11
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_u64_e64 s[24:25], v[2:3]
	s_cbranch_execz .LBB1_15
; %bb.14:
	s_add_u32 s0, s21, s0
	s_addc_u32 s20, s22, s20
	s_sub_u32 s21, 0, s19
	s_subb_u32 s22, 0, s18
	v_mul_hi_u32 v6, s21, v5
	v_mul_lo_u32 v7, s21, v4
	v_mul_lo_u32 v8, s22, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v6, v7
	v_mul_lo_u32 v7, s21, v5
	v_add_nc_u32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v5, v7
	v_mul_lo_u32 v9, v5, v6
	v_mul_hi_u32 v10, v5, v6
	v_mul_hi_u32 v11, v4, v7
	v_mul_lo_u32 v7, v4, v7
	v_mul_hi_u32 v12, v4, v6
	v_mul_lo_u32 v6, v4, v6
	v_add_co_u32 v8, vcc_lo, v8, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v8, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v7, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v8, s21, v6
	v_mul_lo_u32 v10, s22, v6
	v_mul_lo_u32 v9, s21, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v9
	v_mul_lo_u32 v9, s21, v6
	v_add_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v6, v9
	v_mul_lo_u32 v11, v6, v8
	v_mul_hi_u32 v12, v6, v8
	v_mul_hi_u32 v13, v7, v9
	v_mul_lo_u32 v9, v7, v9
	v_mul_hi_u32 v14, v7, v8
	v_mul_lo_u32 v8, v7, v8
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	v_sub_co_u32 v12, vcc_lo, v2, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, v6, v8
	v_add_co_ci_u32_e64 v13, s0, v7, v9, s0
	v_subrev_co_ci_u32_e32 v14, vcc_lo, s20, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v15, v12, v10
	v_mad_u64_u32 v[6:7], null, v12, v13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, v14, v10, 0
	v_mad_u64_u32 v[10:11], null, v14, v13, 0
	s_lshl_b64 s[20:21], s[10:11], 1
	v_add_co_u32 v6, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_not_b64 s[20:21], s[20:21]
	v_add_co_u32 v6, vcc_lo, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, v6, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
	v_mul_lo_u32 v10, s18, v8
	v_mad_u64_u32 v[6:7], null, s19, v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, s19, v9
	v_sub_co_u32 v6, vcc_lo, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v7, v7, v11, v10
	v_sub_nc_u32_e32 v10, v14, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v10, s0, s18, v10, vcc_lo
	v_add_co_u32 v11, s0, v8, 2
	v_add_co_ci_u32_e64 v12, s0, 0, v9, s0
	v_sub_co_u32 v13, s0, v6, s19
	v_sub_co_ci_u32_e32 v7, vcc_lo, v14, v7, vcc_lo
	v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s19, v13
	v_cmp_eq_u32_e64 s0, s18, v7
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v10
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v6
	v_cndmask_b32_e64 v6, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v7
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v15, v6, s0
	v_cndmask_b32_e32 v10, v14, v13, vcc_lo
	v_add_co_u32 v13, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	s_add_u32 s0, s20, s8
	s_addc_u32 s20, s21, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, v14, v12 :: v_dual_cndmask_b32 v10, v13, v11
	v_cmp_ne_u32_e32 vcc_lo, 0, v6
	v_dual_cndmask_b32 v6, v9, v7 :: v_dual_cndmask_b32 v7, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_not_b32_e32 v6, v6
	v_not_b32_e32 v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, s0, v6
	v_mul_lo_u32 v10, s20, v8
	v_mad_u64_u32 v[6:7], null, s0, v8, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v7, v10, v7, v9
	v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
.LBB1_15:                               ; %Flow108
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_16:                               ; %_Z11mediumTransyyy.exit
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v6, v[2:3], off
.LBB1_17:                               ; %Flow110
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s0, 0, s19
	s_subb_u32 s1, 0, s18
	v_mul_hi_u32 v2, s0, v5
	v_mul_lo_u32 v3, s0, v4
	v_mul_lo_u32 v7, s1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_lo_u32 v3, s0, v5
	v_add_nc_u32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v5, v3
	v_mul_lo_u32 v8, v5, v2
	v_mul_hi_u32 v9, v5, v2
	v_mul_hi_u32 v10, v4, v3
	v_mul_lo_u32 v3, v4, v3
	v_mul_hi_u32 v11, v4, v2
	v_mul_lo_u32 v2, v4, v2
	v_add_co_u32 v7, vcc_lo, v7, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v7, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, v8, v10, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v3, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v2, s0, v7
	v_mul_lo_u32 v9, s1, v7
	v_mul_lo_u32 v8, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v8
	v_mul_lo_u32 v8, s0, v7
	v_add_nc_u32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v7, v8
	v_mul_lo_u32 v10, v7, v2
	v_mul_hi_u32 v11, v7, v2
	v_mul_hi_u32 v12, v3, v8
	v_mul_lo_u32 v8, v3, v8
	v_mul_hi_u32 v13, v3, v2
	v_mul_lo_u32 v2, v3, v2
	v_add_co_u32 v9, vcc_lo, v9, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v8, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v2, vcc_lo, v0, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s0, v7, v8
	v_add_co_ci_u32_e64 v13, s0, v3, v9, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v14, v2, v11
	v_mad_u64_u32 v[7:8], null, v2, v13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[9:10], null, v3, v11, 0
	v_mad_u64_u32 v[11:12], null, v3, v13, 0
	v_add_co_u32 v7, vcc_lo, v14, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v8, v10, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
	v_add_co_u32 v9, vcc_lo, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	v_mul_lo_u32 v11, s18, v9
	v_mad_u64_u32 v[7:8], null, s19, v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v12, s19, v10
	v_sub_co_u32 v7, vcc_lo, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v12, v11
	v_sub_nc_u32_e32 v11, v3, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v11, s0, s18, v11, vcc_lo
	v_add_co_u32 v12, s0, v9, 2
	v_add_co_ci_u32_e64 v13, s0, 0, v10, s0
	v_sub_co_u32 v14, s0, v7, s19
	v_sub_co_ci_u32_e32 v8, vcc_lo, v3, v8, vcc_lo
	v_subrev_co_ci_u32_e64 v11, s0, 0, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s19, v14
	v_cmp_eq_u32_e64 s0, s18, v8
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v11
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v7
	v_cndmask_b32_e64 v7, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v8
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v16, v7, s0
	v_cndmask_b32_e32 v11, v15, v14, vcc_lo
	v_add_co_u32 v14, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v10, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v15, v13 :: v_dual_cndmask_b32 v11, v14, v12
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	v_dual_cndmask_b32 v8, v10, v8 :: v_dual_cndmask_b32 v7, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, v8, s19
	v_mul_lo_u32 v12, v7, s18
	v_mad_u64_u32 v[9:10], null, v7, s19, 0
	v_cmp_ge_u64_e64 s2, s[10:11], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v10, v10, v12, v11
	v_sub_co_u32 v9, vcc_lo, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v10, vcc_lo, v3, v10, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[12:13], v[7:8]
	v_mov_b32_e32 v7, 0
	v_cmp_le_u64_e64 s0, s[12:13], v[9:10]
	v_cmp_ge_u64_e64 s1, s[10:11], v[9:10]
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s2, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_25
; %bb.18:
	s_add_u32 s0, s8, 2
	s_addc_u32 s2, s9, 0
	s_mul_hi_u32 s3, s16, s0
	s_mul_i32 s2, s16, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s2, s3, s2
	s_mul_i32 s3, s17, s0
	s_mul_i32 s0, s16, s0
	s_add_i32 s3, s2, s3
	s_add_u32 s2, s0, 1
	s_addc_u32 s3, s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_le_u64_e64 s[2:3], v[2:3]
	s_xor_b32 s0, exec_lo, s0
; %bb.19:
	s_lshl_b64 s[2:3], s[10:11], 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_not_b64 s[2:3], s[2:3]
	s_add_u32 s2, s2, s8
	s_addc_u32 s3, s3, s9
	s_mul_hi_u32 s20, s2, s2
	s_mul_i32 s3, s2, s3
	s_mul_i32 s2, s2, s2
	s_add_i32 s20, s20, s3
	v_sub_co_u32 v2, vcc_lo, v2, s2
	s_add_i32 s20, s20, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, s20, v3, vcc_lo
; %bb.20:                               ; %Flow106
	s_and_not1_saveexec_b32 s2, s0
	s_cbranch_execz .LBB1_24
; %bb.21:
	s_add_u32 s0, s10, 1
	s_addc_u32 s20, s11, 0
	s_mul_i32 s3, s0, s18
	s_mul_hi_u32 s21, s0, s19
	s_mul_i32 s22, s20, s19
	s_add_i32 s3, s21, s3
	s_mul_i32 s21, s0, s19
	s_add_i32 s22, s3, s22
	s_add_u32 s24, s21, s10
	s_addc_u32 s25, s22, s11
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_u64_e64 s[24:25], v[2:3]
	s_cbranch_execz .LBB1_23
; %bb.22:
	s_add_u32 s0, s21, s0
	s_addc_u32 s20, s22, s20
	s_sub_u32 s21, 0, s19
	s_subb_u32 s22, 0, s18
	v_mul_hi_u32 v7, s21, v5
	v_mul_lo_u32 v8, s21, v4
	v_mul_lo_u32 v9, s22, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v7, v8
	v_mul_lo_u32 v8, s21, v5
	v_add_nc_u32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v5, v8
	v_mul_lo_u32 v10, v5, v7
	v_mul_hi_u32 v11, v5, v7
	v_mul_hi_u32 v12, v4, v8
	v_mul_lo_u32 v8, v4, v8
	v_mul_hi_u32 v13, v4, v7
	v_mul_lo_u32 v7, v4, v7
	v_add_co_u32 v9, vcc_lo, v9, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, v4, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, s21, v7
	v_mul_lo_u32 v11, s22, v7
	v_mul_lo_u32 v10, s21, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v10
	v_mul_lo_u32 v10, s21, v7
	v_add_nc_u32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v7, v10
	v_mul_lo_u32 v12, v7, v9
	v_mul_hi_u32 v13, v7, v9
	v_mul_hi_u32 v14, v8, v10
	v_mul_lo_u32 v10, v8, v10
	v_mul_hi_u32 v15, v8, v9
	v_mul_lo_u32 v9, v8, v9
	v_add_co_u32 v11, vcc_lo, v11, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v11, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	v_sub_co_u32 v13, vcc_lo, v2, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s0, v7, v9
	v_add_co_ci_u32_e64 v14, s0, v8, v10, s0
	v_subrev_co_ci_u32_e32 v15, vcc_lo, s20, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v16, v13, v11
	v_mad_u64_u32 v[7:8], null, v13, v14, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[9:10], null, v15, v11, 0
	v_mad_u64_u32 v[11:12], null, v15, v14, 0
	s_lshl_b64 s[20:21], s[10:11], 1
	v_add_co_u32 v7, vcc_lo, v16, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_not_b64 s[20:21], s[20:21]
	v_add_co_u32 v7, vcc_lo, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v8, v10, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
	v_add_co_u32 v9, vcc_lo, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	v_mul_lo_u32 v11, s18, v9
	v_mad_u64_u32 v[7:8], null, s19, v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v12, s19, v10
	v_sub_co_u32 v7, vcc_lo, v13, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v12, v11
	v_sub_nc_u32_e32 v11, v15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v11, s0, s18, v11, vcc_lo
	v_add_co_u32 v12, s0, v9, 2
	v_add_co_ci_u32_e64 v13, s0, 0, v10, s0
	v_sub_co_u32 v14, s0, v7, s19
	v_sub_co_ci_u32_e32 v8, vcc_lo, v15, v8, vcc_lo
	v_subrev_co_ci_u32_e64 v11, s0, 0, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s19, v14
	v_cmp_eq_u32_e64 s0, s18, v8
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v11
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v7
	v_cndmask_b32_e64 v7, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v8
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v16, v7, s0
	v_cndmask_b32_e32 v11, v15, v14, vcc_lo
	v_add_co_u32 v14, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v10, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v11
	s_add_u32 s0, s20, s8
	s_addc_u32 s20, s21, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v15, v13 :: v_dual_cndmask_b32 v11, v14, v12
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	v_dual_cndmask_b32 v7, v10, v8 :: v_dual_cndmask_b32 v8, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_not_b32_e32 v7, v7
	v_not_b32_e32 v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, s0, v7
	v_mul_lo_u32 v11, s20, v9
	v_mad_u64_u32 v[7:8], null, s0, v9, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v11, v8, v10
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
.LBB1_23:                               ; %Flow105
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_24:                               ; %_Z11mediumTransyyy.exit55
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v7, v[2:3], off
.LBB1_25:                               ; %Flow107
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s0, 0, s19
	s_subb_u32 s1, 0, s18
	v_mul_hi_u32 v2, s0, v5
	v_mul_lo_u32 v3, s0, v4
	v_mul_lo_u32 v8, s1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_lo_u32 v3, s0, v5
	v_add_nc_u32_e32 v2, v2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v8, v5, v3
	v_mul_lo_u32 v9, v5, v2
	v_mul_hi_u32 v10, v5, v2
	v_mul_hi_u32 v11, v4, v3
	v_mul_lo_u32 v3, v4, v3
	v_mul_hi_u32 v12, v4, v2
	v_mul_lo_u32 v2, v4, v2
	v_add_co_u32 v8, vcc_lo, v8, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v8, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, v9, v11, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v3, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v5, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v8, s0, v2
	v_mul_lo_u32 v10, s1, v2
	v_mul_lo_u32 v9, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v9
	v_mul_lo_u32 v9, s0, v2
	v_add_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v2, v9
	v_mul_lo_u32 v11, v2, v8
	v_mul_hi_u32 v12, v2, v8
	v_mul_hi_u32 v13, v3, v9
	v_mul_lo_u32 v9, v3, v9
	v_mul_hi_u32 v14, v3, v8
	v_mul_lo_u32 v8, v3, v8
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	v_sub_co_u32 v12, vcc_lo, v0, s19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, v2, v8
	v_add_co_ci_u32_e64 v13, s0, v3, v9, s0
	v_subrev_co_ci_u32_e32 v14, vcc_lo, s18, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v15, v12, v10
	v_mad_u64_u32 v[2:3], null, v12, v13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, v14, v10, 0
	v_mad_u64_u32 v[10:11], null, v14, v13, 0
	v_add_co_u32 v2, vcc_lo, v15, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v3, v9, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
	v_mul_lo_u32 v10, s18, v8
	v_mad_u64_u32 v[2:3], null, s19, v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, s19, v9
	v_sub_co_u32 v2, vcc_lo, v12, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v3, v11, v10
	v_sub_nc_u32_e32 v10, v14, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v10, s0, s18, v10, vcc_lo
	v_add_co_u32 v11, s0, v8, 2
	v_add_co_ci_u32_e64 v13, s0, 0, v9, s0
	v_sub_co_u32 v15, s0, v2, s19
	v_sub_co_ci_u32_e32 v3, vcc_lo, v14, v3, vcc_lo
	v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s19, v15
	v_cmp_eq_u32_e64 s0, s18, v3
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v10
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v2
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v3
	v_cndmask_b32_e64 v17, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v17, v2, s0
	v_cndmask_b32_e32 v10, v16, v15, vcc_lo
	v_add_co_u32 v15, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v16, v13 :: v_dual_cndmask_b32 v10, v15, v11
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_dual_cndmask_b32 v3, v9, v3 :: v_dual_cndmask_b32 v2, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v3, s19
	v_mul_lo_u32 v11, v2, s18
	v_mad_u64_u32 v[8:9], null, v2, s19, 0
	v_cmp_ge_u64_e64 s2, s[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v9, v9, v11, v10
	v_sub_co_u32 v8, vcc_lo, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e32 v9, vcc_lo, v14, v9, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[12:13], v[2:3]
	v_cmp_le_u64_e64 s0, s[12:13], v[8:9]
	v_cmp_ge_u64_e64 s1, s[10:11], v[8:9]
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s2, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_33
; %bb.26:
	s_add_u32 s0, s8, 2
	s_addc_u32 s2, s9, 0
	s_mul_hi_u32 s3, s16, s0
	s_mul_i32 s2, s16, s2
	v_add_co_u32 v2, vcc_lo, v0, s14
	s_add_i32 s2, s3, s2
	s_mul_i32 s3, s17, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v1, vcc_lo
	s_mul_i32 s0, s16, s0
	s_add_i32 s3, s2, s3
	s_add_u32 s2, s0, 1
	s_addc_u32 s3, s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_le_u64_e64 s[2:3], v[2:3]
	s_xor_b32 s0, exec_lo, s0
; %bb.27:
	s_lshl_b64 s[2:3], s[10:11], 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_not_b64 s[2:3], s[2:3]
	s_add_u32 s2, s2, s8
	s_addc_u32 s3, s3, s9
	s_mul_hi_u32 s14, s2, s2
	s_mul_i32 s3, s2, s3
	s_mul_i32 s2, s2, s2
	s_add_i32 s14, s14, s3
	v_sub_co_u32 v2, vcc_lo, v2, s2
	s_add_i32 s14, s14, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, s14, v3, vcc_lo
; %bb.28:                               ; %Flow103
	s_and_not1_saveexec_b32 s2, s0
	s_cbranch_execz .LBB1_32
; %bb.29:
	s_add_u32 s0, s10, 1
	s_addc_u32 s14, s11, 0
	s_mul_i32 s3, s0, s18
	s_mul_hi_u32 s15, s0, s19
	s_mul_i32 s20, s14, s19
	s_add_i32 s3, s15, s3
	s_mul_i32 s15, s0, s19
	s_add_i32 s20, s3, s20
	s_add_u32 s22, s15, s10
	s_addc_u32 s23, s20, s11
	s_mov_b32 s3, exec_lo
	v_cmpx_lt_u64_e64 s[22:23], v[2:3]
	s_cbranch_execz .LBB1_31
; %bb.30:
	s_add_u32 s0, s15, s0
	s_addc_u32 s14, s20, s14
	s_sub_u32 s15, 0, s19
	s_subb_u32 s20, 0, s18
	v_mul_hi_u32 v8, s15, v5
	v_mul_lo_u32 v9, s15, v4
	v_mul_lo_u32 v10, s20, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v9
	v_mul_lo_u32 v9, s15, v5
	v_add_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v5, v9
	v_mul_lo_u32 v11, v5, v8
	v_mul_hi_u32 v12, v5, v8
	v_mul_hi_u32 v13, v4, v9
	v_mul_lo_u32 v9, v4, v9
	v_mul_hi_u32 v14, v4, v8
	v_mul_lo_u32 v8, v4, v8
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v5, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, v4, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v10, s15, v8
	v_mul_lo_u32 v12, s20, v8
	v_mul_lo_u32 v11, s15, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v10, v11
	v_mul_lo_u32 v11, s15, v8
	v_add_nc_u32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v8, v11
	v_mul_lo_u32 v13, v8, v10
	v_mul_hi_u32 v14, v8, v10
	v_mul_hi_u32 v15, v9, v11
	v_mul_lo_u32 v11, v9, v11
	v_mul_hi_u32 v16, v9, v10
	v_mul_lo_u32 v10, v9, v10
	v_add_co_u32 v12, vcc_lo, v12, v13
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v12, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, v13, v15, vcc_lo
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v11, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	v_sub_co_u32 v14, vcc_lo, v2, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, s0, v8, v10
	v_add_co_ci_u32_e64 v15, s0, v9, v11, s0
	v_subrev_co_ci_u32_e32 v16, vcc_lo, s14, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v17, v14, v12
	v_mad_u64_u32 v[8:9], null, v14, v15, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[10:11], null, v16, v12, 0
	v_mad_u64_u32 v[12:13], null, v16, v15, 0
	s_lshl_b64 s[14:15], s[10:11], 1
	v_add_co_u32 v8, vcc_lo, v17, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_not_b64 s[14:15], s[14:15]
	v_add_co_u32 v8, vcc_lo, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v9, v11, vcc_lo
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
	v_add_co_u32 v10, vcc_lo, v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v9, vcc_lo
	v_mul_lo_u32 v12, s18, v10
	v_mad_u64_u32 v[8:9], null, s19, v10, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v13, s19, v11
	v_sub_co_u32 v8, vcc_lo, v14, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v9, v13, v12
	v_sub_nc_u32_e32 v12, v16, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v12, s0, s18, v12, vcc_lo
	v_add_co_u32 v13, s0, v10, 2
	v_add_co_ci_u32_e64 v14, s0, 0, v11, s0
	v_sub_co_u32 v15, s0, v8, s19
	v_sub_co_ci_u32_e32 v9, vcc_lo, v16, v9, vcc_lo
	v_subrev_co_ci_u32_e64 v12, s0, 0, v12, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s19, v15
	v_cmp_eq_u32_e64 s0, s18, v9
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v12
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v8
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v9
	v_cndmask_b32_e64 v17, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v17, v8, s0
	v_cndmask_b32_e32 v12, v16, v15, vcc_lo
	v_add_co_u32 v15, vcc_lo, v10, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v11, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v12
	s_add_u32 s0, s14, s8
	s_addc_u32 s14, s15, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v16, v14 :: v_dual_cndmask_b32 v12, v15, v13
	v_cmp_ne_u32_e32 vcc_lo, 0, v8
	v_dual_cndmask_b32 v8, v11, v9 :: v_dual_cndmask_b32 v9, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_not_b32_e32 v8, v8
	v_not_b32_e32 v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, s0, v8
	v_mul_lo_u32 v12, s14, v10
	v_mad_u64_u32 v[8:9], null, s0, v10, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v12, v9, v11
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
.LBB1_31:                               ; %Flow102
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_32:                               ; %_Z11mediumTransyyy.exit63
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v8, v[2:3], off
.LBB1_33:                               ; %Flow104
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s0, 0, s19
	s_subb_u32 s1, 0, s18
	v_mul_hi_u32 v2, s0, v5
	v_mul_lo_u32 v3, s0, v4
	v_mul_lo_u32 v9, s1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_lo_u32 v3, s0, v5
	v_add_nc_u32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v5, v3
	v_mul_lo_u32 v10, v5, v2
	v_mul_hi_u32 v11, v5, v2
	v_mul_hi_u32 v12, v4, v3
	v_mul_lo_u32 v3, v4, v3
	v_mul_hi_u32 v13, v4, v2
	v_mul_lo_u32 v2, v4, v2
	v_add_co_u32 v9, vcc_lo, v9, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, v10, v12, vcc_lo
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v3, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v5, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v2, s0, v9
	v_mul_lo_u32 v11, s1, v9
	v_mul_lo_u32 v10, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v10
	v_mul_lo_u32 v10, s0, v9
	v_add_nc_u32_e32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v9, v10
	v_mul_lo_u32 v12, v9, v2
	v_mul_hi_u32 v13, v9, v2
	v_mul_hi_u32 v14, v3, v10
	v_mul_lo_u32 v10, v3, v10
	v_mul_hi_u32 v15, v3, v2
	v_mul_lo_u32 v2, v3, v2
	v_add_co_u32 v11, vcc_lo, v11, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v11, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, v2
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v2, vcc_lo, v0, s19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s0, v9, v10
	v_add_co_ci_u32_e64 v15, s0, v3, v11, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s18, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v16, v2, v13
	v_mad_u64_u32 v[9:10], null, v2, v15, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[11:12], null, v3, v13, 0
	v_mad_u64_u32 v[13:14], null, v3, v15, 0
	v_add_co_u32 v9, vcc_lo, v16, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v10, v12, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v11, vcc_lo, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v10, vcc_lo
	v_mul_lo_u32 v13, s18, v11
	v_mad_u64_u32 v[9:10], null, s19, v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v14, s19, v12
	v_sub_co_u32 v9, vcc_lo, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v10, v10, v14, v13
	v_sub_nc_u32_e32 v13, v3, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v13, s0, s18, v13, vcc_lo
	v_add_co_u32 v14, s0, v11, 2
	v_add_co_ci_u32_e64 v15, s0, 0, v12, s0
	v_sub_co_u32 v16, s0, v9, s19
	v_sub_co_ci_u32_e32 v10, vcc_lo, v3, v10, vcc_lo
	v_subrev_co_ci_u32_e64 v13, s0, 0, v13, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s19, v16
	v_cmp_eq_u32_e64 s0, s18, v10
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v13
	v_cndmask_b32_e64 v17, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v9
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v10
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v18, v9, s0
	v_cndmask_b32_e32 v13, v17, v16, vcc_lo
	v_add_co_u32 v16, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v12, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v17, v15 :: v_dual_cndmask_b32 v13, v16, v14
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	v_dual_cndmask_b32 v10, v12, v10 :: v_dual_cndmask_b32 v9, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v13, v10, s19
	v_mul_lo_u32 v14, v9, s18
	v_mad_u64_u32 v[11:12], null, v9, s19, 0
	v_cmp_ge_u64_e64 s2, s[10:11], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v12, v12, v14, v13
	v_sub_co_u32 v11, vcc_lo, v2, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v12, vcc_lo, v3, v12, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[12:13], v[9:10]
	v_mov_b32_e32 v9, 0
	v_cmp_le_u64_e64 s0, s[12:13], v[11:12]
	v_cmp_ge_u64_e64 s1, s[10:11], v[11:12]
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s2, s0
	s_add_u32 s1, s8, 2
	s_addc_u32 s2, s9, 0
	s_mul_hi_u32 s3, s16, s1
	s_mul_i32 s2, s16, s2
	s_mul_i32 s17, s17, s1
	s_add_i32 s2, s3, s2
	s_mul_i32 s16, s16, s1
	s_add_i32 s1, s2, s17
	s_add_u32 s2, s16, 1
	s_addc_u32 s3, s1, 0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_41
; %bb.34:
	s_mov_b32 s0, exec_lo
	v_cmpx_le_u64_e64 s[2:3], v[2:3]
	s_xor_b32 s0, exec_lo, s0
; %bb.35:
	s_lshl_b64 s[12:13], s[10:11], 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_not_b64 s[12:13], s[12:13]
	s_add_u32 s12, s12, s8
	s_addc_u32 s13, s13, s9
	s_mul_hi_u32 s14, s12, s12
	s_mul_i32 s13, s12, s13
	s_mul_i32 s12, s12, s12
	s_add_i32 s14, s14, s13
	v_sub_co_u32 v2, vcc_lo, v2, s12
	s_add_i32 s14, s14, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_subrev_co_ci_u32_e32 v3, vcc_lo, s14, v3, vcc_lo
; %bb.36:                               ; %Flow100
	s_and_not1_saveexec_b32 s12, s0
	s_cbranch_execz .LBB1_40
; %bb.37:
	s_add_u32 s0, s10, 1
	s_addc_u32 s14, s11, 0
	s_mul_i32 s13, s0, s18
	s_mul_hi_u32 s15, s0, s19
	s_mul_i32 s16, s14, s19
	s_add_i32 s13, s15, s13
	s_mul_i32 s15, s0, s19
	s_add_i32 s16, s13, s16
	s_add_u32 s20, s15, s10
	s_addc_u32 s21, s16, s11
	s_mov_b32 s13, exec_lo
	v_cmpx_lt_u64_e64 s[20:21], v[2:3]
	s_cbranch_execz .LBB1_39
; %bb.38:
	s_add_u32 s0, s15, s0
	s_addc_u32 s14, s16, s14
	s_sub_u32 s15, 0, s19
	s_subb_u32 s16, 0, s18
	v_mul_hi_u32 v9, s15, v5
	v_mul_lo_u32 v10, s15, v4
	v_mul_lo_u32 v11, s16, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v10
	v_mul_lo_u32 v10, s15, v5
	v_add_nc_u32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v5, v10
	v_mul_lo_u32 v12, v5, v9
	v_mul_hi_u32 v13, v5, v9
	v_mul_hi_u32 v14, v4, v10
	v_mul_lo_u32 v10, v4, v10
	v_mul_hi_u32 v15, v4, v9
	v_mul_lo_u32 v9, v4, v9
	v_add_co_u32 v11, vcc_lo, v11, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v11, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v5, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, v4, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v11, s15, v9
	v_mul_lo_u32 v13, s16, v9
	v_mul_lo_u32 v12, s15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v11, v12
	v_mul_lo_u32 v12, s15, v9
	v_add_nc_u32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v9, v12
	v_mul_lo_u32 v14, v9, v11
	v_mul_hi_u32 v15, v9, v11
	v_mul_hi_u32 v16, v10, v12
	v_mul_lo_u32 v12, v10, v12
	v_mul_hi_u32 v17, v10, v11
	v_mul_lo_u32 v11, v10, v11
	v_add_co_u32 v13, vcc_lo, v13, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v13, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, v14, v16, vcc_lo
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v12, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
	v_sub_co_u32 v15, vcc_lo, v2, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s0, v9, v11
	v_add_co_ci_u32_e64 v16, s0, v10, v12, s0
	v_subrev_co_ci_u32_e32 v17, vcc_lo, s14, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v18, v15, v13
	v_mad_u64_u32 v[9:10], null, v15, v16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[11:12], null, v17, v13, 0
	v_mad_u64_u32 v[13:14], null, v17, v16, 0
	s_lshl_b64 s[14:15], s[10:11], 1
	v_add_co_u32 v9, vcc_lo, v18, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_not_b64 s[14:15], s[14:15]
	v_add_co_u32 v9, vcc_lo, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v10, v12, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v11, vcc_lo, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v10, vcc_lo
	v_mul_lo_u32 v13, s18, v11
	v_mad_u64_u32 v[9:10], null, s19, v11, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v14, s19, v12
	v_sub_co_u32 v9, vcc_lo, v15, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v10, v10, v14, v13
	v_sub_nc_u32_e32 v13, v17, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v13, s0, s18, v13, vcc_lo
	v_add_co_u32 v14, s0, v11, 2
	v_add_co_ci_u32_e64 v15, s0, 0, v12, s0
	v_sub_co_u32 v16, s0, v9, s19
	v_sub_co_ci_u32_e32 v10, vcc_lo, v17, v10, vcc_lo
	v_subrev_co_ci_u32_e64 v13, s0, 0, v13, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s19, v16
	v_cmp_eq_u32_e64 s0, s18, v10
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v13
	v_cndmask_b32_e64 v17, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v9
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v10
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v18, v9, s0
	v_cndmask_b32_e32 v13, v17, v16, vcc_lo
	v_add_co_u32 v16, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v12, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v13
	s_add_u32 s0, s14, s8
	s_addc_u32 s14, s15, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v17, v15 :: v_dual_cndmask_b32 v13, v16, v14
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	v_dual_cndmask_b32 v9, v12, v10 :: v_dual_cndmask_b32 v10, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_not_b32_e32 v9, v9
	v_not_b32_e32 v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v12, s0, v9
	v_mul_lo_u32 v13, s14, v11
	v_mad_u64_u32 v[9:10], null, s0, v11, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v10, v13, v10, v12
	v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
.LBB1_39:                               ; %Flow99
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_40:                               ; %_Z11mediumTransyyy.exit71
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v9, v[2:3], off
.LBB1_41:                               ; %Flow101
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_le_u64_e64 s[2:3], v[0:1]
	s_xor_b32 s0, exec_lo, s0
; %bb.42:
	s_lshl_b64 s[2:3], s[10:11], 1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_not_b64 s[2:3], s[2:3]
	s_add_u32 s1, s2, s8
	s_addc_u32 s2, s3, s9
	s_mul_hi_u32 s3, s1, s1
	s_mul_i32 s2, s1, s2
	s_mul_i32 s1, s1, s1
	s_add_i32 s3, s3, s2
	v_sub_co_u32 v0, vcc_lo, v0, s1
	s_add_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_subrev_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
; %bb.43:                               ; %Flow98
	s_and_not1_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_47
; %bb.44:
	s_add_u32 s0, s10, 1
	s_addc_u32 s3, s11, 0
	s_mul_i32 s2, s0, s18
	s_mul_hi_u32 s4, s0, s19
	s_mul_i32 s5, s3, s19
	s_add_i32 s2, s4, s2
	s_mul_i32 s4, s0, s19
	s_add_i32 s5, s2, s5
	s_add_u32 s12, s4, s10
	s_addc_u32 s13, s5, s11
	s_mov_b32 s2, exec_lo
	v_cmpx_lt_u64_e64 s[12:13], v[0:1]
	s_cbranch_execz .LBB1_46
; %bb.45:
	s_add_u32 s0, s4, s0
	s_addc_u32 s3, s5, s3
	s_sub_u32 s4, 0, s19
	s_subb_u32 s5, 0, s18
	v_mul_hi_u32 v2, s4, v5
	v_mul_lo_u32 v3, s4, v4
	v_mul_lo_u32 v10, s5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_lo_u32 v3, s4, v5
	v_add_nc_u32_e32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v5, v3
	v_mul_lo_u32 v11, v5, v2
	v_mul_hi_u32 v12, v5, v2
	v_mul_hi_u32 v13, v4, v3
	v_mul_lo_u32 v3, v4, v3
	v_mul_hi_u32 v14, v4, v2
	v_mul_lo_u32 v2, v4, v2
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v10, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v3, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v5, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v4, s4, v2
	v_mul_lo_u32 v10, s5, v2
	v_mul_lo_u32 v5, s4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, v4, v5
	v_mul_lo_u32 v5, s4, v2
	s_lshl_b64 s[4:5], s[10:11], 1
	s_not_b64 s[4:5], s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v10
	v_mul_hi_u32 v10, v2, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v11, v2, v4
	v_mul_hi_u32 v12, v2, v4
	v_mul_hi_u32 v13, v3, v5
	v_mul_lo_u32 v5, v3, v5
	v_mul_hi_u32 v14, v3, v4
	v_mul_lo_u32 v4, v3, v4
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v10, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
	v_sub_co_u32 v12, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, v2, v4
	v_add_co_ci_u32_e64 v13, s0, v3, v5, s0
	v_subrev_co_ci_u32_e32 v14, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v15, v12, v10
	v_mad_u64_u32 v[2:3], null, v12, v13, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v14, v10, 0
	v_mad_u64_u32 v[10:11], null, v14, v13, 0
	v_add_co_u32 v2, vcc_lo, v15, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v3, v5, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v4, vcc_lo, v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	v_mul_lo_u32 v10, s18, v4
	v_mad_u64_u32 v[2:3], null, s19, v4, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, s19, v5
	v_sub_co_u32 v2, vcc_lo, v12, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v3, v11, v10
	v_sub_nc_u32_e32 v10, v14, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v10, s0, s18, v10, vcc_lo
	v_add_co_u32 v11, s0, v4, 2
	v_add_co_ci_u32_e64 v12, s0, 0, v5, s0
	v_sub_co_u32 v13, s0, v2, s19
	v_sub_co_ci_u32_e32 v3, vcc_lo, v14, v3, vcc_lo
	v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s19, v13
	v_cmp_eq_u32_e64 s0, s18, v3
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s18, v10
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v2
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s18, v3
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s18, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v15, v2, s0
	v_cndmask_b32_e32 v10, v14, v13, vcc_lo
	v_add_co_u32 v13, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	s_add_u32 s0, s4, s8
	s_addc_u32 s3, s5, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v14, v12 :: v_dual_cndmask_b32 v10, v13, v11
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_dual_cndmask_b32 v2, v5, v3 :: v_dual_cndmask_b32 v3, v4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_not_b32_e32 v2, v2
	v_not_b32_e32 v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, s0, v2
	v_mul_lo_u32 v10, s3, v4
	v_mad_u64_u32 v[2:3], null, s0, v4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v10, v3, v5
	v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
.LBB1_46:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_47:                               ; %_Z11mediumTransyyy.exit76
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v6, v7
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_f32_e32 v2, v2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v9
	v_mul_f32_e32 v2, 0x3e800000, v2
	global_store_b32 v[0:1], v2, off
.LBB1_48:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21calculateKernelUpdatePfS_yy
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z21calculateKernelUpdatePfS_yy, .Lfunc_end1-_Z21calculateKernelUpdatePfS_yy
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 11696
; NumSgprs: 28
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15calculateKernelPfS_y
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15calculateKernelPfS_y.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21calculateKernelUpdatePfS_yy
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z21calculateKernelUpdatePfS_yy.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
