#include <stdio.h>
#include <stdlib.h>
#include <math.h>

typedef unsigned long long bignum;

// CUDA kernel. Each thread takes care of one element of c
__device__ int isPrime(bignum x)
{

    bignum i;
    bignum lim = (bignum)sqrt((float)x) + 1;

    if (x % 2 == 0)
    {
        return 0;
    }

    for (i = 3; i < lim; i += 2)
    {
        if (x % i == 0)
            return 0;
    }

    return 1;
}

__global__ void checkPrimes(int *results, int arr_size)
{
    // Get our global thread ID
    bignum index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index < arr_size)
    {
        bignum number = 2 * index + 1;
        results[index] = isPrime(number);
    }
}

int main(int argc, char *argv[])
{
    if (argc < 2)
    {
        printf("Usage: prime upbound\n");
        exit(-1);
    }

    bignum n = (bignum)atoi(argv[1]);

    // Host input vectors
    int *h_results;

    // Device input vectors
    int *d_results;

    size_t arr_size = (int)ceil((float) ((n - 1.0) / 2.0));
    printf("arr_size: %ld\n", arr_size);

    // Size, in bytes, of each vector
    size_t results_num_bytes = arr_size * sizeof(int);

    // Allocate memory for each vector on host
    h_results = (int *)malloc(results_num_bytes);

    // Allocate memory for each vector on GPU
    cudaMalloc(&d_results, results_num_bytes);

    bignum i;
    // Initialize vectors on host
    for (i = 0; i < arr_size; i++)
    {
        h_results[i] = 0;
    }

    // Copy host vectors to device
    cudaMemcpy(d_results, h_results, results_num_bytes, cudaMemcpyHostToDevice);

    int blockSize, gridSize;

    // Number of threads in each thread block
    blockSize = 1024;

    // Number of thread blocks in grid
    gridSize = (int)ceil((float) ((n + 1.0) / 2.0 / blockSize));
    // gridSize = (int)ceil((float)n / blockSize);
    printf("gridSize: %d\n", gridSize);
    printf("gridSize * blockSize: %d\n", gridSize*blockSize);

    // Execute the kernel
    checkPrimes<<<gridSize, blockSize>>>(d_results, arr_size);

    // Copy array back to host
    cudaMemcpy(h_results, d_results, results_num_bytes, cudaMemcpyDeviceToHost);

    // Sum up vector c and print result divided by n, this should equal 1 without error
    bignum sum = 0;
    for (i = 0; i < arr_size; i++)
    {
        sum += h_results[i];
    }
    printf("final result: %lld\n", sum);

    // Release device memory
    cudaFree(d_results);

    // Release host memory
    free(h_results);

    return 0;
}

	.file	"tmpxft_003a4004_00000000-6_lab1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7isPrimey
	.type	_Z7isPrimey, @function
_Z7isPrimey:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z7isPrimey, .-_Z7isPrimey
	.globl	_Z32__device_stub__Z11checkPrimesPiiPii
	.type	_Z32__device_stub__Z11checkPrimesPiiPii, @function
_Z32__device_stub__Z11checkPrimesPiiPii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11checkPrimesPii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L4:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z32__device_stub__Z11checkPrimesPiiPii, .-_Z32__device_stub__Z11checkPrimesPiiPii
	.globl	_Z11checkPrimesPii
	.type	_Z11checkPrimesPii, @function
_Z11checkPrimesPii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z11checkPrimesPiiPii
	.cfi_endproc
.LFE2054:
	.size	_Z11checkPrimesPii, .-_Z11checkPrimesPii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Usage: prime upbound\n"
.LC3:
	.string	"arr_size: %ld\n"
.LC5:
	.string	"gridSize: %d\n"
.LC6:
	.string	"gridSize * blockSize: %d\n"
.LC7:
	.string	"final result: %lld\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	decl	%edi
	jg	.L11
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L11:
	movq	8(%rsi), %rdi
	call	atoi@PLT
	cltq
	testq	%rax, %rax
	js	.L12
	cvtsi2sdq	%rax, %xmm1
	movsd	%xmm1, 8(%rsp)
	jmp	.L13
.L12:
	movq	%rax, %rdx
	andl	$1, %eax
	shrq	%rdx
	orq	%rax, %rdx
	cvtsi2sdq	%rdx, %xmm0
	addsd	%xmm0, %xmm0
	movsd	%xmm0, 8(%rsp)
.L13:
	movsd	8(%rsp), %xmm0
	subsd	.LC1(%rip), %xmm0
	mulsd	.LC2(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	call	ceilf@PLT
	movl	$2, %edi
	xorl	%eax, %eax
	cvttss2sil	%xmm0, %r13d
	leaq	.LC3(%rip), %rsi
	movslq	%r13d, %rbp
	movq	%rbp, %rdx
	leaq	0(,%rbp,4), %r12
	call	__printf_chk@PLT
	movq	%r12, %rdi
	call	malloc@PLT
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	xorl	%eax, %eax
.L14:
	cmpq	%rbp, %rax
	jnb	.L21
	xorl	%edx, %edx
	movl	%edx, (%rbx,%rax,4)
	incq	%rax
	jmp	.L14
.L21:
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	call	cudaMemcpy@PLT
	movsd	.LC1(%rip), %xmm0
	addsd	8(%rsp), %xmm0
	mulsd	.LC2(%rip), %xmm0
	mulsd	.LC4(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	call	ceilf@PLT
	movl	$2, %edi
	xorl	%eax, %eax
	cvttss2sil	%xmm0, %r14d
	leaq	.LC5(%rip), %rsi
	movl	%r14d, %edx
	call	__printf_chk@PLT
	movl	%r14d, %edx
	movl	$2, %edi
	xorl	%eax, %eax
	sall	$10, %edx
	leaq	.LC6(%rip), %rsi
	call	__printf_chk@PLT
	movl	%r14d, 32(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$4194305, %edx
	movl	$1, %ecx
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	salq	$10, %rdx
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	24(%rsp), %rdi
	movl	%r13d, %esi
	call	_Z32__device_stub__Z11checkPrimesPiiPii
.L16:
	movq	24(%rsp), %rsi
	movq	%r12, %rdx
	movl	$2, %ecx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	xorl	%edx, %edx
	xorl	%eax, %eax
.L17:
	cmpq	%rbp, %rax
	jnb	.L22
	movslq	(%rbx,%rax,4), %rcx
	incq	%rax
	addq	%rcx, %rdx
	jmp	.L17
.L22:
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z11checkPrimesPii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z11checkPrimesPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1072693248
	.align 8
.LC2:
	.long	0
	.long	1071644672
	.align 8
.LC4:
	.long	0
	.long	1062207488
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>

typedef unsigned long long bignum;

// CUDA kernel. Each thread takes care of one element of c
__device__ int isPrime(bignum x)
{

    bignum i;
    bignum lim = (bignum)sqrt((float)x) + 1;

    if (x % 2 == 0)
    {
        return 0;
    }

    for (i = 3; i < lim; i += 2)
    {
        if (x % i == 0)
            return 0;
    }

    return 1;
}

__global__ void checkPrimes(int *results, int arr_size)
{
    // Get our global thread ID
    bignum index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index < arr_size)
    {
        bignum number = 2 * index + 1;
        results[index] = isPrime(number);
    }
}

int main(int argc, char *argv[])
{
    if (argc < 2)
    {
        printf("Usage: prime upbound\n");
        exit(-1);
    }

    bignum n = (bignum)atoi(argv[1]);

    // Host input vectors
    int *h_results;

    // Device input vectors
    int *d_results;

    size_t arr_size = (int)ceil((float) ((n - 1.0) / 2.0));
    printf("arr_size: %ld\n", arr_size);

    // Size, in bytes, of each vector
    size_t results_num_bytes = arr_size * sizeof(int);

    // Allocate memory for each vector on host
    h_results = (int *)malloc(results_num_bytes);

    // Allocate memory for each vector on GPU
    hipMalloc(&d_results, results_num_bytes);

    bignum i;
    // Initialize vectors on host
    for (i = 0; i < arr_size; i++)
    {
        h_results[i] = 0;
    }

    // Copy host vectors to device
    hipMemcpy(d_results, h_results, results_num_bytes, hipMemcpyHostToDevice);

    int blockSize, gridSize;

    // Number of threads in each thread block
    blockSize = 1024;

    // Number of thread blocks in grid
    gridSize = (int)ceil((float) ((n + 1.0) / 2.0 / blockSize));
    // gridSize = (int)ceil((float)n / blockSize);
    printf("gridSize: %d\n", gridSize);
    printf("gridSize * blockSize: %d\n", gridSize*blockSize);

    // Execute the kernel
    checkPrimes<<<gridSize, blockSize>>>(d_results, arr_size);

    // Copy array back to host
    hipMemcpy(h_results, d_results, results_num_bytes, hipMemcpyDeviceToHost);

    // Sum up vector c and print result divided by n, this should equal 1 without error
    bignum sum = 0;
    for (i = 0; i < arr_size; i++)
    {
        sum += h_results[i];
    }
    printf("final result: %lld\n", sum);

    // Release device memory
    hipFree(d_results);

    // Release host memory
    free(h_results);

    return 0;
}

	.text
	.file	"lab1.hip"
	.globl	_Z26__device_stub__checkPrimesPii # -- Begin function _Z26__device_stub__checkPrimesPii
	.type	_Z26__device_stub__checkPrimesPii,@function
_Z26__device_stub__checkPrimesPii:      # @_Z26__device_stub__checkPrimesPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11checkPrimesPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__checkPrimesPii, .Lfunc_end0-_Z26__device_stub__checkPrimesPii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI1_1:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_2:
	.quad	0xbff0000000000000              # double -1
.LCPI1_3:
	.quad	0x3fe0000000000000              # double 0.5
.LCPI1_4:
	.quad	0x3ff0000000000000              # double 1
.LCPI1_5:
	.quad	0x3f50000000000000              # double 9.765625E-4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$1, %edi
	jle	.LBB1_9
# %bb.1:
	movq	8(%rsi), %rdi
	callq	atoi
	cltq
	movq	%rax, %xmm0
	punpckldq	.LCPI1_0(%rip), %xmm0   # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
	subpd	.LCPI1_1(%rip), %xmm0
	movapd	%xmm0, %xmm1
	unpckhpd	%xmm0, %xmm1                    # xmm1 = xmm1[1],xmm0[1]
	addsd	%xmm0, %xmm1
	movsd	.LCPI1_2(%rip), %xmm0           # xmm0 = mem[0],zero
	movapd	%xmm1, 16(%rsp)                 # 16-byte Spill
	addsd	%xmm1, %xmm0
	mulsd	.LCPI1_3(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %ebp
	movslq	%ebp, %r14
	movl	$.L.str.1, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	printf
	leaq	(,%r14,4), %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %rbx
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	testl	%r14d, %r14d
	je	.LBB1_3
# %bb.2:                                # %.lr.ph.preheader
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movq	%r15, %rdx
	callq	memset@PLT
.LBB1_3:                                # %._crit_edge
	movq	8(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movapd	16(%rsp), %xmm0                 # 16-byte Reload
	addsd	.LCPI1_4(%rip), %xmm0
	mulsd	.LCPI1_3(%rip), %xmm0
	mulsd	.LCPI1_5(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r12d
	movl	$.L.str.2, %edi
	movl	%r12d, %esi
	xorl	%eax, %eax
	callq	printf
	movl	%r12d, %esi
	shll	$10, %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	btsq	$32, %r12
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movq	%r12, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:
	movq	8(%rsp), %rdi
	movl	%ebp, %esi
	callq	_Z26__device_stub__checkPrimesPii
.LBB1_5:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%esi, %esi
	testl	%ebp, %ebp
	je	.LBB1_8
# %bb.6:                                # %.lr.ph42.preheader
	xorl	%eax, %eax
.LBB1_7:                                # %.lr.ph42
                                        # =>This Inner Loop Header: Depth=1
	movslq	(%rbx,%rax,4), %rcx
	addq	%rcx, %rsi
	incq	%rax
	cmpq	%rax, %r14
	jne	.LBB1_7
.LBB1_8:                                # %._crit_edge43
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_9:
	.cfi_def_cfa_offset 80
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$-1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11checkPrimesPii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11checkPrimesPii,@object      # @_Z11checkPrimesPii
	.section	.rodata,"a",@progbits
	.globl	_Z11checkPrimesPii
	.p2align	3, 0x0
_Z11checkPrimesPii:
	.quad	_Z26__device_stub__checkPrimesPii
	.size	_Z11checkPrimesPii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"arr_size: %ld\n"
	.size	.L.str.1, 15

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"gridSize: %d\n"
	.size	.L.str.2, 14

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"gridSize * blockSize: %d\n"
	.size	.L.str.3, 26

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"final result: %lld\n"
	.size	.L.str.4, 20

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11checkPrimesPii"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Usage: prime upbound"
	.size	.Lstr, 21

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__checkPrimesPii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11checkPrimesPii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11checkPrimesPii      ; -- Begin function _Z11checkPrimesPii
	.globl	_Z11checkPrimesPii
	.p2align	8
	.type	_Z11checkPrimesPii,@function
_Z11checkPrimesPii:                     ; @_Z11checkPrimesPii
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x1c
	s_load_b32 s2, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	v_mov_b32_e32 v2, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.1:
	v_lshlrev_b64 v[3:4], 1, v[1:2]
	s_mov_b32 s6, 0
	s_mov_b64 s[4:5], 3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v0, v4
	v_or_b32_e32 v3, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v0, 32, v0
	v_lshlrev_b64 v[5:6], v0, v[3:4]
	v_sub_nc_u32_e32 v0, 32, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v5, 1, v5
	v_or_b32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v5, v5
	v_ldexp_f32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v5, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v6, -1, v5
	v_add_nc_u32_e32 v7, 1, v5
	v_fma_f32 v8, -v6, v5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, -v7, v5, v0
	v_cmp_ge_f32_e64 s2, 0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v5, v6, s2
	v_cmp_lt_f32_e64 s2, 0, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v7, s2
	v_mul_f32_e32 v6, 0x37800000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	v_cndmask_b32_e32 v0, v5, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v0, v0
	v_mul_f32_e32 v5, 0x2f800000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v5, v5
	v_fmac_f32_e32 v0, 0xcf800000, v5
	v_cvt_u32_f32_e32 v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_add_co_u32 v5, vcc_lo, v0, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_mov_b32_e32 v0, 1
	v_cmpx_lt_u64_e32 3, v[5:6]
	s_cbranch_execz .LBB0_7
; %bb.2:                                ; %.lr.ph.i.preheader
                                        ; implicit-def: $sgpr7
.LBB0_3:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v0, s4
	v_cvt_f32_u32_e32 v7, s5
	s_sub_u32 s2, 0, s4
	s_subb_u32 s8, 0, s5
	s_or_b32 s7, s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, 0x4f800000, v7
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, 0x2f800000, v0
	v_trunc_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, 0xcf800000, v7
	v_cvt_u32_f32_e32 v7, v7
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, s2, v7
	v_mul_hi_u32 v9, s2, v0
	v_mul_lo_u32 v10, s8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v9, v8
	v_mul_lo_u32 v9, s2, v0
	v_add_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, v9
	v_mul_lo_u32 v11, v0, v8
	v_mul_hi_u32 v12, v0, v8
	v_mul_hi_u32 v13, v7, v9
	v_mul_lo_u32 v9, v7, v9
	v_mul_hi_u32 v14, v7, v8
	v_mul_lo_u32 v8, v7, v8
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v8, s2, v0
	v_mul_lo_u32 v10, s8, v0
	v_mul_lo_u32 v9, s2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v8, v9
	v_mul_lo_u32 v9, s2, v0
	v_add_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, v9
	v_mul_lo_u32 v11, v0, v8
	v_mul_hi_u32 v12, v0, v8
	v_mul_hi_u32 v13, v7, v9
	v_mul_lo_u32 v9, v7, v9
	v_mul_hi_u32 v14, v7, v8
	v_mul_lo_u32 v8, v7, v8
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v9, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v8
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v12, v3, v0
	v_mul_lo_u32 v0, v4, v0
	v_mad_u64_u32 v[7:8], null, v3, v11, 0
	v_mad_u64_u32 v[9:10], null, v4, v11, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v12, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v7, v0
	v_add_co_ci_u32_e32 v0, vcc_lo, 0, v8, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, s5, v0
	v_mad_u64_u32 v[7:8], null, s4, v0, 0
	v_mul_lo_u32 v0, s4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v7, vcc_lo, v3, v7
	v_add3_u32 v0, v8, v0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v4, v0
	v_subrev_co_ci_u32_e64 v8, s2, s5, v8, vcc_lo
	v_sub_co_ci_u32_e32 v0, vcc_lo, v4, v0, vcc_lo
	v_sub_co_u32 v9, vcc_lo, v7, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v10, s2, 0, v8, vcc_lo
	v_cmp_le_u32_e64 s2, s4, v7
	v_subrev_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v0
	v_cndmask_b32_e64 v11, 0, -1, s2
	v_cmp_le_u32_e64 s2, s4, v9
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, 0, -1, s2
	v_cmp_le_u32_e64 s2, s5, v10
	v_cndmask_b32_e64 v13, 0, -1, s2
	v_cmp_eq_u32_e64 s2, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v13, v12, vcc_lo
	v_sub_co_u32 v13, vcc_lo, v9, s4
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v12
	v_cndmask_b32_e64 v11, v14, v11, s2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v10, v8 :: v_dual_cndmask_b32 v9, v9, v13
	v_cmp_ne_u32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v0, v8 :: v_dual_cndmask_b32 v7, v7, v9
	v_mov_b32_e32 v0, 0
	v_cmpx_ne_u64_e32 0, v[7:8]
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_add_u32 s4, s4, 2
	s_addc_u32 s5, s5, 0
	v_mov_b32_e32 v0, 1
	v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
	s_and_not1_b32 s7, s7, exec_lo
	s_and_b32 s8, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s7, s7, s8
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s7
	s_or_b32 s6, s2, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_3
; %bb.6:                                ; %Flow10
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_7:                                ; %Flow11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11checkPrimesPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11checkPrimesPii, .Lfunc_end0-_Z11checkPrimesPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1240
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11checkPrimesPii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11checkPrimesPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
